diff --git a/.gitattributes b/.gitattributes index 01abb1a1fcae39f544d35f2180b62faf1eb61bdb..9aa5ca482f9e756d8b5bbf0819d286fab089ff2a 100644 --- a/.gitattributes +++ b/.gitattributes @@ -118,3 +118,13 @@ hardware/arduino/avr/firmwares/wifishield/wifi_dnld/src/Doc/gettingstarted.pdf f hardware/arduino/avr/firmwares/wifishield/wifi_dnld/src/Doc/SPB104[[:space:]]product[[:space:]]brief.pdf filter=lfs diff=lfs merge=lfs -text hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/COMPONENTS/WIFI/HD/v2.7.0/UCR1/GCC/lib_ucr1_hd_wl_sta_intwpa_v2.7.0.a filter=lfs diff=lfs merge=lfs -text hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/COMPONENTS/WIFI/HD/v2.7.0/UCR2/GCC/lib_ucr2_hd_wl_sta_intwpa_v2.7.0.a filter=lfs diff=lfs merge=lfs -text +hardware/tools/avr/avr/bin/ar.exe filter=lfs diff=lfs merge=lfs -text +hardware/tools/avr/avr/bin/as.exe filter=lfs diff=lfs merge=lfs -text +hardware/tools/avr/avr/bin/ld.exe filter=lfs diff=lfs merge=lfs -text +hardware/tools/avr/avr/bin/libiconv-2.dll filter=lfs diff=lfs merge=lfs -text +hardware/tools/avr/avr/bin/nm.exe filter=lfs diff=lfs merge=lfs -text +hardware/tools/avr/avr/bin/objcopy.exe filter=lfs diff=lfs merge=lfs -text +hardware/tools/avr/avr/bin/objdump.exe filter=lfs diff=lfs merge=lfs -text +hardware/tools/avr/avr/bin/ranlib.exe filter=lfs diff=lfs merge=lfs -text +hardware/tools/avr/avr/bin/readelf.exe filter=lfs diff=lfs merge=lfs -text +hardware/tools/avr/avr/bin/strip.exe filter=lfs diff=lfs merge=lfs -text diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/pbuf.c b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/pbuf.c new file mode 100644 index 0000000000000000000000000000000000000000..6284b9a3a8e1c67ed1794169be6ae8c095996e65 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/pbuf.c @@ -0,0 +1,931 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/** + * @file + * Packet buffer management + * + * Packets are built from the pbuf data structure. It supports dynamic + * memory allocation for packet contents or can reference externally + * managed packet contents both in RAM and ROM. Quick allocation for + * incoming packets is provided through pools with fixed sized pbufs. + * + * A packet may span over multiple pbufs, chained as a singly linked + * list. This is called a "pbuf chain". + * + * Multiple packets may be queued, also using this singly linked list. + * This is called a "packet queue". + * + * So, a packet queue consists of one or more pbuf chains, each of + * which consist of one or more pbufs. CURRENTLY, PACKET QUEUES ARE + * NOT SUPPORTED!!! Use helper structs to queue multiple packets. + * + * The differences between a pbuf chain and a packet queue are very + * precise but subtle. + * + * The last pbuf of a packet has a ->tot_len field that equals the + * ->len field. It can be found by traversing the list. If the last + * pbuf of a packet has a ->next field other than NULL, more packets + * are on the queue. + * + * Therefore, looping through a pbuf of a single packet, has an + * loop end condition (tot_len == p->len), NOT (next == NULL). + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/stats.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include "arch/perf.h" +#if TCP_QUEUE_OOSEQ +#include "lwip/tcp.h" +#endif + +#include + +#define SIZEOF_STRUCT_PBUF LWIP_MEM_ALIGN_SIZE(sizeof(struct pbuf)) +/* Since the pool is created in memp, PBUF_POOL_BUFSIZE will be automatically + aligned there. Therefore, PBUF_POOL_BUFSIZE_ALIGNED can be used here. */ +#define PBUF_POOL_BUFSIZE_ALIGNED LWIP_MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE) + +#if !TCP_QUEUE_OOSEQ || NO_SYS +#define PBUF_POOL_IS_EMPTY() +#else /* !TCP_QUEUE_OOSEQ || NO_SYS */ +/** Define this to 0 to prevent freeing ooseq pbufs when the PBUF_POOL is empty */ +#ifndef PBUF_POOL_FREE_OOSEQ +#define PBUF_POOL_FREE_OOSEQ 1 +#endif /* PBUF_POOL_FREE_OOSEQ */ + +#if PBUF_POOL_FREE_OOSEQ +#include "lwip/tcpip.h" +#define PBUF_POOL_IS_EMPTY() pbuf_pool_is_empty() +static u8_t pbuf_free_ooseq_queued; +/** + * Attempt to reclaim some memory from queued out-of-sequence TCP segments + * if we run out of pool pbufs. It's better to give priority to new packets + * if we're running out. + * + * This must be done in the correct thread context therefore this function + * can only be used with NO_SYS=0 and through tcpip_callback. + */ +static void +pbuf_free_ooseq(void* arg) +{ + struct tcp_pcb* pcb; + SYS_ARCH_DECL_PROTECT(old_level); + LWIP_UNUSED_ARG(arg); + + SYS_ARCH_PROTECT(old_level); + pbuf_free_ooseq_queued = 0; + SYS_ARCH_UNPROTECT(old_level); + + for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) { + if (NULL != pcb->ooseq) { + /** Free the ooseq pbufs of one PCB only */ + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free_ooseq: freeing out-of-sequence pbufs\n")); + tcp_segs_free(pcb->ooseq); + pcb->ooseq = NULL; + return; + } + } +} + +/** Queue a call to pbuf_free_ooseq if not already queued. */ +static void +pbuf_pool_is_empty(void) +{ + u8_t queued; + SYS_ARCH_DECL_PROTECT(old_level); + + SYS_ARCH_PROTECT(old_level); + queued = pbuf_free_ooseq_queued; + pbuf_free_ooseq_queued = 1; + SYS_ARCH_UNPROTECT(old_level); + + if(!queued) { + /* queue a call to pbuf_free_ooseq if not already queued */ + if(tcpip_callback_with_block(pbuf_free_ooseq, NULL, 0) != ERR_OK) { + SYS_ARCH_PROTECT(old_level); + pbuf_free_ooseq_queued = 0; + SYS_ARCH_UNPROTECT(old_level); + } + } +} +#endif /* PBUF_POOL_FREE_OOSEQ */ +#endif /* !TCP_QUEUE_OOSEQ || NO_SYS */ + +/** + * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type). + * + * The actual memory allocated for the pbuf is determined by the + * layer at which the pbuf is allocated and the requested size + * (from the size parameter). + * + * @param layer flag to define header size + * @param length size of the pbuf's payload + * @param type this parameter decides how and where the pbuf + * should be allocated as follows: + * + * - PBUF_RAM: buffer memory for pbuf is allocated as one large + * chunk. This includes protocol headers as well. + * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for + * protocol headers. Additional headers must be prepended + * by allocating another pbuf and chain in to the front of + * the ROM pbuf. It is assumed that the memory used is really + * similar to ROM in that it is immutable and will not be + * changed. Memory which is dynamic should generally not + * be attached to PBUF_ROM pbufs. Use PBUF_REF instead. + * - PBUF_REF: no buffer memory is allocated for the pbuf, even for + * protocol headers. It is assumed that the pbuf is only + * being used in a single thread. If the pbuf gets queued, + * then pbuf_take should be called to copy the buffer. + * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from + * the pbuf pool that is allocated during pbuf_init(). + * + * @return the allocated pbuf. If multiple pbufs where allocated, this + * is the first pbuf of a pbuf chain. + */ +struct pbuf * +pbuf_alloc(pbuf_layer layer, u16_t length, pbuf_type type) +{ + struct pbuf *p, *q, *r; + u16_t offset; + s32_t rem_len; /* remaining length */ + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F")\n", length)); + + /* determine header offset */ + offset = 0; + switch (layer) { + case PBUF_TRANSPORT: + /* add room for transport (often TCP) layer header */ + offset += PBUF_TRANSPORT_HLEN; + /* FALLTHROUGH */ + case PBUF_IP: + /* add room for IP layer header */ + offset += PBUF_IP_HLEN; + /* FALLTHROUGH */ + case PBUF_LINK: + /* add room for link layer header */ + offset += PBUF_LINK_HLEN; + break; + case PBUF_RAW: + break; + default: + LWIP_ASSERT("pbuf_alloc: bad pbuf layer", 0); + return NULL; + } + + switch (type) { + case PBUF_POOL: + /* allocate head of pbuf chain into p */ + p = memp_malloc(MEMP_PBUF_POOL); + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc: allocated pbuf %p\n", (void *)p)); + if (p == NULL) { + PBUF_POOL_IS_EMPTY(); + return NULL; + } + p->type = type; + p->next = NULL; + + /* make the payload pointer point 'offset' bytes into pbuf data memory */ + p->payload = LWIP_MEM_ALIGN((void *)((u8_t *)p + (SIZEOF_STRUCT_PBUF + offset))); + LWIP_ASSERT("pbuf_alloc: pbuf p->payload properly aligned", + ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); + /* the total length of the pbuf chain is the requested size */ + p->tot_len = length; + /* set the length of the first pbuf in the chain */ + p->len = LWIP_MIN(length, PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)); + LWIP_ASSERT("check p->payload + p->len does not overflow pbuf", + ((u8_t*)p->payload + p->len <= + (u8_t*)p + SIZEOF_STRUCT_PBUF + PBUF_POOL_BUFSIZE_ALIGNED)); + LWIP_ASSERT("PBUF_POOL_BUFSIZE must be bigger than MEM_ALIGNMENT", + (PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)) > 0 ); + /* set reference count (needed here in case we fail) */ + p->ref = 1; + + /* now allocate the tail of the pbuf chain */ + + /* remember first pbuf for linkage in next iteration */ + r = p; + /* remaining length to be allocated */ + rem_len = length - p->len; + /* any remaining pbufs to be allocated? */ + while (rem_len > 0) { + q = memp_malloc(MEMP_PBUF_POOL); + if (q == NULL) { + PBUF_POOL_IS_EMPTY(); + /* free chain so far allocated */ + pbuf_free(p); + /* bail out unsuccesfully */ + return NULL; + } + q->type = type; + q->flags = 0; + q->next = NULL; + /* make previous pbuf point to this pbuf */ + r->next = q; + /* set total length of this pbuf and next in chain */ + LWIP_ASSERT("rem_len < max_u16_t", rem_len < 0xffff); + q->tot_len = (u16_t)rem_len; + /* this pbuf length is pool size, unless smaller sized tail */ + q->len = LWIP_MIN((u16_t)rem_len, PBUF_POOL_BUFSIZE_ALIGNED); + q->payload = (void *)((u8_t *)q + SIZEOF_STRUCT_PBUF); + LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned", + ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0); + LWIP_ASSERT("check p->payload + p->len does not overflow pbuf", + ((u8_t*)p->payload + p->len <= + (u8_t*)p + SIZEOF_STRUCT_PBUF + PBUF_POOL_BUFSIZE_ALIGNED)); + q->ref = 1; + /* calculate remaining length to be allocated */ + rem_len -= q->len; + /* remember this pbuf for linkage in next iteration */ + r = q; + } + /* end of chain */ + /*r->next = NULL;*/ + + break; + case PBUF_RAM: + /* If pbuf is to be allocated in RAM, allocate memory for it. */ + p = (struct pbuf*)mem_malloc(LWIP_MEM_ALIGN_SIZE(SIZEOF_STRUCT_PBUF + offset) + LWIP_MEM_ALIGN_SIZE(length)); + if (p == NULL) { + return NULL; + } + /* Set up internal structure of the pbuf. */ + p->payload = LWIP_MEM_ALIGN((void *)((u8_t *)p + SIZEOF_STRUCT_PBUF + offset)); + p->len = p->tot_len = length; + p->next = NULL; + p->type = type; + + LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned", + ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); + break; + /* pbuf references existing (non-volatile static constant) ROM payload? */ + case PBUF_ROM: + /* pbuf references existing (externally allocated) RAM payload? */ + case PBUF_REF: + /* only allocate memory for the pbuf structure */ + p = memp_malloc(MEMP_PBUF); + if (p == NULL) { + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("pbuf_alloc: Could not allocate MEMP_PBUF for PBUF_%s.\n", + (type == PBUF_ROM) ? "ROM" : "REF")); + return NULL; + } + /* caller must set this field properly, afterwards */ + p->payload = NULL; + p->len = p->tot_len = length; + p->next = NULL; + p->type = type; + break; + default: + LWIP_ASSERT("pbuf_alloc: erroneous type", 0); + return NULL; + } + /* set reference count */ + p->ref = 1; + /* set flags */ + p->flags = 0; + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p)); + return p; +} + + +/** + * Shrink a pbuf chain to a desired length. + * + * @param p pbuf to shrink. + * @param new_len desired new length of pbuf chain + * + * Depending on the desired length, the first few pbufs in a chain might + * be skipped and left unchanged. The new last pbuf in the chain will be + * resized, and any remaining pbufs will be freed. + * + * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted. + * @note May not be called on a packet queue. + * + * @note Despite its name, pbuf_realloc cannot grow the size of a pbuf (chain). + */ +void +pbuf_realloc(struct pbuf *p, u16_t new_len) +{ + struct pbuf *q; + u16_t rem_len; /* remaining length */ + s32_t grow; + + LWIP_ASSERT("pbuf_realloc: p != NULL", p != NULL); + LWIP_ASSERT("pbuf_realloc: sane p->type", p->type == PBUF_POOL || + p->type == PBUF_ROM || + p->type == PBUF_RAM || + p->type == PBUF_REF); + + /* desired length larger than current length? */ + if (new_len >= p->tot_len) { + /* enlarging not yet supported */ + return; + } + + /* the pbuf chain grows by (new_len - p->tot_len) bytes + * (which may be negative in case of shrinking) */ + grow = new_len - p->tot_len; + + /* first, step over any pbufs that should remain in the chain */ + rem_len = new_len; + q = p; + /* should this pbuf be kept? */ + while (rem_len > q->len) { + /* decrease remaining length by pbuf length */ + rem_len -= q->len; + /* decrease total length indicator */ + LWIP_ASSERT("grow < max_u16_t", grow < 0xffff); + q->tot_len += (u16_t)grow; + /* proceed to next pbuf in chain */ + q = q->next; + LWIP_ASSERT("pbuf_realloc: q != NULL", q != NULL); + } + /* we have now reached the new last pbuf (in q) */ + /* rem_len == desired length for pbuf q */ + + /* shrink allocated memory for PBUF_RAM */ + /* (other types merely adjust their length fields */ + if ((q->type == PBUF_RAM) && (rem_len != q->len)) { + /* reallocate and adjust the length of the pbuf that will be split */ + q = mem_realloc(q, (u8_t *)q->payload - (u8_t *)q + rem_len); + LWIP_ASSERT("mem_realloc give q == NULL", q != NULL); + } + /* adjust length fields for new last pbuf */ + q->len = rem_len; + q->tot_len = q->len; + + /* any remaining pbufs in chain? */ + if (q->next != NULL) { + /* free remaining pbufs in chain */ + pbuf_free(q->next); + } + /* q is last packet in chain */ + q->next = NULL; + +} + +/** + * Adjusts the payload pointer to hide or reveal headers in the payload. + * + * Adjusts the ->payload pointer so that space for a header + * (dis)appears in the pbuf payload. + * + * The ->payload, ->tot_len and ->len fields are adjusted. + * + * @param p pbuf to change the header size. + * @param header_size_increment Number of bytes to increment header size which + * increases the size of the pbuf. New space is on the front. + * (Using a negative value decreases the header size.) + * If hdr_size_inc is 0, this function does nothing and returns succesful. + * + * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so + * the call will fail. A check is made that the increase in header size does + * not move the payload pointer in front of the start of the buffer. + * @return non-zero on failure, zero on success. + * + */ +u8_t +pbuf_header(struct pbuf *p, s16_t header_size_increment) +{ + u16_t type; + void *payload; + u16_t increment_magnitude; + + LWIP_ASSERT("p != NULL", p != NULL); + if ((header_size_increment == 0) || (p == NULL)) + return 0; + + if (header_size_increment < 0){ + increment_magnitude = -header_size_increment; + /* Check that we aren't going to move off the end of the pbuf */ + LWIP_ERROR("increment_magnitude <= p->len", (increment_magnitude <= p->len), return 1;); + } else { + increment_magnitude = header_size_increment; +#if 0 + /* Can't assert these as some callers speculatively call + pbuf_header() to see if it's OK. Will return 1 below instead. */ + /* Check that we've got the correct type of pbuf to work with */ + LWIP_ASSERT("p->type == PBUF_RAM || p->type == PBUF_POOL", + p->type == PBUF_RAM || p->type == PBUF_POOL); + /* Check that we aren't going to move off the beginning of the pbuf */ + LWIP_ASSERT("p->payload - increment_magnitude >= p + SIZEOF_STRUCT_PBUF", + (u8_t *)p->payload - increment_magnitude >= (u8_t *)p + SIZEOF_STRUCT_PBUF); +#endif + } + + type = p->type; + /* remember current payload pointer */ + payload = p->payload; + + /* pbuf types containing payloads? */ + if (type == PBUF_RAM || type == PBUF_POOL) { + /* set new payload pointer */ + p->payload = (u8_t *)p->payload - header_size_increment; + /* boundary check fails? */ + if ((u8_t *)p->payload < (u8_t *)p + SIZEOF_STRUCT_PBUF) { + LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("pbuf_header: failed as %p < %p (not enough space for new header size)\n", + (void *)p->payload, (void *)(p + 1))); + /* restore old payload pointer */ + p->payload = payload; + /* bail out unsuccesfully */ + return 1; + } + /* pbuf types refering to external payloads? */ + } else if (type == PBUF_REF || type == PBUF_ROM) { + /* hide a header in the payload? */ + if ((header_size_increment < 0) && (increment_magnitude <= p->len)) { + /* increase payload pointer */ + p->payload = (u8_t *)p->payload - header_size_increment; + } else { + /* cannot expand payload to front (yet!) + * bail out unsuccesfully */ + return 1; + } + } + else { + /* Unknown type */ + LWIP_ASSERT("bad pbuf type", 0); + return 1; + } + /* modify pbuf length fields */ + p->len += header_size_increment; + p->tot_len += header_size_increment; + + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_header: old %p new %p (%"S16_F")\n", + (void *)payload, (void *)p->payload, header_size_increment)); + + return 0; +} + +/** + * Dereference a pbuf chain or queue and deallocate any no-longer-used + * pbufs at the head of this chain or queue. + * + * Decrements the pbuf reference count. If it reaches zero, the pbuf is + * deallocated. + * + * For a pbuf chain, this is repeated for each pbuf in the chain, + * up to the first pbuf which has a non-zero reference count after + * decrementing. So, when all reference counts are one, the whole + * chain is free'd. + * + * @param p The pbuf (chain) to be dereferenced. + * + * @return the number of pbufs that were de-allocated + * from the head of the chain. + * + * @note MUST NOT be called on a packet queue (Not verified to work yet). + * @note the reference counter of a pbuf equals the number of pointers + * that refer to the pbuf (or into the pbuf). + * + * @internal examples: + * + * Assuming existing chains a->b->c with the following reference + * counts, calling pbuf_free(a) results in: + * + * 1->2->3 becomes ...1->3 + * 3->3->3 becomes 2->3->3 + * 1->1->2 becomes ......1 + * 2->1->1 becomes 1->1->1 + * 1->1->1 becomes ....... + * + */ +u8_t +pbuf_free(struct pbuf *p) +{ + u16_t type; + struct pbuf *q; + u8_t count; + + if (p == NULL) { + LWIP_ASSERT("p != NULL", p != NULL); + /* if assertions are disabled, proceed with debug output */ + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("pbuf_free(p == NULL) was called.\n")); + return 0; + } + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free(%p)\n", (void *)p)); + + PERF_START; + + LWIP_ASSERT("pbuf_free: sane type", + p->type == PBUF_RAM || p->type == PBUF_ROM || + p->type == PBUF_REF || p->type == PBUF_POOL); + + count = 0; + /* de-allocate all consecutive pbufs from the head of the chain that + * obtain a zero reference count after decrementing*/ + while (p != NULL) { + u16_t ref; + SYS_ARCH_DECL_PROTECT(old_level); + /* Since decrementing ref cannot be guaranteed to be a single machine operation + * we must protect it. We put the new ref into a local variable to prevent + * further protection. */ + SYS_ARCH_PROTECT(old_level); + /* all pbufs in a chain are referenced at least once */ + LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0); + /* decrease reference count (number of pointers to pbuf) */ + ref = --(p->ref); + SYS_ARCH_UNPROTECT(old_level); + /* this pbuf is no longer referenced to? */ + if (ref == 0) { + /* remember next pbuf in chain for next iteration */ + q = p->next; + LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: deallocating %p\n", (void *)p)); + type = p->type; + /* is this a pbuf from the pool? */ + if (type == PBUF_POOL) { + memp_free(MEMP_PBUF_POOL, p); + /* is this a ROM or RAM referencing pbuf? */ + } else if (type == PBUF_ROM || type == PBUF_REF) { + memp_free(MEMP_PBUF, p); + /* type == PBUF_RAM */ + } else { + mem_free(p); + } + count++; + /* proceed to next pbuf */ + p = q; + /* p->ref > 0, this pbuf is still referenced to */ + /* (and so the remaining pbufs in chain as well) */ + } else { + LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, ref)); + /* stop walking through the chain */ + p = NULL; + } + } + PERF_STOP("pbuf_free"); + /* return number of de-allocated pbufs */ + return count; +} + +/** + * Count number of pbufs in a chain + * + * @param p first pbuf of chain + * @return the number of pbufs in a chain + */ + +u8_t +pbuf_clen(struct pbuf *p) +{ + u8_t len; + + len = 0; + while (p != NULL) { + ++len; + p = p->next; + } + return len; +} + +/** + * Increment the reference count of the pbuf. + * + * @param p pbuf to increase reference counter of + * + */ +void +pbuf_ref(struct pbuf *p) +{ + SYS_ARCH_DECL_PROTECT(old_level); + /* pbuf given? */ + if (p != NULL) { + SYS_ARCH_PROTECT(old_level); + ++(p->ref); + SYS_ARCH_UNPROTECT(old_level); + } +} + +/** + * Concatenate two pbufs (each may be a pbuf chain) and take over + * the caller's reference of the tail pbuf. + * + * @note The caller MAY NOT reference the tail pbuf afterwards. + * Use pbuf_chain() for that purpose. + * + * @see pbuf_chain() + */ + +void +pbuf_cat(struct pbuf *h, struct pbuf *t) +{ + struct pbuf *p; + + LWIP_ERROR("(h != NULL) && (t != NULL) (programmer violates API)", + ((h != NULL) && (t != NULL)), return;); + + /* proceed to last pbuf of chain */ + for (p = h; p->next != NULL; p = p->next) { + /* add total length of second chain to all totals of first chain */ + p->tot_len += t->tot_len; + } + /* { p is last pbuf of first h chain, p->next == NULL } */ + LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len); + LWIP_ASSERT("p->next == NULL", p->next == NULL); + /* add total length of second chain to last pbuf total of first chain */ + p->tot_len += t->tot_len; + /* chain last pbuf of head (p) with first of tail (t) */ + p->next = t; + /* p->next now references t, but the caller will drop its reference to t, + * so netto there is no change to the reference count of t. + */ +} + +/** + * Chain two pbufs (or pbuf chains) together. + * + * The caller MUST call pbuf_free(t) once it has stopped + * using it. Use pbuf_cat() instead if you no longer use t. + * + * @param h head pbuf (chain) + * @param t tail pbuf (chain) + * @note The pbufs MUST belong to the same packet. + * @note MAY NOT be called on a packet queue. + * + * The ->tot_len fields of all pbufs of the head chain are adjusted. + * The ->next field of the last pbuf of the head chain is adjusted. + * The ->ref field of the first pbuf of the tail chain is adjusted. + * + */ +void +pbuf_chain(struct pbuf *h, struct pbuf *t) +{ + pbuf_cat(h, t); + /* t is now referenced by h */ + pbuf_ref(t); + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t)); +} + +/** + * Dechains the first pbuf from its succeeding pbufs in the chain. + * + * Makes p->tot_len field equal to p->len. + * @param p pbuf to dechain + * @return remainder of the pbuf chain, or NULL if it was de-allocated. + * @note May not be called on a packet queue. + */ +struct pbuf * +pbuf_dechain(struct pbuf *p) +{ + struct pbuf *q; + u8_t tail_gone = 1; + /* tail */ + q = p->next; + /* pbuf has successor in chain? */ + if (q != NULL) { + /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */ + LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len); + /* enforce invariant if assertion is disabled */ + q->tot_len = p->tot_len - p->len; + /* decouple pbuf from remainder */ + p->next = NULL; + /* total length of pbuf p is its own length only */ + p->tot_len = p->len; + /* q is no longer referenced by p, free it */ + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_dechain: unreferencing %p\n", (void *)q)); + tail_gone = pbuf_free(q); + if (tail_gone > 0) { + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, + ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q)); + } + /* return remaining tail or NULL if deallocated */ + } + /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */ + LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len); + return ((tail_gone > 0) ? NULL : q); +} + +/** + * + * Create PBUF_RAM copies of pbufs. + * + * Used to queue packets on behalf of the lwIP stack, such as + * ARP based queueing. + * + * @note You MUST explicitly use p = pbuf_take(p); + * + * @note Only one packet is copied, no packet queue! + * + * @param p_to pbuf destination of the copy + * @param p_from pbuf source of the copy + * + * @return ERR_OK if pbuf was copied + * ERR_ARG if one of the pbufs is NULL or p_to is not big + * enough to hold p_from + */ +err_t +pbuf_copy(struct pbuf *p_to, struct pbuf *p_from) +{ + u16_t offset_to=0, offset_from=0, len; + + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy(%p, %p)\n", + (void*)p_to, (void*)p_from)); + + /* is the target big enough to hold the source? */ + LWIP_ERROR("pbuf_copy: target not big enough to hold source", ((p_to != NULL) && + (p_from != NULL) && (p_to->tot_len >= p_from->tot_len)), return ERR_ARG;); + + /* iterate through pbuf chain */ + do + { + LWIP_ASSERT("p_to != NULL", p_to != NULL); + /* copy one part of the original chain */ + if ((p_to->len - offset_to) >= (p_from->len - offset_from)) { + /* complete current p_from fits into current p_to */ + len = p_from->len - offset_from; + } else { + /* current p_from does not fit into current p_to */ + len = p_to->len - offset_to; + } + MEMCPY((u8_t*)p_to->payload + offset_to, (u8_t*)p_from->payload + offset_from, len); + offset_to += len; + offset_from += len; + LWIP_ASSERT("offset_to <= p_to->len", offset_to <= p_to->len); + if (offset_to == p_to->len) { + /* on to next p_to (if any) */ + offset_to = 0; + p_to = p_to->next; + } + LWIP_ASSERT("offset_from <= p_from->len", offset_from <= p_from->len); + if (offset_from >= p_from->len) { + /* on to next p_from (if any) */ + offset_from = 0; + p_from = p_from->next; + } + + if((p_from != NULL) && (p_from->len == p_from->tot_len)) { + /* don't copy more than one packet! */ + LWIP_ERROR("pbuf_copy() does not allow packet queues!\n", + (p_from->next == NULL), return ERR_VAL;); + } + if((p_to != NULL) && (p_to->len == p_to->tot_len)) { + /* don't copy more than one packet! */ + LWIP_ERROR("pbuf_copy() does not allow packet queues!\n", + (p_to->next == NULL), return ERR_VAL;); + } + } while (p_from); + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy: end of chain reached.\n")); + return ERR_OK; +} + +/** + * Copy (part of) the contents of a packet buffer + * to an application supplied buffer. + * + * @param buf the pbuf from which to copy data + * @param dataptr the application supplied buffer + * @param len length of data to copy (dataptr must be big enough). No more + * than buf->tot_len will be copied, irrespective of len + * @param offset offset into the packet buffer from where to begin copying len bytes + * @return the number of bytes copied, or 0 on failure + */ +u16_t +pbuf_copy_partial(struct pbuf *buf, void *dataptr, u16_t len, u16_t offset) +{ + struct pbuf *p; + u16_t left; + u16_t buf_copy_len; + u16_t copied_total = 0; + + LWIP_ERROR("pbuf_copy_partial: invalid buf", (buf != NULL), return 0;); + LWIP_ERROR("pbuf_copy_partial: invalid dataptr", (dataptr != NULL), return 0;); + + left = 0; + + if((buf == NULL) || (dataptr == NULL)) { + return 0; + } + + /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */ + for(p = buf; len != 0 && p != NULL; p = p->next) { + if ((offset != 0) && (offset >= p->len)) { + /* don't copy from this buffer -> on to the next */ + offset -= p->len; + } else { + /* copy from this buffer. maybe only partially. */ + buf_copy_len = p->len - offset; + if (buf_copy_len > len) + buf_copy_len = len; + /* copy the necessary parts of the buffer */ + MEMCPY(&((char*)dataptr)[left], &((char*)p->payload)[offset], buf_copy_len); + copied_total += buf_copy_len; + left += buf_copy_len; + len -= buf_copy_len; + offset = 0; + } + } + return copied_total; +} + +/** + * Copy application supplied data into a pbuf. + * This function can only be used to copy the equivalent of buf->tot_len data. + * + * @param buf pbuf to fill with data + * @param dataptr application supplied data buffer + * @param len length of the application supplied data buffer + * + * @return ERR_OK if successful, ERR_MEM if the pbuf is not big enough + */ +err_t +pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len) +{ + struct pbuf *p; + u16_t buf_copy_len; + u16_t total_copy_len = len; + u16_t copied_total = 0; + + LWIP_ERROR("pbuf_take: invalid buf", (buf != NULL), return 0;); + LWIP_ERROR("pbuf_take: invalid dataptr", (dataptr != NULL), return 0;); + + if ((buf == NULL) || (dataptr == NULL) || (buf->tot_len < len)) { + return ERR_ARG; + } + + /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */ + for(p = buf; total_copy_len != 0; p = p->next) { + LWIP_ASSERT("pbuf_take: invalid pbuf", p != NULL); + buf_copy_len = total_copy_len; + if (buf_copy_len > p->len) { + /* this pbuf cannot hold all remaining data */ + buf_copy_len = p->len; + } + /* copy the necessary parts of the buffer */ + MEMCPY(p->payload, &((char*)dataptr)[copied_total], buf_copy_len); + total_copy_len -= buf_copy_len; + copied_total += buf_copy_len; + } + LWIP_ASSERT("did not copy all data", total_copy_len == 0 && copied_total == len); + return ERR_OK; +} + +/** + * Creates a single pbuf out of a queue of pbufs. + * + * @remark: The source pbuf 'p' is not freed by this function because that can + * be illegal in some places! + * + * @param p the source pbuf + * @param layer pbuf_layer of the new pbuf + * + * @return a new, single pbuf (p->next is NULL) + * or the old pbuf if allocation fails + */ +struct pbuf* +pbuf_coalesce(struct pbuf *p, pbuf_layer layer) +{ + struct pbuf *q; + err_t err; + if (p->next == NULL) { + return p; + } + q = pbuf_alloc(layer, p->tot_len, PBUF_RAM); + if (q == NULL) { + /* @todo: what do we do now? */ + return p; + } + err = pbuf_copy(q, p); + LWIP_ASSERT("pbuf_copy failed", err == ERR_OK); + pbuf_free(p); + return q; +} diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/raw.c b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/raw.c new file mode 100644 index 0000000000000000000000000000000000000000..6966bbc44e839f93e51c1775f4088ef9be92b352 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/raw.c @@ -0,0 +1,355 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/** + * @file + * Implementation of raw protocol PCBs for low-level handling of + * different types of protocols besides (or overriding) those + * already available in lwIP. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/def.h" +#include "lwip/memp.h" +#include "lwip/inet.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/raw.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" +#include "arch/perf.h" + +#include + +/** The list of RAW PCBs */ +static struct raw_pcb *raw_pcbs; + +/** + * Determine if in incoming IP packet is covered by a RAW PCB + * and if so, pass it to a user-provided receive callback function. + * + * Given an incoming IP datagram (as a chain of pbufs) this function + * finds a corresponding RAW PCB and calls the corresponding receive + * callback function. + * + * @param p pbuf to be demultiplexed to a RAW PCB. + * @param inp network interface on which the datagram was received. + * @return - 1 if the packet has been eaten by a RAW PCB receive + * callback function. The caller MAY NOT not reference the + * packet any longer, and MAY NOT call pbuf_free(). + * @return - 0 if packet is not eaten (pbuf is still referenced by the + * caller). + * + */ +u8_t +raw_input(struct pbuf *p, struct netif *inp) +{ + struct raw_pcb *pcb, *prev; + struct ip_hdr *iphdr; + s16_t proto; + u8_t eaten = 0; + + LWIP_UNUSED_ARG(inp); + + iphdr = p->payload; + proto = IPH_PROTO(iphdr); + + prev = NULL; + pcb = raw_pcbs; + /* loop through all raw pcbs until the packet is eaten by one */ + /* this allows multiple pcbs to match against the packet by design */ + while ((eaten == 0) && (pcb != NULL)) { + if (pcb->protocol == proto) { +#if IP_SOF_BROADCAST_RECV + /* broadcast filter? */ + if ((pcb->so_options & SOF_BROADCAST) || !ip_addr_isbroadcast(&(iphdr->dest), inp)) +#endif /* IP_SOF_BROADCAST_RECV */ + { + /* receive callback function available? */ + if (pcb->recv != NULL) { + /* the receive callback function did not eat the packet? */ + if (pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src)) != 0) { + /* receive function ate the packet */ + p = NULL; + eaten = 1; + if (prev != NULL) { + /* move the pcb to the front of raw_pcbs so that is + found faster next time */ + prev->next = pcb->next; + pcb->next = raw_pcbs; + raw_pcbs = pcb; + } + } + } + /* no receive callback function was set for this raw PCB */ + } + /* drop the packet */ + } + prev = pcb; + pcb = pcb->next; + } + return eaten; +} + +/** + * Bind a RAW PCB. + * + * @param pcb RAW PCB to be bound with a local address ipaddr. + * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to + * bind to all local interfaces. + * + * @return lwIP error code. + * - ERR_OK. Successful. No error occured. + * - ERR_USE. The specified IP address is already bound to by + * another RAW PCB. + * + * @see raw_disconnect() + */ +err_t +raw_bind(struct raw_pcb *pcb, struct ip_addr *ipaddr) +{ + ip_addr_set(&pcb->local_ip, ipaddr); + return ERR_OK; +} + +/** + * Connect an RAW PCB. This function is required by upper layers + * of lwip. Using the raw api you could use raw_sendto() instead + * + * This will associate the RAW PCB with the remote address. + * + * @param pcb RAW PCB to be connected with remote address ipaddr and port. + * @param ipaddr remote IP address to connect with. + * + * @return lwIP error code + * + * @see raw_disconnect() and raw_sendto() + */ +err_t +raw_connect(struct raw_pcb *pcb, struct ip_addr *ipaddr) +{ + ip_addr_set(&pcb->remote_ip, ipaddr); + return ERR_OK; +} + + +/** + * Set the callback function for received packets that match the + * raw PCB's protocol and binding. + * + * The callback function MUST either + * - eat the packet by calling pbuf_free() and returning non-zero. The + * packet will not be passed to other raw PCBs or other protocol layers. + * - not free the packet, and return zero. The packet will be matched + * against further PCBs and/or forwarded to another protocol layers. + * + * @return non-zero if the packet was free()d, zero if the packet remains + * available for others. + */ +void +raw_recv(struct raw_pcb *pcb, + u8_t (* recv)(void *arg, struct raw_pcb *upcb, struct pbuf *p, + struct ip_addr *addr), + void *recv_arg) +{ + /* remember recv() callback and user data */ + pcb->recv = recv; + pcb->recv_arg = recv_arg; +} + +/** + * Send the raw IP packet to the given address. Note that actually you cannot + * modify the IP headers (this is inconsistent with the receive callback where + * you actually get the IP headers), you can only specify the IP payload here. + * It requires some more changes in lwIP. (there will be a raw_send() function + * then.) + * + * @param pcb the raw pcb which to send + * @param p the IP payload to send + * @param ipaddr the destination address of the IP packet + * + */ +err_t +raw_sendto(struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr) +{ + err_t err; + struct netif *netif; + struct ip_addr *src_ip; + struct pbuf *q; /* q will be sent down the stack */ + + LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE, ("raw_sendto\n")); + + /* not enough space to add an IP header to first pbuf in given p chain? */ + if (pbuf_header(p, IP_HLEN)) { + /* allocate header in new pbuf */ + q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM); + /* new header pbuf could not be allocated? */ + if (q == NULL) { + LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("raw_sendto: could not allocate header\n")); + return ERR_MEM; + } + /* chain header q in front of given pbuf p */ + pbuf_chain(q, p); + /* { first pbuf q points to header pbuf } */ + LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); + } else { + /* first pbuf q equals given pbuf */ + q = p; + if(pbuf_header(q, -IP_HLEN)) { + LWIP_ASSERT("Can't restore header we just removed!", 0); + return ERR_MEM; + } + } + + if ((netif = ip_route(ipaddr)) == NULL) { + LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_LEVEL_WARNING, ("raw_sendto: No route to 0x%"X32_F"\n", ipaddr->addr)); + /* free any temporary header pbuf allocated by pbuf_header() */ + if (q != p) { + pbuf_free(q); + } + return ERR_RTE; + } + +#if IP_SOF_BROADCAST + /* broadcast filter? */ + if ( ((pcb->so_options & SOF_BROADCAST) == 0) && ip_addr_isbroadcast(ipaddr, netif) ) { + LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_LEVEL_WARNING, ("raw_sendto: SOF_BROADCAST not enabled on pcb %p\n", (void *)pcb)); + /* free any temporary header pbuf allocated by pbuf_header() */ + if (q != p) { + pbuf_free(q); + } + return ERR_VAL; + } +#endif /* IP_SOF_BROADCAST */ + + if (ip_addr_isany(&pcb->local_ip)) { + /* use outgoing network interface IP address as source address */ + src_ip = &(netif->ip_addr); + } else { + /* use RAW PCB local IP address as source address */ + src_ip = &(pcb->local_ip); + } + +#if LWIP_NETIF_HWADDRHINT + netif->addr_hint = &(pcb->addr_hint); +#endif /* LWIP_NETIF_HWADDRHINT*/ + err = ip_output_if (q, src_ip, ipaddr, pcb->ttl, pcb->tos, pcb->protocol, netif); +#if LWIP_NETIF_HWADDRHINT + netif->addr_hint = NULL; +#endif /* LWIP_NETIF_HWADDRHINT*/ + + /* did we chain a header earlier? */ + if (q != p) { + /* free the header */ + pbuf_free(q); + } + return err; +} + +/** + * Send the raw IP packet to the address given by raw_connect() + * + * @param pcb the raw pcb which to send + * @param p the IP payload to send + * + */ +err_t +raw_send(struct raw_pcb *pcb, struct pbuf *p) +{ + return raw_sendto(pcb, p, &pcb->remote_ip); +} + +/** + * Remove an RAW PCB. + * + * @param pcb RAW PCB to be removed. The PCB is removed from the list of + * RAW PCB's and the data structure is freed from memory. + * + * @see raw_new() + */ +void +raw_remove(struct raw_pcb *pcb) +{ + struct raw_pcb *pcb2; + /* pcb to be removed is first in list? */ + if (raw_pcbs == pcb) { + /* make list start at 2nd pcb */ + raw_pcbs = raw_pcbs->next; + /* pcb not 1st in list */ + } else { + for(pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { + /* find pcb in raw_pcbs list */ + if (pcb2->next != NULL && pcb2->next == pcb) { + /* remove pcb from list */ + pcb2->next = pcb->next; + } + } + } + memp_free(MEMP_RAW_PCB, pcb); +} + +/** + * Create a RAW PCB. + * + * @return The RAW PCB which was created. NULL if the PCB data structure + * could not be allocated. + * + * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP) + * + * @see raw_remove() + */ +struct raw_pcb * +raw_new(u8_t proto) { + struct raw_pcb *pcb; + + LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE, ("raw_new\n")); + + pcb = memp_malloc(MEMP_RAW_PCB); + /* could allocate RAW PCB? */ + if (pcb != NULL) { + /* initialize PCB to all zeroes */ + memset(pcb, 0, sizeof(struct raw_pcb)); + pcb->protocol = proto; + pcb->ttl = RAW_TTL; + pcb->next = raw_pcbs; + raw_pcbs = pcb; + } + return pcb; +} + +#endif /* LWIP_RAW */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/stats.c b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/stats.c new file mode 100644 index 0000000000000000000000000000000000000000..4299a9480be4322f2b019b282912293a08932eaa --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/stats.c @@ -0,0 +1,151 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/** + * @file + * Statistics module + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_STATS /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/def.h" +#include "lwip/stats.h" +#include "lwip/mem.h" + +#include + +struct stats_ lwip_stats; + +#if LWIP_STATS_DISPLAY +void +stats_display_proto(struct stats_proto *proto, char *name) +{ + LWIP_PLATFORM_DIAG(("\n%s\n\t", name)); + LWIP_PLATFORM_DIAG(("xmit: %"STAT_COUNTER_F"\n\t", proto->xmit)); + LWIP_PLATFORM_DIAG(("recv: %"STAT_COUNTER_F"\n\t", proto->recv)); + LWIP_PLATFORM_DIAG(("fw: %"STAT_COUNTER_F"\n\t", proto->fw)); + LWIP_PLATFORM_DIAG(("drop: %"STAT_COUNTER_F"\n\t", proto->drop)); + LWIP_PLATFORM_DIAG(("chkerr: %"STAT_COUNTER_F"\n\t", proto->chkerr)); + LWIP_PLATFORM_DIAG(("lenerr: %"STAT_COUNTER_F"\n\t", proto->lenerr)); + LWIP_PLATFORM_DIAG(("memerr: %"STAT_COUNTER_F"\n\t", proto->memerr)); + LWIP_PLATFORM_DIAG(("rterr: %"STAT_COUNTER_F"\n\t", proto->rterr)); + LWIP_PLATFORM_DIAG(("proterr: %"STAT_COUNTER_F"\n\t", proto->proterr)); + LWIP_PLATFORM_DIAG(("opterr: %"STAT_COUNTER_F"\n\t", proto->opterr)); + LWIP_PLATFORM_DIAG(("err: %"STAT_COUNTER_F"\n\t", proto->err)); + LWIP_PLATFORM_DIAG(("cachehit: %"STAT_COUNTER_F"\n", proto->cachehit)); +} + +#if IGMP_STATS +void +stats_display_igmp(struct stats_igmp *igmp) +{ + LWIP_PLATFORM_DIAG(("\nIGMP\n\t")); + LWIP_PLATFORM_DIAG(("lenerr: %"STAT_COUNTER_F"\n\t", igmp->lenerr)); + LWIP_PLATFORM_DIAG(("chkerr: %"STAT_COUNTER_F"\n\t", igmp->chkerr)); + LWIP_PLATFORM_DIAG(("v1_rxed: %"STAT_COUNTER_F"\n\t", igmp->v1_rxed)); + LWIP_PLATFORM_DIAG(("join_sent: %"STAT_COUNTER_F"\n\t", igmp->join_sent)); + LWIP_PLATFORM_DIAG(("leave_sent: %"STAT_COUNTER_F"\n\t", igmp->leave_sent)); + LWIP_PLATFORM_DIAG(("unicast_query: %"STAT_COUNTER_F"\n\t", igmp->unicast_query)); + LWIP_PLATFORM_DIAG(("report_sent: %"STAT_COUNTER_F"\n\t", igmp->report_sent)); + LWIP_PLATFORM_DIAG(("report_rxed: %"STAT_COUNTER_F"\n\t", igmp->report_rxed)); + LWIP_PLATFORM_DIAG(("group_query_rxed: %"STAT_COUNTER_F"\n", igmp->group_query_rxed)); +} +#endif /* IGMP_STATS */ + +#if MEM_STATS || MEMP_STATS +void +stats_display_mem(struct stats_mem *mem, char *name) +{ + LWIP_PLATFORM_DIAG(("\nMEM %s\n\t", name)); + LWIP_PLATFORM_DIAG(("avail: %"U32_F"\n\t", (u32_t)mem->avail)); + LWIP_PLATFORM_DIAG(("used: %"U32_F"\n\t", (u32_t)mem->used)); + LWIP_PLATFORM_DIAG(("max: %"U32_F"\n\t", (u32_t)mem->max)); + LWIP_PLATFORM_DIAG(("err: %"U32_F"\n", (u32_t)mem->err)); +} + +#if MEMP_STATS +void +stats_display_memp(struct stats_mem *mem, int index) +{ + char * memp_names[] = { +#define LWIP_MEMPOOL(name,num,size,desc) desc, +#include "lwip/memp_std.h" + }; + if(index < MEMP_MAX) { + stats_display_mem(mem, memp_names[index]); + } +} +#endif /* MEMP_STATS */ +#endif /* MEM_STATS || MEMP_STATS */ + +#if SYS_STATS +void +stats_display_sys(struct stats_sys *sys) +{ + LWIP_PLATFORM_DIAG(("\nSYS\n\t")); + LWIP_PLATFORM_DIAG(("sem.used: %"U32_F"\n\t", (u32_t)sys->sem.used)); + LWIP_PLATFORM_DIAG(("sem.max: %"U32_F"\n\t", (u32_t)sys->sem.max)); + LWIP_PLATFORM_DIAG(("sem.err: %"U32_F"\n\t", (u32_t)sys->sem.err)); + LWIP_PLATFORM_DIAG(("mbox.used: %"U32_F"\n\t", (u32_t)sys->mbox.used)); + LWIP_PLATFORM_DIAG(("mbox.max: %"U32_F"\n\t", (u32_t)sys->mbox.max)); + LWIP_PLATFORM_DIAG(("mbox.err: %"U32_F"\n\t", (u32_t)sys->mbox.err)); +} +#endif /* SYS_STATS */ + +void +stats_display(void) +{ + s16_t i; + + LINK_STATS_DISPLAY(); + ETHARP_STATS_DISPLAY(); + IPFRAG_STATS_DISPLAY(); + IP_STATS_DISPLAY(); + IGMP_STATS_DISPLAY(); + ICMP_STATS_DISPLAY(); + UDP_STATS_DISPLAY(); + TCP_STATS_DISPLAY(); + MEM_STATS_DISPLAY(); + for (i = 0; i < MEMP_MAX; i++) { + MEMP_STATS_DISPLAY(i); + } + SYS_STATS_DISPLAY(); +} +#endif /* LWIP_STATS_DISPLAY */ + +#endif /* LWIP_STATS */ + diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/tcp.c b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/tcp.c new file mode 100644 index 0000000000000000000000000000000000000000..c588d21dfec4232d071b0117dcc52d6eb19fae9d --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/tcp.c @@ -0,0 +1,1463 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/** + * @file + * Transmission Control Protocol for IP + * + * This file contains common functions for the TCP implementation, such as functinos + * for manipulating the data structures and the TCP timer functions. TCP functions + * related to input and output is found in tcp_in.c and tcp_out.c respectively. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/snmp.h" +#include "lwip/tcp.h" +#include "lwip/debug.h" +#include "lwip/stats.h" + +#include + +const char *tcp_state_str[] = { + "CLOSED", + "LISTEN", + "SYN_SENT", + "SYN_RCVD", + "ESTABLISHED", + "FIN_WAIT_1", + "FIN_WAIT_2", + "CLOSE_WAIT", + "CLOSING", + "LAST_ACK", + "TIME_WAIT" +}; + +/* Incremented every coarse grained timer shot (typically every 500 ms). */ +u32_t tcp_ticks; +const u8_t tcp_backoff[13] = + { 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7}; + /* Times per slowtmr hits */ +const u8_t tcp_persist_backoff[7] = { 3, 6, 12, 24, 48, 96, 120 }; + +/* The TCP PCB lists. */ + +/** List of all TCP PCBs bound but not yet (connected || listening) */ +struct tcp_pcb *tcp_bound_pcbs; +/** List of all TCP PCBs in LISTEN state */ +union tcp_listen_pcbs_t tcp_listen_pcbs; +/** List of all TCP PCBs that are in a state in which + * they accept or send data. */ +struct tcp_pcb *tcp_active_pcbs; +/** List of all TCP PCBs in TIME-WAIT state */ +struct tcp_pcb *tcp_tw_pcbs; + +struct tcp_pcb *tcp_tmp_pcb; + +static u8_t tcp_timer; +static u16_t tcp_new_port(void); + +/** + * Called periodically to dispatch TCP timers. + * + */ +void +tcp_tmr(void) +{ + /* Call tcp_fasttmr() every 250 ms */ + tcp_fasttmr(); + + if (++tcp_timer & 1) { + /* Call tcp_tmr() every 500 ms, i.e., every other timer + tcp_tmr() is called. */ + tcp_slowtmr(); + } +} + +/** + * Closes the connection held by the PCB. + * + * Listening pcbs are freed and may not be referenced any more. + * Connection pcbs are freed if not yet connected and may not be referenced + * any more. If a connection is established (at least SYN received or in + * a closing state), the connection is closed, and put in a closing state. + * The pcb is then automatically freed in tcp_slowtmr(). It is therefore + * unsafe to reference it. + * + * @param pcb the tcp_pcb to close + * @return ERR_OK if connection has been closed + * another err_t if closing failed and pcb is not freed + */ +err_t +tcp_close(struct tcp_pcb *pcb) +{ + err_t err; + +#if TCP_DEBUG + LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in ")); + tcp_debug_print_state(pcb->state); +#endif /* TCP_DEBUG */ + + switch (pcb->state) { + case CLOSED: + /* Closing a pcb in the CLOSED state might seem erroneous, + * however, it is in this state once allocated and as yet unused + * and the user needs some way to free it should the need arise. + * Calling tcp_close() with a pcb that has already been closed, (i.e. twice) + * or for a pcb that has been used and then entered the CLOSED state + * is erroneous, but this should never happen as the pcb has in those cases + * been freed, and so any remaining handles are bogus. */ + err = ERR_OK; + TCP_RMV(&tcp_bound_pcbs, pcb); + memp_free(MEMP_TCP_PCB, pcb); + pcb = NULL; + break; + case LISTEN: + err = ERR_OK; + tcp_pcb_remove((struct tcp_pcb **)&tcp_listen_pcbs.pcbs, pcb); + memp_free(MEMP_TCP_PCB_LISTEN, pcb); + pcb = NULL; + break; + case SYN_SENT: + err = ERR_OK; + tcp_pcb_remove(&tcp_active_pcbs, pcb); + memp_free(MEMP_TCP_PCB, pcb); + pcb = NULL; + snmp_inc_tcpattemptfails(); + break; + case SYN_RCVD: + err = tcp_send_ctrl(pcb, TCP_FIN); + if (err == ERR_OK) { + snmp_inc_tcpattemptfails(); + pcb->state = FIN_WAIT_1; + } + break; + case ESTABLISHED: + err = tcp_send_ctrl(pcb, TCP_FIN); + if (err == ERR_OK) { + snmp_inc_tcpestabresets(); + pcb->state = FIN_WAIT_1; + } + break; + case CLOSE_WAIT: + err = tcp_send_ctrl(pcb, TCP_FIN); + if (err == ERR_OK) { + snmp_inc_tcpestabresets(); + pcb->state = LAST_ACK; + } + break; + default: + /* Has already been closed, do nothing. */ + err = ERR_OK; + pcb = NULL; + break; + } + + if (pcb != NULL && err == ERR_OK) { + /* To ensure all data has been sent when tcp_close returns, we have + to make sure tcp_output doesn't fail. + Since we don't really have to ensure all data has been sent when tcp_close + returns (unsent data is sent from tcp timer functions, also), we don't care + for the return value of tcp_output for now. */ + /* @todo: When implementing SO_LINGER, this must be changed somehow: + If SOF_LINGER is set, the data should be sent when tcp_close returns. */ + tcp_output(pcb); + } + return err; +} + +/** + * Abandons a connection and optionally sends a RST to the remote + * host. Deletes the local protocol control block. This is done when + * a connection is killed because of shortage of memory. + * + * @param pcb the tcp_pcb to abort + * @param reset boolean to indicate whether a reset should be sent + */ +void +tcp_abandon(struct tcp_pcb *pcb, int reset) +{ + u32_t seqno, ackno; + u16_t remote_port, local_port; + struct ip_addr remote_ip, local_ip; +#if LWIP_CALLBACK_API + void (* errf)(void *arg, err_t err); +#endif /* LWIP_CALLBACK_API */ + void *errf_arg; + + + /* Figure out on which TCP PCB list we are, and remove us. If we + are in an active state, call the receive function associated with + the PCB with a NULL argument, and send an RST to the remote end. */ + if (pcb->state == TIME_WAIT) { + tcp_pcb_remove(&tcp_tw_pcbs, pcb); + memp_free(MEMP_TCP_PCB, pcb); + } else { + seqno = pcb->snd_nxt; + ackno = pcb->rcv_nxt; + ip_addr_set(&local_ip, &(pcb->local_ip)); + ip_addr_set(&remote_ip, &(pcb->remote_ip)); + local_port = pcb->local_port; + remote_port = pcb->remote_port; +#if LWIP_CALLBACK_API + errf = pcb->errf; +#endif /* LWIP_CALLBACK_API */ + errf_arg = pcb->callback_arg; + tcp_pcb_remove(&tcp_active_pcbs, pcb); + if (pcb->unacked != NULL) { + tcp_segs_free(pcb->unacked); + } + if (pcb->unsent != NULL) { + tcp_segs_free(pcb->unsent); + } +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL) { + tcp_segs_free(pcb->ooseq); + } +#endif /* TCP_QUEUE_OOSEQ */ + memp_free(MEMP_TCP_PCB, pcb); + TCP_EVENT_ERR(errf, errf_arg, ERR_ABRT); + if (reset) { + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abandon: sending RST\n")); + tcp_rst(seqno, ackno, &local_ip, &remote_ip, local_port, remote_port); + } + } +} + +/** + * Binds the connection to a local portnumber and IP address. If the + * IP address is not given (i.e., ipaddr == NULL), the IP address of + * the outgoing network interface is used instead. + * + * @param pcb the tcp_pcb to bind (no check is done whether this pcb is + * already bound!) + * @param ipaddr the local ip address to bind to (use IP_ADDR_ANY to bind + * to any local address + * @param port the local port to bind to + * @return ERR_USE if the port is already in use + * ERR_OK if bound + */ +err_t +tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port) +{ + struct tcp_pcb *cpcb; + + LWIP_ERROR("tcp_bind: can only bind in state CLOSED", pcb->state == CLOSED, return ERR_ISCONN); + + if (port == 0) { + port = tcp_new_port(); + } + /* Check if the address already is in use. */ + /* Check the listen pcbs. */ + for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; + cpcb != NULL; cpcb = cpcb->next) { + if (cpcb->local_port == port) { + if (ip_addr_isany(&(cpcb->local_ip)) || + ip_addr_isany(ipaddr) || + ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { + return ERR_USE; + } + } + } + /* Check the connected pcbs. */ + for(cpcb = tcp_active_pcbs; + cpcb != NULL; cpcb = cpcb->next) { + if (cpcb->local_port == port) { + if (ip_addr_isany(&(cpcb->local_ip)) || + ip_addr_isany(ipaddr) || + ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { + return ERR_USE; + } + } + } + /* Check the bound, not yet connected pcbs. */ + for(cpcb = tcp_bound_pcbs; cpcb != NULL; cpcb = cpcb->next) { + if (cpcb->local_port == port) { + if (ip_addr_isany(&(cpcb->local_ip)) || + ip_addr_isany(ipaddr) || + ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { + return ERR_USE; + } + } + } + /* @todo: until SO_REUSEADDR is implemented (see task #6995 on savannah), + * we have to check the pcbs in TIME-WAIT state, also: */ + for(cpcb = tcp_tw_pcbs; cpcb != NULL; cpcb = cpcb->next) { + if (cpcb->local_port == port) { + if (ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { + return ERR_USE; + } + } + } + + if (!ip_addr_isany(ipaddr)) { + pcb->local_ip = *ipaddr; + } + pcb->local_port = port; + TCP_REG(&tcp_bound_pcbs, pcb); + LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %"U16_F"\n", port)); + return ERR_OK; +} +#if LWIP_CALLBACK_API +/** + * Default accept callback if no accept callback is specified by the user. + */ +static err_t +tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err) +{ + LWIP_UNUSED_ARG(arg); + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(err); + + return ERR_ABRT; +} +#endif /* LWIP_CALLBACK_API */ + +/** + * Set the state of the connection to be LISTEN, which means that it + * is able to accept incoming connections. The protocol control block + * is reallocated in order to consume less memory. Setting the + * connection to LISTEN is an irreversible process. + * + * @param pcb the original tcp_pcb + * @param backlog the incoming connections queue limit + * @return tcp_pcb used for listening, consumes less memory. + * + * @note The original tcp_pcb is freed. This function therefore has to be + * called like this: + * tpcb = tcp_listen(tpcb); + */ +struct tcp_pcb * +tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog) +{ + struct tcp_pcb_listen *lpcb; + + LWIP_UNUSED_ARG(backlog); + LWIP_ERROR("tcp_listen: pcb already connected", pcb->state == CLOSED, return NULL); + + /* already listening? */ + if (pcb->state == LISTEN) { + return pcb; + } + lpcb = memp_malloc(MEMP_TCP_PCB_LISTEN); + if (lpcb == NULL) { + return NULL; + } + lpcb->callback_arg = pcb->callback_arg; + lpcb->local_port = pcb->local_port; + lpcb->state = LISTEN; + lpcb->so_options = pcb->so_options; + lpcb->so_options |= SOF_ACCEPTCONN; + lpcb->ttl = pcb->ttl; + lpcb->tos = pcb->tos; + ip_addr_set(&lpcb->local_ip, &pcb->local_ip); + TCP_RMV(&tcp_bound_pcbs, pcb); + memp_free(MEMP_TCP_PCB, pcb); +#if LWIP_CALLBACK_API + lpcb->accept = tcp_accept_null; +#endif /* LWIP_CALLBACK_API */ +#if TCP_LISTEN_BACKLOG + lpcb->accepts_pending = 0; + lpcb->backlog = (backlog ? backlog : 1); +#endif /* TCP_LISTEN_BACKLOG */ + TCP_REG(&tcp_listen_pcbs.listen_pcbs, lpcb); + return (struct tcp_pcb *)lpcb; +} + +/** + * Update the state that tracks the available window space to advertise. + * + * Returns how much extra window would be advertised if we sent an + * update now. + */ +u32_t tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb) +{ + u32_t new_right_edge = pcb->rcv_nxt + pcb->rcv_wnd; + + if (TCP_SEQ_GEQ(new_right_edge, pcb->rcv_ann_right_edge + LWIP_MIN((TCP_WND / 2), pcb->mss))) { + /* we can advertise more window */ + pcb->rcv_ann_wnd = pcb->rcv_wnd; + return new_right_edge - pcb->rcv_ann_right_edge; + } else { + if (TCP_SEQ_GT(pcb->rcv_nxt, pcb->rcv_ann_right_edge)) { + /* Can happen due to other end sending out of advertised window, + * but within actual available (but not yet advertised) window */ + pcb->rcv_ann_wnd = 0; + } else { + /* keep the right edge of window constant */ + pcb->rcv_ann_wnd = pcb->rcv_ann_right_edge - pcb->rcv_nxt; + } + return 0; + } +} + +/** + * This function should be called by the application when it has + * processed the data. The purpose is to advertise a larger window + * when the data has been processed. + * + * @param pcb the tcp_pcb for which data is read + * @param len the amount of bytes that have been read by the application + */ +void +tcp_recved(struct tcp_pcb *pcb, u16_t len) +{ + int wnd_inflation; + + LWIP_ASSERT("tcp_recved: len would wrap rcv_wnd\n", + len <= 0xffff - pcb->rcv_wnd ); + + pcb->rcv_wnd += len; + if (pcb->rcv_wnd > TCP_WND) + pcb->rcv_wnd = TCP_WND; + + wnd_inflation = tcp_update_rcv_ann_wnd(pcb); + + /* If the change in the right edge of window is significant (default + * watermark is TCP_WND/2), then send an explicit update now. + * Otherwise wait for a packet to be sent in the normal course of + * events (or more window to be available later) */ + if (wnd_inflation >= TCP_WND_UPDATE_THRESHOLD) + tcp_ack_now(pcb); + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: recveived %"U16_F" bytes, wnd %"U16_F" (%"U16_F").\n", + len, pcb->rcv_wnd, TCP_WND - pcb->rcv_wnd)); +} + +/** + * A nastly hack featuring 'goto' statements that allocates a + * new TCP local port. + * + * @return a new (free) local TCP port number + */ +static u16_t +tcp_new_port(void) +{ + struct tcp_pcb *pcb; +#ifndef TCP_LOCAL_PORT_RANGE_START +#define TCP_LOCAL_PORT_RANGE_START 4096 +#define TCP_LOCAL_PORT_RANGE_END 0x7fff +#endif + static u16_t port = TCP_LOCAL_PORT_RANGE_START; + + again: + if (++port > TCP_LOCAL_PORT_RANGE_END) { + port = TCP_LOCAL_PORT_RANGE_START; + } + + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + if (pcb->local_port == port) { + goto again; + } + } + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + if (pcb->local_port == port) { + goto again; + } + } + for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) { + if (pcb->local_port == port) { + goto again; + } + } + return port; +} + +/** + * Connects to another host. The function given as the "connected" + * argument will be called when the connection has been established. + * + * @param pcb the tcp_pcb used to establish the connection + * @param ipaddr the remote ip address to connect to + * @param port the remote tcp port to connect to + * @param connected callback function to call when connected (or on error) + * @return ERR_VAL if invalid arguments are given + * ERR_OK if connect request has been sent + * other err_t values if connect request couldn't be sent + */ +err_t +tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port, + err_t (* connected)(void *arg, struct tcp_pcb *tpcb, err_t err)) +{ + err_t ret; + u32_t iss; + + LWIP_ERROR("tcp_connect: can only connected from state CLOSED", pcb->state == CLOSED, return ERR_ISCONN); + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port)); + if (ipaddr != NULL) { + pcb->remote_ip = *ipaddr; + } else { + return ERR_VAL; + } + pcb->remote_port = port; + if (pcb->local_port == 0) { + pcb->local_port = tcp_new_port(); + } + iss = tcp_next_iss(); + pcb->rcv_nxt = 0; + pcb->snd_nxt = iss; + pcb->lastack = iss - 1; + pcb->snd_lbb = iss - 1; + pcb->rcv_wnd = TCP_WND; + pcb->rcv_ann_wnd = TCP_WND; + pcb->rcv_ann_right_edge = pcb->rcv_nxt; + pcb->snd_wnd = TCP_WND; + /* As initial send MSS, we use TCP_MSS but limit it to 536. + The send MSS is updated when an MSS option is received. */ + pcb->mss = (TCP_MSS > 536) ? 536 : TCP_MSS; +#if TCP_CALCULATE_EFF_SEND_MSS + pcb->mss = tcp_eff_send_mss(pcb->mss, ipaddr); +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + pcb->cwnd = 1; + pcb->ssthresh = pcb->mss * 10; + pcb->state = SYN_SENT; +#if LWIP_CALLBACK_API + pcb->connected = connected; +#endif /* LWIP_CALLBACK_API */ + TCP_RMV(&tcp_bound_pcbs, pcb); + TCP_REG(&tcp_active_pcbs, pcb); + + snmp_inc_tcpactiveopens(); + + ret = tcp_enqueue(pcb, NULL, 0, TCP_SYN, 0, TF_SEG_OPTS_MSS +#if LWIP_TCP_TIMESTAMPS + | TF_SEG_OPTS_TS +#endif + ); + if (ret == ERR_OK) { + tcp_output(pcb); + } + return ret; +} + +/** + * Called every 500 ms and implements the retransmission timer and the timer that + * removes PCBs that have been in TIME-WAIT for enough time. It also increments + * various timers such as the inactivity timer in each PCB. + * + * Automatically called from tcp_tmr(). + */ +void +tcp_slowtmr(void) +{ + struct tcp_pcb *pcb, *pcb2, *prev; + u16_t eff_wnd; + u8_t pcb_remove; /* flag if a PCB should be removed */ + u8_t pcb_reset; /* flag if a RST should be sent when removing */ + err_t err; + + err = ERR_OK; + + ++tcp_ticks; + + /* Steps through all of the active PCBs. */ + prev = NULL; + pcb = tcp_active_pcbs; + if (pcb == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n")); + } + while (pcb != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n")); + LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED); + LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN); + LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT); + + pcb_remove = 0; + pcb_reset = 0; + + if (pcb->state == SYN_SENT && pcb->nrtx == TCP_SYNMAXRTX) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n")); + } + else if (pcb->nrtx == TCP_MAXRTX) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n")); + } else { + if (pcb->persist_backoff > 0) { + /* If snd_wnd is zero, use persist timer to send 1 byte probes + * instead of using the standard retransmission mechanism. */ + pcb->persist_cnt++; + if (pcb->persist_cnt >= tcp_persist_backoff[pcb->persist_backoff-1]) { + pcb->persist_cnt = 0; + if (pcb->persist_backoff < sizeof(tcp_persist_backoff)) { + pcb->persist_backoff++; + } + tcp_zero_window_probe(pcb); + } + } else { + /* Increase the retransmission timer if it is running */ + if(pcb->rtime >= 0) + ++pcb->rtime; + + if (pcb->unacked != NULL && pcb->rtime >= pcb->rto) { + /* Time for a retransmission. */ + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %"S16_F + " pcb->rto %"S16_F"\n", + pcb->rtime, pcb->rto)); + + /* Double retransmission time-out unless we are trying to + * connect to somebody (i.e., we are in SYN_SENT). */ + if (pcb->state != SYN_SENT) { + pcb->rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[pcb->nrtx]; + } + + /* Reset the retransmission timer. */ + pcb->rtime = 0; + + /* Reduce congestion window and ssthresh. */ + eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd); + pcb->ssthresh = eff_wnd >> 1; + if (pcb->ssthresh < pcb->mss) { + pcb->ssthresh = pcb->mss * 2; + } + pcb->cwnd = pcb->mss; + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"U16_F + " ssthresh %"U16_F"\n", + pcb->cwnd, pcb->ssthresh)); + + /* The following needs to be called AFTER cwnd is set to one + mss - STJ */ + tcp_rexmit_rto(pcb); + } + } + } + /* Check if this PCB has stayed too long in FIN-WAIT-2 */ + if (pcb->state == FIN_WAIT_2) { + if ((u32_t)(tcp_ticks - pcb->tmr) > + TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n")); + } + } + + /* Check if KEEPALIVE should be sent */ + if((pcb->so_options & SOF_KEEPALIVE) && + ((pcb->state == ESTABLISHED) || + (pcb->state == CLOSE_WAIT))) { +#if LWIP_TCP_KEEPALIVE + if((u32_t)(tcp_ticks - pcb->tmr) > + (pcb->keep_idle + (pcb->keep_cnt*pcb->keep_intvl)) + / TCP_SLOW_INTERVAL) +#else + if((u32_t)(tcp_ticks - pcb->tmr) > + (pcb->keep_idle + TCP_MAXIDLE) / TCP_SLOW_INTERVAL) +#endif /* LWIP_TCP_KEEPALIVE */ + { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to %"U16_F".%"U16_F".%"U16_F".%"U16_F".\n", + ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), + ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip))); + + ++pcb_remove; + ++pcb_reset; + } +#if LWIP_TCP_KEEPALIVE + else if((u32_t)(tcp_ticks - pcb->tmr) > + (pcb->keep_idle + pcb->keep_cnt_sent * pcb->keep_intvl) + / TCP_SLOW_INTERVAL) +#else + else if((u32_t)(tcp_ticks - pcb->tmr) > + (pcb->keep_idle + pcb->keep_cnt_sent * TCP_KEEPINTVL_DEFAULT) + / TCP_SLOW_INTERVAL) +#endif /* LWIP_TCP_KEEPALIVE */ + { + tcp_keepalive(pcb); + pcb->keep_cnt_sent++; + } + } + + /* If this PCB has queued out of sequence data, but has been + inactive for too long, will drop the data (it will eventually + be retransmitted). */ +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL && + (u32_t)tcp_ticks - pcb->tmr >= pcb->rto * TCP_OOSEQ_TIMEOUT) { + tcp_segs_free(pcb->ooseq); + pcb->ooseq = NULL; + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n")); + } +#endif /* TCP_QUEUE_OOSEQ */ + + /* Check if this PCB has stayed too long in SYN-RCVD */ + if (pcb->state == SYN_RCVD) { + if ((u32_t)(tcp_ticks - pcb->tmr) > + TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n")); + } + } + + /* Check if this PCB has stayed too long in LAST-ACK */ + if (pcb->state == LAST_ACK) { + if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n")); + } + } + + /* If the PCB should be removed, do it. */ + if (pcb_remove) { + tcp_pcb_purge(pcb); + /* Remove PCB from tcp_active_pcbs list. */ + if (prev != NULL) { + LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs); + prev->next = pcb->next; + } else { + /* This PCB was the first. */ + LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb); + tcp_active_pcbs = pcb->next; + } + + TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_ABRT); + if (pcb_reset) { + tcp_rst(pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip, + pcb->local_port, pcb->remote_port); + } + + pcb2 = pcb->next; + memp_free(MEMP_TCP_PCB, pcb); + pcb = pcb2; + } else { + + /* We check if we should poll the connection. */ + ++pcb->polltmr; + if (pcb->polltmr >= pcb->pollinterval) { + pcb->polltmr = 0; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n")); + TCP_EVENT_POLL(pcb, err); + if (err == ERR_OK) { + tcp_output(pcb); + } + } + + prev = pcb; + pcb = pcb->next; + } + } + + + /* Steps through all of the TIME-WAIT PCBs. */ + prev = NULL; + pcb = tcp_tw_pcbs; + while (pcb != NULL) { + LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); + pcb_remove = 0; + + /* Check if this PCB has stayed long enough in TIME-WAIT */ + if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { + ++pcb_remove; + } + + + + /* If the PCB should be removed, do it. */ + if (pcb_remove) { + tcp_pcb_purge(pcb); + /* Remove PCB from tcp_tw_pcbs list. */ + if (prev != NULL) { + LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs); + prev->next = pcb->next; + } else { + /* This PCB was the first. */ + LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb); + tcp_tw_pcbs = pcb->next; + } + pcb2 = pcb->next; + memp_free(MEMP_TCP_PCB, pcb); + pcb = pcb2; + } else { + prev = pcb; + pcb = pcb->next; + } + } +} + +/** + * Is called every TCP_FAST_INTERVAL (250 ms) and process data previously + * "refused" by upper layer (application) and sends delayed ACKs. + * + * Automatically called from tcp_tmr(). + */ +void +tcp_fasttmr(void) +{ + struct tcp_pcb *pcb; + + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + /* If there is data which was previously "refused" by upper layer */ + if (pcb->refused_data != NULL) { + /* Notify again application with data previously received. */ + err_t err; + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_fasttmr: notify kept packet\n")); + TCP_EVENT_RECV(pcb, pcb->refused_data, ERR_OK, err); + if (err == ERR_OK) { + pcb->refused_data = NULL; + } + } + + /* send delayed ACKs */ + if (pcb->flags & TF_ACK_DELAY) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n")); + tcp_ack_now(pcb); + pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); + } + } +} + +/** + * Deallocates a list of TCP segments (tcp_seg structures). + * + * @param seg tcp_seg list of TCP segments to free + * @return the number of pbufs that were deallocated + */ +u8_t +tcp_segs_free(struct tcp_seg *seg) +{ + u8_t count = 0; + struct tcp_seg *next; + while (seg != NULL) { + next = seg->next; + count += tcp_seg_free(seg); + seg = next; + } + return count; +} + +/** + * Frees a TCP segment (tcp_seg structure). + * + * @param seg single tcp_seg to free + * @return the number of pbufs that were deallocated + */ +u8_t +tcp_seg_free(struct tcp_seg *seg) +{ + u8_t count = 0; + + if (seg != NULL) { + if (seg->p != NULL) { + count = pbuf_free(seg->p); +#if TCP_DEBUG + seg->p = NULL; +#endif /* TCP_DEBUG */ + } + memp_free(MEMP_TCP_SEG, seg); + } + return count; +} + +/** + * Sets the priority of a connection. + * + * @param pcb the tcp_pcb to manipulate + * @param prio new priority + */ +void +tcp_setprio(struct tcp_pcb *pcb, u8_t prio) +{ + pcb->prio = prio; +} +#if TCP_QUEUE_OOSEQ + +/** + * Returns a copy of the given TCP segment. + * The pbuf and data are not copied, only the pointers + * + * @param seg the old tcp_seg + * @return a copy of seg + */ +struct tcp_seg * +tcp_seg_copy(struct tcp_seg *seg) +{ + struct tcp_seg *cseg; + + cseg = memp_malloc(MEMP_TCP_SEG); + if (cseg == NULL) { + return NULL; + } + SMEMCPY((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg)); + pbuf_ref(cseg->p); + return cseg; +} +#endif + +#if LWIP_CALLBACK_API +/** + * Default receive callback that is called if the user didn't register + * a recv callback for the pcb. + */ +err_t +tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) +{ + LWIP_UNUSED_ARG(arg); + if (p != NULL) { + tcp_recved(pcb, p->tot_len); + pbuf_free(p); + } else if (err == ERR_OK) { + return tcp_close(pcb); + } + return ERR_OK; +} +#endif /* LWIP_CALLBACK_API */ + +/** + * Kills the oldest active connection that has lower priority than prio. + * + * @param prio minimum priority + */ +static void +tcp_kill_prio(u8_t prio) +{ + struct tcp_pcb *pcb, *inactive; + u32_t inactivity; + u8_t mprio; + + + mprio = TCP_PRIO_MAX; + + /* We kill the oldest active connection that has lower priority than prio. */ + inactivity = 0; + inactive = NULL; + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + if (pcb->prio <= prio && + pcb->prio <= mprio && + (u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { + inactivity = tcp_ticks - pcb->tmr; + inactive = pcb; + mprio = pcb->prio; + } + } + if (inactive != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n", + (void *)inactive, inactivity)); + tcp_abort(inactive); + } +} + +/** + * Kills the oldest connection that is in TIME_WAIT state. + * Called from tcp_alloc() if no more connections are available. + */ +static void +tcp_kill_timewait(void) +{ + struct tcp_pcb *pcb, *inactive; + u32_t inactivity; + + inactivity = 0; + inactive = NULL; + /* Go through the list of TIME_WAIT pcbs and get the oldest pcb. */ + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { + inactivity = tcp_ticks - pcb->tmr; + inactive = pcb; + } + } + if (inactive != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n", + (void *)inactive, inactivity)); + tcp_abort(inactive); + } +} + +/** + * Allocate a new tcp_pcb structure. + * + * @param prio priority for the new pcb + * @return a new tcp_pcb that initially is in state CLOSED + */ +struct tcp_pcb * +tcp_alloc(u8_t prio) +{ + struct tcp_pcb *pcb; + u32_t iss; + + pcb = memp_malloc(MEMP_TCP_PCB); + if (pcb == NULL) { + /* Try killing oldest connection in TIME-WAIT. */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n")); + tcp_kill_timewait(); + /* Try to allocate a tcp_pcb again. */ + pcb = memp_malloc(MEMP_TCP_PCB); + if (pcb == NULL) { + /* Try killing active connections with lower priority than the new one. */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing connection with prio lower than %d\n", prio)); + tcp_kill_prio(prio); + /* Try to allocate a tcp_pcb again. */ + pcb = memp_malloc(MEMP_TCP_PCB); + if (pcb != NULL) { + /* adjust err stats: memp_malloc failed twice before */ + MEMP_STATS_DEC(err, MEMP_TCP_PCB); + } + } + if (pcb != NULL) { + /* adjust err stats: timewait PCB was freed above */ + MEMP_STATS_DEC(err, MEMP_TCP_PCB); + } + } + if (pcb != NULL) { + memset(pcb, 0, sizeof(struct tcp_pcb)); + pcb->prio = TCP_PRIO_NORMAL; + pcb->snd_buf = TCP_SND_BUF; + pcb->snd_queuelen = 0; + pcb->rcv_wnd = TCP_WND; + pcb->rcv_ann_wnd = TCP_WND; + pcb->tos = 0; + pcb->ttl = TCP_TTL; + /* As initial send MSS, we use TCP_MSS but limit it to 536. + The send MSS is updated when an MSS option is received. */ + pcb->mss = (TCP_MSS > 536) ? 536 : TCP_MSS; + pcb->rto = 3000 / TCP_SLOW_INTERVAL; + pcb->sa = 0; + pcb->sv = 3000 / TCP_SLOW_INTERVAL; + pcb->rtime = -1; + pcb->cwnd = 1; + iss = tcp_next_iss(); + pcb->snd_wl2 = iss; + pcb->snd_nxt = iss; + pcb->lastack = iss; + pcb->snd_lbb = iss; + pcb->tmr = tcp_ticks; + + pcb->polltmr = 0; + +#if LWIP_CALLBACK_API + pcb->recv = tcp_recv_null; +#endif /* LWIP_CALLBACK_API */ + + /* Init KEEPALIVE timer */ + pcb->keep_idle = TCP_KEEPIDLE_DEFAULT; + +#if LWIP_TCP_KEEPALIVE + pcb->keep_intvl = TCP_KEEPINTVL_DEFAULT; + pcb->keep_cnt = TCP_KEEPCNT_DEFAULT; +#endif /* LWIP_TCP_KEEPALIVE */ + + pcb->keep_cnt_sent = 0; + } + return pcb; +} + +/** + * Creates a new TCP protocol control block but doesn't place it on + * any of the TCP PCB lists. + * The pcb is not put on any list until binding using tcp_bind(). + * + * @internal: Maybe there should be a idle TCP PCB list where these + * PCBs are put on. Port reservation using tcp_bind() is implemented but + * allocated pcbs that are not bound can't be killed automatically if wanting + * to allocate a pcb with higher prio (@see tcp_kill_prio()) + * + * @return a new tcp_pcb that initially is in state CLOSED + */ +struct tcp_pcb * +tcp_new(void) +{ + return tcp_alloc(TCP_PRIO_NORMAL); +} + +/** + * Used to specify the argument that should be passed callback + * functions. + * + * @param pcb tcp_pcb to set the callback argument + * @param arg void pointer argument to pass to callback functions + */ +void +tcp_arg(struct tcp_pcb *pcb, void *arg) +{ + pcb->callback_arg = arg; +} +#if LWIP_CALLBACK_API + +/** + * Used to specify the function that should be called when a TCP + * connection receives data. + * + * @param pcb tcp_pcb to set the recv callback + * @param recv callback function to call for this pcb when data is received + */ +void +tcp_recv(struct tcp_pcb *pcb, + err_t (* recv)(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err)) +{ + pcb->recv = recv; +} + +/** + * Used to specify the function that should be called when TCP data + * has been successfully delivered to the remote host. + * + * @param pcb tcp_pcb to set the sent callback + * @param sent callback function to call for this pcb when data is successfully sent + */ +void +tcp_sent(struct tcp_pcb *pcb, + err_t (* sent)(void *arg, struct tcp_pcb *tpcb, u16_t len)) +{ + pcb->sent = sent; +} + +/** + * Used to specify the function that should be called when a fatal error + * has occured on the connection. + * + * @param pcb tcp_pcb to set the err callback + * @param errf callback function to call for this pcb when a fatal error + * has occured on the connection + */ +void +tcp_err(struct tcp_pcb *pcb, + void (* errf)(void *arg, err_t err)) +{ + pcb->errf = errf; +} + +/** + * Used for specifying the function that should be called when a + * LISTENing connection has been connected to another host. + * + * @param pcb tcp_pcb to set the accept callback + * @param accept callback function to call for this pcb when LISTENing + * connection has been connected to another host + */ +void +tcp_accept(struct tcp_pcb *pcb, + err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err)) +{ + pcb->accept = accept; +} +#endif /* LWIP_CALLBACK_API */ + + +/** + * Used to specify the function that should be called periodically + * from TCP. The interval is specified in terms of the TCP coarse + * timer interval, which is called twice a second. + * + */ +void +tcp_poll(struct tcp_pcb *pcb, + err_t (* poll)(void *arg, struct tcp_pcb *tpcb), u8_t interval) +{ +#if LWIP_CALLBACK_API + pcb->poll = poll; +#endif /* LWIP_CALLBACK_API */ + pcb->pollinterval = interval; +} + +/** + * Purges a TCP PCB. Removes any buffered data and frees the buffer memory + * (pcb->ooseq, pcb->unsent and pcb->unacked are freed). + * + * @param pcb tcp_pcb to purge. The pcb itself is not deallocated! + */ +void +tcp_pcb_purge(struct tcp_pcb *pcb) +{ + if (pcb->state != CLOSED && + pcb->state != TIME_WAIT && + pcb->state != LISTEN) { + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n")); + +#if TCP_LISTEN_BACKLOG + if (pcb->state == SYN_RCVD) { + /* Need to find the corresponding listen_pcb and decrease its accepts_pending */ + struct tcp_pcb_listen *lpcb; + LWIP_ASSERT("tcp_pcb_purge: pcb->state == SYN_RCVD but tcp_listen_pcbs is NULL", + tcp_listen_pcbs.listen_pcbs != NULL); + for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + if ((lpcb->local_port == pcb->local_port) && + (ip_addr_isany(&lpcb->local_ip) || + ip_addr_cmp(&pcb->local_ip, &lpcb->local_ip))) { + /* port and address of the listen pcb match the timed-out pcb */ + LWIP_ASSERT("tcp_pcb_purge: listen pcb does not have accepts pending", + lpcb->accepts_pending > 0); + lpcb->accepts_pending--; + break; + } + } + } +#endif /* TCP_LISTEN_BACKLOG */ + + + if (pcb->refused_data != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->refused_data\n")); + pbuf_free(pcb->refused_data); + pcb->refused_data = NULL; + } + if (pcb->unsent != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n")); + } + if (pcb->unacked != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n")); + } +#if TCP_QUEUE_OOSEQ /* LW */ + if (pcb->ooseq != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n")); + } + + /* Stop the retransmission timer as it will expect data on unacked + queue if it fires */ + pcb->rtime = -1; + + tcp_segs_free(pcb->ooseq); + pcb->ooseq = NULL; +#endif /* TCP_QUEUE_OOSEQ */ + tcp_segs_free(pcb->unsent); + tcp_segs_free(pcb->unacked); + pcb->unacked = pcb->unsent = NULL; + } +} + +/** + * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first. + * + * @param pcblist PCB list to purge. + * @param pcb tcp_pcb to purge. The pcb itself is NOT deallocated! + */ +void +tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb) +{ + TCP_RMV(pcblist, pcb); + + tcp_pcb_purge(pcb); + + /* if there is an outstanding delayed ACKs, send it */ + if (pcb->state != TIME_WAIT && + pcb->state != LISTEN && + pcb->flags & TF_ACK_DELAY) { + pcb->flags |= TF_ACK_NOW; + tcp_output(pcb); + } + + if (pcb->state != LISTEN) { + LWIP_ASSERT("unsent segments leaking", pcb->unsent == NULL); + LWIP_ASSERT("unacked segments leaking", pcb->unacked == NULL); +#if TCP_QUEUE_OOSEQ + LWIP_ASSERT("ooseq segments leaking", pcb->ooseq == NULL); +#endif /* TCP_QUEUE_OOSEQ */ + } + + pcb->state = CLOSED; + + LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane()); +} + +/** + * Calculates a new initial sequence number for new connections. + * + * @return u32_t pseudo random sequence number + */ +u32_t +tcp_next_iss(void) +{ + static u32_t iss = 6510; + + iss += tcp_ticks; /* XXX */ + return iss; +} + +#if TCP_CALCULATE_EFF_SEND_MSS +/** + * Calcluates the effective send mss that can be used for a specific IP address + * by using ip_route to determin the netif used to send to the address and + * calculating the minimum of TCP_MSS and that netif's mtu (if set). + */ +u16_t +tcp_eff_send_mss(u16_t sendmss, struct ip_addr *addr) +{ + u16_t mss_s; + struct netif *outif; + + outif = ip_route(addr); + if ((outif != NULL) && (outif->mtu != 0)) { + mss_s = outif->mtu - IP_HLEN - TCP_HLEN; + /* RFC 1122, chap 4.2.2.6: + * Eff.snd.MSS = min(SendMSS+20, MMS_S) - TCPhdrsize - IPoptionsize + * We correct for TCP options in tcp_enqueue(), and don't support + * IP options + */ + sendmss = LWIP_MIN(sendmss, mss_s); + } + return sendmss; +} +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + +const char* +tcp_debug_state_str(enum tcp_state s) +{ + return tcp_state_str[s]; +} + +#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG +/** + * Print a tcp header for debugging purposes. + * + * @param tcphdr pointer to a struct tcp_hdr + */ +void +tcp_debug_print(struct tcp_hdr *tcphdr) +{ + LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n")); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", + ntohs(tcphdr->src), ntohs(tcphdr->dest))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (seq no)\n", + ntohl(tcphdr->seqno))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (ack no)\n", + ntohl(tcphdr->ackno))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %2"U16_F" | |%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"| %5"U16_F" | (hdrlen, flags (", + TCPH_HDRLEN(tcphdr), + TCPH_FLAGS(tcphdr) >> 5 & 1, + TCPH_FLAGS(tcphdr) >> 4 & 1, + TCPH_FLAGS(tcphdr) >> 3 & 1, + TCPH_FLAGS(tcphdr) >> 2 & 1, + TCPH_FLAGS(tcphdr) >> 1 & 1, + TCPH_FLAGS(tcphdr) & 1, + ntohs(tcphdr->wnd))); + tcp_debug_print_flags(TCPH_FLAGS(tcphdr)); + LWIP_DEBUGF(TCP_DEBUG, ("), win)\n")); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| 0x%04"X16_F" | %5"U16_F" | (chksum, urgp)\n", + ntohs(tcphdr->chksum), ntohs(tcphdr->urgp))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); +} + +/** + * Print a tcp state for debugging purposes. + * + * @param s enum tcp_state to print + */ +void +tcp_debug_print_state(enum tcp_state s) +{ + LWIP_DEBUGF(TCP_DEBUG, ("State: %s\n", tcp_state_str[s])); +} + +/** + * Print tcp flags for debugging purposes. + * + * @param flags tcp flags, all active flags are printed + */ +void +tcp_debug_print_flags(u8_t flags) +{ + if (flags & TCP_FIN) { + LWIP_DEBUGF(TCP_DEBUG, ("FIN ")); + } + if (flags & TCP_SYN) { + LWIP_DEBUGF(TCP_DEBUG, ("SYN ")); + } + if (flags & TCP_RST) { + LWIP_DEBUGF(TCP_DEBUG, ("RST ")); + } + if (flags & TCP_PSH) { + LWIP_DEBUGF(TCP_DEBUG, ("PSH ")); + } + if (flags & TCP_ACK) { + LWIP_DEBUGF(TCP_DEBUG, ("ACK ")); + } + if (flags & TCP_URG) { + LWIP_DEBUGF(TCP_DEBUG, ("URG ")); + } + if (flags & TCP_ECE) { + LWIP_DEBUGF(TCP_DEBUG, ("ECE ")); + } + if (flags & TCP_CWR) { + LWIP_DEBUGF(TCP_DEBUG, ("CWR ")); + } + LWIP_DEBUGF(TCP_DEBUG, ("\n")); +} + +/** + * Print all tcp_pcbs in every list for debugging purposes. + */ +void +tcp_debug_print_pcbs(void) +{ + struct tcp_pcb *pcb; + LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n")); + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_DEBUGF(TCP_DEBUG, ("[%p]Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", + pcb, pcb->local_port, pcb->remote_port, + pcb->snd_nxt, pcb->rcv_nxt)); + tcp_debug_print_state(pcb->state); + } + LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n")); + for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_DEBUGF(TCP_DEBUG, ("[%p]Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", + pcb, pcb->local_port, pcb->remote_port, + pcb->snd_nxt, pcb->rcv_nxt)); + tcp_debug_print_state(pcb->state); + } + LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n")); + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_DEBUGF(TCP_DEBUG, ("[%p]Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", + pcb, pcb->local_port, pcb->remote_port, + pcb->snd_nxt, pcb->rcv_nxt)); + tcp_debug_print_state(pcb->state); + } +} + +/** + * Check state consistency of the tcp_pcb lists. + */ +s16_t +tcp_pcbs_sane(void) +{ + struct tcp_pcb *pcb; + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED); + LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN); + LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); + } + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); + } + return 1; +} +#endif /* TCP_DEBUG */ + +#endif /* LWIP_TCP */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/tcp_in.c b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/tcp_in.c new file mode 100644 index 0000000000000000000000000000000000000000..3930b40f6d6684b3be2827a7cd594d3c0236443e --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/tcp_in.c @@ -0,0 +1,1508 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/** + * @file + * Transmission Control Protocol, incoming traffic + * + * The input processing functions of the TCP layer. + * + * These functions are generally called in the order (ip_input() ->) + * tcp_input() -> * tcp_process() -> tcp_receive() (-> application). + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/tcp.h" +#include "lwip/def.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/inet.h" +#include "lwip/inet_chksum.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" +#include "arch/perf.h" + +/* These variables are global to all functions involved in the input + processing of TCP segments. They are set by the tcp_input() + function. */ +static struct tcp_seg inseg; +static struct tcp_hdr *tcphdr; +static struct ip_hdr *iphdr; +static u32_t seqno, ackno; +static u8_t flags; +static u16_t tcplen; + +static u8_t recv_flags; +static struct pbuf *recv_data; + +struct tcp_pcb *tcp_input_pcb; + +/* Forward declarations. */ +static err_t tcp_process(struct tcp_pcb *pcb); +static void tcp_receive(struct tcp_pcb *pcb); +static void tcp_parseopt(struct tcp_pcb *pcb); + +static err_t tcp_listen_input(struct tcp_pcb_listen *pcb); +static err_t tcp_timewait_input(struct tcp_pcb *pcb); + +/** + * The initial input processing of TCP. It verifies the TCP header, demultiplexes + * the segment between the PCBs and passes it on to tcp_process(), which implements + * the TCP finite state machine. This function is called by the IP layer (in + * ip_input()). + * + * @param p received TCP segment to process (p->payload pointing to the IP header) + * @param inp network interface on which this segment was received + */ +void +tcp_input(struct pbuf *p, struct netif *inp) +{ + struct tcp_pcb *pcb, *prev; + struct tcp_pcb_listen *lpcb; + u8_t hdrlen; + err_t err; + + PERF_START; + + TCP_STATS_INC(tcp.recv); + snmp_inc_tcpinsegs(); + + iphdr = p->payload; + tcphdr = (struct tcp_hdr *)((u8_t *)p->payload + IPH_HL(iphdr) * 4); + +#if TCP_INPUT_DEBUG + tcp_debug_print(tcphdr); +#endif + + /* remove header from payload */ + if (pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))) || (p->tot_len < sizeof(struct tcp_hdr))) { + /* drop short packets */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%"U16_F" bytes) discarded\n", p->tot_len)); + TCP_STATS_INC(tcp.lenerr); + TCP_STATS_INC(tcp.drop); + snmp_inc_tcpinerrs(); + pbuf_free(p); + return; + } + + /* Don't even process incoming broadcasts/multicasts. */ + if (ip_addr_isbroadcast(&(iphdr->dest), inp) || + ip_addr_ismulticast(&(iphdr->dest))) { + TCP_STATS_INC(tcp.proterr); + TCP_STATS_INC(tcp.drop); + snmp_inc_tcpinerrs(); + pbuf_free(p); + return; + } + +#if CHECKSUM_CHECK_TCP + /* Verify TCP checksum. */ + if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), + (struct ip_addr *)&(iphdr->dest), + IP_PROTO_TCP, p->tot_len) != 0) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04"X16_F"\n", + inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), (struct ip_addr *)&(iphdr->dest), + IP_PROTO_TCP, p->tot_len))); +#if TCP_DEBUG + tcp_debug_print(tcphdr); +#endif /* TCP_DEBUG */ + TCP_STATS_INC(tcp.chkerr); + TCP_STATS_INC(tcp.drop); + snmp_inc_tcpinerrs(); + pbuf_free(p); + return; + } +#endif + + /* Move the payload pointer in the pbuf so that it points to the + TCP data instead of the TCP header. */ + hdrlen = TCPH_HDRLEN(tcphdr); + if(pbuf_header(p, -(hdrlen * 4))){ + /* drop short packets */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet\n")); + TCP_STATS_INC(tcp.lenerr); + TCP_STATS_INC(tcp.drop); + snmp_inc_tcpinerrs(); + pbuf_free(p); + return; + } + + /* Convert fields in TCP header to host byte order. */ + tcphdr->src = ntohs(tcphdr->src); + tcphdr->dest = ntohs(tcphdr->dest); + seqno = tcphdr->seqno = ntohl(tcphdr->seqno); + ackno = tcphdr->ackno = ntohl(tcphdr->ackno); + tcphdr->wnd = ntohs(tcphdr->wnd); + + flags = TCPH_FLAGS(tcphdr); + tcplen = p->tot_len + ((flags & (TCP_FIN | TCP_SYN)) ? 1 : 0); + + /* Demultiplex an incoming segment. First, we check if it is destined + for an active connection. */ + prev = NULL; + + + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED); + LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); + LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN); + if (pcb->remote_port == tcphdr->src && + pcb->local_port == tcphdr->dest && + ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) && + ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) { + + /* Move this PCB to the front of the list so that subsequent + lookups will be faster (we exploit locality in TCP segment + arrivals). */ + LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb); + if (prev != NULL) { + prev->next = pcb->next; + pcb->next = tcp_active_pcbs; + tcp_active_pcbs = pcb; + } + LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb); + break; + } + prev = pcb; + } + + if (pcb == NULL) { + /* If it did not go to an active connection, we check the connections + in the TIME-WAIT state. */ + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); + if (pcb->remote_port == tcphdr->src && + pcb->local_port == tcphdr->dest && + ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) && + ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) { + /* We don't really care enough to move this PCB to the front + of the list since we are not very likely to receive that + many segments for connections in TIME-WAIT. */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n")); + tcp_timewait_input(pcb); + pbuf_free(p); + return; + } + } + + /* Finally, if we still did not get a match, we check all PCBs that + are LISTENing for incoming connections. */ + prev = NULL; + for(lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + if ((ip_addr_isany(&(lpcb->local_ip)) || + ip_addr_cmp(&(lpcb->local_ip), &(iphdr->dest))) && + lpcb->local_port == tcphdr->dest) { + /* Move this PCB to the front of the list so that subsequent + lookups will be faster (we exploit locality in TCP segment + arrivals). */ + if (prev != NULL) { + ((struct tcp_pcb_listen *)prev)->next = lpcb->next; + /* our successor is the remainder of the listening list */ + lpcb->next = tcp_listen_pcbs.listen_pcbs; + /* put this listening pcb at the head of the listening list */ + tcp_listen_pcbs.listen_pcbs = lpcb; + } + + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n")); + tcp_listen_input(lpcb); + pbuf_free(p); + return; + } + prev = (struct tcp_pcb *)lpcb; + } + } + +#if TCP_INPUT_DEBUG + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags ")); + tcp_debug_print_flags(TCPH_FLAGS(tcphdr)); + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n")); +#endif /* TCP_INPUT_DEBUG */ + + + if (pcb != NULL) { + /* The incoming segment belongs to a connection. */ +#if TCP_INPUT_DEBUG +#if TCP_DEBUG + tcp_debug_print_state(pcb->state); +#endif /* TCP_DEBUG */ +#endif /* TCP_INPUT_DEBUG */ + + /* Set up a tcp_seg structure. */ + inseg.next = NULL; + inseg.len = p->tot_len; + inseg.dataptr = p->payload; + inseg.p = p; + inseg.tcphdr = tcphdr; + + recv_data = NULL; + recv_flags = 0; + + /* If there is data which was previously "refused" by upper layer */ + if (pcb->refused_data != NULL) { + /* Notify again application with data previously received. */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: notify kept packet\n")); + TCP_EVENT_RECV(pcb, pcb->refused_data, ERR_OK, err); + if (err == ERR_OK) { + pcb->refused_data = NULL; + } else { + /* drop incoming packets, because pcb is "full" */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: drop incoming packets, because pcb is \"full\"\n")); + TCP_STATS_INC(tcp.drop); + snmp_inc_tcpinerrs(); + pbuf_free(p); + return; + } + } + tcp_input_pcb = pcb; + err = tcp_process(pcb); + /* A return value of ERR_ABRT means that tcp_abort() was called + and that the pcb has been freed. If so, we don't do anything. */ + if (err != ERR_ABRT) { + if (recv_flags & TF_RESET) { + /* TF_RESET means that the connection was reset by the other + end. We then call the error callback to inform the + application that the connection is dead before we + deallocate the PCB. */ + TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_RST); + tcp_pcb_remove(&tcp_active_pcbs, pcb); + memp_free(MEMP_TCP_PCB, pcb); + } else if (recv_flags & TF_CLOSED) { + /* The connection has been closed and we will deallocate the + PCB. */ + tcp_pcb_remove(&tcp_active_pcbs, pcb); + memp_free(MEMP_TCP_PCB, pcb); + } else { + err = ERR_OK; + /* If the application has registered a "sent" function to be + called when new send buffer space is available, we call it + now. */ + if (pcb->acked > 0) { + TCP_EVENT_SENT(pcb, pcb->acked, err); + } + + if (recv_data != NULL) { + if(flags & TCP_PSH) { + recv_data->flags |= PBUF_FLAG_PUSH; + } + + /* Notify application that data has been received. */ + TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err); + + /* If the upper layer can't receive this data, store it */ + if (err != ERR_OK) { + pcb->refused_data = recv_data; + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: keep incoming packet, because pcb is \"full\"\n")); + } + } + + /* If a FIN segment was received, we call the callback + function with a NULL buffer to indicate EOF. */ + if (recv_flags & TF_GOT_FIN) { + TCP_EVENT_RECV(pcb, NULL, ERR_OK, err); + } + + tcp_input_pcb = NULL; + /* Try to send something out. */ + tcp_output(pcb); +#if TCP_INPUT_DEBUG +#if TCP_DEBUG + tcp_debug_print_state(pcb->state); +#endif /* TCP_DEBUG */ +#endif /* TCP_INPUT_DEBUG */ + } + } + tcp_input_pcb = NULL; + + + /* give up our reference to inseg.p */ + if (inseg.p != NULL) + { + pbuf_free(inseg.p); + inseg.p = NULL; + } + } else { + + /* If no matching PCB was found, send a TCP RST (reset) to the + sender. */ + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n")); + if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) { + TCP_STATS_INC(tcp.proterr); + TCP_STATS_INC(tcp.drop); + tcp_rst(ackno, seqno + tcplen, + &(iphdr->dest), &(iphdr->src), + tcphdr->dest, tcphdr->src); + } + pbuf_free(p); + } + + LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane()); + PERF_STOP("tcp_input"); +} + +/** + * Called by tcp_input() when a segment arrives for a listening + * connection (from tcp_input()). + * + * @param pcb the tcp_pcb_listen for which a segment arrived + * @return ERR_OK if the segment was processed + * another err_t on error + * + * @note the return value is not (yet?) used in tcp_input() + * @note the segment which arrived is saved in global variables, therefore only the pcb + * involved is passed as a parameter to this function + */ +static err_t +tcp_listen_input(struct tcp_pcb_listen *pcb) +{ + struct tcp_pcb *npcb; + err_t rc; + + /* In the LISTEN state, we check for incoming SYN segments, + creates a new PCB, and responds with a SYN|ACK. */ + if (flags & TCP_ACK) { + /* For incoming segments with the ACK flag set, respond with a + RST. */ + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n")); + tcp_rst(ackno + 1, seqno + tcplen, + &(iphdr->dest), &(iphdr->src), + tcphdr->dest, tcphdr->src); + } else if (flags & TCP_SYN) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %"U16_F" -> %"U16_F".\n", tcphdr->src, tcphdr->dest)); +#if TCP_LISTEN_BACKLOG + if (pcb->accepts_pending >= pcb->backlog) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: listen backlog exceeded for port %"U16_F"\n", tcphdr->dest)); + return ERR_ABRT; + } +#endif /* TCP_LISTEN_BACKLOG */ + npcb = tcp_alloc(pcb->prio); + /* If a new PCB could not be created (probably due to lack of memory), + we don't do anything, but rely on the sender will retransmit the + SYN at a time when we have more memory available. */ + if (npcb == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n")); + TCP_STATS_INC(tcp.memerr); + return ERR_MEM; + } +#if TCP_LISTEN_BACKLOG + pcb->accepts_pending++; +#endif /* TCP_LISTEN_BACKLOG */ + /* Set up the new PCB. */ + ip_addr_set(&(npcb->local_ip), &(iphdr->dest)); + npcb->local_port = pcb->local_port; + ip_addr_set(&(npcb->remote_ip), &(iphdr->src)); + npcb->remote_port = tcphdr->src; + npcb->state = SYN_RCVD; + npcb->rcv_nxt = seqno + 1; + npcb->rcv_ann_right_edge = npcb->rcv_nxt; + npcb->snd_wnd = tcphdr->wnd; + npcb->ssthresh = npcb->snd_wnd; + npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */ + npcb->callback_arg = pcb->callback_arg; +#if LWIP_CALLBACK_API + npcb->accept = pcb->accept; +#endif /* LWIP_CALLBACK_API */ + /* inherit socket options */ + npcb->so_options = pcb->so_options & (SOF_DEBUG|SOF_DONTROUTE|SOF_KEEPALIVE|SOF_OOBINLINE|SOF_LINGER); + /* Register the new PCB so that we can begin receiving segments + for it. */ + TCP_REG(&tcp_active_pcbs, npcb); + + /* Parse any options in the SYN. */ + tcp_parseopt(npcb); +#if TCP_CALCULATE_EFF_SEND_MSS + npcb->mss = tcp_eff_send_mss(npcb->mss, &(npcb->remote_ip)); +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + + snmp_inc_tcppassiveopens(); + + /* Send a SYN|ACK together with the MSS option. */ + rc = tcp_enqueue(npcb, NULL, 0, TCP_SYN | TCP_ACK, 0, TF_SEG_OPTS_MSS +#if LWIP_TCP_TIMESTAMPS + /* and maybe include the TIMESTAMP option */ + | (npcb->flags & TF_TIMESTAMP ? TF_SEG_OPTS_TS : 0) +#endif + ); + if (rc != ERR_OK) { + tcp_abandon(npcb, 0); + return rc; + } + return tcp_output(npcb); + } + return ERR_OK; +} + +/** + * Called by tcp_input() when a segment arrives for a connection in + * TIME_WAIT. + * + * @param pcb the tcp_pcb for which a segment arrived + * + * @note the segment which arrived is saved in global variables, therefore only the pcb + * involved is passed as a parameter to this function + */ +static err_t +tcp_timewait_input(struct tcp_pcb *pcb) +{ + /* RFC 1337: in TIME_WAIT, ignore RST and ACK FINs + any 'acceptable' segments */ + /* RFC 793 3.9 Event Processing - Segment Arrives: + * - first check sequence number - we skip that one in TIME_WAIT (always + * acceptable since we only send ACKs) + * - second check the RST bit (... return) */ + if (flags & TCP_RST) { + return ERR_OK; + } + /* - fourth, check the SYN bit, */ + if (flags & TCP_SYN) { + /* If an incoming segment is not acceptable, an acknowledgment + should be sent in reply */ + if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt+pcb->rcv_wnd)) { + /* If the SYN is in the window it is an error, send a reset */ + tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src), + tcphdr->dest, tcphdr->src); + return ERR_OK; + } + } else if (flags & TCP_FIN) { + /* - eighth, check the FIN bit: Remain in the TIME-WAIT state. + Restart the 2 MSL time-wait timeout.*/ + pcb->tmr = tcp_ticks; + } + + if ((tcplen > 0)) { + /* Acknowledge data, FIN or out-of-window SYN */ + pcb->flags |= TF_ACK_NOW; + return tcp_output(pcb); + } + return ERR_OK; +} + +/** + * Implements the TCP state machine. Called by tcp_input. In some + * states tcp_receive() is called to receive data. The tcp_seg + * argument will be freed by the caller (tcp_input()) unless the + * recv_data pointer in the pcb is set. + * + * @param pcb the tcp_pcb for which a segment arrived + * + * @note the segment which arrived is saved in global variables, therefore only the pcb + * involved is passed as a parameter to this function + */ +static err_t +tcp_process(struct tcp_pcb *pcb) +{ + struct tcp_seg *rseg; + u8_t acceptable = 0; + err_t err; + + err = ERR_OK; + + /* Process incoming RST segments. */ + if (flags & TCP_RST) { + /* First, determine if the reset is acceptable. */ + if (pcb->state == SYN_SENT) { + if (ackno == pcb->snd_nxt) { + acceptable = 1; + } + } else { + if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, + pcb->rcv_nxt+pcb->rcv_wnd)) { + acceptable = 1; + } + } + + if (acceptable) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n")); + LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED); + recv_flags |= TF_RESET; + pcb->flags &= ~TF_ACK_DELAY; + return ERR_RST; + } else { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", + seqno, pcb->rcv_nxt)); + LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", + seqno, pcb->rcv_nxt)); + return ERR_OK; + } + } + + if ((flags & TCP_SYN) && (pcb->state != SYN_SENT && pcb->state != SYN_RCVD)) { + /* Cope with new connection attempt after remote end crashed */ + tcp_ack_now(pcb); + return ERR_OK; + } + + /* Update the PCB (in)activity timer. */ + pcb->tmr = tcp_ticks; + pcb->keep_cnt_sent = 0; + + tcp_parseopt(pcb); + + /* Do different things depending on the TCP state. */ + switch (pcb->state) { + case SYN_SENT: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno, + pcb->snd_nxt, ntohl(pcb->unacked->tcphdr->seqno))); + /* received SYN ACK with expected sequence number? */ + if ((flags & TCP_ACK) && (flags & TCP_SYN) + && ackno == ntohl(pcb->unacked->tcphdr->seqno) + 1) { + pcb->snd_buf++; + pcb->rcv_nxt = seqno + 1; + pcb->rcv_ann_right_edge = pcb->rcv_nxt; + pcb->lastack = ackno; + pcb->snd_wnd = tcphdr->wnd; + pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */ + pcb->state = ESTABLISHED; + +#if TCP_CALCULATE_EFF_SEND_MSS + pcb->mss = tcp_eff_send_mss(pcb->mss, &(pcb->remote_ip)); +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + + /* Set ssthresh again after changing pcb->mss (already set in tcp_connect + * but for the default value of pcb->mss) */ + pcb->ssthresh = pcb->mss * 10; + + pcb->cwnd = ((pcb->cwnd == 1) ? (pcb->mss * 2) : pcb->mss); + LWIP_ASSERT("pcb->snd_queuelen > 0", (pcb->snd_queuelen > 0)); + --pcb->snd_queuelen; + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"U16_F"\n", (u16_t)pcb->snd_queuelen)); + rseg = pcb->unacked; + pcb->unacked = rseg->next; + + /* If there's nothing left to acknowledge, stop the retransmit + timer, otherwise reset it to start again */ + if(pcb->unacked == NULL) + pcb->rtime = -1; + else { + pcb->rtime = 0; + pcb->nrtx = 0; + } + + tcp_seg_free(rseg); + + /* Call the user specified function to call when sucessfully + * connected. */ + TCP_EVENT_CONNECTED(pcb, ERR_OK, err); + tcp_ack_now(pcb); + } + /* received ACK? possibly a half-open connection */ + else if (flags & TCP_ACK) { + /* send a RST to bring the other side in a non-synchronized state. */ + tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src), + tcphdr->dest, tcphdr->src); + } + break; + case SYN_RCVD: + if (flags & TCP_ACK) { + /* expected ACK number? */ + if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)) { + u16_t old_cwnd; + pcb->state = ESTABLISHED; + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); +#if LWIP_CALLBACK_API + LWIP_ASSERT("pcb->accept != NULL", pcb->accept != NULL); +#endif + /* Call the accept function. */ + TCP_EVENT_ACCEPT(pcb, ERR_OK, err); + if (err != ERR_OK) { + /* If the accept function returns with an error, we abort + * the connection. */ + tcp_abort(pcb); + return ERR_ABRT; + } + old_cwnd = pcb->cwnd; + /* If there was any data contained within this ACK, + * we'd better pass it on to the application as well. */ + tcp_receive(pcb); + + /* Prevent ACK for SYN to generate a sent event */ + if (pcb->acked != 0) { + pcb->acked--; + } + + pcb->cwnd = ((old_cwnd == 1) ? (pcb->mss * 2) : pcb->mss); + + if (recv_flags & TF_GOT_FIN) { + tcp_ack_now(pcb); + pcb->state = CLOSE_WAIT; + } + } + /* incorrect ACK number */ + else { + /* send RST */ + tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src), + tcphdr->dest, tcphdr->src); + } + } else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) { + /* Looks like another copy of the SYN - retransmit our SYN-ACK */ + tcp_rexmit(pcb); + } + break; + case CLOSE_WAIT: + /* FALLTHROUGH */ + case ESTABLISHED: + tcp_receive(pcb); + if (recv_flags & TF_GOT_FIN) { /* passive close */ + tcp_ack_now(pcb); + pcb->state = CLOSE_WAIT; + } + break; + case FIN_WAIT_1: + tcp_receive(pcb); + if (recv_flags & TF_GOT_FIN) { + if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt)) { + LWIP_DEBUGF(TCP_DEBUG, + ("TCP connection closed: FIN_WAIT_1 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_ack_now(pcb); + tcp_pcb_purge(pcb); + TCP_RMV(&tcp_active_pcbs, pcb); + pcb->state = TIME_WAIT; + TCP_REG(&tcp_tw_pcbs, pcb); + } else { + tcp_ack_now(pcb); + pcb->state = CLOSING; + } + } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt)) { + pcb->state = FIN_WAIT_2; + } + break; + case FIN_WAIT_2: + tcp_receive(pcb); + if (recv_flags & TF_GOT_FIN) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: FIN_WAIT_2 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_ack_now(pcb); + tcp_pcb_purge(pcb); + TCP_RMV(&tcp_active_pcbs, pcb); + pcb->state = TIME_WAIT; + TCP_REG(&tcp_tw_pcbs, pcb); + } + break; + case CLOSING: + tcp_receive(pcb); + if (flags & TCP_ACK && ackno == pcb->snd_nxt) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: CLOSING %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_pcb_purge(pcb); + TCP_RMV(&tcp_active_pcbs, pcb); + pcb->state = TIME_WAIT; + TCP_REG(&tcp_tw_pcbs, pcb); + } + break; + case LAST_ACK: + tcp_receive(pcb); + if (flags & TCP_ACK && ackno == pcb->snd_nxt) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: LAST_ACK %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + /* bugfix #21699: don't set pcb->state to CLOSED here or we risk leaking segments */ + recv_flags |= TF_CLOSED; + } + break; + default: + break; + } + return ERR_OK; +} + +#if TCP_QUEUE_OOSEQ +/** + * Insert segment into the list (segments covered with new one will be deleted) + * + * Called from tcp_receive() + */ +static void +tcp_oos_insert_segment(struct tcp_seg *cseg, struct tcp_seg *next) +{ + struct tcp_seg *old_seg; + + if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { + /* received segment overlaps all following segments */ + tcp_segs_free(next); + next = NULL; + } + else { + /* delete some following segments + oos queue may have segments with FIN flag */ + while (next && + TCP_SEQ_GEQ((seqno + cseg->len), + (next->tcphdr->seqno + next->len))) { + /* cseg with FIN already processed */ + if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) { + TCPH_FLAGS_SET(cseg->tcphdr, TCPH_FLAGS(cseg->tcphdr) | TCP_FIN); + } + old_seg = next; + next = next->next; + tcp_seg_free(old_seg); + } + if (next && + TCP_SEQ_GT(seqno + cseg->len, next->tcphdr->seqno)) { + /* We need to trim the incoming segment. */ + cseg->len = (u16_t)(next->tcphdr->seqno - seqno); + pbuf_realloc(cseg->p, cseg->len); + } + } + cseg->next = next; +} +#endif + +/** + * Called by tcp_process. Checks if the given segment is an ACK for outstanding + * data, and if so frees the memory of the buffered data. Next, is places the + * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment + * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until + * i it has been removed from the buffer. + * + * If the incoming segment constitutes an ACK for a segment that was used for RTT + * estimation, the RTT is estimated here as well. + * + * Called from tcp_process(). + */ +static void +tcp_receive(struct tcp_pcb *pcb) +{ + struct tcp_seg *next; +#if TCP_QUEUE_OOSEQ + struct tcp_seg *prev, *cseg; +#endif + struct pbuf *p; + s32_t off; + s16_t m; + u32_t right_wnd_edge; + u16_t new_tot_len; + int found_dupack = 0; + + if (flags & TCP_ACK) { + right_wnd_edge = pcb->snd_wnd + pcb->snd_wl2; + + /* Update window. */ + if (TCP_SEQ_LT(pcb->snd_wl1, seqno) || + (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) || + (pcb->snd_wl2 == ackno && tcphdr->wnd > pcb->snd_wnd)) { + pcb->snd_wnd = tcphdr->wnd; + pcb->snd_wl1 = seqno; + pcb->snd_wl2 = ackno; + if (pcb->snd_wnd > 0 && pcb->persist_backoff > 0) { + pcb->persist_backoff = 0; + } + LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %"U16_F"\n", pcb->snd_wnd)); +#if TCP_WND_DEBUG + } else { + if (pcb->snd_wnd != tcphdr->wnd) { + LWIP_DEBUGF(TCP_WND_DEBUG, + ("tcp_receive: no window update lastack %"U32_F" ackno %" + U32_F" wl1 %"U32_F" seqno %"U32_F" wl2 %"U32_F"\n", + pcb->lastack, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2)); + } +#endif /* TCP_WND_DEBUG */ + } + + /* (From Stevens TCP/IP Illustrated Vol II, p970.) Its only a + * duplicate ack if: + * 1) It doesn't ACK new data + * 2) length of received packet is zero (i.e. no payload) + * 3) the advertised window hasn't changed + * 4) There is outstanding unacknowledged data (retransmission timer running) + * 5) The ACK is == biggest ACK sequence number so far seen (snd_una) + * + * If it passes all five, should process as a dupack: + * a) dupacks < 3: do nothing + * b) dupacks == 3: fast retransmit + * c) dupacks > 3: increase cwnd + * + * If it only passes 1-3, should reset dupack counter (and add to + * stats, which we don't do in lwIP) + * + * If it only passes 1, should reset dupack counter + * + */ + + /* Clause 1 */ + if (TCP_SEQ_LEQ(ackno, pcb->lastack)) { + pcb->acked = 0; + /* Clause 2 */ + if (tcplen == 0) { + /* Clause 3 */ + if (pcb->snd_wl2 + pcb->snd_wnd == right_wnd_edge){ + /* Clause 4 */ + if (pcb->rtime >= 0) { + /* Clause 5 */ + if (pcb->lastack == ackno) { + found_dupack = 1; + if (pcb->dupacks + 1 > pcb->dupacks) + ++pcb->dupacks; + if (pcb->dupacks > 3) { + /* Inflate the congestion window, but not if it means that + the value overflows. */ + if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { + pcb->cwnd += pcb->mss; + } + } else if (pcb->dupacks == 3) { + /* Do fast retransmit */ + tcp_rexmit_fast(pcb); + } + } + } + } + } + /* If Clause (1) or more is true, but not a duplicate ack, reset + * count of consecutive duplicate acks */ + if (!found_dupack) { + pcb->dupacks = 0; + } + } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)){ + /* We come here when the ACK acknowledges new data. */ + + /* Reset the "IN Fast Retransmit" flag, since we are no longer + in fast retransmit. Also reset the congestion window to the + slow start threshold. */ + if (pcb->flags & TF_INFR) { + pcb->flags &= ~TF_INFR; + pcb->cwnd = pcb->ssthresh; + } + + /* Reset the number of retransmissions. */ + pcb->nrtx = 0; + + /* Reset the retransmission time-out. */ + pcb->rto = (pcb->sa >> 3) + pcb->sv; + + /* Update the send buffer space. Diff between the two can never exceed 64K? */ + pcb->acked = (u16_t)(ackno - pcb->lastack); + + pcb->snd_buf += pcb->acked; + + /* Reset the fast retransmit variables. */ + pcb->dupacks = 0; + pcb->lastack = ackno; + + /* Update the congestion control variables (cwnd and + ssthresh). */ + if (pcb->state >= ESTABLISHED) { + if (pcb->cwnd < pcb->ssthresh) { + if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { + pcb->cwnd += pcb->mss; + } + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"U16_F"\n", pcb->cwnd)); + } else { + u16_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd); + if (new_cwnd > pcb->cwnd) { + pcb->cwnd = new_cwnd; + } + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %"U16_F"\n", pcb->cwnd)); + } + } + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %"U32_F", unacked->seqno %"U32_F":%"U32_F"\n", + ackno, + pcb->unacked != NULL? + ntohl(pcb->unacked->tcphdr->seqno): 0, + pcb->unacked != NULL? + ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0)); + + /* Remove segment from the unacknowledged list if the incoming + ACK acknowlegdes them. */ + while (pcb->unacked != NULL && + TCP_SEQ_LEQ(ntohl(pcb->unacked->tcphdr->seqno) + + TCP_TCPLEN(pcb->unacked), ackno)) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unacked\n", + ntohl(pcb->unacked->tcphdr->seqno), + ntohl(pcb->unacked->tcphdr->seqno) + + TCP_TCPLEN(pcb->unacked))); + + next = pcb->unacked; + pcb->unacked = pcb->unacked->next; + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen)); + LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= pbuf_clen(next->p))); + /* Prevent ACK for FIN to generate a sent event */ + if ((pcb->acked != 0) && ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0)) { + pcb->acked--; + } + + pcb->snd_queuelen -= pbuf_clen(next->p); + tcp_seg_free(next); + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unacked)\n", (u16_t)pcb->snd_queuelen)); + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL || + pcb->unsent != NULL); + } + } + + /* If there's nothing left to acknowledge, stop the retransmit + timer, otherwise reset it to start again */ + if(pcb->unacked == NULL) + pcb->rtime = -1; + else + pcb->rtime = 0; + + pcb->polltmr = 0; + } else { + /* Fix bug bug #21582: out of sequence ACK, didn't really ack anything */ + pcb->acked = 0; + } + + /* We go through the ->unsent list to see if any of the segments + on the list are acknowledged by the ACK. This may seem + strange since an "unsent" segment shouldn't be acked. The + rationale is that lwIP puts all outstanding segments on the + ->unsent list after a retransmission, so these segments may + in fact have been sent once. */ + while (pcb->unsent != NULL && + TCP_SEQ_BETWEEN(ackno, ntohl(pcb->unsent->tcphdr->seqno) + + TCP_TCPLEN(pcb->unsent), pcb->snd_nxt)) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unsent\n", + ntohl(pcb->unsent->tcphdr->seqno), ntohl(pcb->unsent->tcphdr->seqno) + + TCP_TCPLEN(pcb->unsent))); + + next = pcb->unsent; + pcb->unsent = pcb->unsent->next; + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen)); + LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= pbuf_clen(next->p))); + /* Prevent ACK for FIN to generate a sent event */ + if ((pcb->acked != 0) && ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0)) { + pcb->acked--; + } + pcb->snd_queuelen -= pbuf_clen(next->p); + tcp_seg_free(next); + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unsent)\n", (u16_t)pcb->snd_queuelen)); + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_receive: valid queue length", + pcb->unacked != NULL || pcb->unsent != NULL); + } + } + /* End of ACK for new data processing. */ + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %"U32_F" rtseq %"U32_F" ackno %"U32_F"\n", + pcb->rttest, pcb->rtseq, ackno)); + + /* RTT estimation calculations. This is done by checking if the + incoming segment acknowledges the segment we use to take a + round-trip time measurement. */ + if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) { + /* diff between this shouldn't exceed 32K since this are tcp timer ticks + and a round-trip shouldn't be that long... */ + m = (s16_t)(tcp_ticks - pcb->rttest); + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n", + m, m * TCP_SLOW_INTERVAL)); + + /* This is taken directly from VJs original code in his paper */ + m = m - (pcb->sa >> 3); + pcb->sa += m; + if (m < 0) { + m = -m; + } + m = m - (pcb->sv >> 2); + pcb->sv += m; + pcb->rto = (pcb->sa >> 3) + pcb->sv; + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" milliseconds)\n", + pcb->rto, pcb->rto * TCP_SLOW_INTERVAL)); + + pcb->rttest = 0; + } + } + + /* If the incoming segment contains data, we must process it + further. */ + if (tcplen > 0) { + /* This code basically does three things: + + +) If the incoming segment contains data that is the next + in-sequence data, this data is passed to the application. This + might involve trimming the first edge of the data. The rcv_nxt + variable and the advertised window are adjusted. + + +) If the incoming segment has data that is above the next + sequence number expected (->rcv_nxt), the segment is placed on + the ->ooseq queue. This is done by finding the appropriate + place in the ->ooseq queue (which is ordered by sequence + number) and trim the segment in both ends if needed. An + immediate ACK is sent to indicate that we received an + out-of-sequence segment. + + +) Finally, we check if the first segment on the ->ooseq queue + now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If + rcv_nxt > ooseq->seqno, we must trim the first edge of the + segment on ->ooseq before we adjust rcv_nxt. The data in the + segments that are now on sequence are chained onto the + incoming segment so that we only need to call the application + once. + */ + + /* First, we check if we must trim the first edge. We have to do + this if the sequence number of the incoming segment is less + than rcv_nxt, and the sequence number plus the length of the + segment is larger than rcv_nxt. */ + /* if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){ + if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/ + if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)){ + /* Trimming the first edge is done by pushing the payload + pointer in the pbuf downwards. This is somewhat tricky since + we do not want to discard the full contents of the pbuf up to + the new starting point of the data since we have to keep the + TCP header which is present in the first pbuf in the chain. + + What is done is really quite a nasty hack: the first pbuf in + the pbuf chain is pointed to by inseg.p. Since we need to be + able to deallocate the whole pbuf, we cannot change this + inseg.p pointer to point to any of the later pbufs in the + chain. Instead, we point the ->payload pointer in the first + pbuf to data in one of the later pbufs. We also set the + inseg.data pointer to point to the right place. This way, the + ->p pointer will still point to the first pbuf, but the + ->p->payload pointer will point to data in another pbuf. + + After we are done with adjusting the pbuf pointers we must + adjust the ->data pointer in the seg and the segment + length.*/ + + off = pcb->rcv_nxt - seqno; + p = inseg.p; + LWIP_ASSERT("inseg.p != NULL", inseg.p); + LWIP_ASSERT("insane offset!", (off < 0x7fff)); + if (inseg.p->len < off) { + LWIP_ASSERT("pbuf too short!", (((s32_t)inseg.p->tot_len) >= off)); + new_tot_len = (u16_t)(inseg.p->tot_len - off); + while (p->len < off) { + off -= p->len; + /* KJM following line changed (with addition of new_tot_len var) + to fix bug #9076 + inseg.p->tot_len -= p->len; */ + p->tot_len = new_tot_len; + p->len = 0; + p = p->next; + } + if(pbuf_header(p, (s16_t)-off)) { + /* Do we need to cope with this failing? Assert for now */ + LWIP_ASSERT("pbuf_header failed", 0); + } + } else { + if(pbuf_header(inseg.p, (s16_t)-off)) { + /* Do we need to cope with this failing? Assert for now */ + LWIP_ASSERT("pbuf_header failed", 0); + } + } + /* KJM following line changed to use p->payload rather than inseg->p->payload + to fix bug #9076 */ + inseg.dataptr = p->payload; + inseg.len -= (u16_t)(pcb->rcv_nxt - seqno); + inseg.tcphdr->seqno = seqno = pcb->rcv_nxt; + } + else { + if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){ + /* the whole segment is < rcv_nxt */ + /* must be a duplicate of a packet that has already been correctly handled */ + + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno)); + tcp_ack_now(pcb); + } + } + + /* The sequence number must be within the window (above rcv_nxt + and below rcv_nxt + rcv_wnd) in order to be further + processed. */ + if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, + pcb->rcv_nxt + pcb->rcv_wnd - 1)){ + if (pcb->rcv_nxt == seqno) { + /* The incoming segment is the next in sequence. We check if + we have to trim the end of the segment and update rcv_nxt + and pass the data to the application. */ + tcplen = TCP_TCPLEN(&inseg); + + if (tcplen > pcb->rcv_wnd) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, + ("tcp_receive: other end overran receive window" + "seqno %"U32_F" len %"U32_F" right edge %"U32_F"\n", + seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd)); + if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { + /* Must remove the FIN from the header as we're trimming + * that byte of sequence-space from the packet */ + TCPH_FLAGS_SET(inseg.tcphdr, TCPH_FLAGS(inseg.tcphdr) &~ TCP_FIN); + } + /* Adjust length of segment to fit in the window. */ + inseg.len = pcb->rcv_wnd; + if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) { + inseg.len -= 1; + } + pbuf_realloc(inseg.p, inseg.len); + tcplen = TCP_TCPLEN(&inseg); + LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n", + (seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd)); + } +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL) { + if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, + ("tcp_receive: received in-order FIN, binning ooseq queue\n")); + /* Received in-order FIN means anything that was received + * out of order must now have been received in-order, so + * bin the ooseq queue + * rcv_nxt + * . |--ooseq--| + * .==seg============|FIN + */ + while (pcb->ooseq != NULL) { + struct tcp_seg *old_ooseq = pcb->ooseq; + pcb->ooseq = pcb->ooseq->next; + tcp_seg_free(old_ooseq); + } + } + else { + struct tcp_seg* next = pcb->ooseq; + struct tcp_seg *old_seg; + /* rcv_nxt + * . |--ooseq--| + * .==seg============| + */ + while (next && + TCP_SEQ_GEQ(seqno + tcplen, + next->tcphdr->seqno + next->len)) { + /* inseg doesn't have FIN (already processed) */ + if (TCPH_FLAGS(next->tcphdr) & TCP_FIN && + (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) == 0) { + TCPH_FLAGS_SET(inseg.tcphdr, + TCPH_FLAGS(inseg.tcphdr) | TCP_FIN); + tcplen = TCP_TCPLEN(&inseg); + } + old_seg = next; + next = next->next; + tcp_seg_free(old_seg); + } + /* rcv_nxt + * . |--ooseq--| + * .==seg============| + */ + if (next && + TCP_SEQ_GT(seqno + tcplen, + next->tcphdr->seqno)) { + /* FIN in inseg already handled by dropping whole ooseq queue */ + inseg.len = (u16_t)(pcb->ooseq->tcphdr->seqno - seqno); + if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) { + inseg.len -= 1; + } + pbuf_realloc(inseg.p, inseg.len); + tcplen = TCP_TCPLEN(&inseg); + LWIP_ASSERT("tcp_receive: segment not trimmed correctly to ooseq queue\n", + (seqno + tcplen) == pcb->ooseq->tcphdr->seqno); + } + pcb->ooseq = next; + } + } +#endif /* TCP_QUEUE_OOSEQ */ + + pcb->rcv_nxt = seqno + tcplen; + + /* Update the receiver's (our) window. */ + LWIP_ASSERT("tcp_receive: tcplen > rcv_wnd\n", pcb->rcv_wnd >= tcplen); + pcb->rcv_wnd -= tcplen; + + tcp_update_rcv_ann_wnd(pcb); + + /* If there is data in the segment, we make preparations to + pass this up to the application. The ->recv_data variable + is used for holding the pbuf that goes to the + application. The code for reassembling out-of-sequence data + chains its data on this pbuf as well. + + If the segment was a FIN, we set the TF_GOT_FIN flag that will + be used to indicate to the application that the remote side has + closed its end of the connection. */ + if (inseg.p->tot_len > 0) { + recv_data = inseg.p; + /* Since this pbuf now is the responsibility of the + application, we delete our reference to it so that we won't + (mistakingly) deallocate it. */ + inseg.p = NULL; + } + if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n")); + recv_flags |= TF_GOT_FIN; + } + +#if TCP_QUEUE_OOSEQ + /* We now check if we have segments on the ->ooseq queue that + is now in sequence. */ + while (pcb->ooseq != NULL && + pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) { + + cseg = pcb->ooseq; + seqno = pcb->ooseq->tcphdr->seqno; + + pcb->rcv_nxt += TCP_TCPLEN(cseg); + LWIP_ASSERT("tcp_receive: ooseq tcplen > rcv_wnd\n", + pcb->rcv_wnd >= TCP_TCPLEN(cseg)); + pcb->rcv_wnd -= TCP_TCPLEN(cseg); + + tcp_update_rcv_ann_wnd(pcb); + + if (cseg->p->tot_len > 0) { + /* Chain this pbuf onto the pbuf that we will pass to + the application. */ + if (recv_data) { + pbuf_cat(recv_data, cseg->p); + } else { + recv_data = cseg->p; + } + cseg->p = NULL; + } + if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n")); + recv_flags |= TF_GOT_FIN; + if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */ + pcb->state = CLOSE_WAIT; + } + } + + pcb->ooseq = cseg->next; + tcp_seg_free(cseg); + } +#endif /* TCP_QUEUE_OOSEQ */ + + + /* Acknowledge the segment(s). */ + tcp_ack(pcb); + + } else { + /* We get here if the incoming segment is out-of-sequence. */ + tcp_send_empty_ack(pcb); +#if TCP_QUEUE_OOSEQ + /* We queue the segment on the ->ooseq queue. */ + if (pcb->ooseq == NULL) { + pcb->ooseq = tcp_seg_copy(&inseg); + } else { + /* If the queue is not empty, we walk through the queue and + try to find a place where the sequence number of the + incoming segment is between the sequence numbers of the + previous and the next segment on the ->ooseq queue. That is + the place where we put the incoming segment. If needed, we + trim the second edges of the previous and the incoming + segment so that it will fit into the sequence. + + If the incoming segment has the same sequence number as a + segment on the ->ooseq queue, we discard the segment that + contains less data. */ + + prev = NULL; + for(next = pcb->ooseq; next != NULL; next = next->next) { + if (seqno == next->tcphdr->seqno) { + /* The sequence number of the incoming segment is the + same as the sequence number of the segment on + ->ooseq. We check the lengths to see which one to + discard. */ + if (inseg.len > next->len) { + /* The incoming segment is larger than the old + segment. We replace some segments with the new + one. */ + cseg = tcp_seg_copy(&inseg); + if (cseg != NULL) { + if (prev != NULL) { + prev->next = cseg; + } else { + pcb->ooseq = cseg; + } + tcp_oos_insert_segment(cseg, next); + } + break; + } else { + /* Either the lenghts are the same or the incoming + segment was smaller than the old one; in either + case, we ditch the incoming segment. */ + break; + } + } else { + if (prev == NULL) { + if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) { + /* The sequence number of the incoming segment is lower + than the sequence number of the first segment on the + queue. We put the incoming segment first on the + queue. */ + cseg = tcp_seg_copy(&inseg); + if (cseg != NULL) { + pcb->ooseq = cseg; + tcp_oos_insert_segment(cseg, next); + } + break; + } + } else { + /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) && + TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/ + if (TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno+1, next->tcphdr->seqno-1)) { + /* The sequence number of the incoming segment is in + between the sequence numbers of the previous and + the next segment on ->ooseq. We trim trim the previous + segment, delete next segments that included in received segment + and trim received, if needed. */ + cseg = tcp_seg_copy(&inseg); + if (cseg != NULL) { + if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) { + /* We need to trim the prev segment. */ + prev->len = (u16_t)(seqno - prev->tcphdr->seqno); + pbuf_realloc(prev->p, prev->len); + } + prev->next = cseg; + tcp_oos_insert_segment(cseg, next); + } + break; + } + } + /* If the "next" segment is the last segment on the + ooseq queue, we add the incoming segment to the end + of the list. */ + if (next->next == NULL && + TCP_SEQ_GT(seqno, next->tcphdr->seqno)) { + if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) { + /* segment "next" already contains all data */ + break; + } + next->next = tcp_seg_copy(&inseg); + if (next->next != NULL) { + if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) { + /* We need to trim the last segment. */ + next->len = (u16_t)(seqno - next->tcphdr->seqno); + pbuf_realloc(next->p, next->len); + } + } + break; + } + } + prev = next; + } + } +#endif /* TCP_QUEUE_OOSEQ */ + + } + } else { + /* The incoming segment is not withing the window. */ + tcp_send_empty_ack(pcb); + } + } else { + /* Segments with length 0 is taken care of here. Segments that + fall out of the window are ACKed. */ + /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) || + TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/ + if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){ + tcp_ack_now(pcb); + } + } +} + +/** + * Parses the options contained in the incoming segment. + * + * Called from tcp_listen_input() and tcp_process(). + * Currently, only the MSS option is supported! + * + * @param pcb the tcp_pcb for which a segment arrived + */ +static void +tcp_parseopt(struct tcp_pcb *pcb) +{ + u16_t c, max_c; + u16_t mss; + u8_t *opts, opt; +#if LWIP_TCP_TIMESTAMPS + u32_t tsval; +#endif + + opts = (u8_t *)tcphdr + TCP_HLEN; + + /* Parse the TCP MSS option, if present. */ + if(TCPH_HDRLEN(tcphdr) > 0x5) { + max_c = (TCPH_HDRLEN(tcphdr) - 5) << 2; + for (c = 0; c < max_c; ) { + opt = opts[c]; + switch (opt) { + case 0x00: + /* End of options. */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: EOL\n")); + return; + case 0x01: + /* NOP option. */ + ++c; + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: NOP\n")); + break; + case 0x02: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: MSS\n")); + if (opts[c + 1] != 0x04 || c + 0x04 > max_c) { + /* Bad length */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); + return; + } + /* An MSS option with the right option length. */ + mss = (opts[c + 2] << 8) | opts[c + 3]; + /* Limit the mss to the configured TCP_MSS and prevent division by zero */ + pcb->mss = ((mss > TCP_MSS) || (mss == 0)) ? TCP_MSS : mss; + /* Advance to next option */ + c += 0x04; + break; +#if LWIP_TCP_TIMESTAMPS + case 0x08: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: TS\n")); + if (opts[c + 1] != 0x0A || c + 0x0A > max_c) { + /* Bad length */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); + return; + } + /* TCP timestamp option with valid length */ + tsval = (opts[c+2]) | (opts[c+3] << 8) | + (opts[c+4] << 16) | (opts[c+5] << 24); + if (flags & TCP_SYN) { + pcb->ts_recent = ntohl(tsval); + pcb->flags |= TF_TIMESTAMP; + } else if (TCP_SEQ_BETWEEN(pcb->ts_lastacksent, seqno, seqno+tcplen)) { + pcb->ts_recent = ntohl(tsval); + } + /* Advance to next option */ + c += 0x0A; + break; +#endif + default: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: other\n")); + if (opts[c + 1] == 0) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); + /* If the length field is zero, the options are malformed + and we don't process them further. */ + return; + } + /* All other options have a length field, so that we easily + can skip past them. */ + c += opts[c + 1]; + } + } + } +} + +#endif /* LWIP_TCP */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/tcp_out.c b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/tcp_out.c new file mode 100644 index 0000000000000000000000000000000000000000..9605beb8e5a37680cb523a5e5c09b3a39d2bdfb9 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/tcp_out.c @@ -0,0 +1,1071 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/** + * @file + * Transmission Control Protocol, outgoing traffic + * + * The output functions of TCP. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/tcp.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/sys.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/inet.h" +#include "lwip/inet_chksum.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" + +#include +#define _TEST_HD_ +/* Forward declarations.*/ +static void tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb); + +static struct tcp_hdr * +tcp_output_set_header(struct tcp_pcb *pcb, struct pbuf *p, int optlen, + u32_t seqno_be /* already in network byte order */) +{ + struct tcp_hdr *tcphdr = p->payload; + tcphdr->src = htons(pcb->local_port); + tcphdr->dest = htons(pcb->remote_port); + tcphdr->seqno = seqno_be; + tcphdr->ackno = htonl(pcb->rcv_nxt); + TCPH_FLAGS_SET(tcphdr, TCP_ACK); + tcphdr->wnd = htons(pcb->rcv_ann_wnd); + tcphdr->urgp = 0; + TCPH_HDRLEN_SET(tcphdr, (5 + optlen / 4)); + tcphdr->chksum = 0; + + /* If we're sending a packet, update the announced right window edge */ + pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd; + + return tcphdr; +} + +/** + * Called by tcp_close() to send a segment including flags but not data. + * + * @param pcb the tcp_pcb over which to send a segment + * @param flags the flags to set in the segment header + * @return ERR_OK if sent, another err_t otherwise + */ +err_t +tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags) +{ + /* no data, no length, flags, copy=1, no optdata */ + return tcp_enqueue(pcb, NULL, 0, flags, TCP_WRITE_FLAG_COPY, 0); +} + +/** + * Write data for sending (but does not send it immediately). + * + * It waits in the expectation of more data being sent soon (as + * it can send them more efficiently by combining them together). + * To prompt the system to send data now, call tcp_output() after + * calling tcp_write(). + * + * @param pcb Protocol control block of the TCP connection to enqueue data for. + * @param data pointer to the data to send + * @param len length (in bytes) of the data to send + * @param apiflags combination of following flags : + * - TCP_WRITE_FLAG_COPY (0x01) data will be copied into memory belonging to the stack + * - TCP_WRITE_FLAG_MORE (0x02) for TCP connection, PSH flag will be set on last segment sent, + * @return ERR_OK if enqueued, another err_t on error + * + * @see tcp_write() + */ +err_t +tcp_write(struct tcp_pcb *pcb, const void *data, u16_t len, u8_t apiflags) +{ + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, data=%p, len=%"U16_F", apiflags=%"U16_F")\n", (void *)pcb, + data, len, (u16_t)apiflags)); + /* connection is in valid state for data transmission? */ + if (pcb->state == ESTABLISHED || + pcb->state == CLOSE_WAIT || + pcb->state == SYN_SENT || + pcb->state == SYN_RCVD) { + if (len > 0) { +#if LWIP_TCP_TIMESTAMPS + return tcp_enqueue(pcb, (void *)data, len, 0, apiflags, + pcb->flags & TF_TIMESTAMP ? TF_SEG_OPTS_TS : 0); +#else + return tcp_enqueue(pcb, (void *)data, len, 0, apiflags, 0); +#endif + } + return ERR_OK; + } else { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_STATE | LWIP_DBG_LEVEL_SEVERE, ("tcp_write() called in invalid state\n")); + return ERR_CONN; + } +} + +/** + * Enqueue data and/or TCP options for transmission + * + * Called by tcp_connect(), tcp_listen_input(), tcp_send_ctrl() and tcp_write(). + * + * @param pcb Protocol control block for the TCP connection to enqueue data for. + * @param arg Pointer to the data to be enqueued for sending. + * @param len Data length in bytes + * @param flags tcp header flags to set in the outgoing segment + * @param apiflags combination of following flags : + * - TCP_WRITE_FLAG_COPY (0x01) data will be copied into memory belonging to the stack + * - TCP_WRITE_FLAG_MORE (0x02) for TCP connection, PSH flag will be set on last segment sent, + * @param optflags options to include in segment later on (see definition of struct tcp_seg) + */ +err_t +tcp_enqueue(struct tcp_pcb *pcb, void *arg, u16_t len, + u8_t flags, u8_t apiflags, u8_t optflags) +{ + struct pbuf *p; + struct tcp_seg *seg, *useg, *queue; + u32_t seqno; + u16_t left, seglen; + void *ptr; + u16_t queuelen; + u8_t optlen; + + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, + ("tcp_enqueue(pcb=%p, arg=%p, len=%"U16_F", flags=%"X16_F", apiflags=%"U16_F")\n", + (void *)pcb, arg, len, (u16_t)flags, (u16_t)apiflags)); + LWIP_ERROR("tcp_enqueue: packet needs payload, options, or SYN/FIN (programmer violates API)", + ((len != 0) || (optflags != 0) || ((flags & (TCP_SYN | TCP_FIN)) != 0)), + return ERR_ARG;); + LWIP_ERROR("tcp_enqueue: len != 0 || arg == NULL (programmer violates API)", + ((len != 0) || (arg == NULL)), return ERR_ARG;); + + /* fail on too much data */ + if (len > pcb->snd_buf) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_WARNING, + ("tcp_enqueue: too much data (len=%"U16_F" > snd_buf=%"U16_F")\n", len, pcb->snd_buf)); + pcb->flags |= TF_NAGLEMEMERR; + return ERR_MEM; + } + left = len; + ptr = arg; + + optlen = LWIP_TCP_OPT_LENGTH(optflags); + + /* seqno will be the sequence number of the first segment enqueued + * by the call to this function. */ + seqno = pcb->snd_lbb; + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen)); + + /* If total number of pbufs on the unsent/unacked queues exceeds the + * configured maximum, return an error */ + queuelen = pcb->snd_queuelen; + /* check for configured max queuelen and possible overflow */ + if ((queuelen >= TCP_SND_QUEUELEN) || (queuelen > TCP_SNDQUEUELEN_OVERFLOW)) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_WARNING, + ("tcp_enqueue: too long queue %"U16_F" (max %"U16_F")\n", queuelen, TCP_SND_QUEUELEN)); + TCP_STATS_INC(tcp.memerr); + pcb->flags |= TF_NAGLEMEMERR; + return ERR_MEM; + } + if (queuelen != 0) { + LWIP_ASSERT("tcp_enqueue: pbufs on queue => at least one queue non-empty", + pcb->unacked != NULL || pcb->unsent != NULL); + } else { + LWIP_ASSERT("tcp_enqueue: no pbufs on queue => both queues empty", + pcb->unacked == NULL && pcb->unsent == NULL); + } + + /* First, break up the data into segments and tuck them together in + * the local "queue" variable. */ + useg = queue = seg = NULL; + seglen = 0; + while (queue == NULL || left > 0) { + /* The segment length (including options) should be at most the MSS */ + seglen = left > (pcb->mss - optlen) ? (pcb->mss - optlen) : left; + + /* Allocate memory for tcp_seg, and fill in fields. */ + seg = memp_malloc(MEMP_TCP_SEG); + if (seg == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("tcp_enqueue: could not allocate memory for tcp_seg\n")); + goto memerr; + } + seg->next = NULL; + seg->p = NULL; + + /* first segment of to-be-queued data? */ + if (queue == NULL) { + queue = seg; + } + /* subsequent segments of to-be-queued data */ + else { + /* Attach the segment to the end of the queued segments */ + LWIP_ASSERT("useg != NULL", useg != NULL); + useg->next = seg; + } + /* remember last segment of to-be-queued data for next iteration */ + useg = seg; + + /* If copy is set, memory should be allocated + * and data copied into pbuf, otherwise data comes from + * ROM or other static memory, and need not be copied. */ + if (apiflags & TCP_WRITE_FLAG_COPY) { + if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, seglen + optlen, PBUF_RAM)) == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("tcp_enqueue : could not allocate memory for pbuf copy size %"U16_F"\n", seglen)); + goto memerr; + } + LWIP_ASSERT("check that first pbuf can hold the complete seglen", + (seg->p->len >= seglen + optlen)); + queuelen += pbuf_clen(seg->p); + if (arg != NULL) { + MEMCPY((char *)seg->p->payload + optlen, ptr, seglen); + } + seg->dataptr = seg->p->payload; + } + /* do not copy data */ + else { + /* First, allocate a pbuf for the headers. */ + if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("tcp_enqueue: could not allocate memory for header pbuf\n")); + goto memerr; + } + queuelen += pbuf_clen(seg->p); + + /* Second, allocate a pbuf for holding the data. + * since the referenced data is available at least until it is sent out on the + * link (as it has to be ACKed by the remote party) we can safely use PBUF_ROM + * instead of PBUF_REF here. + */ + if (left > 0) { + if ((p = pbuf_alloc(PBUF_RAW, seglen, PBUF_ROM)) == NULL) { + /* If allocation fails, we have to deallocate the header pbuf as well. */ + pbuf_free(seg->p); + seg->p = NULL; + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("tcp_enqueue: could not allocate memory for zero-copy pbuf\n")); + goto memerr; + } + ++queuelen; + /* reference the non-volatile payload data */ + p->payload = ptr; + seg->dataptr = ptr; + + /* Concatenate the headers and data pbufs together. */ + pbuf_cat(seg->p/*header*/, p/*data*/); + p = NULL; + } + } + + /* Now that there are more segments queued, we check again if the + length of the queue exceeds the configured maximum or overflows. */ + if ((queuelen > TCP_SND_QUEUELEN) || (queuelen > TCP_SNDQUEUELEN_OVERFLOW)) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("tcp_enqueue: queue too long %"U16_F" (%"U16_F")\n", queuelen, TCP_SND_QUEUELEN)); + goto memerr; + } + + seg->len = seglen; + + /* build TCP header */ + if (pbuf_header(seg->p, TCP_HLEN)) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_enqueue: no room for TCP header in pbuf.\n")); + TCP_STATS_INC(tcp.err); + goto memerr; + } + seg->tcphdr = seg->p->payload; + seg->tcphdr->src = htons(pcb->local_port); + seg->tcphdr->dest = htons(pcb->remote_port); + seg->tcphdr->seqno = htonl(seqno); + seg->tcphdr->urgp = 0; + TCPH_FLAGS_SET(seg->tcphdr, flags); + /* don't fill in tcphdr->ackno and tcphdr->wnd until later */ + + seg->flags = optflags; + + /* Set the length of the header */ + TCPH_HDRLEN_SET(seg->tcphdr, (5 + optlen / 4)); + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE, ("tcp_enqueue: queueing %"U32_F":%"U32_F" (0x%"X16_F")\n", + ntohl(seg->tcphdr->seqno), + ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg), + (u16_t)flags)); + + left -= seglen; + seqno += seglen; + ptr = (void *)((u8_t *)ptr + seglen); + } + + /* Now that the data to be enqueued has been broken up into TCP + segments in the queue variable, we add them to the end of the + pcb->unsent queue. */ + if (pcb->unsent == NULL) { + useg = NULL; + } + else { + for (useg = pcb->unsent; useg->next != NULL; useg = useg->next); + } + /* { useg is last segment on the unsent queue, NULL if list is empty } */ + + /* If there is room in the last pbuf on the unsent queue, + chain the first pbuf on the queue together with that. */ + if (useg != NULL && + TCP_TCPLEN(useg) != 0 && + !(TCPH_FLAGS(useg->tcphdr) & (TCP_SYN | TCP_FIN)) && + (!(flags & (TCP_SYN | TCP_FIN)) || (flags == TCP_FIN)) && + /* fit within max seg size */ + (useg->len + queue->len <= pcb->mss) && + /* only concatenate segments with the same options */ + (useg->flags == queue->flags) && + /* segments are consecutive */ + (ntohl(useg->tcphdr->seqno) + useg->len == ntohl(queue->tcphdr->seqno)) ) { + /* Remove TCP header from first segment of our to-be-queued list */ + if(pbuf_header(queue->p, -(TCP_HLEN + optlen))) { + /* Can we cope with this failing? Just assert for now */ + LWIP_ASSERT("pbuf_header failed\n", 0); + TCP_STATS_INC(tcp.err); + goto memerr; + } + if (queue->p->len == 0) { + /* free the first (header-only) pbuf if it is now empty (contained only headers) */ + struct pbuf *old_q = queue->p; + queue->p = queue->p->next; + old_q->next = NULL; + queuelen--; + pbuf_free(old_q); + } + if (flags & TCP_FIN) { + /* the new segment contains only FIN, no data -> put the FIN into the last segment */ + LWIP_ASSERT("FIN enqueued together with data", queue->p == NULL && queue->len == 0); + TCPH_SET_FLAG(useg->tcphdr, TCP_FIN); + } else { + LWIP_ASSERT("zero-length pbuf", (queue->p != NULL) && (queue->p->len > 0)); + pbuf_cat(useg->p, queue->p); + useg->len += queue->len; + useg->next = queue->next; + } + + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("tcp_enqueue: chaining segments, new len %"U16_F"\n", useg->len)); + if (seg == queue) { + seg = useg; + seglen = useg->len; + } + memp_free(MEMP_TCP_SEG, queue); + } + else { + /* empty list */ + if (useg == NULL) { + /* initialize list with this segment */ + pcb->unsent = queue; + } + /* enqueue segment */ + else { + useg->next = queue; + } + } + if ((flags & TCP_SYN) || (flags & TCP_FIN)) { + ++len; + } + if (flags & TCP_FIN) { + pcb->flags |= TF_FIN; + } + pcb->snd_lbb += len; + + pcb->snd_buf -= len; + + /* update number of segments on the queues */ + pcb->snd_queuelen = queuelen; + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: %"S16_F" (after enqueued)\n", pcb->snd_queuelen)); + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_enqueue: valid queue length", + pcb->unacked != NULL || pcb->unsent != NULL); + } + + /* Set the PSH flag in the last segment that we enqueued, but only + if the segment has data (indicated by seglen > 0). */ + if (seg != NULL && seglen > 0 && seg->tcphdr != NULL && ((apiflags & TCP_WRITE_FLAG_MORE)==0)) { + TCPH_SET_FLAG(seg->tcphdr, TCP_PSH); + } + + return ERR_OK; +memerr: + pcb->flags |= TF_NAGLEMEMERR; + TCP_STATS_INC(tcp.memerr); + + if (queue != NULL) { + tcp_segs_free(queue); + } + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_enqueue: valid queue length", pcb->unacked != NULL || + pcb->unsent != NULL); + } + LWIP_DEBUGF(TCP_QLEN_DEBUG | LWIP_DBG_STATE, ("tcp_enqueue: %"S16_F" (with mem err)\n", pcb->snd_queuelen)); + return ERR_MEM; +} + + +#if LWIP_TCP_TIMESTAMPS +/* Build a timestamp option (12 bytes long) at the specified options pointer) + * + * @param pcb tcp_pcb + * @param opts option pointer where to store the timestamp option + */ +static void +tcp_build_timestamp_option(struct tcp_pcb *pcb, u32_t *opts) +{ + /* Pad with two NOP options to make everything nicely aligned */ + opts[0] = htonl(0x0101080A); + opts[1] = htonl(sys_now()); + opts[2] = htonl(pcb->ts_recent); +} +#endif + +/** Send an ACK without data. + * + * @param pcb Protocol control block for the TCP connection to send the ACK + */ +err_t +tcp_send_empty_ack(struct tcp_pcb *pcb) +{ + struct pbuf *p; + struct tcp_hdr *tcphdr; + u8_t optlen = 0; + +#if LWIP_TCP_TIMESTAMPS + if (pcb->flags & TF_TIMESTAMP) { + optlen = LWIP_TCP_OPT_LENGTH(TF_SEG_OPTS_TS); + } +#endif + p = pbuf_alloc(PBUF_IP, TCP_HLEN + optlen, PBUF_RAM); + if (p == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n")); + return ERR_BUF; + } + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, + ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt)); + /* remove ACK flags from the PCB, as we send an empty ACK now */ + pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); + + tcphdr = tcp_output_set_header(pcb, p, optlen, htonl(pcb->snd_nxt)); + + /* NB. MSS option is only sent on SYNs, so ignore it here */ +#if LWIP_TCP_TIMESTAMPS + pcb->ts_lastacksent = pcb->rcv_nxt; + + if (pcb->flags & TF_TIMESTAMP) { + tcp_build_timestamp_option(pcb, (u32_t *)(tcphdr + 1)); + } +#endif + +#if CHECKSUM_GEN_TCP + tcphdr->chksum = inet_chksum_pseudo(p, &(pcb->local_ip), &(pcb->remote_ip), + IP_PROTO_TCP, p->tot_len); +#endif +#if LWIP_NETIF_HWADDRHINT + ip_output_hinted(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, + IP_PROTO_TCP, &(pcb->addr_hint)); +#else /* LWIP_NETIF_HWADDRHINT*/ + ip_output(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, + IP_PROTO_TCP); +#endif /* LWIP_NETIF_HWADDRHINT*/ + pbuf_free(p); + + return ERR_OK; +} + +/** + * Find out what we can send and send it + * + * @param pcb Protocol control block for the TCP connection to send data + * @return ERR_OK if data has been sent or nothing to send + * another err_t on error + */ +err_t +tcp_output(struct tcp_pcb *pcb) +{ + struct tcp_seg *seg, *useg; + u32_t wnd, snd_nxt; +#if TCP_CWND_DEBUG + s16_t i = 0; +#endif /* TCP_CWND_DEBUG */ + + /* First, check if we are invoked by the TCP input processing + code. If so, we do not output anything. Instead, we rely on the + input processing code to call us when input processing is done + with. */ + if (tcp_input_pcb == pcb) { + return ERR_OK; + } + + wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd); + + seg = pcb->unsent; + + /* If the TF_ACK_NOW flag is set and no data will be sent (either + * because the ->unsent queue is empty or because the window does + * not allow it), construct an empty ACK segment and send it. + * + * If data is to be sent, we will just piggyback the ACK (see below). + */ + if (pcb->flags & TF_ACK_NOW && + (seg == NULL || + ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd)) { + return tcp_send_empty_ack(pcb); + } + + /* useg should point to last segment on unacked queue */ + useg = pcb->unacked; + if (useg != NULL) { + for (; useg->next != NULL; useg = useg->next); + } + +#if TCP_OUTPUT_DEBUG + if (seg == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n", + (void*)pcb->unsent)); + } +#endif /* TCP_OUTPUT_DEBUG */ +#if TCP_CWND_DEBUG + if (seg == NULL) { + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U16_F + ", cwnd %"U16_F", wnd %"U32_F + ", seg == NULL, ack %"U32_F"\n", + pcb->snd_wnd, pcb->cwnd, wnd, pcb->lastack)); + } else { + LWIP_DEBUGF(TCP_CWND_DEBUG, + ("tcp_output: snd_wnd %"U16_F", cwnd %"U16_F", wnd %"U32_F + ", effwnd %"U32_F", seq %"U32_F", ack %"U32_F"\n", + pcb->snd_wnd, pcb->cwnd, wnd, + ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len, + ntohl(seg->tcphdr->seqno), pcb->lastack)); + } +#endif /* TCP_CWND_DEBUG */ + /* data available and window allows it to be sent? */ + while (seg != NULL && + ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) { + LWIP_ASSERT("RST not expected here!", + (TCPH_FLAGS(seg->tcphdr) & TCP_RST) == 0); + /* Stop sending if the nagle algorithm would prevent it + * Don't stop: + * - if tcp_enqueue had a memory error before (prevent delayed ACK timeout) or + * - if FIN was already enqueued for this PCB (SYN is always alone in a segment - + * either seg->next != NULL or pcb->unacked == NULL; + * RST is no sent using tcp_enqueue/tcp_output. + */ + if((tcp_do_output_nagle(pcb) == 0) && + ((pcb->flags & (TF_NAGLEMEMERR | TF_FIN)) == 0)){ + break; + } +#if TCP_CWND_DEBUG + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U16_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F", i %"S16_F"\n", + pcb->snd_wnd, pcb->cwnd, wnd, + ntohl(seg->tcphdr->seqno) + seg->len - + pcb->lastack, + ntohl(seg->tcphdr->seqno), pcb->lastack, i)); + ++i; +#endif /* TCP_CWND_DEBUG */ + + pcb->unsent = seg->next; + + if (pcb->state != SYN_SENT) { + TCPH_SET_FLAG(seg->tcphdr, TCP_ACK); + pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); + } + + tcp_output_segment(seg, pcb); + snd_nxt = ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg); + if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) { + pcb->snd_nxt = snd_nxt; + } + /* put segment on unacknowledged list if length > 0 */ + if (TCP_TCPLEN(seg) > 0) { + seg->next = NULL; + /* unacked list is empty? */ + if (pcb->unacked == NULL) { + pcb->unacked = seg; + useg = seg; + /* unacked list is not empty? */ + } else { + /* In the case of fast retransmit, the packet should not go to the tail + * of the unacked queue, but rather somewhere before it. We need to check for + * this case. -STJ Jul 27, 2004 */ + if (TCP_SEQ_LT(ntohl(seg->tcphdr->seqno), ntohl(useg->tcphdr->seqno))){ + /* add segment to before tail of unacked list, keeping the list sorted */ + struct tcp_seg **cur_seg = &(pcb->unacked); + while (*cur_seg && + TCP_SEQ_LT(ntohl((*cur_seg)->tcphdr->seqno), ntohl(seg->tcphdr->seqno))) { + cur_seg = &((*cur_seg)->next ); + } + seg->next = (*cur_seg); + (*cur_seg) = seg; + } else { + /* add segment to tail of unacked list */ + useg->next = seg; + useg = useg->next; + } + } + /* do not queue empty segments on the unacked list */ + } else { + tcp_seg_free(seg); + } + seg = pcb->unsent; + } + + if (seg != NULL && pcb->persist_backoff == 0 && + ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > pcb->snd_wnd) { + /* prepare for persist timer */ + pcb->persist_cnt = 0; + pcb->persist_backoff = 1; + } + + pcb->flags &= ~TF_NAGLEMEMERR; + return ERR_OK; +} + +/** + * Called by tcp_output() to actually send a TCP segment over IP. + * + * @param seg the tcp_seg to send + * @param pcb the tcp_pcb for the TCP connection used to send the segment + */ +static void +tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb) +{ + u16_t len; + struct netif *netif; + u32_t *opts; + + /** @bug Exclude retransmitted segments from this count. */ + snmp_inc_tcpoutsegs(); + + /* The TCP header has already been constructed, but the ackno and + wnd fields remain. */ + seg->tcphdr->ackno = htonl(pcb->rcv_nxt); + + /* advertise our receive window size in this TCP segment */ + seg->tcphdr->wnd = htons(pcb->rcv_ann_wnd); + + pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd; + + /* Add any requested options. NB MSS option is only set on SYN + packets, so ignore it here */ + opts = (u32_t *)(seg->tcphdr + 1); + if (seg->flags & TF_SEG_OPTS_MSS) { + TCP_BUILD_MSS_OPTION(*opts); + opts += 1; + } +#if LWIP_TCP_TIMESTAMPS + pcb->ts_lastacksent = pcb->rcv_nxt; + + if (seg->flags & TF_SEG_OPTS_TS) { + tcp_build_timestamp_option(pcb, opts); + opts += 3; + } +#endif + +#ifdef _TEST_HD_ + /* ANGR: set rtime this _before_ checking ip_route(). Otherwise TCP_SYN will + * not be retransmitted in case the interface was down and tcp_connect() + * will not return any error. Since we still want the err_cb() (or maybe + * the wifi link comes up), make sure that we fulfill the retransmissions in + * tcp_slowtmr() + */ + + /* Set retransmission timer running if it is not currently enabled */ + if(pcb->rtime == -1) + pcb->rtime = 0; +#endif + + /* If we don't have a local IP address, we get one by + calling ip_route(). */ + if (ip_addr_isany(&(pcb->local_ip))) { + netif = ip_route(&(pcb->remote_ip)); + if (netif == NULL) { + return; + } + ip_addr_set(&(pcb->local_ip), &(netif->ip_addr)); + } + +#ifndef _TEST_HD_ + //Set retransmission timer running if it is not currently enabled + if(pcb->rtime == -1) + pcb->rtime = 0; +#endif + + if (pcb->rttest == 0) { + pcb->rttest = tcp_ticks; + pcb->rtseq = ntohl(seg->tcphdr->seqno); + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %"U32_F"\n", pcb->rtseq)); + } + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n", + htonl(seg->tcphdr->seqno), htonl(seg->tcphdr->seqno) + + seg->len)); + + len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload); + + seg->p->len -= len; + seg->p->tot_len -= len; + + seg->p->payload = seg->tcphdr; + + seg->tcphdr->chksum = 0; +#if CHECKSUM_GEN_TCP + seg->tcphdr->chksum = inet_chksum_pseudo(seg->p, + &(pcb->local_ip), + &(pcb->remote_ip), + IP_PROTO_TCP, seg->p->tot_len); +#endif + TCP_STATS_INC(tcp.xmit); + +#if LWIP_NETIF_HWADDRHINT + ip_output_hinted(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, + IP_PROTO_TCP, &(pcb->addr_hint)); +#else /* LWIP_NETIF_HWADDRHINT*/ + ip_output(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, + IP_PROTO_TCP); +#endif /* LWIP_NETIF_HWADDRHINT*/ +} + +/** + * Send a TCP RESET packet (empty segment with RST flag set) either to + * abort a connection or to show that there is no matching local connection + * for a received segment. + * + * Called by tcp_abort() (to abort a local connection), tcp_input() (if no + * matching local pcb was found), tcp_listen_input() (if incoming segment + * has ACK flag set) and tcp_process() (received segment in the wrong state) + * + * Since a RST segment is in most cases not sent for an active connection, + * tcp_rst() has a number of arguments that are taken from a tcp_pcb for + * most other segment output functions. + * + * @param seqno the sequence number to use for the outgoing segment + * @param ackno the acknowledge number to use for the outgoing segment + * @param local_ip the local IP address to send the segment from + * @param remote_ip the remote IP address to send the segment to + * @param local_port the local TCP port to send the segment from + * @param remote_port the remote TCP port to send the segment to + */ +void +tcp_rst(u32_t seqno, u32_t ackno, + struct ip_addr *local_ip, struct ip_addr *remote_ip, + u16_t local_port, u16_t remote_port) +{ + struct pbuf *p; + struct tcp_hdr *tcphdr; + p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); + if (p == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n")); + return; + } + LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr", + (p->len >= sizeof(struct tcp_hdr))); + + tcphdr = p->payload; + tcphdr->src = htons(local_port); + tcphdr->dest = htons(remote_port); + tcphdr->seqno = htonl(seqno); + tcphdr->ackno = htonl(ackno); + TCPH_FLAGS_SET(tcphdr, TCP_RST | TCP_ACK); + tcphdr->wnd = htons(TCP_WND); + tcphdr->urgp = 0; + TCPH_HDRLEN_SET(tcphdr, 5); + + tcphdr->chksum = 0; +#if CHECKSUM_GEN_TCP + tcphdr->chksum = inet_chksum_pseudo(p, local_ip, remote_ip, + IP_PROTO_TCP, p->tot_len); +#endif + TCP_STATS_INC(tcp.xmit); + snmp_inc_tcpoutrsts(); + /* Send output with hardcoded TTL since we have no access to the pcb */ + ip_output(p, local_ip, remote_ip, TCP_TTL, 0, IP_PROTO_TCP); + pbuf_free(p); + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno)); +} + +/** + * Requeue all unacked segments for retransmission + * + * Called by tcp_slowtmr() for slow retransmission. + * + * @param pcb the tcp_pcb for which to re-enqueue all unacked segments + */ +void +tcp_rexmit_rto(struct tcp_pcb *pcb) +{ + struct tcp_seg *seg; + + if (pcb->unacked == NULL) { + return; + } + + /* Move all unacked segments to the head of the unsent queue */ + for (seg = pcb->unacked; seg->next != NULL; seg = seg->next); + /* concatenate unsent queue after unacked queue */ + seg->next = pcb->unsent; + /* unsent queue is the concatenated queue (of unacked, unsent) */ + pcb->unsent = pcb->unacked; + /* unacked queue is now empty */ + pcb->unacked = NULL; + + /* increment number of retransmissions */ + ++pcb->nrtx; + + /* Don't take any RTT measurements after retransmitting. */ + pcb->rttest = 0; + + /* Do the actual retransmission */ + tcp_output(pcb); +} + +/** + * Requeue the first unacked segment for retransmission + * + * Called by tcp_receive() for fast retramsmit. + * + * @param pcb the tcp_pcb for which to retransmit the first unacked segment + */ +void +tcp_rexmit(struct tcp_pcb *pcb) +{ + struct tcp_seg *seg; + struct tcp_seg **cur_seg; + + if (pcb->unacked == NULL) { + return; + } + + /* Move the first unacked segment to the unsent queue */ + /* Keep the unsent queue sorted. */ + seg = pcb->unacked; + pcb->unacked = seg->next; + + cur_seg = &(pcb->unsent); + while (*cur_seg && + TCP_SEQ_LT(ntohl((*cur_seg)->tcphdr->seqno), ntohl(seg->tcphdr->seqno))) { + cur_seg = &((*cur_seg)->next ); + } + seg->next = *cur_seg; + *cur_seg = seg; + + ++pcb->nrtx; + + /* Don't take any rtt measurements after retransmitting. */ + pcb->rttest = 0; + + /* Do the actual retransmission. */ + snmp_inc_tcpretranssegs(); + /* No need to call tcp_output: we are always called from tcp_input() + and thus tcp_output directly returns. */ +} + + +/** + * Handle retransmission after three dupacks received + * + * @param pcb the tcp_pcb for which to retransmit the first unacked segment + */ +void +tcp_rexmit_fast(struct tcp_pcb *pcb) +{ + if (pcb->unacked != NULL && !(pcb->flags & TF_INFR)) { + /* This is fast retransmit. Retransmit the first unacked segment. */ + LWIP_DEBUGF(TCP_FR_DEBUG, + ("tcp_receive: dupacks %"U16_F" (%"U32_F + "), fast retransmit %"U32_F"\n", + (u16_t)pcb->dupacks, pcb->lastack, + ntohl(pcb->unacked->tcphdr->seqno))); + tcp_rexmit(pcb); + + /* Set ssthresh to half of the minimum of the current + * cwnd and the advertised window */ + if (pcb->cwnd > pcb->snd_wnd) + pcb->ssthresh = pcb->snd_wnd / 2; + else + pcb->ssthresh = pcb->cwnd / 2; + + /* The minimum value for ssthresh should be 2 MSS */ + if (pcb->ssthresh < 2*pcb->mss) { + LWIP_DEBUGF(TCP_FR_DEBUG, + ("tcp_receive: The minimum value for ssthresh %"U16_F + " should be min 2 mss %"U16_F"...\n", + pcb->ssthresh, 2*pcb->mss)); + pcb->ssthresh = 2*pcb->mss; + } + + pcb->cwnd = pcb->ssthresh + 3 * pcb->mss; + pcb->flags |= TF_INFR; + } +} + + +/** + * Send keepalive packets to keep a connection active although + * no data is sent over it. + * + * Called by tcp_slowtmr() + * + * @param pcb the tcp_pcb for which to send a keepalive packet + */ +void +tcp_keepalive(struct tcp_pcb *pcb) +{ + struct pbuf *p; + struct tcp_hdr *tcphdr; + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), + ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip))); + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F" pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", + tcp_ticks, pcb->tmr, pcb->keep_cnt_sent)); + + p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); + + if(p == NULL) { + LWIP_DEBUGF(TCP_DEBUG, + ("tcp_keepalive: could not allocate memory for pbuf\n")); + return; + } + LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr", + (p->len >= sizeof(struct tcp_hdr))); + + tcphdr = tcp_output_set_header(pcb, p, 0, htonl(pcb->snd_nxt - 1)); + +#if CHECKSUM_GEN_TCP + tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip, + IP_PROTO_TCP, p->tot_len); +#endif + TCP_STATS_INC(tcp.xmit); + + /* Send output to IP */ +#if LWIP_NETIF_HWADDRHINT + ip_output_hinted(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP, + &(pcb->addr_hint)); +#else /* LWIP_NETIF_HWADDRHINT*/ + ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP); +#endif /* LWIP_NETIF_HWADDRHINT*/ + + pbuf_free(p); + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F".\n", + pcb->snd_nxt - 1, pcb->rcv_nxt)); +} + + +/** + * Send persist timer zero-window probes to keep a connection active + * when a window update is lost. + * + * Called by tcp_slowtmr() + * + * @param pcb the tcp_pcb for which to send a zero-window probe packet + */ +void +tcp_zero_window_probe(struct tcp_pcb *pcb) +{ + struct pbuf *p; + struct tcp_hdr *tcphdr; + struct tcp_seg *seg; + u16_t len; + u8_t is_fin; + + LWIP_DEBUGF(TCP_DEBUG, + ("tcp_zero_window_probe: sending ZERO WINDOW probe to %" + U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), + ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip))); + + LWIP_DEBUGF(TCP_DEBUG, + ("tcp_zero_window_probe: tcp_ticks %"U32_F + " pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", + tcp_ticks, pcb->tmr, pcb->keep_cnt_sent)); + + seg = pcb->unacked; + + if(seg == NULL) + seg = pcb->unsent; + + if(seg == NULL) + return; + + is_fin = ((TCPH_FLAGS(seg->tcphdr) & TCP_FIN) != 0) && (seg->len == 0); + len = is_fin ? TCP_HLEN : TCP_HLEN + 1; + + p = pbuf_alloc(PBUF_IP, len, PBUF_RAM); + if(p == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: no memory for pbuf\n")); + return; + } + LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr", + (p->len >= sizeof(struct tcp_hdr))); + + tcphdr = tcp_output_set_header(pcb, p, 0, seg->tcphdr->seqno); + + if (is_fin) { + /* FIN segment, no data */ + TCPH_FLAGS_SET(tcphdr, TCP_ACK | TCP_FIN); + } else { + /* Data segment, copy in one byte from the head of the unacked queue */ + *((char *)p->payload + sizeof(struct tcp_hdr)) = *(char *)seg->dataptr; + } + +#if CHECKSUM_GEN_TCP + tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip, + IP_PROTO_TCP, p->tot_len); +#endif + TCP_STATS_INC(tcp.xmit); + + /* Send output to IP */ +#if LWIP_NETIF_HWADDRHINT + ip_output_hinted(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP, + &(pcb->addr_hint)); +#else /* LWIP_NETIF_HWADDRHINT*/ + ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP); +#endif /* LWIP_NETIF_HWADDRHINT*/ + + pbuf_free(p); + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: seqno %"U32_F + " ackno %"U32_F".\n", + pcb->snd_nxt - 1, pcb->rcv_nxt)); +} +#endif /* LWIP_TCP */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/udp.c b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/udp.c new file mode 100644 index 0000000000000000000000000000000000000000..697ca7ce34dcbf9504f6dbb1170da44e8679eb56 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/core/udp.c @@ -0,0 +1,843 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/** + * @file + * User Datagram Protocol module + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + + +/* udp.c + * + * The code for the User Datagram Protocol UDP & UDPLite (RFC 3828). + * + */ + +/* @todo Check the use of '(struct udp_pcb).chksum_len_rx'! + */ + +#include "lwip/opt.h" + +#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/udp.h" +#include "lwip/def.h" +#include "lwip/memp.h" +#include "lwip/inet.h" +#include "lwip/inet_chksum.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/icmp.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" +#include "arch/perf.h" +#include "lwip/dhcp.h" + +#include + +/* The list of UDP PCBs */ +/* exported in udp.h (was static) */ +struct udp_pcb *udp_pcbs; + +/** + * Process an incoming UDP datagram. + * + * Given an incoming UDP datagram (as a chain of pbufs) this function + * finds a corresponding UDP PCB and hands over the pbuf to the pcbs + * recv function. If no pcb is found or the datagram is incorrect, the + * pbuf is freed. + * + * @param p pbuf to be demultiplexed to a UDP PCB. + * @param inp network interface on which the datagram was received. + * + */ +void +udp_input(struct pbuf *p, struct netif *inp) +{ + struct udp_hdr *udphdr; + struct udp_pcb *pcb, *prev; + struct udp_pcb *uncon_pcb; + struct ip_hdr *iphdr; + u16_t src, dest; + u8_t local_match; + u8_t broadcast; + + PERF_START; + + UDP_STATS_INC(udp.recv); + + iphdr = p->payload; + + /* Check minimum length (IP header + UDP header) + * and move payload pointer to UDP header */ + if (p->tot_len < (IPH_HL(iphdr) * 4 + UDP_HLEN) || pbuf_header(p, -(s16_t)(IPH_HL(iphdr) * 4))) { + /* drop short packets */ + LWIP_DEBUGF(UDP_DEBUG, + ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len)); + UDP_STATS_INC(udp.lenerr); + UDP_STATS_INC(udp.drop); + snmp_inc_udpinerrors(); + pbuf_free(p); + goto end; + } + + udphdr = (struct udp_hdr *)p->payload; + + /* is broadcast packet ? */ + broadcast = ip_addr_isbroadcast(&(iphdr->dest), inp); + + LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len)); + + /* convert src and dest ports to host byte order */ + src = ntohs(udphdr->src); + dest = ntohs(udphdr->dest); + + udp_debug_print(udphdr); + + /* print the UDP source and destination */ + LWIP_DEBUGF(UDP_DEBUG, + ("udp (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") <-- " + "(%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n", + ip4_addr1(&iphdr->dest), ip4_addr2(&iphdr->dest), + ip4_addr3(&iphdr->dest), ip4_addr4(&iphdr->dest), ntohs(udphdr->dest), + ip4_addr1(&iphdr->src), ip4_addr2(&iphdr->src), + ip4_addr3(&iphdr->src), ip4_addr4(&iphdr->src), ntohs(udphdr->src))); + +#if LWIP_DHCP + pcb = NULL; + /* when LWIP_DHCP is active, packets to DHCP_CLIENT_PORT may only be processed by + the dhcp module, no other UDP pcb may use the local UDP port DHCP_CLIENT_PORT */ + if (dest == DHCP_CLIENT_PORT) { + /* all packets for DHCP_CLIENT_PORT not coming from DHCP_SERVER_PORT are dropped! */ + if (src == DHCP_SERVER_PORT) { + if ((inp->dhcp != NULL) && (inp->dhcp->pcb != NULL)) { + /* accept the packe if + (- broadcast or directed to us) -> DHCP is link-layer-addressed, local ip is always ANY! + - inp->dhcp->pcb->remote == ANY or iphdr->src */ + if ((ip_addr_isany(&inp->dhcp->pcb->remote_ip) || + ip_addr_cmp(&(inp->dhcp->pcb->remote_ip), &(iphdr->src)))) { + pcb = inp->dhcp->pcb; + } + } + } + } else +#endif /* LWIP_DHCP */ + { + prev = NULL; + local_match = 0; + uncon_pcb = NULL; + /* Iterate through the UDP pcb list for a matching pcb. + * 'Perfect match' pcbs (connected to the remote port & ip address) are + * preferred. If no perfect match is found, the first unconnected pcb that + * matches the local port and ip address gets the datagram. */ + for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { + local_match = 0; + /* print the PCB local and remote address */ + LWIP_DEBUGF(UDP_DEBUG, + ("pcb (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") --- " + "(%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n", + ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip), + ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port, + ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), + ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port)); + + /* compare PCB local addr+port to UDP destination addr+port */ + if ((pcb->local_port == dest) && + ((!broadcast && ip_addr_isany(&pcb->local_ip)) || + ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)) || +#if LWIP_IGMP + ip_addr_ismulticast(&(iphdr->dest)) || +#endif /* LWIP_IGMP */ +#if IP_SOF_BROADCAST_RECV + (broadcast && (pcb->so_options & SOF_BROADCAST)))) { +#else /* IP_SOF_BROADCAST_RECV */ + (broadcast))) { +#endif /* IP_SOF_BROADCAST_RECV */ + local_match = 1; + if ((uncon_pcb == NULL) && + ((pcb->flags & UDP_FLAGS_CONNECTED) == 0)) { + /* the first unconnected matching PCB */ + uncon_pcb = pcb; + } + } + /* compare PCB remote addr+port to UDP source addr+port */ + if ((local_match != 0) && + (pcb->remote_port == src) && + (ip_addr_isany(&pcb->remote_ip) || + ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)))) { + /* the first fully matching PCB */ + if (prev != NULL) { + /* move the pcb to the front of udp_pcbs so that is + found faster next time */ + prev->next = pcb->next; + pcb->next = udp_pcbs; + udp_pcbs = pcb; + } else { + UDP_STATS_INC(udp.cachehit); + } + break; + } + prev = pcb; + } + /* no fully matching pcb found? then look for an unconnected pcb */ + if (pcb == NULL) { + pcb = uncon_pcb; + } + } + + /* Check checksum if this is a match or if it was directed at us. */ + if (pcb != NULL || ip_addr_cmp(&inp->ip_addr, &iphdr->dest)) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_input: calculating checksum\n")); +#if LWIP_UDPLITE + if (IPH_PROTO(iphdr) == IP_PROTO_UDPLITE) { + /* Do the UDP Lite checksum */ +#if CHECKSUM_CHECK_UDP + u16_t chklen = ntohs(udphdr->len); + if (chklen < sizeof(struct udp_hdr)) { + if (chklen == 0) { + /* For UDP-Lite, checksum length of 0 means checksum + over the complete packet (See RFC 3828 chap. 3.1) */ + chklen = p->tot_len; + } else { + /* At least the UDP-Lite header must be covered by the + checksum! (Again, see RFC 3828 chap. 3.1) */ + UDP_STATS_INC(udp.chkerr); + UDP_STATS_INC(udp.drop); + snmp_inc_udpinerrors(); + pbuf_free(p); + goto end; + } + } + if (inet_chksum_pseudo_partial(p, (struct ip_addr *)&(iphdr->src), + (struct ip_addr *)&(iphdr->dest), + IP_PROTO_UDPLITE, p->tot_len, chklen) != 0) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("udp_input: UDP Lite datagram discarded due to failing checksum\n")); + UDP_STATS_INC(udp.chkerr); + UDP_STATS_INC(udp.drop); + snmp_inc_udpinerrors(); + pbuf_free(p); + goto end; + } +#endif /* CHECKSUM_CHECK_UDP */ + } else +#endif /* LWIP_UDPLITE */ + { +#if CHECKSUM_CHECK_UDP + if (udphdr->chksum != 0) { + if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), + (struct ip_addr *)&(iphdr->dest), + IP_PROTO_UDP, p->tot_len) != 0) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("udp_input: UDP datagram discarded due to failing checksum\n")); + UDP_STATS_INC(udp.chkerr); + UDP_STATS_INC(udp.drop); + snmp_inc_udpinerrors(); + pbuf_free(p); + goto end; + } + } +#endif /* CHECKSUM_CHECK_UDP */ + } + if(pbuf_header(p, -UDP_HLEN)) { + /* Can we cope with this failing? Just assert for now */ + LWIP_ASSERT("pbuf_header failed\n", 0); + UDP_STATS_INC(udp.drop); + snmp_inc_udpinerrors(); + pbuf_free(p); + goto end; + } + if (pcb != NULL) { + snmp_inc_udpindatagrams(); + /* callback */ + if (pcb->recv != NULL) { + /* now the recv function is responsible for freeing p */ + pcb->recv(pcb->recv_arg, pcb, p, &iphdr->src, src); + } else { + /* no recv function registered? then we have to free the pbuf! */ + pbuf_free(p); + goto end; + } + } else { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_input: not for us.\n")); + +#if LWIP_ICMP + /* No match was found, send ICMP destination port unreachable unless + destination address was broadcast/multicast. */ + if (!broadcast && + !ip_addr_ismulticast(&iphdr->dest)) { + /* move payload pointer back to ip header */ + pbuf_header(p, (IPH_HL(iphdr) * 4) + UDP_HLEN); + LWIP_ASSERT("p->payload == iphdr", (p->payload == iphdr)); + icmp_dest_unreach(p, ICMP_DUR_PORT); + } +#endif /* LWIP_ICMP */ + UDP_STATS_INC(udp.proterr); + UDP_STATS_INC(udp.drop); + snmp_inc_udpnoports(); + pbuf_free(p); + } + } else { + pbuf_free(p); + } +end: + PERF_STOP("udp_input"); +} + +/** + * Send data using UDP. + * + * @param pcb UDP PCB used to send the data. + * @param p chain of pbuf's to be sent. + * + * The datagram will be sent to the current remote_ip & remote_port + * stored in pcb. If the pcb is not bound to a port, it will + * automatically be bound to a random port. + * + * @return lwIP error code. + * - ERR_OK. Successful. No error occured. + * - ERR_MEM. Out of memory. + * - ERR_RTE. Could not find route to destination address. + * - More errors could be returned by lower protocol layers. + * + * @see udp_disconnect() udp_sendto() + */ +err_t +udp_send(struct udp_pcb *pcb, struct pbuf *p) +{ + /* send to the packet using remote ip and port stored in the pcb */ + return udp_sendto(pcb, p, &pcb->remote_ip, pcb->remote_port); +} + +/** + * Send data to a specified address using UDP. + * + * @param pcb UDP PCB used to send the data. + * @param p chain of pbuf's to be sent. + * @param dst_ip Destination IP address. + * @param dst_port Destination UDP port. + * + * dst_ip & dst_port are expected to be in the same byte order as in the pcb. + * + * If the PCB already has a remote address association, it will + * be restored after the data is sent. + * + * @return lwIP error code (@see udp_send for possible error codes) + * + * @see udp_disconnect() udp_send() + */ +err_t +udp_sendto(struct udp_pcb *pcb, struct pbuf *p, + struct ip_addr *dst_ip, u16_t dst_port) +{ + struct netif *netif; + + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send\n")); + + /* find the outgoing network interface for this packet */ +#if LWIP_IGMP + netif = ip_route((ip_addr_ismulticast(dst_ip))?(&(pcb->multicast_ip)):(dst_ip)); +#else + netif = ip_route(dst_ip); +#endif /* LWIP_IGMP */ + + /* no outgoing network interface could be found? */ + if (netif == NULL) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: No route to 0x%"X32_F"\n", dst_ip->addr)); + UDP_STATS_INC(udp.rterr); + return ERR_RTE; + } + return udp_sendto_if(pcb, p, dst_ip, dst_port, netif); +} + +/** + * Send data to a specified address using UDP. + * The netif used for sending can be specified. + * + * This function exists mainly for DHCP, to be able to send UDP packets + * on a netif that is still down. + * + * @param pcb UDP PCB used to send the data. + * @param p chain of pbuf's to be sent. + * @param dst_ip Destination IP address. + * @param dst_port Destination UDP port. + * @param netif the netif used for sending. + * + * dst_ip & dst_port are expected to be in the same byte order as in the pcb. + * + * @return lwIP error code (@see udp_send for possible error codes) + * + * @see udp_disconnect() udp_send() + */ +err_t +udp_sendto_if(struct udp_pcb *pcb, struct pbuf *p, + struct ip_addr *dst_ip, u16_t dst_port, struct netif *netif) +{ + struct udp_hdr *udphdr; + struct ip_addr *src_ip; + err_t err; + struct pbuf *q; /* q will be sent down the stack */ + +#if IP_SOF_BROADCAST + /* broadcast filter? */ + if ( ((pcb->so_options & SOF_BROADCAST) == 0) && ip_addr_isbroadcast(dst_ip, netif) ) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("udp_sendto_if: SOF_BROADCAST not enabled on pcb %p\n", (void *)pcb)); + return ERR_VAL; + } +#endif /* IP_SOF_BROADCAST */ + + /* if the PCB is not yet bound to a port, bind it here */ + if (pcb->local_port == 0) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send: not yet bound to a port, binding now\n")); + err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); + if (err != ERR_OK) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: forced port bind failed\n")); + return err; + } + } + + /* not enough space to add an UDP header to first pbuf in given p chain? */ + if (pbuf_header(p, UDP_HLEN)) { + /* allocate header in a separate new pbuf */ + q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM); + /* new header pbuf could not be allocated? */ + if (q == NULL) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: could not allocate header\n")); + return ERR_MEM; + } + /* chain header q in front of given pbuf p */ + pbuf_chain(q, p); + /* first pbuf q points to header pbuf */ + LWIP_DEBUGF(UDP_DEBUG, + ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); + } else { + /* adding space for header within p succeeded */ + /* first pbuf q equals given pbuf */ + q = p; + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p)); + } + LWIP_ASSERT("check that first pbuf can hold struct udp_hdr", + (q->len >= sizeof(struct udp_hdr))); + /* q now represents the packet to be sent */ + udphdr = q->payload; + udphdr->src = htons(pcb->local_port); + udphdr->dest = htons(dst_port); + /* in UDP, 0 checksum means 'no checksum' */ + udphdr->chksum = 0x0000; + + /* PCB local address is IP_ANY_ADDR? */ + if (ip_addr_isany(&pcb->local_ip)) { + /* use outgoing network interface IP address as source address */ + src_ip = &(netif->ip_addr); + } else { + /* check if UDP PCB local IP address is correct + * this could be an old address if netif->ip_addr has changed */ + if (!ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) { + /* local_ip doesn't match, drop the packet */ + if (q != p) { + /* free the header pbuf */ + pbuf_free(q); + q = NULL; + /* p is still referenced by the caller, and will live on */ + } + return ERR_VAL; + } + /* use UDP PCB local IP address as source address */ + src_ip = &(pcb->local_ip); + } + + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %"U16_F"\n", q->tot_len)); + +#if LWIP_UDPLITE + /* UDP Lite protocol? */ + if (pcb->flags & UDP_FLAGS_UDPLITE) { + u16_t chklen, chklen_hdr; + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %"U16_F"\n", q->tot_len)); + /* set UDP message length in UDP header */ + chklen_hdr = chklen = pcb->chksum_len_tx; + if ((chklen < sizeof(struct udp_hdr)) || (chklen > q->tot_len)) { + if (chklen != 0) { + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE pcb->chksum_len is illegal: %"U16_F"\n", chklen)); + } + /* For UDP-Lite, checksum length of 0 means checksum + over the complete packet. (See RFC 3828 chap. 3.1) + At least the UDP-Lite header must be covered by the + checksum, therefore, if chksum_len has an illegal + value, we generate the checksum over the complete + packet to be safe. */ + chklen_hdr = 0; + chklen = q->tot_len; + } + udphdr->len = htons(chklen_hdr); + /* calculate checksum */ +#if CHECKSUM_GEN_UDP + udphdr->chksum = inet_chksum_pseudo_partial(q, src_ip, dst_ip, + IP_PROTO_UDPLITE, q->tot_len, chklen); + /* chksum zero must become 0xffff, as zero means 'no checksum' */ + if (udphdr->chksum == 0x0000) + udphdr->chksum = 0xffff; +#endif /* CHECKSUM_CHECK_UDP */ + /* output to IP */ + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDPLITE,)\n")); +#if LWIP_NETIF_HWADDRHINT + netif->addr_hint = &(pcb->addr_hint); +#endif /* LWIP_NETIF_HWADDRHINT*/ + err = ip_output_if(q, src_ip, dst_ip, pcb->ttl, pcb->tos, IP_PROTO_UDPLITE, netif); +#if LWIP_NETIF_HWADDRHINT + netif->addr_hint = NULL; +#endif /* LWIP_NETIF_HWADDRHINT*/ + } else +#endif /* LWIP_UDPLITE */ + { /* UDP */ + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len)); + udphdr->len = htons(q->tot_len); + /* calculate checksum */ +#if CHECKSUM_GEN_UDP + if ((pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) { + udphdr->chksum = inet_chksum_pseudo(q, src_ip, dst_ip, IP_PROTO_UDP, q->tot_len); + /* chksum zero must become 0xffff, as zero means 'no checksum' */ + if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff; + } +#endif /* CHECKSUM_CHECK_UDP */ + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum)); + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDP,)\n")); + /* output to IP */ +#if LWIP_NETIF_HWADDRHINT + netif->addr_hint = &(pcb->addr_hint); +#endif /* LWIP_NETIF_HWADDRHINT*/ + err = ip_output_if(q, src_ip, dst_ip, pcb->ttl, pcb->tos, IP_PROTO_UDP, netif); +#if LWIP_NETIF_HWADDRHINT + netif->addr_hint = NULL; +#endif /* LWIP_NETIF_HWADDRHINT*/ + } + /* TODO: must this be increased even if error occured? */ + snmp_inc_udpoutdatagrams(); + + /* did we chain a separate header pbuf earlier? */ + if (q != p) { + /* free the header pbuf */ + pbuf_free(q); + q = NULL; + /* p is still referenced by the caller, and will live on */ + } + + UDP_STATS_INC(udp.xmit); + return err; +} + +/** + * Bind an UDP PCB. + * + * @param pcb UDP PCB to be bound with a local address ipaddr and port. + * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to + * bind to all local interfaces. + * @param port local UDP port to bind with. Use 0 to automatically bind + * to a random port between UDP_LOCAL_PORT_RANGE_START and + * UDP_LOCAL_PORT_RANGE_END. + * + * ipaddr & port are expected to be in the same byte order as in the pcb. + * + * @return lwIP error code. + * - ERR_OK. Successful. No error occured. + * - ERR_USE. The specified ipaddr and port are already bound to by + * another UDP PCB. + * + * @see udp_disconnect() + */ +err_t +udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port) +{ + struct udp_pcb *ipcb; + u8_t rebind; + + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_bind(ipaddr = ")); + ip_addr_debug_print(UDP_DEBUG, ipaddr); + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, (", port = %"U16_F")\n", port)); + + rebind = 0; + /* Check for double bind and rebind of the same pcb */ + for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { + /* is this UDP PCB already on active list? */ + if (pcb == ipcb) { + /* pcb may occur at most once in active list */ + LWIP_ASSERT("rebind == 0", rebind == 0); + /* pcb already in list, just rebind */ + rebind = 1; + } + + /* this code does not allow upper layer to share a UDP port for + listening to broadcast or multicast traffic (See SO_REUSE_ADDR and + SO_REUSE_PORT under *BSD). TODO: See where it fits instead, OR + combine with implementation of UDP PCB flags. Leon Woestenberg. */ +#ifdef LWIP_UDP_TODO + /* port matches that of PCB in list? */ + else + if ((ipcb->local_port == port) && + /* IP address matches, or one is IP_ADDR_ANY? */ + (ip_addr_isany(&(ipcb->local_ip)) || + ip_addr_isany(ipaddr) || + ip_addr_cmp(&(ipcb->local_ip), ipaddr))) { + /* other PCB already binds to this local IP and port */ + LWIP_DEBUGF(UDP_DEBUG, + ("udp_bind: local port %"U16_F" already bound by another pcb\n", port)); + return ERR_USE; + } +#endif + } + + ip_addr_set(&pcb->local_ip, ipaddr); + + /* no port specified? */ + if (port == 0) { +#ifndef UDP_LOCAL_PORT_RANGE_START +#define UDP_LOCAL_PORT_RANGE_START 4096 +#define UDP_LOCAL_PORT_RANGE_END 0x7fff +#endif + port = UDP_LOCAL_PORT_RANGE_START; + ipcb = udp_pcbs; + while ((ipcb != NULL) && (port != UDP_LOCAL_PORT_RANGE_END)) { + if (ipcb->local_port == port) { + /* port is already used by another udp_pcb */ + port++; + /* restart scanning all udp pcbs */ + ipcb = udp_pcbs; + } else + /* go on with next udp pcb */ + ipcb = ipcb->next; + } + if (ipcb != NULL) { + /* no more ports available in local range */ + LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n")); + return ERR_USE; + } + } + pcb->local_port = port; + snmp_insert_udpidx_tree(pcb); + /* pcb not active yet? */ + if (rebind == 0) { + /* place the PCB on the active list if not already there */ + pcb->next = udp_pcbs; + udp_pcbs = pcb; + } + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("udp_bind: bound to %"U16_F".%"U16_F".%"U16_F".%"U16_F", port %"U16_F"\n", + (u16_t)((ntohl(pcb->local_ip.addr) >> 24) & 0xff), + (u16_t)((ntohl(pcb->local_ip.addr) >> 16) & 0xff), + (u16_t)((ntohl(pcb->local_ip.addr) >> 8) & 0xff), + (u16_t)(ntohl(pcb->local_ip.addr) & 0xff), pcb->local_port)); + return ERR_OK; +} +/** + * Connect an UDP PCB. + * + * This will associate the UDP PCB with the remote address. + * + * @param pcb UDP PCB to be connected with remote address ipaddr and port. + * @param ipaddr remote IP address to connect with. + * @param port remote UDP port to connect with. + * + * @return lwIP error code + * + * ipaddr & port are expected to be in the same byte order as in the pcb. + * + * The udp pcb is bound to a random local port if not already bound. + * + * @see udp_disconnect() + */ +err_t +udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port) +{ + struct udp_pcb *ipcb; + + if (pcb->local_port == 0) { + err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); + if (err != ERR_OK) + return err; + } + + ip_addr_set(&pcb->remote_ip, ipaddr); + pcb->remote_port = port; + pcb->flags |= UDP_FLAGS_CONNECTED; +/** TODO: this functionality belongs in upper layers */ +#ifdef LWIP_UDP_TODO + /* Nail down local IP for netconn_addr()/getsockname() */ + if (ip_addr_isany(&pcb->local_ip) && !ip_addr_isany(&pcb->remote_ip)) { + struct netif *netif; + + if ((netif = ip_route(&(pcb->remote_ip))) == NULL) { + LWIP_DEBUGF(UDP_DEBUG, ("udp_connect: No route to 0x%lx\n", pcb->remote_ip.addr)); + UDP_STATS_INC(udp.rterr); + return ERR_RTE; + } + /** TODO: this will bind the udp pcb locally, to the interface which + is used to route output packets to the remote address. However, we + might want to accept incoming packets on any interface! */ + pcb->local_ip = netif->ip_addr; + } else if (ip_addr_isany(&pcb->remote_ip)) { + pcb->local_ip.addr = 0; + } +#endif + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("udp_connect: connected to %"U16_F".%"U16_F".%"U16_F".%"U16_F",port %"U16_F"\n", + (u16_t)((ntohl(pcb->remote_ip.addr) >> 24) & 0xff), + (u16_t)((ntohl(pcb->remote_ip.addr) >> 16) & 0xff), + (u16_t)((ntohl(pcb->remote_ip.addr) >> 8) & 0xff), + (u16_t)(ntohl(pcb->remote_ip.addr) & 0xff), pcb->remote_port)); + + /* Insert UDP PCB into the list of active UDP PCBs. */ + for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { + if (pcb == ipcb) { + /* already on the list, just return */ + return ERR_OK; + } + } + /* PCB not yet on the list, add PCB now */ + pcb->next = udp_pcbs; + udp_pcbs = pcb; + return ERR_OK; +} + +/** + * Disconnect a UDP PCB + * + * @param pcb the udp pcb to disconnect. + */ +void +udp_disconnect(struct udp_pcb *pcb) +{ + /* reset remote address association */ + ip_addr_set(&pcb->remote_ip, IP_ADDR_ANY); + pcb->remote_port = 0; + /* mark PCB as unconnected */ + pcb->flags &= ~UDP_FLAGS_CONNECTED; +} + +/** + * Set a receive callback for a UDP PCB + * + * This callback will be called when receiving a datagram for the pcb. + * + * @param pcb the pcb for wich to set the recv callback + * @param recv function pointer of the callback function + * @param recv_arg additional argument to pass to the callback function + */ +void +udp_recv(struct udp_pcb *pcb, + void (* recv)(void *arg, struct udp_pcb *upcb, struct pbuf *p, + struct ip_addr *addr, u16_t port), + void *recv_arg) +{ + /* remember recv() callback and user data */ + pcb->recv = recv; + pcb->recv_arg = recv_arg; +} + +/** + * Remove an UDP PCB. + * + * @param pcb UDP PCB to be removed. The PCB is removed from the list of + * UDP PCB's and the data structure is freed from memory. + * + * @see udp_new() + */ +void +udp_remove(struct udp_pcb *pcb) +{ + struct udp_pcb *pcb2; + + snmp_delete_udpidx_tree(pcb); + /* pcb to be removed is first in list? */ + if (udp_pcbs == pcb) { + /* make list start at 2nd pcb */ + udp_pcbs = udp_pcbs->next; + /* pcb not 1st in list */ + } else + for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { + /* find pcb in udp_pcbs list */ + if (pcb2->next != NULL && pcb2->next == pcb) { + /* remove pcb from list */ + pcb2->next = pcb->next; + } + } + memp_free(MEMP_UDP_PCB, pcb); +} + +/** + * Create a UDP PCB. + * + * @return The UDP PCB which was created. NULL if the PCB data structure + * could not be allocated. + * + * @see udp_remove() + */ +struct udp_pcb * +udp_new(void) +{ + struct udp_pcb *pcb; + pcb = memp_malloc(MEMP_UDP_PCB); + /* could allocate UDP PCB? */ + if (pcb != NULL) { + /* UDP Lite: by initializing to all zeroes, chksum_len is set to 0 + * which means checksum is generated over the whole datagram per default + * (recommended as default by RFC 3828). */ + /* initialize PCB to all zeroes */ + memset(pcb, 0, sizeof(struct udp_pcb)); + pcb->ttl = UDP_TTL; + } + return pcb; +} + +#if UDP_DEBUG +/** + * Print UDP header information for debug purposes. + * + * @param udphdr pointer to the udp header in memory. + */ +void +udp_debug_print(struct udp_hdr *udphdr) +{ + LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n")); + LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", + ntohs(udphdr->src), ntohs(udphdr->dest))); + LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | 0x%04"X16_F" | (len, chksum)\n", + ntohs(udphdr->len), ntohs(udphdr->chksum))); + LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); +} +#endif /* UDP_DEBUG */ + +#endif /* LWIP_UDP */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/autoip.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/autoip.h new file mode 100644 index 0000000000000000000000000000000000000000..d5464b709578cfafeadc4f79c66dbb673373a02b --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/autoip.h @@ -0,0 +1,118 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/** + * @file + * + * AutoIP Automatic LinkLocal IP Configuration + */ + +/* + * + * Copyright (c) 2007 Dominik Spies + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Dominik Spies + * + * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform + * with RFC 3927. + * + * + * Please coordinate changes and requests with Dominik Spies + * + */ + +#ifndef __LWIP_AUTOIP_H__ +#define __LWIP_AUTOIP_H__ + +#include "lwip/opt.h" + +#if LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/netif.h" +#include "lwip/udp.h" +#include "netif/etharp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* AutoIP Timing */ +#define AUTOIP_TMR_INTERVAL 100 +#define AUTOIP_TICKS_PER_SECOND (1000 / AUTOIP_TMR_INTERVAL) + +/* RFC 3927 Constants */ +#define PROBE_WAIT 1 /* second (initial random delay) */ +#define PROBE_MIN 1 /* second (minimum delay till repeated probe) */ +#define PROBE_MAX 2 /* seconds (maximum delay till repeated probe) */ +#define PROBE_NUM 3 /* (number of probe packets) */ +#define ANNOUNCE_NUM 2 /* (number of announcement packets) */ +#define ANNOUNCE_INTERVAL 2 /* seconds (time between announcement packets) */ +#define ANNOUNCE_WAIT 2 /* seconds (delay before announcing) */ +#define MAX_CONFLICTS 10 /* (max conflicts before rate limiting) */ +#define RATE_LIMIT_INTERVAL 60 /* seconds (delay between successive attempts) */ +#define DEFEND_INTERVAL 10 /* seconds (min. wait between defensive ARPs) */ + +/* AutoIP client states */ +#define AUTOIP_STATE_OFF 0 +#define AUTOIP_STATE_PROBING 1 +#define AUTOIP_STATE_ANNOUNCING 2 +#define AUTOIP_STATE_BOUND 3 + +struct autoip +{ + struct ip_addr llipaddr; /* the currently selected, probed, announced or used LL IP-Address */ + u8_t state; /* current AutoIP state machine state */ + u8_t sent_num; /* sent number of probes or announces, dependent on state */ + u16_t ttw; /* ticks to wait, tick is AUTOIP_TMR_INTERVAL long */ + u8_t lastconflict; /* ticks until a conflict can be solved by defending */ + u8_t tried_llipaddr; /* total number of probed/used Link Local IP-Addresses */ +}; + + +/** Init srand, has to be called before entering mainloop */ +void autoip_init(void); + +/** Start AutoIP client */ +err_t autoip_start(struct netif *netif); + +/** Stop AutoIP client */ +err_t autoip_stop(struct netif *netif); + +/** Handles every incoming ARP Packet, called by etharp_arp_input */ +void autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr); + +/** Has to be called in loop every AUTOIP_TMR_INTERVAL milliseconds */ +void autoip_tmr(void); + +/** Handle a possible change in the network configuration */ +void autoip_network_changed(struct netif *netif); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_AUTOIP */ + +#endif /* __LWIP_AUTOIP_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/icmp.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/icmp.h new file mode 100644 index 0000000000000000000000000000000000000000..3f917ba0409b6ab4122c64ae13a54ad27336ed22 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/icmp.h @@ -0,0 +1,113 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_ICMP_H__ +#define __LWIP_ICMP_H__ + +#include "lwip/opt.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ICMP_ER 0 /* echo reply */ +#define ICMP_DUR 3 /* destination unreachable */ +#define ICMP_SQ 4 /* source quench */ +#define ICMP_RD 5 /* redirect */ +#define ICMP_ECHO 8 /* echo */ +#define ICMP_TE 11 /* time exceeded */ +#define ICMP_PP 12 /* parameter problem */ +#define ICMP_TS 13 /* timestamp */ +#define ICMP_TSR 14 /* timestamp reply */ +#define ICMP_IRQ 15 /* information request */ +#define ICMP_IR 16 /* information reply */ + +enum icmp_dur_type { + ICMP_DUR_NET = 0, /* net unreachable */ + ICMP_DUR_HOST = 1, /* host unreachable */ + ICMP_DUR_PROTO = 2, /* protocol unreachable */ + ICMP_DUR_PORT = 3, /* port unreachable */ + ICMP_DUR_FRAG = 4, /* fragmentation needed and DF set */ + ICMP_DUR_SR = 5 /* source route failed */ +}; + +enum icmp_te_type { + ICMP_TE_TTL = 0, /* time to live exceeded in transit */ + ICMP_TE_FRAG = 1 /* fragment reassembly time exceeded */ +}; + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +/** This is the standard ICMP header only that the u32_t data + * is splitted to two u16_t like ICMP echo needs it. + * This header is also used for other ICMP types that do not + * use the data part. + */ +PACK_STRUCT_BEGIN +struct icmp_echo_hdr { + PACK_STRUCT_FIELD(u8_t type); + PACK_STRUCT_FIELD(u8_t code); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u16_t id); + PACK_STRUCT_FIELD(u16_t seqno); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define ICMPH_TYPE(hdr) ((hdr)->type) +#define ICMPH_CODE(hdr) ((hdr)->code) + +/** Combines type and code to an u16_t */ +#define ICMPH_TYPE_SET(hdr, t) ((hdr)->type = (t)) +#define ICMPH_CODE_SET(hdr, c) ((hdr)->code = (c)) + + +#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */ + +void icmp_input(struct pbuf *p, struct netif *inp); +void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t); +void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t); + +#endif /* LWIP_ICMP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_ICMP_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/igmp.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/igmp.h new file mode 100644 index 0000000000000000000000000000000000000000..da67e7508a2d24d96bb011766fc274adc642430d --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/igmp.h @@ -0,0 +1,164 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2002 CITEL Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS'' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is a contribution to the lwIP TCP/IP stack. + * The Swedish Institute of Computer Science and Adam Dunkels + * are specifically granted permission to redistribute this + * source code. +*/ + +#ifndef __LWIP_IGMP_H__ +#define __LWIP_IGMP_H__ + +#include "lwip/opt.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/pbuf.h" + +#if LWIP_IGMP /* don't build if not configured for use in lwipopts.h */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * IGMP constants + */ +#define IP_PROTO_IGMP 2 +#define IGMP_TTL 1 +#define IGMP_MINLEN 8 +#define ROUTER_ALERT 0x9404 +#define ROUTER_ALERTLEN 4 + +/* + * IGMP message types, including version number. + */ +#define IGMP_MEMB_QUERY 0x11 /* Membership query */ +#define IGMP_V1_MEMB_REPORT 0x12 /* Ver. 1 membership report */ +#define IGMP_V2_MEMB_REPORT 0x16 /* Ver. 2 membership report */ +#define IGMP_LEAVE_GROUP 0x17 /* Leave-group message */ + +/* IGMP timer */ +#define IGMP_TMR_INTERVAL 100 /* Milliseconds */ +#define IGMP_V1_DELAYING_MEMBER_TMR (1000/IGMP_TMR_INTERVAL) +#define IGMP_JOIN_DELAYING_MEMBER_TMR (500 /IGMP_TMR_INTERVAL) + +/* MAC Filter Actions */ +#define IGMP_DEL_MAC_FILTER 0 +#define IGMP_ADD_MAC_FILTER 1 + +/* Group membership states */ +#define IGMP_GROUP_NON_MEMBER 0 +#define IGMP_GROUP_DELAYING_MEMBER 1 +#define IGMP_GROUP_IDLE_MEMBER 2 + +/* + * IGMP packet format. + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct igmp_msg { + PACK_STRUCT_FIELD(u8_t igmp_msgtype); + PACK_STRUCT_FIELD(u8_t igmp_maxresp); + PACK_STRUCT_FIELD(u16_t igmp_checksum); + PACK_STRUCT_FIELD(struct ip_addr igmp_group_address); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/* + * now a group structure - there is + * a list of groups for each interface + * these should really be linked from the interface, but + * if we keep them separate we will not affect the lwip original code + * too much + * + * There will be a group for the all systems group address but this + * will not run the state machine as it is used to kick off reports + * from all the other groups + */ + +struct igmp_group { + struct igmp_group *next; + struct netif *interface; + struct ip_addr group_address; + u8_t last_reporter_flag; /* signifies we were the last person to report */ + u8_t group_state; + u16_t timer; + u8_t use; /* counter of simultaneous uses */ +}; + + +/* Prototypes */ +void igmp_init(void); + +err_t igmp_start( struct netif *netif); + +err_t igmp_stop( struct netif *netif); + +void igmp_report_groups( struct netif *netif); + +struct igmp_group *igmp_lookfor_group( struct netif *ifp, struct ip_addr *addr); + +struct igmp_group *igmp_lookup_group( struct netif *ifp, struct ip_addr *addr); + +err_t igmp_remove_group( struct igmp_group *group); + +void igmp_input( struct pbuf *p, struct netif *inp, struct ip_addr *dest); + +err_t igmp_joingroup( struct ip_addr *ifaddr, struct ip_addr *groupaddr); + +err_t igmp_leavegroup( struct ip_addr *ifaddr, struct ip_addr *groupaddr); + +void igmp_tmr(void); + +void igmp_timeout( struct igmp_group *group); + +void igmp_start_timer( struct igmp_group *group, u8_t max_time); + +void igmp_stop_timer( struct igmp_group *group); + +void igmp_delaying_member( struct igmp_group *group, u8_t maxresp); + +err_t igmp_ip_output_if( struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, u8_t ttl, u8_t proto, struct netif *netif); + +void igmp_send( struct igmp_group *group, u8_t type); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IGMP */ + +#endif /* __LWIP_IGMP_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/inet.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/inet.h new file mode 100644 index 0000000000000000000000000000000000000000..903afdf0f0158fd9be6759f76635561b58418223 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/inet.h @@ -0,0 +1,105 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_INET_H__ +#define __LWIP_INET_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* For compatibility with BSD code */ +struct in_addr { + u32_t s_addr; +}; + +#define INADDR_NONE ((u32_t)0xffffffffUL) /* 255.255.255.255 */ +#define INADDR_LOOPBACK ((u32_t)0x7f000001UL) /* 127.0.0.1 */ +#define INADDR_ANY ((u32_t)0x00000000UL) /* 0.0.0.0 */ +#define INADDR_BROADCAST ((u32_t)0xffffffffUL) /* 255.255.255.255 */ + +u32_t inet_addr(const char *cp); +int inet_aton(const char *cp, struct in_addr *addr); +char *inet_ntoa(struct in_addr addr); /* returns ptr to static buffer; not reentrant! */ + +#ifdef htons +#undef htons +#endif /* htons */ +#ifdef htonl +#undef htonl +#endif /* htonl */ +#ifdef ntohs +#undef ntohs +#endif /* ntohs */ +#ifdef ntohl +#undef ntohl +#endif /* ntohl */ + +#ifndef LWIP_PLATFORM_BYTESWAP +#define LWIP_PLATFORM_BYTESWAP 0 +#endif + +#if BYTE_ORDER == BIG_ENDIAN +#define htons(x) (x) +#define ntohs(x) (x) +#define htonl(x) (x) +#define ntohl(x) (x) +#else /* BYTE_ORDER != BIG_ENDIAN */ +#ifdef LWIP_PREFIX_BYTEORDER_FUNCS +/* workaround for naming collisions on some platforms */ +#define htons lwip_htons +#define ntohs lwip_ntohs +#define htonl lwip_htonl +#define ntohl lwip_ntohl +#endif /* LWIP_PREFIX_BYTEORDER_FUNCS */ +#if LWIP_PLATFORM_BYTESWAP +#define htons(x) LWIP_PLATFORM_HTONS(x) +#define ntohs(x) LWIP_PLATFORM_HTONS(x) +#define htonl(x) LWIP_PLATFORM_HTONL(x) +#define ntohl(x) LWIP_PLATFORM_HTONL(x) +#else /* LWIP_PLATFORM_BYTESWAP */ +u16_t htons(u16_t x); +u16_t ntohs(u16_t x); +u32_t htonl(u32_t x); +u32_t ntohl(u32_t x); +#endif /* LWIP_PLATFORM_BYTESWAP */ + +#endif /* BYTE_ORDER == BIG_ENDIAN */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_INET_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/inet_chksum.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/inet_chksum.h new file mode 100644 index 0000000000000000000000000000000000000000..6f5b1b63ab382eca504937a383415b6c6151a94b --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/inet_chksum.h @@ -0,0 +1,62 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_INET_CHKSUM_H__ +#define __LWIP_INET_CHKSUM_H__ + +#include "lwip/opt.h" + +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +u16_t inet_chksum(void *dataptr, u16_t len); +u16_t inet_chksum_pbuf(struct pbuf *p); +u16_t inet_chksum_pseudo(struct pbuf *p, + struct ip_addr *src, struct ip_addr *dest, + u8_t proto, u16_t proto_len); +#if LWIP_UDPLITE +u16_t inet_chksum_pseudo_partial(struct pbuf *p, + struct ip_addr *src, struct ip_addr *dest, + u8_t proto, u16_t proto_len, u16_t chksum_len); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_INET_H__ */ + diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/ip.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/ip.h new file mode 100644 index 0000000000000000000000000000000000000000..6b2cdee177b2f18fd849b51cbac1cdcfa3718e37 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/ip.h @@ -0,0 +1,200 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_IP_H__ +#define __LWIP_IP_H__ + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" +#include "lwip/err.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Currently, the function ip_output_if_opt() is only used with IGMP */ +#define IP_OPTIONS_SEND LWIP_IGMP + +#define IP_HLEN 20 + +#define IP_PROTO_ICMP 1 +#define IP_PROTO_UDP 17 +#define IP_PROTO_UDPLITE 136 +#define IP_PROTO_TCP 6 + +/* This is passed as the destination address to ip_output_if (not + to ip_output), meaning that an IP header already is constructed + in the pbuf. This is used when TCP retransmits. */ +#ifdef IP_HDRINCL +#undef IP_HDRINCL +#endif /* IP_HDRINCL */ +#define IP_HDRINCL NULL + +#if LWIP_NETIF_HWADDRHINT +#define IP_PCB_ADDRHINT ;u8_t addr_hint +#else +#define IP_PCB_ADDRHINT +#endif /* LWIP_NETIF_HWADDRHINT */ + +/* This is the common part of all PCB types. It needs to be at the + beginning of a PCB type definition. It is located here so that + changes to this common part are made in one location instead of + having to change all PCB structs. */ +#define IP_PCB \ + /* ip addresses in network byte order */ \ + struct ip_addr local_ip; \ + struct ip_addr remote_ip; \ + /* Socket options */ \ + u16_t so_options; \ + /* Type Of Service */ \ + u8_t tos; \ + /* Time To Live */ \ + u8_t ttl \ + /* link layer address resolution hint */ \ + IP_PCB_ADDRHINT + +struct ip_pcb { +/* Common members of all PCB types */ + IP_PCB; +}; + +/* + * Option flags per-socket. These are the same like SO_XXX. + */ +#define SOF_DEBUG (u16_t)0x0001U /* turn on debugging info recording */ +#define SOF_ACCEPTCONN (u16_t)0x0002U /* socket has had listen() */ +#define SOF_REUSEADDR (u16_t)0x0004U /* allow local address reuse */ +#define SOF_KEEPALIVE (u16_t)0x0008U /* keep connections alive */ +#define SOF_DONTROUTE (u16_t)0x0010U /* just use interface addresses */ +#define SOF_BROADCAST (u16_t)0x0020U /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */ +#define SOF_USELOOPBACK (u16_t)0x0040U /* bypass hardware when possible */ +#define SOF_LINGER (u16_t)0x0080U /* linger on close if data present */ +#define SOF_OOBINLINE (u16_t)0x0100U /* leave received OOB data in line */ +#define SOF_REUSEPORT (u16_t)0x0200U /* allow local address & port reuse */ + + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_hdr { + /* version / header length / type of service */ + PACK_STRUCT_FIELD(u16_t _v_hl_tos); + /* total length */ + PACK_STRUCT_FIELD(u16_t _len); + /* identification */ + PACK_STRUCT_FIELD(u16_t _id); + /* fragment offset field */ + PACK_STRUCT_FIELD(u16_t _offset); +#define IP_RF 0x8000 /* reserved fragment flag */ +#define IP_DF 0x4000 /* dont fragment flag */ +#define IP_MF 0x2000 /* more fragments flag */ +#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */ + /* time to live / protocol*/ + PACK_STRUCT_FIELD(u16_t _ttl_proto); + /* checksum */ + PACK_STRUCT_FIELD(u16_t _chksum); + /* source and destination IP addresses */ + PACK_STRUCT_FIELD(struct ip_addr src); + PACK_STRUCT_FIELD(struct ip_addr dest); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define IPH_V(hdr) (ntohs((hdr)->_v_hl_tos) >> 12) +#define IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f) +#define IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff) +#define IPH_LEN(hdr) ((hdr)->_len) +#define IPH_ID(hdr) ((hdr)->_id) +#define IPH_OFFSET(hdr) ((hdr)->_offset) +#define IPH_TTL(hdr) (ntohs((hdr)->_ttl_proto) >> 8) +#define IPH_PROTO(hdr) (ntohs((hdr)->_ttl_proto) & 0xff) +#define IPH_CHKSUM(hdr) ((hdr)->_chksum) + +#define IPH_VHLTOS_SET(hdr, v, hl, tos) (hdr)->_v_hl_tos = (htons(((v) << 12) | ((hl) << 8) | (tos))) +#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len) +#define IPH_ID_SET(hdr, id) (hdr)->_id = (id) +#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off) +#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl_proto = (htons(IPH_PROTO(hdr) | ((u16_t)(ttl) << 8))) +#define IPH_PROTO_SET(hdr, proto) (hdr)->_ttl_proto = (htons((proto) | (IPH_TTL(hdr) << 8))) +#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum) + +/** The interface that provided the packet for the current callback invocation. */ +extern struct netif *current_netif; +/** Header of the input packet currently being processed. */ +extern const struct ip_hdr *current_header; + +#define ip_init() /* Compatibility define, not init needed. */ +struct netif *ip_route(struct ip_addr *dest); +err_t ip_input(struct pbuf *p, struct netif *inp); +err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t tos, u8_t proto); +err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t tos, u8_t proto, + struct netif *netif); +#if LWIP_NETIF_HWADDRHINT +err_t ip_output_hinted(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t tos, u8_t proto, u8_t *addr_hint); +#endif /* LWIP_NETIF_HWADDRHINT */ +#if IP_OPTIONS_SEND +err_t ip_output_if_opt(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options, + u16_t optlen); +#endif /* IP_OPTIONS_SEND */ +/** Get the interface that received the current packet. + * This function must only be called from a receive callback (udp_recv, + * raw_recv, tcp_accept). It will return NULL otherwise. */ +#define ip_current_netif() (current_netif) +/** Get the IP header of the current packet. + * This function must only be called from a receive callback (udp_recv, + * raw_recv, tcp_accept). It will return NULL otherwise. */ +#define ip_current_header() (current_header) +#if IP_DEBUG +void ip_debug_print(struct pbuf *p); +#else +#define ip_debug_print(p) +#endif /* IP_DEBUG */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_IP_H__ */ + + diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/ip_addr.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/ip_addr.h new file mode 100644 index 0000000000000000000000000000000000000000..5fbc44d14a509d656b0ac5ffaaae532779397d21 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/ip_addr.h @@ -0,0 +1,175 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_IP_ADDR_H__ +#define __LWIP_IP_ADDR_H__ + +#include "lwip/opt.h" + +#include "lwip/inet.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_addr { + PACK_STRUCT_FIELD(u32_t addr); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/* + * struct ipaddr2 is used in the definition of the ARP packet format in + * order to support compilers that don't have structure packing. + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_addr2 { + PACK_STRUCT_FIELD(u16_t addrw[2]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +struct netif; + +extern const struct ip_addr ip_addr_any; +extern const struct ip_addr ip_addr_broadcast; + +/** IP_ADDR_ can be used as a fixed IP address + * for the wildcard and the broadcast address + */ +#define IP_ADDR_ANY ((struct ip_addr *)&ip_addr_any) +#define IP_ADDR_BROADCAST ((struct ip_addr *)&ip_addr_broadcast) + +/* Definitions of the bits in an Internet address integer. + + On subnets, host and network parts are found according to + the subnet mask, not these masks. */ + +#define IN_CLASSA(a) ((((u32_t)(a)) & 0x80000000UL) == 0) +#define IN_CLASSA_NET 0xff000000 +#define IN_CLASSA_NSHIFT 24 +#define IN_CLASSA_HOST (0xffffffff & ~IN_CLASSA_NET) +#define IN_CLASSA_MAX 128 + +#define IN_CLASSB(a) ((((u32_t)(a)) & 0xc0000000UL) == 0x80000000UL) +#define IN_CLASSB_NET 0xffff0000 +#define IN_CLASSB_NSHIFT 16 +#define IN_CLASSB_HOST (0xffffffff & ~IN_CLASSB_NET) +#define IN_CLASSB_MAX 65536 + +#define IN_CLASSC(a) ((((u32_t)(a)) & 0xe0000000UL) == 0xc0000000UL) +#define IN_CLASSC_NET 0xffffff00 +#define IN_CLASSC_NSHIFT 8 +#define IN_CLASSC_HOST (0xffffffff & ~IN_CLASSC_NET) + +#define IN_CLASSD(a) (((u32_t)(a) & 0xf0000000UL) == 0xe0000000UL) +#define IN_CLASSD_NET 0xf0000000 /* These ones aren't really */ +#define IN_CLASSD_NSHIFT 28 /* net and host fields, but */ +#define IN_CLASSD_HOST 0x0fffffff /* routing needn't know. */ +#define IN_MULTICAST(a) IN_CLASSD(a) + +#define IN_EXPERIMENTAL(a) (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL) +#define IN_BADCLASS(a) (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL) + +#define IN_LOOPBACKNET 127 /* official! */ + +#define IP4_ADDR(ipaddr, a,b,c,d) \ + (ipaddr)->addr = htonl(((u32_t)((a) & 0xff) << 24) | \ + ((u32_t)((b) & 0xff) << 16) | \ + ((u32_t)((c) & 0xff) << 8) | \ + (u32_t)((d) & 0xff)) + +#define ip_addr_set(dest, src) (dest)->addr = \ + ((src) == NULL? 0:\ + (src)->addr) +/** + * Determine if two address are on the same network. + * + * @arg addr1 IP address 1 + * @arg addr2 IP address 2 + * @arg mask network identifier mask + * @return !0 if the network identifiers of both address match + */ +#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \ + (mask)->addr) == \ + ((addr2)->addr & \ + (mask)->addr)) +#define ip_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr) + +#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == 0) + +u8_t ip_addr_isbroadcast(struct ip_addr *, struct netif *); + +#define ip_addr_ismulticast(addr1) (((addr1)->addr & ntohl(0xf0000000UL)) == ntohl(0xe0000000UL)) + +#define ip_addr_islinklocal(addr1) (((addr1)->addr & ntohl(0xffff0000UL)) == ntohl(0xa9fe0000UL)) + +#define ip_addr_debug_print(debug, ipaddr) \ + LWIP_DEBUGF(debug, ("%"U16_F".%"U16_F".%"U16_F".%"U16_F, \ + ipaddr != NULL ? \ + (u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff : 0, \ + ipaddr != NULL ? \ + (u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff : 0, \ + ipaddr != NULL ? \ + (u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff : 0, \ + ipaddr != NULL ? \ + (u16_t)ntohl((ipaddr)->addr) & 0xff : 0)) + +/* These are cast to u16_t, with the intent that they are often arguments + * to printf using the U16_F format from cc.h. */ +#define ip4_addr1(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff) +#define ip4_addr2(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff) +#define ip4_addr3(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff) +#define ip4_addr4(ipaddr) ((u16_t)(ntohl((ipaddr)->addr)) & 0xff) + +/** + * Same as inet_ntoa() but takes a struct ip_addr* + */ +#define ip_ntoa(addr) ((addr != NULL) ? inet_ntoa(*((struct in_addr*)(addr))) : "NULL") + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_IP_ADDR_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/ip_frag.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/ip_frag.h new file mode 100644 index 0000000000000000000000000000000000000000..adc6e91955886787fb06a7672d8d75d8d60d0cde --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4/lwip/ip_frag.h @@ -0,0 +1,78 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Jani Monoses + * + */ + +#ifndef __LWIP_IP_FRAG_H__ +#define __LWIP_IP_FRAG_H__ + +#include "lwip/opt.h" +#include "lwip/err.h" +#include "lwip/pbuf.h" +#include "lwip/netif.h" +#include "lwip/ip_addr.h" +#include "lwip/ip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if IP_REASSEMBLY +/* The IP reassembly timer interval in milliseconds. */ +#define IP_TMR_INTERVAL 1000 + +/* IP reassembly helper struct. + * This is exported because memp needs to know the size. + */ +struct ip_reassdata { + struct ip_reassdata *next; + struct pbuf *p; + struct ip_hdr iphdr; + u16_t datagram_len; + u8_t flags; + u8_t timer; +}; + +void ip_reass_init(void); +void ip_reass_tmr(void); +struct pbuf * ip_reass(struct pbuf *p); +#endif /* IP_REASSEMBLY */ + +#if IP_FRAG +err_t ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest); +#endif /* IP_FRAG */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_IP_FRAG_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/api.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/api.h new file mode 100644 index 0000000000000000000000000000000000000000..7d2c9e6ecea45ccabe0148495b9c3764eb6d20ef --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/api.h @@ -0,0 +1,224 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_API_H__ +#define __LWIP_API_H__ + +#include "lwip/opt.h" + +#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ + +#include /* for size_t */ + +#include "lwip/netbuf.h" +#include "lwip/sys.h" +#include "lwip/ip_addr.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Throughout this file, IP addresses and port numbers are expected to be in + * the same byte order as in the corresponding pcb. + */ + +/* Flags for netconn_write */ +#define NETCONN_NOFLAG 0x00 +#define NETCONN_NOCOPY 0x00 /* Only for source code compatibility */ +#define NETCONN_COPY 0x01 +#define NETCONN_MORE 0x02 + +/* Helpers to process several netconn_types by the same code */ +#define NETCONNTYPE_GROUP(t) (t&0xF0) +#define NETCONNTYPE_DATAGRAM(t) (t&0xE0) + +enum netconn_type { + NETCONN_INVALID = 0, + /* NETCONN_TCP Group */ + NETCONN_TCP = 0x10, + /* NETCONN_UDP Group */ + NETCONN_UDP = 0x20, + NETCONN_UDPLITE = 0x21, + NETCONN_UDPNOCHKSUM= 0x22, + /* NETCONN_RAW Group */ + NETCONN_RAW = 0x40 +}; + +enum netconn_state { + NETCONN_NONE, + NETCONN_WRITE, + NETCONN_LISTEN, + NETCONN_CONNECT, + NETCONN_CLOSE +}; + +enum netconn_evt { + NETCONN_EVT_RCVPLUS, + NETCONN_EVT_RCVMINUS, + NETCONN_EVT_SENDPLUS, + NETCONN_EVT_SENDMINUS +}; + +#if LWIP_IGMP +enum netconn_igmp { + NETCONN_JOIN, + NETCONN_LEAVE +}; +#endif /* LWIP_IGMP */ + +/* forward-declare some structs to avoid to include their headers */ +struct ip_pcb; +struct tcp_pcb; +struct udp_pcb; +struct raw_pcb; +struct netconn; + +/** A callback prototype to inform about events for a netconn */ +typedef void (* netconn_callback)(struct netconn *, enum netconn_evt, u16_t len); + +/** A netconn descriptor */ +struct netconn { + /** type of the netconn (TCP, UDP or RAW) */ + enum netconn_type type; + /** current state of the netconn */ + enum netconn_state state; + /** the lwIP internal protocol control block */ + union { + struct ip_pcb *ip; + struct tcp_pcb *tcp; + struct udp_pcb *udp; + struct raw_pcb *raw; + } pcb; + /** the last error this netconn had */ + err_t err; + /** sem that is used to synchroneously execute functions in the core context */ + sys_sem_t op_completed; + /** mbox where received packets are stored until they are fetched + by the netconn application thread (can grow quite big) */ + sys_mbox_t recvmbox; + /** mbox where new connections are stored until processed + by the application thread */ + sys_mbox_t acceptmbox; + /** only used for socket layer */ + int socket; +#if LWIP_SO_RCVTIMEO + /** timeout to wait for new data to be received + (or connections to arrive for listening netconns) */ + int recv_timeout; +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF + /** maximum amount of bytes queued in recvmbox */ + int recv_bufsize; +#endif /* LWIP_SO_RCVBUF */ + s16_t recv_avail; +#if LWIP_TCP + /** TCP: when data passed to netconn_write doesn't fit into the send buffer, + this temporarily stores the message. */ + struct api_msg_msg *write_msg; + /** TCP: when data passed to netconn_write doesn't fit into the send buffer, + this temporarily stores how much is already sent. */ + size_t write_offset; +#if LWIP_TCPIP_CORE_LOCKING + /** TCP: when data passed to netconn_write doesn't fit into the send buffer, + this temporarily stores whether to wake up the original application task + if data couldn't be sent in the first try. */ + u8_t write_delayed; +#endif /* LWIP_TCPIP_CORE_LOCKING */ +#endif /* LWIP_TCP */ + /** A callback function that is informed about events for this netconn */ + netconn_callback callback; +}; + +/* Register an Network connection event */ +#define API_EVENT(c,e,l) if (c->callback) { \ + (*c->callback)(c, e, l); \ + } + +/* Network connection functions: */ +#define netconn_new(t) netconn_new_with_proto_and_callback(t, 0, NULL) +#define netconn_new_with_callback(t, c) netconn_new_with_proto_and_callback(t, 0, c) +struct +netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto, + netconn_callback callback); +err_t netconn_delete (struct netconn *conn); +/** Get the type of a netconn (as enum netconn_type). */ +#define netconn_type(conn) (conn->type) + +err_t netconn_getaddr (struct netconn *conn, + struct ip_addr *addr, + u16_t *port, + u8_t local); +#define netconn_peer(c,i,p) netconn_getaddr(c,i,p,0) +#define netconn_addr(c,i,p) netconn_getaddr(c,i,p,1) + +err_t netconn_bind (struct netconn *conn, + struct ip_addr *addr, + u16_t port); +err_t netconn_connect (struct netconn *conn, + struct ip_addr *addr, + u16_t port); +err_t netconn_disconnect (struct netconn *conn); +err_t netconn_listen_with_backlog(struct netconn *conn, u8_t backlog); +#define netconn_listen(conn) netconn_listen_with_backlog(conn, TCP_DEFAULT_LISTEN_BACKLOG) +struct netconn * netconn_accept (struct netconn *conn); +struct netbuf * netconn_recv (struct netconn *conn); +err_t netconn_sendto (struct netconn *conn, + struct netbuf *buf, struct ip_addr *addr, u16_t port); +err_t netconn_send (struct netconn *conn, + struct netbuf *buf); +err_t netconn_write (struct netconn *conn, + const void *dataptr, size_t size, + u8_t apiflags); +err_t netconn_close (struct netconn *conn); + +#if LWIP_IGMP +err_t netconn_join_leave_group (struct netconn *conn, + struct ip_addr *multiaddr, + struct ip_addr *interface, + enum netconn_igmp join_or_leave); +#endif /* LWIP_IGMP */ +#if LWIP_DNS +err_t netconn_gethostbyname(const char *name, struct ip_addr *addr); +#endif /* LWIP_DNS */ + +#define netconn_err(conn) ((conn)->err) +#define netconn_recv_bufsize(conn) ((conn)->recv_bufsize) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_NETCONN */ + +#endif /* __LWIP_API_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/api_msg.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/api_msg.h new file mode 100644 index 0000000000000000000000000000000000000000..7718d909b293a5b513944cee411a539d419f2d26 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/api_msg.h @@ -0,0 +1,164 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_API_MSG_H__ +#define __LWIP_API_MSG_H__ + +#include "lwip/opt.h" + +#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ + +#include /* for size_t */ + +#include "lwip/ip_addr.h" +#include "lwip/err.h" +#include "lwip/sys.h" +#include "lwip/igmp.h" +#include "lwip/api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* IP addresses and port numbers are expected to be in + * the same byte order as in the corresponding pcb. + */ +/** This struct includes everything that is necessary to execute a function + for a netconn in another thread context (mainly used to process netconns + in the tcpip_thread context to be thread safe). */ +struct api_msg_msg { + /** The netconn which to process - always needed: it includes the semaphore + which is used to block the application thread until the function finished. */ + struct netconn *conn; + /** Depending on the executed function, one of these union members is used */ + union { + /** used for do_send */ + struct netbuf *b; + /** used for do_newconn */ + struct { + u8_t proto; + } n; + /** used for do_bind and do_connect */ + struct { + struct ip_addr *ipaddr; + u16_t port; + } bc; + /** used for do_getaddr */ + struct { + struct ip_addr *ipaddr; + u16_t *port; + u8_t local; + } ad; + /** used for do_write */ + struct { + const void *dataptr; + size_t len; + u8_t apiflags; + } w; + /** used for do_recv */ + struct { + u16_t len; + } r; +#if LWIP_IGMP + /** used for do_join_leave_group */ + struct { + struct ip_addr *multiaddr; + struct ip_addr *interface; + enum netconn_igmp join_or_leave; + } jl; +#endif /* LWIP_IGMP */ +#if TCP_LISTEN_BACKLOG + struct { + u8_t backlog; + } lb; +#endif /* TCP_LISTEN_BACKLOG */ + } msg; +}; + +/** This struct contains a function to execute in another thread context and + a struct api_msg_msg that serves as an argument for this function. + This is passed to tcpip_apimsg to execute functions in tcpip_thread context. */ +struct api_msg { + /** function to execute in tcpip_thread context */ + void (* function)(struct api_msg_msg *msg); + /** arguments for this function */ + struct api_msg_msg msg; +}; + +#if LWIP_DNS +/** As do_gethostbyname requires more arguments but doesn't require a netconn, + it has its own struct (to avoid struct api_msg getting bigger than necessary). + do_gethostbyname must be called using tcpip_callback instead of tcpip_apimsg + (see netconn_gethostbyname). */ +struct dns_api_msg { + /** Hostname to query or dotted IP address string */ + const char *name; + /** Rhe resolved address is stored here */ + struct ip_addr *addr; + /** This semaphore is posted when the name is resolved, the application thread + should wait on it. */ + sys_sem_t sem; + /** Errors are given back here */ + err_t *err; +}; +#endif /* LWIP_DNS */ + +void do_newconn ( struct api_msg_msg *msg); +void do_delconn ( struct api_msg_msg *msg); +void do_bind ( struct api_msg_msg *msg); +void do_connect ( struct api_msg_msg *msg); +void do_disconnect ( struct api_msg_msg *msg); +void do_listen ( struct api_msg_msg *msg); +void do_send ( struct api_msg_msg *msg); +void do_recv ( struct api_msg_msg *msg); +void do_write ( struct api_msg_msg *msg); +void do_getaddr ( struct api_msg_msg *msg); +void do_close ( struct api_msg_msg *msg); +#if LWIP_IGMP +void do_join_leave_group( struct api_msg_msg *msg); +#endif /* LWIP_IGMP */ + +#if LWIP_DNS +void do_gethostbyname(void *arg); +#endif /* LWIP_DNS */ + +struct netconn* netconn_alloc(enum netconn_type t, netconn_callback callback); +void netconn_free(struct netconn *conn); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_NETCONN */ + +#endif /* __LWIP_API_MSG_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/arch.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/arch.h new file mode 100644 index 0000000000000000000000000000000000000000..5ab190a732d1e6a4803efa570e35ca99bf274759 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/arch.h @@ -0,0 +1,235 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_ARCH_H__ +#define __LWIP_ARCH_H__ + +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 1234 +#endif + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 4321 +#endif + +#include "arch/cc.h" + +/** Temporary: define format string for size_t if not defined in cc.h */ +#ifndef SZT_F +#define SZT_F U32_F +#endif /* SZT_F */ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef PACK_STRUCT_BEGIN +#define PACK_STRUCT_BEGIN +#endif /* PACK_STRUCT_BEGIN */ + +#ifndef PACK_STRUCT_END +#define PACK_STRUCT_END +#endif /* PACK_STRUCT_END */ + +#ifndef PACK_STRUCT_FIELD +#define PACK_STRUCT_FIELD(x) x +#endif /* PACK_STRUCT_FIELD */ + + +#ifndef LWIP_UNUSED_ARG +#define LWIP_UNUSED_ARG(x) (void)x +#endif /* LWIP_UNUSED_ARG */ + + +#ifdef LWIP_PROVIDE_ERRNO + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Arg list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + + +#define ENSROK 0 /* DNS server returned answer with no data */ +#define ENSRNODATA 160 /* DNS server returned answer with no data */ +#define ENSRFORMERR 161 /* DNS server claims query was misformatted */ +#define ENSRSERVFAIL 162 /* DNS server returned general failure */ +#define ENSRNOTFOUND 163 /* Domain name not found */ +#define ENSRNOTIMP 164 /* DNS server does not implement requested operation */ +#define ENSRREFUSED 165 /* DNS server refused query */ +#define ENSRBADQUERY 166 /* Misformatted DNS query */ +#define ENSRBADNAME 167 /* Misformatted domain name */ +#define ENSRBADFAMILY 168 /* Unsupported address family */ +#define ENSRBADRESP 169 /* Misformatted DNS reply */ +#define ENSRCONNREFUSED 170 /* Could not contact DNS servers */ +#define ENSRTIMEOUT 171 /* Timeout while contacting DNS servers */ +#define ENSROF 172 /* End of file */ +#define ENSRFILE 173 /* Error reading file */ +#define ENSRNOMEM 174 /* Out of memory */ +#define ENSRDESTRUCTION 175 /* Application terminated lookup */ +#define ENSRQUERYDOMAINTOOLONG 176 /* Domain name is too long */ +#define ENSRCNAMELOOP 177 /* Domain name is too long */ + +#ifndef errno +extern int errno; +#endif + +#endif /* LWIP_PROVIDE_ERRNO */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_ARCH_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/debug.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/debug.h new file mode 100644 index 0000000000000000000000000000000000000000..fb0760790f5c4fd5fd3225bfaedcdfedcca1c890 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/debug.h @@ -0,0 +1,100 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_DEBUG_H__ +#define __LWIP_DEBUG_H__ + +#include "lwip/arch.h" + +/** lower two bits indicate debug level + * - 0 all + * - 1 warning + * - 2 serious + * - 3 severe + */ +#define LWIP_DBG_LEVEL_ALL 0x00 +#define LWIP_DBG_LEVEL_OFF LWIP_DBG_LEVEL_ALL /* compatibility define only */ +#define LWIP_DBG_LEVEL_WARNING 0x01 /* bad checksums, dropped packets, ... */ +#define LWIP_DBG_LEVEL_SERIOUS 0x02 /* memory allocation failures, ... */ +#define LWIP_DBG_LEVEL_SEVERE 0x03 +#define LWIP_DBG_MASK_LEVEL 0x03 + +/** flag for LWIP_DEBUGF to enable that debug message */ +#define LWIP_DBG_ON 0x80U +/** flag for LWIP_DEBUGF to disable that debug message */ +#define LWIP_DBG_OFF 0x00U + +/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */ +#define LWIP_DBG_TRACE 0x40U +/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */ +#define LWIP_DBG_STATE 0x20U +/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */ +#define LWIP_DBG_FRESH 0x10U +/** flag for LWIP_DEBUGF to halt after printing this debug message */ +#define LWIP_DBG_HALT 0x08U + +#ifndef LWIP_NOASSERT +#define LWIP_ASSERT(message, assertion) do { if(!(assertion)) \ + LWIP_PLATFORM_ASSERT(message); } while(0) +#else /* LWIP_NOASSERT */ +#define LWIP_ASSERT(message, assertion) +#endif /* LWIP_NOASSERT */ + +/** if "expression" isn't true, then print "message" and execute "handler" expression */ +#ifndef LWIP_ERROR +#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \ + LWIP_PLATFORM_ASSERT(message); handler;}} while(0) +#endif /* LWIP_ERROR */ + +#ifdef LWIP_DEBUG +/** print debug message only if debug message type is enabled... + * AND is of correct type AND is at least LWIP_DBG_LEVEL + */ +#define LWIP_DEBUGF(debug, message) do { \ + if ( \ + ((debug) & LWIP_DBG_ON) && \ + ((debug) & LWIP_DBG_TYPES_ON) && \ + ((s16_t)((debug) & LWIP_DBG_MASK_LEVEL) >= LWIP_DBG_MIN_LEVEL)) { \ + LWIP_PLATFORM_DIAG(message); \ + if ((debug) & LWIP_DBG_HALT) { \ + while(1); \ + } \ + } \ + } while(0) + +#else /* LWIP_DEBUG */ +#define LWIP_DEBUGF(debug, message) +#endif /* LWIP_DEBUG */ + +#endif /* __LWIP_DEBUG_H__ */ + diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/def.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/def.h new file mode 100644 index 0000000000000000000000000000000000000000..c3681ac1fdf8915b29ffafaa9305aa2e360ea1a9 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/def.h @@ -0,0 +1,49 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_DEF_H__ +#define __LWIP_DEF_H__ + +/* this might define NULL already */ +#include "lwip/arch.h" + +#define LWIP_MAX(x , y) (((x) > (y)) ? (x) : (y)) +#define LWIP_MIN(x , y) (((x) < (y)) ? (x) : (y)) + +#ifndef NULL +#define NULL ((void *)0) +#endif + + +#endif /* __LWIP_DEF_H__ */ + diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/dhcp.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/dhcp.h new file mode 100644 index 0000000000000000000000000000000000000000..27a0adeb87c571447239792ef61a4dbd03f0f090 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/dhcp.h @@ -0,0 +1,248 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/** @file + */ + +#ifndef __LWIP_DHCP_H__ +#define __LWIP_DHCP_H__ + +#include "lwip/opt.h" + +#if LWIP_DHCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/netif.h" +#include "lwip/udp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** period (in seconds) of the application calling dhcp_coarse_tmr() */ +#define DHCP_COARSE_TIMER_SECS 60 +/** period (in milliseconds) of the application calling dhcp_coarse_tmr() */ +#define DHCP_COARSE_TIMER_MSECS (DHCP_COARSE_TIMER_SECS * 1000UL) +/** period (in milliseconds) of the application calling dhcp_fine_tmr() */ +#define DHCP_FINE_TIMER_MSECS 500 + +struct dhcp +{ + /** transaction identifier of last sent request */ + u32_t xid; + /** our connection to the DHCP server */ + struct udp_pcb *pcb; + /** incoming msg */ + struct dhcp_msg *msg_in; + /** incoming msg options */ + void *options_in; + /** ingoing msg options length */ + u16_t options_in_len; + /** current DHCP state machine state */ + u8_t state; + /** retries of current request */ + u8_t tries; + + struct pbuf *p_out; /* pbuf of outcoming msg */ + struct dhcp_msg *msg_out; /* outgoing msg */ + u16_t options_out_len; /* outgoing msg options length */ + u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */ + u16_t t1_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */ + u16_t t2_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */ + struct ip_addr server_ip_addr; /* dhcp server address that offered this lease */ + struct ip_addr offered_ip_addr; + struct ip_addr offered_sn_mask; + struct ip_addr offered_gw_addr; + struct ip_addr offered_bc_addr; +#define DHCP_MAX_DNS 2 + u32_t dns_count; /* actual number of DNS servers obtained */ + struct ip_addr offered_dns_addr[DHCP_MAX_DNS]; /* DNS server addresses */ + + u32_t offered_t0_lease; /* lease period (in seconds) */ + u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */ + u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period) */ +#if LWIP_DHCP_AUTOIP_COOP + u8_t autoip_coop_state; +#endif +/** Patch #1308 + * TODO: See dhcp.c "TODO"s + */ +#if 0 + struct ip_addr offered_si_addr; + u8_t *boot_file_name; +#endif +}; + +/* MUST be compiled with "pack structs" or equivalent! */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** minimum set of fields of any DHCP message */ +struct dhcp_msg +{ + PACK_STRUCT_FIELD(u8_t op); + PACK_STRUCT_FIELD(u8_t htype); + PACK_STRUCT_FIELD(u8_t hlen); + PACK_STRUCT_FIELD(u8_t hops); + PACK_STRUCT_FIELD(u32_t xid); + PACK_STRUCT_FIELD(u16_t secs); + PACK_STRUCT_FIELD(u16_t flags); + PACK_STRUCT_FIELD(struct ip_addr ciaddr); + PACK_STRUCT_FIELD(struct ip_addr yiaddr); + PACK_STRUCT_FIELD(struct ip_addr siaddr); + PACK_STRUCT_FIELD(struct ip_addr giaddr); +#define DHCP_CHADDR_LEN 16U + PACK_STRUCT_FIELD(u8_t chaddr[DHCP_CHADDR_LEN]); +#define DHCP_SNAME_LEN 64U + PACK_STRUCT_FIELD(u8_t sname[DHCP_SNAME_LEN]); +#define DHCP_FILE_LEN 128U + PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]); + PACK_STRUCT_FIELD(u32_t cookie); +#define DHCP_MIN_OPTIONS_LEN 68U +/** make sure user does not configure this too small */ +#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN)) +# undef DHCP_OPTIONS_LEN +#endif +/** allow this to be configured in lwipopts.h, but not too small */ +#if (!defined(DHCP_OPTIONS_LEN)) +/** set this to be sufficient for your options in outgoing DHCP msgs */ +# define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN +#endif + PACK_STRUCT_FIELD(u8_t options[DHCP_OPTIONS_LEN]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** start DHCP configuration */ +err_t dhcp_start(struct netif *netif); +/** enforce early lease renewal (not needed normally)*/ +err_t dhcp_renew(struct netif *netif); +/** release the DHCP lease, usually called before dhcp_stop()*/ +err_t dhcp_release(struct netif *netif); +/** stop DHCP configuration */ +void dhcp_stop(struct netif *netif); +/** inform server of our manual IP address */ +void dhcp_inform(struct netif *netif); +/** Handle a possible change in the network configuration */ +void dhcp_network_changed(struct netif *netif); + +/** if enabled, check whether the offered IP address is not in use, using ARP */ +#if DHCP_DOES_ARP_CHECK +void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr); +#endif + +/** to be called every minute */ +void dhcp_coarse_tmr(void); +/** to be called every half second */ +void dhcp_fine_tmr(void); + +/** DHCP message item offsets and length */ +#define DHCP_MSG_OFS (UDP_DATA_OFS) + #define DHCP_OP_OFS (DHCP_MSG_OFS + 0) + #define DHCP_HTYPE_OFS (DHCP_MSG_OFS + 1) + #define DHCP_HLEN_OFS (DHCP_MSG_OFS + 2) + #define DHCP_HOPS_OFS (DHCP_MSG_OFS + 3) + #define DHCP_XID_OFS (DHCP_MSG_OFS + 4) + #define DHCP_SECS_OFS (DHCP_MSG_OFS + 8) + #define DHCP_FLAGS_OFS (DHCP_MSG_OFS + 10) + #define DHCP_CIADDR_OFS (DHCP_MSG_OFS + 12) + #define DHCP_YIADDR_OFS (DHCP_MSG_OFS + 16) + #define DHCP_SIADDR_OFS (DHCP_MSG_OFS + 20) + #define DHCP_GIADDR_OFS (DHCP_MSG_OFS + 24) + #define DHCP_CHADDR_OFS (DHCP_MSG_OFS + 28) + #define DHCP_SNAME_OFS (DHCP_MSG_OFS + 44) + #define DHCP_FILE_OFS (DHCP_MSG_OFS + 108) +#define DHCP_MSG_LEN 236 + +#define DHCP_COOKIE_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN) +#define DHCP_OPTIONS_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN + 4) + +#define DHCP_CLIENT_PORT 68 +#define DHCP_SERVER_PORT 67 + +/** DHCP client states */ +#define DHCP_REQUESTING 1 +#define DHCP_INIT 2 +#define DHCP_REBOOTING 3 +#define DHCP_REBINDING 4 +#define DHCP_RENEWING 5 +#define DHCP_SELECTING 6 +#define DHCP_INFORMING 7 +#define DHCP_CHECKING 8 +#define DHCP_PERMANENT 9 +#define DHCP_BOUND 10 +/** not yet implemented #define DHCP_RELEASING 11 */ +#define DHCP_BACKING_OFF 12 +#define DHCP_OFF 13 + +/** AUTOIP cooperatation flags */ +#define DHCP_AUTOIP_COOP_STATE_OFF 0 +#define DHCP_AUTOIP_COOP_STATE_ON 1 + +#define DHCP_BOOTREQUEST 1 +#define DHCP_BOOTREPLY 2 + +#define DHCP_DISCOVER 1 +#define DHCP_OFFER 2 +#define DHCP_REQUEST 3 +#define DHCP_DECLINE 4 +#define DHCP_ACK 5 +#define DHCP_NAK 6 +#define DHCP_RELEASE 7 +#define DHCP_INFORM 8 + +#define DHCP_HTYPE_ETH 1 + +#define DHCP_HLEN_ETH 6 + +#define DHCP_BROADCAST_FLAG 15 +#define DHCP_BROADCAST_MASK (1 << DHCP_FLAG_BROADCAST) + +/** BootP options */ +#define DHCP_OPTION_PAD 0 +#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */ +#define DHCP_OPTION_ROUTER 3 +#define DHCP_OPTION_DNS_SERVER 6 +#define DHCP_OPTION_HOSTNAME 12 +#define DHCP_OPTION_IP_TTL 23 +#define DHCP_OPTION_MTU 26 +#define DHCP_OPTION_BROADCAST 28 +#define DHCP_OPTION_TCP_TTL 37 +#define DHCP_OPTION_END 255 + +/** DHCP options */ +#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */ +#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */ +#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */ + +#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */ +#define DHCP_OPTION_MESSAGE_TYPE_LEN 1 + + +#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */ +#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */ + +#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */ +#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2 + +#define DHCP_OPTION_T1 58 /* T1 renewal time */ +#define DHCP_OPTION_T2 59 /* T2 rebinding time */ +#define DHCP_OPTION_US 60 +#define DHCP_OPTION_CLIENT_ID 61 +#define DHCP_OPTION_TFTP_SERVERNAME 66 +#define DHCP_OPTION_BOOTFILE 67 + +/** possible combinations of overloading the file and sname fields with options */ +#define DHCP_OVERLOAD_NONE 0 +#define DHCP_OVERLOAD_FILE 1 +#define DHCP_OVERLOAD_SNAME 2 +#define DHCP_OVERLOAD_SNAME_FILE 3 + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_DHCP */ + +#endif /*__LWIP_DHCP_H__*/ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/dns.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/dns.h new file mode 100644 index 0000000000000000000000000000000000000000..c1b8ae0318ecee6ae8d07f4a43eb0e6cea268056 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/dns.h @@ -0,0 +1,99 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/** + * lwip DNS resolver header file. + + * Author: Jim Pettinato + * April 2007 + + * ported from uIP resolv.c Copyright (c) 2002-2003, Adam Dunkels. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __LWIP_DNS_H__ +#define __LWIP_DNS_H__ + +#include "lwip/opt.h" + +#if LWIP_DNS /* don't build if not configured for use in lwipopts.h */ + +/** DNS timer period */ +#define DNS_TMR_INTERVAL 1000 + +/** DNS field TYPE used for "Resource Records" */ +#define DNS_RRTYPE_A 1 /* a host address */ +#define DNS_RRTYPE_NS 2 /* an authoritative name server */ +#define DNS_RRTYPE_MD 3 /* a mail destination (Obsolete - use MX) */ +#define DNS_RRTYPE_MF 4 /* a mail forwarder (Obsolete - use MX) */ +#define DNS_RRTYPE_CNAME 5 /* the canonical name for an alias */ +#define DNS_RRTYPE_SOA 6 /* marks the start of a zone of authority */ +#define DNS_RRTYPE_MB 7 /* a mailbox domain name (EXPERIMENTAL) */ +#define DNS_RRTYPE_MG 8 /* a mail group member (EXPERIMENTAL) */ +#define DNS_RRTYPE_MR 9 /* a mail rename domain name (EXPERIMENTAL) */ +#define DNS_RRTYPE_NULL 10 /* a null RR (EXPERIMENTAL) */ +#define DNS_RRTYPE_WKS 11 /* a well known service description */ +#define DNS_RRTYPE_PTR 12 /* a domain name pointer */ +#define DNS_RRTYPE_HINFO 13 /* host information */ +#define DNS_RRTYPE_MINFO 14 /* mailbox or mail list information */ +#define DNS_RRTYPE_MX 15 /* mail exchange */ +#define DNS_RRTYPE_TXT 16 /* text strings */ + +/** DNS field CLASS used for "Resource Records" */ +#define DNS_RRCLASS_IN 1 /* the Internet */ +#define DNS_RRCLASS_CS 2 /* the CSNET class (Obsolete - used only for examples in some obsolete RFCs) */ +#define DNS_RRCLASS_CH 3 /* the CHAOS class */ +#define DNS_RRCLASS_HS 4 /* Hesiod [Dyer 87] */ +#define DNS_RRCLASS_FLUSH 0x800 /* Flush bit */ + +/** Callback which is invoked when a hostname is found. + * A function of this type must be implemented by the application using the DNS resolver. + * @param name pointer to the name that was looked up. + * @param ipaddr pointer to a struct ip_addr containing the IP address of the hostname, + * or NULL if the name could not be found (or on any other error). + * @param callback_arg a user-specified callback argument passed to dns_gethostbyname +*/ +typedef void (*dns_found_callback)(const char *name, struct ip_addr *ipaddr, void *callback_arg); + + +void dns_init(void); + +void dns_tmr(void); + +void dns_setserver(u8_t numdns, struct ip_addr *dnsserver); + +struct ip_addr dns_getserver(u8_t numdns); + +err_t dns_gethostbyname(const char *hostname, struct ip_addr *addr, + dns_found_callback found, void *callback_arg); + +#if DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC +int dns_local_removehost(const char *hostname, const struct ip_addr *addr); +err_t dns_local_addhost(const char *hostname, const struct ip_addr *addr); +#endif /* DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +#endif /* LWIP_DNS */ + +#endif /* __LWIP_DNS_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/err.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/err.h new file mode 100644 index 0000000000000000000000000000000000000000..792f276065bba777146cf4eaa0134b0e610f5593 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/err.h @@ -0,0 +1,89 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_ERR_H__ +#define __LWIP_ERR_H__ + +#include "lwip/opt.h" +#include "lwip/arch.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Define LWIP_ERR_T in cc.h if you want to use + * a different type for your platform (must be signed). */ +#ifdef LWIP_ERR_T +typedef LWIP_ERR_T err_t; +#else /* LWIP_ERR_T */ + typedef s8_t err_t; +#endif /* LWIP_ERR_T*/ + +/* Definitions for error constants. */ + +#define ERR_OK 0 /* No error, everything OK. */ +#define ERR_MEM -1 /* Out of memory error. */ +#define ERR_BUF -2 /* Buffer error. */ +#define ERR_TIMEOUT -3 /* Timeout. */ +#define ERR_RTE -4 /* Routing problem. */ + +#define ERR_IS_FATAL(e) ((e) < ERR_RTE) + +#define ERR_ABRT -5 /* Connection aborted. */ +#define ERR_RST -6 /* Connection reset. */ +#define ERR_CLSD -7 /* Connection closed. */ +#define ERR_CONN -8 /* Not connected. */ + +#define ERR_VAL -9 /* Illegal value. */ + +#define ERR_ARG -10 /* Illegal argument. */ + +#define ERR_USE -11 /* Address in use. */ + +#define ERR_IF -12 /* Low-level netif error */ +#define ERR_ISCONN -13 /* Already connected. */ + +#define ERR_INPROGRESS -14 /* Operation in progress */ + + +#ifdef LWIP_DEBUG +extern const char *lwip_strerr(err_t err); +#else +#define lwip_strerr(x) "" +#endif /* LWIP_DEBUG */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_ERR_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/init.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/init.h new file mode 100644 index 0000000000000000000000000000000000000000..a86e0d9c8e12fdefe781ecee885b6d2e3d18cdbc --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/init.h @@ -0,0 +1,74 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_INIT_H__ +#define __LWIP_INIT_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** X.x.x: Major version of the stack */ +#define LWIP_VERSION_MAJOR 1U +/** x.X.x: Minor version of the stack */ +#define LWIP_VERSION_MINOR 3U +/** x.x.X: Revision of the stack */ +#define LWIP_VERSION_REVISION 2U +/** For release candidates, this is set to 1..254 + * For official releases, this is set to 255 (LWIP_RC_RELEASE) + * For development versions (CVS), this is set to 0 (LWIP_RC_DEVELOPMENT) */ +#define LWIP_VERSION_RC 255U + +/** LWIP_VERSION_RC is set to LWIP_RC_RELEASE for official releases */ +#define LWIP_RC_RELEASE 255U +/** LWIP_VERSION_RC is set to LWIP_RC_DEVELOPMENT for CVS versions */ +#define LWIP_RC_DEVELOPMENT 0U + +#define LWIP_VERSION_IS_RELEASE (LWIP_VERSION_RC == LWIP_RC_RELEASE) +#define LWIP_VERSION_IS_DEVELOPMENT (LWIP_VERSION_RC == LWIP_RC_DEVELOPMENT) +#define LWIP_VERSION_IS_RC ((LWIP_VERSION_RC != LWIP_RC_RELEASE) && (LWIP_VERSION_RC != LWIP_RC_DEVELOPMENT)) + +/** Provides the version of the stack */ +#define LWIP_VERSION (LWIP_VERSION_MAJOR << 24 | LWIP_VERSION_MINOR << 16 | \ + LWIP_VERSION_REVISION << 8 | LWIP_VERSION_RC) + +/* Modules initialization */ +void lwip_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_INIT_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/mem.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/mem.h new file mode 100644 index 0000000000000000000000000000000000000000..327229e587946649f818a1b8eaa1fe4a785111be --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/mem.h @@ -0,0 +1,109 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_MEM_H__ +#define __LWIP_MEM_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if MEM_LIBC_MALLOC + +#include /* for size_t */ + +typedef size_t mem_size_t; + +/* aliases for C library malloc() */ +#define mem_init() +/* in case C library malloc() needs extra protection, + * allow these defines to be overridden. + */ +#ifndef mem_free +#define mem_free free +#endif +#ifndef mem_malloc +#define mem_malloc malloc +#endif +#ifndef mem_calloc +#define mem_calloc calloc +#endif +#ifndef mem_realloc +static void *mem_realloc(void *mem, mem_size_t size) +{ + LWIP_UNUSED_ARG(size); + return mem; +} +#endif +#else /* MEM_LIBC_MALLOC */ + +/* MEM_SIZE would have to be aligned, but using 64000 here instead of + * 65535 leaves some room for alignment... + */ +#if MEM_SIZE > 64000l +typedef u32_t mem_size_t; +#else +typedef u16_t mem_size_t; +#endif /* MEM_SIZE > 64000 */ + +#if MEM_USE_POOLS +/** mem_init is not used when using pools instead of a heap */ +#define mem_init() +/** mem_realloc is not used when using pools instead of a heap: + we can't free part of a pool element and don't want to copy the rest */ +#define mem_realloc(mem, size) (mem) +#else /* MEM_USE_POOLS */ +/* lwIP alternative malloc */ +void mem_init(void); +void *mem_realloc(void *mem, mem_size_t size); +#endif /* MEM_USE_POOLS */ +void *mem_malloc(mem_size_t size); +void *mem_calloc(mem_size_t count, mem_size_t size); +void mem_free(void *mem); +#endif /* MEM_LIBC_MALLOC */ + +#ifndef LWIP_MEM_ALIGN_SIZE +#define LWIP_MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1) & ~(MEM_ALIGNMENT-1)) +#endif + +#ifndef LWIP_MEM_ALIGN +#define LWIP_MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1))) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_MEM_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/memp.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/memp.h new file mode 100644 index 0000000000000000000000000000000000000000..3de7bf9a0427495bb32b7005ff0abc4d782da04c --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/memp.h @@ -0,0 +1,118 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __LWIP_MEMP_H__ +#define __LWIP_MEMP_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Create the list of all memory pools managed by memp. MEMP_MAX represents a NULL pool at the end */ +typedef enum { +#define LWIP_MEMPOOL(name,num,size,desc) MEMP_##name, +#include "lwip/memp_std.h" + MEMP_MAX +} memp_t; + +#if MEM_USE_POOLS +/* Use a helper type to get the start and end of the user "memory pools" for mem_malloc */ +typedef enum { + /* Get the first (via: + MEMP_POOL_HELPER_START = ((u8_t) 1*MEMP_POOL_A + 0*MEMP_POOL_B + 0*MEMP_POOL_C + 0)*/ + MEMP_POOL_HELPER_FIRST = ((u8_t) +#define LWIP_MEMPOOL(name,num,size,desc) +#define LWIP_MALLOC_MEMPOOL_START 1 +#define LWIP_MALLOC_MEMPOOL(num, size) * MEMP_POOL_##size + 0 +#define LWIP_MALLOC_MEMPOOL_END +#include "lwip/memp_std.h" + ) , + /* Get the last (via: + MEMP_POOL_HELPER_END = ((u8_t) 0 + MEMP_POOL_A*0 + MEMP_POOL_B*0 + MEMP_POOL_C*1) */ + MEMP_POOL_HELPER_LAST = ((u8_t) +#define LWIP_MEMPOOL(name,num,size,desc) +#define LWIP_MALLOC_MEMPOOL_START +#define LWIP_MALLOC_MEMPOOL(num, size) 0 + MEMP_POOL_##size * +#define LWIP_MALLOC_MEMPOOL_END 1 +#include "lwip/memp_std.h" + ) +} memp_pool_helper_t; + +/* The actual start and stop values are here (cast them over) + We use this helper type and these defines so we can avoid using const memp_t values */ +#define MEMP_POOL_FIRST ((memp_t) MEMP_POOL_HELPER_FIRST) +#define MEMP_POOL_LAST ((memp_t) MEMP_POOL_HELPER_LAST) +#endif /* MEM_USE_POOLS */ + +#if MEMP_MEM_MALLOC || MEM_USE_POOLS +extern const u16_t memp_sizes[MEMP_MAX]; +#endif /* MEMP_MEM_MALLOC || MEM_USE_POOLS */ + +#if MEMP_MEM_MALLOC + +#include "mem.h" + +#define memp_init() +#define memp_malloc(type) mem_malloc(memp_sizes[type]) +#define memp_free(type, mem) mem_free(mem) + +#else /* MEMP_MEM_MALLOC */ + +#if MEM_USE_POOLS +/** This structure is used to save the pool one element came from. */ +struct memp_malloc_helper +{ + memp_t poolnr; +}; +#endif /* MEM_USE_POOLS */ + +void memp_init(void); + +#if MEMP_OVERFLOW_CHECK +void *memp_malloc_fn(memp_t type, const char* file, const int line); +#define memp_malloc(t) memp_malloc_fn((t), __FILE__, __LINE__) +#else +void *memp_malloc(memp_t type); +#endif +void memp_free(memp_t type, void *mem); + +#endif /* MEMP_MEM_MALLOC */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_MEMP_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/memp_std.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/memp_std.h new file mode 100644 index 0000000000000000000000000000000000000000..d8d4945ddb807fbad5a2cd695189c74cb4fcbe8d --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/memp_std.h @@ -0,0 +1,104 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * SETUP: Make sure we define everything we will need. + * + * We have create three types of pools: + * 1) MEMPOOL - standard pools + * 2) MALLOC_MEMPOOL - to be used by mem_malloc in mem.c + * 3) PBUF_MEMPOOL - a mempool of pbuf's, so include space for the pbuf struct + * + * If the include'r doesn't require any special treatment of each of the types + * above, then will declare #2 & #3 to be just standard mempools. + */ +#ifndef LWIP_MALLOC_MEMPOOL +/* This treats "malloc pools" just like any other pool. + The pools are a little bigger to provide 'size' as the amount of user data. */ +#define LWIP_MALLOC_MEMPOOL(num, size) LWIP_MEMPOOL(POOL_##size, num, (size + sizeof(struct memp_malloc_helper)), "MALLOC_"#size) +#define LWIP_MALLOC_MEMPOOL_START +#define LWIP_MALLOC_MEMPOOL_END +#endif /* LWIP_MALLOC_MEMPOOL */ + +#ifndef LWIP_PBUF_MEMPOOL +/* This treats "pbuf pools" just like any other pool. + * Allocates buffers for a pbuf struct AND a payload size */ +#define LWIP_PBUF_MEMPOOL(name, num, payload, desc) LWIP_MEMPOOL(name, num, (MEMP_ALIGN_SIZE(sizeof(struct pbuf)) + MEMP_ALIGN_SIZE(payload)), desc) +#endif /* LWIP_PBUF_MEMPOOL */ + + +/* + * A list of internal pools used by LWIP. + * + * LWIP_MEMPOOL(pool_name, number_elements, element_size, pool_description) + * creates a pool name MEMP_pool_name. description is used in stats.c + */ +#if LWIP_RAW +LWIP_MEMPOOL(RAW_PCB, MEMP_NUM_RAW_PCB, sizeof(struct raw_pcb), "RAW_PCB") +#endif /* LWIP_RAW */ + +#if LWIP_UDP +LWIP_MEMPOOL(UDP_PCB, MEMP_NUM_UDP_PCB, sizeof(struct udp_pcb), "UDP_PCB") +#endif /* LWIP_UDP */ + +#if LWIP_TCP +LWIP_MEMPOOL(TCP_PCB, MEMP_NUM_TCP_PCB, sizeof(struct tcp_pcb), "TCP_PCB") +LWIP_MEMPOOL(TCP_PCB_LISTEN, MEMP_NUM_TCP_PCB_LISTEN, sizeof(struct tcp_pcb_listen), "TCP_PCB_LISTEN") +LWIP_MEMPOOL(TCP_SEG, MEMP_NUM_TCP_SEG, sizeof(struct tcp_seg), "TCP_SEG") +#endif /* LWIP_TCP */ + +#if IP_REASSEMBLY +LWIP_MEMPOOL(REASSDATA, MEMP_NUM_REASSDATA, sizeof(struct ip_reassdata), "REASSDATA") +#endif /* IP_REASSEMBLY */ + +#if LWIP_NETCONN +LWIP_MEMPOOL(NETBUF, MEMP_NUM_NETBUF, sizeof(struct netbuf), "NETBUF") +LWIP_MEMPOOL(NETCONN, MEMP_NUM_NETCONN, sizeof(struct netconn), "NETCONN") +#endif /* LWIP_NETCONN */ + +#if NO_SYS==0 +LWIP_MEMPOOL(TCPIP_MSG_API, MEMP_NUM_TCPIP_MSG_API, sizeof(struct tcpip_msg), "TCPIP_MSG_API") +LWIP_MEMPOOL(TCPIP_MSG_INPKT,MEMP_NUM_TCPIP_MSG_INPKT, sizeof(struct tcpip_msg), "TCPIP_MSG_INPKT") +#endif /* NO_SYS==0 */ + +#if ARP_QUEUEING +LWIP_MEMPOOL(ARP_QUEUE, MEMP_NUM_ARP_QUEUE, sizeof(struct etharp_q_entry), "ARP_QUEUE") +#endif /* ARP_QUEUEING */ + +#if LWIP_IGMP +LWIP_MEMPOOL(IGMP_GROUP, MEMP_NUM_IGMP_GROUP, sizeof(struct igmp_group), "IGMP_GROUP") +#endif /* LWIP_IGMP */ + +#if NO_SYS==0 +LWIP_MEMPOOL(SYS_TIMEOUT, MEMP_NUM_SYS_TIMEOUT, sizeof(struct sys_timeo), "SYS_TIMEOUT") +#endif /* NO_SYS==0 */ + + +/* + * A list of pools of pbuf's used by LWIP. + * + * LWIP_PBUF_MEMPOOL(pool_name, number_elements, pbuf_payload_size, pool_description) + * creates a pool name MEMP_pool_name. description is used in stats.c + * This allocates enough space for the pbuf struct and a payload. + * (Example: pbuf_payload_size=0 allocates only size for the struct) + */ +LWIP_PBUF_MEMPOOL(PBUF, MEMP_NUM_PBUF, 0, "PBUF_REF/ROM") +LWIP_PBUF_MEMPOOL(PBUF_POOL, PBUF_POOL_SIZE, PBUF_POOL_BUFSIZE, "PBUF_POOL") + + +/* + * Allow for user-defined pools; this must be explicitly set in lwipopts.h + * since the default is to NOT look for lwippools.h + */ +#if MEMP_USE_CUSTOM_POOLS +#include "lwippools.h" +#endif /* MEMP_USE_CUSTOM_POOLS */ + +/* + * REQUIRED CLEANUP: Clear up so we don't get "multiply defined" error later + * (#undef is ignored for something that is not defined) + */ +#undef LWIP_MEMPOOL +#undef LWIP_MALLOC_MEMPOOL +#undef LWIP_MALLOC_MEMPOOL_START +#undef LWIP_MALLOC_MEMPOOL_END +#undef LWIP_PBUF_MEMPOOL diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/netbuf.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/netbuf.h new file mode 100644 index 0000000000000000000000000000000000000000..ab9ea33d1ae9841a2fa4d4f295dcf93ded1e5b35 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/netbuf.h @@ -0,0 +1,88 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_NETBUF_H__ +#define __LWIP_NETBUF_H__ + +#include "lwip/opt.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct netbuf { + struct pbuf *p, *ptr; + struct ip_addr *addr; + u16_t port; +#if LWIP_NETBUF_RECVINFO + struct ip_addr *toaddr; + u16_t toport; +#endif /* LWIP_NETBUF_RECVINFO */ +}; + +/* Network buffer functions: */ +struct netbuf * netbuf_new (void); +void netbuf_delete (struct netbuf *buf); +void * netbuf_alloc (struct netbuf *buf, u16_t size); +void netbuf_free (struct netbuf *buf); +err_t netbuf_ref (struct netbuf *buf, + const void *dataptr, u16_t size); +void netbuf_chain (struct netbuf *head, + struct netbuf *tail); + +u16_t netbuf_len (struct netbuf *buf); +err_t netbuf_data (struct netbuf *buf, + void **dataptr, u16_t *len); +s8_t netbuf_next (struct netbuf *buf); +void netbuf_first (struct netbuf *buf); + + +#define netbuf_copy_partial(buf, dataptr, len, offset) \ + pbuf_copy_partial((buf)->p, (dataptr), (len), (offset)) +#define netbuf_copy(buf,dataptr,len) netbuf_copy_partial(buf, dataptr, len, 0) +#define netbuf_take(buf, dataptr, len) pbuf_take((buf)->p, dataptr, len) +#define netbuf_len(buf) ((buf)->p->tot_len) +#define netbuf_fromaddr(buf) ((buf)->addr) +#define netbuf_fromport(buf) ((buf)->port) +#if LWIP_NETBUF_RECVINFO +#define netbuf_destaddr(buf) ((buf)->toaddr) +#define netbuf_destport(buf) ((buf)->toport) +#endif /* LWIP_NETBUF_RECVINFO */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_NETBUF_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/netdb.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/netdb.h new file mode 100644 index 0000000000000000000000000000000000000000..c59c3a442cced71142eebd5a392d37013df4203f --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/netdb.h @@ -0,0 +1,113 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ + +#include "lwip/opt.h" + +#if LWIP_DNS && LWIP_SOCKET + +#include /* for size_t */ + +#include "lwip/sockets.h" + +/* some rarely used options */ +#ifndef LWIP_DNS_API_DECLARE_H_ERRNO +#define LWIP_DNS_API_DECLARE_H_ERRNO 1 +#endif + +#ifndef LWIP_DNS_API_DEFINE_ERRORS +#define LWIP_DNS_API_DEFINE_ERRORS 1 +#endif + +#ifndef LWIP_DNS_API_DECLARE_STRUCTS +#define LWIP_DNS_API_DECLARE_STRUCTS 1 +#endif + +#if LWIP_DNS_API_DEFINE_ERRORS +/** Errors used by the DNS API functions, h_errno can be one of them */ +#define EAI_NONAME 200 +#define EAI_SERVICE 201 +#define EAI_FAIL 202 +#define EAI_MEMORY 203 + +#define HOST_NOT_FOUND 210 +#define NO_DATA 211 +#define NO_RECOVERY 212 +#define TRY_AGAIN 213 +#endif /* LWIP_DNS_API_DEFINE_ERRORS */ + +#if LWIP_DNS_API_DECLARE_STRUCTS +struct hostent { + char *h_name; /* Official name of the host. */ + char **h_aliases; /* A pointer to an array of pointers to alternative host names, + terminated by a null pointer. */ + int h_addrtype; /* Address type. */ + int h_length; /* The length, in bytes, of the address. */ + char **h_addr_list; /* A pointer to an array of pointers to network addresses (in + network byte order) for the host, terminated by a null pointer. */ +#define h_addr h_addr_list[0] /* for backward compatibility */ +}; + +struct addrinfo { + int ai_flags; /* Input flags. */ + int ai_family; /* Address family of socket. */ + int ai_socktype; /* Socket type. */ + int ai_protocol; /* Protocol of socket. */ + socklen_t ai_addrlen; /* Length of socket address. */ + struct sockaddr *ai_addr; /* Socket address of socket. */ + char *ai_canonname; /* Canonical name of service location. */ + struct addrinfo *ai_next; /* Pointer to next in list. */ +}; +#endif /* LWIP_DNS_API_DECLARE_STRUCTS */ + +#if LWIP_DNS_API_DECLARE_H_ERRNO +/* application accessable error code set by the DNS API functions */ +extern int h_errno; +#endif /* LWIP_DNS_API_DECLARE_H_ERRNO*/ + +struct hostent *lwip_gethostbyname(const char *name); +int lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf, + size_t buflen, struct hostent **result, int *h_errnop); +void lwip_freeaddrinfo(struct addrinfo *ai); +int lwip_getaddrinfo(const char *nodename, + const char *servname, + const struct addrinfo *hints, + struct addrinfo **res); + +#if LWIP_COMPAT_SOCKETS +#define gethostbyname(name) lwip_gethostbyname(name) +#define gethostbyname_r(name, ret, buf, buflen, result, h_errnop) \ + lwip_gethostbyname_r(name, ret, buf, buflen, result, h_errnop) +#define freeaddrinfo(addrinfo) lwip_freeaddrinfo(addrinfo) +#define getaddrinfo(nodname, servname, hints, res) \ + lwip_getaddrinfo(nodname, servname, hints, res) +#endif /* LWIP_COMPAT_SOCKETS */ + +#endif /* LWIP_DNS && LWIP_SOCKET */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/netif.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/netif.h new file mode 100644 index 0000000000000000000000000000000000000000..8e650d74d61ee97c18bf88be4bd5b57d8806007e --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/netif.h @@ -0,0 +1,265 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_NETIF_H__ +#define __LWIP_NETIF_H__ + +#include "lwip/opt.h" + +#define ENABLE_LOOPBACK (LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF) + +#include "lwip/err.h" + +#include "lwip/ip_addr.h" + +#include "lwip/inet.h" +#include "lwip/pbuf.h" +#if LWIP_DHCP +struct dhcp; +#endif +#if LWIP_AUTOIP +struct autoip; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* Throughout this file, IP addresses are expected to be in + * the same byte order as in IP_PCB. */ + +/** must be the maximum of all used hardware address lengths + across all types of interfaces in use */ +#define NETIF_MAX_HWADDR_LEN 6U + +/** TODO: define the use (where, when, whom) of netif flags */ + +/** whether the network interface is 'up'. this is + * a software flag used to control whether this network + * interface is enabled and processes traffic. + */ +#define NETIF_FLAG_UP 0x01U +/** if set, the netif has broadcast capability */ +#define NETIF_FLAG_BROADCAST 0x02U +/** if set, the netif is one end of a point-to-point connection */ +#define NETIF_FLAG_POINTTOPOINT 0x04U +/** if set, the interface is configured using DHCP */ +#define NETIF_FLAG_DHCP 0x08U +/** if set, the interface has an active link + * (set by the network interface driver) */ +#define NETIF_FLAG_LINK_UP 0x10U +/** if set, the netif is an device using ARP */ +#define NETIF_FLAG_ETHARP 0x20U +/** if set, the netif has IGMP capability */ +#define NETIF_FLAG_IGMP 0x40U + +/** Generic data structure used for all lwIP network interfaces. + * The following fields should be filled in by the initialization + * function for the device driver: hwaddr_len, hwaddr[], mtu, flags */ + +struct netif { + /** pointer to next in linked list */ + struct netif *next; + + /** IP address configuration in network byte order */ + struct ip_addr ip_addr; + struct ip_addr netmask; + struct ip_addr gw; + + /** This function is called by the network device driver + * to pass a packet up the TCP/IP stack. */ + err_t (* input)(struct pbuf *p, struct netif *inp); + /** This function is called by the IP module when it wants + * to send a packet on the interface. This function typically + * first resolves the hardware address, then sends the packet. */ + err_t (* output)(struct netif *netif, struct pbuf *p, + struct ip_addr *ipaddr); + /** This function is called by the ARP module when it wants + * to send a packet on the interface. This function outputs + * the pbuf as-is on the link medium. */ + err_t (* linkoutput)(struct netif *netif, struct pbuf *p); +#if LWIP_NETIF_STATUS_CALLBACK + /** This function is called when the netif state is set to up or down + */ + void (* status_callback)(struct netif *netif); +#endif /* LWIP_NETIF_STATUS_CALLBACK */ +#if LWIP_NETIF_LINK_CALLBACK + /** This function is called when the netif link is set to up or down + */ + void (* link_callback)(struct netif *netif); +#endif /* LWIP_NETIF_LINK_CALLBACK */ + /** This field can be set by the device driver and could point + * to state information for the device. */ + void *state; +#if LWIP_DHCP + /** the DHCP client state information for this netif */ + struct dhcp *dhcp; +#endif /* LWIP_DHCP */ +#if LWIP_AUTOIP + /** the AutoIP client state information for this netif */ + struct autoip *autoip; +#endif +#if LWIP_NETIF_HOSTNAME + /* the hostname for this netif, NULL is a valid value */ + char* hostname; +#endif /* LWIP_NETIF_HOSTNAME */ + /** maximum transfer unit (in bytes) */ + u16_t mtu; + /** number of bytes used in hwaddr */ + u8_t hwaddr_len; + /** link level hardware address of this interface */ + u8_t hwaddr[NETIF_MAX_HWADDR_LEN]; + /** flags (see NETIF_FLAG_ above) */ + u8_t flags; + /** descriptive abbreviation */ + char name[2]; + /** number of this interface */ + u8_t num; +#if LWIP_SNMP + /** link type (from "snmp_ifType" enum from snmp.h) */ + u8_t link_type; + /** (estimate) link speed */ + u32_t link_speed; + /** timestamp at last change made (up/down) */ + u32_t ts; + /** counters */ + u32_t ifinoctets; + u32_t ifinucastpkts; + u32_t ifinnucastpkts; + u32_t ifindiscards; + u32_t ifoutoctets; + u32_t ifoutucastpkts; + u32_t ifoutnucastpkts; + u32_t ifoutdiscards; +#endif /* LWIP_SNMP */ +#if LWIP_IGMP + /* This function could be called to add or delete a entry in the multicast filter table of the ethernet MAC.*/ + err_t (*igmp_mac_filter)( struct netif *netif, struct ip_addr *group, u8_t action); +#endif /* LWIP_IGMP */ +#if LWIP_NETIF_HWADDRHINT + u8_t *addr_hint; +#endif /* LWIP_NETIF_HWADDRHINT */ +#if ENABLE_LOOPBACK + /* List of packets to be queued for ourselves. */ + struct pbuf *loop_first; + struct pbuf *loop_last; +#if LWIP_LOOPBACK_MAX_PBUFS + u16_t loop_cnt_current; +#endif /* LWIP_LOOPBACK_MAX_PBUFS */ +#endif /* ENABLE_LOOPBACK */ +}; + +#if LWIP_SNMP +#define NETIF_INIT_SNMP(netif, type, speed) \ + /* use "snmp_ifType" enum from snmp.h for "type", snmp_ifType_ethernet_csmacd by example */ \ + netif->link_type = type; \ + /* your link speed here (units: bits per second) */ \ + netif->link_speed = speed; \ + netif->ts = 0; \ + netif->ifinoctets = 0; \ + netif->ifinucastpkts = 0; \ + netif->ifinnucastpkts = 0; \ + netif->ifindiscards = 0; \ + netif->ifoutoctets = 0; \ + netif->ifoutucastpkts = 0; \ + netif->ifoutnucastpkts = 0; \ + netif->ifoutdiscards = 0 +#else /* LWIP_SNMP */ +#define NETIF_INIT_SNMP(netif, type, speed) +#endif /* LWIP_SNMP */ + + +/** The list of network interfaces. */ +extern struct netif *netif_list; +/** The default network interface. */ +extern struct netif *netif_default; + +#define netif_init() /* Compatibility define, not init needed. */ + +struct netif *netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask, + struct ip_addr *gw, + void *state, + err_t (* init)(struct netif *netif), + err_t (* input)(struct pbuf *p, struct netif *netif)); + +void +netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask, + struct ip_addr *gw); +void netif_remove(struct netif * netif); + +/* Returns a network interface given its name. The name is of the form + "et0", where the first two letters are the "name" field in the + netif structure, and the digit is in the num field in the same + structure. */ +struct netif *netif_find(char *name); + +void netif_set_default(struct netif *netif); + +void netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr); +void netif_set_netmask(struct netif *netif, struct ip_addr *netmask); +void netif_set_gw(struct netif *netif, struct ip_addr *gw); + +void netif_set_up(struct netif *netif); +void netif_set_down(struct netif *netif); +u8_t netif_is_up(struct netif *netif); + +#if LWIP_NETIF_STATUS_CALLBACK +/* + * Set callback to be called when interface is brought up/down + */ +void netif_set_status_callback(struct netif *netif, void (* status_callback)(struct netif *netif)); +#endif /* LWIP_NETIF_STATUS_CALLBACK */ + +#if LWIP_NETIF_LINK_CALLBACK +void netif_set_link_up(struct netif *netif); +void netif_set_link_down(struct netif *netif); +u8_t netif_is_link_up(struct netif *netif); +/* + * Set callback to be called when link is brought up/down + */ +void netif_set_link_callback(struct netif *netif, void (* link_callback)(struct netif *netif)); +#endif /* LWIP_NETIF_LINK_CALLBACK */ + +#ifdef __cplusplus +} +#endif + +#if ENABLE_LOOPBACK +err_t netif_loop_output(struct netif *netif, struct pbuf *p, struct ip_addr *dest_ip); +void netif_poll(struct netif *netif); +#if !LWIP_NETIF_LOOPBACK_MULTITHREADING +void netif_poll_all(void); +#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */ +#endif /* ENABLE_LOOPBACK */ + +#endif /* __LWIP_NETIF_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/netifapi.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/netifapi.h new file mode 100644 index 0000000000000000000000000000000000000000..22d8690ea00c8dbd256520ded5a36ba5390e24b0 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/netifapi.h @@ -0,0 +1,107 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#ifndef __LWIP_NETIFAPI_H__ +#define __LWIP_NETIFAPI_H__ + +#include "lwip/opt.h" + +#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/sys.h" +#include "lwip/netif.h" +#include "lwip/dhcp.h" +#include "lwip/autoip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct netifapi_msg_msg { +#if !LWIP_TCPIP_CORE_LOCKING + sys_sem_t sem; +#endif /* !LWIP_TCPIP_CORE_LOCKING */ + err_t err; + struct netif *netif; + union { + struct { + struct ip_addr *ipaddr; + struct ip_addr *netmask; + struct ip_addr *gw; + void *state; + err_t (* init) (struct netif *netif); + err_t (* input)(struct pbuf *p, struct netif *netif); + } add; + struct { + void (* voidfunc)(struct netif *netif); + err_t (* errtfunc)(struct netif *netif); + } common; + } msg; +}; + +struct netifapi_msg { + void (* function)(struct netifapi_msg_msg *msg); + struct netifapi_msg_msg msg; +}; + + +/* API for application */ +err_t netifapi_netif_add ( struct netif *netif, + struct ip_addr *ipaddr, + struct ip_addr *netmask, + struct ip_addr *gw, + void *state, + err_t (* init)(struct netif *netif), + err_t (* input)(struct pbuf *p, struct netif *netif) ); + +err_t netifapi_netif_set_addr ( struct netif *netif, + struct ip_addr *ipaddr, + struct ip_addr *netmask, + struct ip_addr *gw ); + +err_t netifapi_netif_common ( struct netif *netif, + void (* voidfunc)(struct netif *netif), + err_t (* errtfunc)(struct netif *netif) ); + +#define netifapi_netif_remove(n) netifapi_netif_common(n, netif_remove, NULL) +#define netifapi_netif_set_up(n) netifapi_netif_common(n, netif_set_up, NULL) +#define netifapi_netif_set_down(n) netifapi_netif_common(n, netif_set_down, NULL) +#define netifapi_netif_set_default(n) netifapi_netif_common(n, netif_set_default, NULL) +#define netifapi_dhcp_start(n) netifapi_netif_common(n, NULL, dhcp_start) +#define netifapi_dhcp_stop(n) netifapi_netif_common(n, dhcp_stop, NULL) +#define netifapi_autoip_start(n) netifapi_netif_common(n, NULL, autoip_start) +#define netifapi_autoip_stop(n) netifapi_netif_common(n, NULL, autoip_stop) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_NETIF_API */ + +#endif /* __LWIP_NETIFAPI_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/opt.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/opt.h new file mode 100644 index 0000000000000000000000000000000000000000..a7cdbd8e7c4188372effece70cf7e3ce98ba14e8 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/opt.h @@ -0,0 +1,1842 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/** + * @file + * + * lwIP Options Configuration + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_OPT_H__ +#define __LWIP_OPT_H__ + +/* + * Include user defined options first. Anything not defined in these files + * will be set to standard values. Override anything you dont like! + */ +#include "lwipopts.h" +#include "lwip/debug.h" + +/* + ----------------------------------------------- + ---------- Platform specific locking ---------- + ----------------------------------------------- +*/ + +/** + * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain + * critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#ifndef SYS_LIGHTWEIGHT_PROT +#define SYS_LIGHTWEIGHT_PROT 0 +#endif + +/** + * NO_SYS==1: Provides VERY minimal functionality. Otherwise, + * use lwIP facilities. + */ +#ifndef NO_SYS +#define NO_SYS 0 +#endif + +/** + * MEMCPY: override this if you have a faster implementation at hand than the + * one included in your C library + */ +#ifndef MEMCPY +#define MEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/** + * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a + * call to memcpy() if the length is known at compile time and is small. + */ +#ifndef SMEMCPY +#define SMEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ +/** + * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library + * instead of the lwip internal allocator. Can save code size if you + * already use it. + */ +#ifndef MEM_LIBC_MALLOC +#define MEM_LIBC_MALLOC 0 +#endif + +/** +* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. +* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution +* speed and usage from interrupts! +*/ +#ifndef MEMP_MEM_MALLOC +#define MEMP_MEM_MALLOC 0 +#endif + +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> #define MEM_ALIGNMENT 4 + * 2 byte alignment -> #define MEM_ALIGNMENT 2 + */ +#ifndef MEM_ALIGNMENT +#define MEM_ALIGNMENT 1 +#endif + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#ifndef MEM_SIZE +#define MEM_SIZE 1600 +#endif + +/** + * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable + * amount of bytes before and after each memp element in every pool and fills + * it with a prominent default value. + * MEMP_OVERFLOW_CHECK == 0 no checking + * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed + * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time + * memp_malloc() or memp_free() is called (useful but slow!) + */ +#ifndef MEMP_OVERFLOW_CHECK +#define MEMP_OVERFLOW_CHECK 0 +#endif + +/** + * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make + * sure that there are no cycles in the linked lists. + */ +#ifndef MEMP_SANITY_CHECK +#define MEMP_SANITY_CHECK 0 +#endif + +/** + * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set + * of memory pools of various sizes. When mem_malloc is called, an element of + * the smallest pool that can provide the length needed is returned. + * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled. + */ +#ifndef MEM_USE_POOLS +#define MEM_USE_POOLS 0 +#endif + +/** + * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next + * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more + * reliable. */ +#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL +#define MEM_USE_POOLS_TRY_BIGGER_POOL 0 +#endif + +/** + * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h + * that defines additional pools beyond the "standard" ones required + * by lwIP. If you set this to 1, you must have lwippools.h in your + * inlude path somewhere. + */ +#ifndef MEMP_USE_CUSTOM_POOLS +#define MEMP_USE_CUSTOM_POOLS 0 +#endif + +/** + * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from + * interrupt context (or another context that doesn't allow waiting for a + * semaphore). + * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT, + * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs + * with each loop so that mem_free can run. + * + * ATTENTION: As you can see from the above description, this leads to dis-/ + * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc + * can need longer. + * + * If you don't want that, at least for NO_SYS=0, you can still use the following + * functions to enqueue a deallocation call which then runs in the tcpip_thread + * context: + * - pbuf_free_callback(p); + * - mem_free_callback(m); + */ +#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT +#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0 +#endif + +/* + ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ +*/ +/** + * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). + * If the application sends a lot of data out of ROM (or other static memory), + * this should be set high. + */ +#ifndef MEMP_NUM_PBUF +#define MEMP_NUM_PBUF 16 +#endif + +/** + * MEMP_NUM_RAW_PCB: Number of raw connection PCBs + * (requires the LWIP_RAW option) + */ +#ifndef MEMP_NUM_RAW_PCB +#define MEMP_NUM_RAW_PCB 4 +#endif + +/** + * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + * per active UDP "connection". + * (requires the LWIP_UDP option) + */ +#ifndef MEMP_NUM_UDP_PCB +#define MEMP_NUM_UDP_PCB 4 +#endif + +/** + * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB +#define MEMP_NUM_TCP_PCB 5 +#endif + +/** + * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB_LISTEN +#define MEMP_NUM_TCP_PCB_LISTEN 8 +#endif + +/** + * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_SEG +#define MEMP_NUM_TCP_SEG 16 +#endif + +/** + * MEMP_NUM_REASSDATA: the number of simultaneously IP packets queued for + * reassembly (whole packets, not fragments!) + */ +#ifndef MEMP_NUM_REASSDATA +#define MEMP_NUM_REASSDATA 5 +#endif + +/** + * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing + * packets (pbufs) that are waiting for an ARP request (to resolve + * their destination address) to finish. + * (requires the ARP_QUEUEING option) + */ +#ifndef MEMP_NUM_ARP_QUEUE +#define MEMP_NUM_ARP_QUEUE 30 +#endif + +/** + * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces + * can be members et the same time (one per netif - allsystems group -, plus one + * per netif membership). + * (requires the LWIP_IGMP option) + */ +#ifndef MEMP_NUM_IGMP_GROUP +#define MEMP_NUM_IGMP_GROUP 8 +#endif + +/** + * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. + * (requires NO_SYS==0) + */ +#ifndef MEMP_NUM_SYS_TIMEOUT +#define MEMP_NUM_SYS_TIMEOUT 3 +#endif + +/** + * MEMP_NUM_NETBUF: the number of struct netbufs. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETBUF +#define MEMP_NUM_NETBUF 2 +#endif + +/** + * MEMP_NUM_NETCONN: the number of struct netconns. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETCONN +#define MEMP_NUM_NETCONN 4 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used + * for callback/timeout API communication. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_API +#define MEMP_NUM_TCPIP_MSG_API 8 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used + * for incoming packets. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_INPKT +#define MEMP_NUM_TCPIP_MSG_INPKT 8 +#endif + +/** + * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + */ +#ifndef PBUF_POOL_SIZE +#define PBUF_POOL_SIZE 16 +#endif + +/* + --------------------------------- + ---------- ARP options ---------- + --------------------------------- +*/ +/** + * LWIP_ARP==1: Enable ARP functionality. + */ +#ifndef LWIP_ARP +#define LWIP_ARP 1 +#endif + +/** + * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. + */ +#ifndef ARP_TABLE_SIZE +#define ARP_TABLE_SIZE 10 +#endif + +/** + * ARP_QUEUEING==1: Outgoing packets are queued during hardware address + * resolution. + */ +#ifndef ARP_QUEUEING +#define ARP_QUEUEING 1 +#endif + +/** + * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be + * updated with the source MAC and IP addresses supplied in the packet. + * You may want to disable this if you do not trust LAN peers to have the + * correct addresses, or as a limited approach to attempt to handle + * spoofing. If disabled, lwIP will need to make a new ARP request if + * the peer is not already in the ARP table, adding a little latency. + */ +#ifndef ETHARP_TRUST_IP_MAC +#define ETHARP_TRUST_IP_MAC 1 +#endif + +/** + * ETHARP_SUPPORT_VLAN==1: support receiving ethernet packets with VLAN header. + * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check. + * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted. + * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted. + */ +#ifndef ETHARP_SUPPORT_VLAN +#define ETHARP_SUPPORT_VLAN 0 +#endif + +/* + -------------------------------- + ---------- IP options ---------- + -------------------------------- +*/ +/** + * IP_FORWARD==1: Enables the ability to forward IP packets across network + * interfaces. If you are going to run lwIP on a device with only one network + * interface, define this to 0. + */ +#ifndef IP_FORWARD +#define IP_FORWARD 0 +#endif + +/** + * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. + * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. + * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). + */ +#ifndef IP_OPTIONS_ALLOWED +#define IP_OPTIONS_ALLOWED 1 +#endif + +/** + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via IP_FRAG. + */ +#ifndef IP_REASSEMBLY +#define IP_REASSEMBLY 1 +#endif + +/** + * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#ifndef IP_FRAG +#define IP_FRAG 1 +#endif + +/** + * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) + * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived + * in this time, the whole packet is discarded. + */ +#ifndef IP_REASS_MAXAGE +#define IP_REASS_MAXAGE 3 +#endif + +/** + * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. + * Since the received pbufs are enqueued, be sure to configure + * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive + * packets even if the maximum amount of fragments is enqueued for reassembly! + */ +#ifndef IP_REASS_MAX_PBUFS +#define IP_REASS_MAX_PBUFS 10 +#endif + +/** + * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP + * fragmentation. Otherwise pbufs are allocated and reference the original + * packet data to be fragmented. + */ +#ifndef IP_FRAG_USES_STATIC_BUF +#define IP_FRAG_USES_STATIC_BUF 1 +#endif + +/** + * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer + * (requires IP_FRAG_USES_STATIC_BUF==1) + */ +#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU) +#define IP_FRAG_MAX_MTU 1500 +#endif + +/** + * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. + */ +#ifndef IP_DEFAULT_TTL +#define IP_DEFAULT_TTL 255 +#endif + +/** + * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast + * filter per pcb on udp and raw send operations. To enable broadcast filter + * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1. + */ +#ifndef IP_SOF_BROADCAST +#define IP_SOF_BROADCAST 0 +#endif + +/** + * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast + * filter on recv operations. + */ +#ifndef IP_SOF_BROADCAST_RECV +#define IP_SOF_BROADCAST_RECV 0 +#endif + +/* + ---------------------------------- + ---------- ICMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_ICMP==1: Enable ICMP module inside the IP stack. + * Be careful, disable that make your product non-compliant to RFC1122 + */ +#ifndef LWIP_ICMP +#define LWIP_ICMP 1 +#endif + +/** + * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. + */ +#ifndef ICMP_TTL +#define ICMP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only) + */ +#ifndef LWIP_BROADCAST_PING +#define LWIP_BROADCAST_PING 0 +#endif + +/** + * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only) + */ +#ifndef LWIP_MULTICAST_PING +#define LWIP_MULTICAST_PING 0 +#endif + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef LWIP_RAW +#define LWIP_RAW 1 +#endif + +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef RAW_TTL +#define RAW_TTL (IP_DEFAULT_TTL) +#endif + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#ifndef LWIP_DHCP +#define LWIP_DHCP 0 +#endif + +/** + * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. + */ +#ifndef DHCP_DOES_ARP_CHECK +#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP)) +#endif + +/* + ------------------------------------ + ---------- AUTOIP options ---------- + ------------------------------------ +*/ +/** + * LWIP_AUTOIP==1: Enable AUTOIP module. + */ +#ifndef LWIP_AUTOIP +#define LWIP_AUTOIP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on + * the same interface at the same time. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP +#define LWIP_DHCP_AUTOIP_COOP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes + * that should be sent before falling back on AUTOIP. This can be set + * as low as 1 to get an AutoIP address very quickly, but you should + * be prepared to handle a changing IP address when DHCP overrides + * AutoIP. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES +#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 +#endif + +/* + ---------------------------------- + ---------- SNMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP + * transport. + */ +#ifndef LWIP_SNMP +#define LWIP_SNMP 0 +#endif + +/** + * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will + * allow. At least one request buffer is required. + */ +#ifndef SNMP_CONCURRENT_REQUESTS +#define SNMP_CONCURRENT_REQUESTS 1 +#endif + +/** + * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap + * destination is required + */ +#ifndef SNMP_TRAP_DESTINATIONS +#define SNMP_TRAP_DESTINATIONS 1 +#endif + +/** + * SNMP_PRIVATE_MIB: + */ +#ifndef SNMP_PRIVATE_MIB +#define SNMP_PRIVATE_MIB 0 +#endif + +/** + * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not + * a safe action and disabled when SNMP_SAFE_REQUESTS = 1). + * Unsafe requests are disabled by default! + */ +#ifndef SNMP_SAFE_REQUESTS +#define SNMP_SAFE_REQUESTS 1 +#endif + +/* + ---------------------------------- + ---------- IGMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_IGMP==1: Turn on IGMP module. + */ +#ifndef LWIP_IGMP +#define LWIP_IGMP 0 +#endif + +/* + ---------------------------------- + ---------- DNS options ----------- + ---------------------------------- +*/ +/** + * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS + * transport. + */ +#ifndef LWIP_DNS +#define LWIP_DNS 0 +#endif + +/** DNS maximum number of entries to maintain locally. */ +#ifndef DNS_TABLE_SIZE +#define DNS_TABLE_SIZE 4 +#endif + +/** DNS maximum host name length supported in the name table. */ +#ifndef DNS_MAX_NAME_LENGTH +#define DNS_MAX_NAME_LENGTH 256 +#endif + +/** The maximum of DNS servers */ +#ifndef DNS_MAX_SERVERS +#define DNS_MAX_SERVERS 2 +#endif + +/** DNS do a name checking between the query and the response. */ +#ifndef DNS_DOES_NAME_CHECK +#define DNS_DOES_NAME_CHECK 1 +#endif + +/** DNS use a local buffer if DNS_USES_STATIC_BUF=0, a static one if + DNS_USES_STATIC_BUF=1, or a dynamic one if DNS_USES_STATIC_BUF=2. + The buffer will be of size DNS_MSG_SIZE */ +#ifndef DNS_USES_STATIC_BUF +#define DNS_USES_STATIC_BUF 1 +#endif + +/** DNS message max. size. Default value is RFC compliant. */ +#ifndef DNS_MSG_SIZE +#define DNS_MSG_SIZE 512 +#endif + +/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, + * you have to define + * #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}} + * (an array of structs name/address, where address is an u32_t in network + * byte order). + * + * Instead, you can also use an external function: + * #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name) + * that returns the IP address or INADDR_NONE if not found. + */ +#ifndef DNS_LOCAL_HOSTLIST +#define DNS_LOCAL_HOSTLIST 0 +#endif /* DNS_LOCAL_HOSTLIST */ + +/** If this is turned on, the local host-list can be dynamically changed + * at runtime. */ +#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC +#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0 +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +/* + --------------------------------- + ---------- UDP options ---------- + --------------------------------- +*/ +/** + * LWIP_UDP==1: Turn on UDP. + */ +#ifndef LWIP_UDP +#define LWIP_UDP 1 +#endif + +/** + * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) + */ +#ifndef LWIP_UDPLITE +#define LWIP_UDPLITE 0 +#endif + +/** + * UDP_TTL: Default Time-To-Live value. + */ +#ifndef UDP_TTL +#define UDP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf. + */ +#ifndef LWIP_NETBUF_RECVINFO +#define LWIP_NETBUF_RECVINFO 0 +#endif + +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ +/** + * LWIP_TCP==1: Turn on TCP. + */ +#ifndef LWIP_TCP +#define LWIP_TCP 1 +#endif + +/** + * TCP_TTL: Default Time-To-Live value. + */ +#ifndef TCP_TTL +#define TCP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * TCP_WND: The size of a TCP window. This must be at least + * (2 * TCP_MSS) for things to work well + */ +#ifndef TCP_WND +#define TCP_WND (4 * TCP_MSS) +#endif + +/** + * TCP_MAXRTX: Maximum number of retransmissions of data segments. + */ +#ifndef TCP_MAXRTX +#define TCP_MAXRTX 12 +#endif + +/** + * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. + */ +#ifndef TCP_SYNMAXRTX +#define TCP_SYNMAXRTX 6 +#endif + +/** + * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. + * Define to 0 if your device is low on memory. + */ +#ifndef TCP_QUEUE_OOSEQ +#define TCP_QUEUE_OOSEQ (LWIP_TCP) +#endif + +/** + * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default, + * you might want to increase this.) + * For the receive side, this MSS is advertised to the remote side + * when opening a connection. For the transmit size, this MSS sets + * an upper limit on the MSS advertised by the remote host. + */ +#ifndef TCP_MSS +#define TCP_MSS 536 +#endif + +/** + * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really + * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which + * reflects the available reassembly buffer size at the remote host) and the + * largest size permitted by the IP layer" (RFC 1122) + * Setting this to 1 enables code that checks TCP_MSS against the MTU of the + * netif used for a connection and limits the MSS if it would be too big otherwise. + */ +#ifndef TCP_CALCULATE_EFF_SEND_MSS +#define TCP_CALCULATE_EFF_SEND_MSS 1 +#endif + + +/** + * TCP_SND_BUF: TCP sender buffer space (bytes). + */ +#ifndef TCP_SND_BUF +#define TCP_SND_BUF 256 +#endif + +/** + * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least + * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. + */ +#ifndef TCP_SND_QUEUELEN +#define TCP_SND_QUEUELEN (4 * (TCP_SND_BUF)/(TCP_MSS)) +#endif + +/** + * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than or equal + * to TCP_SND_BUF. It is the amount of space which must be available in the + * TCP snd_buf for select to return writable. + */ +#ifndef TCP_SNDLOWAT +#define TCP_SNDLOWAT ((TCP_SND_BUF)/2) +#endif + +/** + * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. + */ +#ifndef TCP_LISTEN_BACKLOG +#define TCP_LISTEN_BACKLOG 0 +#endif + +/** + * The maximum allowed backlog for TCP listen netconns. + * This backlog is used unless another is explicitly specified. + * 0xff is the maximum (u8_t). + */ +#ifndef TCP_DEFAULT_LISTEN_BACKLOG +#define TCP_DEFAULT_LISTEN_BACKLOG 0xff +#endif + +/** + * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option. + */ +#ifndef LWIP_TCP_TIMESTAMPS +#define LWIP_TCP_TIMESTAMPS 0 +#endif + +/** + * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an + * explicit window update + */ +#ifndef TCP_WND_UPDATE_THRESHOLD +#define TCP_WND_UPDATE_THRESHOLD (TCP_WND / 4) +#endif + +/** + * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1. + * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all + * events (accept, sent, etc) that happen in the system. + * LWIP_CALLBACK_API==1: The PCB callback function is called directly + * for the event. + */ +#ifndef LWIP_EVENT_API +#define LWIP_EVENT_API 0 +#define LWIP_CALLBACK_API 1 +#else +#define LWIP_EVENT_API 1 +#define LWIP_CALLBACK_API 0 +#endif + + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ +/** + * PBUF_LINK_HLEN: the number of bytes that should be allocated for a + * link level header. The default is 14, the standard value for + * Ethernet. + */ +#ifndef PBUF_LINK_HLEN +#define PBUF_LINK_HLEN 14 +#endif + +/** + * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is + * designed to accomodate single full size TCP frame in one pbuf, including + * TCP_MSS, IP header, and link header. + */ +#ifndef PBUF_POOL_BUFSIZE +#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN) +#endif + +/* + ------------------------------------------------ + ---------- Network Interfaces options ---------- + ------------------------------------------------ +*/ +/** + * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname + * field. + */ +#ifndef LWIP_NETIF_HOSTNAME +#define LWIP_NETIF_HOSTNAME 0 +#endif + +/** + * LWIP_NETIF_API==1: Support netif api (in netifapi.c) + */ +#ifndef LWIP_NETIF_API +#define LWIP_NETIF_API 0 +#endif + +/** + * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface + * changes its up/down status (i.e., due to DHCP IP acquistion) + */ +#ifndef LWIP_NETIF_STATUS_CALLBACK +#define LWIP_NETIF_STATUS_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#ifndef LWIP_NETIF_LINK_CALLBACK +#define LWIP_NETIF_LINK_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table + * indices) in struct netif. TCP and UDP can make use of this to prevent + * scanning the ARP table for every sent packet. While this is faster for big + * ARP tables or many concurrent connections, it might be counterproductive + * if you have a tiny ARP table or if there never are concurrent connections. + */ +#ifndef LWIP_NETIF_HWADDRHINT +#define LWIP_NETIF_HWADDRHINT 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP + * address equal to the netif IP address, looping them back up the stack. + */ +#ifndef LWIP_NETIF_LOOPBACK +#define LWIP_NETIF_LOOPBACK 0 +#endif + +/** + * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback + * sending for each netif (0 = disabled) + */ +#ifndef LWIP_LOOPBACK_MAX_PBUFS +#define LWIP_LOOPBACK_MAX_PBUFS 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in + * the system, as netifs must change how they behave depending on this setting + * for the LWIP_NETIF_LOOPBACK option to work. + * Setting this is needed to avoid reentering non-reentrant functions like + * tcp_input(). + * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a + * multithreaded environment like tcpip.c. In this case, netif->input() + * is called directly. + * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup. + * The packets are put on a list and netif_poll() must be called in + * the main application loop. + */ +#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING +#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS) +#endif + +/** + * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data + * to be sent into one single pbuf. This is for compatibility with DMA-enabled + * MACs that do not support scatter-gather. + * Beware that this might involve CPU-memcpy before transmitting that would not + * be needed without this flag! Use this only if you need to! + * + * @todo: TCP and IP-frag do not work with this, yet: + */ +#ifndef LWIP_NETIF_TX_SINGLE_PBUF +#define LWIP_NETIF_TX_SINGLE_PBUF 0 +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + +/* + ------------------------------------ + ---------- LOOPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c + */ +#ifndef LWIP_HAVE_LOOPIF +#define LWIP_HAVE_LOOPIF 0 +#endif + +/* + ------------------------------------ + ---------- SLIPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c + */ +#ifndef LWIP_HAVE_SLIPIF +#define LWIP_HAVE_SLIPIF 0 +#endif + +/* + ------------------------------------ + ---------- Thread options ---------- + ------------------------------------ +*/ +/** + * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. + */ +#ifndef TCPIP_THREAD_NAME +#define TCPIP_THREAD_NAME "tcpip_thread" +#endif + +/** + * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_STACKSIZE +#define TCPIP_THREAD_STACKSIZE 0 +#endif + +/** + * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_PRIO +#define TCPIP_THREAD_PRIO 1 +#endif + +/** + * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when tcpip_init is called. + */ +#ifndef TCPIP_MBOX_SIZE +#define TCPIP_MBOX_SIZE 0 +#endif + +/** + * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread. + */ +#ifndef SLIPIF_THREAD_NAME +#define SLIPIF_THREAD_NAME "slipif_loop" +#endif + +/** + * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_STACKSIZE +#define SLIPIF_THREAD_STACKSIZE 0 +#endif + +/** + * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_PRIO +#define SLIPIF_THREAD_PRIO 1 +#endif + +/** + * PPP_THREAD_NAME: The name assigned to the pppMain thread. + */ +#ifndef PPP_THREAD_NAME +#define PPP_THREAD_NAME "pppMain" +#endif + +/** + * PPP_THREAD_STACKSIZE: The stack size used by the pppMain thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_STACKSIZE +#define PPP_THREAD_STACKSIZE 0 +#endif + +/** + * PPP_THREAD_PRIO: The priority assigned to the pppMain thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_PRIO +#define PPP_THREAD_PRIO 1 +#endif + +/** + * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread. + */ +#ifndef DEFAULT_THREAD_NAME +#define DEFAULT_THREAD_NAME "lwIP" +#endif + +/** + * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_STACKSIZE +#define DEFAULT_THREAD_STACKSIZE 0 +#endif + +/** + * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_PRIO +#define DEFAULT_THREAD_PRIO 1 +#endif + +/** + * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_RAW_RECVMBOX_SIZE +#define DEFAULT_RAW_RECVMBOX_SIZE 0 +#endif + +/** + * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_UDP_RECVMBOX_SIZE +#define DEFAULT_UDP_RECVMBOX_SIZE 0 +#endif + +/** + * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_TCP_RECVMBOX_SIZE +#define DEFAULT_TCP_RECVMBOX_SIZE 0 +#endif + +/** + * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when the acceptmbox is created. + */ +#ifndef DEFAULT_ACCEPTMBOX_SIZE +#define DEFAULT_ACCEPTMBOX_SIZE 0 +#endif + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING +#define LWIP_TCPIP_CORE_LOCKING 0 +#endif + +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#ifndef LWIP_NETCONN +#define LWIP_NETCONN 1 +#endif + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#ifndef LWIP_SOCKET +#define LWIP_SOCKET 1 +#endif + +/** + * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names. + * (only used if you use sockets.c) + */ +#ifndef LWIP_COMPAT_SOCKETS +#define LWIP_COMPAT_SOCKETS 1 +#endif + +/** + * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names. + * Disable this option if you use a POSIX operating system that uses the same + * names (read, write & close). (only used if you use sockets.c) + */ +#ifndef LWIP_POSIX_SOCKETS_IO_NAMES +#define LWIP_POSIX_SOCKETS_IO_NAMES 1 +#endif + +/** + * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT + * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set + * in seconds. (does not require sockets.c, and will affect tcp.c) + */ +#ifndef LWIP_TCP_KEEPALIVE +#define LWIP_TCP_KEEPALIVE 1 +#endif + +/** + * LWIP_SO_RCVTIMEO==1: Enable SO_RCVTIMEO processing. + */ +#ifndef LWIP_SO_RCVTIMEO +#define LWIP_SO_RCVTIMEO 0 +#endif + +/** + * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. + */ +#ifndef LWIP_SO_RCVBUF +#define LWIP_SO_RCVBUF 0 +#endif + +/** + * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize. + */ +#ifndef RECV_BUFSIZE_DEFAULT +#define RECV_BUFSIZE_DEFAULT INT_MAX +#endif + +/** + * SO_REUSE==1: Enable SO_REUSEADDR and SO_REUSEPORT options. DO NOT USE! + */ +#ifndef SO_REUSE +#define SO_REUSE 0 +#endif + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#ifndef LWIP_STATS +#define LWIP_STATS 1 +#endif + +#if LWIP_STATS + +/** + * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. + */ +#ifndef LWIP_STATS_DISPLAY +#define LWIP_STATS_DISPLAY 0 +#endif + +/** + * LINK_STATS==1: Enable link stats. + */ +#ifndef LINK_STATS +#define LINK_STATS 1 +#endif + +/** + * ETHARP_STATS==1: Enable etharp stats. + */ +#ifndef ETHARP_STATS +#define ETHARP_STATS (LWIP_ARP) +#endif + +/** + * IP_STATS==1: Enable IP stats. + */ +#ifndef IP_STATS +#define IP_STATS 1 +#endif + +/** + * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is + * on if using either frag or reass. + */ +#ifndef IPFRAG_STATS +#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG) +#endif + +/** + * ICMP_STATS==1: Enable ICMP stats. + */ +#ifndef ICMP_STATS +#define ICMP_STATS 1 +#endif + +/** + * IGMP_STATS==1: Enable IGMP stats. + */ +#ifndef IGMP_STATS +#define IGMP_STATS (LWIP_IGMP) +#endif + +/** + * UDP_STATS==1: Enable UDP stats. Default is on if + * UDP enabled, otherwise off. + */ +#ifndef UDP_STATS +#define UDP_STATS (LWIP_UDP) +#endif + +/** + * TCP_STATS==1: Enable TCP stats. Default is on if TCP + * enabled, otherwise off. + */ +#ifndef TCP_STATS +#define TCP_STATS (LWIP_TCP) +#endif + +/** + * MEM_STATS==1: Enable mem.c stats. + */ +#ifndef MEM_STATS +#define MEM_STATS ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0)) +#endif + +/** + * MEMP_STATS==1: Enable memp.c pool stats. + */ +#ifndef MEMP_STATS +#define MEMP_STATS (MEMP_MEM_MALLOC == 0) +#endif + +/** + * SYS_STATS==1: Enable system stats (sem and mbox counts, etc). + */ +#ifndef SYS_STATS +#define SYS_STATS (NO_SYS == 0) +#endif + +#else + +#define LINK_STATS 0 +#define IP_STATS 0 +#define IPFRAG_STATS 0 +#define ICMP_STATS 0 +#define IGMP_STATS 0 +#define UDP_STATS 0 +#define TCP_STATS 0 +#define MEM_STATS 0 +#define MEMP_STATS 0 +#define SYS_STATS 0 +#define LWIP_STATS_DISPLAY 0 + +#endif /* LWIP_STATS */ + +/* + --------------------------------- + ---------- PPP options ---------- + --------------------------------- +*/ +/** + * PPP_SUPPORT==1: Enable PPP. + */ +#ifndef PPP_SUPPORT +#define PPP_SUPPORT 0 +#endif + +/** + * PPPOE_SUPPORT==1: Enable PPP Over Ethernet + */ +#ifndef PPPOE_SUPPORT +#define PPPOE_SUPPORT 0 +#endif + +/** + * PPPOS_SUPPORT==1: Enable PPP Over Serial + */ +#ifndef PPPOS_SUPPORT +#define PPPOS_SUPPORT PPP_SUPPORT +#endif + +#if PPP_SUPPORT + +/** + * NUM_PPP: Max PPP sessions. + */ +#ifndef NUM_PPP +#define NUM_PPP 1 +#endif + +/** + * PAP_SUPPORT==1: Support PAP. + */ +#ifndef PAP_SUPPORT +#define PAP_SUPPORT 0 +#endif + +/** + * CHAP_SUPPORT==1: Support CHAP. + */ +#ifndef CHAP_SUPPORT +#define CHAP_SUPPORT 0 +#endif + +/** + * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef MSCHAP_SUPPORT +#define MSCHAP_SUPPORT 0 +#endif + +/** + * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CBCP_SUPPORT +#define CBCP_SUPPORT 0 +#endif + +/** + * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CCP_SUPPORT +#define CCP_SUPPORT 0 +#endif + +/** + * VJ_SUPPORT==1: Support VJ header compression. + */ +#ifndef VJ_SUPPORT +#define VJ_SUPPORT 0 +#endif + +/** + * MD5_SUPPORT==1: Support MD5 (see also CHAP). + */ +#ifndef MD5_SUPPORT +#define MD5_SUPPORT 0 +#endif + +/* + * Timeouts + */ +#ifndef FSM_DEFTIMEOUT +#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef FSM_DEFMAXTERMREQS +#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXCONFREQS +#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXNAKLOOPS +#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ +#endif + +#ifndef UPAP_DEFTIMEOUT +#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */ +#endif + +#ifndef UPAP_DEFREQTIME +#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ +#endif + +#ifndef CHAP_DEFTIMEOUT +#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef CHAP_DEFTRANSMITS +#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */ +#endif + +/* Interval in seconds between keepalive echo requests, 0 to disable. */ +#ifndef LCP_ECHOINTERVAL +#define LCP_ECHOINTERVAL 0 +#endif + +/* Number of unanswered echo requests before failure. */ +#ifndef LCP_MAXECHOFAILS +#define LCP_MAXECHOFAILS 3 +#endif + +/* Max Xmit idle time (in jiffies) before resend flag char. */ +#ifndef PPP_MAXIDLEFLAG +#define PPP_MAXIDLEFLAG 100 +#endif + +/* + * Packet sizes + * + * Note - lcp shouldn't be allowed to negotiate stuff outside these + * limits. See lcp.h in the pppd directory. + * (XXX - these constants should simply be shared by lcp.c instead + * of living in lcp.h) + */ +#define PPP_MTU 1500 /* Default MTU (size of Info field) */ +#ifndef PPP_MAXMTU +/* #define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) */ +#define PPP_MAXMTU 1500 /* Largest MTU we allow */ +#endif +#define PPP_MINMTU 64 +#define PPP_MRU 1500 /* default MRU = max length of info field */ +#define PPP_MAXMRU 1500 /* Largest MRU we allow */ +#ifndef PPP_DEFMRU +#define PPP_DEFMRU 296 /* Try for this */ +#endif +#define PPP_MINMRU 128 /* No MRUs below this */ + +#ifndef MAXNAMELEN +#define MAXNAMELEN 256 /* max length of hostname or name for auth */ +#endif +#ifndef MAXSECRETLEN +#define MAXSECRETLEN 256 /* max length of password or secret */ +#endif + +#endif /* PPP_SUPPORT */ + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +/** + * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. + */ +#ifndef CHECKSUM_GEN_IP +#define CHECKSUM_GEN_IP 1 +#endif + +/** + * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. + */ +#ifndef CHECKSUM_GEN_UDP +#define CHECKSUM_GEN_UDP 1 +#endif + +/** + * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets. + */ +#ifndef CHECKSUM_GEN_TCP +#define CHECKSUM_GEN_TCP 1 +#endif + +/** + * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. + */ +#ifndef CHECKSUM_CHECK_IP +#define CHECKSUM_CHECK_IP 1 +#endif + +/** + * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. + */ +#ifndef CHECKSUM_CHECK_UDP +#define CHECKSUM_CHECK_UDP 1 +#endif + +/** + * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets. + */ +#ifndef CHECKSUM_CHECK_TCP +#define CHECKSUM_CHECK_TCP 1 +#endif + +/* + --------------------------------------- + ---------- Debugging options ---------- + --------------------------------------- +*/ +/** + * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is + * compared against this value. If it is smaller, then debugging + * messages are written. + */ +#ifndef LWIP_DBG_MIN_LEVEL +#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL +#endif + +/** + * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable + * debug messages of certain types. + */ +#ifndef LWIP_DBG_TYPES_ON +#define LWIP_DBG_TYPES_ON LWIP_DBG_ON +#endif + +/** + * ETHARP_DEBUG: Enable debugging in etharp.c. + */ +#ifndef ETHARP_DEBUG +#define ETHARP_DEBUG LWIP_DBG_OFF +#endif + +/** + * NETIF_DEBUG: Enable debugging in netif.c. + */ +#ifndef NETIF_DEBUG +#define NETIF_DEBUG LWIP_DBG_OFF +#endif + +/** + * PBUF_DEBUG: Enable debugging in pbuf.c. + */ +#ifndef PBUF_DEBUG +#define PBUF_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_LIB_DEBUG: Enable debugging in api_lib.c. + */ +#ifndef API_LIB_DEBUG +#define API_LIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_MSG_DEBUG: Enable debugging in api_msg.c. + */ +#ifndef API_MSG_DEBUG +#define API_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SOCKETS_DEBUG: Enable debugging in sockets.c. + */ +#ifndef SOCKETS_DEBUG +#define SOCKETS_DEBUG LWIP_DBG_OFF +#endif + +/** + * ICMP_DEBUG: Enable debugging in icmp.c. + */ +#ifndef ICMP_DEBUG +#define ICMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IGMP_DEBUG: Enable debugging in igmp.c. + */ +#ifndef IGMP_DEBUG +#define IGMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * INET_DEBUG: Enable debugging in inet.c. + */ +#ifndef INET_DEBUG +#define INET_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_DEBUG: Enable debugging for IP. + */ +#ifndef IP_DEBUG +#define IP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass. + */ +#ifndef IP_REASS_DEBUG +#define IP_REASS_DEBUG LWIP_DBG_OFF +#endif + +/** + * RAW_DEBUG: Enable debugging in raw.c. + */ +#ifndef RAW_DEBUG +#define RAW_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEM_DEBUG: Enable debugging in mem.c. + */ +#ifndef MEM_DEBUG +#define MEM_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEMP_DEBUG: Enable debugging in memp.c. + */ +#ifndef MEMP_DEBUG +#define MEMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SYS_DEBUG: Enable debugging in sys.c. + */ +#ifndef SYS_DEBUG +#define SYS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_DEBUG: Enable debugging for TCP. + */ +#ifndef TCP_DEBUG +#define TCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. + */ +#ifndef TCP_INPUT_DEBUG +#define TCP_INPUT_DEBUG LWIP_DBG_ON +#endif + +/** + * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit. + */ +#ifndef TCP_FR_DEBUG +#define TCP_FR_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit + * timeout. + */ +#ifndef TCP_RTO_DEBUG +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_CWND_DEBUG: Enable debugging for TCP congestion window. + */ +#ifndef TCP_CWND_DEBUG +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating. + */ +#ifndef TCP_WND_DEBUG +#define TCP_WND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. + */ +#ifndef TCP_OUTPUT_DEBUG +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RST_DEBUG: Enable debugging for TCP with the RST message. + */ +#ifndef TCP_RST_DEBUG +#define TCP_RST_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths. + */ +#ifndef TCP_QLEN_DEBUG +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#endif + +/** + * UDP_DEBUG: Enable debugging in UDP. + */ +#ifndef UDP_DEBUG +#define UDP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCPIP_DEBUG: Enable debugging in tcpip.c. + */ +#ifndef TCPIP_DEBUG +#define TCPIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * PPP_DEBUG: Enable debugging for PPP. + */ +#ifndef PPP_DEBUG +#define PPP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SLIP_DEBUG: Enable debugging in slipif.c. + */ +#ifndef SLIP_DEBUG +#define SLIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * DHCP_DEBUG: Enable debugging in dhcp.c. + */ +#ifndef DHCP_DEBUG +#define DHCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * AUTOIP_DEBUG: Enable debugging in autoip.c. + */ +#ifndef AUTOIP_DEBUG +#define AUTOIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MSG_DEBUG: Enable debugging for SNMP messages. + */ +#ifndef SNMP_MSG_DEBUG +#define SNMP_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs. + */ +#ifndef SNMP_MIB_DEBUG +#define SNMP_MIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * DNS_DEBUG: Enable debugging for DNS. + */ +#ifndef DNS_DEBUG +#define DNS_DEBUG LWIP_DBG_OFF +#endif + +#endif /* __LWIP_OPT_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/pbuf.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/pbuf.h new file mode 100644 index 0000000000000000000000000000000000000000..8ca61b176ff557d4003ccf5e3f8edab7a805c773 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/pbuf.h @@ -0,0 +1,122 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __LWIP_PBUF_H__ +#define __LWIP_PBUF_H__ + +#include "lwip/opt.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PBUF_TRANSPORT_HLEN 20 +#define PBUF_IP_HLEN 20 + +typedef enum { + PBUF_TRANSPORT, + PBUF_IP, + PBUF_LINK, + PBUF_RAW +} pbuf_layer; + +typedef enum { + PBUF_RAM, /* pbuf data is stored in RAM */ + PBUF_ROM, /* pbuf data is stored in ROM */ + PBUF_REF, /* pbuf comes from the pbuf pool */ + PBUF_POOL /* pbuf payload refers to RAM */ +} pbuf_type; + + +/** indicates this packet's data should be immediately passed to the application */ +#define PBUF_FLAG_PUSH 0x01U + +struct pbuf { + /** next pbuf in singly linked pbuf chain */ + struct pbuf *next; + + /** pointer to the actual data in the buffer */ + void *payload; + + /** + * total length of this buffer and all next buffers in chain + * belonging to the same packet. + * + * For non-queue packet chains this is the invariant: + * p->tot_len == p->len + (p->next? p->next->tot_len: 0) + */ + u16_t tot_len; + + /** length of this buffer */ + u16_t len; + + /** pbuf_type as u8_t instead of enum to save space */ + u8_t /*pbuf_type*/ type; + + /** misc flags */ + u8_t flags; + + /** + * the reference count always equals the number of pointers + * that refer to this pbuf. This can be pointers from an application, + * the stack itself, or pbuf->next pointers from a chain. + */ + u16_t ref; + +}; + +/* Initializes the pbuf module. This call is empty for now, but may not be in future. */ +#define pbuf_init() + +struct pbuf *pbuf_alloc(pbuf_layer l, u16_t size, pbuf_type type); +void pbuf_realloc(struct pbuf *p, u16_t size); +u8_t pbuf_header(struct pbuf *p, s16_t header_size); +void pbuf_ref(struct pbuf *p); +void pbuf_ref_chain(struct pbuf *p); +u8_t pbuf_free(struct pbuf *p); +u8_t pbuf_clen(struct pbuf *p); +void pbuf_cat(struct pbuf *head, struct pbuf *tail); +void pbuf_chain(struct pbuf *head, struct pbuf *tail); +struct pbuf *pbuf_dechain(struct pbuf *p); +err_t pbuf_copy(struct pbuf *p_to, struct pbuf *p_from); +u16_t pbuf_copy_partial(struct pbuf *p, void *dataptr, u16_t len, u16_t offset); +err_t pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len); +struct pbuf *pbuf_coalesce(struct pbuf *p, pbuf_layer layer); + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_PBUF_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/raw.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/raw.h new file mode 100644 index 0000000000000000000000000000000000000000..545c43367a65cea132ca48960850e3dd9916b678 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/raw.h @@ -0,0 +1,99 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_RAW_H__ +#define __LWIP_RAW_H__ + +#include "lwip/opt.h" + +#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/inet.h" +#include "lwip/ip.h" +#include "lwip/ip_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct raw_pcb { +/* Common members of all PCB types */ + IP_PCB; + + struct raw_pcb *next; + + u8_t protocol; + + /* receive callback function + * @param arg user supplied argument (raw_pcb.recv_arg) + * @param pcb the raw_pcb which received data + * @param p the packet buffer that was received + * @param addr the remote IP address from which the packet was received + * @return 1 if the packet was 'eaten' (aka. deleted), + * 0 if the packet lives on + * If returning 1, the callback is responsible for freeing the pbuf + * if it's not used any more. + */ + u8_t (* recv)(void *arg, struct raw_pcb *pcb, struct pbuf *p, + struct ip_addr *addr); + /* user-supplied argument for the recv callback */ + void *recv_arg; +}; + +/* The following functions is the application layer interface to the + RAW code. */ +struct raw_pcb * raw_new (u8_t proto); +void raw_remove (struct raw_pcb *pcb); +err_t raw_bind (struct raw_pcb *pcb, struct ip_addr *ipaddr); +err_t raw_connect (struct raw_pcb *pcb, struct ip_addr *ipaddr); + +void raw_recv (struct raw_pcb *pcb, + u8_t (* recv)(void *arg, struct raw_pcb *pcb, + struct pbuf *p, + struct ip_addr *addr), + void *recv_arg); +err_t raw_sendto (struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr); +err_t raw_send (struct raw_pcb *pcb, struct pbuf *p); + +/* The following functions are the lower layer interface to RAW. */ +u8_t raw_input (struct pbuf *p, struct netif *inp); +#define raw_init() /* Compatibility define, not init needed. */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_RAW */ + +#endif /* __LWIP_RAW_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/sio.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/sio.h new file mode 100644 index 0000000000000000000000000000000000000000..10eabcf165d9bbba1136a63d86b1b114c87265c7 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/sio.h @@ -0,0 +1,143 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + */ + +/* + * This is the interface to the platform specific serial IO module + * It needs to be implemented by those platforms which need SLIP or PPP + */ + +#ifndef __SIO_H__ +#define __SIO_H__ + +#include "lwip/arch.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* If you want to define sio_fd_t elsewhere or differently, + define this in your cc.h file. */ +#ifndef __sio_fd_t_defined +typedef void * sio_fd_t; +#endif + +/* The following functions can be defined to something else in your cc.h file + or be implemented in your custom sio.c file. */ + +#ifndef sio_open +/** + * Opens a serial device for communication. + * + * @param devnum device number + * @return handle to serial device if successful, NULL otherwise + */ +sio_fd_t sio_open(u8_t devnum); +#endif + +#ifndef sio_send +/** + * Sends a single character to the serial device. + * + * @param c character to send + * @param fd serial device handle + * + * @note This function will block until the character can be sent. + */ +void sio_send(u8_t c, sio_fd_t fd); +#endif + +#ifndef sio_recv +/** + * Receives a single character from the serial device. + * + * @param fd serial device handle + * + * @note This function will block until a character is received. + */ +u8_t sio_recv(sio_fd_t fd); +#endif + +#ifndef sio_read +/** + * Reads from the serial device. + * + * @param fd serial device handle + * @param data pointer to data buffer for receiving + * @param len maximum length (in bytes) of data to receive + * @return number of bytes actually received - may be 0 if aborted by sio_read_abort + * + * @note This function will block until data can be received. The blocking + * can be cancelled by calling sio_read_abort(). + */ +u32_t sio_read(sio_fd_t fd, u8_t *data, u32_t len); +#endif + +#ifndef sio_tryread +/** + * Tries to read from the serial device. Same as sio_read but returns + * immediately if no data is available and never blocks. + * + * @param fd serial device handle + * @param data pointer to data buffer for receiving + * @param len maximum length (in bytes) of data to receive + * @return number of bytes actually received + */ +u32_t sio_tryread(sio_fd_t fd, u8_t *data, u32_t len); +#endif + +#ifndef sio_write +/** + * Writes to the serial device. + * + * @param fd serial device handle + * @param data pointer to data to send + * @param len length (in bytes) of data to send + * @return number of bytes actually sent + * + * @note This function will block until all data can be sent. + */ +u32_t sio_write(sio_fd_t fd, u8_t *data, u32_t len); +#endif + +#ifndef sio_read_abort +/** + * Aborts a blocking sio_read() call. + * + * @param fd serial device handle + */ +void sio_read_abort(sio_fd_t fd); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __SIO_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/snmp.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/snmp.h new file mode 100644 index 0000000000000000000000000000000000000000..b87717f9a0603629d32646204852b77ab24625b5 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/snmp.h @@ -0,0 +1,366 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001, 2002 Leon Woestenberg + * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Leon Woestenberg + * + */ +#ifndef __LWIP_SNMP_H__ +#define __LWIP_SNMP_H__ + +#include "lwip/opt.h" +#include "lwip/netif.h" +#include "lwip/udp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @see RFC1213, "MIB-II, 6. Definitions" + */ +enum snmp_ifType { + snmp_ifType_other=1, /* none of the following */ + snmp_ifType_regular1822, + snmp_ifType_hdh1822, + snmp_ifType_ddn_x25, + snmp_ifType_rfc877_x25, + snmp_ifType_ethernet_csmacd, + snmp_ifType_iso88023_csmacd, + snmp_ifType_iso88024_tokenBus, + snmp_ifType_iso88025_tokenRing, + snmp_ifType_iso88026_man, + snmp_ifType_starLan, + snmp_ifType_proteon_10Mbit, + snmp_ifType_proteon_80Mbit, + snmp_ifType_hyperchannel, + snmp_ifType_fddi, + snmp_ifType_lapb, + snmp_ifType_sdlc, + snmp_ifType_ds1, /* T-1 */ + snmp_ifType_e1, /* european equiv. of T-1 */ + snmp_ifType_basicISDN, + snmp_ifType_primaryISDN, /* proprietary serial */ + snmp_ifType_propPointToPointSerial, + snmp_ifType_ppp, + snmp_ifType_softwareLoopback, + snmp_ifType_eon, /* CLNP over IP [11] */ + snmp_ifType_ethernet_3Mbit, + snmp_ifType_nsip, /* XNS over IP */ + snmp_ifType_slip, /* generic SLIP */ + snmp_ifType_ultra, /* ULTRA technologies */ + snmp_ifType_ds3, /* T-3 */ + snmp_ifType_sip, /* SMDS */ + snmp_ifType_frame_relay +}; + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ + +/** SNMP "sysuptime" Interval */ +#define SNMP_SYSUPTIME_INTERVAL 10 + +/** fixed maximum length for object identifier type */ +#define LWIP_SNMP_OBJ_ID_LEN 32 + +/** internal object identifier representation */ +struct snmp_obj_id +{ + u8_t len; + s32_t id[LWIP_SNMP_OBJ_ID_LEN]; +}; + +/* system */ +void snmp_set_sysdesr(u8_t* str, u8_t* len); +void snmp_set_sysobjid(struct snmp_obj_id *oid); +void snmp_get_sysobjid_ptr(struct snmp_obj_id **oid); +void snmp_inc_sysuptime(void); +void snmp_add_sysuptime(u32_t value); +void snmp_get_sysuptime(u32_t *value); +void snmp_set_syscontact(u8_t *ocstr, u8_t *ocstrlen); +void snmp_set_sysname(u8_t *ocstr, u8_t *ocstrlen); +void snmp_set_syslocation(u8_t *ocstr, u8_t *ocstrlen); + +/* network interface */ +void snmp_add_ifinoctets(struct netif *ni, u32_t value); +void snmp_inc_ifinucastpkts(struct netif *ni); +void snmp_inc_ifinnucastpkts(struct netif *ni); +void snmp_inc_ifindiscards(struct netif *ni); +void snmp_add_ifoutoctets(struct netif *ni, u32_t value); +void snmp_inc_ifoutucastpkts(struct netif *ni); +void snmp_inc_ifoutnucastpkts(struct netif *ni); +void snmp_inc_ifoutdiscards(struct netif *ni); +void snmp_inc_iflist(void); +void snmp_dec_iflist(void); + +/* ARP (for atTable and ipNetToMediaTable) */ +void snmp_insert_arpidx_tree(struct netif *ni, struct ip_addr *ip); +void snmp_delete_arpidx_tree(struct netif *ni, struct ip_addr *ip); + +/* IP */ +void snmp_inc_ipinreceives(void); +void snmp_inc_ipinhdrerrors(void); +void snmp_inc_ipinaddrerrors(void); +void snmp_inc_ipforwdatagrams(void); +void snmp_inc_ipinunknownprotos(void); +void snmp_inc_ipindiscards(void); +void snmp_inc_ipindelivers(void); +void snmp_inc_ipoutrequests(void); +void snmp_inc_ipoutdiscards(void); +void snmp_inc_ipoutnoroutes(void); +void snmp_inc_ipreasmreqds(void); +void snmp_inc_ipreasmoks(void); +void snmp_inc_ipreasmfails(void); +void snmp_inc_ipfragoks(void); +void snmp_inc_ipfragfails(void); +void snmp_inc_ipfragcreates(void); +void snmp_inc_iproutingdiscards(void); +void snmp_insert_ipaddridx_tree(struct netif *ni); +void snmp_delete_ipaddridx_tree(struct netif *ni); +void snmp_insert_iprteidx_tree(u8_t dflt, struct netif *ni); +void snmp_delete_iprteidx_tree(u8_t dflt, struct netif *ni); + +/* ICMP */ +void snmp_inc_icmpinmsgs(void); +void snmp_inc_icmpinerrors(void); +void snmp_inc_icmpindestunreachs(void); +void snmp_inc_icmpintimeexcds(void); +void snmp_inc_icmpinparmprobs(void); +void snmp_inc_icmpinsrcquenchs(void); +void snmp_inc_icmpinredirects(void); +void snmp_inc_icmpinechos(void); +void snmp_inc_icmpinechoreps(void); +void snmp_inc_icmpintimestamps(void); +void snmp_inc_icmpintimestampreps(void); +void snmp_inc_icmpinaddrmasks(void); +void snmp_inc_icmpinaddrmaskreps(void); +void snmp_inc_icmpoutmsgs(void); +void snmp_inc_icmpouterrors(void); +void snmp_inc_icmpoutdestunreachs(void); +void snmp_inc_icmpouttimeexcds(void); +void snmp_inc_icmpoutparmprobs(void); +void snmp_inc_icmpoutsrcquenchs(void); +void snmp_inc_icmpoutredirects(void); +void snmp_inc_icmpoutechos(void); +void snmp_inc_icmpoutechoreps(void); +void snmp_inc_icmpouttimestamps(void); +void snmp_inc_icmpouttimestampreps(void); +void snmp_inc_icmpoutaddrmasks(void); +void snmp_inc_icmpoutaddrmaskreps(void); + +/* TCP */ +void snmp_inc_tcpactiveopens(void); +void snmp_inc_tcppassiveopens(void); +void snmp_inc_tcpattemptfails(void); +void snmp_inc_tcpestabresets(void); +void snmp_inc_tcpinsegs(void); +void snmp_inc_tcpoutsegs(void); +void snmp_inc_tcpretranssegs(void); +void snmp_inc_tcpinerrs(void); +void snmp_inc_tcpoutrsts(void); + +/* UDP */ +void snmp_inc_udpindatagrams(void); +void snmp_inc_udpnoports(void); +void snmp_inc_udpinerrors(void); +void snmp_inc_udpoutdatagrams(void); +void snmp_insert_udpidx_tree(struct udp_pcb *pcb); +void snmp_delete_udpidx_tree(struct udp_pcb *pcb); + +/* SNMP */ +void snmp_inc_snmpinpkts(void); +void snmp_inc_snmpoutpkts(void); +void snmp_inc_snmpinbadversions(void); +void snmp_inc_snmpinbadcommunitynames(void); +void snmp_inc_snmpinbadcommunityuses(void); +void snmp_inc_snmpinasnparseerrs(void); +void snmp_inc_snmpintoobigs(void); +void snmp_inc_snmpinnosuchnames(void); +void snmp_inc_snmpinbadvalues(void); +void snmp_inc_snmpinreadonlys(void); +void snmp_inc_snmpingenerrs(void); +void snmp_add_snmpintotalreqvars(u8_t value); +void snmp_add_snmpintotalsetvars(u8_t value); +void snmp_inc_snmpingetrequests(void); +void snmp_inc_snmpingetnexts(void); +void snmp_inc_snmpinsetrequests(void); +void snmp_inc_snmpingetresponses(void); +void snmp_inc_snmpintraps(void); +void snmp_inc_snmpouttoobigs(void); +void snmp_inc_snmpoutnosuchnames(void); +void snmp_inc_snmpoutbadvalues(void); +void snmp_inc_snmpoutgenerrs(void); +void snmp_inc_snmpoutgetrequests(void); +void snmp_inc_snmpoutgetnexts(void); +void snmp_inc_snmpoutsetrequests(void); +void snmp_inc_snmpoutgetresponses(void); +void snmp_inc_snmpouttraps(void); +void snmp_get_snmpgrpid_ptr(struct snmp_obj_id **oid); +void snmp_set_snmpenableauthentraps(u8_t *value); +void snmp_get_snmpenableauthentraps(u8_t *value); + +/* LWIP_SNMP support not available */ +/* define everything to be empty */ +#else + +/* system */ +#define snmp_set_sysdesr(str, len) +#define snmp_set_sysobjid(oid); +#define snmp_get_sysobjid_ptr(oid) +#define snmp_inc_sysuptime() +#define snmp_add_sysuptime(value) +#define snmp_get_sysuptime(value) +#define snmp_set_syscontact(ocstr, ocstrlen); +#define snmp_set_sysname(ocstr, ocstrlen); +#define snmp_set_syslocation(ocstr, ocstrlen); + +/* network interface */ +#define snmp_add_ifinoctets(ni,value) +#define snmp_inc_ifinucastpkts(ni) +#define snmp_inc_ifinnucastpkts(ni) +#define snmp_inc_ifindiscards(ni) +#define snmp_add_ifoutoctets(ni,value) +#define snmp_inc_ifoutucastpkts(ni) +#define snmp_inc_ifoutnucastpkts(ni) +#define snmp_inc_ifoutdiscards(ni) +#define snmp_inc_iflist() +#define snmp_dec_iflist() + +/* ARP */ +#define snmp_insert_arpidx_tree(ni,ip) +#define snmp_delete_arpidx_tree(ni,ip) + +/* IP */ +#define snmp_inc_ipinreceives() +#define snmp_inc_ipinhdrerrors() +#define snmp_inc_ipinaddrerrors() +#define snmp_inc_ipforwdatagrams() +#define snmp_inc_ipinunknownprotos() +#define snmp_inc_ipindiscards() +#define snmp_inc_ipindelivers() +#define snmp_inc_ipoutrequests() +#define snmp_inc_ipoutdiscards() +#define snmp_inc_ipoutnoroutes() +#define snmp_inc_ipreasmreqds() +#define snmp_inc_ipreasmoks() +#define snmp_inc_ipreasmfails() +#define snmp_inc_ipfragoks() +#define snmp_inc_ipfragfails() +#define snmp_inc_ipfragcreates() +#define snmp_inc_iproutingdiscards() +#define snmp_insert_ipaddridx_tree(ni) +#define snmp_delete_ipaddridx_tree(ni) +#define snmp_insert_iprteidx_tree(dflt, ni) +#define snmp_delete_iprteidx_tree(dflt, ni) + +/* ICMP */ +#define snmp_inc_icmpinmsgs() +#define snmp_inc_icmpinerrors() +#define snmp_inc_icmpindestunreachs() +#define snmp_inc_icmpintimeexcds() +#define snmp_inc_icmpinparmprobs() +#define snmp_inc_icmpinsrcquenchs() +#define snmp_inc_icmpinredirects() +#define snmp_inc_icmpinechos() +#define snmp_inc_icmpinechoreps() +#define snmp_inc_icmpintimestamps() +#define snmp_inc_icmpintimestampreps() +#define snmp_inc_icmpinaddrmasks() +#define snmp_inc_icmpinaddrmaskreps() +#define snmp_inc_icmpoutmsgs() +#define snmp_inc_icmpouterrors() +#define snmp_inc_icmpoutdestunreachs() +#define snmp_inc_icmpouttimeexcds() +#define snmp_inc_icmpoutparmprobs() +#define snmp_inc_icmpoutsrcquenchs() +#define snmp_inc_icmpoutredirects() +#define snmp_inc_icmpoutechos() +#define snmp_inc_icmpoutechoreps() +#define snmp_inc_icmpouttimestamps() +#define snmp_inc_icmpouttimestampreps() +#define snmp_inc_icmpoutaddrmasks() +#define snmp_inc_icmpoutaddrmaskreps() +/* TCP */ +#define snmp_inc_tcpactiveopens() +#define snmp_inc_tcppassiveopens() +#define snmp_inc_tcpattemptfails() +#define snmp_inc_tcpestabresets() +#define snmp_inc_tcpinsegs() +#define snmp_inc_tcpoutsegs() +#define snmp_inc_tcpretranssegs() +#define snmp_inc_tcpinerrs() +#define snmp_inc_tcpoutrsts() + +/* UDP */ +#define snmp_inc_udpindatagrams() +#define snmp_inc_udpnoports() +#define snmp_inc_udpinerrors() +#define snmp_inc_udpoutdatagrams() +#define snmp_insert_udpidx_tree(pcb) +#define snmp_delete_udpidx_tree(pcb) + +/* SNMP */ +#define snmp_inc_snmpinpkts() +#define snmp_inc_snmpoutpkts() +#define snmp_inc_snmpinbadversions() +#define snmp_inc_snmpinbadcommunitynames() +#define snmp_inc_snmpinbadcommunityuses() +#define snmp_inc_snmpinasnparseerrs() +#define snmp_inc_snmpintoobigs() +#define snmp_inc_snmpinnosuchnames() +#define snmp_inc_snmpinbadvalues() +#define snmp_inc_snmpinreadonlys() +#define snmp_inc_snmpingenerrs() +#define snmp_add_snmpintotalreqvars(value) +#define snmp_add_snmpintotalsetvars(value) +#define snmp_inc_snmpingetrequests() +#define snmp_inc_snmpingetnexts() +#define snmp_inc_snmpinsetrequests() +#define snmp_inc_snmpingetresponses() +#define snmp_inc_snmpintraps() +#define snmp_inc_snmpouttoobigs() +#define snmp_inc_snmpoutnosuchnames() +#define snmp_inc_snmpoutbadvalues() +#define snmp_inc_snmpoutgenerrs() +#define snmp_inc_snmpoutgetrequests() +#define snmp_inc_snmpoutgetnexts() +#define snmp_inc_snmpoutsetrequests() +#define snmp_inc_snmpoutgetresponses() +#define snmp_inc_snmpouttraps() +#define snmp_get_snmpgrpid_ptr(oid) +#define snmp_set_snmpenableauthentraps(value) +#define snmp_get_snmpenableauthentraps(value) + +#endif /* LWIP_SNMP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_SNMP_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/snmp_asn1.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/snmp_asn1.h new file mode 100644 index 0000000000000000000000000000000000000000..a40d5ef8d8074a4361bc0d353ef7f795782d6315 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/snmp_asn1.h @@ -0,0 +1,103 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/** + * @file + * Abstract Syntax Notation One (ISO 8824, 8825) codec. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#ifndef __LWIP_SNMP_ASN1_H__ +#define __LWIP_SNMP_ASN1_H__ + +#include "lwip/opt.h" +#include "lwip/err.h" +#include "lwip/pbuf.h" +#include "lwip/snmp.h" + +#if LWIP_SNMP + +#ifdef __cplusplus +extern "C" { +#endif + +#define SNMP_ASN1_UNIV (!0x80 | !0x40) +#define SNMP_ASN1_APPLIC (!0x80 | 0x40) +#define SNMP_ASN1_CONTXT ( 0x80 | !0x40) + +#define SNMP_ASN1_CONSTR (0x20) +#define SNMP_ASN1_PRIMIT (!0x20) + +/* universal tags */ +#define SNMP_ASN1_INTEG 2 +#define SNMP_ASN1_OC_STR 4 +#define SNMP_ASN1_NUL 5 +#define SNMP_ASN1_OBJ_ID 6 +#define SNMP_ASN1_SEQ 16 + +/* application specific (SNMP) tags */ +#define SNMP_ASN1_IPADDR 0 /* octet string size(4) */ +#define SNMP_ASN1_COUNTER 1 /* u32_t */ +#define SNMP_ASN1_GAUGE 2 /* u32_t */ +#define SNMP_ASN1_TIMETICKS 3 /* u32_t */ +#define SNMP_ASN1_OPAQUE 4 /* octet string */ + +/* context specific (SNMP) tags */ +#define SNMP_ASN1_PDU_GET_REQ 0 +#define SNMP_ASN1_PDU_GET_NEXT_REQ 1 +#define SNMP_ASN1_PDU_GET_RESP 2 +#define SNMP_ASN1_PDU_SET_REQ 3 +#define SNMP_ASN1_PDU_TRAP 4 + +err_t snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type); +err_t snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length); +err_t snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value); +err_t snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value); +err_t snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid); +err_t snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw); + +void snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed); +void snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed); +void snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed); +void snmp_asn1_enc_oid_cnt(u8_t ident_len, s32_t *ident, u16_t *octets_needed); +err_t snmp_asn1_enc_type(struct pbuf *p, u16_t ofs, u8_t type); +err_t snmp_asn1_enc_length(struct pbuf *p, u16_t ofs, u16_t length); +err_t snmp_asn1_enc_u32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, u32_t value); +err_t snmp_asn1_enc_s32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, s32_t value); +err_t snmp_asn1_enc_oid(struct pbuf *p, u16_t ofs, u8_t ident_len, s32_t *ident); +err_t snmp_asn1_enc_raw(struct pbuf *p, u16_t ofs, u8_t raw_len, u8_t *raw); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_SNMP */ + +#endif /* __LWIP_SNMP_ASN1_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/snmp_msg.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/snmp_msg.h new file mode 100644 index 0000000000000000000000000000000000000000..6e50a61867d1babd97b5c732099c58fb0f52cc5f --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/snmp_msg.h @@ -0,0 +1,313 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/** + * @file + * SNMP Agent message handling structures. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#ifndef __LWIP_SNMP_MSG_H__ +#define __LWIP_SNMP_MSG_H__ + +#include "lwip/opt.h" +#include "lwip/snmp.h" +#include "lwip/snmp_structs.h" + +#if LWIP_SNMP + +#if SNMP_PRIVATE_MIB +#include "private_mib.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* The listen port of the SNMP agent. Clients have to make their requests to + this port. Most standard clients won't work if you change this! */ +#ifndef SNMP_IN_PORT +#define SNMP_IN_PORT 161 +#endif +/* The remote port the SNMP agent sends traps to. Most standard trap sinks won't + work if you change this! */ +#ifndef SNMP_TRAP_PORT +#define SNMP_TRAP_PORT 162 +#endif + +#define SNMP_ES_NOERROR 0 +#define SNMP_ES_TOOBIG 1 +#define SNMP_ES_NOSUCHNAME 2 +#define SNMP_ES_BADVALUE 3 +#define SNMP_ES_READONLY 4 +#define SNMP_ES_GENERROR 5 + +#define SNMP_GENTRAP_COLDSTART 0 +#define SNMP_GENTRAP_WARMSTART 1 +#define SNMP_GENTRAP_AUTHFAIL 4 +#define SNMP_GENTRAP_ENTERPRISESPC 6 + +struct snmp_varbind +{ + /* next pointer, NULL for last in list */ + struct snmp_varbind *next; + /* previous pointer, NULL for first in list */ + struct snmp_varbind *prev; + + /* object identifier length (in s32_t) */ + u8_t ident_len; + /* object identifier array */ + s32_t *ident; + + /* object value ASN1 type */ + u8_t value_type; + /* object value length (in u8_t) */ + u8_t value_len; + /* object value */ + void *value; + + /* encoding varbind seq length length */ + u8_t seqlenlen; + /* encoding object identifier length length */ + u8_t olenlen; + /* encoding object value length length */ + u8_t vlenlen; + /* encoding varbind seq length */ + u16_t seqlen; + /* encoding object identifier length */ + u16_t olen; + /* encoding object value length */ + u16_t vlen; +}; + +struct snmp_varbind_root +{ + struct snmp_varbind *head; + struct snmp_varbind *tail; + /* number of variable bindings in list */ + u8_t count; + /* encoding varbind-list seq length length */ + u8_t seqlenlen; + /* encoding varbind-list seq length */ + u16_t seqlen; +}; + +/** output response message header length fields */ +struct snmp_resp_header_lengths +{ + /* encoding error-index length length */ + u8_t erridxlenlen; + /* encoding error-status length length */ + u8_t errstatlenlen; + /* encoding request id length length */ + u8_t ridlenlen; + /* encoding pdu length length */ + u8_t pdulenlen; + /* encoding community length length */ + u8_t comlenlen; + /* encoding version length length */ + u8_t verlenlen; + /* encoding sequence length length */ + u8_t seqlenlen; + + /* encoding error-index length */ + u16_t erridxlen; + /* encoding error-status length */ + u16_t errstatlen; + /* encoding request id length */ + u16_t ridlen; + /* encoding pdu length */ + u16_t pdulen; + /* encoding community length */ + u16_t comlen; + /* encoding version length */ + u16_t verlen; + /* encoding sequence length */ + u16_t seqlen; +}; + +/** output response message header length fields */ +struct snmp_trap_header_lengths +{ + /* encoding timestamp length length */ + u8_t tslenlen; + /* encoding specific-trap length length */ + u8_t strplenlen; + /* encoding generic-trap length length */ + u8_t gtrplenlen; + /* encoding agent-addr length length */ + u8_t aaddrlenlen; + /* encoding enterprise-id length length */ + u8_t eidlenlen; + /* encoding pdu length length */ + u8_t pdulenlen; + /* encoding community length length */ + u8_t comlenlen; + /* encoding version length length */ + u8_t verlenlen; + /* encoding sequence length length */ + u8_t seqlenlen; + + /* encoding timestamp length */ + u16_t tslen; + /* encoding specific-trap length */ + u16_t strplen; + /* encoding generic-trap length */ + u16_t gtrplen; + /* encoding agent-addr length */ + u16_t aaddrlen; + /* encoding enterprise-id length */ + u16_t eidlen; + /* encoding pdu length */ + u16_t pdulen; + /* encoding community length */ + u16_t comlen; + /* encoding version length */ + u16_t verlen; + /* encoding sequence length */ + u16_t seqlen; +}; + +/* Accepting new SNMP messages. */ +#define SNMP_MSG_EMPTY 0 +/* Search for matching object for variable binding. */ +#define SNMP_MSG_SEARCH_OBJ 1 +/* Perform SNMP operation on in-memory object. + Pass-through states, for symmetry only. */ +#define SNMP_MSG_INTERNAL_GET_OBJDEF 2 +#define SNMP_MSG_INTERNAL_GET_VALUE 3 +#define SNMP_MSG_INTERNAL_SET_TEST 4 +#define SNMP_MSG_INTERNAL_GET_OBJDEF_S 5 +#define SNMP_MSG_INTERNAL_SET_VALUE 6 +/* Perform SNMP operation on object located externally. + In theory this could be used for building a proxy agent. + Practical use is for an enterprise spc. app. gateway. */ +#define SNMP_MSG_EXTERNAL_GET_OBJDEF 7 +#define SNMP_MSG_EXTERNAL_GET_VALUE 8 +#define SNMP_MSG_EXTERNAL_SET_TEST 9 +#define SNMP_MSG_EXTERNAL_GET_OBJDEF_S 10 +#define SNMP_MSG_EXTERNAL_SET_VALUE 11 + +#define SNMP_COMMUNITY_STR_LEN 64 +struct snmp_msg_pstat +{ + /* lwIP local port (161) binding */ + struct udp_pcb *pcb; + /* source IP address */ + struct ip_addr sip; + /* source UDP port */ + u16_t sp; + /* request type */ + u8_t rt; + /* request ID */ + s32_t rid; + /* error status */ + s32_t error_status; + /* error index */ + s32_t error_index; + /* community name (zero terminated) */ + u8_t community[SNMP_COMMUNITY_STR_LEN + 1]; + /* community string length (exclusive zero term) */ + u8_t com_strlen; + /* one out of MSG_EMPTY, MSG_DEMUX, MSG_INTERNAL, MSG_EXTERNAL_x */ + u8_t state; + /* saved arguments for MSG_EXTERNAL_x */ + struct mib_external_node *ext_mib_node; + struct snmp_name_ptr ext_name_ptr; + struct obj_def ext_object_def; + struct snmp_obj_id ext_oid; + /* index into input variable binding list */ + u8_t vb_idx; + /* ptr into input variable binding list */ + struct snmp_varbind *vb_ptr; + /* list of variable bindings from input */ + struct snmp_varbind_root invb; + /* list of variable bindings to output */ + struct snmp_varbind_root outvb; + /* output response lengths used in ASN encoding */ + struct snmp_resp_header_lengths rhl; +}; + +struct snmp_msg_trap +{ + /* lwIP local port (161) binding */ + struct udp_pcb *pcb; + /* destination IP address in network order */ + struct ip_addr dip; + + /* source enterprise ID (sysObjectID) */ + struct snmp_obj_id *enterprise; + /* source IP address, raw network order format */ + u8_t sip_raw[4]; + /* generic trap code */ + u32_t gen_trap; + /* specific trap code */ + u32_t spc_trap; + /* timestamp */ + u32_t ts; + /* list of variable bindings to output */ + struct snmp_varbind_root outvb; + /* output trap lengths used in ASN encoding */ + struct snmp_trap_header_lengths thl; +}; + +/** Agent Version constant, 0 = v1 oddity */ +extern const s32_t snmp_version; +/** Agent default "public" community string */ +extern const char snmp_publiccommunity[7]; + +extern struct snmp_msg_trap trap_msg; + +/** Agent setup, start listening to port 161. */ +void snmp_init(void); +void snmp_trap_dst_enable(u8_t dst_idx, u8_t enable); +void snmp_trap_dst_ip_set(u8_t dst_idx, struct ip_addr *dst); + +/** Varbind-list functions. */ +struct snmp_varbind* snmp_varbind_alloc(struct snmp_obj_id *oid, u8_t type, u8_t len); +void snmp_varbind_free(struct snmp_varbind *vb); +void snmp_varbind_list_free(struct snmp_varbind_root *root); +void snmp_varbind_tail_add(struct snmp_varbind_root *root, struct snmp_varbind *vb); +struct snmp_varbind* snmp_varbind_tail_remove(struct snmp_varbind_root *root); + +/** Handle an internal (recv) or external (private response) event. */ +void snmp_msg_event(u8_t request_id); +err_t snmp_send_response(struct snmp_msg_pstat *m_stat); +err_t snmp_send_trap(s8_t generic_trap, struct snmp_obj_id *eoid, s32_t specific_trap); +void snmp_coldstart_trap(void); +void snmp_authfail_trap(void); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_SNMP */ + +#endif /* __LWIP_SNMP_MSG_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/snmp_structs.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/snmp_structs.h new file mode 100644 index 0000000000000000000000000000000000000000..93f4ea3c11846fa766282a0c8ca62266ea728ccb --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/snmp_structs.h @@ -0,0 +1,264 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/** + * @file + * Generic MIB tree structures. + * + * @todo namespace prefixes + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#ifndef __LWIP_SNMP_STRUCTS_H__ +#define __LWIP_SNMP_STRUCTS_H__ + +#include "lwip/opt.h" + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/snmp.h" + +#if SNMP_PRIVATE_MIB +#include "private_mib.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* MIB object instance */ +#define MIB_OBJECT_NONE 0 +#define MIB_OBJECT_SCALAR 1 +#define MIB_OBJECT_TAB 2 + +/* MIB object access */ +#define MIB_OBJECT_READ_ONLY 0 +#define MIB_OBJECT_READ_WRITE 1 +#define MIB_OBJECT_WRITE_ONLY 2 +#define MIB_OBJECT_NOT_ACCESSIBLE 3 + +/** object definition returned by (get_object_def)() */ +struct obj_def +{ + /* MIB_OBJECT_NONE (0), MIB_OBJECT_SCALAR (1), MIB_OBJECT_TAB (2) */ + u8_t instance; + /* 0 read-only, 1 read-write, 2 write-only, 3 not-accessible */ + u8_t access; + /* ASN type for this object */ + u8_t asn_type; + /* value length (host length) */ + u16_t v_len; + /* length of instance part of supplied object identifier */ + u8_t id_inst_len; + /* instance part of supplied object identifier */ + s32_t *id_inst_ptr; +}; + +struct snmp_name_ptr +{ + u8_t ident_len; + s32_t *ident; +}; + +/** MIB const scalar (.0) node */ +#define MIB_NODE_SC 0x01 +/** MIB const array node */ +#define MIB_NODE_AR 0x02 +/** MIB array node (mem_malloced from RAM) */ +#define MIB_NODE_RA 0x03 +/** MIB list root node (mem_malloced from RAM) */ +#define MIB_NODE_LR 0x04 +/** MIB node for external objects */ +#define MIB_NODE_EX 0x05 + +/** node "base class" layout, the mandatory fields for a node */ +struct mib_node +{ + /** returns struct obj_def for the given object identifier */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + /** returns object value for the given object identifier, + @note the caller must allocate at least len bytes for the value */ + void (*get_value)(struct obj_def *od, u16_t len, void *value); + /** tests length and/or range BEFORE setting */ + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + /** sets object value, only to be called when set_test() */ + void (*set_value)(struct obj_def *od, u16_t len, void *value); + /** One out of MIB_NODE_AR, MIB_NODE_LR or MIB_NODE_EX */ + const u8_t node_type; + /* array or max list length */ + const u16_t maxlength; +}; + +/** derived node for scalars .0 index */ +typedef struct mib_node mib_scalar_node; + +/** derived node, points to a fixed size const array + of sub-identifiers plus a 'child' pointer */ +struct mib_array_node +{ + /* inherited "base class" members */ + void (* const get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (* const get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + const u8_t node_type; + const u16_t maxlength; + + /* aditional struct members */ + const s32_t *objid; + struct mib_node* const *nptr; +}; + +/** derived node, points to a fixed size mem_malloced array + of sub-identifiers plus a 'child' pointer */ +struct mib_ram_array_node +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* aditional struct members */ + s32_t *objid; + struct mib_node **nptr; +}; + +struct mib_list_node +{ + struct mib_list_node *prev; + struct mib_list_node *next; + s32_t objid; + struct mib_node *nptr; +}; + +/** derived node, points to a doubly linked list + of sub-identifiers plus a 'child' pointer */ +struct mib_list_rootnode +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* aditional struct members */ + struct mib_list_node *head; + struct mib_list_node *tail; + /* counts list nodes in list */ + u16_t count; +}; + +/** derived node, has access functions for mib object in external memory or device + using 'tree_level' and 'idx', with a range 0 .. (level_length() - 1) */ +struct mib_external_node +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* aditional struct members */ + /** points to an extenal (in memory) record of some sort of addressing + information, passed to and interpreted by the funtions below */ + void* addr_inf; + /** tree levels under this node */ + u8_t tree_levels; + /** number of objects at this level */ + u16_t (*level_length)(void* addr_inf, u8_t level); + /** compares object sub identifier with external id + return zero when equal, nonzero when unequal */ + s32_t (*ident_cmp)(void* addr_inf, u8_t level, u16_t idx, s32_t sub_id); + void (*get_objid)(void* addr_inf, u8_t level, u16_t idx, s32_t *sub_id); + + /** async Questions */ + void (*get_object_def_q)(void* addr_inf, u8_t rid, u8_t ident_len, s32_t *ident); + void (*get_value_q)(u8_t rid, struct obj_def *od); + void (*set_test_q)(u8_t rid, struct obj_def *od); + void (*set_value_q)(u8_t rid, struct obj_def *od, u16_t len, void *value); + /** async Answers */ + void (*get_object_def_a)(u8_t rid, u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); + u8_t (*set_test_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); + void (*set_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); + /** async Panic Close (agent returns error reply, + e.g. used for external transaction cleanup) */ + void (*get_object_def_pc)(u8_t rid, u8_t ident_len, s32_t *ident); + void (*get_value_pc)(u8_t rid, struct obj_def *od); + void (*set_test_pc)(u8_t rid, struct obj_def *od); + void (*set_value_pc)(u8_t rid, struct obj_def *od); +}; + +/** export MIB tree from mib2.c */ +extern const struct mib_array_node internet; + +/** dummy function pointers for non-leaf MIB nodes from mib2.c */ +void noleafs_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +void noleafs_get_value(struct obj_def *od, u16_t len, void *value); +u8_t noleafs_set_test(struct obj_def *od, u16_t len, void *value); +void noleafs_set_value(struct obj_def *od, u16_t len, void *value); + +void snmp_oidtoip(s32_t *ident, struct ip_addr *ip); +void snmp_iptooid(struct ip_addr *ip, s32_t *ident); +void snmp_ifindextonetif(s32_t ifindex, struct netif **netif); +void snmp_netiftoifindex(struct netif *netif, s32_t *ifidx); + +struct mib_list_node* snmp_mib_ln_alloc(s32_t id); +void snmp_mib_ln_free(struct mib_list_node *ln); +struct mib_list_rootnode* snmp_mib_lrn_alloc(void); +void snmp_mib_lrn_free(struct mib_list_rootnode *lrn); + +s8_t snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn); +s8_t snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn); +struct mib_list_rootnode *snmp_mib_node_delete(struct mib_list_rootnode *rn, struct mib_list_node *n); + +struct mib_node* snmp_search_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_name_ptr *np); +struct mib_node* snmp_expand_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret); +u8_t snmp_iso_prefix_tst(u8_t ident_len, s32_t *ident); +u8_t snmp_iso_prefix_expand(u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_SNMP */ + +#endif /* __LWIP_SNMP_STRUCTS_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/sockets.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/sockets.h new file mode 100644 index 0000000000000000000000000000000000000000..675c1f7400c3a15d8cc6bc216e61443ca429cb02 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/sockets.h @@ -0,0 +1,359 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + + +#ifndef __LWIP_SOCKETS_H__ +#define __LWIP_SOCKETS_H__ + +#include "lwip/opt.h" + +#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ + +#include /* for size_t */ + +#include "lwip/ip_addr.h" +#include "lwip/inet.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* members are in network byte order */ +struct sockaddr_in { + u8_t sin_len; + u8_t sin_family; + u16_t sin_port; + struct in_addr sin_addr; + char sin_zero[8]; +}; + +struct sockaddr { + u8_t sa_len; + u8_t sa_family; + char sa_data[14]; +}; + +#ifndef socklen_t +# define socklen_t u32_t +#endif + +/* Socket protocol types (TCP/UDP/RAW) */ +#define SOCK_STREAM 1 +#define SOCK_DGRAM 2 +#define SOCK_RAW 3 + +/* + * Option flags per-socket. These must match the SOF_ flags in ip.h! + */ +#define SO_DEBUG 0x0001 /* Unimplemented: turn on debugging info recording */ +#define SO_ACCEPTCONN 0x0002 /* socket has had listen() */ +#define SO_REUSEADDR 0x0004 /* Unimplemented: allow local address reuse */ +#define SO_KEEPALIVE 0x0008 /* keep connections alive */ +#define SO_DONTROUTE 0x0010 /* Unimplemented: just use interface addresses */ +#define SO_BROADCAST 0x0020 /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */ +#define SO_USELOOPBACK 0x0040 /* Unimplemented: bypass hardware when possible */ +#define SO_LINGER 0x0080 /* linger on close if data present */ +#define SO_OOBINLINE 0x0100 /* Unimplemented: leave received OOB data in line */ +#define SO_REUSEPORT 0x0200 /* Unimplemented: allow local address & port reuse */ + +#define SO_DONTLINGER ((int)(~SO_LINGER)) + +/* + * Additional options, not kept in so_options. + */ +#define SO_SNDBUF 0x1001 /* Unimplemented: send buffer size */ +#define SO_RCVBUF 0x1002 /* receive buffer size */ +#define SO_SNDLOWAT 0x1003 /* Unimplemented: send low-water mark */ +#define SO_RCVLOWAT 0x1004 /* Unimplemented: receive low-water mark */ +#define SO_SNDTIMEO 0x1005 /* Unimplemented: send timeout */ +#define SO_RCVTIMEO 0x1006 /* receive timeout */ +#define SO_ERROR 0x1007 /* get error status and clear */ +#define SO_TYPE 0x1008 /* get socket type */ +#define SO_CONTIMEO 0x1009 /* Unimplemented: connect timeout */ +#define SO_NO_CHECK 0x100a /* don't create UDP checksum */ + + +/* + * Structure used for manipulating linger option. + */ +struct linger { + int l_onoff; /* option on/off */ + int l_linger; /* linger time */ +}; + +/* + * Level number for (get/set)sockopt() to apply to socket itself. + */ +#define SOL_SOCKET 0xfff /* options for socket level */ + + +#define AF_UNSPEC 0 +#define AF_INET 2 +#define PF_INET AF_INET +#define PF_UNSPEC AF_UNSPEC + +#define IPPROTO_IP 0 +#define IPPROTO_TCP 6 +#define IPPROTO_UDP 17 +#define IPPROTO_UDPLITE 136 + +/* Flags we can use with send and recv. */ +#define MSG_PEEK 0x01 /* Peeks at an incoming message */ +#define MSG_WAITALL 0x02 /* Unimplemented: Requests that the function block until the full amount of data requested can be returned */ +#define MSG_OOB 0x04 /* Unimplemented: Requests out-of-band data. The significance and semantics of out-of-band data are protocol-specific */ +#define MSG_DONTWAIT 0x08 /* Nonblocking i/o for this operation only */ +#define MSG_MORE 0x10 /* Sender will send more */ + + +/* + * Options for level IPPROTO_IP + */ +#define IP_TOS 1 +#define IP_TTL 2 + +#if LWIP_TCP +/* + * Options for level IPPROTO_TCP + */ +#define TCP_NODELAY 0x01 /* don't delay send to coalesce packets */ +#define TCP_KEEPALIVE 0x02 /* send KEEPALIVE probes when idle for pcb->keep_idle milliseconds */ +#define TCP_KEEPIDLE 0x03 /* set pcb->keep_idle - Same as TCP_KEEPALIVE, but use seconds for get/setsockopt */ +#define TCP_KEEPINTVL 0x04 /* set pcb->keep_intvl - Use seconds for get/setsockopt */ +#define TCP_KEEPCNT 0x05 /* set pcb->keep_cnt - Use number of probes sent for get/setsockopt */ +#endif /* LWIP_TCP */ + +#if LWIP_UDP && LWIP_UDPLITE +/* + * Options for level IPPROTO_UDPLITE + */ +#define UDPLITE_SEND_CSCOV 0x01 /* sender checksum coverage */ +#define UDPLITE_RECV_CSCOV 0x02 /* minimal receiver checksum coverage */ +#endif /* LWIP_UDP && LWIP_UDPLITE*/ + + +#if LWIP_IGMP +/* + * Options and types for UDP multicast traffic handling + */ +#define IP_ADD_MEMBERSHIP 3 +#define IP_DROP_MEMBERSHIP 4 +#define IP_MULTICAST_TTL 5 +#define IP_MULTICAST_IF 6 +#define IP_MULTICAST_LOOP 7 + +typedef struct ip_mreq { + struct in_addr imr_multiaddr; /* IP multicast address of group */ + struct in_addr imr_interface; /* local IP address of interface */ +} ip_mreq; +#endif /* LWIP_IGMP */ + +/* + * The Type of Service provides an indication of the abstract + * parameters of the quality of service desired. These parameters are + * to be used to guide the selection of the actual service parameters + * when transmitting a datagram through a particular network. Several + * networks offer service precedence, which somehow treats high + * precedence traffic as more important than other traffic (generally + * by accepting only traffic above a certain precedence at time of high + * load). The major choice is a three way tradeoff between low-delay, + * high-reliability, and high-throughput. + * The use of the Delay, Throughput, and Reliability indications may + * increase the cost (in some sense) of the service. In many networks + * better performance for one of these parameters is coupled with worse + * performance on another. Except for very unusual cases at most two + * of these three indications should be set. + */ +#define IPTOS_TOS_MASK 0x1E +#define IPTOS_TOS(tos) ((tos) & IPTOS_TOS_MASK) +#define IPTOS_LOWDELAY 0x10 +#define IPTOS_THROUGHPUT 0x08 +#define IPTOS_RELIABILITY 0x04 +#define IPTOS_LOWCOST 0x02 +#define IPTOS_MINCOST IPTOS_LOWCOST + +/* + * The Network Control precedence designation is intended to be used + * within a network only. The actual use and control of that + * designation is up to each network. The Internetwork Control + * designation is intended for use by gateway control originators only. + * If the actual use of these precedence designations is of concern to + * a particular network, it is the responsibility of that network to + * control the access to, and use of, those precedence designations. + */ +#define IPTOS_PREC_MASK 0xe0 +#define IPTOS_PREC(tos) ((tos) & IPTOS_PREC_MASK) +#define IPTOS_PREC_NETCONTROL 0xe0 +#define IPTOS_PREC_INTERNETCONTROL 0xc0 +#define IPTOS_PREC_CRITIC_ECP 0xa0 +#define IPTOS_PREC_FLASHOVERRIDE 0x80 +#define IPTOS_PREC_FLASH 0x60 +#define IPTOS_PREC_IMMEDIATE 0x40 +#define IPTOS_PREC_PRIORITY 0x20 +#define IPTOS_PREC_ROUTINE 0x00 + + +/* + * Commands for ioctlsocket(), taken from the BSD file fcntl.h. + * lwip_ioctl only supports FIONREAD and FIONBIO, for now + * + * Ioctl's have the command encoded in the lower word, + * and the size of any in or out parameters in the upper + * word. The high 2 bits of the upper word are used + * to encode the in/out status of the parameter; for now + * we restrict parameters to at most 128 bytes. + */ +#if !defined(FIONREAD) || !defined(FIONBIO) +#define IOCPARM_MASK 0x7fU /* parameters must be < 128 bytes */ +#define IOC_VOID 0x20000000UL /* no parameters */ +#define IOC_OUT 0x40000000UL /* copy out parameters */ +#define IOC_IN 0x80000000UL /* copy in parameters */ +#define IOC_INOUT (IOC_IN|IOC_OUT) + /* 0x20000000 distinguishes new & + old ioctl's */ +#define _IO(x,y) (IOC_VOID|((x)<<8)|(y)) + +#define _IOR(x,y,t) (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) + +#define _IOW(x,y,t) (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) +#endif /* !defined(FIONREAD) || !defined(FIONBIO) */ + +#ifndef FIONREAD +#define FIONREAD _IOR('f', 127, unsigned long) /* get # bytes to read */ +#endif +#ifndef FIONBIO +#define FIONBIO _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */ +#endif + +/* Socket I/O Controls: unimplemented */ +#ifndef SIOCSHIWAT +#define SIOCSHIWAT _IOW('s', 0, unsigned long) /* set high watermark */ +#define SIOCGHIWAT _IOR('s', 1, unsigned long) /* get high watermark */ +#define SIOCSLOWAT _IOW('s', 2, unsigned long) /* set low watermark */ +#define SIOCGLOWAT _IOR('s', 3, unsigned long) /* get low watermark */ +#define SIOCATMARK _IOR('s', 7, unsigned long) /* at oob mark? */ +#endif + +/* Socket flags: */ +#ifndef O_NONBLOCK +#define O_NONBLOCK 04000U +#endif + +/* FD_SET used for lwip_select */ +#ifndef FD_SET + #undef FD_SETSIZE + /* Make FD_SETSIZE match NUM_SOCKETS in socket.c */ + #define FD_SETSIZE MEMP_NUM_NETCONN + #define FD_SET(n, p) ((p)->fd_bits[(n)/8] |= (1 << ((n) & 7))) + #define FD_CLR(n, p) ((p)->fd_bits[(n)/8] &= ~(1 << ((n) & 7))) + #define FD_ISSET(n,p) ((p)->fd_bits[(n)/8] & (1 << ((n) & 7))) + #define FD_ZERO(p) memset((void*)(p),0,sizeof(*(p))) + + typedef struct fd_set { + unsigned char fd_bits [(FD_SETSIZE+7)/8]; + } fd_set; + +#endif /* FD_SET */ + +/** LWIP_TIMEVAL_PRIVATE: if you want to use the struct timeval provided + * by your system, set this to 0 and include in cc.h */ +#ifndef LWIP_TIMEVAL_PRIVATE +#define LWIP_TIMEVAL_PRIVATE 1 +#endif + +#if LWIP_TIMEVAL_PRIVATE +struct timeval { + long tv_sec; /* seconds */ + long tv_usec; /* and microseconds */ +}; +#endif /* LWIP_TIMEVAL_PRIVATE */ + +void lwip_socket_init(void); + +int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen); +int lwip_bind(int s, const struct sockaddr *name, socklen_t namelen); +int lwip_shutdown(int s, int how); +int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen); +int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen); +int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen); +int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen); +int lwip_close(int s); +int lwip_connect(int s, const struct sockaddr *name, socklen_t namelen); +int lwip_listen(int s, int backlog); +int lwip_recv(int s, void *mem, size_t len, int flags); +int lwip_read(int s, void *mem, size_t len); +int lwip_recvfrom(int s, void *mem, size_t len, int flags, + struct sockaddr *from, socklen_t *fromlen); +int lwip_send(int s, const void *dataptr, size_t size, int flags); +int lwip_sendto(int s, const void *dataptr, size_t size, int flags, + const struct sockaddr *to, socklen_t tolen); +int lwip_socket(int domain, int type, int protocol); +int lwip_write(int s, const void *dataptr, size_t size); +int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, + struct timeval *timeout); +int lwip_ioctl(int s, long cmd, void *argp); + +#if LWIP_COMPAT_SOCKETS +#define accept(a,b,c) lwip_accept(a,b,c) +#define bind(a,b,c) lwip_bind(a,b,c) +#define shutdown(a,b) lwip_shutdown(a,b) +#define closesocket(s) lwip_close(s) +#define connect(a,b,c) lwip_connect(a,b,c) +#define getsockname(a,b,c) lwip_getsockname(a,b,c) +#define getpeername(a,b,c) lwip_getpeername(a,b,c) +#define setsockopt(a,b,c,d,e) lwip_setsockopt(a,b,c,d,e) +#define getsockopt(a,b,c,d,e) lwip_getsockopt(a,b,c,d,e) +#define listen(a,b) lwip_listen(a,b) +#define recv(a,b,c,d) lwip_recv(a,b,c,d) +#define recvfrom(a,b,c,d,e,f) lwip_recvfrom(a,b,c,d,e,f) +#define send(a,b,c,d) lwip_send(a,b,c,d) +#define sendto(a,b,c,d,e,f) lwip_sendto(a,b,c,d,e,f) +#define socket(a,b,c) lwip_socket(a,b,c) +#define select(a,b,c,d,e) lwip_select(a,b,c,d,e) +#define ioctlsocket(a,b,c) lwip_ioctl(a,b,c) + +#if LWIP_POSIX_SOCKETS_IO_NAMES +#define read(a,b,c) lwip_read(a,b,c) +#define write(a,b,c) lwip_write(a,b,c) +#define close(s) lwip_close(s) +#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */ + +#endif /* LWIP_COMPAT_SOCKETS */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_SOCKET */ + +#endif /* __LWIP_SOCKETS_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/stats.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/stats.h new file mode 100644 index 0000000000000000000000000000000000000000..4aec5e54485895df10acbcfb5a7e92754ac3c8ca --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/stats.h @@ -0,0 +1,285 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_STATS_H__ +#define __LWIP_STATS_H__ + +#include "lwip/opt.h" + +#include "lwip/mem.h" +#include "lwip/memp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_STATS + +#ifndef LWIP_STATS_LARGE +#define LWIP_STATS_LARGE 0 +#endif + +#if LWIP_STATS_LARGE +#define STAT_COUNTER u32_t +#define STAT_COUNTER_F U32_F +#else +#define STAT_COUNTER u16_t +#define STAT_COUNTER_F U16_F +#endif + +struct stats_proto { + STAT_COUNTER xmit; /* Transmitted packets. */ + STAT_COUNTER recv; /* Received packets. */ + STAT_COUNTER fw; /* Forwarded packets. */ + STAT_COUNTER drop; /* Dropped packets. */ + STAT_COUNTER chkerr; /* Checksum error. */ + STAT_COUNTER lenerr; /* Invalid length error. */ + STAT_COUNTER memerr; /* Out of memory error. */ + STAT_COUNTER rterr; /* Routing error. */ + STAT_COUNTER proterr; /* Protocol error. */ + STAT_COUNTER opterr; /* Error in options. */ + STAT_COUNTER err; /* Misc error. */ + STAT_COUNTER cachehit; +}; + +struct stats_igmp { + STAT_COUNTER lenerr; /* Invalid length error. */ + STAT_COUNTER chkerr; /* Checksum error. */ + STAT_COUNTER v1_rxed; /* */ + STAT_COUNTER join_sent; /* */ + STAT_COUNTER leave_sent; /* */ + STAT_COUNTER unicast_query; /* */ + STAT_COUNTER report_sent; /* */ + STAT_COUNTER report_rxed; /* */ + STAT_COUNTER group_query_rxed; /* */ +}; + +struct stats_mem { + mem_size_t avail; + mem_size_t used; + mem_size_t max; + STAT_COUNTER err; + STAT_COUNTER illegal; +}; + +struct stats_syselem { + STAT_COUNTER used; + STAT_COUNTER max; + STAT_COUNTER err; +}; + +struct stats_sys { + struct stats_syselem sem; + struct stats_syselem mbox; +}; + +struct stats_ { +#if LINK_STATS + struct stats_proto link; +#endif +#if ETHARP_STATS + struct stats_proto etharp; +#endif +#if IPFRAG_STATS + struct stats_proto ip_frag; +#endif +#if IP_STATS + struct stats_proto ip; +#endif +#if ICMP_STATS + struct stats_proto icmp; +#endif +#if IGMP_STATS + struct stats_igmp igmp; +#endif +#if UDP_STATS + struct stats_proto udp; +#endif +#if TCP_STATS + struct stats_proto tcp; +#endif +#if MEM_STATS + struct stats_mem mem; +#endif +#if MEMP_STATS + struct stats_mem memp[MEMP_MAX]; +#endif +#if SYS_STATS + struct stats_sys sys; +#endif +}; + +extern struct stats_ lwip_stats; + +#define stats_init() /* Compatibility define, not init needed. */ + +#define STATS_INC(x) ++lwip_stats.x +#define STATS_DEC(x) --lwip_stats.x +#else +#define stats_init() +#define STATS_INC(x) +#define STATS_DEC(x) +#endif /* LWIP_STATS */ + +#if TCP_STATS +#define TCP_STATS_INC(x) STATS_INC(x) +#define TCP_STATS_DISPLAY() stats_display_proto(&lwip_stats.tcp, "TCP") +#else +#define TCP_STATS_INC(x) +#define TCP_STATS_DISPLAY() +#endif + +#if UDP_STATS +#define UDP_STATS_INC(x) STATS_INC(x) +#define UDP_STATS_DISPLAY() stats_display_proto(&lwip_stats.udp, "UDP") +#else +#define UDP_STATS_INC(x) +#define UDP_STATS_DISPLAY() +#endif + +#if ICMP_STATS +#define ICMP_STATS_INC(x) STATS_INC(x) +#define ICMP_STATS_DISPLAY() stats_display_proto(&lwip_stats.icmp, "ICMP") +#else +#define ICMP_STATS_INC(x) +#define ICMP_STATS_DISPLAY() +#endif + +#if IGMP_STATS +#define IGMP_STATS_INC(x) STATS_INC(x) +#define IGMP_STATS_DISPLAY() stats_display_igmp(&lwip_stats.igmp) +#else +#define IGMP_STATS_INC(x) +#define IGMP_STATS_DISPLAY() +#endif + +#if IP_STATS +#define IP_STATS_INC(x) STATS_INC(x) +#define IP_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip, "IP") +#else +#define IP_STATS_INC(x) +#define IP_STATS_DISPLAY() +#endif + +#if IPFRAG_STATS +#define IPFRAG_STATS_INC(x) STATS_INC(x) +#define IPFRAG_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG") +#else +#define IPFRAG_STATS_INC(x) +#define IPFRAG_STATS_DISPLAY() +#endif + +#if ETHARP_STATS +#define ETHARP_STATS_INC(x) STATS_INC(x) +#define ETHARP_STATS_DISPLAY() stats_display_proto(&lwip_stats.etharp, "ETHARP") +#else +#define ETHARP_STATS_INC(x) +#define ETHARP_STATS_DISPLAY() +#endif + +#if LINK_STATS +#define LINK_STATS_INC(x) STATS_INC(x) +#define LINK_STATS_DISPLAY() stats_display_proto(&lwip_stats.link, "LINK") +#else +#define LINK_STATS_INC(x) +#define LINK_STATS_DISPLAY() +#endif + +#if MEM_STATS +#define MEM_STATS_AVAIL(x, y) lwip_stats.mem.x = y +#define MEM_STATS_INC(x) STATS_INC(mem.x) +#define MEM_STATS_INC_USED(x, y) do { lwip_stats.mem.used += y; \ + if (lwip_stats.mem.max < lwip_stats.mem.used) { \ + lwip_stats.mem.max = lwip_stats.mem.used; \ + } \ + } while(0) +#define MEM_STATS_DEC_USED(x, y) lwip_stats.mem.x -= y +#define MEM_STATS_DISPLAY() stats_display_mem(&lwip_stats.mem, "HEAP") +#else +#define MEM_STATS_AVAIL(x, y) +#define MEM_STATS_INC(x) +#define MEM_STATS_INC_USED(x, y) +#define MEM_STATS_DEC_USED(x, y) +#define MEM_STATS_DISPLAY() +#endif + +#if MEMP_STATS +#define MEMP_STATS_AVAIL(x, i, y) lwip_stats.memp[i].x = y +#define MEMP_STATS_INC(x, i) STATS_INC(memp[i].x) +#define MEMP_STATS_DEC(x, i) STATS_DEC(memp[i].x) +#define MEMP_STATS_INC_USED(x, i) do { ++lwip_stats.memp[i].used; \ + if (lwip_stats.memp[i].max < lwip_stats.memp[i].used) { \ + lwip_stats.memp[i].max = lwip_stats.memp[i].used; \ + } \ + } while(0) +#define MEMP_STATS_DISPLAY(i) stats_display_memp(&lwip_stats.memp[i], i) +#else +#define MEMP_STATS_AVAIL(x, i, y) +#define MEMP_STATS_INC(x, i) +#define MEMP_STATS_DEC(x, i) +#define MEMP_STATS_INC_USED(x, i) +#define MEMP_STATS_DISPLAY(i) +#endif + +#if SYS_STATS +#define SYS_STATS_INC(x) STATS_INC(sys.x) +#define SYS_STATS_DEC(x) STATS_DEC(sys.x) +#define SYS_STATS_DISPLAY() stats_display_sys(&lwip_stats.sys) +#else +#define SYS_STATS_INC(x) +#define SYS_STATS_DEC(x) +#define SYS_STATS_DISPLAY() +#endif + +/* Display of statistics */ +#if LWIP_STATS_DISPLAY +void stats_display(void); +void stats_display_proto(struct stats_proto *proto, char *name); +void stats_display_igmp(struct stats_igmp *igmp); +void stats_display_mem(struct stats_mem *mem, char *name); +void stats_display_memp(struct stats_mem *mem, int index); +void stats_display_sys(struct stats_sys *sys); +#else +#define stats_display() +#define stats_display_proto(proto, name) +#define stats_display_igmp(igmp) +#define stats_display_mem(mem, name) +#define stats_display_memp(mem, index) +#define stats_display_sys(sys) +#endif /* LWIP_STATS_DISPLAY */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_STATS_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/sys.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/sys.h new file mode 100644 index 0000000000000000000000000000000000000000..9a4f02abc7b7ec8650fbbbf09bfcd572a17921a7 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/sys.h @@ -0,0 +1,245 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_SYS_H__ +#define __LWIP_SYS_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if NO_SYS + +/* For a totally minimal and standalone system, we provide null + definitions of the sys_ functions. */ +typedef u8_t sys_sem_t; +typedef u8_t sys_mbox_t; +struct sys_timeo {u8_t dummy;}; + +#define sys_init() +#define sys_timeout(m,h,a) +#define sys_untimeout(m,a) +#define sys_sem_new(c) c +#define sys_sem_signal(s) +#define sys_sem_wait(s) +#define sys_sem_wait_timeout(s,t) +#define sys_arch_sem_wait(s,t) +#define sys_sem_free(s) +#define sys_mbox_new(s) 0 +#define sys_mbox_fetch(m,d) +#define sys_mbox_tryfetch(m,d) +#define sys_mbox_post(m,d) +#define sys_mbox_trypost(m,d) +#define sys_mbox_free(m) + +#define sys_thread_new(n,t,a,s,p) + +#else /* NO_SYS */ + +/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */ +#define SYS_ARCH_TIMEOUT 0xffffffffUL + +/* sys_mbox_tryfetch returns SYS_MBOX_EMPTY if appropriate. + * For now we use the same magic value, but we allow this to change in future. + */ +#define SYS_MBOX_EMPTY SYS_ARCH_TIMEOUT + +#include "lwip/err.h" +#include "arch/sys_arch.h" + +typedef void (* sys_timeout_handler)(void *arg); + +struct sys_timeo { + struct sys_timeo *next; + u32_t time; + sys_timeout_handler h; + void *arg; +}; + +struct sys_timeouts { + struct sys_timeo *next; +}; + +/* sys_init() must be called before anthing else. */ +void sys_init(void); + +/* + * sys_timeout(): + * + * Schedule a timeout a specified amount of milliseconds in the + * future. When the timeout occurs, the specified timeout handler will + * be called. The handler will be passed the "arg" argument when + * called. + * + */ +void sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg); +void sys_untimeout(sys_timeout_handler h, void *arg); +struct sys_timeouts *sys_arch_timeouts(void); + +/* Semaphore functions. */ +sys_sem_t sys_sem_new(u8_t count); +void sys_sem_signal(sys_sem_t sem); +u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout); +void sys_sem_free(sys_sem_t sem); +void sys_sem_wait(sys_sem_t sem); +int sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout); + +/* Time functions. */ +#ifndef sys_msleep +void sys_msleep(u32_t ms); /* only has a (close to) 1 jiffy resolution. */ +#endif +#ifndef sys_jiffies +u32_t sys_jiffies(void); /* since power up. */ +#endif + +/* Mailbox functions. */ +sys_mbox_t sys_mbox_new(int size); +void sys_mbox_post(sys_mbox_t mbox, void *msg); +err_t sys_mbox_trypost(sys_mbox_t mbox, void *msg); +u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout); +#ifndef sys_arch_mbox_tryfetch /* Allow port to override with a macro */ +u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg); +#endif +/* For now, we map straight to sys_arch implementation. */ +#define sys_mbox_tryfetch(mbox, msg) sys_arch_mbox_tryfetch(mbox, msg) +void sys_mbox_free(sys_mbox_t mbox); +void sys_mbox_fetch(sys_mbox_t mbox, void **msg); + +/* Thread functions. */ +sys_thread_t sys_thread_new(char *name, void (* thread)(void *arg), void *arg, int stacksize, int prio); + +#endif /* NO_SYS */ + +/** Returns the current time in milliseconds. */ +u32_t sys_now(void); + +/* Critical Region Protection */ +/* These functions must be implemented in the sys_arch.c file. + In some implementations they can provide a more light-weight protection + mechanism than using semaphores. Otherwise semaphores can be used for + implementation */ +#ifndef SYS_ARCH_PROTECT +/** SYS_LIGHTWEIGHT_PROT + * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection + * for certain critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#if SYS_LIGHTWEIGHT_PROT + +/** SYS_ARCH_DECL_PROTECT + * declare a protection variable. This macro will default to defining a variable of + * type sys_prot_t. If a particular port needs a different implementation, then + * this macro may be defined in sys_arch.h. + */ +#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev +/** SYS_ARCH_PROTECT + * Perform a "fast" protect. This could be implemented by + * disabling interrupts for an embedded system or by using a semaphore or + * mutex. The implementation should allow calling SYS_ARCH_PROTECT when + * already protected. The old protection level is returned in the variable + * "lev". This macro will default to calling the sys_arch_protect() function + * which should be implemented in sys_arch.c. If a particular port needs a + * different implementation, then this macro may be defined in sys_arch.h + */ +#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect() +/** SYS_ARCH_UNPROTECT + * Perform a "fast" set of the protection level to "lev". This could be + * implemented by setting the interrupt level to "lev" within the MACRO or by + * using a semaphore or mutex. This macro will default to calling the + * sys_arch_unprotect() function which should be implemented in + * sys_arch.c. If a particular port needs a different implementation, then + * this macro may be defined in sys_arch.h + */ +#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev) +sys_prot_t sys_arch_protect(void); +void sys_arch_unprotect(sys_prot_t pval); + +#else + +#define SYS_ARCH_DECL_PROTECT(lev) +#define SYS_ARCH_PROTECT(lev) +#define SYS_ARCH_UNPROTECT(lev) + +#endif /* SYS_LIGHTWEIGHT_PROT */ + +#endif /* SYS_ARCH_PROTECT */ + +/* + * Macros to set/get and increase/decrease variables in a thread-safe way. + * Use these for accessing variable that are used from more than one thread. + */ + +#ifndef SYS_ARCH_INC +#define SYS_ARCH_INC(var, val) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + var += val; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_INC */ + +#ifndef SYS_ARCH_DEC +#define SYS_ARCH_DEC(var, val) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + var -= val; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_DEC */ + +#ifndef SYS_ARCH_GET +#define SYS_ARCH_GET(var, ret) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + ret = var; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_GET */ + +#ifndef SYS_ARCH_SET +#define SYS_ARCH_SET(var, val) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + var = val; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_SET */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_SYS_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/tcp.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/tcp.h new file mode 100644 index 0000000000000000000000000000000000000000..c1515744d479a0c3a2438885997db8c49312915b --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/tcp.h @@ -0,0 +1,709 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_TCP_H__ +#define __LWIP_TCP_H__ + +#include "lwip/opt.h" + +#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/sys.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/ip.h" +#include "lwip/icmp.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct tcp_pcb; + +/* Functions for interfacing with TCP: */ + +/* Lower layer interface to TCP: */ +#define tcp_init() /* Compatibility define, not init needed. */ +void tcp_tmr (void); /* Must be called every + TCP_TMR_INTERVAL + ms. (Typically 250 ms). */ +/* Application program's interface: */ +struct tcp_pcb * tcp_new (void); +struct tcp_pcb * tcp_alloc (u8_t prio); + +void tcp_arg (struct tcp_pcb *pcb, void *arg); +void tcp_accept (struct tcp_pcb *pcb, + err_t (* accept)(void *arg, struct tcp_pcb *newpcb, + err_t err)); +void tcp_recv (struct tcp_pcb *pcb, + err_t (* recv)(void *arg, struct tcp_pcb *tpcb, + struct pbuf *p, err_t err)); +void tcp_sent (struct tcp_pcb *pcb, + err_t (* sent)(void *arg, struct tcp_pcb *tpcb, + u16_t len)); +void tcp_poll (struct tcp_pcb *pcb, + err_t (* poll)(void *arg, struct tcp_pcb *tpcb), + u8_t interval); +void tcp_err (struct tcp_pcb *pcb, + void (* err)(void *arg, err_t err)); + +#define tcp_mss(pcb) ((pcb)->mss) +#define tcp_sndbuf(pcb) ((pcb)->snd_buf) +#define tcp_nagle_disable(pcb) ((pcb)->flags |= TF_NODELAY) +#define tcp_nagle_enable(pcb) ((pcb)->flags &= ~TF_NODELAY) +#define tcp_nagle_disabled(pcb) (((pcb)->flags & TF_NODELAY) != 0) + +#if TCP_LISTEN_BACKLOG +#define tcp_accepted(pcb) (((struct tcp_pcb_listen *)(pcb))->accepts_pending--) +#else /* TCP_LISTEN_BACKLOG */ +#define tcp_accepted(pcb) +#endif /* TCP_LISTEN_BACKLOG */ + +void tcp_recved (struct tcp_pcb *pcb, u16_t len); +err_t tcp_bind (struct tcp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port); +err_t tcp_connect (struct tcp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port, err_t (* connected)(void *arg, + struct tcp_pcb *tpcb, + err_t err)); + +struct tcp_pcb * tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog); +#define tcp_listen(pcb) tcp_listen_with_backlog(pcb, TCP_DEFAULT_LISTEN_BACKLOG) + +void tcp_abandon (struct tcp_pcb *pcb, int reset); +#define tcp_abort(pcb) tcp_abandon((pcb), 1) +err_t tcp_close (struct tcp_pcb *pcb); + +/* Flags for "apiflags" parameter in tcp_write and tcp_enqueue */ +#define TCP_WRITE_FLAG_COPY 0x01 +#define TCP_WRITE_FLAG_MORE 0x02 + +err_t tcp_write (struct tcp_pcb *pcb, const void *dataptr, u16_t len, + u8_t apiflags); + +void tcp_setprio (struct tcp_pcb *pcb, u8_t prio); + +#define TCP_PRIO_MIN 1 +#define TCP_PRIO_NORMAL 64 +#define TCP_PRIO_MAX 127 + +/* It is also possible to call these two functions at the right + intervals (instead of calling tcp_tmr()). */ +void tcp_slowtmr (void); +void tcp_fasttmr (void); + + +/* Only used by IP to pass a TCP segment to TCP: */ +void tcp_input (struct pbuf *p, struct netif *inp); +/* Used within the TCP code only: */ +err_t tcp_send_empty_ack(struct tcp_pcb *pcb); +err_t tcp_output (struct tcp_pcb *pcb); +void tcp_rexmit (struct tcp_pcb *pcb); +void tcp_rexmit_rto (struct tcp_pcb *pcb); +void tcp_rexmit_fast (struct tcp_pcb *pcb); +u32_t tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb); + +/** + * This is the Nagle algorithm: try to combine user data to send as few TCP + * segments as possible. Only send if + * - no previously transmitted data on the connection remains unacknowledged or + * - the TF_NODELAY flag is set (nagle algorithm turned off for this pcb) or + * - the only unsent segment is at least pcb->mss bytes long (or there is more + * than one unsent segment - with lwIP, this can happen although unsent->len < mss) + * - or if we are in fast-retransmit (TF_INFR) + */ +#define tcp_do_output_nagle(tpcb) ((((tpcb)->unacked == NULL) || \ + ((tpcb)->flags & (TF_NODELAY | TF_INFR)) || \ + (((tpcb)->unsent != NULL) && (((tpcb)->unsent->next != NULL) || \ + ((tpcb)->unsent->len >= (tpcb)->mss))) \ + ) ? 1 : 0) +#define tcp_output_nagle(tpcb) (tcp_do_output_nagle(tpcb) ? tcp_output(tpcb) : ERR_OK) + + +#define TCP_SEQ_LT(a,b) ((s32_t)((a)-(b)) < 0) +#define TCP_SEQ_LEQ(a,b) ((s32_t)((a)-(b)) <= 0) +#define TCP_SEQ_GT(a,b) ((s32_t)((a)-(b)) > 0) +#define TCP_SEQ_GEQ(a,b) ((s32_t)((a)-(b)) >= 0) +/* is b<=a<=c? */ +#if 0 /* see bug #10548 */ +#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b)) +#endif +#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c)) +#define TCP_FIN 0x01U +#define TCP_SYN 0x02U +#define TCP_RST 0x04U +#define TCP_PSH 0x08U +#define TCP_ACK 0x10U +#define TCP_URG 0x20U +#define TCP_ECE 0x40U +#define TCP_CWR 0x80U + +#define TCP_FLAGS 0x3fU + +/* Length of the TCP header, excluding options. */ +#define TCP_HLEN 20 + +#ifndef TCP_TMR_INTERVAL +#define TCP_TMR_INTERVAL 250 /* The TCP timer interval in milliseconds. */ +#endif /* TCP_TMR_INTERVAL */ + +#ifndef TCP_FAST_INTERVAL +#define TCP_FAST_INTERVAL TCP_TMR_INTERVAL /* the fine grained timeout in milliseconds */ +#endif /* TCP_FAST_INTERVAL */ + +#ifndef TCP_SLOW_INTERVAL +#define TCP_SLOW_INTERVAL (2*TCP_TMR_INTERVAL) /* the coarse grained timeout in milliseconds */ +#endif /* TCP_SLOW_INTERVAL */ + +#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */ +#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */ + +#define TCP_OOSEQ_TIMEOUT 6U /* x RTO */ + +#ifndef TCP_MSL +#define TCP_MSL 60000UL /* The maximum segment lifetime in milliseconds */ +#endif + +/* Keepalive values, compliant with RFC 1122. Don't change this unless you know what you're doing */ +#ifndef TCP_KEEPIDLE_DEFAULT +#define TCP_KEEPIDLE_DEFAULT 7200000UL /* Default KEEPALIVE timer in milliseconds */ +#endif + +#ifndef TCP_KEEPINTVL_DEFAULT +#define TCP_KEEPINTVL_DEFAULT 75000UL /* Default Time between KEEPALIVE probes in milliseconds */ +#endif + +#ifndef TCP_KEEPCNT_DEFAULT +#define TCP_KEEPCNT_DEFAULT 9U /* Default Counter for KEEPALIVE probes */ +#endif + +#define TCP_MAXIDLE TCP_KEEPCNT_DEFAULT * TCP_KEEPINTVL_DEFAULT /* Maximum KEEPALIVE probe time */ + +/* Fields are (of course) in network byte order. + * Some fields are converted to host byte order in tcp_input(). + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct tcp_hdr { + PACK_STRUCT_FIELD(u16_t src); + PACK_STRUCT_FIELD(u16_t dest); + PACK_STRUCT_FIELD(u32_t seqno); + PACK_STRUCT_FIELD(u32_t ackno); + PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags); + PACK_STRUCT_FIELD(u16_t wnd); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u16_t urgp); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define TCPH_OFFSET(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 8) +#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12) +#define TCPH_FLAGS(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS) + +#define TCPH_OFFSET_SET(phdr, offset) (phdr)->_hdrlen_rsvd_flags = htons(((offset) << 8) | TCPH_FLAGS(phdr)) +#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr)) +#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = (((phdr)->_hdrlen_rsvd_flags & htons((u16_t)(~(u16_t)(TCP_FLAGS)))) | htons(flags)) +#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = ((phdr)->_hdrlen_rsvd_flags | htons(flags)) +#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) ) + +#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & (TCP_FIN | TCP_SYN)) != 0)) + +enum tcp_state { + CLOSED = 0, + LISTEN = 1, + SYN_SENT = 2, + SYN_RCVD = 3, + ESTABLISHED = 4, + FIN_WAIT_1 = 5, + FIN_WAIT_2 = 6, + CLOSE_WAIT = 7, + CLOSING = 8, + LAST_ACK = 9, + TIME_WAIT = 10 +}; + +/** Flags used on input processing, not on pcb->flags +*/ +#define TF_RESET (u8_t)0x08U /* Connection was reset. */ +#define TF_CLOSED (u8_t)0x10U /* Connection was sucessfully closed. */ +#define TF_GOT_FIN (u8_t)0x20U /* Connection was closed by the remote end. */ + + +#if LWIP_CALLBACK_API + /* Function to call when a listener has been connected. + * @param arg user-supplied argument (tcp_pcb.callback_arg) + * @param pcb a new tcp_pcb that now is connected + * @param err an error argument (TODO: that is current always ERR_OK?) + * @return ERR_OK: accept the new connection, + * any other err_t abortsthe new connection + */ +#define DEF_ACCEPT_CALLBACK err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err) +#else /* LWIP_CALLBACK_API */ +#define DEF_ACCEPT_CALLBACK +#endif /* LWIP_CALLBACK_API */ + +/** + * members common to struct tcp_pcb and struct tcp_listen_pcb + */ +#define TCP_PCB_COMMON(type) \ + type *next; /* for the linked list */ \ + enum tcp_state state; /* TCP state */ \ + u8_t prio; \ + void *callback_arg; \ + /* ports are in host byte order */ \ + u16_t local_port; \ + /* the accept callback for listen- and normal pcbs, if LWIP_CALLBACK_API */ \ + DEF_ACCEPT_CALLBACK + + +/* the TCP protocol control block */ +struct tcp_pcb { +/** common PCB members */ + IP_PCB; +/** protocol specific PCB members */ + TCP_PCB_COMMON(struct tcp_pcb); + + /* ports are in host byte order */ + u16_t remote_port; + + u8_t flags; +#define TF_ACK_DELAY ((u8_t)0x01U) /* Delayed ACK. */ +#define TF_ACK_NOW ((u8_t)0x02U) /* Immediate ACK. */ +#define TF_INFR ((u8_t)0x04U) /* In fast recovery. */ +#define TF_TIMESTAMP ((u8_t)0x08U) /* Timestamp option enabled */ +#define TF_FIN ((u8_t)0x20U) /* Connection was closed locally (FIN segment enqueued). */ +#define TF_NODELAY ((u8_t)0x40U) /* Disable Nagle algorithm */ +#define TF_NAGLEMEMERR ((u8_t)0x80U) /* nagle enabled, memerr, try to output to prevent delayed ACK to happen */ + + /* the rest of the fields are in host byte order + as we have to do some math with them */ + /* receiver variables */ + u32_t rcv_nxt; /* next seqno expected */ + u16_t rcv_wnd; /* receiver window available */ + u16_t rcv_ann_wnd; /* receiver window to announce */ + u32_t rcv_ann_right_edge; /* announced right edge of window */ + + /* Timers */ + u32_t tmr; + u8_t polltmr, pollinterval; + + /* Retransmission timer. */ + s16_t rtime; + + u16_t mss; /* maximum segment size */ + + /* RTT (round trip time) estimation variables */ + u32_t rttest; /* RTT estimate in 500ms ticks */ + u32_t rtseq; /* sequence number being timed */ + s16_t sa, sv; /* @todo document this */ + + s16_t rto; /* retransmission time-out */ + u8_t nrtx; /* number of retransmissions */ + + /* fast retransmit/recovery */ + u32_t lastack; /* Highest acknowledged seqno. */ + u8_t dupacks; + + /* congestion avoidance/control variables */ + u16_t cwnd; + u16_t ssthresh; + + /* sender variables */ + u32_t snd_nxt; /* next new seqno to be sent */ + u16_t snd_wnd; /* sender window */ + u32_t snd_wl1, snd_wl2; /* Sequence and acknowledgement numbers of last + window update. */ + u32_t snd_lbb; /* Sequence number of next byte to be buffered. */ + + u16_t acked; + + u16_t snd_buf; /* Available buffer space for sending (in bytes). */ +#define TCP_SNDQUEUELEN_OVERFLOW (0xffff-3) + u16_t snd_queuelen; /* Available buffer space for sending (in tcp_segs). */ + + + /* These are ordered by sequence number: */ + struct tcp_seg *unsent; /* Unsent (queued) segments. */ + struct tcp_seg *unacked; /* Sent but unacknowledged segments. */ +#if TCP_QUEUE_OOSEQ + struct tcp_seg *ooseq; /* Received out of sequence segments. */ +#endif /* TCP_QUEUE_OOSEQ */ + + struct pbuf *refused_data; /* Data previously received but not yet taken by upper layer */ + +#if LWIP_CALLBACK_API + /* Function to be called when more send buffer space is available. + * @param arg user-supplied argument (tcp_pcb.callback_arg) + * @param pcb the tcp_pcb which has send buffer space available + * @param space the amount of bytes available + * @return ERR_OK: try to send some data by calling tcp_output + */ + err_t (* sent)(void *arg, struct tcp_pcb *pcb, u16_t space); + + /* Function to be called when (in-sequence) data has arrived. + * @param arg user-supplied argument (tcp_pcb.callback_arg) + * @param pcb the tcp_pcb for which data has arrived + * @param p the packet buffer which arrived + * @param err an error argument (TODO: that is current always ERR_OK?) + * @return ERR_OK: try to send some data by calling tcp_output + */ + err_t (* recv)(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err); + + /* Function to be called when a connection has been set up. + * @param arg user-supplied argument (tcp_pcb.callback_arg) + * @param pcb the tcp_pcb that now is connected + * @param err an error argument (TODO: that is current always ERR_OK?) + * @return value is currently ignored + */ + err_t (* connected)(void *arg, struct tcp_pcb *pcb, err_t err); + + /* Function which is called periodically. + * The period can be adjusted in multiples of the TCP slow timer interval + * by changing tcp_pcb.polltmr. + * @param arg user-supplied argument (tcp_pcb.callback_arg) + * @param pcb the tcp_pcb to poll for + * @return ERR_OK: try to send some data by calling tcp_output + */ + err_t (* poll)(void *arg, struct tcp_pcb *pcb); + + /* Function to be called whenever a fatal error occurs. + * There is no pcb parameter since most of the times, the pcb is + * already deallocated (or there is no pcb) when this function is called. + * @param arg user-supplied argument (tcp_pcb.callback_arg) + * @param err an indication why the error callback is called: + * ERR_ABRT: aborted through tcp_abort or by a TCP timer + * ERR_RST: the connection was reset by the remote host + */ + void (* errf)(void *arg, err_t err); +#endif /* LWIP_CALLBACK_API */ + +#if LWIP_TCP_TIMESTAMPS + u32_t ts_lastacksent; + u32_t ts_recent; +#endif /* LWIP_TCP_TIMESTAMPS */ + + /* idle time before KEEPALIVE is sent */ + u32_t keep_idle; +#if LWIP_TCP_KEEPALIVE + u32_t keep_intvl; + u32_t keep_cnt; +#endif /* LWIP_TCP_KEEPALIVE */ + + /* Persist timer counter */ + u32_t persist_cnt; + /* Persist timer back-off */ + u8_t persist_backoff; + + /* KEEPALIVE counter */ + u8_t keep_cnt_sent; +}; + +struct tcp_pcb_listen { +/* Common members of all PCB types */ + IP_PCB; +/* Protocol specific PCB members */ + TCP_PCB_COMMON(struct tcp_pcb_listen); + +#if TCP_LISTEN_BACKLOG + u8_t backlog; + u8_t accepts_pending; +#endif /* TCP_LISTEN_BACKLOG */ +}; + +#if LWIP_EVENT_API + +enum lwip_event { + LWIP_EVENT_ACCEPT, + LWIP_EVENT_SENT, + LWIP_EVENT_RECV, + LWIP_EVENT_CONNECTED, + LWIP_EVENT_POLL, + LWIP_EVENT_ERR +}; + +err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb, + enum lwip_event, + struct pbuf *p, + u16_t size, + err_t err); + +#define TCP_EVENT_ACCEPT(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_ACCEPT, NULL, 0, err) +#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_SENT, NULL, space, ERR_OK) +#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_RECV, (p), 0, (err)) +#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_CONNECTED, NULL, 0, (err)) +#define TCP_EVENT_POLL(pcb,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_POLL, NULL, 0, ERR_OK) +#define TCP_EVENT_ERR(errf,arg,err) lwip_tcp_event((arg), NULL, \ + LWIP_EVENT_ERR, NULL, 0, (err)) +#else /* LWIP_EVENT_API */ + +#define TCP_EVENT_ACCEPT(pcb,err,ret) \ + do { \ + if((pcb)->accept != NULL) \ + (ret) = (pcb)->accept((pcb)->callback_arg,(pcb),(err)); \ + else (ret) = ERR_OK; \ + } while (0) + +#define TCP_EVENT_SENT(pcb,space,ret) \ + do { \ + if((pcb)->sent != NULL) \ + (ret) = (pcb)->sent((pcb)->callback_arg,(pcb),(space)); \ + else (ret) = ERR_OK; \ + } while (0) + +#define TCP_EVENT_RECV(pcb,p,err,ret) \ + do { \ + if((pcb)->recv != NULL) { \ + (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err)); \ + } else { \ + (ret) = tcp_recv_null(NULL, (pcb), (p), (err)); \ + } \ + } while (0) + +#define TCP_EVENT_CONNECTED(pcb,err,ret) \ + do { \ + if((pcb)->connected != NULL) \ + (ret) = (pcb)->connected((pcb)->callback_arg,(pcb),(err)); \ + else (ret) = ERR_OK; \ + } while (0) + +#define TCP_EVENT_POLL(pcb,ret) \ + do { \ + if((pcb)->poll != NULL) \ + (ret) = (pcb)->poll((pcb)->callback_arg,(pcb)); \ + else (ret) = ERR_OK; \ + } while (0) + +#define TCP_EVENT_ERR(errf,arg,err) \ + do { \ + if((errf) != NULL) \ + (errf)((arg),(err)); \ + } while (0) + +#endif /* LWIP_EVENT_API */ + +/* This structure represents a TCP segment on the unsent and unacked queues */ +struct tcp_seg { + struct tcp_seg *next; /* used when putting segements on a queue */ + struct pbuf *p; /* buffer containing data + TCP header */ + void *dataptr; /* pointer to the TCP data in the pbuf */ + u16_t len; /* the TCP length of this segment */ + u8_t flags; +#define TF_SEG_OPTS_MSS (u8_t)0x01U /* Include MSS option. */ +#define TF_SEG_OPTS_TS (u8_t)0x02U /* Include timestamp option. */ + struct tcp_hdr *tcphdr; /* the TCP header */ +}; + +#define LWIP_TCP_OPT_LENGTH(flags) \ + (flags & TF_SEG_OPTS_MSS ? 4 : 0) + \ + (flags & TF_SEG_OPTS_TS ? 12 : 0) + +/** This returns a TCP header option for MSS in an u32_t */ +#define TCP_BUILD_MSS_OPTION(x) (x) = htonl(((u32_t)2 << 24) | \ + ((u32_t)4 << 16) | \ + (((u32_t)TCP_MSS / 256) << 8) | \ + (TCP_MSS & 255)) + +/* Internal functions and global variables: */ +struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb); +void tcp_pcb_purge(struct tcp_pcb *pcb); +void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb); + +u8_t tcp_segs_free(struct tcp_seg *seg); +u8_t tcp_seg_free(struct tcp_seg *seg); +struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg); + +#define tcp_ack(pcb) \ + do { \ + if((pcb)->flags & TF_ACK_DELAY) { \ + (pcb)->flags &= ~TF_ACK_DELAY; \ + (pcb)->flags |= TF_ACK_NOW; \ + tcp_output(pcb); \ + } \ + else { \ + (pcb)->flags |= TF_ACK_DELAY; \ + } \ + } while (0) + +#define tcp_ack_now(pcb) \ + do { \ + (pcb)->flags |= TF_ACK_NOW; \ + tcp_output(pcb); \ + } while (0) + +err_t tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags); +err_t tcp_enqueue(struct tcp_pcb *pcb, void *dataptr, u16_t len, + u8_t flags, u8_t apiflags, u8_t optflags); + +void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg); + +void tcp_rst(u32_t seqno, u32_t ackno, + struct ip_addr *local_ip, struct ip_addr *remote_ip, + u16_t local_port, u16_t remote_port); + +u32_t tcp_next_iss(void); + +void tcp_keepalive(struct tcp_pcb *pcb); +void tcp_zero_window_probe(struct tcp_pcb *pcb); + +#if TCP_CALCULATE_EFF_SEND_MSS +u16_t tcp_eff_send_mss(u16_t sendmss, struct ip_addr *addr); +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + +#if LWIP_CALLBACK_API +err_t tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err); +#endif /* LWIP_CALLBACK_API */ + +extern struct tcp_pcb *tcp_input_pcb; +extern u32_t tcp_ticks; + +const char* tcp_debug_state_str(enum tcp_state s); +#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG +void tcp_debug_print(struct tcp_hdr *tcphdr); +void tcp_debug_print_flags(u8_t flags); +void tcp_debug_print_state(enum tcp_state s); +void tcp_debug_print_pcbs(void); +s16_t tcp_pcbs_sane(void); +#else +# define tcp_debug_print(tcphdr) +# define tcp_debug_print_flags(flags) +# define tcp_debug_print_state(s) +# define tcp_debug_print_pcbs() +# define tcp_pcbs_sane() 1 +#endif /* TCP_DEBUG */ + +#if NO_SYS +#define tcp_timer_needed() +#else +void tcp_timer_needed(void); +#endif + +/* The TCP PCB lists. */ +union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */ + struct tcp_pcb_listen *listen_pcbs; + struct tcp_pcb *pcbs; +}; +extern union tcp_listen_pcbs_t tcp_listen_pcbs; +extern struct tcp_pcb *tcp_active_pcbs; /* List of all TCP PCBs that are in a + state in which they accept or send + data. */ +extern struct tcp_pcb *tcp_tw_pcbs; /* List of all TCP PCBs in TIME-WAIT. */ + +extern struct tcp_pcb *tcp_tmp_pcb; /* Only used for temporary storage. */ + +/* Axioms about the above lists: + 1) Every TCP PCB that is not CLOSED is in one of the lists. + 2) A PCB is only in one of the lists. + 3) All PCBs in the tcp_listen_pcbs list is in LISTEN state. + 4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state. +*/ + +/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB + with a PCB list or removes a PCB from a list, respectively. */ +#if 0 +#define TCP_REG(pcbs, npcb) do {\ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", npcb, npcb->local_port)); \ + for(tcp_tmp_pcb = *pcbs; \ + tcp_tmp_pcb != NULL; \ + tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != npcb); \ + } \ + LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", npcb->state != CLOSED); \ + npcb->next = *pcbs; \ + LWIP_ASSERT("TCP_REG: npcb->next != npcb", npcb->next != npcb); \ + *(pcbs) = npcb; \ + LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ + tcp_timer_needed(); \ + } while(0) +#define TCP_RMV(pcbs, npcb) do { \ + LWIP_ASSERT("TCP_RMV: pcbs != NULL", *pcbs != NULL); \ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", npcb, *pcbs)); \ + if(*pcbs == npcb) { \ + *pcbs = (*pcbs)->next; \ + } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + if(tcp_tmp_pcb->next == npcb) { \ + tcp_tmp_pcb->next = npcb->next; \ + break; \ + } \ + } \ + npcb->next = NULL; \ + LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", npcb, *pcbs)); \ + } while(0) + +#else /* LWIP_DEBUG */ + +#define TCP_REG(pcbs, npcb) \ + do { \ + npcb->next = *pcbs; \ + *(pcbs) = npcb; \ + tcp_timer_needed(); \ + } while (0) + +#define TCP_RMV(pcbs, npcb) \ + do { \ + if(*(pcbs) == npcb) { \ + (*(pcbs)) = (*pcbs)->next; \ + } \ + else { \ + for(tcp_tmp_pcb = *pcbs; \ + tcp_tmp_pcb != NULL; \ + tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + if(tcp_tmp_pcb->next == npcb) { \ + tcp_tmp_pcb->next = npcb->next; \ + break; \ + } \ + } \ + } \ + npcb->next = NULL; \ + } while(0) + +#endif /* LWIP_DEBUG */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_TCP */ + +#endif /* __LWIP_TCP_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/tcpip.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/tcpip.h new file mode 100644 index 0000000000000000000000000000000000000000..00a3ec5dc2ece7135d616992c11f422c29362d4b --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/tcpip.h @@ -0,0 +1,143 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_TCPIP_H__ +#define __LWIP_TCPIP_H__ + +#include "lwip/opt.h" + +#if !NO_SYS /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/api_msg.h" +#include "lwip/netifapi.h" +#include "lwip/pbuf.h" +#include "lwip/api.h" +#include "lwip/sys.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_TCPIP_CORE_LOCKING +/** The global semaphore to lock the stack. */ +extern sys_sem_t lock_tcpip_core; +#define LOCK_TCPIP_CORE() sys_sem_wait(lock_tcpip_core) +#define UNLOCK_TCPIP_CORE() sys_sem_signal(lock_tcpip_core) +#define TCPIP_APIMSG(m) tcpip_apimsg_lock(m) +#define TCPIP_APIMSG_ACK(m) +#define TCPIP_NETIFAPI(m) tcpip_netifapi_lock(m) +#define TCPIP_NETIFAPI_ACK(m) +#else +#define LOCK_TCPIP_CORE() +#define UNLOCK_TCPIP_CORE() +#define TCPIP_APIMSG(m) tcpip_apimsg(m) +#define TCPIP_APIMSG_ACK(m) sys_sem_signal(m->conn->op_completed) +#define TCPIP_NETIFAPI(m) tcpip_netifapi(m) +#define TCPIP_NETIFAPI_ACK(m) sys_sem_signal(m->sem) +#endif /* LWIP_TCPIP_CORE_LOCKING */ + +void tcpip_init(void (* tcpip_init_done)(void *), void *arg); + +#if LWIP_NETCONN +err_t tcpip_apimsg(struct api_msg *apimsg); +#if LWIP_TCPIP_CORE_LOCKING +err_t tcpip_apimsg_lock(struct api_msg *apimsg); +#endif /* LWIP_TCPIP_CORE_LOCKING */ +#endif /* LWIP_NETCONN */ + +err_t tcpip_input(struct pbuf *p, struct netif *inp); + +#if LWIP_NETIF_API +err_t tcpip_netifapi(struct netifapi_msg *netifapimsg); +#if LWIP_TCPIP_CORE_LOCKING +err_t tcpip_netifapi_lock(struct netifapi_msg *netifapimsg); +#endif /* LWIP_TCPIP_CORE_LOCKING */ +#endif /* LWIP_NETIF_API */ + +err_t tcpip_callback_with_block(void (*f)(void *ctx), void *ctx, u8_t block); +#define tcpip_callback(f, ctx) tcpip_callback_with_block(f, ctx, 1) + +/* free pbufs or heap memory from another context without blocking */ +err_t pbuf_free_callback(struct pbuf *p); +err_t mem_free_callback(void *m); + +err_t tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg); +err_t tcpip_untimeout(sys_timeout_handler h, void *arg); + +enum tcpip_msg_type { +#if LWIP_NETCONN + TCPIP_MSG_API, +#endif /* LWIP_NETCONN */ + TCPIP_MSG_INPKT, +#if LWIP_NETIF_API + TCPIP_MSG_NETIFAPI, +#endif /* LWIP_NETIF_API */ + TCPIP_MSG_CALLBACK, + TCPIP_MSG_TIMEOUT, + TCPIP_MSG_UNTIMEOUT +}; + +struct tcpip_msg { + enum tcpip_msg_type type; + sys_sem_t *sem; + union { +#if LWIP_NETCONN + struct api_msg *apimsg; +#endif /* LWIP_NETCONN */ +#if LWIP_NETIF_API + struct netifapi_msg *netifapimsg; +#endif /* LWIP_NETIF_API */ + struct { + struct pbuf *p; + struct netif *netif; + } inp; + struct { + void (*f)(void *ctx); + void *ctx; + } cb; + struct { + u32_t msecs; + sys_timeout_handler h; + void *arg; + } tmo; + } msg; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* !NO_SYS */ + +#endif /* __LWIP_TCPIP_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/udp.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/udp.h new file mode 100644 index 0000000000000000000000000000000000000000..1269ee19cfc2ccab03fbc657c0a135266c0ffa48 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/lwip/udp.h @@ -0,0 +1,155 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_UDP_H__ +#define __LWIP_UDP_H__ + +#include "lwip/opt.h" + +#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/netif.h" +#include "lwip/ip_addr.h" +#include "lwip/ip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define UDP_HLEN 8 + +/* Fields are (of course) in network byte order. */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct udp_hdr { + PACK_STRUCT_FIELD(u16_t src); + PACK_STRUCT_FIELD(u16_t dest); /* src/dest UDP ports */ + PACK_STRUCT_FIELD(u16_t len); + PACK_STRUCT_FIELD(u16_t chksum); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define UDP_FLAGS_NOCHKSUM 0x01U +#define UDP_FLAGS_UDPLITE 0x02U +#define UDP_FLAGS_CONNECTED 0x04U + +struct udp_pcb { +/* Common members of all PCB types */ + IP_PCB; + +/* Protocol specific PCB members */ + + struct udp_pcb *next; + + u8_t flags; + /* ports are in host byte order */ + u16_t local_port, remote_port; + +#if LWIP_IGMP + /* outgoing network interface for multicast packets */ + struct ip_addr multicast_ip; +#endif /* LWIP_IGMP */ + +#if LWIP_UDPLITE + /* used for UDP_LITE only */ + u16_t chksum_len_rx, chksum_len_tx; +#endif /* LWIP_UDPLITE */ + + /* receive callback function + * addr and port are in same byte order as in the pcb + * The callback is responsible for freeing the pbuf + * if it's not used any more. + * + * ATTENTION: Be aware that 'addr' points into the pbuf 'p' so freeing this pbuf + * makes 'addr' invalid, too. + * + * @param arg user supplied argument (udp_pcb.recv_arg) + * @param pcb the udp_pcb which received data + * @param p the packet buffer that was received + * @param addr the remote IP address from which the packet was received + * @param port the remote port from which the packet was received + */ + void (* recv)(void *arg, struct udp_pcb *pcb, struct pbuf *p, + struct ip_addr *addr, u16_t port); + /* user-supplied argument for the recv callback */ + void *recv_arg; +}; +/* udp_pcbs export for exernal reference (e.g. SNMP agent) */ +extern struct udp_pcb *udp_pcbs; + +/* The following functions is the application layer interface to the + UDP code. */ +struct udp_pcb * udp_new (void); +void udp_remove (struct udp_pcb *pcb); +err_t udp_bind (struct udp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port); +err_t udp_connect (struct udp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port); +void udp_disconnect (struct udp_pcb *pcb); +void udp_recv (struct udp_pcb *pcb, + void (* recv)(void *arg, struct udp_pcb *upcb, + struct pbuf *p, + struct ip_addr *addr, + u16_t port), + void *recv_arg); +err_t udp_sendto_if (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port, struct netif *netif); +err_t udp_sendto (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port); +err_t udp_send (struct udp_pcb *pcb, struct pbuf *p); + +#define udp_flags(pcb) ((pcb)->flags) +#define udp_setflags(pcb, f) ((pcb)->flags = (f)) + +/* The following functions are the lower layer interface to UDP. */ +void udp_input (struct pbuf *p, struct netif *inp); + +#define udp_init() /* Compatibility define, not init needed. */ + +#if UDP_DEBUG +void udp_debug_print(struct udp_hdr *udphdr); +#else +#define udp_debug_print(udphdr) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_UDP */ + +#endif /* __LWIP_UDP_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/netif/etharp.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/netif/etharp.h new file mode 100644 index 0000000000000000000000000000000000000000..fb1542a77d745a048dcf49ed138c158a74818007 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/netif/etharp.h @@ -0,0 +1,194 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * Copyright (c) 2003-2004 Leon Woestenberg + * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __NETIF_ETHARP_H__ +#define __NETIF_ETHARP_H__ + +#include "lwip/opt.h" + +#if LWIP_ARP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/ip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ETH_PAD_SIZE +#define ETH_PAD_SIZE 0 +#endif + +#ifndef ETHARP_HWADDR_LEN +#define ETHARP_HWADDR_LEN 6 +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct eth_addr { + PACK_STRUCT_FIELD(u8_t addr[ETHARP_HWADDR_LEN]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct eth_hdr { +#if ETH_PAD_SIZE + PACK_STRUCT_FIELD(u8_t padding[ETH_PAD_SIZE]); +#endif + PACK_STRUCT_FIELD(struct eth_addr dest); + PACK_STRUCT_FIELD(struct eth_addr src); + PACK_STRUCT_FIELD(u16_t type); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define SIZEOF_ETH_HDR (14 + ETH_PAD_SIZE) + +#if ETHARP_SUPPORT_VLAN + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct eth_vlan_hdr { + PACK_STRUCT_FIELD(u16_t tpid); + PACK_STRUCT_FIELD(u16_t prio_vid); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define SIZEOF_VLAN_HDR 4 +#define VLAN_ID(vlan_hdr) (htons((vlan_hdr)->prio_vid) & 0xFFF) + +#endif /* ETHARP_SUPPORT_VLAN */ + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** the ARP message */ +struct etharp_hdr { + PACK_STRUCT_FIELD(u16_t hwtype); + PACK_STRUCT_FIELD(u16_t proto); + PACK_STRUCT_FIELD(u16_t _hwlen_protolen); + PACK_STRUCT_FIELD(u16_t opcode); + PACK_STRUCT_FIELD(struct eth_addr shwaddr); + PACK_STRUCT_FIELD(struct ip_addr2 sipaddr); + PACK_STRUCT_FIELD(struct eth_addr dhwaddr); + PACK_STRUCT_FIELD(struct ip_addr2 dipaddr); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define SIZEOF_ETHARP_HDR 28 +#define SIZEOF_ETHARP_PACKET (SIZEOF_ETH_HDR + SIZEOF_ETHARP_HDR) + +/** 5 seconds period */ +#define ARP_TMR_INTERVAL 5000 + +#define ETHTYPE_ARP 0x0806 +#define ETHTYPE_IP 0x0800 +#define ETHTYPE_VLAN 0x8100 +#define ETHTYPE_PPPOEDISC 0x8863 /* PPP Over Ethernet Discovery Stage */ +#define ETHTYPE_PPPOE 0x8864 /* PPP Over Ethernet Session Stage */ + +/** ARP message types (opcodes) */ +#define ARP_REQUEST 1 +#define ARP_REPLY 2 + +#if ARP_QUEUEING +/** struct for queueing outgoing packets for unknown address + * defined here to be accessed by memp.h + */ +struct etharp_q_entry { + struct etharp_q_entry *next; + struct pbuf *p; +}; +#endif /* ARP_QUEUEING */ + +#define etharp_init() /* Compatibility define, not init needed. */ +void etharp_tmr(void); +s8_t etharp_find_addr(struct netif *netif, struct ip_addr *ipaddr, + struct eth_addr **eth_ret, struct ip_addr **ip_ret); +void etharp_ip_input(struct netif *netif, struct pbuf *p); +void etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, + struct pbuf *p); +err_t etharp_output(struct netif *netif, struct pbuf *q, struct ip_addr *ipaddr); +err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q); +err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr); +/** For Ethernet network interfaces, we might want to send "gratuitous ARP"; + * this is an ARP packet sent by a node in order to spontaneously cause other + * nodes to update an entry in their ARP cache. + * From RFC 3220 "IP Mobility Support for IPv4" section 4.6. */ +#define etharp_gratuitous(netif) etharp_request((netif), &(netif)->ip_addr) + +err_t ethernet_input(struct pbuf *p, struct netif *netif); + +#if LWIP_AUTOIP +err_t etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr, + const struct eth_addr *ethdst_addr, + const struct eth_addr *hwsrc_addr, const struct ip_addr *ipsrc_addr, + const struct eth_addr *hwdst_addr, const struct ip_addr *ipdst_addr, + const u16_t opcode); +#endif /* LWIP_AUTOIP */ + +#define eth_addr_cmp(addr1, addr2) (memcmp((addr1)->addr, (addr2)->addr, ETHARP_HWADDR_LEN) == 0) + +extern const struct eth_addr ethbroadcast, ethzero; + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_ARP */ + +#endif /* __NETIF_ARP_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/netif/loopif.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/netif/loopif.h new file mode 100644 index 0000000000000000000000000000000000000000..3f4fa62cb7e9223e46ffb47605daa04f7c5a72e8 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/netif/loopif.h @@ -0,0 +1,55 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __NETIF_LOOPIF_H__ +#define __NETIF_LOOPIF_H__ + +#include "lwip/opt.h" +#include "lwip/netif.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if !LWIP_NETIF_LOOPBACK_MULTITHREADING +#define loopif_poll netif_poll +#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */ + +err_t loopif_init(struct netif *netif); + +#ifdef __cplusplus +} +#endif + +#endif /* __NETIF_LOOPIF_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/netif/ppp_oe.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/netif/ppp_oe.h new file mode 100644 index 0000000000000000000000000000000000000000..fac0a78d066c1157e18357c745b889e203e9c89d --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/netif/ppp_oe.h @@ -0,0 +1,163 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/***************************************************************************** +* ppp_oe.h - PPP Over Ethernet implementation for lwIP. +* +* Copyright (c) 2006 by Marc Boucher, Services Informatiques (MBSI) inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 06-01-01 Marc Boucher +* Ported to lwIP. +*****************************************************************************/ + + + +/* based on NetBSD: if_pppoe.c,v 1.64 2006/01/31 23:50:15 martin Exp */ + +/*- + * Copyright (c) 2002 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Martin Husemann . + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef PPP_OE_H +#define PPP_OE_H + +#include "lwip/opt.h" + +#if PPPOE_SUPPORT > 0 + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct pppoehdr { + PACK_STRUCT_FIELD(u8_t vertype); + PACK_STRUCT_FIELD(u8_t code); + PACK_STRUCT_FIELD(u16_t session); + PACK_STRUCT_FIELD(u16_t plen); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct pppoetag { + PACK_STRUCT_FIELD(u16_t tag); + PACK_STRUCT_FIELD(u16_t len); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + + +#define PPPOE_STATE_INITIAL 0 +#define PPPOE_STATE_PADI_SENT 1 +#define PPPOE_STATE_PADR_SENT 2 +#define PPPOE_STATE_SESSION 3 +#define PPPOE_STATE_CLOSING 4 +/* passive */ +#define PPPOE_STATE_PADO_SENT 1 + +#define PPPOE_HEADERLEN sizeof(struct pppoehdr) +#define PPPOE_VERTYPE 0x11 /* VER=1, TYPE = 1 */ + +#define PPPOE_TAG_EOL 0x0000 /* end of list */ +#define PPPOE_TAG_SNAME 0x0101 /* service name */ +#define PPPOE_TAG_ACNAME 0x0102 /* access concentrator name */ +#define PPPOE_TAG_HUNIQUE 0x0103 /* host unique */ +#define PPPOE_TAG_ACCOOKIE 0x0104 /* AC cookie */ +#define PPPOE_TAG_VENDOR 0x0105 /* vendor specific */ +#define PPPOE_TAG_RELAYSID 0x0110 /* relay session id */ +#define PPPOE_TAG_SNAME_ERR 0x0201 /* service name error */ +#define PPPOE_TAG_ACSYS_ERR 0x0202 /* AC system error */ +#define PPPOE_TAG_GENERIC_ERR 0x0203 /* gerneric error */ + +#define PPPOE_CODE_PADI 0x09 /* Active Discovery Initiation */ +#define PPPOE_CODE_PADO 0x07 /* Active Discovery Offer */ +#define PPPOE_CODE_PADR 0x19 /* Active Discovery Request */ +#define PPPOE_CODE_PADS 0x65 /* Active Discovery Session confirmation */ +#define PPPOE_CODE_PADT 0xA7 /* Active Discovery Terminate */ + +#ifndef ETHERMTU +#define ETHERMTU 1500 +#endif + +/* two byte PPP protocol discriminator, then IP data */ +#define PPPOE_MAXMTU (ETHERMTU-PPPOE_HEADERLEN-2) + +struct pppoe_softc; + + +void pppoe_init(void); + +err_t pppoe_create(struct netif *ethif, int pd, void (*linkStatusCB)(int pd, int up), struct pppoe_softc **scptr); +err_t pppoe_destroy(struct netif *ifp); + +int pppoe_connect(struct pppoe_softc *sc); +void pppoe_disconnect(struct pppoe_softc *sc); + +void pppoe_disc_input(struct netif *netif, struct pbuf *p); +void pppoe_data_input(struct netif *netif, struct pbuf *p); + +err_t pppoe_xmit(struct pppoe_softc *sc, struct pbuf *pb); + +extern int pppoe_hdrlen; + +#endif /* PPPOE_SUPPORT */ + +#endif /* PPP_OE_H */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/netif/slipif.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/netif/slipif.h new file mode 100644 index 0000000000000000000000000000000000000000..ddc2dfa56789c50a583fffe01ede272740e2e039 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/netif/slipif.h @@ -0,0 +1,53 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __NETIF_SLIPIF_H__ +#define __NETIF_SLIPIF_H__ + +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +err_t slipif_init(struct netif * netif); +void slipif_poll(struct netif *netif); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/netif/etharp.c b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/netif/etharp.c new file mode 100644 index 0000000000000000000000000000000000000000..1a5d134041e3334df819908be535d762f813cec9 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/netif/etharp.c @@ -0,0 +1,1224 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/** + * @file + * Address Resolution Protocol module for IP over Ethernet + * + * Functionally, ARP is divided into two parts. The first maps an IP address + * to a physical address when sending a packet, and the second part answers + * requests from other machines for our physical address. + * + * This implementation complies with RFC 826 (Ethernet ARP). It supports + * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6 + * if an interface calls etharp_gratuitous(our_netif) upon address change. + */ + +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * Copyright (c) 2003-2004 Leon Woestenberg + * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#include "lwip/opt.h" + +#if LWIP_ARP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/inet.h" +#include "lwip/ip.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" +#include "lwip/dhcp.h" +#include "lwip/autoip.h" +#include "netif/etharp.h" + +#if PPPOE_SUPPORT +#include "netif/ppp_oe.h" +#endif /* PPPOE_SUPPORT */ + +#include + +/** the time an ARP entry stays valid after its last update, + * for ARP_TMR_INTERVAL = 5000, this is + * (240 * 5) seconds = 20 minutes. + */ +#define ARP_MAXAGE 240 +/** the time an ARP entry stays pending after first request, + * for ARP_TMR_INTERVAL = 5000, this is + * (2 * 5) seconds = 10 seconds. + * + * @internal Keep this number at least 2, otherwise it might + * run out instantly if the timeout occurs directly after a request. + */ +#define ARP_MAXPENDING 2 + +#define HWTYPE_ETHERNET 1 + +#define ARPH_HWLEN(hdr) (ntohs((hdr)->_hwlen_protolen) >> 8) +#define ARPH_PROTOLEN(hdr) (ntohs((hdr)->_hwlen_protolen) & 0xff) + +#define ARPH_HWLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons(ARPH_PROTOLEN(hdr) | ((len) << 8)) +#define ARPH_PROTOLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons((len) | (ARPH_HWLEN(hdr) << 8)) + +enum etharp_state { + ETHARP_STATE_EMPTY = 0, + ETHARP_STATE_PENDING, + ETHARP_STATE_STABLE +}; + +struct etharp_entry { +#if ARP_QUEUEING + /** + * Pointer to queue of pending outgoing packets on this ARP entry. + */ + struct etharp_q_entry *q; +#endif + struct ip_addr ipaddr; + struct eth_addr ethaddr; + enum etharp_state state; + u8_t ctime; + struct netif *netif; +}; + +const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}}; +const struct eth_addr ethzero = {{0,0,0,0,0,0}}; +static struct etharp_entry arp_table[ARP_TABLE_SIZE]; +#if !LWIP_NETIF_HWADDRHINT +static u8_t etharp_cached_entry; +#endif + +/** + * Try hard to create a new entry - we want the IP address to appear in + * the cache (even if this means removing an active entry or so). */ +#define ETHARP_TRY_HARD 1 +#define ETHARP_FIND_ONLY 2 + +#if LWIP_NETIF_HWADDRHINT +#define NETIF_SET_HINT(netif, hint) if (((netif) != NULL) && ((netif)->addr_hint != NULL)) \ + *((netif)->addr_hint) = (hint); +static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags, struct netif *netif); +#else /* LWIP_NETIF_HWADDRHINT */ +static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags); +#endif /* LWIP_NETIF_HWADDRHINT */ + +static err_t update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags); + + +/* Some checks, instead of etharp_init(): */ +#if (LWIP_ARP && (ARP_TABLE_SIZE > 0x7f)) + #error "If you want to use ARP, ARP_TABLE_SIZE must fit in an s8_t, so, you have to reduce it in your lwipopts.h" +#endif + + +#if ARP_QUEUEING +/** + * Free a complete queue of etharp entries + * + * @param q a qeueue of etharp_q_entry's to free + */ +static void +free_etharp_q(struct etharp_q_entry *q) +{ + struct etharp_q_entry *r; + LWIP_ASSERT("q != NULL", q != NULL); + LWIP_ASSERT("q->p != NULL", q->p != NULL); + while (q) { + r = q; + q = q->next; + LWIP_ASSERT("r->p != NULL", (r->p != NULL)); + pbuf_free(r->p); + memp_free(MEMP_ARP_QUEUE, r); + } +} +#endif + +/** + * Clears expired entries in the ARP table. + * + * This function should be called every ETHARP_TMR_INTERVAL microseconds (5 seconds), + * in order to expire entries in the ARP table. + */ +void +etharp_tmr(void) +{ + u8_t i; + + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n")); + /* remove expired entries from the ARP table */ + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + arp_table[i].ctime++; + if (((arp_table[i].state == ETHARP_STATE_STABLE) && + (arp_table[i].ctime >= ARP_MAXAGE)) || + ((arp_table[i].state == ETHARP_STATE_PENDING) && + (arp_table[i].ctime >= ARP_MAXPENDING))) { + /* pending or stable entry has become old! */ + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired %s entry %"U16_F".\n", + arp_table[i].state == ETHARP_STATE_STABLE ? "stable" : "pending", (u16_t)i)); + /* clean up entries that have just been expired */ + /* remove from SNMP ARP index tree */ + snmp_delete_arpidx_tree(arp_table[i].netif, &arp_table[i].ipaddr); +#if ARP_QUEUEING + /* and empty packet queue */ + if (arp_table[i].q != NULL) { + /* remove all queued packets */ + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].q))); + free_etharp_q(arp_table[i].q); + arp_table[i].q = NULL; + } +#endif + /* recycle entry for re-use */ + arp_table[i].state = ETHARP_STATE_EMPTY; + } +#if ARP_QUEUEING + /* still pending entry? (not expired) */ + if (arp_table[i].state == ETHARP_STATE_PENDING) { + /* resend an ARP query here? */ + } +#endif + } +} + +/** + * Search the ARP table for a matching or new entry. + * + * If an IP address is given, return a pending or stable ARP entry that matches + * the address. If no match is found, create a new entry with this address set, + * but in state ETHARP_EMPTY. The caller must check and possibly change the + * state of the returned entry. + * + * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY. + * + * In all cases, attempt to create new entries from an empty entry. If no + * empty entries are available and ETHARP_TRY_HARD flag is set, recycle + * old entries. Heuristic choose the least important entry for recycling. + * + * @param ipaddr IP address to find in ARP cache, or to add if not found. + * @param flags + * - ETHARP_TRY_HARD: Try hard to create a entry by allowing recycling of + * active (stable or pending) entries. + * + * @return The ARP entry index that matched or is created, ERR_MEM if no + * entry is found or could be recycled. + */ +static s8_t +#if LWIP_NETIF_HWADDRHINT +find_entry(struct ip_addr *ipaddr, u8_t flags, struct netif *netif) +#else /* LWIP_NETIF_HWADDRHINT */ +find_entry(struct ip_addr *ipaddr, u8_t flags) +#endif /* LWIP_NETIF_HWADDRHINT */ +{ + s8_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE; + s8_t empty = ARP_TABLE_SIZE; + u8_t i = 0, age_pending = 0, age_stable = 0; +#if ARP_QUEUEING + /* oldest entry with packets on queue */ + s8_t old_queue = ARP_TABLE_SIZE; + /* its age */ + u8_t age_queue = 0; +#endif + + /* First, test if the last call to this function asked for the + * same address. If so, we're really fast! */ + if (ipaddr) { + /* ipaddr to search for was given */ +#if LWIP_NETIF_HWADDRHINT + if ((netif != NULL) && (netif->addr_hint != NULL)) { + /* per-pcb cached entry was given */ + u8_t per_pcb_cache = *(netif->addr_hint); + if ((per_pcb_cache < ARP_TABLE_SIZE) && arp_table[per_pcb_cache].state == ETHARP_STATE_STABLE) { + /* the per-pcb-cached entry is stable */ + if (ip_addr_cmp(ipaddr, &arp_table[per_pcb_cache].ipaddr)) { + /* per-pcb cached entry was the right one! */ + ETHARP_STATS_INC(etharp.cachehit); + return per_pcb_cache; + } + } + } +#else /* #if LWIP_NETIF_HWADDRHINT */ + if (arp_table[etharp_cached_entry].state == ETHARP_STATE_STABLE) { + /* the cached entry is stable */ + if (ip_addr_cmp(ipaddr, &arp_table[etharp_cached_entry].ipaddr)) { + /* cached entry was the right one! */ + ETHARP_STATS_INC(etharp.cachehit); + return etharp_cached_entry; + } + } +#endif /* #if LWIP_NETIF_HWADDRHINT */ + } + + /** + * a) do a search through the cache, remember candidates + * b) select candidate entry + * c) create new entry + */ + + /* a) in a single search sweep, do all of this + * 1) remember the first empty entry (if any) + * 2) remember the oldest stable entry (if any) + * 3) remember the oldest pending entry without queued packets (if any) + * 4) remember the oldest pending entry with queued packets (if any) + * 5) search for a matching IP entry, either pending or stable + * until 5 matches, or all entries are searched for. + */ + + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + /* no empty entry found yet and now we do find one? */ + if ((empty == ARP_TABLE_SIZE) && (arp_table[i].state == ETHARP_STATE_EMPTY)) { + LWIP_DEBUGF(ETHARP_DEBUG, ("find_entry: found empty entry %"U16_F"\n", (u16_t)i)); + /* remember first empty entry */ + empty = i; + } + /* pending entry? */ + else if (arp_table[i].state == ETHARP_STATE_PENDING) { + /* if given, does IP address match IP address in ARP entry? */ + if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: found matching pending entry %"U16_F"\n", (u16_t)i)); + /* found exact IP address match, simply bail out */ +#if LWIP_NETIF_HWADDRHINT + NETIF_SET_HINT(netif, i); +#else /* #if LWIP_NETIF_HWADDRHINT */ + etharp_cached_entry = i; +#endif /* #if LWIP_NETIF_HWADDRHINT */ + return i; +#if ARP_QUEUEING + /* pending with queued packets? */ + } else if (arp_table[i].q != NULL) { + if (arp_table[i].ctime >= age_queue) { + old_queue = i; + age_queue = arp_table[i].ctime; + } +#endif + /* pending without queued packets? */ + } else { + if (arp_table[i].ctime >= age_pending) { + old_pending = i; + age_pending = arp_table[i].ctime; + } + } + } + /* stable entry? */ + else if (arp_table[i].state == ETHARP_STATE_STABLE) { + /* if given, does IP address match IP address in ARP entry? */ + if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: found matching stable entry %"U16_F"\n", (u16_t)i)); + /* found exact IP address match, simply bail out */ +#if LWIP_NETIF_HWADDRHINT + NETIF_SET_HINT(netif, i); +#else /* #if LWIP_NETIF_HWADDRHINT */ + etharp_cached_entry = i; +#endif /* #if LWIP_NETIF_HWADDRHINT */ + return i; + /* remember entry with oldest stable entry in oldest, its age in maxtime */ + } else if (arp_table[i].ctime >= age_stable) { + old_stable = i; + age_stable = arp_table[i].ctime; + } + } + } + /* { we have no match } => try to create a new entry */ + + /* no empty entry found and not allowed to recycle? */ + if (((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_TRY_HARD) == 0)) + /* or don't create new entry, only search? */ + || ((flags & ETHARP_FIND_ONLY) != 0)) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: no empty entry found and not allowed to recycle\n")); + return (s8_t)ERR_MEM; + } + + /* b) choose the least destructive entry to recycle: + * 1) empty entry + * 2) oldest stable entry + * 3) oldest pending entry without queued packets + * 4) oldest pending entry with queued packets + * + * { ETHARP_TRY_HARD is set at this point } + */ + + /* 1) empty entry available? */ + if (empty < ARP_TABLE_SIZE) { + i = empty; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting empty entry %"U16_F"\n", (u16_t)i)); + } + /* 2) found recyclable stable entry? */ + else if (old_stable < ARP_TABLE_SIZE) { + /* recycle oldest stable*/ + i = old_stable; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting oldest stable entry %"U16_F"\n", (u16_t)i)); +#if ARP_QUEUEING + /* no queued packets should exist on stable entries */ + LWIP_ASSERT("arp_table[i].q == NULL", arp_table[i].q == NULL); +#endif + /* 3) found recyclable pending entry without queued packets? */ + } else if (old_pending < ARP_TABLE_SIZE) { + /* recycle oldest pending */ + i = old_pending; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F" (without queue)\n", (u16_t)i)); +#if ARP_QUEUEING + /* 4) found recyclable pending entry with queued packets? */ + } else if (old_queue < ARP_TABLE_SIZE) { + /* recycle oldest pending */ + i = old_queue; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F", freeing packet queue %p\n", (u16_t)i, (void *)(arp_table[i].q))); + free_etharp_q(arp_table[i].q); + arp_table[i].q = NULL; +#endif + /* no empty or recyclable entries found */ + } else { + return (s8_t)ERR_MEM; + } + + /* { empty or recyclable entry found } */ + LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE); + + if (arp_table[i].state != ETHARP_STATE_EMPTY) + { + snmp_delete_arpidx_tree(arp_table[i].netif, &arp_table[i].ipaddr); + } + /* recycle entry (no-op for an already empty entry) */ + arp_table[i].state = ETHARP_STATE_EMPTY; + + /* IP address given? */ + if (ipaddr != NULL) { + /* set IP address */ + ip_addr_set(&arp_table[i].ipaddr, ipaddr); + } + arp_table[i].ctime = 0; +#if LWIP_NETIF_HWADDRHINT + NETIF_SET_HINT(netif, i); +#else /* #if LWIP_NETIF_HWADDRHINT */ + etharp_cached_entry = i; +#endif /* #if LWIP_NETIF_HWADDRHINT */ + return (err_t)i; +} + +/** + * Send an IP packet on the network using netif->linkoutput + * The ethernet header is filled in before sending. + * + * @params netif the lwIP network interface on which to send the packet + * @params p the packet to send, p->payload pointing to the (uninitialized) ethernet header + * @params src the source MAC address to be copied into the ethernet header + * @params dst the destination MAC address to be copied into the ethernet header + * @return ERR_OK if the packet was sent, any other err_t on failure + */ +static err_t +etharp_send_ip(struct netif *netif, struct pbuf *p, struct eth_addr *src, struct eth_addr *dst) +{ + struct eth_hdr *ethhdr = p->payload; + u8_t k; + + LWIP_ASSERT("netif->hwaddr_len must be the same as ETHARP_HWADDR_LEN for etharp!", + (netif->hwaddr_len == ETHARP_HWADDR_LEN)); + k = ETHARP_HWADDR_LEN; + while(k > 0) { + k--; + ethhdr->dest.addr[k] = dst->addr[k]; + ethhdr->src.addr[k] = src->addr[k]; + } + ethhdr->type = htons(ETHTYPE_IP); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_send_ip: sending packet %p\n", (void *)p)); + /* send the packet */ + return netif->linkoutput(netif, p); +} + +/** + * Update (or insert) a IP/MAC address pair in the ARP cache. + * + * If a pending entry is resolved, any queued packets will be sent + * at this point. + * + * @param ipaddr IP address of the inserted ARP entry. + * @param ethaddr Ethernet address of the inserted ARP entry. + * @param flags Defines behaviour: + * - ETHARP_TRY_HARD Allows ARP to insert this as a new item. If not specified, + * only existing ARP entries will be updated. + * + * @return + * - ERR_OK Succesfully updated ARP cache. + * - ERR_MEM If we could not add a new ARP entry when ETHARP_TRY_HARD was set. + * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. + * + * @see pbuf_free() + */ +static err_t +update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags) +{ + s8_t i; + u8_t k; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry()\n")); + LWIP_ASSERT("netif->hwaddr_len == ETHARP_HWADDR_LEN", netif->hwaddr_len == ETHARP_HWADDR_LEN); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n", + ip4_addr1(ipaddr), ip4_addr2(ipaddr), ip4_addr3(ipaddr), ip4_addr4(ipaddr), + ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2], + ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5])); + /* non-unicast address? */ + if (ip_addr_isany(ipaddr) || + ip_addr_isbroadcast(ipaddr, netif) || + ip_addr_ismulticast(ipaddr)) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry: will not add non-unicast IP address to ARP cache\n")); + return ERR_ARG; + } + /* find or create ARP entry */ +#if LWIP_NETIF_HWADDRHINT + i = find_entry(ipaddr, flags, netif); +#else /* LWIP_NETIF_HWADDRHINT */ + i = find_entry(ipaddr, flags); +#endif /* LWIP_NETIF_HWADDRHINT */ + /* bail out if no entry could be found */ + if (i < 0) + return (err_t)i; + + /* mark it stable */ + arp_table[i].state = ETHARP_STATE_STABLE; + /* record network interface */ + arp_table[i].netif = netif; + + /* insert in SNMP ARP index tree */ + snmp_insert_arpidx_tree(netif, &arp_table[i].ipaddr); + + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry: updating stable entry %"S16_F"\n", (s16_t)i)); + /* update address */ + k = ETHARP_HWADDR_LEN; + while (k > 0) { + k--; + arp_table[i].ethaddr.addr[k] = ethaddr->addr[k]; + } + /* reset time stamp */ + arp_table[i].ctime = 0; +#if ARP_QUEUEING + /* this is where we will send out queued packets! */ + while (arp_table[i].q != NULL) { + struct pbuf *p; + /* remember remainder of queue */ + struct etharp_q_entry *q = arp_table[i].q; + /* pop first item off the queue */ + arp_table[i].q = q->next; + /* get the packet pointer */ + p = q->p; + /* now queue entry can be freed */ + memp_free(MEMP_ARP_QUEUE, q); + /* send the queued IP packet */ + etharp_send_ip(netif, p, (struct eth_addr*)(netif->hwaddr), ethaddr); + /* free the queued IP packet */ + pbuf_free(p); + } +#endif + return ERR_OK; +} + +/** + * Finds (stable) ethernet/IP address pair from ARP table + * using interface and IP address index. + * @note the addresses in the ARP table are in network order! + * + * @param netif points to interface index + * @param ipaddr points to the (network order) IP address index + * @param eth_ret points to return pointer + * @param ip_ret points to return pointer + * @return table index if found, -1 otherwise + */ +s8_t +etharp_find_addr(struct netif *netif, struct ip_addr *ipaddr, + struct eth_addr **eth_ret, struct ip_addr **ip_ret) +{ + s8_t i; + + LWIP_UNUSED_ARG(netif); + +#if LWIP_NETIF_HWADDRHINT + i = find_entry(ipaddr, ETHARP_FIND_ONLY, NULL); +#else /* LWIP_NETIF_HWADDRHINT */ + i = find_entry(ipaddr, ETHARP_FIND_ONLY); +#endif /* LWIP_NETIF_HWADDRHINT */ + if((i >= 0) && arp_table[i].state == ETHARP_STATE_STABLE) { + *eth_ret = &arp_table[i].ethaddr; + *ip_ret = &arp_table[i].ipaddr; + return i; + } + return -1; +} + +/** + * Updates the ARP table using the given IP packet. + * + * Uses the incoming IP packet's source address to update the + * ARP cache for the local network. The function does not alter + * or free the packet. This function must be called before the + * packet p is passed to the IP layer. + * + * @param netif The lwIP network interface on which the IP packet pbuf arrived. + * @param p The IP packet that arrived on netif. + * + * @return NULL + * + * @see pbuf_free() + */ +void +etharp_ip_input(struct netif *netif, struct pbuf *p) +{ + struct eth_hdr *ethhdr; + struct ip_hdr *iphdr; + LWIP_ERROR("netif != NULL", (netif != NULL), return;); + /* Only insert an entry if the source IP address of the + incoming IP packet comes from a host on the local network. */ + ethhdr = p->payload; + iphdr = (struct ip_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR); +#if ETHARP_SUPPORT_VLAN + if (ethhdr->type == ETHTYPE_VLAN) { + iphdr = (struct ip_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR); + } +#endif /* ETHARP_SUPPORT_VLAN */ + + /* source is not on the local network? */ + if (!ip_addr_netcmp(&(iphdr->src), &(netif->ip_addr), &(netif->netmask))) { + /* do nothing */ + return; + } + + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_ip_input: updating ETHARP table.\n")); + /* update ARP table */ + /* @todo We could use ETHARP_TRY_HARD if we think we are going to talk + * back soon (for example, if the destination IP address is ours. */ + update_arp_entry(netif, &(iphdr->src), &(ethhdr->src), 0); +} + + +/** + * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache + * send out queued IP packets. Updates cache with snooped address pairs. + * + * Should be called for incoming ARP packets. The pbuf in the argument + * is freed by this function. + * + * @param netif The lwIP network interface on which the ARP packet pbuf arrived. + * @param ethaddr Ethernet address of netif. + * @param p The ARP packet that arrived on netif. Is freed by this function. + * + * @return NULL + * + * @see pbuf_free() + */ +void +etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, struct pbuf *p) +{ + struct etharp_hdr *hdr; + struct eth_hdr *ethhdr; + /* these are aligned properly, whereas the ARP header fields might not be */ + struct ip_addr sipaddr, dipaddr; + u8_t i; + u8_t for_us; +#if LWIP_AUTOIP + const u8_t * ethdst_hwaddr; +#endif /* LWIP_AUTOIP */ + + LWIP_ERROR("netif != NULL", (netif != NULL), return;); + + /* drop short ARP packets: we have to check for p->len instead of p->tot_len here + since a struct etharp_hdr is pointed to p->payload, so it musn't be chained! */ + if (p->len < SIZEOF_ETHARP_PACKET) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, + ("etharp_arp_input: packet dropped, too short (%"S16_F"/%"S16_F")\n", p->tot_len, + (s16_t)SIZEOF_ETHARP_PACKET)); + ETHARP_STATS_INC(etharp.lenerr); + ETHARP_STATS_INC(etharp.drop); + pbuf_free(p); + return; + } + + ethhdr = p->payload; + hdr = (struct etharp_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR); +#if ETHARP_SUPPORT_VLAN + if (ethhdr->type == ETHTYPE_VLAN) { + hdr = (struct etharp_hdr *)(((u8_t*)ethhdr) + SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR); + } +#endif /* ETHARP_SUPPORT_VLAN */ + + /* RFC 826 "Packet Reception": */ + if ((hdr->hwtype != htons(HWTYPE_ETHERNET)) || + (hdr->_hwlen_protolen != htons((ETHARP_HWADDR_LEN << 8) | sizeof(struct ip_addr))) || + (hdr->proto != htons(ETHTYPE_IP)) || + (ethhdr->type != htons(ETHTYPE_ARP))) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, + ("etharp_arp_input: packet dropped, wrong hw type, hwlen, proto, protolen or ethernet type (%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F")\n", + hdr->hwtype, ARPH_HWLEN(hdr), hdr->proto, ARPH_PROTOLEN(hdr), ethhdr->type)); + ETHARP_STATS_INC(etharp.proterr); + ETHARP_STATS_INC(etharp.drop); + pbuf_free(p); + return; + } + ETHARP_STATS_INC(etharp.recv); + +#if LWIP_AUTOIP + /* We have to check if a host already has configured our random + * created link local address and continously check if there is + * a host with this IP-address so we can detect collisions */ + autoip_arp_reply(netif, hdr); +#endif /* LWIP_AUTOIP */ + + /* Copy struct ip_addr2 to aligned ip_addr, to support compilers without + * structure packing (not using structure copy which breaks strict-aliasing rules). */ + SMEMCPY(&sipaddr, &hdr->sipaddr, sizeof(sipaddr)); + SMEMCPY(&dipaddr, &hdr->dipaddr, sizeof(dipaddr)); + + /* this interface is not configured? */ + if (netif->ip_addr.addr == 0) { + for_us = 0; + } else { + /* ARP packet directed to us? */ + for_us = ip_addr_cmp(&dipaddr, &(netif->ip_addr)); + } + + /* ARP message directed to us? */ + if (for_us) { + /* add IP address in ARP cache; assume requester wants to talk to us. + * can result in directly sending the queued packets for this host. */ + update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), ETHARP_TRY_HARD); + /* ARP message not directed to us? */ + } else { + /* update the source IP address in the cache, if present */ + update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), 0); + } + + /* now act on the message itself */ + switch (htons(hdr->opcode)) { + /* ARP request? */ + case ARP_REQUEST: + /* ARP request. If it asked for our address, we send out a + * reply. In any case, we time-stamp any existing ARP entry, + * and possiby send out an IP packet that was queued on it. */ + + LWIP_DEBUGF (ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: incoming ARP request\n")); + /* ARP request for our address? */ + if (for_us) { + + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: replying to ARP request for our IP address\n")); + /* Re-use pbuf to send ARP reply. + Since we are re-using an existing pbuf, we can't call etharp_raw since + that would allocate a new pbuf. */ + hdr->opcode = htons(ARP_REPLY); + + hdr->dipaddr = hdr->sipaddr; + SMEMCPY(&hdr->sipaddr, &netif->ip_addr, sizeof(hdr->sipaddr)); + + LWIP_ASSERT("netif->hwaddr_len must be the same as ETHARP_HWADDR_LEN for etharp!", + (netif->hwaddr_len == ETHARP_HWADDR_LEN)); + i = ETHARP_HWADDR_LEN; +#if LWIP_AUTOIP + /* If we are using Link-Local, ARP packets must be broadcast on the + * link layer. (See RFC3927 Section 2.5) */ + ethdst_hwaddr = ((netif->autoip != NULL) && (netif->autoip->state != AUTOIP_STATE_OFF)) ? (u8_t*)(ethbroadcast.addr) : hdr->shwaddr.addr; +#endif /* LWIP_AUTOIP */ + + while(i > 0) { + i--; + hdr->dhwaddr.addr[i] = hdr->shwaddr.addr[i]; +#if LWIP_AUTOIP + ethhdr->dest.addr[i] = ethdst_hwaddr[i]; +#else /* LWIP_AUTOIP */ + ethhdr->dest.addr[i] = hdr->shwaddr.addr[i]; +#endif /* LWIP_AUTOIP */ + hdr->shwaddr.addr[i] = ethaddr->addr[i]; + ethhdr->src.addr[i] = ethaddr->addr[i]; + } + + /* hwtype, hwaddr_len, proto, protolen and the type in the ethernet header + are already correct, we tested that before */ + + /* return ARP reply */ + netif->linkoutput(netif, p); + /* we are not configured? */ + } else if (netif->ip_addr.addr == 0) { + /* { for_us == 0 and netif->ip_addr.addr == 0 } */ + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: we are unconfigured, ARP request ignored.\n")); + /* request was not directed to us */ + } else { + /* { for_us == 0 and netif->ip_addr.addr != 0 } */ + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: ARP request was not for us.\n")); + } + break; + case ARP_REPLY: + /* ARP reply. We already updated the ARP cache earlier. */ + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: incoming ARP reply\n")); +#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK) + /* DHCP wants to know about ARP replies from any host with an + * IP address also offered to us by the DHCP server. We do not + * want to take a duplicate IP address on a single network. + * @todo How should we handle redundant (fail-over) interfaces? */ + dhcp_arp_reply(netif, &sipaddr); +#endif + break; + default: + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: ARP unknown opcode type %"S16_F"\n", htons(hdr->opcode))); + ETHARP_STATS_INC(etharp.err); + break; + } + /* free ARP packet */ + pbuf_free(p); +} + +/** + * Resolve and fill-in Ethernet address header for outgoing IP packet. + * + * For IP multicast and broadcast, corresponding Ethernet addresses + * are selected and the packet is transmitted on the link. + * + * For unicast addresses, the packet is submitted to etharp_query(). In + * case the IP address is outside the local network, the IP address of + * the gateway is used. + * + * @param netif The lwIP network interface which the IP packet will be sent on. + * @param q The pbuf(s) containing the IP packet to be sent. + * @param ipaddr The IP address of the packet destination. + * + * @return + * - ERR_RTE No route to destination (no gateway to external networks), + * or the return type of either etharp_query() or etharp_send_ip(). + */ +err_t +etharp_output(struct netif *netif, struct pbuf *q, struct ip_addr *ipaddr) +{ + struct eth_addr *dest, mcastaddr; + + /* make room for Ethernet header - should not fail */ + if (pbuf_header(q, sizeof(struct eth_hdr)) != 0) { + /* bail out */ + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("etharp_output: could not allocate room for header.\n")); + LINK_STATS_INC(link.lenerr); + return ERR_BUF; + } + + /* assume unresolved Ethernet address */ + dest = NULL; + /* Determine on destination hardware address. Broadcasts and multicasts + * are special, other IP addresses are looked up in the ARP table. */ + + /* broadcast destination IP address? */ + if (ip_addr_isbroadcast(ipaddr, netif)) { + /* broadcast on Ethernet also */ + dest = (struct eth_addr *)ðbroadcast; + /* multicast destination IP address? */ + } else if (ip_addr_ismulticast(ipaddr)) { + /* Hash IP multicast address to MAC address.*/ + mcastaddr.addr[0] = 0x01; + mcastaddr.addr[1] = 0x00; + mcastaddr.addr[2] = 0x5e; + mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f; + mcastaddr.addr[4] = ip4_addr3(ipaddr); + mcastaddr.addr[5] = ip4_addr4(ipaddr); + /* destination Ethernet address is multicast */ + dest = &mcastaddr; + /* unicast destination IP address? */ + } else { + /* outside local network? */ + if (!ip_addr_netcmp(ipaddr, &(netif->ip_addr), &(netif->netmask))) { + /* interface has default gateway? */ + if (netif->gw.addr != 0) { + /* send to hardware address of default gateway IP address */ + ipaddr = &(netif->gw); + /* no default gateway available */ + } else { + /* no route to destination error (default gateway missing) */ + return ERR_RTE; + } + } + /* queue on destination Ethernet address belonging to ipaddr */ + return etharp_query(netif, ipaddr, q); + } + + /* continuation for multicast/broadcast destinations */ + /* obtain source Ethernet address of the given interface */ + /* send packet directly on the link */ + return etharp_send_ip(netif, q, (struct eth_addr*)(netif->hwaddr), dest); +} + +/** + * Send an ARP request for the given IP address and/or queue a packet. + * + * If the IP address was not yet in the cache, a pending ARP cache entry + * is added and an ARP request is sent for the given address. The packet + * is queued on this entry. + * + * If the IP address was already pending in the cache, a new ARP request + * is sent for the given address. The packet is queued on this entry. + * + * If the IP address was already stable in the cache, and a packet is + * given, it is directly sent and no ARP request is sent out. + * + * If the IP address was already stable in the cache, and no packet is + * given, an ARP request is sent out. + * + * @param netif The lwIP network interface on which ipaddr + * must be queried for. + * @param ipaddr The IP address to be resolved. + * @param q If non-NULL, a pbuf that must be delivered to the IP address. + * q is not freed by this function. + * + * @note q must only be ONE packet, not a packet queue! + * + * @return + * - ERR_BUF Could not make room for Ethernet header. + * - ERR_MEM Hardware address unknown, and no more ARP entries available + * to query for address or queue the packet. + * - ERR_MEM Could not queue packet due to memory shortage. + * - ERR_RTE No route to destination (no gateway to external networks). + * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. + * + */ +err_t +etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q) +{ + struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr; + err_t result = ERR_MEM; + s8_t i; /* ARP entry index */ + + /* non-unicast address? */ + if (ip_addr_isbroadcast(ipaddr, netif) || + ip_addr_ismulticast(ipaddr) || + ip_addr_isany(ipaddr)) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n")); + return ERR_ARG; + } + + /* find entry in ARP cache, ask to create entry if queueing packet */ +#if LWIP_NETIF_HWADDRHINT + i = find_entry(ipaddr, ETHARP_TRY_HARD, netif); +#else /* LWIP_NETIF_HWADDRHINT */ + i = find_entry(ipaddr, ETHARP_TRY_HARD); +#endif /* LWIP_NETIF_HWADDRHINT */ + + /* could not find or create entry? */ + if (i < 0) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not create ARP entry\n")); + if (q) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: packet dropped\n")); + ETHARP_STATS_INC(etharp.memerr); + } + return (err_t)i; + } + + /* mark a fresh entry as pending (we just sent a request) */ + if (arp_table[i].state == ETHARP_STATE_EMPTY) { + arp_table[i].state = ETHARP_STATE_PENDING; + } + + /* { i is either a STABLE or (new or existing) PENDING entry } */ + LWIP_ASSERT("arp_table[i].state == PENDING or STABLE", + ((arp_table[i].state == ETHARP_STATE_PENDING) || + (arp_table[i].state == ETHARP_STATE_STABLE))); + + /* do we have a pending entry? or an implicit query request? */ + if ((arp_table[i].state == ETHARP_STATE_PENDING) || (q == NULL)) { + /* try to resolve it; send out ARP request */ + result = etharp_request(netif, ipaddr); + if (result != ERR_OK) { + /* ARP request couldn't be sent */ + /* We don't re-send arp request in etharp_tmr, but we still queue packets, + since this failure could be temporary, and the next packet calling + etharp_query again could lead to sending the queued packets. */ + } + } + + /* packet given? */ + if (q != NULL) { + /* stable entry? */ + if (arp_table[i].state == ETHARP_STATE_STABLE) { + /* we have a valid IP->Ethernet address mapping */ + /* send the packet */ + result = etharp_send_ip(netif, q, srcaddr, &(arp_table[i].ethaddr)); + /* pending entry? (either just created or already pending */ + } else if (arp_table[i].state == ETHARP_STATE_PENDING) { +#if ARP_QUEUEING /* queue the given q packet */ + struct pbuf *p; + int copy_needed = 0; + /* IF q includes a PBUF_REF, PBUF_POOL or PBUF_RAM, we have no choice but + * to copy the whole queue into a new PBUF_RAM (see bug #11400) + * PBUF_ROMs can be left as they are, since ROM must not get changed. */ + p = q; + while (p) { + LWIP_ASSERT("no packet queues allowed!", (p->len != p->tot_len) || (p->next == 0)); + if(p->type != PBUF_ROM) { + copy_needed = 1; + break; + } + p = p->next; + } + if(copy_needed) { + /* copy the whole packet into new pbufs */ + p = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); + if(p != NULL) { + if (pbuf_copy(p, q) != ERR_OK) { + pbuf_free(p); + p = NULL; + } + } + } else { + /* referencing the old pbuf is enough */ + p = q; + pbuf_ref(p); + } + /* packet could be taken over? */ + if (p != NULL) { + /* queue packet ... */ + struct etharp_q_entry *new_entry; + /* allocate a new arp queue entry */ + new_entry = memp_malloc(MEMP_ARP_QUEUE); + if (new_entry != NULL) { + new_entry->next = 0; + new_entry->p = p; + if(arp_table[i].q != NULL) { + /* queue was already existent, append the new entry to the end */ + struct etharp_q_entry *r; + r = arp_table[i].q; + while (r->next != NULL) { + r = r->next; + } + r->next = new_entry; + } else { + /* queue did not exist, first item in queue */ + arp_table[i].q = new_entry; + } + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"S16_F"\n", (void *)q, (s16_t)i)); + result = ERR_OK; + } else { + /* the pool MEMP_ARP_QUEUE is empty */ + pbuf_free(p); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); + /* { result == ERR_MEM } through initialization */ + } + } else { + ETHARP_STATS_INC(etharp.memerr); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); + /* { result == ERR_MEM } through initialization */ + } +#else /* ARP_QUEUEING == 0 */ + /* q && state == PENDING && ARP_QUEUEING == 0 => result = ERR_MEM */ + /* { result == ERR_MEM } through initialization */ + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: Ethernet destination address unknown, queueing disabled, packet %p dropped\n", (void *)q)); +#endif + } + } + return result; +} + +/** + * Send a raw ARP packet (opcode and all addresses can be modified) + * + * @param netif the lwip network interface on which to send the ARP packet + * @param ethsrc_addr the source MAC address for the ethernet header + * @param ethdst_addr the destination MAC address for the ethernet header + * @param hwsrc_addr the source MAC address for the ARP protocol header + * @param ipsrc_addr the source IP address for the ARP protocol header + * @param hwdst_addr the destination MAC address for the ARP protocol header + * @param ipdst_addr the destination IP address for the ARP protocol header + * @param opcode the type of the ARP packet + * @return ERR_OK if the ARP packet has been sent + * ERR_MEM if the ARP packet couldn't be allocated + * any other err_t on failure + */ +#if !LWIP_AUTOIP +static +#endif /* LWIP_AUTOIP */ +err_t +etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr, + const struct eth_addr *ethdst_addr, + const struct eth_addr *hwsrc_addr, const struct ip_addr *ipsrc_addr, + const struct eth_addr *hwdst_addr, const struct ip_addr *ipdst_addr, + const u16_t opcode) +{ + struct pbuf *p; + err_t result = ERR_OK; + u8_t k; /* ARP entry index */ + struct eth_hdr *ethhdr; + struct etharp_hdr *hdr; +#if LWIP_AUTOIP + const u8_t * ethdst_hwaddr; +#endif /* LWIP_AUTOIP */ + + /* allocate a pbuf for the outgoing ARP request packet */ + p = pbuf_alloc(PBUF_RAW, SIZEOF_ETHARP_PACKET, PBUF_RAM); + /* could allocate a pbuf for an ARP request? */ + if (p == NULL) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("etharp_raw: could not allocate pbuf for ARP request.\n")); + ETHARP_STATS_INC(etharp.memerr); + return ERR_MEM; + } + LWIP_ASSERT("check that first pbuf can hold struct etharp_hdr", + (p->len >= SIZEOF_ETHARP_PACKET)); + + ethhdr = p->payload; + hdr = (struct etharp_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_raw: sending raw ARP packet.\n")); + hdr->opcode = htons(opcode); + + LWIP_ASSERT("netif->hwaddr_len must be the same as ETHARP_HWADDR_LEN for etharp!", + (netif->hwaddr_len == ETHARP_HWADDR_LEN)); + k = ETHARP_HWADDR_LEN; +#if LWIP_AUTOIP + /* If we are using Link-Local, ARP packets must be broadcast on the + * link layer. (See RFC3927 Section 2.5) */ + ethdst_hwaddr = ((netif->autoip != NULL) && (netif->autoip->state != AUTOIP_STATE_OFF)) ? (u8_t*)(ethbroadcast.addr) : ethdst_addr->addr; +#endif /* LWIP_AUTOIP */ + /* Write MAC-Addresses (combined loop for both headers) */ + while(k > 0) { + k--; + /* Write the ARP MAC-Addresses */ + hdr->shwaddr.addr[k] = hwsrc_addr->addr[k]; + hdr->dhwaddr.addr[k] = hwdst_addr->addr[k]; + /* Write the Ethernet MAC-Addresses */ +#if LWIP_AUTOIP + ethhdr->dest.addr[k] = ethdst_hwaddr[k]; +#else /* LWIP_AUTOIP */ + ethhdr->dest.addr[k] = ethdst_addr->addr[k]; +#endif /* LWIP_AUTOIP */ + ethhdr->src.addr[k] = ethsrc_addr->addr[k]; + } + hdr->sipaddr = *(struct ip_addr2 *)ipsrc_addr; + hdr->dipaddr = *(struct ip_addr2 *)ipdst_addr; + + hdr->hwtype = htons(HWTYPE_ETHERNET); + hdr->proto = htons(ETHTYPE_IP); + /* set hwlen and protolen together */ + hdr->_hwlen_protolen = htons((ETHARP_HWADDR_LEN << 8) | sizeof(struct ip_addr)); + + ethhdr->type = htons(ETHTYPE_ARP); + /* send ARP query */ + result = netif->linkoutput(netif, p); + ETHARP_STATS_INC(etharp.xmit); + /* free ARP query packet */ + pbuf_free(p); + p = NULL; + /* could not allocate pbuf for ARP request */ + + return result; +} + +/** + * Send an ARP request packet asking for ipaddr. + * + * @param netif the lwip network interface on which to send the request + * @param ipaddr the IP address for which to ask + * @return ERR_OK if the request has been sent + * ERR_MEM if the ARP packet couldn't be allocated + * any other err_t on failure + */ +err_t +etharp_request(struct netif *netif, struct ip_addr *ipaddr) +{ + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_request: sending ARP request.\n")); + return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, ðbroadcast, + (struct eth_addr *)netif->hwaddr, &netif->ip_addr, ðzero, + ipaddr, ARP_REQUEST); +} + +/** + * Process received ethernet frames. Using this function instead of directly + * calling ip_input and passing ARP frames through etharp in ethernetif_input, + * the ARP cache is protected from concurrent access. + * + * @param p the recevied packet, p->payload pointing to the ethernet header + * @param netif the network interface on which the packet was received + */ +err_t +ethernet_input(struct pbuf *p, struct netif *netif) +{ + struct eth_hdr* ethhdr; + u16_t type; + + /* points to packet payload, which starts with an Ethernet header */ + ethhdr = p->payload; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, + ("ethernet_input: dest:%02x:%02x:%02x:%02x:%02x:%02x, src:%02x:%02x:%02x:%02x:%02x:%02x, type:%2hx\n", + (unsigned)ethhdr->dest.addr[0], (unsigned)ethhdr->dest.addr[1], (unsigned)ethhdr->dest.addr[2], + (unsigned)ethhdr->dest.addr[3], (unsigned)ethhdr->dest.addr[4], (unsigned)ethhdr->dest.addr[5], + (unsigned)ethhdr->src.addr[0], (unsigned)ethhdr->src.addr[1], (unsigned)ethhdr->src.addr[2], + (unsigned)ethhdr->src.addr[3], (unsigned)ethhdr->src.addr[4], (unsigned)ethhdr->src.addr[5], + (unsigned)htons(ethhdr->type))); + + type = htons(ethhdr->type); +#if ETHARP_SUPPORT_VLAN + if (type == ETHTYPE_VLAN) { + struct eth_vlan_hdr *vlan = (struct eth_vlan_hdr*)(((char*)ethhdr) + SIZEOF_ETH_HDR); +#ifdef ETHARP_VLAN_CHECK /* if not, allow all VLANs */ + if (VLAN_ID(vlan) != ETHARP_VLAN_CHECK) { + /* silently ignore this packet: not for our VLAN */ + pbuf_free(p); + return ERR_OK; + } +#endif /* ETHARP_VLAN_CHECK */ + type = htons(vlan->tpid); + } +#endif /* ETHARP_SUPPORT_VLAN */ + + switch (type) { + /* IP packet? */ + case ETHTYPE_IP: +#if ETHARP_TRUST_IP_MAC + /* update ARP table */ + etharp_ip_input(netif, p); +#endif /* ETHARP_TRUST_IP_MAC */ + /* skip Ethernet header */ + if(pbuf_header(p, -(s16_t)SIZEOF_ETH_HDR)) { + LWIP_ASSERT("Can't move over header in packet", 0); + pbuf_free(p); + p = NULL; + } else { + /* pass to IP layer */ + ip_input(p, netif); + } + break; + + case ETHTYPE_ARP: + /* pass p to ARP module */ + etharp_arp_input(netif, (struct eth_addr*)(netif->hwaddr), p); + break; + +#if PPPOE_SUPPORT + case ETHTYPE_PPPOEDISC: /* PPP Over Ethernet Discovery Stage */ + pppoe_disc_input(netif, p); + break; + + case ETHTYPE_PPPOE: /* PPP Over Ethernet Session Stage */ + pppoe_data_input(netif, p); + break; +#endif /* PPPOE_SUPPORT */ + + default: + ETHARP_STATS_INC(etharp.proterr); + ETHARP_STATS_INC(etharp.drop); + pbuf_free(p); + p = NULL; + break; + } + + /* This means the pbuf is freed or consumed, + so the caller doesn't have to free it again */ + return ERR_OK; +} +#endif /* LWIP_ARP */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/netif/loopif.c b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/netif/loopif.c new file mode 100644 index 0000000000000000000000000000000000000000..b7d663294956b7431ef8ec04e30d4903b02eef34 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/netif/loopif.c @@ -0,0 +1,68 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/** + * @file + * Loop Interface + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#include "lwip/opt.h" + +#if LWIP_HAVE_LOOPIF + +#include "netif/loopif.h" +#include "lwip/snmp.h" + +/** + * Initialize a lwip network interface structure for a loopback interface + * + * @param netif the lwip network interface structure for this loopif + * @return ERR_OK if the loopif is initialized + * ERR_MEM if private data couldn't be allocated + */ +err_t +loopif_init(struct netif *netif) +{ + /* initialize the snmp variables and counters inside the struct netif + * ifSpeed: no assumption can be made! + */ + NETIF_INIT_SNMP(netif, snmp_ifType_softwareLoopback, 0); + + netif->name[0] = 'l'; + netif->name[1] = 'o'; + netif->output = netif_loop_output; + return ERR_OK; +} + +#endif /* LWIP_HAVE_LOOPIF */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/if/include/arch/cc.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/if/include/arch/cc.h new file mode 100644 index 0000000000000000000000000000000000000000..fc9c07df3f6afe50cbabe2c81586d7338a00c37f --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/if/include/arch/cc.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __ARCH_CC_H__ +#define __ARCH_CC_H__ + +/* Define platform endianness */ +#ifndef BYTE_ORDER +#define BYTE_ORDER BIG_ENDIAN +#endif /* BYTE_ORDER */ + +/* Define generic types used in lwIP */ +typedef unsigned char u8_t; +typedef signed char s8_t; +typedef unsigned short u16_t; +typedef signed short s16_t; +typedef unsigned long u32_t; +typedef signed long s32_t; + +typedef u32_t mem_ptr_t; + +/* Define (sn)printf formatters for these lwIP types */ +#define U16_F "u" +#define S16_F "d" +#define X16_F "x" +#define U32_F "u" +#define S32_F "d" +#define X32_F "x" + +/* Compiler hints for packing structures */ +#define PACK_STRUCT_FIELD(x) x +#define PACK_STRUCT_STRUCT __attribute__((packed)) +#define PACK_STRUCT_BEGIN +#define PACK_STRUCT_END + +/* Plaform specific diagnostic output */ +#ifdef CONFIG_OWL +# include +# define LWIP_PLATFORM_DIAG(x) owl_printf x +# define LWIP_PLATFORM_ASSERT(x) owl_assert(x) +#else +# include +# define LWIP_PLATFORM_DIAG(x) do { printk x; } while(0) +# define LWIP_PLATFORM_ASSERT(x) do { \ + printk("Assertion \"%s\" failed at line " \ + "%d in %s\n", \ + x, __LINE__, __FILE__); while(1); \ + } while(0) +#endif + +#endif /* __ARCH_CC_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/if/include/arch/perf.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/if/include/arch/perf.h new file mode 100644 index 0000000000000000000000000000000000000000..49917871ed2a354455d77811d50743f6ce809390 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/if/include/arch/perf.h @@ -0,0 +1,7 @@ +#ifndef __PERF_H__ +#define __PERF_H__ + +#define PERF_START /* null definition */ +#define PERF_STOP(x) /* null definition */ + +#endif diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/if/include/lwipopts.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/if/include/lwipopts.h new file mode 100644 index 0000000000000000000000000000000000000000..ae4df230f54affef3b5587c6257411b70e2128e6 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/if/include/lwipopts.h @@ -0,0 +1,426 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/** + * @file + * + * lwIP Options Configuration + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIPOPTS_H__ +#define __LWIPOPTS_H__ + +#include "wl_api.h" + +/* + ----------------------------------------------- + ---------- Platform specific locking ---------- + ----------------------------------------------- +*/ + +/** + * NO_SYS==1: Provides VERY minimal functionality. Otherwise, + * use lwIP facilities. + */ +#define NO_SYS 1 + + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> #define MEM_ALIGNMENT 4 + * 2 byte alignment -> #define MEM_ALIGNMENT 2 + */ +#define MEM_ALIGNMENT 4 + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#define MEM_SIZE 16000 + + +/* + ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ +*/ +/** + * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). + * If the application sends a lot of data out of ROM (or other static memory), + * this should be set high. + */ +#define MEMP_NUM_PBUF 30 + +/** + * MEMP_NUM_RAW_PCB: Number of raw connection PCBs + * (requires the LWIP_RAW option) + */ +#define MEMP_NUM_RAW_PCB 4 + +/** + * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + * per active UDP "connection". + * (requires the LWIP_UDP option) + */ +#define MEMP_NUM_UDP_PCB 4 + +/** + * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. + * (requires the LWIP_TCP option) + */ +#define MEMP_NUM_TCP_PCB 2 + +/** + * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. + * (requires the LWIP_TCP option) + */ +#define MEMP_NUM_TCP_PCB_LISTEN 2 + +/** + * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. + * (requires the LWIP_TCP option) + */ +#define MEMP_NUM_TCP_SEG 32 + +/** + * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing + * packets (pbufs) that are waiting for an ARP request (to resolve + * their destination address) to finish. + * (requires the ARP_QUEUEING option) + */ +#define MEMP_NUM_ARP_QUEUE 2 + +/** + * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. + * (requires NO_SYS==0) + */ +#define MEMP_NUM_SYS_TIMEOUT 0 + +/** + * MEMP_NUM_NETBUF: the number of struct netbufs. + * (only needed if you use the sequential API, like api_lib.c) + */ +#define MEMP_NUM_NETBUF 0 + +/** + * MEMP_NUM_NETCONN: the number of struct netconns. + * (only needed if you use the sequential API, like api_lib.c) + */ +#define MEMP_NUM_NETCONN 0 + +/** + * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used + * for callback/timeout API communication. + * (only needed if you use tcpip.c) + */ +#define MEMP_NUM_TCPIP_MSG_API 0 + +/** + * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used + * for incoming packets. + * (only needed if you use tcpip.c) + */ +#define MEMP_NUM_TCPIP_MSG_INPKT 0 + +/** + * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + */ +#define PBUF_POOL_SIZE 32 + +/* + --------------------------------- + ---------- ARP options ---------- + --------------------------------- +*/ +/** + * LWIP_ARP==1: Enable ARP functionality. + */ +#define LWIP_ARP 1 + +/* + -------------------------------- + ---------- IP options ---------- + -------------------------------- +*/ +/** + * IP_FORWARD==1: Enables the ability to forward IP packets across network + * interfaces. If you are going to run lwIP on a device with only one network + * interface, define this to 0. + */ +#define IP_FORWARD 0 + +/** + * IP_OPTIONS: Defines the behavior for IP options. + * IP_OPTIONS==0_ALLOWED: All packets with IP options are dropped. + * IP_OPTIONS==1_ALLOWED: IP options are allowed (but not parsed). + */ +#define IP_OPTIONS_ALLOWED 1 + +/** + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via IP_FRAG. + */ +#define IP_REASSEMBLY 1 + +/** + * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#define IP_FRAG 1 + +/** + * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) + * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived + * in this time, the whole packet is discarded. + */ +#define IP_REASS_MAXAGE 3 + +/** + * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. + * Since the received pbufs are enqueued, be sure to configure + * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive + * packets even if the maximum amount of fragments is enqueued for reassembly! + */ +#define IP_REASS_MAX_PBUFS 10 + +/** + * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP + * fragmentation. Otherwise pbufs are allocated and reference the original + * packet data to be fragmented. + */ +#define IP_FRAG_USES_STATIC_BUF 0 + +/** + * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. + */ +#define IP_DEFAULT_TTL 255 + +/* + ---------------------------------- + ---------- ICMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_ICMP==1: Enable ICMP module inside the IP stack. + * Be careful, disable that make your product non-compliant to RFC1122 + */ +#define LWIP_ICMP 1 + +/** + * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. + */ +#define ICMP_TTL (IP_DEFAULT_TTL) + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#define LWIP_RAW 1 + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#define LWIP_DHCP 1 + +/* + ------------------------------------ + ---------- AUTOIP options ---------- + ------------------------------------ +*/ +/** + * LWIP_AUTOIP==1: Enable AUTOIP module. + */ +#define LWIP_AUTOIP 0 + +/* + ---------------------------------- + ---------- SNMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP + * transport. + */ +#define LWIP_SNMP 0 +#define SNMP_PRIVATE_MIB 0 + +/* + ---------------------------------- + ---------- IGMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_IGMP==1: Turn on IGMP module. + */ +#define LWIP_IGMP 1 + +/* + ---------------------------------- + ---------- DNS options ----------- + ---------------------------------- +*/ +/** + * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS + * transport. + */ +#define LWIP_DNS 1 + +/* + --------------------------------- + ---------- UDP options ---------- + --------------------------------- +*/ +/** + * LWIP_UDP==1: Turn on UDP. + */ +#define LWIP_UDP 1 + +/** + * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) + */ +#define LWIP_UDPLITE 0 + +/** + * UDP_TTL: Default Time-To-Live value. + */ +#define UDP_TTL (IP_DEFAULT_TTL) + +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ +/** + * LWIP_TCP==1: Turn on TCP. + */ +#define LWIP_TCP 1 + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ +/** + * PBUF_LINK_HLEN: the number of bytes that should be allocated for a + * link level header. The default is 14, the standard value for + * Ethernet. + */ +#define PBUF_LINK_HLEN (14 + ETH_PAD_SIZE) + +/* + ------------------------------------ + ---------- LOOPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c + */ +#define LWIP_HAVE_LOOPIF 1 +#define LWIP_LOOPIF_MULTITHREADING 0 + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ + +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#define LWIP_NETCONN 0 + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#define LWIP_SOCKET 0 + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#define LWIP_STATS 1 +#define LINK_STATS 1 + +/* Misc */ +#define LWIP_NETIF_LINK_CALLBACK 1 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_TIMEVAL_PRIVATE 0 + +#undef DHCP_DOES_ARP_CHECK + +#if 0 +#define LWIP_DEBUG 1 +//#define NETIF_DEBUG LWIP_DBG_ON +#define DHCP_DEBUG LWIP_DBG_ON +//#define ICMP_DEBUG LWIP_DBG_ON +//#define TCP_DEBUG LWIP_DBG_ON +//#define TCP_RTO_DEBUG LWIP_DBG_ON +//#define IP_DEBUG LWIP_DBG_ON +//#define TCP_CWND_DEBUG LWIP_DBG_ON +//#define ETHARP_DEBUG LWIP_DBG_ON +//#define PBUF_DEBUG LWIP_DBG_ON +#define TCP_INPUT_DEBUG LWIP_DBG_ON +#define TCP_OUTPUT_DEBUG LWIP_DBG_ON +#endif + +#define ETH_PAD_SIZE WL_HEADER_SIZE /* size of wifiengine header */ +#define MEM_LIBC_MALLOC 1 + +#define TCP_MSS 512 +#define TCP_SND_BUF 4096 +#endif /* __LWIPOPTS_H__ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/if/include/netif/wlif.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/if/include/netif/wlif.h new file mode 100644 index 0000000000000000000000000000000000000000..6354e1c91ba9a04b0b8794fe2ef44a97c1397d47 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/if/include/netif/wlif.h @@ -0,0 +1,10 @@ +#ifndef __NETIF_NRWLANIF_H__ +#define __NETIF_NRWLANIF_H__ + +#include "lwip/netif.h" +#include "lwip/err.h" + +err_t wlif_init(struct netif *netif); +void wlif_poll(struct netif *netif); + +#endif diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/if/netif/wlif.c b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/if/netif/wlif.c new file mode 100644 index 0000000000000000000000000000000000000000..55d5b6abd8380fe8115359cbad03c0ec057e8927 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/if/netif/wlif.c @@ -0,0 +1,386 @@ +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/stats.h" +#include "lwip/sys.h" +#include "netif/etharp.h" +#include "netif/wlif.h" +#include +#include + +#define IFNAME0 'w' +#define IFNAME1 'l' + +/* the queue size will affect the tx performance when using power save. + * A small queue will quickly become filled up if we have to wake the device + * before the actual transmission can occur. When the queue is filled up, the + * packets will be discarded and retransmission will be handled by the upper + * layers. In case of TCP, the retransmission time might be quite long. + * + * If the packets can be put in the pqueue instead, all the packets + * (if possible) will be transmitted when the device wakes up, so we don't have + * to wait for retransmission from upper layers. + */ +#define PQUEUE_SIZE 8 + +struct wlif_t { + volatile uint8_t rx_pending; + + struct { + struct pbuf* buf[PQUEUE_SIZE]; + uint8_t first; + uint8_t last; + } pqueue; +}; + +#define PQUEUE_EMPTY(q) (q.last == q.first) +#define PQUEUE_FULL(q) ((q.last + 1) % PQUEUE_SIZE == q.first) +#define PQUEUE_FIRST(q) (q.buf[q.first]) +#define PQUEUE_DEQUEUE(q) \ + ({ \ + struct pbuf* __p = PQUEUE_FIRST(q); \ + q.first = (q.first + 1) % PQUEUE_SIZE; \ + __p; \ + }) +#define PQUEUE_ENQUEUE(q, p) \ + ({ \ + q.buf[q.last] = p; \ + q.last = (q.last + 1) % PQUEUE_SIZE; \ + }) + + +static err_t process_pqueue(struct netif* netif) +{ + struct pbuf *p; + struct pbuf *q; + int status; + struct wlif_t *priv = (struct wlif_t*) netif->state; + + /* queue empty? finished */ + if (PQUEUE_EMPTY(priv->pqueue)) + return ERR_OK; + + /* get first packet in queue */ + p = PQUEUE_FIRST(priv->pqueue); + + status = wl_process_tx( + p->payload + WL_HEADER_SIZE, /* ptr to eth hdr */ + p->len - WL_HEADER_SIZE, /* input buffer len */ + p->tot_len - WL_HEADER_SIZE, /* pkt len */ + p->payload, /* ptr to WE hdr */ + 0, /* prio */ + p); /* pkt handle */ + + /* if we fail due to power save mode, leave packet in queue and + * try again when target is awake again (upon WL_RX_EVENT_WAKEUP). + */ + if (status == WL_RESOURCES) + return ERR_IF; + + /* if we fail for another reason, just discard the packet */ + if (status != WL_SUCCESS) { + PQUEUE_DEQUEUE(priv->pqueue); + pbuf_free(p); + return ERR_IF; + } + + /* Send the data from the pbuf to the interface, one pbuf at a + * time. The size of the data in each pbuf is kept in the ->len + * variable. + */ + for (q = p; q != NULL; q = q->next) + wl_tx(q->payload, q->len); + + /* remove packet from queue and dec refcnt */ + PQUEUE_DEQUEUE(priv->pqueue); + pbuf_free(p); + + LINK_STATS_INC(link.xmit); + + /* tell caller to process next packet */ + return ERR_INPROGRESS; +} + + +/** + * Called in interrupt context when we can read more data from the mac. + * + */ +static void +rx_isr(void* ctx) +{ + struct netif *netif = ctx; + struct wlif_t *priv = (struct wlif_t*) netif->state; + priv->rx_pending = 1; +} + + +/** + * In this function, the hardware should be initialized. + * Called from wlif_init(). + * + * @param netif the already initialized lwip network interface structure + * for this ethernetif + */ +static err_t +low_level_init(struct netif *netif) +{ + /* device capabilities */ + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | + NETIF_FLAG_IGMP; + + /* NETIF_FLAG_LINK_UP must be set only when we have an wlan assoc */ + + /* set MAC hardware address length */ + netif->hwaddr_len = ETHARP_HWADDR_LEN; + + if (wl_get_mac_addr(netif->hwaddr) != WL_SUCCESS) + return ERR_IF; + + /* maximum transfer unit */ + netif->mtu = 1500; + + return ERR_OK; +} + + +/** + * This function should do the actual transmission of the packet. The packet is + * contained in the pbuf that is passed to the function. This pbuf + * might be chained. + * + * @param netif the lwip network interface structure for this ethernetif + * @param p the MAC packet to send (e.g. IP packet including MAC addresses and + * type) + * @return ERR_OK if the packet could be sent + * an err_t value if the packet couldn't be sent + * + * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to + * strange results. You might consider waiting for space in the DMA queue + * to become availale since the stack doesn't retry to send a packet + * dropped because of memory failure (except for the TCP timers). + */ +static err_t +low_level_output(struct netif *netif, struct pbuf *p) +{ + struct wlif_t* priv = (struct wlif_t*) netif->state; + + /* must have a linear buffer containing up to and including + * the ethernet header + */ + if (p->len < sizeof(struct eth_hdr)) + return ERR_IF; + + /* queue full? drop packet */ + if (PQUEUE_FULL(priv->pqueue)) + return ERR_INPROGRESS; /* no one seems to check this anyway */ + + /* queue packet */ + PQUEUE_ENQUEUE(priv->pqueue, p); + pbuf_ref(p); + while (process_pqueue(netif) == ERR_INPROGRESS); + return ERR_OK; /* no one seems to check this anyway */ +} + +/** + * Should allocate a pbuf and transfer the bytes of the incoming + * packet from the interface into the pbuf. + * + * @param netif the lwip network interface structure for this ethernetif + * @return a pbuf filled with the received packet (including MAC header) + * NULL on memory error + */ +static struct pbuf * +low_level_input(struct netif *netif) +{ + struct pbuf *p; + struct wlif_t *priv = (struct wlif_t*) netif->state; + + char *stripped_pkt; + size_t stripped_pkt_len; + u16_t vlan; + u8_t rx_hdr_size; + int status; + u16_t len; + + /* maximum packet length from wl_rx() */ + len = WL_MAX_PKT_LEN; + + /* We allocate a continous pbuf */ + p = pbuf_alloc(PBUF_RAW, len, PBUF_RAM); + if (p == NULL) { + LWIP_DEBUGF(NETIF_DEBUG, ("low_level_input: fail to alloc " + "pbuf of len:%"S32_F"\n", len)); + return NULL; + } + + /* Read the entire msg */ + priv->rx_pending = 0; + wl_rx(p->payload, &len); + if (len == 0) { + LWIP_DEBUGF(NETIF_DEBUG, ("low_level_input: len was 0")); + return NULL; + } + + status = wl_process_rx( + p->payload, /* input buf */ + len, /* input buf length */ + &stripped_pkt, + &stripped_pkt_len, + &vlan); + + if (status == WL_ABSORBED) { + LWIP_DEBUGF(NETIF_DEBUG, ("low_level_input: absorbed")); + pbuf_free(p); + return NULL; + } + + /* Data packet, remove padding */ + rx_hdr_size = stripped_pkt - (char*) p->payload; + pbuf_realloc(p, stripped_pkt_len + rx_hdr_size); + + LINK_STATS_INC(link.recv); + return p; +} + + +/** + * This function will be called by wlif_poll() when a packet has been received + * from the mac. Then the type of the received packet is determined and + * the appropriate input function is called. + * + * @param netif the lwip network interface structure for this ethernetif + */ +static void +wlif_input(struct netif *netif) +{ + struct eth_hdr *ethhdr; + struct pbuf *p; + + /* move received packet into a new pbuf */ + p = low_level_input(netif); + + /* no packet could be read, silently ignore this */ + if (p == NULL) + return; + + /* points to packet payload, which starts with an Ethernet header */ + ethhdr = p->payload; + switch (htons(ethhdr->type)) { + /* IP or ARP packet? */ + case ETHTYPE_IP: + case ETHTYPE_ARP: +#if PPPOE_SUPPORT + /* PPPoE packet? */ + case ETHTYPE_PPPOEDISC: + case ETHTYPE_PPPOE: +#endif /* PPPOE_SUPPORT */ + /* full packet send to tcpip_thread to process */ + if (netif->input(p, netif) != ERR_OK) { + LWIP_DEBUGF(NETIF_DEBUG, + ("wlif_input: IP input error\n")); + pbuf_free(p); + p = NULL; + } + break; + + default: + pbuf_free(p); + p = NULL; + break; + } +} + +static ssize_t pkt_read_cb(char *dst, + void *src_handle, + size_t read_len, + int offset) { + ssize_t rc; + + rc = pbuf_copy_partial((struct pbuf *)src_handle, + dst, + read_len, + offset + WL_HEADER_SIZE); + if ( 0 == rc ) { + return -1; + } + + return rc; +} + +/** + * Should be called at the beginning of the program to set up the + * network interface. It calls the function low_level_init() to do the + * actual setup of the hardware. + * + * This function should be passed as a parameter to netif_add(). + * + * @param netif the lwip network interface structure for this ethernetif + * @return ERR_OK if the loopif is initialized + * ERR_MEM if private data couldn't be allocated + * any other err_t on error + */ +err_t +wlif_init(struct netif *netif) +{ + static struct wlif_t wlif; + + LWIP_ASSERT("netif != NULL", (netif != NULL)); + +#if LWIP_NETIF_HOSTNAME + /* Initialize interface hostname */ + if ( NULL == netif->hostname ) { + netif->hostname = "wlif"; + } +#endif /* LWIP_NETIF_HOSTNAME */ + + netif->state = &wlif; + netif->name[0] = IFNAME0; + netif->name[1] = IFNAME1; + + /* We directly use etharp_output() here to save a function call. + * You can instead declare your own function an call etharp_output() + * from it if you have to do some checks before sending (e.g. if link + * is available...) */ + netif->output = etharp_output; + netif->linkoutput = low_level_output; + + wl_register_rx_isr(rx_isr, netif); + wl_register_pkt_read_cb(pkt_read_cb); + + /* initialize the hardware */ + return low_level_init(netif); +} + + +/** + * + */ +void +wlif_poll(struct netif* netif) +{ + struct wlif_t* priv = NULL; + + /* wl api forward progress */ + wl_poll(); + + if (netif) + priv = (struct wlif_t*) netif->state; + + /* wlif_init() not called yet? */ + if (priv == NULL) + return; + + /* no packets pending? */ + if (!priv->rx_pending) + return; + + /* read the pending packet */ + wlif_input(netif); + + /* send any packets that was queued due to filled up target queue + * or power save mode. + */ + process_pqueue(netif); +} diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/readme.txt b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/readme.txt new file mode 100644 index 0000000000000000000000000000000000000000..c95f30e72229e90fa2e5f98da36e7e488ef240ef --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/readme.txt @@ -0,0 +1 @@ +This directory is specific to the WIFI H&D SPB104 components (\COMPONENTS\WIFI\HD_SPB104). diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS/ctrl_access.c b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS/ctrl_access.c new file mode 100644 index 0000000000000000000000000000000000000000..09790c259c9a6511bd9bcbf80ceae9804aa4b072 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS/ctrl_access.c @@ -0,0 +1,571 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Abstraction layer for memory interfaces. + * + * This module contains the interfaces: + * - MEM <-> USB; + * - MEM <-> RAM; + * - MEM <-> MEM. + * + * This module may be configured and expanded to support the following features: + * - write-protected globals; + * - password-protected data; + * - specific features; + * - etc. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +//_____ I N C L U D E S ____________________________________________________ + +#include "compiler.h" +#include "preprocessor.h" +#ifdef FREERTOS_USED +#include "FreeRTOS.h" +#include "semphr.h" +#endif +#include "ctrl_access.h" + + +//_____ D E F I N I T I O N S ______________________________________________ + +#ifdef FREERTOS_USED + +/*! \name LUN Access Protection Macros + */ +//! @{ + +/*! \brief Locks accesses to LUNs. + * + * \return \c TRUE if the access was successfully locked, else \c FALSE. + */ +#define Ctrl_access_lock() ctrl_access_lock() + +/*! \brief Unlocks accesses to LUNs. + */ +#define Ctrl_access_unlock() xSemaphoreGive(ctrl_access_semphr) + +//! @} + +//! Handle to the semaphore protecting accesses to LUNs. +static xSemaphoreHandle ctrl_access_semphr = NULL; + +#else + +/*! \name LUN Access Protection Macros + */ +//! @{ + +/*! \brief Locks accesses to LUNs. + * + * \return \c TRUE if the access was successfully locked, else \c FALSE. + */ +#define Ctrl_access_lock() TRUE + +/*! \brief Unlocks accesses to LUNs. + */ +#define Ctrl_access_unlock() + +//! @} + +#endif // FREERTOS_USED + + +#if MAX_LUN + +/*! \brief Initializes an entry of the LUN descriptor table. + * + * \param lun Logical Unit Number. + * + * \return LUN descriptor table entry initializer. + */ +#if ACCESS_USB == ENABLED && ACCESS_MEM_TO_RAM == ENABLED +#define Lun_desc_entry(lun) \ + {\ + TPASTE3(Lun_, lun, _test_unit_ready),\ + TPASTE3(Lun_, lun, _read_capacity),\ + TPASTE3(Lun_, lun, _wr_protect),\ + TPASTE3(Lun_, lun, _removal),\ + TPASTE3(Lun_, lun, _usb_read_10),\ + TPASTE3(Lun_, lun, _usb_write_10),\ + TPASTE3(Lun_, lun, _mem_2_ram),\ + TPASTE3(Lun_, lun, _ram_2_mem),\ + TPASTE3(LUN_, lun, _NAME)\ + } +#elif ACCESS_USB == ENABLED +#define Lun_desc_entry(lun) \ + {\ + TPASTE3(Lun_, lun, _test_unit_ready),\ + TPASTE3(Lun_, lun, _read_capacity),\ + TPASTE3(Lun_, lun, _wr_protect),\ + TPASTE3(Lun_, lun, _removal),\ + TPASTE3(Lun_, lun, _usb_read_10),\ + TPASTE3(Lun_, lun, _usb_write_10),\ + TPASTE3(LUN_, lun, _NAME)\ + } +#elif ACCESS_MEM_TO_RAM == ENABLED +#define Lun_desc_entry(lun) \ + {\ + TPASTE3(Lun_, lun, _test_unit_ready),\ + TPASTE3(Lun_, lun, _read_capacity),\ + TPASTE3(Lun_, lun, _wr_protect),\ + TPASTE3(Lun_, lun, _removal),\ + TPASTE3(Lun_, lun, _mem_2_ram),\ + TPASTE3(Lun_, lun, _ram_2_mem),\ + TPASTE3(LUN_, lun, _NAME)\ + } +#else +#define Lun_desc_entry(lun) \ + {\ + TPASTE3(Lun_, lun, _test_unit_ready),\ + TPASTE3(Lun_, lun, _read_capacity),\ + TPASTE3(Lun_, lun, _wr_protect),\ + TPASTE3(Lun_, lun, _removal),\ + TPASTE3(LUN_, lun, _NAME)\ + } +#endif + +//! LUN descriptor table. +static const struct +{ + Ctrl_status (*test_unit_ready)(void); + Ctrl_status (*read_capacity)(U32 *); + Bool (*wr_protect)(void); + Bool (*removal)(void); +#if ACCESS_USB == ENABLED + Ctrl_status (*usb_read_10)(U32, U16); + Ctrl_status (*usb_write_10)(U32, U16); +#endif +#if ACCESS_MEM_TO_RAM == ENABLED + Ctrl_status (*mem_2_ram)(U32, void *); + Ctrl_status (*ram_2_mem)(U32, const void *); +#endif + const char *name; +} lun_desc[MAX_LUN] = +{ +#if LUN_0 == ENABLE + Lun_desc_entry(0), +#endif +#if LUN_1 == ENABLE + Lun_desc_entry(1), +#endif +#if LUN_2 == ENABLE + Lun_desc_entry(2), +#endif +#if LUN_3 == ENABLE + Lun_desc_entry(3), +#endif +#if LUN_4 == ENABLE + Lun_desc_entry(4), +#endif +#if LUN_5 == ENABLE + Lun_desc_entry(5), +#endif +#if LUN_6 == ENABLE + Lun_desc_entry(6), +#endif +#if LUN_7 == ENABLE + Lun_desc_entry(7) +#endif +}; + +#endif + + +#if GLOBAL_WR_PROTECT == ENABLED +Bool g_wr_protect; +#endif + + +/*! \name Control Interface + */ +//! @{ + + +#ifdef FREERTOS_USED + +Bool ctrl_access_init(void) +{ + // If the handle to the protecting semaphore is not valid, + if (!ctrl_access_semphr) + { + // try to create the semaphore. + vSemaphoreCreateBinary(ctrl_access_semphr); + + // If the semaphore could not be created, there is no backup solution. + if (!ctrl_access_semphr) return FALSE; + } + + return TRUE; +} + + +/*! \brief Locks accesses to LUNs. + * + * \return \c TRUE if the access was successfully locked, else \c FALSE. + */ +static Bool ctrl_access_lock(void) +{ + // If the semaphore could not be created, there is no backup solution. + if (!ctrl_access_semphr) return FALSE; + + // Wait for the semaphore. + while (!xSemaphoreTake(ctrl_access_semphr, portMAX_DELAY)); + + return TRUE; +} + +#endif // FREERTOS_USED + + +U8 get_nb_lun(void) +{ +#if MEM_USB == ENABLE + U8 nb_lun; + + if (!Ctrl_access_lock()) return MAX_LUN; + + nb_lun = MAX_LUN + host_get_lun(); + + Ctrl_access_unlock(); + + return nb_lun; +#else + return MAX_LUN; +#endif +} + + +U8 get_cur_lun(void) +{ + return LUN_ID_0; +} + + +Ctrl_status mem_test_unit_ready(U8 lun) +{ + Ctrl_status status; + + if (!Ctrl_access_lock()) return CTRL_FAIL; + + status = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].test_unit_ready() : +#endif +#if LUN_USB == ENABLE + Lun_usb_test_unit_ready(lun - LUN_ID_USB); +#else + CTRL_FAIL; +#endif + + Ctrl_access_unlock(); + + return status; +} + + +Ctrl_status mem_read_capacity(U8 lun, U32 *u32_nb_sector) +{ + Ctrl_status status; + + if (!Ctrl_access_lock()) return CTRL_FAIL; + + status = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].read_capacity(u32_nb_sector) : +#endif +#if LUN_USB == ENABLE + Lun_usb_read_capacity(lun - LUN_ID_USB, u32_nb_sector); +#else + CTRL_FAIL; +#endif + + Ctrl_access_unlock(); + + return status; +} + + +U8 mem_sector_size(U8 lun) +{ + U8 sector_size; + + if (!Ctrl_access_lock()) return 0; + + sector_size = +#if MAX_LUN + (lun < MAX_LUN) ? 1 : +#endif +#if LUN_USB == ENABLE + Lun_usb_read_sector_size(lun - LUN_ID_USB); +#else + 0; +#endif + + Ctrl_access_unlock(); + + return sector_size; +} + + +Bool mem_wr_protect(U8 lun) +{ + Bool wr_protect; + + if (!Ctrl_access_lock()) return TRUE; + + wr_protect = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].wr_protect() : +#endif +#if LUN_USB == ENABLE + Lun_usb_wr_protect(lun - LUN_ID_USB); +#else + TRUE; +#endif + + Ctrl_access_unlock(); + + return wr_protect; +} + + +Bool mem_removal(U8 lun) +{ + Bool removal; + + if (!Ctrl_access_lock()) return TRUE; + + removal = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].removal() : +#endif +#if LUN_USB == ENABLE + Lun_usb_removal(); +#else + TRUE; +#endif + + Ctrl_access_unlock(); + + return removal; +} + + +const char *mem_name(U8 lun) +{ + return +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].name : +#endif +#if LUN_USB == ENABLE + LUN_USB_NAME; +#else + NULL; +#endif +} + + +//! @} + + +#if ACCESS_USB == ENABLED + +/*! \name MEM <-> USB Interface + */ +//! @{ + + +Ctrl_status memory_2_usb(U8 lun, U32 addr, U16 nb_sector) +{ + Ctrl_status status; + + if (!Ctrl_access_lock()) return CTRL_FAIL; + + memory_start_read_action(nb_sector); + status = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].usb_read_10(addr, nb_sector) : +#endif + CTRL_FAIL; + memory_stop_read_action(); + + Ctrl_access_unlock(); + + return status; +} + + +Ctrl_status usb_2_memory(U8 lun, U32 addr, U16 nb_sector) +{ + Ctrl_status status; + + if (!Ctrl_access_lock()) return CTRL_FAIL; + + memory_start_write_action(nb_sector); + status = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].usb_write_10(addr, nb_sector) : +#endif + CTRL_FAIL; + memory_stop_write_action(); + + Ctrl_access_unlock(); + + return status; +} + + +//! @} + +#endif // ACCESS_USB == ENABLED + + +#if ACCESS_MEM_TO_RAM == ENABLED + +/*! \name MEM <-> RAM Interface + */ +//! @{ + + +Ctrl_status memory_2_ram(U8 lun, U32 addr, void *ram) +{ + Ctrl_status status; + + if (!Ctrl_access_lock()) return CTRL_FAIL; + + memory_start_read_action(1); + status = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].mem_2_ram(addr, ram) : +#endif +#if LUN_USB == ENABLE + Lun_usb_mem_2_ram(addr, ram); +#else + CTRL_FAIL; +#endif + memory_stop_read_action(); + + Ctrl_access_unlock(); + + return status; +} + + +Ctrl_status ram_2_memory(U8 lun, U32 addr, const void *ram) +{ + Ctrl_status status; + + if (!Ctrl_access_lock()) return CTRL_FAIL; + + memory_start_write_action(1); + status = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].ram_2_mem(addr, ram) : +#endif +#if LUN_USB == ENABLE + Lun_usb_ram_2_mem(addr, ram); +#else + CTRL_FAIL; +#endif + memory_stop_write_action(); + + Ctrl_access_unlock(); + + return status; +} + + +//! @} + +#endif // ACCESS_MEM_TO_RAM == ENABLED + + +#if ACCESS_STREAM == ENABLED + +/*! \name Streaming MEM <-> MEM Interface + */ +//! @{ + + + #if ACCESS_MEM_TO_MEM == ENABLED + +#include "fat.h" + +Ctrl_status stream_mem_to_mem(U8 src_lun, U32 src_addr, U8 dest_lun, U32 dest_addr, U16 nb_sector) +{ +#if (defined __GNUC__) && (defined __AVR32__) + __attribute__((__aligned__(4))) +#elif (defined __ICCAVR32__) + #pragma data_alignment = 4 +#endif + static U8 sector_buf[FS_512B]; + Ctrl_status status = CTRL_GOOD; + + while (nb_sector--) + { + if ((status = memory_2_ram(src_lun, src_addr++, sector_buf)) != CTRL_GOOD) break; + if ((status = ram_2_memory(dest_lun, dest_addr++, sector_buf)) != CTRL_GOOD) break; + } + + return status; +} + + #endif // ACCESS_MEM_TO_MEM == ENABLED + + +Ctrl_status stream_state(U8 id) +{ + return CTRL_GOOD; +} + + +U16 stream_stop(U8 id) +{ + return 0; +} + + +//! @} + +#endif // ACCESS_STREAM == ENABLED diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS/ctrl_access.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS/ctrl_access.h new file mode 100644 index 0000000000000000000000000000000000000000..358bf65897cfdef5b61c84898d376cb7da91fd70 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS/ctrl_access.h @@ -0,0 +1,369 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Abstraction layer for memory interfaces. + * + * This module contains the interfaces: + * - MEM <-> USB; + * - MEM <-> RAM; + * - MEM <-> MEM. + * + * This module may be configured and expanded to support the following features: + * - write-protected globals; + * - password-protected data; + * - specific features; + * - etc. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _CTRL_ACCESS_H_ +#define _CTRL_ACCESS_H_ + +#include "compiler.h" +#include "conf_access.h" + + +//! Status returned by CTRL_ACCESS interfaces. +typedef enum +{ + CTRL_GOOD = PASS, //!< Success, memory ready. + CTRL_FAIL = FAIL, //!< An error occurred. + CTRL_NO_PRESENT = FAIL + 1, //!< Memory unplugged. + CTRL_BUSY = FAIL + 2 //!< Memory not initialized or changed. +} Ctrl_status; + + +// FYI: Each Logical Unit Number (LUN) corresponds to a memory. + +// Check LUN defines. +#ifndef LUN_0 + #error LUN_0 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_1 + #error LUN_1 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_2 + #error LUN_2 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_3 + #error LUN_3 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_4 + #error LUN_4 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_5 + #error LUN_5 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_6 + #error LUN_6 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_7 + #error LUN_7 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_USB + #error LUN_USB must be defined as ENABLE or DISABLE in conf_access.h +#endif + +/*! \name LUN IDs + */ +//! @{ +#define LUN_ID_0 (0) //!< First static LUN. +#define LUN_ID_1 (LUN_ID_0 + LUN_0) +#define LUN_ID_2 (LUN_ID_1 + LUN_1) +#define LUN_ID_3 (LUN_ID_2 + LUN_2) +#define LUN_ID_4 (LUN_ID_3 + LUN_3) +#define LUN_ID_5 (LUN_ID_4 + LUN_4) +#define LUN_ID_6 (LUN_ID_5 + LUN_5) +#define LUN_ID_7 (LUN_ID_6 + LUN_6) +#define MAX_LUN (LUN_ID_7 + LUN_7) //!< Number of static LUNs. +#define LUN_ID_USB (MAX_LUN) //!< First dynamic LUN (USB host mass storage). +//! @} + + +// Include LUN header files. +#if LUN_0 == ENABLE + #include LUN_0_INCLUDE +#endif +#if LUN_1 == ENABLE + #include LUN_1_INCLUDE +#endif +#if LUN_2 == ENABLE + #include LUN_2_INCLUDE +#endif +#if LUN_3 == ENABLE + #include LUN_3_INCLUDE +#endif +#if LUN_4 == ENABLE + #include LUN_4_INCLUDE +#endif +#if LUN_5 == ENABLE + #include LUN_5_INCLUDE +#endif +#if LUN_6 == ENABLE + #include LUN_6_INCLUDE +#endif +#if LUN_7 == ENABLE + #include LUN_7_INCLUDE +#endif +#if LUN_USB == ENABLE + #include LUN_USB_INCLUDE +#endif + + +// Check the configuration of write protection in conf_access.h. +#ifndef GLOBAL_WR_PROTECT + #error GLOBAL_WR_PROTECT must be defined as ENABLED or DISABLED in conf_access.h +#endif + + +#if GLOBAL_WR_PROTECT == ENABLED + +//! Write protect. +extern Bool g_wr_protect; + +#endif + + +/*! \name Control Interface + */ +//! @{ + +#ifdef FREERTOS_USED + +/*! \brief Initializes the LUN access locker. + * + * \return \c TRUE if the locker was successfully initialized, else \c FALSE. + */ +extern Bool ctrl_access_init(void); + +#endif // FREERTOS_USED + +/*! \brief Returns the number of LUNs. + * + * \return Number of LUNs in the system. + */ +extern U8 get_nb_lun(void); + +/*! \brief Returns the current LUN. + * + * \return Current LUN. + * + * \todo Implement. + */ +extern U8 get_cur_lun(void); + +/*! \brief Tests the memory state and initializes the memory if required. + * + * The TEST UNIT READY SCSI primary command allows an application client to poll + * a LUN until it is ready without having to allocate memory for returned data. + * + * This command may be used to check the media status of LUNs with removable + * media. + * + * \param lun Logical Unit Number. + * + * \return Status. + */ +extern Ctrl_status mem_test_unit_ready(U8 lun); + +/*! \brief Returns the address of the last valid sector (512 bytes) in the + * memory. + * + * \param lun Logical Unit Number. + * \param u32_nb_sector Pointer to the address of the last valid sector. + * + * \return Status. + */ +extern Ctrl_status mem_read_capacity(U8 lun, U32 *u32_nb_sector); + +/*! \brief Returns the size of the physical sector. + * + * \param lun Logical Unit Number. + * + * \return Sector size (unit: 512 bytes). + */ +extern U8 mem_sector_size(U8 lun); + +/*! \brief Returns the write-protection state of the memory. + * + * \param lun Logical Unit Number. + * + * \return \c TRUE if the memory is write-protected, else \c FALSE. + * + * \note Only used by removable memories with hardware-specific write + * protection. + */ +extern Bool mem_wr_protect(U8 lun); + +/*! \brief Tells whether the memory is removable. + * + * \param lun Logical Unit Number. + * + * \return \c TRUE if the memory is removable, else \c FALSE. + */ +extern Bool mem_removal(U8 lun); + +/*! \brief Returns a pointer to the LUN name. + * + * \param lun Logical Unit Number. + * + * \return Pointer to the LUN name string. + */ +extern const char *mem_name(U8 lun); + +//! @} + + +#if ACCESS_USB == ENABLED + +/*! \name MEM <-> USB Interface + */ +//! @{ + +/*! \brief Tranfers data from the memory to USB. + * + * \param lun Logical Unit Number. + * \param addr Address of first memory sector to read. + * \param nb_sector Number of sectors to transfer. + * + * \return Status. + */ +extern Ctrl_status memory_2_usb(U8 lun, U32 addr, U16 nb_sector); + +/*! \brief Tranfers data from USB to the memory. + * + * \param lun Logical Unit Number. + * \param addr Address of first memory sector to write. + * \param nb_sector Number of sectors to transfer. + * + * \return Status. + */ +extern Ctrl_status usb_2_memory(U8 lun, U32 addr, U16 nb_sector); + +//! @} + +#endif // ACCESS_USB == ENABLED + + +#if ACCESS_MEM_TO_RAM == ENABLED + +/*! \name MEM <-> RAM Interface + */ +//! @{ + +/*! \brief Copies 1 data sector from the memory to RAM. + * + * \param lun Logical Unit Number. + * \param addr Address of first memory sector to read. + * \param ram Pointer to RAM buffer to write. + * + * \return Status. + */ +extern Ctrl_status memory_2_ram(U8 lun, U32 addr, void *ram); + +/*! \brief Copies 1 data sector from RAM to the memory. + * + * \param lun Logical Unit Number. + * \param addr Address of first memory sector to write. + * \param ram Pointer to RAM buffer to read. + * + * \return Status. + */ +extern Ctrl_status ram_2_memory(U8 lun, U32 addr, const void *ram); + +//! @} + +#endif // ACCESS_MEM_TO_RAM == ENABLED + + +#if ACCESS_STREAM == ENABLED + +/*! \name Streaming MEM <-> MEM Interface + */ +//! @{ + +//! Erroneous streaming data transfer ID. +#define ID_STREAM_ERR 0xFF + + #if ACCESS_MEM_TO_MEM == ENABLED + +/*! \brief Copies data from one memory to another. + * + * \param src_lun Source Logical Unit Number. + * \param src_addr Source address of first memory sector to read. + * \param dest_lun Destination Logical Unit Number. + * \param dest_addr Destination address of first memory sector to write. + * \param nb_sector Number of sectors to copy. + * + * \return Status. + */ +extern Ctrl_status stream_mem_to_mem(U8 src_lun, U32 src_addr, U8 dest_lun, U32 dest_addr, U16 nb_sector); + + #endif // ACCESS_MEM_TO_MEM == ENABLED + +/*! \brief Returns the state of a streaming data transfer. + * + * \param id Transfer ID. + * + * \return Status. + * + * \todo Implement. + */ +extern Ctrl_status stream_state(U8 id); + +/*! \brief Stops a streaming data transfer. + * + * \param id Transfer ID. + * + * \return Number of remaining sectors. + * + * \todo Implement. + */ +extern U16 stream_stop(U8 id); + +//! @} + +#endif // ACCESS_STREAM == ENABLED + + +#endif // _CTRL_ACCESS_H_ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/debug.c b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/debug.c new file mode 100644 index 0000000000000000000000000000000000000000..fe8a2a0d8bc3b053686c41e10eba541777ac8bf0 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/debug.c @@ -0,0 +1,133 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Macros and functions dedicated to debug purposes. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include "compiler.h" +#include "debug.h" +#include "util.h" + + +#if (defined __GNUC__) +# include "malloc.h" + +U32 get_heap_curr_used_size( void ) +{ + struct mallinfo my_info=mallinfo(); + return my_info.uordblks; +} + +U32 get_heap_total_used_size( void ) +{ + struct mallinfo my_info=mallinfo(); + return my_info.arena; +} +#endif + +U32 get_heap_free_size( void ) +{ + U32 high_mark= AVR32_SRAM_SIZE; + U32 low_mark = 0; + U32 size ; + void* p_mem; + + size = (high_mark + low_mark)/2; + + do + { + p_mem = malloc(size); + if( p_mem != NULL) + { // Can allocate memory + free(p_mem); + low_mark = size; + } + else + { // Can not allocate memory + high_mark = size; + } + + size = (high_mark + low_mark)/2; + } + while( (high_mark-low_mark) >1 ); + + return size; +} + +static void* round_trace_pbuf; +static U32 round_trace_size; + +void uc3_round_trace_init(void* buf, U32 size) +{ + round_trace_pbuf = buf; + (*(U32*)round_trace_pbuf)=(U32)buf+4; + round_trace_size = size; +} + +void uc3_round_trace(U32 val) +{ + //Disable_global_interrupt(); + + U32* p_wr = (U32*)(*(U32*)round_trace_pbuf); + *p_wr = val; + p_wr++; + if( ((U32)p_wr % round_trace_size) ==0 ) + p_wr= (U32*)round_trace_pbuf+1; + *p_wr = 0xdeadbeef; + *(U32*)round_trace_pbuf = (U32)p_wr; + + //Enable_global_interrupt(); +} + +void dump(char* _buf, uint16_t _count) { + + int i; + for (i = 0; i < _count; ++i) + { + printk("0x%x ", _buf[i]); + if ((i!=0)&&(i % 10 == 0)) + printk("\n\t"); + } + printk("\n"); +} + diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/debug.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/debug.h new file mode 100644 index 0000000000000000000000000000000000000000..a832d7c9c0aa6191223c5627dcf8c0dc896b8e94 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/debug.h @@ -0,0 +1,116 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Macros and functions dedicated to debug purposes. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _DEBUG_H_ +#define _DEBUG_H_ + +#include "stringz.h" + +/*! \brief These macros are used to add traces memory. + * + * First, initialise the trace with Uc3_trace_init(pointer), giving the start address + * of the memory location where will be stored the trace. + * Use Uc3_trace(something) to store "something" into the memory. The end of the trace + * is signaled by the "0xdeadbeef" pattern. + */ +#define Uc3_trace_init(debug_addr) \ + *(U32*)(debug_addr)=debug_addr+4 + +#define Uc3_trace(debug_addr, x) \ + *(U32*)(*(U32*)(debug_addr) ) = (U32)(x) ;\ + *(U32*)(*(U32*)(debug_addr)+4) = 0xdeadbeef ;\ + *(U32*)(debug_addr ) = *(U32*)(debug_addr)+4 + +/*! \brief This macro is used to insert labels into assembly output. + * + */ +#define Insert_label(name) \ + __asm__ __volatile__ (STRINGZ(name)":"); + +#if (defined __GNUC__) +/*! \brief Returns the number of total of used bytes allocated from the HEAP. + * + * \retval total number of used bytes. + */ +U32 get_heap_total_used_size( void ); + +/*! \brief Returns the number of bytes currently used from the HEAP. + * + * \retval total number of used bytes. + */ +U32 get_heap_curr_used_size( void ); +#endif + +/*! \brief Returns the number of free bytes in the HEAP. + * + * This funtion tries to allocate the maximum number of bytes by dichotomical method. + * + * \retval number of free bytes. + */ +extern U32 get_heap_free_size( void ); + +/*! \name Traces function using a round buffer + */ +//! @{ + +/*! \brief Initialize the trace using a round buffer. + * + * \param buf Base address of the buffer used for the trace. + * \param size Size of the round buffer. Must be a power of 2. + */ +void uc3_round_trace_init(void* buf, U32 size); + +/*! \brief Trace a data in the round buffer. + * + * The end of the trace is signaled by the "0xdeadbeef" pattern. + * \param val Data to trace; + */ +void uc3_round_trace(U32 val); + +//! @} + + +#endif // _DEBUG_H_ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/print_funcs.c b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/print_funcs.c new file mode 100644 index 0000000000000000000000000000000000000000..99e9274662f6f840e31683f1e548ba1df09d207a --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/print_funcs.c @@ -0,0 +1,215 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Strings and integers print module for debug purposes. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include "compiler.h" +#include "gpio.h" +#include "usart.h" +#include "print_funcs.h" + + +//! ASCII representation of hexadecimal digits. +static const char HEX_DIGITS[16] = "0123456789ABCDEF"; + + +void init_dbg_rs232(long pba_hz) +{ + init_dbg_rs232_ex(DBG_USART_BAUDRATE, pba_hz); +} + + +void init_dbg_rs232_ex(unsigned long baudrate, long pba_hz) +{ + static const gpio_map_t DBG_USART_GPIO_MAP = + { + {DBG_USART_RX_PIN, DBG_USART_RX_FUNCTION}, + {DBG_USART_TX_PIN, DBG_USART_TX_FUNCTION} + }; + + // Options for debug USART. + usart_options_t dbg_usart_options = + { + .baudrate = baudrate, + .charlength = 8, + .paritytype = USART_NO_PARITY, + .stopbits = USART_1_STOPBIT, + .channelmode = USART_NORMAL_CHMODE + }; + + // Setup GPIO for debug USART. + gpio_enable_module(DBG_USART_GPIO_MAP, + sizeof(DBG_USART_GPIO_MAP) / sizeof(DBG_USART_GPIO_MAP[0])); + + // Initialize it in RS232 mode. + usart_init_rs232(DBG_USART, &dbg_usart_options, pba_hz); +} + + +void print_dbg(const char *str) +{ + // Redirection to the debug USART. + print(DBG_USART, str); +} + + +void print_dbg_char(int c) +{ + // Redirection to the debug USART. + print_char(DBG_USART, c); +} + + +void print_dbg_ulong(unsigned long n) +{ + // Redirection to the debug USART. + print_ulong(DBG_USART, n); +} + + +void print_dbg_char_hex(unsigned char n) +{ + // Redirection to the debug USART. + print_char_hex(DBG_USART, n); +} + + +void print_dbg_short_hex(unsigned short n) +{ + // Redirection to the debug USART. + print_short_hex(DBG_USART, n); +} + + +void print_dbg_hex(unsigned long n) +{ + // Redirection to the debug USART. + print_hex(DBG_USART, n); +} + + +void print(volatile avr32_usart_t *usart, const char *str) +{ + // Invoke the USART driver to transmit the input string with the given USART. + usart_write_line(usart, str); +} + + +void print_char(volatile avr32_usart_t *usart, int c) +{ + // Invoke the USART driver to transmit the input character with the given USART. + usart_putchar(usart, c); +} + + +void print_ulong(volatile avr32_usart_t *usart, unsigned long n) +{ + char tmp[11]; + int i = sizeof(tmp) - 1; + + // Convert the given number to an ASCII decimal representation. + tmp[i] = '\0'; + do + { + tmp[--i] = '0' + n % 10; + n /= 10; + } while (n); + + // Transmit the resulting string with the given USART. + print(usart, tmp + i); +} + + +void print_char_hex(volatile avr32_usart_t *usart, unsigned char n) +{ + char tmp[3]; + int i; + + // Convert the given number to an ASCII hexadecimal representation. + tmp[2] = '\0'; + for (i = 1; i >= 0; i--) + { + tmp[i] = HEX_DIGITS[n & 0xF]; + n >>= 4; + } + + // Transmit the resulting string with the given USART. + print(usart, tmp); +} + + +void print_short_hex(volatile avr32_usart_t *usart, unsigned short n) +{ + char tmp[5]; + int i; + + // Convert the given number to an ASCII hexadecimal representation. + tmp[4] = '\0'; + for (i = 3; i >= 0; i--) + { + tmp[i] = HEX_DIGITS[n & 0xF]; + n >>= 4; + } + + // Transmit the resulting string with the given USART. + print(usart, tmp); +} + + +void print_hex(volatile avr32_usart_t *usart, unsigned long n) +{ + char tmp[9]; + int i; + + // Convert the given number to an ASCII hexadecimal representation. + tmp[8] = '\0'; + for (i = 7; i >= 0; i--) + { + tmp[i] = HEX_DIGITS[n & 0xF]; + n >>= 4; + } + + // Transmit the resulting string with the given USART. + print(usart, tmp); +} diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/print_funcs.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/print_funcs.h new file mode 100644 index 0000000000000000000000000000000000000000..38f931dc2450dc281339ae208a957ff70b58ef7b --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/print_funcs.h @@ -0,0 +1,294 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Strings and integers print module for debug purposes. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _PRINT_FUNCS_H_ +#define _PRINT_FUNCS_H_ + +#include +#include "board.h" + + +/*! \name USART Settings for the Debug Module + */ +//! @{ +#if BOARD == EVK1100 +# define DBG_USART (&AVR32_USART1) +# define DBG_USART_RX_PIN AVR32_USART1_RXD_0_0_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART1_RXD_0_0_FUNCTION +# define DBG_USART_TX_PIN AVR32_USART1_TXD_0_0_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART1_TXD_0_0_FUNCTION +# define DBG_USART_BAUDRATE 57600 +#elif BOARD == EVK1101 +# define DBG_USART (&AVR32_USART1) +# define DBG_USART_RX_PIN AVR32_USART1_RXD_0_0_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART1_RXD_0_0_FUNCTION +# define DBG_USART_TX_PIN AVR32_USART1_TXD_0_0_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART1_TXD_0_0_FUNCTION +# define DBG_USART_BAUDRATE 57600 +#elif BOARD == UC3C_EK +# define DBG_USART (&AVR32_USART2) +# define DBG_USART_RX_PIN AVR32_USART2_RXD_0_1_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART2_RXD_0_1_FUNCTION +# define DBG_USART_TX_PIN AVR32_USART2_TXD_0_1_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART2_TXD_0_1_FUNCTION +# define DBG_USART_BAUDRATE 57600 +#elif BOARD == EVK1104 +# define DBG_USART (&AVR32_USART1) +# define DBG_USART_RX_PIN AVR32_USART1_RXD_0_0_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART1_RXD_0_0_FUNCTION +# define DBG_USART_TX_PIN AVR32_USART1_TXD_0_0_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART1_TXD_0_0_FUNCTION +# define DBG_USART_BAUDRATE 57600 +#elif BOARD == EVK1105 +# define DBG_USART (&AVR32_USART0) +# define DBG_USART_RX_PIN AVR32_USART0_RXD_0_0_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART0_RXD_0_0_FUNCTION +# define DBG_USART_TX_PIN AVR32_USART0_TXD_0_0_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART0_TXD_0_0_FUNCTION +# define DBG_USART_BAUDRATE 57600 +#elif BOARD == STK1000 +# define DBG_USART (&AVR32_USART1) +# define DBG_USART_RX_PIN AVR32_USART1_RXD_0_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART1_RXD_0_FUNCTION +# define DBG_USART_TX_PIN AVR32_USART1_TXD_0_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART1_TXD_0_FUNCTION +# define DBG_USART_BAUDRATE 115200 +#elif BOARD == NGW100 +# define DBG_USART (&AVR32_USART1) +# define DBG_USART_RX_PIN AVR32_USART1_RXD_0_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART1_RXD_0_FUNCTION +# define DBG_USART_TX_PIN AVR32_USART1_TXD_0_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART1_TXD_0_FUNCTION +# define DBG_USART_BAUDRATE 115200 +#elif BOARD == STK600_RCUC3L0 +# define DBG_USART (&AVR32_USART1) +# define DBG_USART_RX_PIN AVR32_USART1_RXD_0_1_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART1_RXD_0_1_FUNCTION +// For the RX pin, connect STK600.PORTE.PE3 to STK600.RS232 SPARE.RXD +# define DBG_USART_TX_PIN AVR32_USART1_TXD_0_1_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART1_TXD_0_1_FUNCTION +// For the TX pin, connect STK600.PORTE.PE2 to STK600.RS232 SPARE.TXD +# define DBG_USART_BAUDRATE 57600 +# define DBG_USART_CLOCK_MASK AVR32_USART1_CLK_PBA +#elif BOARD == UC3L_EK +# define DBG_USART (&AVR32_USART3) +# define DBG_USART_RX_PIN AVR32_USART3_RXD_0_0_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART3_RXD_0_0_FUNCTION +# define DBG_USART_TX_PIN AVR32_USART3_TXD_0_0_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART3_TXD_0_0_FUNCTION +# define DBG_USART_BAUDRATE 57600 +# define DBG_USART_CLOCK_MASK AVR32_USART3_CLK_PBA +#elif BOARD == ARDUINO +# define DBG_USART (&AVR32_USART1) +# define DBG_USART_RX_PIN AVR32_USART1_RXD_0_0_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART1_RXD_0_0_FUNCTION +# define DBG_USART_TX_PIN AVR32_USART1_TXD_0_0_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART1_TXD_0_0_FUNCTION +# define DBG_USART_BAUDRATE 57600 +# define DBG_USART_CLOCK_MASK AVR32_USART1_CLK_PBA +#endif + +#if !defined(DBG_USART) || \ + !defined(DBG_USART_RX_PIN) || \ + !defined(DBG_USART_RX_FUNCTION) || \ + !defined(DBG_USART_TX_PIN) || \ + !defined(DBG_USART_TX_FUNCTION) || \ + !defined(DBG_USART_BAUDRATE) +# error The USART configuration to use for debug on your board is missing +#endif +//! @} + +/*! \name VT100 Common Commands + */ +//! @{ +#define CLEARSCR "\x1B[2J\x1B[;H" //!< Clear screen. +#define CLEAREOL "\x1B[K" //!< Clear end of line. +#define CLEAREOS "\x1B[J" //!< Clear end of screen. +#define CLEARLCR "\x1B[0K" //!< Clear line cursor right. +#define CLEARLCL "\x1B[1K" //!< Clear line cursor left. +#define CLEARELN "\x1B[2K" //!< Clear entire line. +#define CLEARCDW "\x1B[0J" //!< Clear cursor down. +#define CLEARCUP "\x1B[1J" //!< Clear cursor up. +#define GOTOYX "\x1B[%.2d;%.2dH" //!< Set cursor to (y, x). +#define INSERTMOD "\x1B[4h" //!< Insert mode. +#define OVERWRITEMOD "\x1B[4l" //!< Overwrite mode. +#define DELAFCURSOR "\x1B[K" //!< Erase from cursor to end of line. +#define CRLF "\r\n" //!< Carriage Return + Line Feed. +//! @} + +/*! \name VT100 Cursor Commands + */ +//! @{ +#define CURSON "\x1B[?25h" //!< Show cursor. +#define CURSOFF "\x1B[?25l" //!< Hide cursor. +//! @} + +/*! \name VT100 Character Commands + */ +//! @{ +#define NORMAL "\x1B[0m" //!< Normal. +#define BOLD "\x1B[1m" //!< Bold. +#define UNDERLINE "\x1B[4m" //!< Underline. +#define BLINKING "\x1B[5m" //!< Blink. +#define INVVIDEO "\x1B[7m" //!< Inverse video. +//! @} + +/*! \name VT100 Color Commands + */ +//! @{ +#define CL_BLACK "\033[22;30m" //!< Black. +#define CL_RED "\033[22;31m" //!< Red. +#define CL_GREEN "\033[22;32m" //!< Green. +#define CL_BROWN "\033[22;33m" //!< Brown. +#define CL_BLUE "\033[22;34m" //!< Blue. +#define CL_MAGENTA "\033[22;35m" //!< Magenta. +#define CL_CYAN "\033[22;36m" //!< Cyan. +#define CL_GRAY "\033[22;37m" //!< Gray. +#define CL_DARKGRAY "\033[01;30m" //!< Dark gray. +#define CL_LIGHTRED "\033[01;31m" //!< Light red. +#define CL_LIGHTGREEN "\033[01;32m" //!< Light green. +#define CL_YELLOW "\033[01;33m" //!< Yellow. +#define CL_LIGHTBLUE "\033[01;34m" //!< Light blue. +#define CL_LIGHTMAGENTA "\033[01;35m" //!< Light magenta. +#define CL_LIGHTCYAN "\033[01;36m" //!< Light cyan. +#define CL_WHITE "\033[01;37m" //!< White. +//! @} + + +/*! \brief Sets up DBG_USART with 8N1 at DBG_USART_BAUDRATE. + * + * \param pba_hz PBA clock frequency (Hz). + */ +extern void init_dbg_rs232(long pba_hz); + +/*! \brief Sets up DBG_USART with 8N1 at a given baud rate. + * + * \param baudrate Baud rate to set DBG_USART to. + * \param pba_hz PBA clock frequency (Hz). + */ +extern void init_dbg_rs232_ex(unsigned long baudrate, long pba_hz); + +/*! \brief Prints a string of characters to DBG_USART. + * + * \param str The string of characters to print. + */ +extern void print_dbg(const char *str); + +/*! \brief Prints a character to DBG_USART. + * + * \param c The character to print. + */ +extern void print_dbg_char(int c); + +/*! \brief Prints an integer to DBG_USART in a decimal representation. + * + * \param n The integer to print. + */ +extern void print_dbg_ulong(unsigned long n); + +/*! \brief Prints a char to DBG_USART in an hexadecimal representation. + * + * \param n The char to print. + */ +extern void print_dbg_char_hex(unsigned char n); + +/*! \brief Prints a short integer to DBG_USART in an hexadecimal representation. + * + * \param n The short integer to print. + */ +extern void print_dbg_short_hex(unsigned short n); + +/*! \brief Prints an integer to DBG_USART in an hexadecimal representation. + * + * \param n The integer to print. + */ +extern void print_dbg_hex(unsigned long n); + +/*! \brief Prints a string of characters to a given USART. + * + * \param usart Base address of the USART instance to print to. + * \param str The string of characters to print. + */ +extern void print(volatile avr32_usart_t *usart, const char *str); + +/*! \brief Prints a character to a given USART. + * + * \param usart Base address of the USART instance to print to. + * \param c The character to print. + */ +extern void print_char(volatile avr32_usart_t *usart, int c); + +/*! \brief Prints an integer to a given USART in a decimal representation. + * + * \param usart Base address of the USART instance to print to. + * \param n The integer to print. + */ +extern void print_ulong(volatile avr32_usart_t *usart, unsigned long n); + +/*! \brief Prints a char to a given USART in an hexadecimal representation. + * + * \param usart Base address of the USART instance to print to. + * \param n The char to print. + */ +extern void print_char_hex(volatile avr32_usart_t *usart, unsigned char n); + +/*! \brief Prints a short integer to a given USART in an hexadecimal + * representation. + * + * \param usart Base address of the USART instance to print to. + * \param n The short integer to print. + */ +extern void print_short_hex(volatile avr32_usart_t *usart, unsigned short n); + +/*! \brief Prints an integer to a given USART in an hexadecimal representation. + * + * \param usart Base address of the USART instance to print to. + * \param n The integer to print. + */ +extern void print_hex(volatile avr32_usart_t *usart, unsigned long n); + + +#endif // _PRINT_FUNCS_H_ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_cpu.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_cpu.h new file mode 100644 index 0000000000000000000000000000000000000000..e3ebea7a1a4aa57100b1411a74b1df86dcf78396 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_cpu.h @@ -0,0 +1,63 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief NEWLIB_ADDONS CPU include file for AVR32. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef __AVR32_NEWLIB_ADDONS_CPU_H__ +#define __AVR32_NEWLIB_ADDONS_CPU_H__ + +#include <_ansi.h> + +_BEGIN_STD_C + +#define CPU_HZ get_cpu_hz() + +void udelay(unsigned long usec); +void set_cpu_hz(unsigned int clk_hz); +unsigned int get_cpu_hz(); + +_END_STD_C + +#endif diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_exceptions.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_exceptions.h new file mode 100644 index 0000000000000000000000000000000000000000..31caf13044cfb5014d3d4efd1280a643f32cf263 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_exceptions.h @@ -0,0 +1,120 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief NEWLIB_ADDONS exceptions include file for AVR32. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef __AVR32_NEWLIB_ADDONS_EXCEPTIONS_H__ +#define __AVR32_NEWLIB_ADDONS_EXCEPTIONS_H__ + +#include <_ansi.h> + +_BEGIN_STD_C + +/* + Exception vector offsets +*/ +#define EVBA_UNRECOVERABLE 0x000 +#define EVBA_TLB_MULTIPLE 0x004 +#define EVBA_BUS_ERROR_DATA 0x008 +#define EVBA_BUS_ERROR_INSTR 0x00C +#define EVBA_NMI 0x010 +#define EVBA_INSTR_ADDR 0x014 +#define EVBA_ITLB_MISS 0x050 +#define EVBA_ITLB_PROT 0x018 +#define EVBA_BREAKPOINT 0x01C +#define EVBA_ILLEGAL_OPCODE 0x020 +#define EVBA_UNIMPLEMENTED 0x024 +#define EVBA_PRIVILEGE_VIOL 0x028 +#define EVBA_FLOATING_POINT 0x02C +#define EVBA_COP_ABSENT 0x030 +#define EVBA_SCALL 0x100 +#define EVBA_DATA_ADDR_R 0x034 +#define EVBA_DATA_ADDR_W 0x038 +#define EVBA_DTLB_MISS_R 0x060 +#define EVBA_DTLB_MISS_W 0x070 +#define EVBA_DTLB_PROT_R 0x03C +#define EVBA_DTLB_PROT_W 0x040 +#define EVBA_DTLB_MODIFIED 0x044 + + +/* + Define the form of the function used when registering exceptions. + The function should return the address which the exception should + return to after the exception processing. +*/ + +typedef unsigned int (*__exception_handler)(int /*evba_offset*/, int /*return address*/); + +/* + Define the form of the function used when registering a scall handler. +*/ + +typedef void (*__scall_handler)(int /*code*/, int /*p1*/, int /*p2*/ + , int /*p3*/, int /*p4*/); + +/* + Function for registering an exception handler for the exception with + offset given by evba_offset. +*/ +void _register_exception_handler(__exception_handler handler, int evba_offset); + +/* + Function for registering a scall handler which can be a arbirary + function which uses r8-r12 for parameters. +*/ +void _register_scall_handler(__scall_handler handler); + +/* + Initialize exceptions. Must be called before registering exception handlers + and needed to enable exceptions. 'evba' is the pointer to the exception + vector. 'handler_table' is a pointer to an array where the pointers to + the exception handlers are stored. This array must be at least 0x104 bytes + and word aligned. +*/ +void init_exceptions(void *evba, void *handler_table); + +_END_STD_C + +#endif diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_interrupts.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_interrupts.h new file mode 100644 index 0000000000000000000000000000000000000000..76d81f7371b80e977fc08143346675a6141fed22 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_interrupts.h @@ -0,0 +1,82 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief NEWLIB_ADDONS interrupts include file for AVR32. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef __AVR32_NEWLIB_ADDONS_INTERRUPTS_H__ +#define __AVR32_NEWLIB_ADDONS_INTERRUPTS_H__ + +#include <_ansi.h> + +_BEGIN_STD_C + +#define INT_GRPS 64 +#define INT_LINES 32 +#define INTPR_BASE (__intc_base__ + 0x0000) +#define INTREQ_BASE (__intc_base__ + 64*4) +#define INTCAUSE_BASE (__intc_base__ + 2*64*4) + +//Register offsets +#define INTLEVEL 30 +#define AUTOVECTOR 0 +#define AUTOVECTOR_BITS 14 + +//Priorities +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 + + +typedef void (*__newlib_int_handler)(int /* int_grp*/, void */*user_handle*/); + +__newlib_int_handler register_interrupt(__newlib_int_handler handler, int int_grp, int line, int priority, + .../* void *user_handle*/); +void init_interrupts(); +void set_interrupts_base(void *base); + +_END_STD_C + +#endif diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_io.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_io.h new file mode 100644 index 0000000000000000000000000000000000000000..a725769fa806e6fa733a934372d39369cdcb423f --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_io.h @@ -0,0 +1,174 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief NEWLIB_ADDONS miscellaneous macros include file for AVR32. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef __AVR32_NEWLIB_ADDONS_IO_H__ +#define __AVR32_NEWLIB_ADDONS_IO_H__ + +#include <_ansi.h> + +_BEGIN_STD_C + +typedef char u8; +typedef unsigned int u32; + +#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define __raw_readb(a) (*(volatile unsigned char *)(a)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_readl(a) (*(volatile unsigned int *)(a)) + +/* As long as I/O is only performed in P4 (or possibly P3), we're safe */ +#define writeb(v,a) __raw_writeb(v,a) +#define writew(v,a) __raw_writew(v,a) +#define writel(v,a) __raw_writel(v,a) + +#define readb(a) __raw_readb(a) +#define readw(a) __raw_readw(a) +#define readl(a) __raw_readl(a) + +/* Memory segments when segmentation is enabled */ +#define P0SEG 0x00000000 +#define P1SEG 0x80000000 +#define P2SEG 0xa0000000 +#define P3SEG 0xc0000000 +#define P4SEG 0xe0000000 + +/* Returns the privileged segment base of a given address */ +#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000) + +/* Returns the physical address of a PnSEG (n=1,2) address */ +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) + +/* + * Map an address to a certain privileged segment + */ +#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG)) +#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG)) +#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG)) +#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG)) + + +#define cached(addr) P1SEGADDR(addr) +#define uncached(addr) P2SEGADDR(addr) +#define physaddr(addr) PHYSADDR(addr) + +#define BF(field, value) \ + ({ union { \ + struct { \ + unsigned : 32 - field ## _OFFSET - field ## _SIZE ; \ + unsigned long __val: field ## _SIZE ; \ + }; \ + unsigned long __ul; \ + } __tmp; \ + __tmp.__ul = 0; \ + __tmp.__val = value; \ + __tmp.__ul;}) + +#define BF_D(field, value) \ + ({ union { \ + struct { \ + unsigned long long : 64 - field ## _OFFSET - field ## _SIZE ; \ + unsigned long long __val: field ## _SIZE ; \ + }; \ + unsigned long long __ul; \ + } __tmp; \ + __tmp.__ul = 0; \ + __tmp.__val = value; \ + __tmp.__ul;}) + +#define BFINS(var, field, value) \ + { union {\ + struct { \ + unsigned : 32 - field ## _OFFSET - field ## _SIZE ; \ + unsigned long __val: field ## _SIZE ; \ + }; \ + unsigned long __ul; \ + } __tmp; \ + __tmp.__ul = var; \ + __tmp.__val = value; \ + var = __tmp.__ul;} + +#define BFEXT(var, field) \ + ({ union {\ + struct { \ + unsigned : 32 - field ## _OFFSET - field ## _SIZE ; \ + unsigned long __val: field ## _SIZE ; \ + }; \ + unsigned long __ul; \ + } __tmp; \ + __tmp.__ul = var; \ + __tmp.__val; }) + +#define BFINS_D(var, field, value) \ + { union {\ + struct { \ + unsigned long long : 64 - field ## _OFFSET - field ## _SIZE ; \ + unsigned long long __val: field ## _SIZE ; \ + }; \ + unsigned long long __ul; \ + } __tmp; \ + __tmp.__ul = var; \ + __tmp.__val = value; \ + var = __tmp.__ul;} + +#define BFEXT_D(var, field) \ + ({ union {\ + struct { \ + unsigned long long : 64 - field ## _OFFSET - field ## _SIZE ; \ + unsigned long long __val: field ## _SIZE ; \ + }; \ + unsigned long long __ul; \ + } __tmp; \ + __tmp.__ul = var; \ + __tmp.__val; }) + + +_END_STD_C + +#endif diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_usart.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_usart.h new file mode 100644 index 0000000000000000000000000000000000000000..6c4697d783ee0126464268549b6eba7083d352f4 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_usart.h @@ -0,0 +1,208 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief NEWLIB_ADDONS USART include file for AVR32. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef __AVR32_NEWLIB_ADDONS_USART_H__ +#define __AVR32_NEWLIB_ADDONS_USART_H__ + +#include <_ansi.h> + +#include "nlao_io.h" + +_BEGIN_STD_C + +struct usart3 { + volatile u32 us_cr; + volatile u32 us_mr; + volatile u32 us_ier; + volatile u32 us_idr; + volatile u32 us_imr; + volatile u32 us_csr; + volatile u32 us_rhr; + volatile u32 us_thr; + volatile u32 us_brgr; + volatile u32 us_rtor; + volatile u32 us_ttgr; + volatile u32 us_reserved[5]; + volatile u32 us_fidi; + volatile u32 us_ner; + volatile u32 us_xxr; + volatile u32 us_if; +}; + +/* Register offsets */ +#define US_CR 0x0000 +#define US_MR 0x0004 +#define US_IER 0x0008 +#define US_IDR 0x000c +#define US_IMR 0x0010 +#define US_CSR 0x0014 +#define US_RHR 0x0018 +#define US_THR 0x001c +#define US_BRGR 0x0020 +#define US_RTOR 0x0024 +#define US_TTGR 0x0028 + +#define US_FIDI 0x0040 +#define US_NER 0x0044 +#define US_XXR 0x0048 +#define US_IF 0x004c + +#define US_RPR 0x0100 +#define US_RCR 0x0104 +#define US_TPR 0x0108 +#define US_TCR 0x010c +#define US_RNPR 0x0110 +#define US_RNCR 0x0114 +#define US_TNPR 0x0118 +#define US_TNCR 0x011c +#define US_PTCR 0x0120 +#define US_PTSR 0x0124 + + + + +/* USART3 Control Register */ +#define US_CR_RSTRX (1 << 2) +#define US_CR_RSTTX (1 << 3) +#define US_CR_RXEN (1 << 4) +#define US_CR_RXDIS (1 << 5) +#define US_CR_TXEN (1 << 6) +#define US_CR_TXDIS (1 << 7) +#define US_CR_RSTSTA (1 << 8) +#define US_CR_STTBRK (1 << 9) +#define US_CR_STPBRK (1 << 10) + +#define US_CR_DTREN (1 << 16) +#define US_CR_DTRDIS (1 << 17) +#define US_CR_RTSEN (1 << 18) +#define US_CR_RTSDIS (1 << 19) + +/* USART3 Mode Register */ +#define US_MR_MODE (15 << 0) +#define US_MR_MODE_NORMAL ( 0 << 0) +#define US_MR_MODE_HWFLOW ( 2 << 0) +#define US_MR_CLKS ( 3 << 4) +#define US_MR_CLKS_CLOCK ( 0 << 4) +#define US_MR_CLKS_FDIV1 ( 1 << 4) +#define US_MR_CLKS_SLOW ( 2 << 4) +#define US_MR_CLKS_EXT ( 3 << 4) +#define US_MR_CHRL_5BITS ( 0 << 6) +#define US_MR_CHRL_6BITS ( 1 << 6) +#define US_MR_CHRL_7BITS ( 2 << 6) +#define US_MR_CHRL_8BITS ( 3 << 6) +#define US_MR_SYNC ( 1 << 8) +#define US_MR_PAR_EVEN ( 0 << 9) +#define US_MR_PAR_ODD ( 1 << 9) +#define US_MR_PAR_SPACE ( 2 << 9) +#define US_MR_PAR_MARK ( 3 << 9) +#define US_MR_PAR_NONE ( 4 << 9) +#define US_MR_PAR_MDROP ( 6 << 9) +#define US_MR_NBSTOP_1BIT ( 0 << 12) +#define US_MR_NBSTOP_1_5BIT ( 1 << 12) +#define US_MR_NBSTOP_2BITS ( 2 << 12) +#define US_MR_OVER ( 1 << 19) +#define US_MR_OVER_X16 ( 0 << 19) +#define US_MR_OVER_X8 ( 1 << 19) + +/* USART3 Channel Status Register */ +#define US_CSR_RXRDY (1 << 0) +#define US_CSR_TXRDY (1 << 1) +#define US_CSR_RXBRK (1 << 2) +#define US_CSR_ENDRX (1 << 3) +#define US_CSR_ENDTX (1 << 4) + + +#define US_CSR_OVRE (1 << 5) +#define US_CSR_FRAME (1 << 6) +#define US_CSR_PARE (1 << 7) + +#define US_CSR_TXEMPTY (1 << 9) + +#define US_CSR_TXBUFE (1 << 11) +#define US_CSR_RXBUFF (1 << 12) +#define US_CSR_RIIC (1 << 16) +#define US_CSR_DSRIC (1 << 17) +#define US_CSR_DCDIC (1 << 18) +#define US_CSR_CTSIC (1 << 19) +#define US_CSR_RI (1 << 20) +#define US_CSR_DSR (1 << 21) +#define US_CSR_DCD (1 << 22) +#define US_CSR_CTS (1 << 23) + +/* USART3 Baud Rate Generator Register */ +#define US_BRGR_CD_OFFSET 0 +#define US_BRGR_FP_OFFSET 16 + +#define US_BRGR_CD_SIZE 16 +#define US_BRGR_FP_SIZE 3 + +#define US_BRGR_CD (0xFFFF << 0) +#define US_BRGR_FP ( 7 << 16) + +/*USART3 PDC Transfer Control Register */ +#define US_PTCR_RXTEN (1 << 0) +#define US_PTCR_RXTDIS (1 << 1) +#define US_PTCR_TXTEN (1 << 8) +#define US_PTCR_TXTDIS (1 << 9) + +/*USART3 PDC Transfer Status Register */ +#define US_PTSR_RXTEN (1 << 0) +#define US_PTSR_TXTEN (1 << 8) + + +int usart_init(int baudrate); +void usart_putc(char c); +void usart_puts(const char *s); +int usart_getc(void); +int usart_tstc(void); +void usart_setbrg(int baudrate, int cpu_clock); +void set_usart_base(void *usart_base); + + +_END_STD_C + +#endif /* MERLIN_USART3_H */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/libnewlib_addons-at32ucr2-speed_opt.a b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/libnewlib_addons-at32ucr2-speed_opt.a new file mode 100644 index 0000000000000000000000000000000000000000..aa673eccdd47c07f3ab27c1726263ee9a8306143 Binary files /dev/null and b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/libnewlib_addons-at32ucr2-speed_opt.a differ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/GCC/link_uc3a0512.lds b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/GCC/link_uc3a0512.lds new file mode 100644 index 0000000000000000000000000000000000000000..59152ac0b97d2abed8242c54f9488420d6efcfcb --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/GCC/link_uc3a0512.lds @@ -0,0 +1,266 @@ +/****************************************************************************** + * AVR32 AT32UC3A0512 GNU LD script file. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: AVR32 AT32UC3A0512 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") + +OUTPUT_ARCH(avr32:uc) + +ENTRY(_start) + +MEMORY +{ + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00080000 + INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC + USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200 +} + +PHDRS +{ + FLASH PT_LOAD; + INTRAM_ALIGN PT_NULL; + INTRAM_AT_FLASH PT_LOAD; + INTRAM PT_NULL; + USERPAGE PT_LOAD; +} + +SECTIONS +{ + /* If this heap size is selected, all the INTRAM space from the end of the + data area to the beginning of the stack will be allocated for the heap. */ + __max_heap_size__ = -1; + + /* Use a default heap size if heap size was not defined. */ + __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__; + + /* Use a default stack size if stack size was not defined. */ + __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K; + + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x80000000); . = 0x80000000; + .interp : { *(.interp) } >FLASH AT>FLASH :FLASH + .reset : { *(.reset) } >FLASH AT>FLASH :FLASH + .hash : { *(.hash) } >FLASH AT>FLASH :FLASH + .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH + .dynstr : { *(.dynstr) } >FLASH AT>FLASH :FLASH + .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH + .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH + .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH + .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH + .rela.init : { *(.rela.init) } >FLASH AT>FLASH :FLASH + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH + .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rel.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH + .rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH + .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH + .rela.dtors : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH + .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH + .rela.got : { *(.rela.got) } >FLASH AT>FLASH :FLASH + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rel.plt : { *(.rel.plt) } >FLASH AT>FLASH :FLASH + .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH + .init : + { + KEEP (*(.init)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .plt : { *(.plt) } >FLASH AT>FLASH :FLASH + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .fini : + { + KEEP (*(.fini)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rodata1 : { *(.rodata1) } >FLASH AT>FLASH :FLASH + .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH + .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH + . = ORIGIN(INTRAM); + .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM_ALIGN + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + /* Thread Local Storage sections */ + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + PROVIDE (__preinit_array_start = ALIGN(32 / 8)); + .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (__fini_array_end = .); + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin*.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .dtors : + { + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .ramtext : { *(.ramtext .ramtext.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .ddalign : { . = ALIGN(8); } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .data : + { + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .data1 : { *(.data1) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .balign : { . = ALIGN(8); PROVIDE(_edata = .); } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (edata = .); + __bss_start = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(8); + } >INTRAM AT>INTRAM :INTRAM + . = ALIGN(8); + _end = .; + PROVIDE (end = .); + __heap_start__ = ALIGN(8); + .heap : + { + *(.heap) + . = (__heap_size__ == __max_heap_size__) ? + ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) : + __heap_size__; + } >INTRAM AT>INTRAM :INTRAM + __heap_end__ = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ : + { + _stack = .; + *(.stack) + . = __stack_size__; + _estack = .; + } >INTRAM AT>INTRAM :INTRAM + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/GCC/link_uc3a1256.lds b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/GCC/link_uc3a1256.lds new file mode 100644 index 0000000000000000000000000000000000000000..a5926d8bee47ac59e0c4ef4199fe709ea351d9a7 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/GCC/link_uc3a1256.lds @@ -0,0 +1,266 @@ +/****************************************************************************** + * AVR32 AT32UC3A1256 GNU LD script file. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: AVR32 AT32UC3A1256 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") + +OUTPUT_ARCH(avr32:uc) + +ENTRY(_start) + +MEMORY +{ + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000 + INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC + USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200 +} + +PHDRS +{ + FLASH PT_LOAD; + INTRAM_ALIGN PT_NULL; + INTRAM_AT_FLASH PT_LOAD; + INTRAM PT_NULL; + USERPAGE PT_LOAD; +} + +SECTIONS +{ + /* If this heap size is selected, all the INTRAM space from the end of the + data area to the beginning of the stack will be allocated for the heap. */ + __max_heap_size__ = -1; + + /* Use a default heap size if heap size was not defined. */ + __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__; + + /* Use a default stack size if stack size was not defined. */ + __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K; + + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x80000000); . = 0x80000000; + .interp : { *(.interp) } >FLASH AT>FLASH :FLASH + .reset : { *(.reset) } >FLASH AT>FLASH :FLASH + .hash : { *(.hash) } >FLASH AT>FLASH :FLASH + .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH + .dynstr : { *(.dynstr) } >FLASH AT>FLASH :FLASH + .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH + .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH + .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH + .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH + .rela.init : { *(.rela.init) } >FLASH AT>FLASH :FLASH + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH + .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rel.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH + .rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH + .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH + .rela.dtors : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH + .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH + .rela.got : { *(.rela.got) } >FLASH AT>FLASH :FLASH + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rel.plt : { *(.rel.plt) } >FLASH AT>FLASH :FLASH + .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH + .init : + { + KEEP (*(.init)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .plt : { *(.plt) } >FLASH AT>FLASH :FLASH + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .fini : + { + KEEP (*(.fini)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rodata1 : { *(.rodata1) } >FLASH AT>FLASH :FLASH + .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH + .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH + . = ORIGIN(INTRAM); + .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM_ALIGN + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + /* Thread Local Storage sections */ + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + PROVIDE (__preinit_array_start = ALIGN(32 / 8)); + .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (__fini_array_end = .); + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin*.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .dtors : + { + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .ramtext : { *(.ramtext .ramtext.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .ddalign : { . = ALIGN(8); } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .data : + { + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .data1 : { *(.data1) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .balign : { . = ALIGN(8); PROVIDE(_edata = .); } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (edata = .); + __bss_start = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(8); + } >INTRAM AT>INTRAM :INTRAM + . = ALIGN(8); + _end = .; + PROVIDE (end = .); + __heap_start__ = ALIGN(8); + .heap : + { + *(.heap) + . = (__heap_size__ == __max_heap_size__) ? + ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) : + __heap_size__; + } >INTRAM AT>INTRAM :INTRAM + __heap_end__ = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ : + { + _stack = .; + *(.stack) + . = __stack_size__; + _estack = .; + } >INTRAM AT>INTRAM :INTRAM + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/mrepeat.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/mrepeat.h new file mode 100644 index 0000000000000000000000000000000000000000..41163b6d916f9eecf05bd75c1db2d068090615a9 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/mrepeat.h @@ -0,0 +1,328 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Preprocessor macro repeating utils. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _MREPEAT_H_ +#define _MREPEAT_H_ + +#include "preprocessor.h" + + +//! Maximal number of repetitions supported by MREPEAT. +#define MREPEAT_LIMIT 256 + +/*! \brief Macro repeat. + * + * This macro represents a horizontal repetition construct. + * + * \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT. + * \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with + * the current repetition number and the auxiliary data argument. + * \param data Auxiliary data passed to macro. + * + * \return macro(0, data) macro(1, data) ... macro(count - 1, data) + */ +#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data) + +#define MREPEAT0( macro, data) +#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data) +#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data) +#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data) +#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data) +#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data) +#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data) +#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data) +#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data) +#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data) +#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data) +#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data) +#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data) +#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data) +#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data) +#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data) +#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data) +#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data) +#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data) +#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data) +#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data) +#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data) +#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data) +#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data) +#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data) +#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data) +#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data) +#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data) +#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data) +#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data) +#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data) +#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data) +#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data) +#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data) +#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data) +#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data) +#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data) +#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data) +#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data) +#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data) +#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data) +#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data) +#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data) +#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data) +#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data) +#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data) +#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data) +#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data) +#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data) +#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data) +#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data) +#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data) +#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data) +#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data) +#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data) +#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data) +#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data) +#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data) +#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data) +#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data) +#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data) +#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data) +#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data) +#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data) +#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data) +#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data) +#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data) +#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data) +#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data) +#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data) +#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data) +#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data) +#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data) +#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data) +#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data) +#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data) +#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data) +#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data) +#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data) +#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data) +#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data) +#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data) +#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data) +#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data) +#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data) +#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data) +#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data) +#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data) +#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data) +#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data) +#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data) +#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data) +#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data) +#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data) +#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data) +#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data) +#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data) +#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data) +#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data) +#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data) +#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data) +#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data) +#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data) +#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data) +#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data) +#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data) +#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data) +#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data) +#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data) +#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data) +#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data) +#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data) +#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data) +#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data) +#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data) +#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data) +#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data) +#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data) +#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data) +#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data) +#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data) +#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data) +#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data) +#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data) +#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data) +#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data) +#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data) +#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data) +#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data) +#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data) +#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data) +#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data) +#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data) +#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data) +#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data) +#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data) +#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data) +#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data) +#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data) +#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data) +#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data) +#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data) +#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data) +#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data) +#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data) +#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data) +#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data) +#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data) +#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data) +#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data) +#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data) +#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data) +#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data) +#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data) +#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data) +#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data) +#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data) +#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data) +#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data) +#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data) +#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data) +#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data) +#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data) +#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data) +#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data) +#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data) +#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data) +#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data) +#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data) +#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data) +#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data) +#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data) +#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data) +#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data) +#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data) +#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data) +#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data) +#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data) +#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data) +#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data) +#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data) +#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data) +#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data) +#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data) +#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data) +#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data) +#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data) +#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data) +#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data) +#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data) +#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data) +#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data) +#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data) +#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data) +#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data) +#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data) +#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data) +#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data) +#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data) +#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data) +#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data) +#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data) +#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data) +#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data) +#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data) +#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data) +#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data) +#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data) +#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data) +#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data) +#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data) +#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data) +#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data) +#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data) +#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data) +#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data) +#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data) +#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data) +#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data) +#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data) +#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data) +#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data) +#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data) +#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data) +#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data) +#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data) +#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data) +#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data) +#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data) +#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data) +#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data) +#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data) +#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data) +#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data) +#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data) +#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data) +#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data) +#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data) +#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data) +#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data) +#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data) +#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data) +#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data) +#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data) +#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data) +#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data) +#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data) +#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data) +#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data) +#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data) +#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data) +#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data) +#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data) +#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data) +#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data) +#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data) +#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data) + + +#endif // _MREPEAT_H_ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/preprocessor.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/preprocessor.h new file mode 100644 index 0000000000000000000000000000000000000000..5b996ba11f24b06c93d9a8652eccae6109c20dbc --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/preprocessor.h @@ -0,0 +1,55 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Preprocessor utils. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _PREPROCESSOR_H_ +#define _PREPROCESSOR_H_ + +#include "tpaste.h" +#include "stringz.h" +#include "mrepeat.h" + + +#endif // _PREPROCESSOR_H_ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/stringz.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/stringz.h new file mode 100644 index 0000000000000000000000000000000000000000..3528ea0dabbf5cadad47f50df597c1d14ddb9e62 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/stringz.h @@ -0,0 +1,75 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Preprocessor stringizing utils. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _STRINGZ_H_ +#define _STRINGZ_H_ + + +/*! \brief Stringize. + * + * Stringize a preprocessing token, this token being allowed to be \#defined. + * + * May be used only within macros with the token passed as an argument if the token is \#defined. + * + * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN) + * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to + * writing "A0". + */ +#define STRINGZ(x) #x + +/*! \brief Absolute stringize. + * + * Stringize a preprocessing token, this token being allowed to be \#defined. + * + * No restriction of use if the token is \#defined. + * + * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is + * equivalent to writing "A0". + */ +#define ASTRINGZ(x) STRINGZ(x) + + +#endif // _STRINGZ_H_ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/tpaste.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/tpaste.h new file mode 100644 index 0000000000000000000000000000000000000000..a5d7beeaa80594c904d2d12e9445139d0b29ee02 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/tpaste.h @@ -0,0 +1,95 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Preprocessor token pasting utils. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _TPASTE_H_ +#define _TPASTE_H_ + + +/*! \name Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * May be used only within macros with the tokens passed as arguments if the tokens are \#defined. + * + * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by + * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is + * equivalent to writing U32. + */ +//! @{ +#define TPASTE2( a, b) a##b +#define TPASTE3( a, b, c) a##b##c +#define TPASTE4( a, b, c, d) a##b##c##d +#define TPASTE5( a, b, c, d, e) a##b##c##d##e +#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f +#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g +#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h +#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i +#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j +//! @} + +/*! \name Absolute Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * No restriction of use if the tokens are \#defined. + * + * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined + * as 32 is equivalent to writing U32. + */ +//! @{ +#define ATPASTE2( a, b) TPASTE2( a, b) +#define ATPASTE3( a, b, c) TPASTE3( a, b, c) +#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d) +#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e) +#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f) +#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g) +#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h) +#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i) +#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j) +//! @} + + +#endif // _TPASTE_H_ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/STARTUP_FILES/GCC/crt0.x b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/STARTUP_FILES/GCC/crt0.x new file mode 100644 index 0000000000000000000000000000000000000000..23b658b9846186bd136acdde585cfac1d3ab87f5 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/STARTUP_FILES/GCC/crt0.x @@ -0,0 +1,121 @@ +/* This file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AVR32UC C runtime startup file. + * + * This file has been built from the Newlib crt0.S. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32UC devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include + + +//! @{ +//! \verbatim + + + // This must be linked @ 0x80000000 if it is to be run upon reset. + .section .reset, "ax", @progbits + + + .global _start + .type _start, @function +_start: + // Jump to the C runtime startup routine. + lda.w pc, _stext + + + // _stext is placed outside the .reset section so that the program entry point + // can be changed without affecting the C runtime startup. + .section .text._stext, "ax", @progbits + + + .global _stext + .type _stext, @function +_stext: + // Set initial stack pointer. + lda.w sp, _estack + + // Set up EVBA so interrupts can be enabled. + lda.w r0, _evba + mtsr AVR32_EVBA, r0 + + // Enable the exception processing. + csrf AVR32_SR_EM_OFFSET + + // Load initialized data having a global lifetime from the data LMA. + lda.w r0, _data + lda.w r1, _edata + cp r0, r1 + brhs idata_load_loop_end + lda.w r2, _data_lma +idata_load_loop: + ld.d r4, r2++ + st.d r0++, r4 + cp r0, r1 + brlo idata_load_loop +idata_load_loop_end: + + // Clear uninitialized data having a global lifetime in the blank static storage section. + lda.w r0, __bss_start + lda.w r1, _end + cp r0, r1 + brhs udata_clear_loop_end + mov r2, 0 + mov r3, 0 +udata_clear_loop: + st.d r0++, r2 + cp r0, r1 + brlo udata_clear_loop +udata_clear_loop_end: + +#ifdef CONFIG_FRAME_POINTER + // Safety: Set the default "return" @ to the exit routine address. + lda.w lr, exit +#endif + + // Start the show. + lda.w pc, main + + +//! \endverbatim +//! @} diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/compiler.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/compiler.h new file mode 100644 index 0000000000000000000000000000000000000000..885be7fb98a89c93698d8d9f707b8f3bd8e09e84 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/compiler.h @@ -0,0 +1,1145 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Compiler file for AVR32. + * + * This file defines commonly used types and macros. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _COMPILER_H_ +#define _COMPILER_H_ + +#if ((defined __GNUC__) && (defined __AVR32__)) || (defined __ICCAVR32__ || defined __AAVR32__) +# include +#endif +#if (defined __ICCAVR32__) +# include +#endif +#include "preprocessor.h" + +#include "parts.h" + + +//_____ D E C L A R A T I O N S ____________________________________________ + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. + +#include +#include + + +#if (defined __ICCAVR32__) + +/*! \name Compiler Keywords + * + * Port of some keywords from GNU GCC for AVR32 to IAR Embedded Workbench for Atmel AVR32. + */ +//! @{ +#define __asm__ asm +#define __inline__ inline +#define __volatile__ +//! @} + +#endif + + +/*! \name Usual Types + */ +//! @{ +typedef unsigned char Bool; //!< Boolean. +#ifndef __cplusplus +#if !defined(__bool_true_false_are_defined) +typedef unsigned char bool; //!< Boolean. +#endif +#endif +typedef signed char S8 ; //!< 8-bit signed integer. +typedef unsigned char U8 ; //!< 8-bit unsigned integer. +typedef signed short int S16; //!< 16-bit signed integer. +typedef unsigned short int U16; //!< 16-bit unsigned integer. +typedef signed long int S32; //!< 32-bit signed integer. +typedef unsigned long int U32; //!< 32-bit unsigned integer. +typedef signed long long int S64; //!< 64-bit signed integer. +typedef unsigned long long int U64; //!< 64-bit unsigned integer. +typedef float F32; //!< 32-bit floating-point number. +typedef double F64; //!< 64-bit floating-point number. +//! @} + + +/*! \name Status Types + */ +//! @{ +typedef Bool Status_bool_t; //!< Boolean status. +typedef U8 Status_t; //!< 8-bit-coded status. +//! @} + + +/*! \name Aliasing Aggregate Types + */ +//! @{ + +//! 16-bit union. +typedef union +{ + S16 s16 ; + U16 u16 ; + S8 s8 [2]; + U8 u8 [2]; +} Union16; + +//! 32-bit union. +typedef union +{ + S32 s32 ; + U32 u32 ; + S16 s16[2]; + U16 u16[2]; + S8 s8 [4]; + U8 u8 [4]; +} Union32; + +//! 64-bit union. +typedef union +{ + S64 s64 ; + U64 u64 ; + S32 s32[2]; + U32 u32[2]; + S16 s16[4]; + U16 u16[4]; + S8 s8 [8]; + U8 u8 [8]; +} Union64; + +//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + S64 *s64ptr; + U64 *u64ptr; + S32 *s32ptr; + U32 *u32ptr; + S16 *s16ptr; + U16 *u16ptr; + S8 *s8ptr ; + U8 *u8ptr ; +} UnionPtr; + +//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + volatile S64 *s64ptr; + volatile U64 *u64ptr; + volatile S32 *s32ptr; + volatile U32 *u32ptr; + volatile S16 *s16ptr; + volatile U16 *u16ptr; + volatile S8 *s8ptr ; + volatile U8 *u8ptr ; +} UnionVPtr; + +//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + const S64 *s64ptr; + const U64 *u64ptr; + const S32 *s32ptr; + const U32 *u32ptr; + const S16 *s16ptr; + const U16 *u16ptr; + const S8 *s8ptr ; + const U8 *u8ptr ; +} UnionCPtr; + +//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + const volatile S64 *s64ptr; + const volatile U64 *u64ptr; + const volatile S32 *s32ptr; + const volatile U32 *u32ptr; + const volatile S16 *s16ptr; + const volatile U16 *u16ptr; + const volatile S8 *s8ptr ; + const volatile U8 *u8ptr ; +} UnionCVPtr; + +//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + S64 *s64ptr; + U64 *u64ptr; + S32 *s32ptr; + U32 *u32ptr; + S16 *s16ptr; + U16 *u16ptr; + S8 *s8ptr ; + U8 *u8ptr ; +} StructPtr; + +//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + volatile S64 *s64ptr; + volatile U64 *u64ptr; + volatile S32 *s32ptr; + volatile U32 *u32ptr; + volatile S16 *s16ptr; + volatile U16 *u16ptr; + volatile S8 *s8ptr ; + volatile U8 *u8ptr ; +} StructVPtr; + +//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + const S64 *s64ptr; + const U64 *u64ptr; + const S32 *s32ptr; + const U32 *u32ptr; + const S16 *s16ptr; + const U16 *u16ptr; + const S8 *s8ptr ; + const U8 *u8ptr ; +} StructCPtr; + +//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + const volatile S64 *s64ptr; + const volatile U64 *u64ptr; + const volatile S32 *s32ptr; + const volatile U32 *u32ptr; + const volatile S16 *s16ptr; + const volatile U16 *u16ptr; + const volatile S8 *s8ptr ; + const volatile U8 *u8ptr ; +} StructCVPtr; + +//! @} + +#endif // __AVR32_ABI_COMPILER__ + + +//_____ M A C R O S ________________________________________________________ + +/*! \name Usual Constants + */ +//! @{ +#define DISABLE 0 +#define ENABLE 1 +#define DISABLED 0 +#define ENABLED 1 +#define OFF 0 +#define ON 1 +#define FALSE 0 +#define TRUE 1 +#ifndef __cplusplus +#if !defined(__bool_true_false_are_defined) +#define false FALSE +#define true TRUE +#endif +#endif +#define KO 0 +#define OK 1 +#define PASS 0 +#define FAIL 1 +#define LOW 0 +#define HIGH 1 +#define CLR 0 +#define SET 1 +//! @} + + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. + +/*! \name Bit-Field Handling + */ +//! @{ + +/*! \brief Reads the bits of a value specified by a given bit-mask. + * + * \param value Value to read bits from. + * \param mask Bit-mask indicating bits to read. + * + * \return Read bits. + */ +#define Rd_bits( value, mask) ((value) & (mask)) + +/*! \brief Writes the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue to write bits to. + * \param mask Bit-mask indicating bits to write. + * \param bits Bits to write. + * + * \return Resulting value with written bits. + */ +#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\ + ((bits ) & (mask))) + +/*! \brief Tests the bits of a value specified by a given bit-mask. + * + * \param value Value of which to test bits. + * \param mask Bit-mask indicating bits to test. + * + * \return \c 1 if at least one of the tested bits is set, else \c 0. + */ +#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0) + +/*! \brief Clears the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to clear bits. + * \param mask Bit-mask indicating bits to clear. + * + * \return Resulting value with cleared bits. + */ +#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask)) + +/*! \brief Sets the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to set bits. + * \param mask Bit-mask indicating bits to set. + * + * \return Resulting value with set bits. + */ +#define Set_bits(lvalue, mask) ((lvalue) |= (mask)) + +/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to toggle bits. + * \param mask Bit-mask indicating bits to toggle. + * + * \return Resulting value with toggled bits. + */ +#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask)) + +/*! \brief Reads the bit-field of a value specified by a given bit-mask. + * + * \param value Value to read a bit-field from. + * \param mask Bit-mask indicating the bit-field to read. + * + * \return Read bit-field. + */ +#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask)) + +/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue to write a bit-field to. + * \param mask Bit-mask indicating the bit-field to write. + * \param bitfield Bit-field to write. + * + * \return Resulting value with written bit-field. + */ +#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask))) + +//! @} + + +/*! \brief This macro is used to test fatal errors. + * + * The macro tests if the expression is FALSE. If it is, a fatal error is + * detected and the application hangs up. + * + * \param expr Expression to evaluate and supposed to be nonzero. + */ +#ifdef _ASSERT_ENABLE_ + #define Assert(expr) \ + {\ + if (!(expr)) while (TRUE);\ + } +#else + #define Assert(expr) +#endif + + +/*! \name Zero-Bit Counting + * + * Under AVR32-GCC, __builtin_clz and __builtin_ctz behave like macros when + * applied to constant expressions (values known at compile time), so they are + * more optimized than the use of the corresponding assembly instructions and + * they can be used as constant expressions e.g. to initialize objects having + * static storage duration, and like the corresponding assembly instructions + * when applied to non-constant expressions (values unknown at compile time), so + * they are more optimized than an assembly periphrasis. Hence, clz and ctz + * ensure a possible and optimized behavior for both constant and non-constant + * expressions. + */ +//! @{ + +/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer. + * + * \param u Value of which to count the leading zero bits. + * + * \return The count of leading zero bits in \a u. + */ +#if (defined __GNUC__) + #define clz(u) __builtin_clz(u) +#elif (defined __ICCAVR32__) + #define clz(u) __count_leading_zeros(u) +#endif + +/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#if (defined __GNUC__) + #define ctz(u) __builtin_ctz(u) +#elif (defined __ICCAVR32__) + #define ctz(u) __count_trailing_zeros(u) +#endif + +//! @} + + +/*! \name Bit Reversing + */ +//! @{ + +/*! \brief Reverses the bits of \a u8. + * + * \param u8 U8 of which to reverse the bits. + * + * \return Value resulting from \a u8 with reversed bits. + */ +#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24)) + +/*! \brief Reverses the bits of \a u16. + * + * \param u16 U16 of which to reverse the bits. + * + * \return Value resulting from \a u16 with reversed bits. + */ +#define bit_reverse16(u16) ((U16)(bit_reverse32((U16)(u16)) >> 16)) + +/*! \brief Reverses the bits of \a u32. + * + * \param u32 U32 of which to reverse the bits. + * + * \return Value resulting from \a u32 with reversed bits. + */ +#if (defined __GNUC__) + #define bit_reverse32(u32) \ + (\ + {\ + unsigned int __value = (U32)(u32);\ + __asm__ ("brev\t%0" : "+r" (__value) : : "cc");\ + (U32)__value;\ + }\ + ) +#elif (defined __ICCAVR32__) + #define bit_reverse32(u32) ((U32)__bit_reverse((U32)(u32))) +#endif + +/*! \brief Reverses the bits of \a u64. + * + * \param u64 U64 of which to reverse the bits. + * + * \return Value resulting from \a u64 with reversed bits. + */ +#define bit_reverse64(u64) ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) |\ + ((U64)bit_reverse32((U64)(u64)) << 32))) + +//! @} + + +/*! \name Alignment + */ +//! @{ + +/*! \brief Tests alignment of the number \a val with the \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0. + */ +#define Test_align(val, n ) (!Tst_bits( val, (n) - 1 ) ) + +/*! \brief Gets alignment of the number \a val with respect to the \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Alignment of the number \a val with respect to the \a n boundary. + */ +#define Get_align( val, n ) ( Rd_bits( val, (n) - 1 ) ) + +/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary. + * + * \param lval Input/output lvalue. + * \param n Boundary. + * \param alg Alignment. + * + * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary. + */ +#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) ) + +/*! \brief Aligns the number \a val with the upper \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Value resulting from the number \a val aligned with the upper \a n boundary. + */ +#define Align_up( val, n ) (((val) + ((n) - 1)) & ~((n) - 1)) + +/*! \brief Aligns the number \a val with the lower \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Value resulting from the number \a val aligned with the lower \a n boundary. + */ +#define Align_down(val, n ) ( (val) & ~((n) - 1)) + +//! @} + + +/*! \name Mathematics + * + * The same considerations as for clz and ctz apply here but AVR32-GCC does not + * provide built-in functions to access the assembly instructions abs, min and + * max and it does not produce them by itself in most cases, so two sets of + * macros are defined here: + * - Abs, Min and Max to apply to constant expressions (values known at + * compile time); + * - abs, min and max to apply to non-constant expressions (values unknown at + * compile time). + */ +//! @{ + +/*! \brief Takes the absolute value of \a a. + * + * \param a Input value. + * + * \return Absolute value of \a a. + * + * \note More optimized if only used with values known at compile time. + */ +#define Abs(a) (((a) < 0 ) ? -(a) : (a)) + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Min(a, b) (((a) < (b)) ? (a) : (b)) + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Max(a, b) (((a) > (b)) ? (a) : (b)) + +/*! \brief Takes the absolute value of \a a. + * + * \param a Input value. + * + * \return Absolute value of \a a. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) + #define abs(a) \ + (\ + {\ + int __value = (a);\ + __asm__ ("abs\t%0" : "+r" (__value) : : "cc");\ + __value;\ + }\ + ) +#elif (defined __ICCAVR32__) + #define abs(a) Abs(a) +#endif + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) + #define min(a, b) \ + (\ + {\ + int __value, __arg_a = (a), __arg_b = (b);\ + __asm__ ("min\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\ + __value;\ + }\ + ) +#elif (defined __ICCAVR32__) + #define min(a, b) __min(a, b) +#endif + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) + #define max(a, b) \ + (\ + {\ + int __value, __arg_a = (a), __arg_b = (b);\ + __asm__ ("max\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\ + __value;\ + }\ + ) +#elif (defined __ICCAVR32__) + #define max(a, b) __max(a, b) +#endif + +//! @} + + +/*! \brief Calls the routine at address \a addr. + * + * It generates a long call opcode. + * + * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if + * it is invoked from the CPU supervisor mode. + * + * \param addr Address of the routine to call. + * + * \note It may be used as a long jump opcode in some special cases. + */ +#define Long_call(addr) ((*(void (*)(void))(addr))()) + +/*! \brief Resets the CPU by software. + * + * \warning It shall not be called from the CPU application mode. + */ +#if (defined __GNUC__) + #define Reset_CPU() \ + (\ + {\ + __asm__ __volatile__ (\ + "lddpc r9, 3f\n\t"\ + "mfsr r8, %[SR]\n\t"\ + "bfextu r8, r8, %[SR_M_OFFSET], %[SR_M_SIZE]\n\t"\ + "cp.w r8, 0b001\n\t"\ + "breq 0f\n\t"\ + "sub r8, pc, $ - 1f\n\t"\ + "pushm r8-r9\n\t"\ + "rete\n"\ + "0:\n\t"\ + "mtsr %[SR], r9\n"\ + "1:\n\t"\ + "mov r0, 0\n\t"\ + "mov r1, 0\n\t"\ + "mov r2, 0\n\t"\ + "mov r3, 0\n\t"\ + "mov r4, 0\n\t"\ + "mov r5, 0\n\t"\ + "mov r6, 0\n\t"\ + "mov r7, 0\n\t"\ + "mov r8, 0\n\t"\ + "mov r9, 0\n\t"\ + "mov r10, 0\n\t"\ + "mov r11, 0\n\t"\ + "mov r12, 0\n\t"\ + "mov sp, 0\n\t"\ + "stdsp sp[0], sp\n\t"\ + "ldmts sp, sp\n\t"\ + "mov lr, 0\n\t"\ + "lddpc pc, 2f\n\t"\ + ".balign 4\n"\ + "2:\n\t"\ + ".word _start\n"\ + "3:\n\t"\ + ".word %[RESET_SR]"\ + :\ + : [SR] "i" (AVR32_SR),\ + [SR_M_OFFSET] "i" (AVR32_SR_M_OFFSET),\ + [SR_M_SIZE] "i" (AVR32_SR_M_SIZE),\ + [RESET_SR] "i" (AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))\ + );\ + }\ + ) +#elif (defined __ICCAVR32__) + #define Reset_CPU() \ + {\ + extern void *volatile __program_start;\ + __asm__ __volatile__ (\ + "mov r7, LWRD(__program_start)\n\t"\ + "orh r7, HWRD(__program_start)\n\t"\ + "mov r9, LWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))")\n\t"\ + "orh r9, HWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))")\n\t"\ + "mfsr r8, "ASTRINGZ(AVR32_SR)"\n\t"\ + "bfextu r8, r8, "ASTRINGZ(AVR32_SR_M_OFFSET)", "ASTRINGZ(AVR32_SR_M_SIZE)"\n\t"\ + "cp.w r8, 001b\n\t"\ + "breq $ + 10\n\t"\ + "sub r8, pc, -12\n\t"\ + "pushm r8-r9\n\t"\ + "rete\n\t"\ + "mtsr "ASTRINGZ(AVR32_SR)", r9\n\t"\ + "mov r0, 0\n\t"\ + "mov r1, 0\n\t"\ + "mov r2, 0\n\t"\ + "mov r3, 0\n\t"\ + "mov r4, 0\n\t"\ + "mov r5, 0\n\t"\ + "mov r6, 0\n\t"\ + "st.w r0[4], r7\n\t"\ + "mov r7, 0\n\t"\ + "mov r8, 0\n\t"\ + "mov r9, 0\n\t"\ + "mov r10, 0\n\t"\ + "mov r11, 0\n\t"\ + "mov r12, 0\n\t"\ + "mov sp, 0\n\t"\ + "stdsp sp[0], sp\n\t"\ + "ldmts sp, sp\n\t"\ + "mov lr, 0\n\t"\ + "ld.w pc, lr[4]"\ + );\ + __program_start;\ + } +#endif + + +/*! \name System Register Access + */ +//! @{ + +/*! \brief Gets the value of the \a sysreg system register. + * + * \param sysreg Address of the system register of which to get the value. + * + * \return Value of the \a sysreg system register. + */ +#if (defined __GNUC__) + #define Get_system_register(sysreg) __builtin_mfsr(sysreg) +#elif (defined __ICCAVR32__) + #define Get_system_register(sysreg) __get_system_register(sysreg) +#endif + +/*! \brief Sets the value of the \a sysreg system register to \a value. + * + * \param sysreg Address of the system register of which to set the value. + * \param value Value to set the \a sysreg system register to. + */ +#if (defined __GNUC__) + #define Set_system_register(sysreg, value) __builtin_mtsr(sysreg, value) +#elif (defined __ICCAVR32__) + #define Set_system_register(sysreg, value) __set_system_register(sysreg, value) +#endif + +//! @} + + +/*! \name CPU Status Register Access + */ +//! @{ + +/*! \brief Tells whether exceptions are globally enabled. + * + * \return \c 1 if exceptions are globally enabled, else \c 0. + */ +#define Is_global_exception_enabled() (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_EM_MASK)) + +/*! \brief Disables exceptions globally. + */ +#if (defined __GNUC__) + #define Disable_global_exception() ({__asm__ __volatile__ ("ssrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));}) +#elif (defined __ICCAVR32__) + #define Disable_global_exception() (__set_status_flag(AVR32_SR_EM_OFFSET)) +#endif + +/*! \brief Enables exceptions globally. + */ +#if (defined __GNUC__) + #define Enable_global_exception() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));}) +#elif (defined __ICCAVR32__) + #define Enable_global_exception() (__clear_status_flag(AVR32_SR_EM_OFFSET)) +#endif + +/*! \brief Tells whether interrupts are globally enabled. + * + * \return \c 1 if interrupts are globally enabled, else \c 0. + */ +#define Is_global_interrupt_enabled() (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_GM_MASK)) + +/*! \brief Disables interrupts globally. + */ +#if (defined __GNUC__) + #define Disable_global_interrupt() ({__asm__ __volatile__ ("ssrf\t%0" : : "i" (AVR32_SR_GM_OFFSET));}) +#elif (defined __ICCAVR32__) + #define Disable_global_interrupt() (__disable_interrupt()) +#endif + +/*! \brief Enables interrupts globally. + */ +#if (defined __GNUC__) + #define Enable_global_interrupt() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_GM_OFFSET));}) +#elif (defined __ICCAVR32__) + #define Enable_global_interrupt() (__enable_interrupt()) +#endif + +/*! \brief Tells whether interrupt level \a int_level is enabled. + * + * \param int_level Interrupt level (0 to 3). + * + * \return \c 1 if interrupt level \a int_level is enabled, else \c 0. + */ +#define Is_interrupt_level_enabled(int_level) (!Tst_bits(Get_system_register(AVR32_SR), TPASTE3(AVR32_SR_I, int_level, M_MASK))) + +/*! \brief Disables interrupt level \a int_level. + * + * \param int_level Interrupt level to disable (0 to 3). + */ +#if (defined __GNUC__) + #define Disable_interrupt_level(int_level) ({__asm__ __volatile__ ("ssrf\t%0" : : "i" (TPASTE3(AVR32_SR_I, int_level, M_OFFSET)));}) +#elif (defined __ICCAVR32__) + #define Disable_interrupt_level(int_level) (__set_status_flag(TPASTE3(AVR32_SR_I, int_level, M_OFFSET))) +#endif + +/*! \brief Enables interrupt level \a int_level. + * + * \param int_level Interrupt level to enable (0 to 3). + */ +#if (defined __GNUC__) + #define Enable_interrupt_level(int_level) ({__asm__ __volatile__ ("csrf\t%0" : : "i" (TPASTE3(AVR32_SR_I, int_level, M_OFFSET)));}) +#elif (defined __ICCAVR32__) + #define Enable_interrupt_level(int_level) (__clear_status_flag(TPASTE3(AVR32_SR_I, int_level, M_OFFSET))) +#endif + +/*! \brief Protects subsequent code from interrupts. + */ +#define AVR32_ENTER_CRITICAL_REGION( ) \ + { \ + Bool global_interrupt_enabled = Is_global_interrupt_enabled(); \ + Disable_global_interrupt(); // Disable the appropriate interrupts. + +/*! \brief This macro must always be used in conjunction with AVR32_ENTER_CRITICAL_REGION + * so that interrupts are enabled again. + */ +#define AVR32_LEAVE_CRITICAL_REGION( ) \ + if (global_interrupt_enabled) Enable_global_interrupt(); \ + } + +//! @} + + +/*! \name Debug Register Access + */ +//! @{ + +/*! \brief Gets the value of the \a dbgreg debug register. + * + * \param dbgreg Address of the debug register of which to get the value. + * + * \return Value of the \a dbgreg debug register. + */ +#if (defined __GNUC__) + #define Get_debug_register(dbgreg) __builtin_mfdr(dbgreg) +#elif (defined __ICCAVR32__) + #define Get_debug_register(dbgreg) __get_debug_register(dbgreg) +#endif + +/*! \brief Sets the value of the \a dbgreg debug register to \a value. + * + * \param dbgreg Address of the debug register of which to set the value. + * \param value Value to set the \a dbgreg debug register to. + */ +#if (defined __GNUC__) + #define Set_debug_register(dbgreg, value) __builtin_mtdr(dbgreg, value) +#elif (defined __ICCAVR32__) + #define Set_debug_register(dbgreg, value) __set_debug_register(dbgreg, value) +#endif + +//! @} + +#endif // __AVR32_ABI_COMPILER__ + + +//! Boolean evaluating MCU little endianism. +#if ((defined __GNUC__) && (defined __AVR32__)) || ((defined __ICCAVR32__) || (defined __AAVR32__)) + #define LITTLE_ENDIAN_MCU FALSE +#else + #error If you are here, you should check what is exactly the processor you are using... + #define LITTLE_ENDIAN_MCU FALSE +#endif + +// Check that MCU endianism is correctly defined. +#ifndef LITTLE_ENDIAN_MCU + #error YOU MUST define the MCU endianism with LITTLE_ENDIAN_MCU: either FALSE or TRUE +#endif + +//! Boolean evaluating MCU big endianism. +#define BIG_ENDIAN_MCU (!LITTLE_ENDIAN_MCU) + + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. + +/*! \name MCU Endianism Handling + */ +//! @{ + +#if (LITTLE_ENDIAN_MCU==TRUE) + #define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16. + #define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16. + + #define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32. + #define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32. + #define LSB0W(u32) (((U8 *)&(u32))[0]) //!< Least significant byte of 1st rank of \a u32. + #define LSB1W(u32) (((U8 *)&(u32))[1]) //!< Least significant byte of 2nd rank of \a u32. + #define LSB2W(u32) (((U8 *)&(u32))[2]) //!< Least significant byte of 3rd rank of \a u32. + #define LSB3W(u32) (((U8 *)&(u32))[3]) //!< Least significant byte of 4th rank of \a u32. + #define MSB3W(u32) LSB0W(u32) //!< Most significant byte of 4th rank of \a u32. + #define MSB2W(u32) LSB1W(u32) //!< Most significant byte of 3rd rank of \a u32. + #define MSB1W(u32) LSB2W(u32) //!< Most significant byte of 2nd rank of \a u32. + #define MSB0W(u32) LSB3W(u32) //!< Most significant byte of 1st rank of \a u32. + + #define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64. + #define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64. + #define LSH0(u64) (((U16 *)&(u64))[0]) //!< Least significant half-word of 1st rank of \a u64. + #define LSH1(u64) (((U16 *)&(u64))[1]) //!< Least significant half-word of 2nd rank of \a u64. + #define LSH2(u64) (((U16 *)&(u64))[2]) //!< Least significant half-word of 3rd rank of \a u64. + #define LSH3(u64) (((U16 *)&(u64))[3]) //!< Least significant half-word of 4th rank of \a u64. + #define MSH3(u64) LSH0(u64) //!< Most significant half-word of 4th rank of \a u64. + #define MSH2(u64) LSH1(u64) //!< Most significant half-word of 3rd rank of \a u64. + #define MSH1(u64) LSH2(u64) //!< Most significant half-word of 2nd rank of \a u64. + #define MSH0(u64) LSH3(u64) //!< Most significant half-word of 1st rank of \a u64. + #define LSB0D(u64) (((U8 *)&(u64))[0]) //!< Least significant byte of 1st rank of \a u64. + #define LSB1D(u64) (((U8 *)&(u64))[1]) //!< Least significant byte of 2nd rank of \a u64. + #define LSB2D(u64) (((U8 *)&(u64))[2]) //!< Least significant byte of 3rd rank of \a u64. + #define LSB3D(u64) (((U8 *)&(u64))[3]) //!< Least significant byte of 4th rank of \a u64. + #define LSB4D(u64) (((U8 *)&(u64))[4]) //!< Least significant byte of 5th rank of \a u64. + #define LSB5D(u64) (((U8 *)&(u64))[5]) //!< Least significant byte of 6th rank of \a u64. + #define LSB6D(u64) (((U8 *)&(u64))[6]) //!< Least significant byte of 7th rank of \a u64. + #define LSB7D(u64) (((U8 *)&(u64))[7]) //!< Least significant byte of 8th rank of \a u64. + #define MSB7D(u64) LSB0D(u64) //!< Most significant byte of 8th rank of \a u64. + #define MSB6D(u64) LSB1D(u64) //!< Most significant byte of 7th rank of \a u64. + #define MSB5D(u64) LSB2D(u64) //!< Most significant byte of 6th rank of \a u64. + #define MSB4D(u64) LSB3D(u64) //!< Most significant byte of 5th rank of \a u64. + #define MSB3D(u64) LSB4D(u64) //!< Most significant byte of 4th rank of \a u64. + #define MSB2D(u64) LSB5D(u64) //!< Most significant byte of 3rd rank of \a u64. + #define MSB1D(u64) LSB6D(u64) //!< Most significant byte of 2nd rank of \a u64. + #define MSB0D(u64) LSB7D(u64) //!< Most significant byte of 1st rank of \a u64. + +#elif (BIG_ENDIAN_MCU==TRUE) + #define MSB(u16) (((U8 *)&(u16))[0]) //!< Most significant byte of \a u16. + #define LSB(u16) (((U8 *)&(u16))[1]) //!< Least significant byte of \a u16. + + #define MSH(u32) (((U16 *)&(u32))[0]) //!< Most significant half-word of \a u32. + #define LSH(u32) (((U16 *)&(u32))[1]) //!< Least significant half-word of \a u32. + #define MSB0W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 1st rank of \a u32. + #define MSB1W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 2nd rank of \a u32. + #define MSB2W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 3rd rank of \a u32. + #define MSB3W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 4th rank of \a u32. + #define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32. + #define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32. + #define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32. + #define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32. + + #define MSW(u64) (((U32 *)&(u64))[0]) //!< Most significant word of \a u64. + #define LSW(u64) (((U32 *)&(u64))[1]) //!< Least significant word of \a u64. + #define MSH0(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 1st rank of \a u64. + #define MSH1(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 2nd rank of \a u64. + #define MSH2(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 3rd rank of \a u64. + #define MSH3(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 4th rank of \a u64. + #define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64. + #define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64. + #define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64. + #define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64. + #define MSB0D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 1st rank of \a u64. + #define MSB1D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 2nd rank of \a u64. + #define MSB2D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 3rd rank of \a u64. + #define MSB3D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 4th rank of \a u64. + #define MSB4D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 5th rank of \a u64. + #define MSB5D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 6th rank of \a u64. + #define MSB6D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 7th rank of \a u64. + #define MSB7D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 8th rank of \a u64. + #define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64. + #define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64. + #define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64. + #define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64. + #define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64. + #define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64. + #define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64. + #define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64. + +#else + #error Unknown endianism. +#endif + +//! @} + + +/*! \name Endianism Conversion + * + * The same considerations as for clz and ctz apply here but AVR32-GCC's + * __builtin_bswap_16 and __builtin_bswap_32 do not behave like macros when + * applied to constant expressions, so two sets of macros are defined here: + * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known + * at compile time); + * - swap16, swap32 and swap64 to apply to non-constant expressions (values + * unknown at compile time). + */ +//! @{ + +/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). + * + * \param u16 U16 of which to toggle the endianism. + * + * \return Value resulting from \a u16 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\ + ((U16)(u16) << 8))) + +/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). + * + * \param u32 U32 of which to toggle the endianism. + * + * \return Value resulting from \a u32 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\ + ((U32)Swap16((U32)(u32)) << 16))) + +/*! \brief Toggles the endianism of \a u64 (by swapping its bytes). + * + * \param u64 U64 of which to toggle the endianism. + * + * \return Value resulting from \a u64 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\ + ((U64)Swap32((U64)(u64)) << 32))) + +/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). + * + * \param u16 U16 of which to toggle the endianism. + * + * \return Value resulting from \a u16 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) + #define swap16(u16) ((U16)__builtin_bswap_16((U16)(u16))) +#elif (defined __ICCAVR32__) + #define swap16(u16) ((U16)__swap_bytes_in_halfwords((U16)(u16))) +#endif + +/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). + * + * \param u32 U32 of which to toggle the endianism. + * + * \return Value resulting from \a u32 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) + #define swap32(u32) ((U32)__builtin_bswap_32((U32)(u32))) +#elif (defined __ICCAVR32__) + #define swap32(u32) ((U32)__swap_bytes((U32)(u32))) +#endif + +/*! \brief Toggles the endianism of \a u64 (by swapping its bytes). + * + * \param u64 U64 of which to toggle the endianism. + * + * \return Value resulting from \a u64 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\ + ((U64)swap32((U64)(u64)) << 32))) + +//! @} + + +/*! \name Target Abstraction + */ +//! @{ + +#define _GLOBEXT_ extern //!< extern storage-class specifier. +#define _CONST_TYPE_ const //!< const type qualifier. +#define _MEM_TYPE_SLOW_ //!< Slow memory type. +#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type. +#define _MEM_TYPE_FAST_ //!< Fast memory type. + +typedef U8 Byte; //!< 8-bit unsigned integer. + +#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM. +#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM. +#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM. +#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM. + +#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32. +#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32. +#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32. +#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32. +#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32. +#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32. +#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32. +#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32. + +//! @} + +#endif // __AVR32_ABI_COMPILER__ + + +#endif // _COMPILER_H_ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/conf_isp.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/conf_isp.h new file mode 100644 index 0000000000000000000000000000000000000000..ca516ee0020af5f8f602a0a82e53e6e8dd362bb3 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/conf_isp.h @@ -0,0 +1,136 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ****************************************************************** + * + * \brief ISP configuration file. + * + * This file contains the possible external configuration of the ISP. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a USB module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ***************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _CONF_ISP_H_ +#define _CONF_ISP_H_ + +#include +#include "compiler.h" + + +//_____ D E F I N I T I O N S ______________________________________________ + +#define PRODUCT_MANUFACTURER_ID 0x58 +#define PRODUCT_FAMILY_ID 0x20 + +#define ISP_VERSION 0x10 +#define ISP_ID0 0x00 +#define ISP_ID1 0x00 + +#define ISP_CFG1 (*(volatile U32 *)ISP_CFG1_ADDRESS) +#define ISP_CFG1_ADDRESS (AVR32_FLASHC_USER_PAGE_ADDRESS + ISP_CFG1_OFFSET) +#define ISP_CFG1_OFFSET 0x000001FC +#define ISP_CFG1_SIZE 4 + +#define ISP_CFG1_BOOT_KEY1 16 +#define ISP_CFG1_BOOT_KEY1_MASK 0xFFFF0000 +#define ISP_CFG1_BOOT_KEY1_OFFSET 16 +#define ISP_CFG1_BOOT_KEY1_SIZE 16 +#define ISP_CFG1_BOOT_KEY1_VALUE 0xE11E + +#define ISP_CFG1_FORCE 9 +#define ISP_CFG1_FORCE_MASK 0x00000200 +#define ISP_CFG1_FORCE_OFFSET 9 +#define ISP_CFG1_FORCE_SIZE 1 + +#define ISP_CFG1_IO_COND_EN 8 +#define ISP_CFG1_IO_COND_EN_MASK 0x00000100 +#define ISP_CFG1_IO_COND_EN_OFFSET 8 +#define ISP_CFG1_IO_COND_EN_SIZE 1 + +#define ISP_CFG1_CRC8 0 +#define ISP_CFG1_CRC8_MASK 0x000000FF +#define ISP_CFG1_CRC8_OFFSET 0 +#define ISP_CFG1_CRC8_SIZE 8 +#define ISP_CFG1_CRC8_POLYNOMIAL 0x107 + +#define ISP_CFG2 (*(volatile U32 *)ISP_CFG2_ADDRESS) +#define ISP_CFG2_ADDRESS (AVR32_FLASHC_USER_PAGE_ADDRESS + ISP_CFG2_OFFSET) +#define ISP_CFG2_OFFSET 0x000001F8 +#define ISP_CFG2_SIZE 4 + +#define ISP_CFG2_BOOT_KEY 17 +#define ISP_CFG2_BOOT_KEY_MASK 0xFFFE0000 +#define ISP_CFG2_BOOT_KEY_OFFSET 17 +#define ISP_CFG2_BOOT_KEY_SIZE 15 +#define ISP_CFG2_BOOT_KEY_VALUE 0x494F + +#define ISP_CFG2_IO_COND_LEVEL 16 +#define ISP_CFG2_IO_COND_LEVEL_MASK 0x00010000 +#define ISP_CFG2_IO_COND_LEVEL_OFFSET 16 +#define ISP_CFG2_IO_COND_LEVEL_SIZE 1 + +#define ISP_CFG2_IO_COND_PIN 8 +#define ISP_CFG2_IO_COND_PIN_MASK 0x0000FF00 +#define ISP_CFG2_IO_COND_PIN_OFFSET 8 +#define ISP_CFG2_IO_COND_PIN_SIZE 8 + +#define ISP_CFG2_CRC8 0 +#define ISP_CFG2_CRC8_MASK 0x000000FF +#define ISP_CFG2_CRC8_OFFSET 0 +#define ISP_CFG2_CRC8_SIZE 8 +#define ISP_CFG2_CRC8_POLYNOMIAL 0x107 + +#define ISP_KEY (*(volatile U32 *)ISP_KEY_ADDRESS) +#define ISP_KEY_ADDRESS (AVR32_SRAM_ADDRESS + ISP_KEY_OFFSET) +#define ISP_KEY_OFFSET 0x00000000 +#define ISP_KEY_SIZE 4 +#define ISP_KEY_VALUE ('I' << 24 | 'S' << 16 | 'P' << 8 | 'K') + +#ifndef ISP_OSC + #define ISP_OSC 0 +#endif + +#define DFU_FRAME_LENGTH 2048 + +#define PROGRAM_START_ADDRESS (AVR32_FLASH_ADDRESS + PROGRAM_START_OFFSET) +#define PROGRAM_START_OFFSET 0x00002000 + + +#endif // _CONF_ISP_H_ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/parts.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/parts.h new file mode 100644 index 0000000000000000000000000000000000000000..6637b2f76e8f82631cfb8fb8e838d074329d3714 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/parts.h @@ -0,0 +1,203 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Arch file for AVR32. + * + * This file defines common AVR32 UC3 series. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _ARCH_H_ +#define _ARCH_H_ + +// UC3 A Series +#define UC3A0 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3A0128__) || \ + defined (__AVR32_UC3A0256__) || \ + defined (__AVR32_UC3A0512__) || \ + defined (__AVR32_UC3A0512ES__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3A0128__) || \ + defined (__AT32UC3A0256__) || \ + defined (__AT32UC3A0512__) || \ + defined (__AT32UC3A0512ES__))) + +#define UC3A1 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3A1128__) || \ + defined (__AVR32_UC3A1256__) || \ + defined (__AVR32_UC3A1512__) || \ + defined (__AVR32_UC3A1512ES__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3A1128__) || \ + defined (__AT32UC3A1256__) || \ + defined (__AT32UC3A1512__) || \ + defined (__AT32UC3A1512ES__))) + +#define UC3A3 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3A364__) || \ + defined (__AVR32_UC3A364S__) || \ + defined (__AVR32_UC3A3128__) || \ + defined (__AVR32_UC3A3128S__) || \ + defined (__AVR32_UC3A3256__) || \ + defined (__AVR32_UC3A3256S__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3A364__) || \ + defined (__AT32UC3A364S__) || \ + defined (__AT32UC3A3128__) || \ + defined (__AT32UC3A3128S__) || \ + defined (__AT32UC3A3256__) || \ + defined (__AT32UC3A3256S__))) + +#define UC3A (UC3A0 || UC3A1 || UC3A3) + +// UC3 B Series +#define UC3B0 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3B064__) || \ + defined (__AVR32_UC3B0128__) || \ + defined (__AVR32_UC3B0256__) || \ + defined (__AVR32_UC3B0256ES__) || \ + defined (__AVR32_UC3B0512__) || \ + defined (__AVR32_UC3B0512REVC_))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3B064__) || \ + defined (__AT32UC3B0128__) || \ + defined (__AT32UC3B0256__) || \ + defined (__AT32UC3B0256ES__) || \ + defined (__AT32UC3B0512__) || \ + defined (__AT32UC3B0512REVC__))) + +#define UC3B1 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3B164__) || \ + defined (__AVR32_UC3B1128__) || \ + defined (__AVR32_UC3B1256__) || \ + defined (__AVR32_UC3B1256ES__) || \ + defined (__AVR32_UC3B1512__) || \ + defined (__AVR32_UC3B1512ES__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3B164__) || \ + defined (__AT32UC3B1128__) || \ + defined (__AT32UC3B1256__) || \ + defined (__AT32UC3B1256ES__) || \ + defined (__AT32UC3B1512__) || \ + defined (__AT32UC3B1512REVC__))) + +#define UC3B (UC3B0 || UC3B1 ) + +// UC3 C Series +#define UC3C0 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3C064C__) || \ + defined (__AVR32_UC3C0128C__) || \ + defined (__AVR32_UC3C0256C__) || \ + defined (__AVR32_UC3C0512CREVC__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3C064C__) || \ + defined (__AT32UC3C0128C__) || \ + defined (__AT32UC3C0256C__) || \ + defined (__AT32UC3C0512C__))) + +#define UC3C1 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3C164C__) || \ + defined (__AVR32_UC3C1128C__) || \ + defined (__AVR32_UC3C1256C__) || \ + defined (__AVR32_UC3C1512CREVC__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3C164C__) || \ + defined (__AT32UC3C1128C__) || \ + defined (__AT32UC3C1256C__) || \ + defined (__AT32UC3C1512C__))) + +#define UC3C2 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3C264C__) || \ + defined (__AVR32_UC3C2128C__) || \ + defined (__AVR32_UC3C2256C__) || \ + defined (__AVR32_UC3C2512CREVC__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3C264C__) || \ + defined (__AT32UC3C2128C__) || \ + defined (__AT32UC3C2256C__) || \ + defined (__AT32UC3C2512C__))) + +#define UC3C (UC3C0 || UC3C1 || UC3C2) + +// UC3 L Device series +#define UC3L0 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3L016__) || \ + defined (__AVR32_UC3L032__) || \ + defined (__AVR32_UC3L064__) || \ + defined (__AVR32_UC3L064REVB__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3L016__) || \ + defined (__AT32UC3L032__) || \ + defined (__AT32UC3L064__) || \ + defined (__AT32UC3L064REVB__))) + +#define UC3L1 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3L116__) || \ + defined (__AVR32_UC3L132__) || \ + defined (__AVR32_UC3L164__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3L116__) || \ + defined (__AT32UC3L132__) || \ + defined (__AT32UC3L164__))) + +#define UC3L2 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3L216__) || \ + defined (__AVR32_UC3L232__) || \ + defined (__AVR32_UC3L264__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3L216__) || \ + defined (__AT32UC3L232__) || \ + defined (__AT32UC3L264__))) + +#define UC3L3 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3L316__) || \ + defined (__AVR32_UC3L332__) || \ + defined (__AVR32_UC3L364__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3L316__) || \ + defined (__AT32UC3L332__) || \ + defined (__AT32UC3L364__))) + +#define UC3L (UC3L0 || UC3L1 || UC3L2 || UC3L3) + +#endif // _ARCH_H_ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/timer.c b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/timer.c new file mode 100644 index 0000000000000000000000000000000000000000..6ffba634a9068347e6d8856bc597933dcd8722c4 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/timer.c @@ -0,0 +1,232 @@ +/*! \page License + * Copyright (C) 2009, H&D Wireless AB All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of H&D Wireless AB may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY H&D WIRELESS AB ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#ifdef FREERTOS_USED +#include "FreeRTOS.h" +#include "task.h" +#endif + +#define TIMER_HZ 4 + + +struct timeout_t { + U32 tick; + U32 expire_at_tick; + Bool expired; + U8 type; + void (*cb)(void* ctx); + void* ctx; +}; + +struct timer_t { + volatile U32 tick; + struct timeout_t timeout[10]; + void (*tick_isr) (void* ctx); + const U32 MS_PER_TICK; + void *ctx; +}; + +#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0]) + + +static struct timer_t TIMER = { + .tick = 0, +#ifdef FREERTOS_USED + .MS_PER_TICK = 1 / portTICK_RATE_MS, +#else + .MS_PER_TICK = TIMER_HZ, +#endif + .timeout = { { 0 } }, +}; + +#ifdef FREERTOS_USED /* Use TICK-hook */ + +void vApplicationTickHook( void ) { + struct timer_t* priv = &TIMER; + priv->tick++; + if(priv->tick_isr) { + priv->tick_isr(priv->ctx); + } +} + +#else /* Use interrupt directly */ + +static __attribute__((__interrupt__)) void irq_handler(void) +{ + volatile avr32_rtc_t *rtc = &AVR32_RTC; + struct timer_t* priv = &TIMER; + priv->tick++; + + if(priv->tick_isr) + priv->tick_isr(priv->ctx); + + rtc->icr = AVR32_RTC_ICR_TOPI_MASK; + rtc->isr; +} + +#endif + +void timer_init(void (*tick_isr) (void* ctx), void* ctx) +{ + struct timer_t* priv = &TIMER; + uint8_t id; + +#ifndef FREERTOS_USED + INTC_register_interrupt(&irq_handler, AVR32_RTC_IRQ, AVR32_INTC_INT0); + if (!rtc_init(&AVR32_RTC, RTC_OSC_RC, 0)) + Assert(0); + + rtc_set_top_value(&AVR32_RTC, 115 * priv->MS_PER_TICK / 2); + rtc_enable_interrupt(&AVR32_RTC); + rtc_enable(&AVR32_RTC); +#else + /* With FreeRTOS we use the OS tick instead */ +#endif + priv->tick_isr = tick_isr; + priv->ctx = ctx; + + for (id = 0; id < ARRAY_SIZE(priv->timeout); id++) + priv->timeout[id].expired = TRUE; +} + + +U32 timer_get_ms(void) +{ + struct timer_t* priv = &TIMER; + return priv->tick * priv->MS_PER_TICK; +} + +void timer_delay(U32 ms) +{ + struct timer_t* priv = &TIMER; + U32 expire_at_tick = priv->tick + ms / priv->MS_PER_TICK; + while (priv->tick < expire_at_tick); +} + +/** + * Called from application main loop to invoke any scheduled timeout cbs. + * This function might be called as often as possible rather than at each tick + * to support the timeout value '0', e.g a timeout within less than one tick. + * + */ +void timer_poll(void) +{ + struct timer_t* priv = &TIMER; + U8 i; + + for (i = 0; i < ARRAY_SIZE(priv->timeout); i++) { + struct timeout_t* tmo = &priv->timeout[i]; + if (tmo->expired) + continue; + + if (tmo->expire_at_tick > priv->tick) + continue; + + if (tmo->cb) + tmo->cb(tmo->ctx); + + if (tmo->type == TIMEOUT_PERIODIC) + tmo->expire_at_tick = priv->tick + tmo->tick; + else + tmo->expired = TRUE; + } +} + +static U32 timer_sched_timeout(U32 ms, U8 type) +{ + struct timer_t* priv = &TIMER; + struct timeout_t* tmo; + U8 id; + + Assert(type == TIMEOUT_ONESHOT || type == TIMEOUT_PERIODIC); + + for (id = 0; id < ARRAY_SIZE(priv->timeout); id++) { + tmo = &priv->timeout[id]; + if (tmo->expired) + break; + } + + Assert(id != ARRAY_SIZE(priv->timeout)); + + tmo->tick = ms / priv->MS_PER_TICK; + tmo->expire_at_tick = priv->tick + tmo->tick; + tmo->type = type; + tmo->expired = FALSE; + return id; +} + +U32 timer_sched_timeout_cb(U32 ms, U8 type, void (*cb)(void *ctx), void* ctx) +{ + struct timer_t* priv = &TIMER; + struct timeout_t* tmo; + U8 id; + + Assert(cb); + id = timer_sched_timeout(ms, type); + tmo = &priv->timeout[id]; + + tmo->cb = cb; + tmo->ctx = ctx; + return id; +} + + +U32 timer_mod(U32 id, U32 ms, U8 type, void (*cb)(void *ctx), void* ctx) +{ + struct timer_t* priv = &TIMER; + + if (id != INVALID_TIMER_ID && !priv->timeout[id].expired) + timer_cancel_timeout(id); + + return timer_sched_timeout_cb(ms, type, cb, ctx); +} + +void timer_cancel_timeout(U32 id) +{ + struct timer_t* priv = &TIMER; + struct timeout_t* tmo; + + tmo = &priv->timeout[id]; + tmo->expired = TRUE; +} + +int timer_interval_passed(U32 old, U32 new, U32 diff) { + /* New did not wrap */ + if (new > old && new - old > diff) { + return 1; + } + /* New did wrap */ + else if (new < old && ( ( (U32)(-1) - old ) + new ) > diff ) { + return 1; + } + return 0; +} diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/timer.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/timer.h new file mode 100644 index 0000000000000000000000000000000000000000..6614fbc44867b9e0e4c64f79cf8d0b3f6f498192 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/timer.h @@ -0,0 +1,51 @@ +/*! \page License + * Copyright (C) 2009, H&D Wireless AB All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of H&D Wireless AB may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY H&D WIRELESS AB ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef TIMER_H +#define TIMER_H +#include + +enum { + TIMEOUT_ONESHOT, + TIMEOUT_PERIODIC +}; + +#define INVALID_TIMER_ID 0xFFFFFFFF + +/* Handle timer overflows. Return 1 if the interval has passed. */ +int timer_interval_passed(uint32_t old, uint32_t new, uint32_t diff); + +void timer_tick(); +void timer_init(void (*tick_isr) (void* ctx), void* ctx); +void timer_poll(void); +void timer_delay(uint32_t ms); +uint32_t timer_sched_timeout_cb(uint32_t ms, uint8_t type, void (*cb)(void *ctx), void* ctx); +uint32_t timer_mod(uint32_t id, uint32_t ms, uint8_t type, void (*cb)(void *ctx), void* ctx); +void timer_cancel_timeout(uint32_t id); +uint32_t timer_get_ms(void); + +#endif diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/top_defs.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/top_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..09f7c3ef89e743108c90d46ea1d8841d080ccaf9 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/top_defs.h @@ -0,0 +1,120 @@ +/*! \page License + * Copyright (C) 2009, H&D Wireless AB All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of H&D Wireless AB may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY H&D WIRELESS AB ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _TOP_DEFS_H +#define _TOP_DEFS_H + +#include +#include + +#define ARRAY_SIZE(a) sizeof(a) / sizeof((a)[0]) + +#ifndef UNREF +#define UNREF(x) x = x +#endif + +#if __GNUC__ +#ifdef __KERNEL__ +#define WEAK_DECL +#else +#define WEAK_DECL __attribute__ ((__weak__)) +#endif +#define PACKED __attribute__ ((__packed__)) +#define USED __attribute__ ((__used__)) +#else + #error "Unsupported compiler" +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + + +#if 0 +#include +/* + * These functions should _NOT_ be used, call iprintf, sniprintf, iscanf, siscanf etc + * instead. Those functions do not have support for floating point formats. + * Not using these functions saves 27kB of code. + */ +extern int printf(const char *format, ...) __attribute__ ((deprecated)); +extern int sprintf(char *str, const char *format, ...) __attribute__ ((deprecated)); +extern int snprintf(char *str, size_t size, const char *format, ...) __attribute__ ((deprecated)); + +int vprintf(const char *format, va_list ap) __attribute__ ((deprecated)); +int vfprintf(FILE *stream, const char *format, va_list ap) __attribute__ ((deprecated)); +int vsprintf(char *str, const char *format, va_list ap) __attribute__ ((deprecated)); +int vsnprintf(char *str, size_t size, const char *format, va_list ap) __attribute__ ((deprecated)); + +int scanf(const char *format, ...) __attribute__ ((deprecated)); +int fscanf(FILE *stream, const char *format, ...) __attribute__ ((deprecated)); +int sscanf(const char *str, const char *format, ...) __attribute__ ((deprecated)); + +int vscanf(const char *format, va_list ap) __attribute__ ((deprecated)); +int vsscanf(const char *str, const char *format, va_list ap) __attribute__ ((deprecated)); +int vfscanf(FILE *stream, const char *format, va_list ap) __attribute__ ((deprecated)); +#endif + +#endif + + + +#if defined(__linux__) || defined(__APPLE__) + #include + #include + #define sniprintf snprintf + #define asiprintf asprintf + #define printk printf + #define siscanf sscanf + + #define WL_ASSERT(x) assert(x) + #define WL_DEBUG(args...) printf(args) + + #ifdef NO_LWIP + /* IP address representation from lwIP */ + struct ip_addr { + uint32_t addr; + } PACKED; + #endif + + #define FEAT_SOCKETS + +#else + #define WL_ASSERT(cond) do { \ + if (!(cond)) { \ + printk("%s:%d\n", __FILE__, __LINE__); \ + for(;;); \ + } \ + } while(0) + #define WL_DEBUG(args...) printk(args) + + +#endif diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/trace.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/trace.h new file mode 100644 index 0000000000000000000000000000000000000000..984262a81b81434206a7f26dbfc92afe264ea44f --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/trace.h @@ -0,0 +1,44 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*! \page License + * Copyright (C) 2009, H&D Wireless AB All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of H&D Wireless AB may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY H&D WIRELESS AB ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef TRACE_H +#define TRACE_H + +#include +#include "printf-stdarg.h" + +#define ASSERT(cond, str) do { \ + if (!(cond)) { \ + printk("%s\n", str); \ + Assert(0); \ + } \ + } while(0) + + +#endif diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/util.c b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/util.c new file mode 100644 index 0000000000000000000000000000000000000000..c01edebf46db233b9a445322edab8531ceaa87d5 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/util.c @@ -0,0 +1,260 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*! \page License + * Copyright (C) 2009, H&D Wireless AB All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of H&D Wireless AB may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY H&D WIRELESS AB ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const char* ip2str(struct ip_addr addr) +{ + static char buf[16]; + +#if BYTE_ORDER == LITTLE_ENDIAN + sniprintf(buf, sizeof(buf), "%lu.%lu.%lu.%lu", + addr.addr & 0xff, + (addr.addr >> 8) & 0xff, + (addr.addr >> 16) & 0xff, + (addr.addr >> 24) & 0xff); + return buf; +#else + sniprintf(buf, sizeof(buf), "%lu.%lu.%lu.%lu", + (addr.addr >> 24) & 0xff, + (addr.addr >> 16) & 0xff, + (addr.addr >> 8) & 0xff, + (addr.addr) & 0xff); + return buf; +#endif +} + +struct ip_addr str2ip(const char* str) +{ + int a,b,c,d; + uint32_t ip = 0; + struct ip_addr addr; + + if (siscanf(str,"%d.%d.%d.%d",&a,&b,&c,&d) != 4) + goto out; + + if (a < 0 || a > 255 || b < 0 || b > 255 || + c < 0 || c > 255 || d < 0 || d > 255) { + goto out; + } + +#if BYTE_ORDER == LITTLE_ENDIAN + ip = (d << 24) | (c << 16) | (b << 8) | a; +#else + ip = (a << 24) | (b << 16) | (c << 8) | d; +#endif + + out: + addr.addr = ip; + return addr; +} + +uint8_t ascii_to_key(char *outp, const char *inp) { + char buf[3]; + int len; + buf[2] = '\0'; + len = strlen(inp); + if (len % 2) { + printk("Invalid length\n"); + } + len = 0; + while (*inp) { + if (! isxdigit(*inp) || ! isxdigit(*(inp+1)) || + len > WL_MAX_PASS_LEN) { + return 0; + } + buf[0] = *inp++; + buf[1] = *inp++; + *outp++ = strtol(buf, NULL, 16); + len++; + } + return len; +} + + + +void printbuf(const char *prefix, const void *data, size_t len) +{ + const unsigned char *s = data; + int i, j; + + for (i = 0; i < len; i += 16) + { + printk("%s ", prefix); + for(j = 0; j < 16; j++) { + if(i + j >= len) + printk(" "); + else + printk("%02X ", (uint16_t)s[i + j]); + } + printk(": "); + for(j = 0; j < 16; j++) { + if(i + j >= len) + break; + if(s[i+j] >= 32 && s[i+j] < 127) + printk("%c", s[i + j]); + else + printk("."); + } + printk("\n"); + } +} + + +void print_network(struct wl_network_t* wl_network) +{ + printk("%s ", mac2str(wl_network->bssid.octet)); + printk("\"%s\"", ssid2str(&wl_network->ssid)); + printk(" RSSI %d dBm ", wl_network->rssi); + switch(wl_network->net_type) { + case WL_CONN_TYPE_ADHOC: + printk(" Ad-Hoc "); + break; + default : + break; + } + switch (wl_network->enc_type) { + case ENC_TYPE_WEP : + printk(" (WEP encryption)"); + break; + case ENC_TYPE_TKIP : + printk(" (TKIP encryption)"); + break; + case ENC_TYPE_CCMP : + printk(" (CCMP encryption)"); + break; + case ENC_TYPE_NONE : + break; + } + printk("\n"); + +} + +void print_network_list(void) +{ + struct wl_network_list_t* wl_network_list; + uint8_t i; + + wl_get_network_list(&wl_network_list); + + if (wl_network_list->cnt == 0) + printk("no nets found\n"); + + for (i = 0; i < wl_network_list->cnt; i++) + print_network(wl_network_list->net[i]); +} + +int join_argv(char *dst, size_t dst_len, int argc, char* argv[]) { + char *p = dst; + int i; + int len = 0; + + /* Not really kosher, an ssid may legally contain 0-bytes but + * the console interface does not deal with that. + */ + for (i = 0; i < argc; i++) { + len += strlen(argv[i]); + if (len > dst_len) { + printk("ssid too long (max %d)\n", (int) dst_len); + return 0; + } + p += sniprintf(p, + dst_len - (p - dst), + "%s ", + argv[i]); + } + if (p == dst) { + return 0; + } + p--; + *p = '\0'; /* Delete last space */ + + return p - dst; +} + +const char* ssid2str(struct wl_ssid_t *ssid) { + static char buf[WL_SSID_MAX_LENGTH + 1]; + + memset(buf, 0, sizeof buf); + memcpy(buf, ssid->ssid, ssid->len); + + return buf; +} + + +const char* mac2str(uint8_t* mac) +{ + static char buf[18]; + sniprintf(buf, sizeof(buf), "%02x-%02x-%02x-%02x-%02x-%02x", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + return buf; +} + + +char* enc_type2str(enum wl_enc_type enc_type) +{ + switch(enc_type) { + case ENC_TYPE_WEP: + return "WEP"; + case ENC_TYPE_CCMP: + return "CCMP"; + case ENC_TYPE_TKIP: + return "TKIP"; + default: + return ""; + }; +} + +int equal_ssid(const struct wl_ssid_t* ssid1, + const struct wl_ssid_t* ssid2) { + if (ssid1->len == ssid2->len && + (memcmp(ssid1->ssid, ssid2->ssid, ssid1->len) == 0)) { + return 1; + } + return 0; +} + +int equal_bssid(const struct wl_mac_addr_t* bssid1, + const struct wl_mac_addr_t* bssid2) { + if (memcmp(bssid1, bssid2, sizeof *bssid1) == 0) { + return 1; + } + return 0; +} + + diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/util.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/util.h new file mode 100644 index 0000000000000000000000000000000000000000..2b3f74f833970e7ecf55fe6686dbf0879d901000 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/util.h @@ -0,0 +1,71 @@ +/*! \page License + * Copyright (C) 2009, H&D Wireless AB All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of H&D Wireless AB may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY H&D WIRELESS AB ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _UTIL_H +#define _UTIL_H +#include +#include +#include +#include "lwip/ip.h" +#include + +const char* ip2str(struct ip_addr addr); + +struct ip_addr str2ip(const char* str); + +uint8_t ascii_to_key(char *outp, const char *inp); + +void print_network(struct wl_network_t* wl_network); + +void print_network_list(void); + +int join_argv(char *dst, size_t dst_len, int argc, char* argv[]); + +void printbuf(const char *prefix, const void *data, size_t len); + +const char* ssid2str(struct wl_ssid_t *ssid); + +const char* mac2str(uint8_t mac[6]); + +char* enc_type2str(enum wl_enc_type enc_type); + +int equal_ssid(const struct wl_ssid_t* ssid1, + const struct wl_ssid_t* ssid2); + +int equal_bssid(const struct wl_mac_addr_t* bssid1, + const struct wl_mac_addr_t* bssid2); + +#define NET_SET_SSID(net, xssid, ssid_len) do { \ + DE_MEMCPY((net)->ssid.ssid, (xssid), (ssid_len)); \ + (net)->ssid.len = (ssid_len); \ + } while (0) + +#define NET_SET_BSSID(net, xbssid) do { \ + DE_MEMCPY(&(net)->bssid, &(xbssid), sizeof (xbssid)); \ + } while (0) + +#endif /* _UTIL_H */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/wifi_spi.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/wifi_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..e2e262c2ff4d7b01b6d4dfb16bad9c8ab93256d5 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/wifi_spi.h @@ -0,0 +1,160 @@ +/* + * wifi_spi.h + * + * Created on: Jul 4, 2010 + * Author: mlf by Metodo2 srl + */ +#ifndef WiFi_Spi_h +#define WiFi_Spi_h + +#include "wl_definitions.h" + +#define CMD_FLAG 0 +#define REPLY_FLAG 1<<7 +#define DATA_FLAG 0x40 + +#define WIFI_SPI_ACK 1 +#define WIFI_SPI_ERR 0xFF + +#define TIMEOUT_CHAR 1000 + +//#define MAX_SOCK_NUM 4 /**< Maxmium number of socket */ +#define NO_SOCKET_AVAIL 255 + +#define START_CMD 0xE0 +#define END_CMD 0xEE +#define ERR_CMD 0xEF +#define CMD_POS 1 // Position of Command OpCode on SPI stream +#define PARAM_LEN_POS 2 // Position of Param len on SPI stream + +enum { + SET_NET_CMD = 0x10, + SET_PASSPHRASE_CMD = 0x11, + SET_KEY_CMD = 0x12, + TEST_CMD = 0x13, + SET_IP_CONFIG_CMD = 0x14, + SET_DNS_CONFIG_CMD = 0x15, + + GET_CONN_STATUS_CMD = 0x20, + GET_IPADDR_CMD = 0x21, + GET_MACADDR_CMD = 0x22, + GET_CURR_SSID_CMD = 0x23, + GET_CURR_BSSID_CMD = 0x24, + GET_CURR_RSSI_CMD = 0x25, + GET_CURR_ENCT_CMD = 0x26, + SCAN_NETWORKS = 0x27, + START_SERVER_TCP_CMD= 0x28, + GET_STATE_TCP_CMD = 0x29, + DATA_SENT_TCP_CMD = 0x2A, + AVAIL_DATA_TCP_CMD = 0x2B, + GET_DATA_TCP_CMD = 0x2C, + START_CLIENT_TCP_CMD= 0x2D, + STOP_CLIENT_TCP_CMD = 0x2E, + GET_CLIENT_STATE_TCP_CMD = 0x2F, + DISCONNECT_CMD = 0x30, + GET_IDX_SSID_CMD = 0x31, + GET_IDX_RSSI_CMD = 0x32, + GET_IDX_ENCT_CMD = 0x33, + REQ_HOST_BY_NAME_CMD= 0x34, + GET_HOST_BY_NAME_CMD= 0x35, + START_SCAN_NETWORKS = 0x36, + GET_FW_VERSION_CMD = 0x37, + GET_TEST_CMD = 0x38, + SEND_DATA_UDP_CMD = 0x39, + GET_REMOTE_DATA_CMD = 0x3A, + + // All command with DATA_FLAG 0x40 send a 16bit Len + + SEND_DATA_TCP_CMD = 0x44, + GET_DATABUF_TCP_CMD = 0x45, + INSERT_DATABUF_CMD = 0x46, + +}; + +#if 0 +enum wl_tcp_state { + CLOSED = 0, + LISTEN = 1, + SYN_SENT = 2, + SYN_RCVD = 3, + ESTABLISHED = 4, + FIN_WAIT_1 = 5, + FIN_WAIT_2 = 6, + CLOSE_WAIT = 7, + CLOSING = 8, + LAST_ACK = 9, + TIME_WAIT = 10 +}; +#endif + +enum numParams{ + PARAM_NUMS_0, + PARAM_NUMS_1, + PARAM_NUMS_2, + PARAM_NUMS_3, + PARAM_NUMS_4, + PARAM_NUMS_5, + MAX_PARAM_NUMS +}; + +#define MAX_PARAMS MAX_PARAM_NUMS-1 +#define PARAM_LEN_SIZE 1 + +typedef struct __attribute__((__packed__)) +{ + uint8_t paramLen; + char* param; +}tParam; + +typedef struct __attribute__((__packed__)) +{ + uint16_t dataLen; + char* data; +}tDataParam; + + +typedef struct __attribute__((__packed__)) +{ + unsigned char cmd; + unsigned char tcmd; + unsigned char nParam; + tParam params[MAX_PARAMS]; +}tSpiMsg; + +typedef struct __attribute__((__packed__)) +{ + unsigned char cmd; + unsigned char tcmd; + unsigned char nParam; + tDataParam params[MAX_PARAMS]; +}tSpiMsgData; + + +typedef struct __attribute__((__packed__)) +{ + unsigned char cmd; + unsigned char tcmd; + //unsigned char totLen; + unsigned char nParam; +}tSpiHdr; + +typedef struct __attribute__((__packed__)) +{ + uint8_t paramLen; + uint32_t param; +}tLongParam; + +typedef struct __attribute__((__packed__)) +{ + uint8_t paramLen; + uint16_t param; +}tIntParam; + +typedef struct __attribute__((__packed__)) +{ + uint8_t paramLen; + uint8_t param; +}tByteParam; + +#endif +uint8_t param; \ No newline at end of file diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/wl_cm.c b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/wl_cm.c new file mode 100644 index 0000000000000000000000000000000000000000..ebc0e45dd85f7cf24e3c9459957fe9fa21cf7e66 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/wl_cm.c @@ -0,0 +1,431 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*! \page License + * Copyright (C) 2009, H&D Wireless AB All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of H&D Wireless AB may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY H&D WIRELESS AB ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "wl_cm.h" +#include "util.h" +#include +#include "debug.h" + +/** Roaming configuration parameters **/ + +/*! The ROAMING_RSSI_THRESHOLD setting defines how bad the current + * signal strength should be before we'll consider roaming to an AP + * with better signal strength. The objective is to stay on the + * current AP as long as the RSSI is decent, even if there are other + * APs in the same BSS with better RSSI available. + * If ROAMING_RSSI_THRESHOLD is too high we might roam unecessarily. + * If ROAMING_RSSI_THRESHOLD is too low we might not roam in time to + * avoid packet loss. This also impacts power consumption, staying + * too long with an AP with poor RSSI will consume more power. + * Unit is dBm. + */ +#define ROAMING_RSSI_THRESHOLD -65 + +/*! The ROAMING_RSSI_DIFF setting defines how much better + * than the currently associated AP a new AP must be before + * we'll attempt to roam over to the new AP. + * If ROAMING_RSSI_DIFF is too high it might be too hard + * to roam (important if the STA is expected to move + * quickly through different AP coverage areas). + * If ROAMING_RSSI_DIFF is too low we might bounce between + * two APs with similar signal strengths. + * Unit is dBm. + */ +#define ROAMING_RSSI_DIFF 10 + +# include "printf-stdarg.h" +#include "ard_utils.h" +#include "debug.h" + +/** \defgroup wl_cm Connection Manager + * + * These functions are used to configure and control the WiFi connetion + * manager. + * + * + * @{ + */ + +struct cm_candidate { + struct wl_ssid_t ssid; + struct wl_mac_addr_t bssid; +}; + +struct cm { + cm_scan_cb_t *scan_cb; + cm_conn_cb_t *conn_cb; + cm_disconn_cb_t *disconn_cb; + void* ctx; + uint8_t enabled; + struct cm_candidate candidate; +}; + + +/** + * This function can be modified to pick a network based on + * application specific criteria. + * + * If the SSID can not be found in the scan list it will be + * assumed to be a hidden SSID and the wl_connect() command + * will be called to attempt to probe for the network and + * connect to it. + */ +static struct wl_network_t* +find_best_candidate(struct cm* cm) +{ + struct wl_network_list_t* netlist; + struct wl_network_t *best_net = NULL; + uint8_t i; + + if (wl_get_network_list(&netlist) != WL_SUCCESS) + return NULL; + + if (netlist->cnt == 0) + return NULL; + + for (i = 0; i < netlist->cnt; i++) { + /* match on ssid */ + if (cm->candidate.ssid.len) + if (!equal_ssid(&cm->candidate.ssid, + &netlist->net[i]->ssid)) + continue; + + /* match bssid */ + if (strncmp((char*) cm->candidate.bssid.octet, + "\xff\xff\xff\xff\xff\xff", 6)) + if (!equal_bssid(&cm->candidate.bssid, + &netlist->net[i]->bssid)) + continue; + /* check for best rssi. */ + if ( best_net && + ( best_net->rssi > netlist->net[i]->rssi) ) { + continue; + } + best_net = netlist->net[i]; + } + + return best_net; +} + + +/** + * + */ +static void +select_net(struct cm* cm) +{ + struct wl_network_t *candidate_net; + struct wl_network_t *current_net; + struct wl_ssid_t *ssid_p; + + int ret; + + /* Nothing to do */ + if (0 == cm->candidate.ssid.len) { + return; + } + + current_net = wl_get_current_network(); + candidate_net = find_best_candidate(cm); + + /* Connected to the candidate? ... */ + if ( current_net == candidate_net ) { + if ( current_net ) { + /* ...yes, dont change. */ + + return; + } + } + + /* Roaming checks */ + if (current_net && candidate_net) { + /* Are we changing BSSs? */ + if ( equal_ssid(&candidate_net->ssid, + ¤t_net->ssid)) { + + /* ...no. Does the currently connected + * net have a decent RSSI?...*/ + if ( current_net->rssi > ROAMING_RSSI_THRESHOLD ) { + /* ...yes, stay with it. */ + return; + } + /* ...no. Does the candidate have + * sufficiently better RSSI to + * motivate a switch to it? */ + if ( candidate_net->rssi < current_net->rssi + + ROAMING_RSSI_DIFF) { + return; + } + /* ...yes, try to roam to candidate_net */ + CM_DPRINTF("CM: Roaming from rssi %d to %d\n", + current_net->rssi, + candidate_net->rssi); + } + } + /* a candidate is found */ + if (candidate_net) { + /* We connect to a specific bssid here because + * find_best_candidate() might have picked a + * particulare AP among many with the same SSID. + * wl_connect() would pick one of them at random. + */ + ret = wl_connect_bssid(candidate_net->bssid); + } + /* no candidate found */ + else { + CM_DPRINTF("CM: No candidate found for ssid \"%s\"\n", + ssid2str(&cm->candidate.ssid)); + /* Might be a hidden SSID so we try to connect to it. + * wl_connect() will trigger a directed scan + * for the SSID in this case. + */ + ssid_p = &cm->candidate.ssid; + ret = wl_connect(ssid_p->ssid, ssid_p->len); + } + switch (ret) { + case WL_SUCCESS : + return; + case WL_BUSY: + wl_disconnect(); + return; + case WL_RETRY: + break; + default : + CM_DPRINTF("CM: failed to connect\n"); + break; + } + + /* some operation failed or no candidate found */ + if (wl_scan() != WL_SUCCESS) + CM_DPRINTF("CM: failed to scan\n"); +} + + +/** + * + */ +static void +wl_scan_complete_cb(void* ctx) +{ + struct cm *cm = ctx; + + CM_DPRINTF("CM: scan completed\n"); + + if (cm->scan_cb) + cm->scan_cb(cm->ctx); + + if ( 0 == cm->enabled ) { + return; + } + select_net(cm); +} + +/** + * + */ +static void +wl_media_connected_cb(void* ctx) +{ + struct cm *cm = ctx; + struct wl_network_t *net = wl_get_current_network(); + CM_DPRINTF("CM: connected to %s\n", ssid2str(&net->ssid)); + LINK_LED_ON(); + ERROR_LED_OFF(); + if (cm->conn_cb) + cm->conn_cb(net, cm->ctx); +} + + +/** + * + */ +static void +wl_conn_failure_cb(void* ctx) +{ + struct cm *cm = ctx; + CM_DPRINTF("CM: connect failed, scanning\n"); + ERROR_LED_ON(); + LINK_LED_OFF(); + + if ( 0 == cm->enabled ) { + return; + } + if (wl_scan() != WL_SUCCESS) + /* should never happen */ + CM_DPRINTF("CM: could not start scan after connect fail!\n"); +} + + +/** + * + */ +static void +wl_conn_lost_cb(void* ctx) +{ + struct cm *cm = ctx; + CM_DPRINTF("CM: connection lost, scanning\n"); + LINK_LED_OFF(); + if (cm->disconn_cb) + cm->disconn_cb(cm->ctx); + + if ( 0 == cm->enabled ) { + return; + } + if (wl_scan() != WL_SUCCESS) + /* should never happen */ + CM_DPRINTF("CM: could not start scan after connect lost!\n"); +} + + +/** + * + */ +static void +wl_event_cb(struct wl_event_t event, void* ctx) +{ + struct cm *cm = ctx; + + switch (event.id) { + case WL_EVENT_MEDIA_CONNECTED: + wl_media_connected_cb(cm); + break; + + case WL_EVENT_CONN_FAILURE: + wl_conn_failure_cb(cm); + break; + + case WL_EVENT_MEDIA_DISCONNECTED: + CM_DPRINTF("CM: disconnected\n"); + wl_conn_lost_cb(cm); + break; + + case WL_EVENT_SCAN_COMPLETE: + wl_scan_complete_cb(cm); + break; + + default: + CM_DPRINTF("CM: unhandled event\n"); + }; +} + +static struct cm *cm = NULL; + + +/** + * Doesn't actually start the CM, just initializing. CM will run whenever + * an valid ssid is set through wl_cm_set_network() and wl_cm_start() + * has been called. + */ +wl_err_t +wl_cm_init(cm_scan_cb_t scan_cb, + cm_conn_cb_t conn_cb, + cm_disconn_cb_t disconn_cb, + void* ctx) +{ + if (cm != NULL) + return WL_FAILURE; + + cm = calloc(1, sizeof(struct cm)); + if (cm == NULL) { + CM_DPRINTF("CM: out of memory\n"); + return WL_FAILURE; + } + + if (wl_register_event_cb(wl_event_cb, cm) != WL_SUCCESS) { + CM_DPRINTF("CM: could not register event cb\n"); + return WL_FAILURE; + } + + cm->scan_cb = scan_cb; + cm->conn_cb = conn_cb; + cm->disconn_cb = disconn_cb; + cm->enabled = 0; + cm->ctx = ctx; + + CM_DPRINTF("CM: initialized\n"); + return WL_SUCCESS; +} + +wl_err_t +wl_cm_start(void) { + if (NULL == cm) + return WL_FAILURE; + + cm->enabled = 1; + return WL_SUCCESS; +} + +wl_err_t +wl_cm_stop(void) { + if (NULL == cm) + return WL_FAILURE; + + cm->enabled = 0; + return WL_SUCCESS; +} + + +/** + * Set the desired network which the connection manager should try to + * connect to. + * + * The ssid and bssid of the desired network should be specified. The ssid and + * bssid will be matched against the networks found during scan. If any + * parameter is null, it will always match. If both parameters are null, + * the first found network will be chosen. + * + * @param ssid The ssid of the desired network. If null, any ssid will match. + * @param bssid The bssid of the desired network. If null, any bssid will match. + * + */ +wl_err_t +wl_cm_set_network(struct wl_ssid_t *ssid, struct wl_mac_addr_t *bssid) +{ + if (cm == NULL) + return WL_FAILURE; + + if (ssid) + memcpy(&cm->candidate.ssid, ssid, sizeof(cm->candidate.ssid)); + else + cm->candidate.ssid.len = 0; + + if (bssid) + memcpy(&cm->candidate.bssid, bssid, + sizeof(cm->candidate.bssid)); + else + memset(&cm->candidate.bssid, 0xff, sizeof(cm->candidate.bssid)); + + if (cm->candidate.ssid.len) + wl_scan(); + + return WL_SUCCESS; +} +/* + * @} + */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/wl_cm.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/wl_cm.h new file mode 100644 index 0000000000000000000000000000000000000000..bbb65d97965d7d27b95b8c85e4d05eab004dad71 --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/wl_cm.h @@ -0,0 +1,51 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*! \page License + * Copyright (C) 2009, H&D Wireless AB All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of H&D Wireless AB may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY H&D WIRELESS AB ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef WL_CM_H +#define WL_CM_H + +#include +#include +#include + +typedef void (cm_scan_cb_t)(void* ctx); +typedef void (cm_conn_cb_t)(struct wl_network_t *net, void* ctx); +typedef void (cm_disconn_cb_t)(void* ctx); + +wl_err_t wl_cm_set_network(struct wl_ssid_t *ssid, struct wl_mac_addr_t *bssid); + +wl_err_t wl_cm_init(cm_scan_cb_t scan_cb, + cm_conn_cb_t conn_cb, + cm_disconn_cb_t disconn_cb, + void* ctx); + +wl_err_t wl_cm_start(void); +wl_err_t wl_cm_stop(void); + +#endif diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/wl_definitions.h b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/wl_definitions.h new file mode 100644 index 0000000000000000000000000000000000000000..b07c203fc97a8cc1b65bf34fc0cc04e6cb999dda --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/wl_definitions.h @@ -0,0 +1,39 @@ +/* + * wl_definitions.h + * + * Created on: Mar 6, 2011 + * Author: mlf by Metodo2 srl + */ + +#ifndef WL_DEFINITIONS_H_ +#define WL_DEFINITIONS_H_ + +// Maximum size of a SSID +#define WL_SSID_MAX_LENGTH 32 +// Length of passphrase. Valid lengths are 8-63. +#define WL_WPA_KEY_MAX_LENGTH 63 +// Length of key in bytes. Valid values are 5 and 13. +#define WL_WEP_KEY_MAX_LENGTH 13 +// Size of a MAC-address or BSSID +#define WL_MAC_ADDR_LENGTH 6 +// Size of a MAC-address or BSSID +#define WL_IPV4_LENGTH 4 +// Maximum size of a SSID list +#define WL_NETWORKS_LIST_MAXNUM 10 +// Maxmium number of socket +#define MAX_SOCK_NUM 4 +//Maximum number of attempts to establish wifi connection +#define WL_MAX_ATTEMPT_CONNECTION 10 + +typedef enum { + WL_IDLE_STATUS, + WL_NO_SSID_AVAIL, + WL_SCAN_COMPLETED, + WL_CONNECTED, + WL_CONNECT_FAILED, + WL_CONNECTION_LOST, + WL_DISCONNECTED +} wl_status_t; + + +#endif /* WL_DEFINITIONS_H_ */ diff --git a/hardware/arduino/avr/firmwares/wifishield/wifiHD/wifiHD.cproj b/hardware/arduino/avr/firmwares/wifishield/wifiHD/wifiHD.cproj new file mode 100644 index 0000000000000000000000000000000000000000..3d15941fd788efface0df3b4fd3e36f34832bb4a --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifiHD/wifiHD.cproj @@ -0,0 +1,1291 @@ + + + + 2.0 + 6.0 + com.Atmel.AVRGCC32 + 417e15db-488a-4b56-8d4e-fbe832b2b649 + wifiHD + AT32uc3a1256 + none + Importer + Executable + C + wifiHD + .elf + $(MSBuildProjectDirectory)\$(Configuration) + Native + com.atmel.avrdbg.tool.jtagicemk3 + true + + + + + + + + + + + + + + JTAG + + com.atmel.avrdbg.tool.jtagicemk3 + JTAGICE3 + J30200003078 + true + false + + + + 127.0.0.1 + 51999 + False + + + JTAG + + 250000 + 1000000 + 150000 + false + false + 0 + 0 + 0 + 0 + + + + 3.5.0 + false + + 0 + + + + + True + True + True + True + + + BOARD=ARDUINO + WITH_KEY + WITH_WPA + WITH_NO_DMA + DATAFLASH=1 + _INFO_DEBUG_=1 + + + + + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PDCA + ../src/SOFTWARE_FRAMEWORK/DRIVERS/TC + ../src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX + ../src/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EBI/SMC + ../src/SOFTWARE_FRAMEWORK/UTILS/DEBUG + ../src/SOFTWARE_FRAMEWORK/SERVICES/DELAY + ../src/SOFTWARE_FRAMEWORK/DRIVERS/USART + ../src/SOFTWARE_FRAMEWORK/DRIVERS/SPI + ../src/SOFTWARE_FRAMEWORK/DRIVERS/RTC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PM + ../src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EIC + ../src/CONFIG + ../src/SOFTWARE_FRAMEWORK/DRIVERS/CPU/CYCLE_COUNTER + ../src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE + ../src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR + ../src/SOFTWARE_FRAMEWORK/UTILS + ../src/SOFTWARE_FRAMEWORK/DRIVERS/INTC + ../src/SOFTWARE_FRAMEWORK/BOARDS + ../src + ../src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include + ../src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4 + ../src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/if/include + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/WIFI/HD + + + Optimize for size (-Os) + -fdata-sections -ffunction-sections + True + True + True + True + -c -fmessage-length=0 + True + + + newlib_addons-at32ucr2-speed_opt + _ucr2_hd_spi_v2.7.0 + _ucr2_hd_wl_sta_intwpa_v2.7.0 + + + + + ../src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS + ../src/SOFTWARE_FRAMEWORK/BOARDS + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/WIFI/HD/v2.7.0/UCR2/GCC + + + True + True + True + -Wl,--gc-sections -Wl,-e,_trampoline -T../src/SOFTWARE_FRAMEWORK/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/GCC/link_uc3a1256.lds + + + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PDCA + ../src/SOFTWARE_FRAMEWORK/DRIVERS/TC + ../src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX + ../src/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EBI/SMC + ../src/SOFTWARE_FRAMEWORK/UTILS/DEBUG + ../src/SOFTWARE_FRAMEWORK/SERVICES/DELAY + ../src/SOFTWARE_FRAMEWORK/DRIVERS/USART + ../src/SOFTWARE_FRAMEWORK/DRIVERS/SPI + ../src/SOFTWARE_FRAMEWORK/DRIVERS/RTC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PM + ../src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EIC + ../src/CONFIG + ../src/SOFTWARE_FRAMEWORK/DRIVERS/CPU/CYCLE_COUNTER + ../src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE + ../src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR + ../src/SOFTWARE_FRAMEWORK/UTILS + ../src/SOFTWARE_FRAMEWORK/DRIVERS/INTC + ../src/SOFTWARE_FRAMEWORK/BOARDS + + + -Wa,-g + + + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PDCA + ../src/SOFTWARE_FRAMEWORK/DRIVERS/TC + ../src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX + ../src/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EBI/SMC + ../src/SOFTWARE_FRAMEWORK/UTILS/DEBUG + ../src/SOFTWARE_FRAMEWORK/SERVICES/DELAY + ../src/SOFTWARE_FRAMEWORK/DRIVERS/USART + ../src/SOFTWARE_FRAMEWORK/DRIVERS/SPI + ../src/SOFTWARE_FRAMEWORK/DRIVERS/RTC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PM + ../src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EIC + ../src/CONFIG + ../src/SOFTWARE_FRAMEWORK/DRIVERS/CPU/CYCLE_COUNTER + ../src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE + ../src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR + ../src/SOFTWARE_FRAMEWORK/UTILS + ../src/SOFTWARE_FRAMEWORK/DRIVERS/INTC + ../src/SOFTWARE_FRAMEWORK/BOARDS + + + + + + + + + True + True + True + True + false + false + + + BOARD=ARDUINO + NO_SYS + _DEBUG_ + _ASSERT_ENABLE_ + WITH_KEY + WITH_WPA + WITH_NO_DMA + DATAFLASH=1 + _INFO_DEBUG_=1 + + + + + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PDCA + ../src/SOFTWARE_FRAMEWORK/DRIVERS/TC + ../src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX + ../src/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EBI/SMC + ../src/SOFTWARE_FRAMEWORK/UTILS/DEBUG + ../src/SOFTWARE_FRAMEWORK/SERVICES/DELAY + ../src/SOFTWARE_FRAMEWORK/DRIVERS/USART + ../src/SOFTWARE_FRAMEWORK/DRIVERS/SPI + ../src/SOFTWARE_FRAMEWORK/DRIVERS/RTC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PM + ../src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EIC + ../src/CONFIG + ../src/SOFTWARE_FRAMEWORK/DRIVERS/CPU/CYCLE_COUNTER + ../src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE + ../src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR + ../src/SOFTWARE_FRAMEWORK/UTILS + ../src/SOFTWARE_FRAMEWORK/DRIVERS/INTC + ../src/SOFTWARE_FRAMEWORK/BOARDS + ../src + ../src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include + ../src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4 + ../src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/if/include + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/WIFI/HD + + + Optimize (-O1) + -fdata-sections -ffunction-sections + true + false + false + false + false + true + true + false + false + false + Maximum (-g3) + false + false + true + false + false + false + false + -c -fmessage-length=0 + false + true + false + false + false + false + + + newlib_addons-at32ucr2-speed_opt + _ucr2_hd_spi_v2.7.0 + _ucr2_hd_wl_sta_intwpa_v2.7.0 + + + + + ../src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS + ../src/SOFTWARE_FRAMEWORK/BOARDS + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/WIFI/HD/v2.7.0/UCR2/GCC + + + true + false + false + false + false + true + true + + + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PDCA + ../src/SOFTWARE_FRAMEWORK/DRIVERS/TC + ../src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX + ../src/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EBI/SMC + ../src/SOFTWARE_FRAMEWORK/UTILS/DEBUG + ../src/SOFTWARE_FRAMEWORK/SERVICES/DELAY + ../src/SOFTWARE_FRAMEWORK/DRIVERS/USART + ../src/SOFTWARE_FRAMEWORK/DRIVERS/SPI + ../src/SOFTWARE_FRAMEWORK/DRIVERS/RTC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PM + ../src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EIC + ../src/CONFIG + ../src/SOFTWARE_FRAMEWORK/DRIVERS/CPU/CYCLE_COUNTER + ../src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE + ../src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR + ../src/SOFTWARE_FRAMEWORK/UTILS + ../src/SOFTWARE_FRAMEWORK/DRIVERS/INTC + ../src/SOFTWARE_FRAMEWORK/BOARDS + + + false + Default (-g) + -Wa,-g + + + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PDCA + ../src/SOFTWARE_FRAMEWORK/DRIVERS/TC + ../src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX + ../src/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EBI/SMC + ../src/SOFTWARE_FRAMEWORK/UTILS/DEBUG + ../src/SOFTWARE_FRAMEWORK/SERVICES/DELAY + ../src/SOFTWARE_FRAMEWORK/DRIVERS/USART + ../src/SOFTWARE_FRAMEWORK/DRIVERS/SPI + ../src/SOFTWARE_FRAMEWORK/DRIVERS/RTC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PM + ../src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EIC + ../src/CONFIG + ../src/SOFTWARE_FRAMEWORK/DRIVERS/CPU/CYCLE_COUNTER + ../src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE + ../src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR + ../src/SOFTWARE_FRAMEWORK/UTILS + ../src/SOFTWARE_FRAMEWORK/DRIVERS/INTC + ../src/SOFTWARE_FRAMEWORK/BOARDS + + + false + false + Default (-Wa,-g) + + + + + bin\Debug_512\ + + + True + True + True + True + false + false + + + BOARD=ARDUINO + _APP_DEBUG_ + _DEBUG_ + _ASSERT_ENABLE_ + EXT_BOARD=SPB104 + WITH_KEY + WITH_WPA + WITH_NO_DMA + LWIP_DEBUG + _INFO_DEBUG_=1 + + + + + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PDCA + ../src/SOFTWARE_FRAMEWORK/DRIVERS/TC + ../src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX + ../src/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EBI/SMC + ../src/SOFTWARE_FRAMEWORK/UTILS/DEBUG + ../src/SOFTWARE_FRAMEWORK/SERVICES/DELAY + ../src/SOFTWARE_FRAMEWORK/DRIVERS/USART + ../src/SOFTWARE_FRAMEWORK/DRIVERS/SPI + ../src/SOFTWARE_FRAMEWORK/DRIVERS/RTC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PM + ../src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EIC + ../src/CONFIG + ../src/SOFTWARE_FRAMEWORK/DRIVERS/CPU/CYCLE_COUNTER + ../src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE + ../src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR + ../src/SOFTWARE_FRAMEWORK/UTILS + ../src/SOFTWARE_FRAMEWORK/DRIVERS/INTC + ../src/SOFTWARE_FRAMEWORK/BOARDS + ../src + ../src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include + ../src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4 + ../src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/if/include + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/WIFI/HD + + + Optimize (-O1) + -fdata-sections + true + false + false + false + false + true + false + false + false + false + Maximum (-g3) + false + false + true + false + false + false + false + -c -fmessage-length=0 + false + true + false + false + false + false + + + newlib_addons-at32ucr2-speed_opt + _ucr2_hd_spi_standalone_v2.1.1 + _ucr2_hd_wl_standalone_v2.1.1 + + + + + ../src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS + ../src/SOFTWARE_FRAMEWORK/BOARDS + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/WIFI/HD/v2.1.1/UCR2/GCC + + + true + false + false + false + false + true + true + + + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PDCA + ../src/SOFTWARE_FRAMEWORK/DRIVERS/TC + ../src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX + ../src/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EBI/SMC + ../src/SOFTWARE_FRAMEWORK/UTILS/DEBUG + ../src/SOFTWARE_FRAMEWORK/SERVICES/DELAY + ../src/SOFTWARE_FRAMEWORK/DRIVERS/USART + ../src/SOFTWARE_FRAMEWORK/DRIVERS/SPI + ../src/SOFTWARE_FRAMEWORK/DRIVERS/RTC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PM + ../src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EIC + ../src/CONFIG + ../src/SOFTWARE_FRAMEWORK/DRIVERS/CPU/CYCLE_COUNTER + ../src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE + ../src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR + ../src/SOFTWARE_FRAMEWORK/UTILS + ../src/SOFTWARE_FRAMEWORK/DRIVERS/INTC + ../src/SOFTWARE_FRAMEWORK/BOARDS + + + false + Default (-g) + -Wa,-g + + + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PDCA + ../src/SOFTWARE_FRAMEWORK/DRIVERS/TC + ../src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX + ../src/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EBI/SMC + ../src/SOFTWARE_FRAMEWORK/UTILS/DEBUG + ../src/SOFTWARE_FRAMEWORK/SERVICES/DELAY + ../src/SOFTWARE_FRAMEWORK/DRIVERS/USART + ../src/SOFTWARE_FRAMEWORK/DRIVERS/SPI + ../src/SOFTWARE_FRAMEWORK/DRIVERS/RTC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PM + ../src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EIC + ../src/CONFIG + ../src/SOFTWARE_FRAMEWORK/DRIVERS/CPU/CYCLE_COUNTER + ../src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE + ../src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR + ../src/SOFTWARE_FRAMEWORK/UTILS + ../src/SOFTWARE_FRAMEWORK/DRIVERS/INTC + ../src/SOFTWARE_FRAMEWORK/BOARDS + + + false + false + Default (-Wa,-g) + + + + + bin\Release_512\ + + + True + True + True + True + false + false + + + BOARD=ARDUINO + _ASSERT_ENABLE_ + EXT_BOARD=SPB104 + WITH_KEY + WITH_WPA + WITH_NO_DMA + LWIP_DEBUG + _INFO_DEBUG_=1 + + + + + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PDCA + ../src/SOFTWARE_FRAMEWORK/DRIVERS/TC + ../src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX + ../src/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EBI/SMC + ../src/SOFTWARE_FRAMEWORK/UTILS/DEBUG + ../src/SOFTWARE_FRAMEWORK/SERVICES/DELAY + ../src/SOFTWARE_FRAMEWORK/DRIVERS/USART + ../src/SOFTWARE_FRAMEWORK/DRIVERS/SPI + ../src/SOFTWARE_FRAMEWORK/DRIVERS/RTC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PM + ../src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EIC + ../src/CONFIG + ../src/SOFTWARE_FRAMEWORK/DRIVERS/CPU/CYCLE_COUNTER + ../src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE + ../src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR + ../src/SOFTWARE_FRAMEWORK/UTILS + ../src/SOFTWARE_FRAMEWORK/DRIVERS/INTC + ../src/SOFTWARE_FRAMEWORK/BOARDS + ../src + ../src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include + ../src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-1.3.2/src/include/ipv4 + ../src/SOFTWARE_FRAMEWORK/SERVICES/LWIP/lwip-port-1.3.2/HD/if/include + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/WIFI/HD + + + -fdata-sections + true + false + false + false + false + true + false + false + false + false + false + false + true + false + false + false + false + -c -fmessage-length=0 + false + true + false + false + false + false + + + newlib_addons-at32ucr2-speed_opt + _ucr2_hd_spi_standalone_v2.1.1 + _ucr2_hd_wl_standalone_v2.1.1 + + + + + ../src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS + ../src/SOFTWARE_FRAMEWORK/BOARDS + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/WIFI/HD/v2.1.1/UCR2/GCC + + + true + false + false + false + false + true + true + + + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PDCA + ../src/SOFTWARE_FRAMEWORK/DRIVERS/TC + ../src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX + ../src/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EBI/SMC + ../src/SOFTWARE_FRAMEWORK/UTILS/DEBUG + ../src/SOFTWARE_FRAMEWORK/SERVICES/DELAY + ../src/SOFTWARE_FRAMEWORK/DRIVERS/USART + ../src/SOFTWARE_FRAMEWORK/DRIVERS/SPI + ../src/SOFTWARE_FRAMEWORK/DRIVERS/RTC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PM + ../src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EIC + ../src/CONFIG + ../src/SOFTWARE_FRAMEWORK/DRIVERS/CPU/CYCLE_COUNTER + ../src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE + ../src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR + ../src/SOFTWARE_FRAMEWORK/UTILS + ../src/SOFTWARE_FRAMEWORK/DRIVERS/INTC + ../src/SOFTWARE_FRAMEWORK/BOARDS + + + false + -Wa,-g + + + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PDCA + ../src/SOFTWARE_FRAMEWORK/DRIVERS/TC + ../src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS + ../src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX + ../src/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EBI/SMC + ../src/SOFTWARE_FRAMEWORK/UTILS/DEBUG + ../src/SOFTWARE_FRAMEWORK/SERVICES/DELAY + ../src/SOFTWARE_FRAMEWORK/DRIVERS/USART + ../src/SOFTWARE_FRAMEWORK/DRIVERS/SPI + ../src/SOFTWARE_FRAMEWORK/DRIVERS/RTC + ../src/SOFTWARE_FRAMEWORK/DRIVERS/PM + ../src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO + ../src/SOFTWARE_FRAMEWORK/DRIVERS/EIC + ../src/CONFIG + ../src/SOFTWARE_FRAMEWORK/DRIVERS/CPU/CYCLE_COUNTER + ../src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE + ../src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR + ../src/SOFTWARE_FRAMEWORK/UTILS + ../src/SOFTWARE_FRAMEWORK/DRIVERS/INTC + ../src/SOFTWARE_FRAMEWORK/BOARDS + + + false + false + + + + + + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + + compile + + + compile + + + + + compile + + + + compile + + + compile + + + + compile + + + compile + + + compile + + + + + + + + + compile + + + compile + + + compile + + + compile + + + compile + + + + compile + + + compile + + + compile + + + + + compile + + + compile + + + compile + + + + + compile + + + compile + + + compile + + + + + + compile + + + + + compile + + + compile + + + + compile + + + compile + + + + compile + + + compile + + + + compile + + + compile + + + compile + + + + compile + + + compile + + + + compile + + + compile + + + compile + + + compile + + + compile + + + + compile + + + compile + + + + compile + + + compile + + + + compile + + + compile + + + + compile + + + compile + + + + + compile + + + compile + + + + + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + + compile + + + compile + + + compile + + + compile + + + + compile + + + compile + + + + + compile + + + + + compile + + + + compile + + + compile + + + + compile + + + + compile + + + + + compile + + + compile + + + + compile + + + compile + + + compile + + + + compile + + + compile + + + compile + + + compile + + + + + compile + + + + compile + + + compile + + + compile + + + compile + + + compile + + + + + + + compile + + + + + compile + + + + compile + + + compile + + + compile + + + compile + + + + + compile + + + \ No newline at end of file diff --git a/hardware/arduino/avr/firmwares/wifishield/wifishield.atsln b/hardware/arduino/avr/firmwares/wifishield/wifishield.atsln new file mode 100644 index 0000000000000000000000000000000000000000..e9a149ba152168828f0190e862053d89af831c2e --- /dev/null +++ b/hardware/arduino/avr/firmwares/wifishield/wifishield.atsln @@ -0,0 +1,36 @@ + +Microsoft Visual Studio Solution File, Format Version 11.00 +# Atmel Studio Solution File, Format Version 11.00 +Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "wifi_dnld", "wifi_dnld\wifi_dnld.cproj", "{EB9606BC-DE32-4EDD-9CDA-AE3BF36977A2}" +EndProject +Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "wifiHD", "wifiHD\wifiHD.cproj", "{417E15DB-488A-4B56-8D4E-FBE832B2B649}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug_512|AVR = Debug_512|AVR + Debug|AVR = Debug|AVR + Release_512|AVR = Release_512|AVR + Release|AVR = Release|AVR + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {EB9606BC-DE32-4EDD-9CDA-AE3BF36977A2}.Debug_512|AVR.ActiveCfg = Debug|AVR + {EB9606BC-DE32-4EDD-9CDA-AE3BF36977A2}.Debug_512|AVR.Build.0 = Debug|AVR + {EB9606BC-DE32-4EDD-9CDA-AE3BF36977A2}.Debug|AVR.ActiveCfg = Debug|AVR + {EB9606BC-DE32-4EDD-9CDA-AE3BF36977A2}.Debug|AVR.Build.0 = Debug|AVR + {EB9606BC-DE32-4EDD-9CDA-AE3BF36977A2}.Release_512|AVR.ActiveCfg = Release|AVR + {EB9606BC-DE32-4EDD-9CDA-AE3BF36977A2}.Release_512|AVR.Build.0 = Release|AVR + {EB9606BC-DE32-4EDD-9CDA-AE3BF36977A2}.Release|AVR.ActiveCfg = Release|AVR + {EB9606BC-DE32-4EDD-9CDA-AE3BF36977A2}.Release|AVR.Build.0 = Release|AVR + {417E15DB-488A-4B56-8D4E-FBE832B2B649}.Debug_512|AVR.ActiveCfg = Debug_512|AVR + {417E15DB-488A-4B56-8D4E-FBE832B2B649}.Debug_512|AVR.Build.0 = Debug_512|AVR + {417E15DB-488A-4B56-8D4E-FBE832B2B649}.Debug|AVR.ActiveCfg = Debug|AVR + {417E15DB-488A-4B56-8D4E-FBE832B2B649}.Debug|AVR.Build.0 = Debug|AVR + {417E15DB-488A-4B56-8D4E-FBE832B2B649}.Release_512|AVR.ActiveCfg = Release_512|AVR + {417E15DB-488A-4B56-8D4E-FBE832B2B649}.Release_512|AVR.Build.0 = Release_512|AVR + {417E15DB-488A-4B56-8D4E-FBE832B2B649}.Release|AVR.ActiveCfg = Release|AVR + {417E15DB-488A-4B56-8D4E-FBE832B2B649}.Release|AVR.Build.0 = Release|AVR + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/hardware/arduino/avr/libraries/EEPROM/README.md b/hardware/arduino/avr/libraries/EEPROM/README.md new file mode 100644 index 0000000000000000000000000000000000000000..a62413613da45e0c0a2b85d50cf714df2ac903e6 --- /dev/null +++ b/hardware/arduino/avr/libraries/EEPROM/README.md @@ -0,0 +1,139 @@ +## **EEPROM Library V2.0** for Arduino + +**Written by:** _Christopher Andrews_. + +### **What is the EEPROM library.** + +Th EEPROM library provides an easy to use interface to interact with the internal non-volatile storage found in AVR based Arduino boards. This library will work on many AVR devices like ATtiny and ATmega chips. + +### **How to use it** +The EEPROM library is included in your IDE download. To add its functionality to your sketch you'll need to reference the library header file. You do this by adding an include directive to the top of your sketch. + +```Arduino +#include + +void setup(){ + +} + +void loop(){ + +} + +``` + +The library provides a global variable named `EEPROM`, you use this variable to access the library functions. The methods provided in the EEPROM class are listed below. + +You can view all the examples [here](examples/). + +### **Library functions** + +#### **`EEPROM.read( address )`** [[_example_]](examples/eeprom_read/eeprom_read.ino) + +This function allows you to read a single byte of data from the eeprom. +Its only parameter is an `int` which should be set to the address you wish to read. + +The function returns an `unsigned char` containing the value read. + +#### **`EEPROM.write( address, value )`** [[_example_]](examples/eeprom_write/eeprom_write.ino) + +The `write()` method allows you to write a single byte of data to the EEPROM. +Two parameters are needed. The first is an `int` containing the address that is to be written, and the second is a the data to be written (`unsigned char`). + +This function does not return any value. + +#### **`EEPROM.update( address, value )`** [[_example_]](examples/eeprom_update/eeprom_update.ino) + +This function is similar to `EEPROM.write()` however this method will only write data if the cell contents pointed to by `address` is different to `value`. This method can help prevent unnecessary wear on the EEPROM cells. + +This function does not return any value. + +#### **`EEPROM.get( address, object )`** [[_example_]](examples/eeprom_get/eeprom_get.ino) + +This function will retrieve any object from the EEPROM. +Two parameters are needed to call this function. The first is an `int` containing the address that is to be written, and the second is the object you would like to read. + +This function returns a reference to the `object` passed in. It does not need to be used and is only returned for conveience. + +#### **`EEPROM.put( address, object )`** [[_example_]](examples/eeprom_put/eeprom_put.ino) + +This function will write any object to the EEPROM. +Two parameters are needed to call this function. The first is an `int` containing the address that is to be written, and the second is the object you would like to write. + +This function uses the _update_ method to write its data, and therefore only rewrites changed cells. + +This function returns a reference to the `object` passed in. It does not need to be used and is only returned for conveience. + +#### **Subscript operator: `EEPROM[address]`** [[_example_]](examples/eeprom_crc/eeprom_crc.ino) + +This operator allows using the identifier `EEPROM` like an array. +EEPROM cells can be read _and_ **_written_** directly using this method. + +This operator returns a reference to the EEPROM cell. + +```c++ +unsigned char val; + +//Read first EEPROM cell. +val = EEPROM[ 0 ]; + +//Write first EEPROM cell. +EEPROM[ 0 ] = val; + +//Compare contents +if( val == EEPROM[ 0 ] ){ + //Do something... +} +``` + +#### **`EEPROM.length()`** + +This function returns an `unsigned int` containing the number of cells in the EEPROM. + +--- + +### **Advanced features** + +This library uses a component based approach to provide its functionality. This means you can also use these components to design a customized approach. Two background classes are available for use: `EERef` & `EEPtr`. + +#### **`EERef` class** + +This object references an EEPROM cell. +Its purpose is to mimic a typical byte of RAM, however its storage is the EEPROM. +This class has an overhead of two bytes, similar to storing a pointer to an EEPROM cell. + +```C++ +EERef ref = EEPROM[ 10 ]; //Create a reference to 11th cell. + +ref = 4; //write to EEPROM cell. + +unsigned char val = ref; //Read referenced cell. +``` + +#### **`EEPtr` class** + +This object is a bidirectional pointer to EEPROM cells represented by `EERef` objects. +Just like a normal pointer type, this type can be dereferenced and repositioned using +increment/decrement operators. + +```C++ +EEPtr ptr = 10; //Create a pointer to 11th cell. + +*ptr = 4; //dereference and write to EEPROM cell. + +unsigned char val = *ptr; //dereference and read. + +ptr++; //Move to next EEPROM cell. +``` + +#### **`EEPROM.begin()`** + +This function returns an `EEPtr` pointing to the first cell in the EEPROM. +This is useful for STL objects, custom iteration and C++11 style ranged for loops. + +#### **`EEPROM.end()`** + +This function returns an `EEPtr` pointing at the location after the last EEPROM cell. +Used with `begin()` to provide custom iteration. + +**Note:** The `EEPtr` returned is invalid as it is out of range. Infact the hardware causes wrapping of the address (overflow) and `EEPROM.end()` actually references the first EEPROM cell. diff --git a/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_clear/eeprom_clear.ino b/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_clear/eeprom_clear.ino new file mode 100644 index 0000000000000000000000000000000000000000..8b5121c8ce317c0a812d1a8d167e5c882ae37899 --- /dev/null +++ b/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_clear/eeprom_clear.ino @@ -0,0 +1,39 @@ +/* + * EEPROM Clear + * + * Sets all of the bytes of the EEPROM to 0. + * Please see eeprom_iteration for a more in depth + * look at how to traverse the EEPROM. + * + * This example code is in the public domain. + */ + +#include + +void setup() { + // initialize the LED pin as an output. + pinMode(13, OUTPUT); + + /*** + Iterate through each byte of the EEPROM storage. + + Larger AVR processors have larger EEPROM sizes, E.g: + - Arduno Duemilanove: 512b EEPROM storage. + - Arduino Uno: 1kb EEPROM storage. + - Arduino Mega: 4kb EEPROM storage. + + Rather than hard-coding the length, you should use the pre-provided length function. + This will make your code portable to all AVR processors. + ***/ + + for (int i = 0 ; i < EEPROM.length() ; i++) { + EEPROM.write(i, 0); + } + + // turn the LED on when we're done + digitalWrite(13, HIGH); +} + +void loop() { + /** Empty loop. **/ +} diff --git a/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_crc/eeprom_crc.ino b/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_crc/eeprom_crc.ino new file mode 100644 index 0000000000000000000000000000000000000000..c6db85c3b795671385ebb84ef26ceb03eddc2ec8 --- /dev/null +++ b/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_crc/eeprom_crc.ino @@ -0,0 +1,52 @@ +/*** + Written by Christopher Andrews. + CRC algorithm generated by pycrc, MIT licence ( https://github.com/tpircher/pycrc ). + + A CRC is a simple way of checking whether data has changed or become corrupted. + This example calculates a CRC value directly on the EEPROM values. + The purpose of this example is to highlight how the EEPROM object can be used just like an array. +***/ + +#include +#include + +void setup() { + + //Start serial + Serial.begin(9600); + while (!Serial) { + ; // wait for serial port to connect. Needed for native USB port only + } + + //Print length of data to run CRC on. + Serial.print("EEPROM length: "); + Serial.println(EEPROM.length()); + + //Print the result of calling eeprom_crc() + Serial.print("CRC32 of EEPROM data: 0x"); + Serial.println(eeprom_crc(), HEX); + Serial.print("\n\nDone!"); +} + +void loop() { + /* Empty loop */ +} + +unsigned long eeprom_crc(void) { + + const unsigned long crc_table[16] = { + 0x00000000, 0x1db71064, 0x3b6e20c8, 0x26d930ac, + 0x76dc4190, 0x6b6b51f4, 0x4db26158, 0x5005713c, + 0xedb88320, 0xf00f9344, 0xd6d6a3e8, 0xcb61b38c, + 0x9b64c2b0, 0x86d3d2d4, 0xa00ae278, 0xbdbdf21c + }; + + unsigned long crc = ~0L; + + for (int index = 0 ; index < EEPROM.length() ; ++index) { + crc = crc_table[(crc ^ EEPROM[index]) & 0x0f] ^ (crc >> 4); + crc = crc_table[(crc ^ (EEPROM[index] >> 4)) & 0x0f] ^ (crc >> 4); + crc = ~crc; + } + return crc; +} diff --git a/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_get/eeprom_get.ino b/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_get/eeprom_get.ino new file mode 100644 index 0000000000000000000000000000000000000000..a07cee7c797d134b39d787c8ed0b2b2c2af9a00b --- /dev/null +++ b/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_get/eeprom_get.ino @@ -0,0 +1,68 @@ +/*** + eeprom_get example. + + This shows how to use the EEPROM.get() method. + + To pre-set the EEPROM data, run the example sketch eeprom_put. + This sketch will run without it, however, the values shown + will be shown from what ever is already on the EEPROM. + + This may cause the serial object to print out a large string + of garbage if there is no null character inside one of the strings + loaded. + + Written by Christopher Andrews 2015 + Released under MIT licence. +***/ + +#include + +void setup() { + + float f = 0.00f; //Variable to store data read from EEPROM. + int eeAddress = 0; //EEPROM address to start reading from + + Serial.begin(9600); + while (!Serial) { + ; // wait for serial port to connect. Needed for native USB port only + } + Serial.print("Read float from EEPROM: "); + + //Get the float data from the EEPROM at position 'eeAddress' + EEPROM.get(eeAddress, f); + Serial.println(f, 3); //This may print 'ovf, nan' if the data inside the EEPROM is not a valid float. + + /*** + As get also returns a reference to 'f', you can use it inline. + E.g: Serial.print( EEPROM.get( eeAddress, f ) ); + ***/ + + /*** + Get can be used with custom structures too. + I have separated this into an extra function. + ***/ + + secondTest(); //Run the next test. +} + +struct MyObject { + float field1; + byte field2; + char name[10]; +}; + +void secondTest() { + int eeAddress = sizeof(float); //Move address to the next byte after float 'f'. + + MyObject customVar; //Variable to store custom object read from EEPROM. + EEPROM.get(eeAddress, customVar); + + Serial.println("Read custom object from EEPROM: "); + Serial.println(customVar.field1); + Serial.println(customVar.field2); + Serial.println(customVar.name); +} + +void loop() { + /* Empty loop */ +} diff --git a/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_iteration/eeprom_iteration.ino b/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_iteration/eeprom_iteration.ino new file mode 100644 index 0000000000000000000000000000000000000000..3673b472f8bfcba77afd4d511561c09fee672f06 --- /dev/null +++ b/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_iteration/eeprom_iteration.ino @@ -0,0 +1,57 @@ +/*** + eeprom_iteration example. + + A set of example snippets highlighting the + simplest methods for traversing the EEPROM. + + Running this sketch is not necessary, this is + simply highlighting certain programming methods. + + Written by Christopher Andrews 2015 + Released under MIT licence. +***/ + +#include + +void setup() { + + /*** + Iterate the EEPROM using a for loop. + ***/ + + for (int index = 0 ; index < EEPROM.length() ; index++) { + + //Add one to each cell in the EEPROM + EEPROM[ index ] += 1; + } + + /*** + Iterate the EEPROM using a while loop. + ***/ + + int index = 0; + + while (index < EEPROM.length()) { + + //Add one to each cell in the EEPROM + EEPROM[ index ] += 1; + index++; + } + + /*** + Iterate the EEPROM using a do-while loop. + ***/ + + int idx = 0; //Used 'idx' to avoid name conflict with 'index' above. + + do { + + //Add one to each cell in the EEPROM + EEPROM[ idx ] += 1; + idx++; + } while (idx < EEPROM.length()); + + +} //End of setup function. + +void loop() {} \ No newline at end of file diff --git a/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_put/eeprom_put.ino b/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_put/eeprom_put.ino new file mode 100644 index 0000000000000000000000000000000000000000..c1ba0a57d5e37c734eda7fe29602acb463897a98 --- /dev/null +++ b/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_put/eeprom_put.ino @@ -0,0 +1,58 @@ +/*** + eeprom_put example. + + This shows how to use the EEPROM.put() method. + Also, this sketch will pre-set the EEPROM data for the + example sketch eeprom_get. + + Note, unlike the single byte version EEPROM.write(), + the put method will use update semantics. As in a byte + will only be written to the EEPROM if the data is actually + different. + + Written by Christopher Andrews 2015 + Released under MIT licence. +***/ + +#include + +struct MyObject { + float field1; + byte field2; + char name[10]; +}; + +void setup() { + + Serial.begin(9600); + while (!Serial) { + ; // wait for serial port to connect. Needed for native USB port only + } + + float f = 123.456f; //Variable to store in EEPROM. + int eeAddress = 0; //Location we want the data to be put. + + + //One simple call, with the address first and the object second. + EEPROM.put(eeAddress, f); + + Serial.println("Written float data type!"); + + /** Put is designed for use with custom structures also. **/ + + //Data to store. + MyObject customVar = { + 3.14f, + 65, + "Working!" + }; + + eeAddress += sizeof(float); //Move address to the next byte after float 'f'. + + EEPROM.put(eeAddress, customVar); + Serial.print("Written custom data type! \n\nView the example sketch eeprom_get to see how you can retrieve the values!"); +} + +void loop() { + /* Empty loop */ +} diff --git a/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_read/eeprom_read.ino b/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_read/eeprom_read.ino new file mode 100644 index 0000000000000000000000000000000000000000..a8a3510d8400387bad6ed46bc6c26b9220e68e30 --- /dev/null +++ b/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_read/eeprom_read.ino @@ -0,0 +1,56 @@ +/* + * EEPROM Read + * + * Reads the value of each byte of the EEPROM and prints it + * to the computer. + * This example code is in the public domain. + */ + +#include + +// start reading from the first byte (address 0) of the EEPROM +int address = 0; +byte value; + +void setup() { + // initialize serial and wait for port to open: + Serial.begin(9600); + while (!Serial) { + ; // wait for serial port to connect. Needed for native USB port only + } +} + +void loop() { + // read a byte from the current address of the EEPROM + value = EEPROM.read(address); + + Serial.print(address); + Serial.print("\t"); + Serial.print(value, DEC); + Serial.println(); + + /*** + Advance to the next address, when at the end restart at the beginning. + + Larger AVR processors have larger EEPROM sizes, E.g: + - Arduno Duemilanove: 512b EEPROM storage. + - Arduino Uno: 1kb EEPROM storage. + - Arduino Mega: 4kb EEPROM storage. + + Rather than hard-coding the length, you should use the pre-provided length function. + This will make your code portable to all AVR processors. + ***/ + address = address + 1; + if (address == EEPROM.length()) { + address = 0; + } + + /*** + As the EEPROM sizes are powers of two, wrapping (preventing overflow) of an + EEPROM address is also doable by a bitwise and of the length - 1. + + ++address &= EEPROM.length() - 1; + ***/ + + delay(500); +} diff --git a/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_update/eeprom_update.ino b/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_update/eeprom_update.ino new file mode 100644 index 0000000000000000000000000000000000000000..5e3db5b4f594cbdf9fc0d98a662acdc56f22fd75 --- /dev/null +++ b/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_update/eeprom_update.ino @@ -0,0 +1,71 @@ +/*** + EEPROM Update method + + Stores values read from analog input 0 into the EEPROM. + These values will stay in the EEPROM when the board is + turned off and may be retrieved later by another sketch. + + If a value has not changed in the EEPROM, it is not overwritten + which would reduce the life span of the EEPROM unnecessarily. + + Released using MIT licence. + ***/ + +#include + +/** the current address in the EEPROM (i.e. which byte we're going to write to next) **/ +int address = 0; + +void setup() { + /** EMpty setup **/ +} + +void loop() { + /*** + need to divide by 4 because analog inputs range from + 0 to 1023 and each byte of the EEPROM can only hold a + value from 0 to 255. + ***/ + int val = analogRead(0) / 4; + + /*** + Update the particular EEPROM cell. + these values will remain there when the board is + turned off. + ***/ + EEPROM.update(address, val); + + /*** + The function EEPROM.update(address, val) is equivalent to the following: + + if( EEPROM.read(address) != val ){ + EEPROM.write(address, val); + } + ***/ + + + /*** + Advance to the next address, when at the end restart at the beginning. + + Larger AVR processors have larger EEPROM sizes, E.g: + - Arduno Duemilanove: 512b EEPROM storage. + - Arduino Uno: 1kb EEPROM storage. + - Arduino Mega: 4kb EEPROM storage. + + Rather than hard-coding the length, you should use the pre-provided length function. + This will make your code portable to all AVR processors. + ***/ + address = address + 1; + if (address == EEPROM.length()) { + address = 0; + } + + /*** + As the EEPROM sizes are powers of two, wrapping (preventing overflow) of an + EEPROM address is also doable by a bitwise and of the length - 1. + + ++address &= EEPROM.length() - 1; + ***/ + + delay(100); +} diff --git a/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_write/eeprom_write.ino b/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_write/eeprom_write.ino new file mode 100644 index 0000000000000000000000000000000000000000..f9bea641f98c53eb75048701805de67e5fb63c55 --- /dev/null +++ b/hardware/arduino/avr/libraries/EEPROM/examples/eeprom_write/eeprom_write.ino @@ -0,0 +1,60 @@ +/* + * EEPROM Write + * + * Stores values read from analog input 0 into the EEPROM. + * These values will stay in the EEPROM when the board is + * turned off and may be retrieved later by another sketch. + */ + +#include + +/** the current address in the EEPROM (i.e. which byte we're going to write to next) **/ +int addr = 0; + +void setup() { + /** Empty setup. **/ +} + +void loop() { + /*** + Need to divide by 4 because analog inputs range from + 0 to 1023 and each byte of the EEPROM can only hold a + value from 0 to 255. + ***/ + + int val = analogRead(0) / 4; + + /*** + Write the value to the appropriate byte of the EEPROM. + these values will remain there when the board is + turned off. + ***/ + + EEPROM.write(addr, val); + + /*** + Advance to the next address, when at the end restart at the beginning. + + Larger AVR processors have larger EEPROM sizes, E.g: + - Arduno Duemilanove: 512b EEPROM storage. + - Arduino Uno: 1kb EEPROM storage. + - Arduino Mega: 4kb EEPROM storage. + + Rather than hard-coding the length, you should use the pre-provided length function. + This will make your code portable to all AVR processors. + ***/ + addr = addr + 1; + if (addr == EEPROM.length()) { + addr = 0; + } + + /*** + As the EEPROM sizes are powers of two, wrapping (preventing overflow) of an + EEPROM address is also doable by a bitwise and of the length - 1. + + ++addr &= EEPROM.length() - 1; + ***/ + + + delay(100); +} diff --git a/hardware/arduino/avr/libraries/EEPROM/keywords.txt b/hardware/arduino/avr/libraries/EEPROM/keywords.txt new file mode 100644 index 0000000000000000000000000000000000000000..2cabc0b06247f3f309d43b8bb238d6a0754eb053 --- /dev/null +++ b/hardware/arduino/avr/libraries/EEPROM/keywords.txt @@ -0,0 +1,22 @@ +####################################### +# Syntax Coloring Map For EEPROM +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +EEPROM KEYWORD1 +EERef KEYWORD1 +EEPtr KEYWORD2 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +update KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### + diff --git a/hardware/arduino/avr/libraries/EEPROM/library.properties b/hardware/arduino/avr/libraries/EEPROM/library.properties new file mode 100644 index 0000000000000000000000000000000000000000..3b20032675ecc6804c6a23e0540bef983dc9721f --- /dev/null +++ b/hardware/arduino/avr/libraries/EEPROM/library.properties @@ -0,0 +1,10 @@ +name=EEPROM +version=2.0 +author=Arduino, Christopher Andrews +maintainer=Arduino +sentence=Enables reading and writing to the permanent board storage. +paragraph=This library allows to read and write data in a memory type, the EEPROM, that keeps its content also when the board is powered off. The amount of EEPROM available depends on the microcontroller type. +category=Data Storage +url=http://www.arduino.cc/en/Reference/EEPROM +architectures=avr + diff --git a/hardware/arduino/avr/libraries/EEPROM/src/EEPROM.h b/hardware/arduino/avr/libraries/EEPROM/src/EEPROM.h new file mode 100644 index 0000000000000000000000000000000000000000..c8ec271be16c3cbbff7bdf0bc36a407ef561f486 --- /dev/null +++ b/hardware/arduino/avr/libraries/EEPROM/src/EEPROM.h @@ -0,0 +1,146 @@ +/* + EEPROM.h - EEPROM library + Original Copyright (c) 2006 David A. Mellis. All right reserved. + New version by Christopher Andrews 2015. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef EEPROM_h +#define EEPROM_h + +#include +#include +#include + +/*** + EERef class. + + This object references an EEPROM cell. + Its purpose is to mimic a typical byte of RAM, however its storage is the EEPROM. + This class has an overhead of two bytes, similar to storing a pointer to an EEPROM cell. +***/ + +struct EERef{ + + EERef( const int index ) + : index( index ) {} + + //Access/read members. + uint8_t operator*() const { return eeprom_read_byte( (uint8_t*) index ); } + operator uint8_t() const { return **this; } + + //Assignment/write members. + EERef &operator=( const EERef &ref ) { return *this = *ref; } + EERef &operator=( uint8_t in ) { return eeprom_write_byte( (uint8_t*) index, in ), *this; } + EERef &operator +=( uint8_t in ) { return *this = **this + in; } + EERef &operator -=( uint8_t in ) { return *this = **this - in; } + EERef &operator *=( uint8_t in ) { return *this = **this * in; } + EERef &operator /=( uint8_t in ) { return *this = **this / in; } + EERef &operator ^=( uint8_t in ) { return *this = **this ^ in; } + EERef &operator %=( uint8_t in ) { return *this = **this % in; } + EERef &operator &=( uint8_t in ) { return *this = **this & in; } + EERef &operator |=( uint8_t in ) { return *this = **this | in; } + EERef &operator <<=( uint8_t in ) { return *this = **this << in; } + EERef &operator >>=( uint8_t in ) { return *this = **this >> in; } + + EERef &update( uint8_t in ) { return in != *this ? *this = in : *this; } + + /** Prefix increment/decrement **/ + EERef& operator++() { return *this += 1; } + EERef& operator--() { return *this -= 1; } + + /** Postfix increment/decrement **/ + uint8_t operator++ (int){ + uint8_t ret = **this; + return ++(*this), ret; + } + + uint8_t operator-- (int){ + uint8_t ret = **this; + return --(*this), ret; + } + + int index; //Index of current EEPROM cell. +}; + +/*** + EEPtr class. + + This object is a bidirectional pointer to EEPROM cells represented by EERef objects. + Just like a normal pointer type, this can be dereferenced and repositioned using + increment/decrement operators. +***/ + +struct EEPtr{ + + EEPtr( const int index ) + : index( index ) {} + + operator int() const { return index; } + EEPtr &operator=( int in ) { return index = in, *this; } + + //Iterator functionality. + bool operator!=( const EEPtr &ptr ) { return index != ptr.index; } + EERef operator*() { return index; } + + /** Prefix & Postfix increment/decrement **/ + EEPtr& operator++() { return ++index, *this; } + EEPtr& operator--() { return --index, *this; } + EEPtr operator++ (int) { return index++; } + EEPtr operator-- (int) { return index--; } + + int index; //Index of current EEPROM cell. +}; + +/*** + EEPROMClass class. + + This object represents the entire EEPROM space. + It wraps the functionality of EEPtr and EERef into a basic interface. + This class is also 100% backwards compatible with earlier Arduino core releases. +***/ + +struct EEPROMClass{ + + //Basic user access methods. + EERef operator[]( const int idx ) { return idx; } + uint8_t read( int idx ) { return EERef( idx ); } + void write( int idx, uint8_t val ) { (EERef( idx )) = val; } + void update( int idx, uint8_t val ) { EERef( idx ).update( val ); } + + //STL and C++11 iteration capability. + EEPtr begin() { return 0x00; } + EEPtr end() { return length(); } //Standards requires this to be the item after the last valid entry. The returned pointer is invalid. + uint16_t length() { return E2END + 1; } + + //Functionality to 'get' and 'put' objects to and from EEPROM. + template< typename T > T &get( int idx, T &t ){ + EEPtr e = idx; + uint8_t *ptr = (uint8_t*) &t; + for( int count = sizeof(T) ; count ; --count, ++e ) *ptr++ = *e; + return t; + } + + template< typename T > const T &put( int idx, const T &t ){ + EEPtr e = idx; + const uint8_t *ptr = (const uint8_t*) &t; + for( int count = sizeof(T) ; count ; --count, ++e ) (*e).update( *ptr++ ); + return t; + } +}; + +static EEPROMClass EEPROM; +#endif diff --git a/hardware/arduino/avr/libraries/HID/keywords.txt b/hardware/arduino/avr/libraries/HID/keywords.txt new file mode 100644 index 0000000000000000000000000000000000000000..32a9ba5f20c382217545454649454f9daf994ba9 --- /dev/null +++ b/hardware/arduino/avr/libraries/HID/keywords.txt @@ -0,0 +1,21 @@ +####################################### +# Syntax Coloring Map HID +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +HID KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### +begin KEYWORD2 +SendReport KEYWORD2 +AppendDescriptor KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### +HID_TX LITERAL1 \ No newline at end of file diff --git a/hardware/arduino/avr/libraries/HID/library.properties b/hardware/arduino/avr/libraries/HID/library.properties new file mode 100644 index 0000000000000000000000000000000000000000..9075bd87a810faabf0789a29207da7543c92e1fe --- /dev/null +++ b/hardware/arduino/avr/libraries/HID/library.properties @@ -0,0 +1,9 @@ +name=HID +version=1.0 +author=Arduino +maintainer=Arduino +sentence=Module for PluggableUSB infrastructure. Exposes an API for devices like Keyboards, Mice and Gamepads. +paragraph= +category=Communication +url=http://www.arduino.cc/en/Reference/HID +architectures=avr diff --git a/hardware/arduino/avr/libraries/HID/src/HID.cpp b/hardware/arduino/avr/libraries/HID/src/HID.cpp new file mode 100644 index 0000000000000000000000000000000000000000..21ede269e74f994634ccbe58b96d241378d68e13 --- /dev/null +++ b/hardware/arduino/avr/libraries/HID/src/HID.cpp @@ -0,0 +1,162 @@ +/* + Copyright (c) 2015, Arduino LLC + Original code (pre-library): Copyright (c) 2011, Peter Barrett + + Permission to use, copy, modify, and/or distribute this software for + any purpose with or without fee is hereby granted, provided that the + above copyright notice and this permission notice appear in all copies. + + THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR + BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES + OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + SOFTWARE. + */ + +#include "HID.h" + +#if defined(USBCON) + +HID_& HID() +{ + static HID_ obj; + return obj; +} + +int HID_::getInterface(uint8_t* interfaceCount) +{ + *interfaceCount += 1; // uses 1 + HIDDescriptor hidInterface = { + D_INTERFACE(pluggedInterface, 1, USB_DEVICE_CLASS_HUMAN_INTERFACE, HID_SUBCLASS_NONE, HID_PROTOCOL_NONE), + D_HIDREPORT(descriptorSize), + D_ENDPOINT(USB_ENDPOINT_IN(pluggedEndpoint), USB_ENDPOINT_TYPE_INTERRUPT, USB_EP_SIZE, 0x01) + }; + return USB_SendControl(0, &hidInterface, sizeof(hidInterface)); +} + +int HID_::getDescriptor(USBSetup& setup) +{ + // Check if this is a HID Class Descriptor request + if (setup.bmRequestType != REQUEST_DEVICETOHOST_STANDARD_INTERFACE) { return 0; } + if (setup.wValueH != HID_REPORT_DESCRIPTOR_TYPE) { return 0; } + + // In a HID Class Descriptor wIndex cointains the interface number + if (setup.wIndex != pluggedInterface) { return 0; } + + int total = 0; + HIDSubDescriptor* node; + for (node = rootNode; node; node = node->next) { + int res = USB_SendControl(TRANSFER_PGM, node->data, node->length); + if (res == -1) + return -1; + total += res; + } + + // Reset the protocol on reenumeration. Normally the host should not assume the state of the protocol + // due to the USB specs, but Windows and Linux just assumes its in report mode. + protocol = HID_REPORT_PROTOCOL; + + return total; +} + +uint8_t HID_::getShortName(char *name) +{ + name[0] = 'H'; + name[1] = 'I'; + name[2] = 'D'; + name[3] = 'A' + (descriptorSize & 0x0F); + name[4] = 'A' + ((descriptorSize >> 4) & 0x0F); + return 5; +} + +void HID_::AppendDescriptor(HIDSubDescriptor *node) +{ + if (!rootNode) { + rootNode = node; + } else { + HIDSubDescriptor *current = rootNode; + while (current->next) { + current = current->next; + } + current->next = node; + } + descriptorSize += node->length; +} + +int HID_::SendReport(uint8_t id, const void* data, int len) +{ + auto ret = USB_Send(pluggedEndpoint, &id, 1); + if (ret < 0) return ret; + auto ret2 = USB_Send(pluggedEndpoint | TRANSFER_RELEASE, data, len); + if (ret2 < 0) return ret2; + return ret + ret2; +} + +bool HID_::setup(USBSetup& setup) +{ + if (pluggedInterface != setup.wIndex) { + return false; + } + + uint8_t request = setup.bRequest; + uint8_t requestType = setup.bmRequestType; + + if (requestType == REQUEST_DEVICETOHOST_CLASS_INTERFACE) + { + if (request == HID_GET_REPORT) { + // TODO: HID_GetReport(); + return true; + } + if (request == HID_GET_PROTOCOL) { + // TODO: Send8(protocol); + return true; + } + if (request == HID_GET_IDLE) { + // TODO: Send8(idle); + } + } + + if (requestType == REQUEST_HOSTTODEVICE_CLASS_INTERFACE) + { + if (request == HID_SET_PROTOCOL) { + // The USB Host tells us if we are in boot or report mode. + // This only works with a real boot compatible device. + protocol = setup.wValueL; + return true; + } + if (request == HID_SET_IDLE) { + idle = setup.wValueL; + return true; + } + if (request == HID_SET_REPORT) + { + //uint8_t reportID = setup.wValueL; + //uint16_t length = setup.wLength; + //uint8_t data[length]; + // Make sure to not read more data than USB_EP_SIZE. + // You can read multiple times through a loop. + // The first byte (may!) contain the reportID on a multreport. + //USB_RecvControl(data, length); + } + } + + return false; +} + +HID_::HID_(void) : PluggableUSBModule(1, 1, epType), + rootNode(NULL), descriptorSize(0), + protocol(HID_REPORT_PROTOCOL), idle(1) +{ + epType[0] = EP_TYPE_INTERRUPT_IN; + PluggableUSB().plug(this); +} + +int HID_::begin(void) +{ + return 0; +} + +#endif /* if defined(USBCON) */ diff --git a/hardware/arduino/avr/libraries/HID/src/HID.h b/hardware/arduino/avr/libraries/HID/src/HID.h new file mode 100644 index 0000000000000000000000000000000000000000..93c4bd5b4ee405d8ab8249b5b93d6dcd0159ea9b --- /dev/null +++ b/hardware/arduino/avr/libraries/HID/src/HID.h @@ -0,0 +1,125 @@ +/* + Copyright (c) 2015, Arduino LLC + Original code (pre-library): Copyright (c) 2011, Peter Barrett + + Permission to use, copy, modify, and/or distribute this software for + any purpose with or without fee is hereby granted, provided that the + above copyright notice and this permission notice appear in all copies. + + THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR + BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES + OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + SOFTWARE. + */ + +#ifndef HID_h +#define HID_h + +#include +#include +#include "PluggableUSB.h" + +#if defined(USBCON) + +#define _USING_HID + +// HID 'Driver' +// ------------ +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B + +#define HID_HID_DESCRIPTOR_TYPE 0x21 +#define HID_REPORT_DESCRIPTOR_TYPE 0x22 +#define HID_PHYSICAL_DESCRIPTOR_TYPE 0x23 + +// HID subclass HID1.11 Page 8 4.2 Subclass +#define HID_SUBCLASS_NONE 0 +#define HID_SUBCLASS_BOOT_INTERFACE 1 + +// HID Keyboard/Mouse bios compatible protocols HID1.11 Page 9 4.3 Protocols +#define HID_PROTOCOL_NONE 0 +#define HID_PROTOCOL_KEYBOARD 1 +#define HID_PROTOCOL_MOUSE 2 + +// Normal or bios protocol (Keyboard/Mouse) HID1.11 Page 54 7.2.5 Get_Protocol Request +// "protocol" variable is used for this purpose. +#define HID_BOOT_PROTOCOL 0 +#define HID_REPORT_PROTOCOL 1 + +// HID Request Type HID1.11 Page 51 7.2.1 Get_Report Request +#define HID_REPORT_TYPE_INPUT 1 +#define HID_REPORT_TYPE_OUTPUT 2 +#define HID_REPORT_TYPE_FEATURE 3 + +typedef struct +{ + uint8_t len; // 9 + uint8_t dtype; // 0x21 + uint8_t addr; + uint8_t versionL; // 0x101 + uint8_t versionH; // 0x101 + uint8_t country; + uint8_t desctype; // 0x22 report + uint8_t descLenL; + uint8_t descLenH; +} HIDDescDescriptor; + +typedef struct +{ + InterfaceDescriptor hid; + HIDDescDescriptor desc; + EndpointDescriptor in; +} HIDDescriptor; + +class HIDSubDescriptor { +public: + HIDSubDescriptor *next = NULL; + HIDSubDescriptor(const void *d, const uint16_t l) : data(d), length(l) { } + + const void* data; + const uint16_t length; +}; + +class HID_ : public PluggableUSBModule +{ +public: + HID_(void); + int begin(void); + int SendReport(uint8_t id, const void* data, int len); + void AppendDescriptor(HIDSubDescriptor* node); + +protected: + // Implementation of the PluggableUSBModule + int getInterface(uint8_t* interfaceCount); + int getDescriptor(USBSetup& setup); + bool setup(USBSetup& setup); + uint8_t getShortName(char* name); + +private: + uint8_t epType[1]; + + HIDSubDescriptor* rootNode; + uint16_t descriptorSize; + + uint8_t protocol; + uint8_t idle; +}; + +// Replacement for global singleton. +// This function prevents static-initialization-order-fiasco +// https://isocpp.org/wiki/faq/ctors#static-init-order-on-first-use +HID_& HID(); + +#define D_HIDREPORT(length) { 9, 0x21, 0x01, 0x01, 0, 1, 0x22, lowByte(length), highByte(length) } + +#endif // USBCON + +#endif // HID_h diff --git a/hardware/arduino/avr/libraries/SPI/examples/BarometricPressureSensor/BarometricPressureSensor.ino b/hardware/arduino/avr/libraries/SPI/examples/BarometricPressureSensor/BarometricPressureSensor.ino new file mode 100644 index 0000000000000000000000000000000000000000..df73adeb2e502f15d2535998fb6764629e6a2ad1 --- /dev/null +++ b/hardware/arduino/avr/libraries/SPI/examples/BarometricPressureSensor/BarometricPressureSensor.ino @@ -0,0 +1,143 @@ +/* + SCP1000 Barometric Pressure Sensor Display + + Shows the output of a Barometric Pressure Sensor on a + Uses the SPI library. For details on the sensor, see: + http://www.sparkfun.com/commerce/product_info.php?products_id=8161 + http://www.vti.fi/en/support/obsolete_products/pressure_sensors/ + + This sketch adapted from Nathan Seidle's SCP1000 example for PIC: + http://www.sparkfun.com/datasheets/Sensors/SCP1000-Testing.zip + + Circuit: + SCP1000 sensor attached to pins 6, 7, 10 - 13: + DRDY: pin 6 + CSB: pin 7 + MOSI: pin 11 + MISO: pin 12 + SCK: pin 13 + + created 31 July 2010 + modified 14 August 2010 + by Tom Igoe + */ + +// the sensor communicates using SPI, so include the library: +#include + +//Sensor's memory register addresses: +const int PRESSURE = 0x1F; //3 most significant bits of pressure +const int PRESSURE_LSB = 0x20; //16 least significant bits of pressure +const int TEMPERATURE = 0x21; //16 bit temperature reading +const byte READ = 0b11111100; // SCP1000's read command +const byte WRITE = 0b00000010; // SCP1000's write command + +// pins used for the connection with the sensor +// the other you need are controlled by the SPI library): +const int dataReadyPin = 6; +const int chipSelectPin = 7; + +void setup() { + Serial.begin(9600); + + // start the SPI library: + SPI.begin(); + + // initalize the data ready and chip select pins: + pinMode(dataReadyPin, INPUT); + pinMode(chipSelectPin, OUTPUT); + + //Configure SCP1000 for low noise configuration: + writeRegister(0x02, 0x2D); + writeRegister(0x01, 0x03); + writeRegister(0x03, 0x02); + // give the sensor time to set up: + delay(100); +} + +void loop() { + //Select High Resolution Mode + writeRegister(0x03, 0x0A); + + // don't do anything until the data ready pin is high: + if (digitalRead(dataReadyPin) == HIGH) { + //Read the temperature data + int tempData = readRegister(0x21, 2); + + // convert the temperature to celsius and display it: + float realTemp = (float)tempData / 20.0; + Serial.print("Temp[C]="); + Serial.print(realTemp); + + + //Read the pressure data highest 3 bits: + byte pressure_data_high = readRegister(0x1F, 1); + pressure_data_high &= 0b00000111; //you only needs bits 2 to 0 + + //Read the pressure data lower 16 bits: + unsigned int pressure_data_low = readRegister(0x20, 2); + //combine the two parts into one 19-bit number: + long pressure = ((pressure_data_high << 16) | pressure_data_low) / 4; + + // display the temperature: + Serial.println("\tPressure [Pa]=" + String(pressure)); + } +} + +//Read from or write to register from the SCP1000: +unsigned int readRegister(byte thisRegister, int bytesToRead) { + byte inByte = 0; // incoming byte from the SPI + unsigned int result = 0; // result to return + Serial.print(thisRegister, BIN); + Serial.print("\t"); + // SCP1000 expects the register name in the upper 6 bits + // of the byte. So shift the bits left by two bits: + thisRegister = thisRegister << 2; + // now combine the address and the command into one byte + byte dataToSend = thisRegister & READ; + Serial.println(thisRegister, BIN); + // take the chip select low to select the device: + digitalWrite(chipSelectPin, LOW); + // send the device the register you want to read: + SPI.transfer(dataToSend); + // send a value of 0 to read the first byte returned: + result = SPI.transfer(0x00); + // decrement the number of bytes left to read: + bytesToRead--; + // if you still have another byte to read: + if (bytesToRead > 0) { + // shift the first byte left, then get the second byte: + result = result << 8; + inByte = SPI.transfer(0x00); + // combine the byte you just got with the previous one: + result = result | inByte; + // decrement the number of bytes left to read: + bytesToRead--; + } + // take the chip select high to de-select: + digitalWrite(chipSelectPin, HIGH); + // return the result: + return (result); +} + + +//Sends a write command to SCP1000 + +void writeRegister(byte thisRegister, byte thisValue) { + + // SCP1000 expects the register address in the upper 6 bits + // of the byte. So shift the bits left by two bits: + thisRegister = thisRegister << 2; + // now combine the register address and the command into one byte: + byte dataToSend = thisRegister | WRITE; + + // take the chip select low to select the device: + digitalWrite(chipSelectPin, LOW); + + SPI.transfer(dataToSend); //Send register location + SPI.transfer(thisValue); //Send value to record into register + + // take the chip select high to de-select: + digitalWrite(chipSelectPin, HIGH); +} + diff --git a/hardware/arduino/avr/libraries/SPI/examples/DigitalPotControl/DigitalPotControl.ino b/hardware/arduino/avr/libraries/SPI/examples/DigitalPotControl/DigitalPotControl.ino new file mode 100644 index 0000000000000000000000000000000000000000..8719058e75c14a2cee65cc1199f6c424d40e83b2 --- /dev/null +++ b/hardware/arduino/avr/libraries/SPI/examples/DigitalPotControl/DigitalPotControl.ino @@ -0,0 +1,73 @@ +/* + Digital Pot Control + + This example controls an Analog Devices AD5206 digital potentiometer. + The AD5206 has 6 potentiometer channels. Each channel's pins are labeled + A - connect this to voltage + W - this is the pot's wiper, which changes when you set it + B - connect this to ground. + + The AD5206 is SPI-compatible,and to command it, you send two bytes, + one with the channel number (0 - 5) and one with the resistance value for the + channel (0 - 255). + + The circuit: + * All A pins of AD5206 connected to +5V + * All B pins of AD5206 connected to ground + * An LED and a 220-ohm resisor in series connected from each W pin to ground + * CS - to digital pin 10 (SS pin) + * SDI - to digital pin 11 (MOSI pin) + * CLK - to digital pin 13 (SCK pin) + + created 10 Aug 2010 + by Tom Igoe + + Thanks to Heather Dewey-Hagborg for the original tutorial, 2005 + +*/ + + +// inslude the SPI library: +#include + + +// set pin 10 as the slave select for the digital pot: +const int slaveSelectPin = 10; + +void setup() { + // set the slaveSelectPin as an output: + pinMode(slaveSelectPin, OUTPUT); + // initialize SPI: + SPI.begin(); +} + +void loop() { + // go through the six channels of the digital pot: + for (int channel = 0; channel < 6; channel++) { + // change the resistance on this channel from min to max: + for (int level = 0; level < 255; level++) { + digitalPotWrite(channel, level); + delay(10); + } + // wait a second at the top: + delay(100); + // change the resistance on this channel from max to min: + for (int level = 0; level < 255; level++) { + digitalPotWrite(channel, 255 - level); + delay(10); + } + } + +} + +void digitalPotWrite(int address, int value) { + // take the SS pin low to select the chip: + digitalWrite(slaveSelectPin, LOW); + delay(100); + // send in the address and value via SPI: + SPI.transfer(address); + SPI.transfer(value); + delay(100); + // take the SS pin high to de-select the chip: + digitalWrite(slaveSelectPin, HIGH); +} diff --git a/hardware/arduino/avr/libraries/SPI/keywords.txt b/hardware/arduino/avr/libraries/SPI/keywords.txt new file mode 100644 index 0000000000000000000000000000000000000000..fa7616581aa685f98ed36c2dbc50cd1de3ccb641 --- /dev/null +++ b/hardware/arduino/avr/libraries/SPI/keywords.txt @@ -0,0 +1,36 @@ +####################################### +# Syntax Coloring Map SPI +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +SPI KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### +begin KEYWORD2 +end KEYWORD2 +transfer KEYWORD2 +setBitOrder KEYWORD2 +setDataMode KEYWORD2 +setClockDivider KEYWORD2 + + +####################################### +# Constants (LITERAL1) +####################################### +SPI_CLOCK_DIV4 LITERAL1 +SPI_CLOCK_DIV16 LITERAL1 +SPI_CLOCK_DIV64 LITERAL1 +SPI_CLOCK_DIV128 LITERAL1 +SPI_CLOCK_DIV2 LITERAL1 +SPI_CLOCK_DIV8 LITERAL1 +SPI_CLOCK_DIV32 LITERAL1 +SPI_CLOCK_DIV64 LITERAL1 +SPI_MODE0 LITERAL1 +SPI_MODE1 LITERAL1 +SPI_MODE2 LITERAL1 +SPI_MODE3 LITERAL1 \ No newline at end of file diff --git a/hardware/arduino/avr/libraries/SPI/library.properties b/hardware/arduino/avr/libraries/SPI/library.properties new file mode 100644 index 0000000000000000000000000000000000000000..4ed8db90e99528a5cd068d1adea5e966a0b8be3b --- /dev/null +++ b/hardware/arduino/avr/libraries/SPI/library.properties @@ -0,0 +1,10 @@ +name=SPI +version=1.0 +author=Arduino +maintainer=Arduino +sentence=Enables the communication with devices that use the Serial Peripheral Interface (SPI) Bus. +paragraph=SPI is a synchronous serial data protocol used by microcontrollers for communicating with one or more peripheral devices quickly over short distances. It uses three lines common to all devices (MISO, MOSI and SCK) and one specific for each device. +category=Communication +url=http://www.arduino.cc/en/Reference/SPI +architectures=avr + diff --git a/hardware/arduino/avr/libraries/SPI/src/SPI.cpp b/hardware/arduino/avr/libraries/SPI/src/SPI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..af14e07b12fa251b81a53f4462c8ad0870cd4aed --- /dev/null +++ b/hardware/arduino/avr/libraries/SPI/src/SPI.cpp @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2010 by Cristian Maglie + * Copyright (c) 2014 by Paul Stoffregen (Transaction API) + * Copyright (c) 2014 by Matthijs Kooijman (SPISettings AVR) + * Copyright (c) 2014 by Andrew J. Kroll (atomicity fixes) + * SPI Master library for arduino. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of either the GNU General Public License version 2 + * or the GNU Lesser General Public License version 2.1, both as + * published by the Free Software Foundation. + */ + +#include "SPI.h" + +SPIClass SPI; + +uint8_t SPIClass::initialized = 0; +uint8_t SPIClass::interruptMode = 0; +uint8_t SPIClass::interruptMask = 0; +uint8_t SPIClass::interruptSave = 0; +#ifdef SPI_TRANSACTION_MISMATCH_LED +uint8_t SPIClass::inTransactionFlag = 0; +#endif + +void SPIClass::begin() +{ + uint8_t sreg = SREG; + noInterrupts(); // Protect from a scheduler and prevent transactionBegin + if (!initialized) { + // Set SS to high so a connected chip will be "deselected" by default + uint8_t port = digitalPinToPort(SS); + uint8_t bit = digitalPinToBitMask(SS); + volatile uint8_t *reg = portModeRegister(port); + + // if the SS pin is not already configured as an output + // then set it high (to enable the internal pull-up resistor) + if(!(*reg & bit)){ + digitalWrite(SS, HIGH); + } + + // When the SS pin is set as OUTPUT, it can be used as + // a general purpose output port (it doesn't influence + // SPI operations). + pinMode(SS, OUTPUT); + + // Warning: if the SS pin ever becomes a LOW INPUT then SPI + // automatically switches to Slave, so the data direction of + // the SS pin MUST be kept as OUTPUT. + SPCR |= _BV(MSTR); + SPCR |= _BV(SPE); + + // Set direction register for SCK and MOSI pin. + // MISO pin automatically overrides to INPUT. + // By doing this AFTER enabling SPI, we avoid accidentally + // clocking in a single bit since the lines go directly + // from "input" to SPI control. + // http://code.google.com/p/arduino/issues/detail?id=888 + pinMode(SCK, OUTPUT); + pinMode(MOSI, OUTPUT); + } + initialized++; // reference count + SREG = sreg; +} + +void SPIClass::end() { + uint8_t sreg = SREG; + noInterrupts(); // Protect from a scheduler and prevent transactionBegin + // Decrease the reference counter + if (initialized) + initialized--; + // If there are no more references disable SPI + if (!initialized) { + SPCR &= ~_BV(SPE); + interruptMode = 0; + #ifdef SPI_TRANSACTION_MISMATCH_LED + inTransactionFlag = 0; + #endif + } + SREG = sreg; +} + +// mapping of interrupt numbers to bits within SPI_AVR_EIMSK +#if defined(__AVR_ATmega32U4__) + #define SPI_INT0_MASK (1< + * Copyright (c) 2014 by Paul Stoffregen (Transaction API) + * Copyright (c) 2014 by Matthijs Kooijman (SPISettings AVR) + * Copyright (c) 2014 by Andrew J. Kroll (atomicity fixes) + * SPI Master library for arduino. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of either the GNU General Public License version 2 + * or the GNU Lesser General Public License version 2.1, both as + * published by the Free Software Foundation. + */ + +#ifndef _SPI_H_INCLUDED +#define _SPI_H_INCLUDED + +#include + +// SPI_HAS_TRANSACTION means SPI has beginTransaction(), endTransaction(), +// usingInterrupt(), and SPISetting(clock, bitOrder, dataMode) +#define SPI_HAS_TRANSACTION 1 + +// SPI_HAS_NOTUSINGINTERRUPT means that SPI has notUsingInterrupt() method +#define SPI_HAS_NOTUSINGINTERRUPT 1 + +// SPI_ATOMIC_VERSION means that SPI has atomicity fixes and what version. +// This way when there is a bug fix you can check this define to alert users +// of your code if it uses better version of this library. +// This also implies everything that SPI_HAS_TRANSACTION as documented above is +// available too. +#define SPI_ATOMIC_VERSION 1 + +// Uncomment this line to add detection of mismatched begin/end transactions. +// A mismatch occurs if other libraries fail to use SPI.endTransaction() for +// each SPI.beginTransaction(). Connect an LED to this pin. The LED will turn +// on if any mismatch is ever detected. +//#define SPI_TRANSACTION_MISMATCH_LED 5 + +#ifndef LSBFIRST +#define LSBFIRST 0 +#endif +#ifndef MSBFIRST +#define MSBFIRST 1 +#endif + +#define SPI_CLOCK_DIV4 0x00 +#define SPI_CLOCK_DIV16 0x01 +#define SPI_CLOCK_DIV64 0x02 +#define SPI_CLOCK_DIV128 0x03 +#define SPI_CLOCK_DIV2 0x04 +#define SPI_CLOCK_DIV8 0x05 +#define SPI_CLOCK_DIV32 0x06 + +#define SPI_MODE0 0x00 +#define SPI_MODE1 0x04 +#define SPI_MODE2 0x08 +#define SPI_MODE3 0x0C + +#define SPI_MODE_MASK 0x0C // CPOL = bit 3, CPHA = bit 2 on SPCR +#define SPI_CLOCK_MASK 0x03 // SPR1 = bit 1, SPR0 = bit 0 on SPCR +#define SPI_2XCLOCK_MASK 0x01 // SPI2X = bit 0 on SPSR + +// define SPI_AVR_EIMSK for AVR boards with external interrupt pins +#if defined(EIMSK) + #define SPI_AVR_EIMSK EIMSK +#elif defined(GICR) + #define SPI_AVR_EIMSK GICR +#elif defined(GIMSK) + #define SPI_AVR_EIMSK GIMSK +#endif + +class SPISettings { +public: + SPISettings(uint32_t clock, uint8_t bitOrder, uint8_t dataMode) { + if (__builtin_constant_p(clock)) { + init_AlwaysInline(clock, bitOrder, dataMode); + } else { + init_MightInline(clock, bitOrder, dataMode); + } + } + SPISettings() { + init_AlwaysInline(4000000, MSBFIRST, SPI_MODE0); + } +private: + void init_MightInline(uint32_t clock, uint8_t bitOrder, uint8_t dataMode) { + init_AlwaysInline(clock, bitOrder, dataMode); + } + void init_AlwaysInline(uint32_t clock, uint8_t bitOrder, uint8_t dataMode) + __attribute__((__always_inline__)) { + // Clock settings are defined as follows. Note that this shows SPI2X + // inverted, so the bits form increasing numbers. Also note that + // fosc/64 appears twice + // SPR1 SPR0 ~SPI2X Freq + // 0 0 0 fosc/2 + // 0 0 1 fosc/4 + // 0 1 0 fosc/8 + // 0 1 1 fosc/16 + // 1 0 0 fosc/32 + // 1 0 1 fosc/64 + // 1 1 0 fosc/64 + // 1 1 1 fosc/128 + + // We find the fastest clock that is less than or equal to the + // given clock rate. The clock divider that results in clock_setting + // is 2 ^^ (clock_div + 1). If nothing is slow enough, we'll use the + // slowest (128 == 2 ^^ 7, so clock_div = 6). + uint8_t clockDiv; + + // When the clock is known at compiletime, use this if-then-else + // cascade, which the compiler knows how to completely optimize + // away. When clock is not known, use a loop instead, which generates + // shorter code. + if (__builtin_constant_p(clock)) { + if (clock >= F_CPU / 2) { + clockDiv = 0; + } else if (clock >= F_CPU / 4) { + clockDiv = 1; + } else if (clock >= F_CPU / 8) { + clockDiv = 2; + } else if (clock >= F_CPU / 16) { + clockDiv = 3; + } else if (clock >= F_CPU / 32) { + clockDiv = 4; + } else if (clock >= F_CPU / 64) { + clockDiv = 5; + } else { + clockDiv = 6; + } + } else { + uint32_t clockSetting = F_CPU / 2; + clockDiv = 0; + while (clockDiv < 6 && clock < clockSetting) { + clockSetting /= 2; + clockDiv++; + } + } + + // Compensate for the duplicate fosc/64 + if (clockDiv == 6) + clockDiv = 7; + + // Invert the SPI2X bit + clockDiv ^= 0x1; + + // Pack into the SPISettings class + spcr = _BV(SPE) | _BV(MSTR) | ((bitOrder == LSBFIRST) ? _BV(DORD) : 0) | + (dataMode & SPI_MODE_MASK) | ((clockDiv >> 1) & SPI_CLOCK_MASK); + spsr = clockDiv & SPI_2XCLOCK_MASK; + } + uint8_t spcr; + uint8_t spsr; + friend class SPIClass; +}; + + +class SPIClass { +public: + // Initialize the SPI library + static void begin(); + + // If SPI is used from within an interrupt, this function registers + // that interrupt with the SPI library, so beginTransaction() can + // prevent conflicts. The input interruptNumber is the number used + // with attachInterrupt. If SPI is used from a different interrupt + // (eg, a timer), interruptNumber should be 255. + static void usingInterrupt(uint8_t interruptNumber); + // And this does the opposite. + static void notUsingInterrupt(uint8_t interruptNumber); + // Note: the usingInterrupt and notUsingInterrupt functions should + // not to be called from ISR context or inside a transaction. + // For details see: + // https://github.com/arduino/Arduino/pull/2381 + // https://github.com/arduino/Arduino/pull/2449 + + // Before using SPI.transfer() or asserting chip select pins, + // this function is used to gain exclusive access to the SPI bus + // and configure the correct settings. + inline static void beginTransaction(SPISettings settings) { + if (interruptMode > 0) { + uint8_t sreg = SREG; + noInterrupts(); + + #ifdef SPI_AVR_EIMSK + if (interruptMode == 1) { + interruptSave = SPI_AVR_EIMSK; + SPI_AVR_EIMSK &= ~interruptMask; + SREG = sreg; + } else + #endif + { + interruptSave = sreg; + } + } + + #ifdef SPI_TRANSACTION_MISMATCH_LED + if (inTransactionFlag) { + pinMode(SPI_TRANSACTION_MISMATCH_LED, OUTPUT); + digitalWrite(SPI_TRANSACTION_MISMATCH_LED, HIGH); + } + inTransactionFlag = 1; + #endif + + SPCR = settings.spcr; + SPSR = settings.spsr; + } + + // Write to the SPI bus (MOSI pin) and also receive (MISO pin) + inline static uint8_t transfer(uint8_t data) { + SPDR = data; + /* + * The following NOP introduces a small delay that can prevent the wait + * loop form iterating when running at the maximum speed. This gives + * about 10% more speed, even if it seems counter-intuitive. At lower + * speeds it is unnoticed. + */ + asm volatile("nop"); + while (!(SPSR & _BV(SPIF))) ; // wait + return SPDR; + } + inline static uint16_t transfer16(uint16_t data) { + union { uint16_t val; struct { uint8_t lsb; uint8_t msb; }; } in, out; + in.val = data; + if (!(SPCR & _BV(DORD))) { + SPDR = in.msb; + asm volatile("nop"); // See transfer(uint8_t) function + while (!(SPSR & _BV(SPIF))) ; + out.msb = SPDR; + SPDR = in.lsb; + asm volatile("nop"); + while (!(SPSR & _BV(SPIF))) ; + out.lsb = SPDR; + } else { + SPDR = in.lsb; + asm volatile("nop"); + while (!(SPSR & _BV(SPIF))) ; + out.lsb = SPDR; + SPDR = in.msb; + asm volatile("nop"); + while (!(SPSR & _BV(SPIF))) ; + out.msb = SPDR; + } + return out.val; + } + inline static void transfer(void *buf, size_t count) { + if (count == 0) return; + uint8_t *p = (uint8_t *)buf; + SPDR = *p; + while (--count > 0) { + uint8_t out = *(p + 1); + while (!(SPSR & _BV(SPIF))) ; + uint8_t in = SPDR; + SPDR = out; + *p++ = in; + } + while (!(SPSR & _BV(SPIF))) ; + *p = SPDR; + } + // After performing a group of transfers and releasing the chip select + // signal, this function allows others to access the SPI bus + inline static void endTransaction(void) { + #ifdef SPI_TRANSACTION_MISMATCH_LED + if (!inTransactionFlag) { + pinMode(SPI_TRANSACTION_MISMATCH_LED, OUTPUT); + digitalWrite(SPI_TRANSACTION_MISMATCH_LED, HIGH); + } + inTransactionFlag = 0; + #endif + + if (interruptMode > 0) { + #ifdef SPI_AVR_EIMSK + uint8_t sreg = SREG; + #endif + noInterrupts(); + #ifdef SPI_AVR_EIMSK + if (interruptMode == 1) { + SPI_AVR_EIMSK = interruptSave; + SREG = sreg; + } else + #endif + { + SREG = interruptSave; + } + } + } + + // Disable the SPI bus + static void end(); + + // This function is deprecated. New applications should use + // beginTransaction() to configure SPI settings. + inline static void setBitOrder(uint8_t bitOrder) { + if (bitOrder == LSBFIRST) SPCR |= _BV(DORD); + else SPCR &= ~(_BV(DORD)); + } + // This function is deprecated. New applications should use + // beginTransaction() to configure SPI settings. + inline static void setDataMode(uint8_t dataMode) { + SPCR = (SPCR & ~SPI_MODE_MASK) | dataMode; + } + // This function is deprecated. New applications should use + // beginTransaction() to configure SPI settings. + inline static void setClockDivider(uint8_t clockDiv) { + SPCR = (SPCR & ~SPI_CLOCK_MASK) | (clockDiv & SPI_CLOCK_MASK); + SPSR = (SPSR & ~SPI_2XCLOCK_MASK) | ((clockDiv >> 2) & SPI_2XCLOCK_MASK); + } + // These undocumented functions should not be used. SPI.transfer() + // polls the hardware flag which is automatically cleared as the + // AVR responds to SPI's interrupt + inline static void attachInterrupt() { SPCR |= _BV(SPIE); } + inline static void detachInterrupt() { SPCR &= ~_BV(SPIE); } + +private: + static uint8_t initialized; + static uint8_t interruptMode; // 0=none, 1=mask, 2=global + static uint8_t interruptMask; // which interrupts to mask + static uint8_t interruptSave; // temp storage, to restore state + #ifdef SPI_TRANSACTION_MISMATCH_LED + static uint8_t inTransactionFlag; + #endif +}; + +extern SPIClass SPI; + +#endif diff --git a/hardware/arduino/avr/libraries/SoftwareSerial/examples/SoftwareSerialExample/SoftwareSerialExample.ino b/hardware/arduino/avr/libraries/SoftwareSerial/examples/SoftwareSerialExample/SoftwareSerialExample.ino new file mode 100644 index 0000000000000000000000000000000000000000..61ce88c62962b98f55bd461876fec791b7554414 --- /dev/null +++ b/hardware/arduino/avr/libraries/SoftwareSerial/examples/SoftwareSerialExample/SoftwareSerialExample.ino @@ -0,0 +1,55 @@ +/* + Software serial multple serial test + + Receives from the hardware serial, sends to software serial. + Receives from software serial, sends to hardware serial. + + The circuit: + * RX is digital pin 10 (connect to TX of other device) + * TX is digital pin 11 (connect to RX of other device) + + Note: + Not all pins on the Mega and Mega 2560 support change interrupts, + so only the following can be used for RX: + 10, 11, 12, 13, 50, 51, 52, 53, 62, 63, 64, 65, 66, 67, 68, 69 + + Not all pins on the Leonardo and Micro support change interrupts, + so only the following can be used for RX: + 8, 9, 10, 11, 14 (MISO), 15 (SCK), 16 (MOSI). + + created back in the mists of time + modified 25 May 2012 + by Tom Igoe + based on Mikal Hart's example + + This example code is in the public domain. + + */ +#include + +SoftwareSerial mySerial(10, 11); // RX, TX + +void setup() { + // Open serial communications and wait for port to open: + Serial.begin(57600); + while (!Serial) { + ; // wait for serial port to connect. Needed for native USB port only + } + + + Serial.println("Goodnight moon!"); + + // set the data rate for the SoftwareSerial port + mySerial.begin(4800); + mySerial.println("Hello, world?"); +} + +void loop() { // run over and over + if (mySerial.available()) { + Serial.write(mySerial.read()); + } + if (Serial.available()) { + mySerial.write(Serial.read()); + } +} + diff --git a/hardware/arduino/avr/libraries/SoftwareSerial/examples/TwoPortReceive/TwoPortReceive.ino b/hardware/arduino/avr/libraries/SoftwareSerial/examples/TwoPortReceive/TwoPortReceive.ino new file mode 100644 index 0000000000000000000000000000000000000000..8d7f93e8f2e5863f5cfe0d8a29782e4a3f2f783f --- /dev/null +++ b/hardware/arduino/avr/libraries/SoftwareSerial/examples/TwoPortReceive/TwoPortReceive.ino @@ -0,0 +1,91 @@ +/* + Software serial multple serial test + + Receives from the two software serial ports, + sends to the hardware serial port. + + In order to listen on a software port, you call port.listen(). + When using two software serial ports, you have to switch ports + by listen()ing on each one in turn. Pick a logical time to switch + ports, like the end of an expected transmission, or when the + buffer is empty. This example switches ports when there is nothing + more to read from a port + + The circuit: + Two devices which communicate serially are needed. + * First serial device's TX attached to digital pin 10(RX), RX to pin 11(TX) + * Second serial device's TX attached to digital pin 8(RX), RX to pin 9(TX) + + Note: + Not all pins on the Mega and Mega 2560 support change interrupts, + so only the following can be used for RX: + 10, 11, 12, 13, 50, 51, 52, 53, 62, 63, 64, 65, 66, 67, 68, 69 + + Not all pins on the Leonardo support change interrupts, + so only the following can be used for RX: + 8, 9, 10, 11, 14 (MISO), 15 (SCK), 16 (MOSI). + + created 18 Apr. 2011 + modified 19 March 2016 + by Tom Igoe + based on Mikal Hart's twoPortRXExample + + This example code is in the public domain. + + */ + +#include +// software serial #1: RX = digital pin 10, TX = digital pin 11 +SoftwareSerial portOne(10, 11); + +// software serial #2: RX = digital pin 8, TX = digital pin 9 +// on the Mega, use other pins instead, since 8 and 9 don't work on the Mega +SoftwareSerial portTwo(8, 9); + +void setup() { + // Open serial communications and wait for port to open: + Serial.begin(9600); + while (!Serial) { + ; // wait for serial port to connect. Needed for native USB port only + } + + + // Start each software serial port + portOne.begin(9600); + portTwo.begin(9600); +} + +void loop() { + // By default, the last intialized port is listening. + // when you want to listen on a port, explicitly select it: + portOne.listen(); + Serial.println("Data from port one:"); + // while there is data coming in, read it + // and send to the hardware serial port: + while (portOne.available() > 0) { + char inByte = portOne.read(); + Serial.write(inByte); + } + + // blank line to separate data from the two ports: + Serial.println(); + + // Now listen on the second port + portTwo.listen(); + // while there is data coming in, read it + // and send to the hardware serial port: + Serial.println("Data from port two:"); + while (portTwo.available() > 0) { + char inByte = portTwo.read(); + Serial.write(inByte); + } + + // blank line to separate data from the two ports: + Serial.println(); +} + + + + + + diff --git a/hardware/arduino/avr/libraries/SoftwareSerial/keywords.txt b/hardware/arduino/avr/libraries/SoftwareSerial/keywords.txt new file mode 100644 index 0000000000000000000000000000000000000000..aaea17c202275b35a553623d41d30a3858c02e71 --- /dev/null +++ b/hardware/arduino/avr/libraries/SoftwareSerial/keywords.txt @@ -0,0 +1,30 @@ +####################################### +# Syntax Coloring Map for SoftwareSerial +# (formerly NewSoftSerial) +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +SoftwareSerial KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +begin KEYWORD2 +end KEYWORD2 +read KEYWORD2 +write KEYWORD2 +available KEYWORD2 +isListening KEYWORD2 +overflow KEYWORD2 +flush KEYWORD2 +listen KEYWORD2 +peek KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### + diff --git a/hardware/arduino/avr/libraries/SoftwareSerial/library.properties b/hardware/arduino/avr/libraries/SoftwareSerial/library.properties new file mode 100644 index 0000000000000000000000000000000000000000..6d20a49cf0ce5809f6c6608cbb5615c97fcc6234 --- /dev/null +++ b/hardware/arduino/avr/libraries/SoftwareSerial/library.properties @@ -0,0 +1,10 @@ +name=SoftwareSerial +version=1.0 +author=Arduino +maintainer=Arduino +sentence=Enables serial communication on any digital pin. +paragraph=The SoftwareSerial library has been developed to allow serial communication on any digital pin of the board, using software to replicate the functionality of the hardware UART. It is possible to have multiple software serial ports with speeds up to 115200 bps. +category=Communication +url=http://www.arduino.cc/en/Reference/SoftwareSerial +architectures=avr + diff --git a/hardware/arduino/avr/libraries/SoftwareSerial/src/SoftwareSerial.cpp b/hardware/arduino/avr/libraries/SoftwareSerial/src/SoftwareSerial.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3163d7a3174e1e7a321148f8a8f86a78b79198a4 --- /dev/null +++ b/hardware/arduino/avr/libraries/SoftwareSerial/src/SoftwareSerial.cpp @@ -0,0 +1,486 @@ +/* +SoftwareSerial.cpp (formerly NewSoftSerial.cpp) - +Multi-instance software serial library for Arduino/Wiring +-- Interrupt-driven receive and other improvements by ladyada + (http://ladyada.net) +-- Tuning, circular buffer, derivation from class Print/Stream, + multi-instance support, porting to 8MHz processors, + various optimizations, PROGMEM delay tables, inverse logic and + direct port writing by Mikal Hart (http://www.arduiniana.org) +-- Pin change interrupt macros by Paul Stoffregen (http://www.pjrc.com) +-- 20MHz processor support by Garrett Mace (http://www.macetech.com) +-- ATmega1280/2560 support by Brett Hagman (http://www.roguerobotics.com/) + +This library is free software; you can redistribute it and/or +modify it under the terms of the GNU Lesser General Public +License as published by the Free Software Foundation; either +version 2.1 of the License, or (at your option) any later version. + +This library is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Lesser General Public License for more details. + +You should have received a copy of the GNU Lesser General Public +License along with this library; if not, write to the Free Software +Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +The latest version of this library can always be found at +http://arduiniana.org. +*/ + +// When set, _DEBUG co-opts pins 11 and 13 for debugging with an +// oscilloscope or logic analyzer. Beware: it also slightly modifies +// the bit times, so don't rely on it too much at high baud rates +#define _DEBUG 0 +#define _DEBUG_PIN1 11 +#define _DEBUG_PIN2 13 +// +// Includes +// +#include +#include +#include +#include +#include + +// +// Statics +// +SoftwareSerial *SoftwareSerial::active_object = 0; +uint8_t SoftwareSerial::_receive_buffer[_SS_MAX_RX_BUFF]; +volatile uint8_t SoftwareSerial::_receive_buffer_tail = 0; +volatile uint8_t SoftwareSerial::_receive_buffer_head = 0; + +// +// Debugging +// +// This function generates a brief pulse +// for debugging or measuring on an oscilloscope. +#if _DEBUG +inline void DebugPulse(uint8_t pin, uint8_t count) +{ + volatile uint8_t *pport = portOutputRegister(digitalPinToPort(pin)); + + uint8_t val = *pport; + while (count--) + { + *pport = val | digitalPinToBitMask(pin); + *pport = val; + } +} +#else +inline void DebugPulse(uint8_t, uint8_t) {} +#endif + +// +// Private methods +// + +/* static */ +inline void SoftwareSerial::tunedDelay(uint16_t delay) { + _delay_loop_2(delay); +} + +// This function sets the current object as the "listening" +// one and returns true if it replaces another +bool SoftwareSerial::listen() +{ + if (!_rx_delay_stopbit) + return false; + + if (active_object != this) + { + if (active_object) + active_object->stopListening(); + + _buffer_overflow = false; + _receive_buffer_head = _receive_buffer_tail = 0; + active_object = this; + + setRxIntMsk(true); + return true; + } + + return false; +} + +// Stop listening. Returns true if we were actually listening. +bool SoftwareSerial::stopListening() +{ + if (active_object == this) + { + setRxIntMsk(false); + active_object = NULL; + return true; + } + return false; +} + +// +// The receive routine called by the interrupt handler +// +void SoftwareSerial::recv() +{ + +#if GCC_VERSION < 40302 +// Work-around for avr-gcc 4.3.0 OSX version bug +// Preserve the registers that the compiler misses +// (courtesy of Arduino forum user *etracer*) + asm volatile( + "push r18 \n\t" + "push r19 \n\t" + "push r20 \n\t" + "push r21 \n\t" + "push r22 \n\t" + "push r23 \n\t" + "push r26 \n\t" + "push r27 \n\t" + ::); +#endif + + uint8_t d = 0; + + // If RX line is high, then we don't see any start bit + // so interrupt is probably not for us + if (_inverse_logic ? rx_pin_read() : !rx_pin_read()) + { + // Disable further interrupts during reception, this prevents + // triggering another interrupt directly after we return, which can + // cause problems at higher baudrates. + setRxIntMsk(false); + + // Wait approximately 1/2 of a bit width to "center" the sample + tunedDelay(_rx_delay_centering); + DebugPulse(_DEBUG_PIN2, 1); + + // Read each of the 8 bits + for (uint8_t i=8; i > 0; --i) + { + tunedDelay(_rx_delay_intrabit); + d >>= 1; + DebugPulse(_DEBUG_PIN2, 1); + if (rx_pin_read()) + d |= 0x80; + } + + if (_inverse_logic) + d = ~d; + + // if buffer full, set the overflow flag and return + uint8_t next = (_receive_buffer_tail + 1) % _SS_MAX_RX_BUFF; + if (next != _receive_buffer_head) + { + // save new data in buffer: tail points to where byte goes + _receive_buffer[_receive_buffer_tail] = d; // save new byte + _receive_buffer_tail = next; + } + else + { + DebugPulse(_DEBUG_PIN1, 1); + _buffer_overflow = true; + } + + // skip the stop bit + tunedDelay(_rx_delay_stopbit); + DebugPulse(_DEBUG_PIN1, 1); + + // Re-enable interrupts when we're sure to be inside the stop bit + setRxIntMsk(true); + + } + +#if GCC_VERSION < 40302 +// Work-around for avr-gcc 4.3.0 OSX version bug +// Restore the registers that the compiler misses + asm volatile( + "pop r27 \n\t" + "pop r26 \n\t" + "pop r23 \n\t" + "pop r22 \n\t" + "pop r21 \n\t" + "pop r20 \n\t" + "pop r19 \n\t" + "pop r18 \n\t" + ::); +#endif +} + +uint8_t SoftwareSerial::rx_pin_read() +{ + return *_receivePortRegister & _receiveBitMask; +} + +// +// Interrupt handling +// + +/* static */ +inline void SoftwareSerial::handle_interrupt() +{ + if (active_object) + { + active_object->recv(); + } +} + +#if defined(PCINT0_vect) +ISR(PCINT0_vect) +{ + SoftwareSerial::handle_interrupt(); +} +#endif + +#if defined(PCINT1_vect) +ISR(PCINT1_vect, ISR_ALIASOF(PCINT0_vect)); +#endif + +#if defined(PCINT2_vect) +ISR(PCINT2_vect, ISR_ALIASOF(PCINT0_vect)); +#endif + +#if defined(PCINT3_vect) +ISR(PCINT3_vect, ISR_ALIASOF(PCINT0_vect)); +#endif + +// +// Constructor +// +SoftwareSerial::SoftwareSerial(uint8_t receivePin, uint8_t transmitPin, bool inverse_logic /* = false */) : + _rx_delay_centering(0), + _rx_delay_intrabit(0), + _rx_delay_stopbit(0), + _tx_delay(0), + _buffer_overflow(false), + _inverse_logic(inverse_logic) +{ + setTX(transmitPin); + setRX(receivePin); +} + +// +// Destructor +// +SoftwareSerial::~SoftwareSerial() +{ + end(); +} + +void SoftwareSerial::setTX(uint8_t tx) +{ + // First write, then set output. If we do this the other way around, + // the pin would be output low for a short while before switching to + // output high. Now, it is input with pullup for a short while, which + // is fine. With inverse logic, either order is fine. + digitalWrite(tx, _inverse_logic ? LOW : HIGH); + pinMode(tx, OUTPUT); + _transmitBitMask = digitalPinToBitMask(tx); + uint8_t port = digitalPinToPort(tx); + _transmitPortRegister = portOutputRegister(port); +} + +void SoftwareSerial::setRX(uint8_t rx) +{ + pinMode(rx, INPUT); + if (!_inverse_logic) + digitalWrite(rx, HIGH); // pullup for normal logic! + _receivePin = rx; + _receiveBitMask = digitalPinToBitMask(rx); + uint8_t port = digitalPinToPort(rx); + _receivePortRegister = portInputRegister(port); +} + +uint16_t SoftwareSerial::subtract_cap(uint16_t num, uint16_t sub) { + if (num > sub) + return num - sub; + else + return 1; +} + +// +// Public methods +// + +void SoftwareSerial::begin(long speed) +{ + _rx_delay_centering = _rx_delay_intrabit = _rx_delay_stopbit = _tx_delay = 0; + + // Precalculate the various delays, in number of 4-cycle delays + uint16_t bit_delay = (F_CPU / speed) / 4; + + // 12 (gcc 4.8.2) or 13 (gcc 4.3.2) cycles from start bit to first bit, + // 15 (gcc 4.8.2) or 16 (gcc 4.3.2) cycles between bits, + // 12 (gcc 4.8.2) or 14 (gcc 4.3.2) cycles from last bit to stop bit + // These are all close enough to just use 15 cycles, since the inter-bit + // timings are the most critical (deviations stack 8 times) + _tx_delay = subtract_cap(bit_delay, 15 / 4); + + // Only setup rx when we have a valid PCINT for this pin + if (digitalPinToPCICR((int8_t)_receivePin)) { + #if GCC_VERSION > 40800 + // Timings counted from gcc 4.8.2 output. This works up to 115200 on + // 16Mhz and 57600 on 8Mhz. + // + // When the start bit occurs, there are 3 or 4 cycles before the + // interrupt flag is set, 4 cycles before the PC is set to the right + // interrupt vector address and the old PC is pushed on the stack, + // and then 75 cycles of instructions (including the RJMP in the + // ISR vector table) until the first delay. After the delay, there + // are 17 more cycles until the pin value is read (excluding the + // delay in the loop). + // We want to have a total delay of 1.5 bit time. Inside the loop, + // we already wait for 1 bit time - 23 cycles, so here we wait for + // 0.5 bit time - (71 + 18 - 22) cycles. + _rx_delay_centering = subtract_cap(bit_delay / 2, (4 + 4 + 75 + 17 - 23) / 4); + + // There are 23 cycles in each loop iteration (excluding the delay) + _rx_delay_intrabit = subtract_cap(bit_delay, 23 / 4); + + // There are 37 cycles from the last bit read to the start of + // stopbit delay and 11 cycles from the delay until the interrupt + // mask is enabled again (which _must_ happen during the stopbit). + // This delay aims at 3/4 of a bit time, meaning the end of the + // delay will be at 1/4th of the stopbit. This allows some extra + // time for ISR cleanup, which makes 115200 baud at 16Mhz work more + // reliably + _rx_delay_stopbit = subtract_cap(bit_delay * 3 / 4, (37 + 11) / 4); + #else // Timings counted from gcc 4.3.2 output + // Note that this code is a _lot_ slower, mostly due to bad register + // allocation choices of gcc. This works up to 57600 on 16Mhz and + // 38400 on 8Mhz. + _rx_delay_centering = subtract_cap(bit_delay / 2, (4 + 4 + 97 + 29 - 11) / 4); + _rx_delay_intrabit = subtract_cap(bit_delay, 11 / 4); + _rx_delay_stopbit = subtract_cap(bit_delay * 3 / 4, (44 + 17) / 4); + #endif + + + // Enable the PCINT for the entire port here, but never disable it + // (others might also need it, so we disable the interrupt by using + // the per-pin PCMSK register). + *digitalPinToPCICR((int8_t)_receivePin) |= _BV(digitalPinToPCICRbit(_receivePin)); + // Precalculate the pcint mask register and value, so setRxIntMask + // can be used inside the ISR without costing too much time. + _pcint_maskreg = digitalPinToPCMSK(_receivePin); + _pcint_maskvalue = _BV(digitalPinToPCMSKbit(_receivePin)); + + tunedDelay(_tx_delay); // if we were low this establishes the end + } + +#if _DEBUG + pinMode(_DEBUG_PIN1, OUTPUT); + pinMode(_DEBUG_PIN2, OUTPUT); +#endif + + listen(); +} + +void SoftwareSerial::setRxIntMsk(bool enable) +{ + if (enable) + *_pcint_maskreg |= _pcint_maskvalue; + else + *_pcint_maskreg &= ~_pcint_maskvalue; +} + +void SoftwareSerial::end() +{ + stopListening(); +} + + +// Read data from buffer +int SoftwareSerial::read() +{ + if (!isListening()) + return -1; + + // Empty buffer? + if (_receive_buffer_head == _receive_buffer_tail) + return -1; + + // Read from "head" + uint8_t d = _receive_buffer[_receive_buffer_head]; // grab next byte + _receive_buffer_head = (_receive_buffer_head + 1) % _SS_MAX_RX_BUFF; + return d; +} + +int SoftwareSerial::available() +{ + if (!isListening()) + return 0; + + return (_receive_buffer_tail + _SS_MAX_RX_BUFF - _receive_buffer_head) % _SS_MAX_RX_BUFF; +} + +size_t SoftwareSerial::write(uint8_t b) +{ + if (_tx_delay == 0) { + setWriteError(); + return 0; + } + + // By declaring these as local variables, the compiler will put them + // in registers _before_ disabling interrupts and entering the + // critical timing sections below, which makes it a lot easier to + // verify the cycle timings + volatile uint8_t *reg = _transmitPortRegister; + uint8_t reg_mask = _transmitBitMask; + uint8_t inv_mask = ~_transmitBitMask; + uint8_t oldSREG = SREG; + bool inv = _inverse_logic; + uint16_t delay = _tx_delay; + + if (inv) + b = ~b; + + cli(); // turn off interrupts for a clean txmit + + // Write the start bit + if (inv) + *reg |= reg_mask; + else + *reg &= inv_mask; + + tunedDelay(delay); + + // Write each of the 8 bits + for (uint8_t i = 8; i > 0; --i) + { + if (b & 1) // choose bit + *reg |= reg_mask; // send 1 + else + *reg &= inv_mask; // send 0 + + tunedDelay(delay); + b >>= 1; + } + + // restore pin to natural state + if (inv) + *reg &= inv_mask; + else + *reg |= reg_mask; + + SREG = oldSREG; // turn interrupts back on + tunedDelay(_tx_delay); + + return 1; +} + +void SoftwareSerial::flush() +{ + // There is no tx buffering, simply return +} + +int SoftwareSerial::peek() +{ + if (!isListening()) + return -1; + + // Empty buffer? + if (_receive_buffer_head == _receive_buffer_tail) + return -1; + + // Read from "head" + return _receive_buffer[_receive_buffer_head]; +} diff --git a/hardware/arduino/avr/libraries/SoftwareSerial/src/SoftwareSerial.h b/hardware/arduino/avr/libraries/SoftwareSerial/src/SoftwareSerial.h new file mode 100644 index 0000000000000000000000000000000000000000..d8b88cea11cfe87416787a70f9a2f61fa33a348e --- /dev/null +++ b/hardware/arduino/avr/libraries/SoftwareSerial/src/SoftwareSerial.h @@ -0,0 +1,114 @@ +/* +SoftwareSerial.h (formerly NewSoftSerial.h) - +Multi-instance software serial library for Arduino/Wiring +-- Interrupt-driven receive and other improvements by ladyada + (http://ladyada.net) +-- Tuning, circular buffer, derivation from class Print/Stream, + multi-instance support, porting to 8MHz processors, + various optimizations, PROGMEM delay tables, inverse logic and + direct port writing by Mikal Hart (http://www.arduiniana.org) +-- Pin change interrupt macros by Paul Stoffregen (http://www.pjrc.com) +-- 20MHz processor support by Garrett Mace (http://www.macetech.com) +-- ATmega1280/2560 support by Brett Hagman (http://www.roguerobotics.com/) + +This library is free software; you can redistribute it and/or +modify it under the terms of the GNU Lesser General Public +License as published by the Free Software Foundation; either +version 2.1 of the License, or (at your option) any later version. + +This library is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Lesser General Public License for more details. + +You should have received a copy of the GNU Lesser General Public +License along with this library; if not, write to the Free Software +Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +The latest version of this library can always be found at +http://arduiniana.org. +*/ + +#ifndef SoftwareSerial_h +#define SoftwareSerial_h + +#include +#include + +/****************************************************************************** +* Definitions +******************************************************************************/ + +#ifndef _SS_MAX_RX_BUFF +#define _SS_MAX_RX_BUFF 64 // RX buffer size +#endif + +#ifndef GCC_VERSION +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__) +#endif + +class SoftwareSerial : public Stream +{ +private: + // per object data + uint8_t _receivePin; + uint8_t _receiveBitMask; + volatile uint8_t *_receivePortRegister; + uint8_t _transmitBitMask; + volatile uint8_t *_transmitPortRegister; + volatile uint8_t *_pcint_maskreg; + uint8_t _pcint_maskvalue; + + // Expressed as 4-cycle delays (must never be 0!) + uint16_t _rx_delay_centering; + uint16_t _rx_delay_intrabit; + uint16_t _rx_delay_stopbit; + uint16_t _tx_delay; + + uint16_t _buffer_overflow:1; + uint16_t _inverse_logic:1; + + // static data + static uint8_t _receive_buffer[_SS_MAX_RX_BUFF]; + static volatile uint8_t _receive_buffer_tail; + static volatile uint8_t _receive_buffer_head; + static SoftwareSerial *active_object; + + // private methods + inline void recv() __attribute__((__always_inline__)); + uint8_t rx_pin_read(); + void setTX(uint8_t transmitPin); + void setRX(uint8_t receivePin); + inline void setRxIntMsk(bool enable) __attribute__((__always_inline__)); + + // Return num - sub, or 1 if the result would be < 1 + static uint16_t subtract_cap(uint16_t num, uint16_t sub); + + // private static method for timing + static inline void tunedDelay(uint16_t delay); + +public: + // public methods + SoftwareSerial(uint8_t receivePin, uint8_t transmitPin, bool inverse_logic = false); + ~SoftwareSerial(); + void begin(long speed); + bool listen(); + void end(); + bool isListening() { return this == active_object; } + bool stopListening(); + bool overflow() { bool ret = _buffer_overflow; if (ret) _buffer_overflow = false; return ret; } + int peek(); + + virtual size_t write(uint8_t byte); + virtual int read(); + virtual int available(); + virtual void flush(); + operator bool() { return true; } + + using Print::write; + + // public only for easy access by interrupt handlers + static inline void handle_interrupt() __attribute__((__always_inline__)); +}; + +#endif diff --git a/hardware/arduino/avr/libraries/Wire/examples/SFRRanger_reader/SFRRanger_reader.ino b/hardware/arduino/avr/libraries/Wire/examples/SFRRanger_reader/SFRRanger_reader.ino new file mode 100644 index 0000000000000000000000000000000000000000..4d0a68f8d4d98fde2987ce9ade59f1fc70c7aebb --- /dev/null +++ b/hardware/arduino/avr/libraries/Wire/examples/SFRRanger_reader/SFRRanger_reader.ino @@ -0,0 +1,84 @@ +// I2C SRF10 or SRF08 Devantech Ultrasonic Ranger Finder +// by Nicholas Zambetti +// and James Tichenor + +// Demonstrates use of the Wire library reading data from the +// Devantech Utrasonic Rangers SFR08 and SFR10 + +// Created 29 April 2006 + +// This example code is in the public domain. + + +#include + +void setup() { + Wire.begin(); // join i2c bus (address optional for master) + Serial.begin(9600); // start serial communication at 9600bps +} + +int reading = 0; + +void loop() { + // step 1: instruct sensor to read echoes + Wire.beginTransmission(112); // transmit to device #112 (0x70) + // the address specified in the datasheet is 224 (0xE0) + // but i2c adressing uses the high 7 bits so it's 112 + Wire.write(byte(0x00)); // sets register pointer to the command register (0x00) + Wire.write(byte(0x50)); // command sensor to measure in "inches" (0x50) + // use 0x51 for centimeters + // use 0x52 for ping microseconds + Wire.endTransmission(); // stop transmitting + + // step 2: wait for readings to happen + delay(70); // datasheet suggests at least 65 milliseconds + + // step 3: instruct sensor to return a particular echo reading + Wire.beginTransmission(112); // transmit to device #112 + Wire.write(byte(0x02)); // sets register pointer to echo #1 register (0x02) + Wire.endTransmission(); // stop transmitting + + // step 4: request reading from sensor + Wire.requestFrom(112, 2); // request 2 bytes from slave device #112 + + // step 5: receive reading from sensor + if (2 <= Wire.available()) { // if two bytes were received + reading = Wire.read(); // receive high byte (overwrites previous reading) + reading = reading << 8; // shift high byte to be high 8 bits + reading |= Wire.read(); // receive low byte as lower 8 bits + Serial.println(reading); // print the reading + } + + delay(250); // wait a bit since people have to read the output :) +} + + +/* + +// The following code changes the address of a Devantech Ultrasonic Range Finder (SRF10 or SRF08) +// usage: changeAddress(0x70, 0xE6); + +void changeAddress(byte oldAddress, byte newAddress) +{ + Wire.beginTransmission(oldAddress); + Wire.write(byte(0x00)); + Wire.write(byte(0xA0)); + Wire.endTransmission(); + + Wire.beginTransmission(oldAddress); + Wire.write(byte(0x00)); + Wire.write(byte(0xAA)); + Wire.endTransmission(); + + Wire.beginTransmission(oldAddress); + Wire.write(byte(0x00)); + Wire.write(byte(0xA5)); + Wire.endTransmission(); + + Wire.beginTransmission(oldAddress); + Wire.write(byte(0x00)); + Wire.write(newAddress); + Wire.endTransmission(); +} + +*/ diff --git a/hardware/arduino/avr/libraries/Wire/examples/digital_potentiometer/digital_potentiometer.ino b/hardware/arduino/avr/libraries/Wire/examples/digital_potentiometer/digital_potentiometer.ino new file mode 100644 index 0000000000000000000000000000000000000000..dd40a2526e62e970a3a3e5b2dea213650e49fa66 --- /dev/null +++ b/hardware/arduino/avr/libraries/Wire/examples/digital_potentiometer/digital_potentiometer.ino @@ -0,0 +1,34 @@ +// I2C Digital Potentiometer +// by Nicholas Zambetti +// and Shawn Bonkowski + +// Demonstrates use of the Wire library +// Controls AD5171 digital potentiometer via I2C/TWI + +// Created 31 March 2006 + +// This example code is in the public domain. + + +#include + +void setup() { + Wire.begin(); // join i2c bus (address optional for master) +} + +byte val = 0; + +void loop() { + Wire.beginTransmission(44); // transmit to device #44 (0x2c) + // device address is specified in datasheet + Wire.write(byte(0x00)); // sends instruction byte + Wire.write(val); // sends potentiometer value byte + Wire.endTransmission(); // stop transmitting + + val++; // increment value + if (val == 64) { // if reached 64th position (max) + val = 0; // start over from lowest value + } + delay(500); +} + diff --git a/hardware/arduino/avr/libraries/Wire/examples/i2c_scanner/i2c_scanner.ino b/hardware/arduino/avr/libraries/Wire/examples/i2c_scanner/i2c_scanner.ino new file mode 100644 index 0000000000000000000000000000000000000000..3febbf441623781635113abdb4cdeeaead62ce05 --- /dev/null +++ b/hardware/arduino/avr/libraries/Wire/examples/i2c_scanner/i2c_scanner.ino @@ -0,0 +1,75 @@ +// -------------------------------------- +// i2c_scanner +// +// Version 1 +// This program (or code that looks like it) +// can be found in many places. +// For example on the Arduino.cc forum. +// The original author is not know. +// Version 2, Juni 2012, Using Arduino 1.0.1 +// Adapted to be as simple as possible by Arduino.cc user Krodal +// Version 3, Feb 26 2013 +// V3 by louarnold +// Version 4, March 3, 2013, Using Arduino 1.0.3 +// by Arduino.cc user Krodal. +// Changes by louarnold removed. +// Scanning addresses changed from 0...127 to 1...119, +// according to the i2c scanner by Nick Gammon +// https://www.gammon.com.au/forum/?id=10896 +// Version 5, March 28, 2013 +// As version 4, but address scans now to 127. +// A sensor seems to use address 120. +// Version 6, November 27, 2015. +// Added waiting for the Leonardo serial communication. +// +// +// This sketch tests the standard 7-bit addresses +// Devices with higher bit address might not be seen properly. +// + +#include + +void setup() { + Wire.begin(); + + Serial.begin(9600); + while (!Serial); // Leonardo: wait for serial monitor + Serial.println("\nI2C Scanner"); +} + +void loop() { + int nDevices = 0; + + Serial.println("Scanning..."); + + for (byte address = 1; address < 127; ++address) { + // The i2c_scanner uses the return value of + // the Write.endTransmisstion to see if + // a device did acknowledge to the address. + Wire.beginTransmission(address); + byte error = Wire.endTransmission(); + + if (error == 0) { + Serial.print("I2C device found at address 0x"); + if (address < 16) { + Serial.print("0"); + } + Serial.print(address, HEX); + Serial.println(" !"); + + ++nDevices; + } else if (error == 4) { + Serial.print("Unknown error at address 0x"); + if (address < 16) { + Serial.print("0"); + } + Serial.println(address, HEX); + } + } + if (nDevices == 0) { + Serial.println("No I2C devices found\n"); + } else { + Serial.println("done\n"); + } + delay(5000); // Wait 5 seconds for next scan +} diff --git a/hardware/arduino/avr/libraries/Wire/examples/master_reader/master_reader.ino b/hardware/arduino/avr/libraries/Wire/examples/master_reader/master_reader.ino new file mode 100644 index 0000000000000000000000000000000000000000..ecab72ab92483ae9abe85b232c97f56bfdc13241 --- /dev/null +++ b/hardware/arduino/avr/libraries/Wire/examples/master_reader/master_reader.ino @@ -0,0 +1,29 @@ +// Wire Master Reader +// by Nicholas Zambetti + +// Demonstrates use of the Wire library +// Reads data from an I2C/TWI slave device +// Refer to the "Wire Slave Sender" example for use with this + +// Created 29 March 2006 + +// This example code is in the public domain. + + +#include + +void setup() { + Wire.begin(); // join i2c bus (address optional for master) + Serial.begin(9600); // start serial for output +} + +void loop() { + Wire.requestFrom(8, 6); // request 6 bytes from slave device #8 + + while (Wire.available()) { // slave may send less than requested + char c = Wire.read(); // receive a byte as character + Serial.print(c); // print the character + } + + delay(500); +} diff --git a/hardware/arduino/avr/libraries/Wire/examples/master_writer/master_writer.ino b/hardware/arduino/avr/libraries/Wire/examples/master_writer/master_writer.ino new file mode 100644 index 0000000000000000000000000000000000000000..5cbea1179d98b0b4c836446a3eda9b59229e0e2c --- /dev/null +++ b/hardware/arduino/avr/libraries/Wire/examples/master_writer/master_writer.ino @@ -0,0 +1,29 @@ +// Wire Master Writer +// by Nicholas Zambetti + +// Demonstrates use of the Wire library +// Writes data to an I2C/TWI slave device +// Refer to the "Wire Slave Receiver" example for use with this + +// Created 29 March 2006 + +// This example code is in the public domain. + + +#include + +void setup() { + Wire.begin(); // join i2c bus (address optional for master) +} + +byte x = 0; + +void loop() { + Wire.beginTransmission(8); // transmit to device #8 + Wire.write("x is "); // sends five bytes + Wire.write(x); // sends one byte + Wire.endTransmission(); // stop transmitting + + x++; + delay(500); +} diff --git a/hardware/arduino/avr/libraries/Wire/examples/slave_receiver/slave_receiver.ino b/hardware/arduino/avr/libraries/Wire/examples/slave_receiver/slave_receiver.ino new file mode 100644 index 0000000000000000000000000000000000000000..8051d53acc48b489777f6fb596e40b0bbb65b1c8 --- /dev/null +++ b/hardware/arduino/avr/libraries/Wire/examples/slave_receiver/slave_receiver.ino @@ -0,0 +1,34 @@ +// Wire Slave Receiver +// by Nicholas Zambetti + +// Demonstrates use of the Wire library +// Receives data as an I2C/TWI slave device +// Refer to the "Wire Master Writer" example for use with this + +// Created 29 March 2006 + +// This example code is in the public domain. + + +#include + +void setup() { + Wire.begin(8); // join i2c bus with address #8 + Wire.onReceive(receiveEvent); // register event + Serial.begin(9600); // start serial for output +} + +void loop() { + delay(100); +} + +// function that executes whenever data is received from master +// this function is registered as an event, see setup() +void receiveEvent(int howMany) { + while (1 < Wire.available()) { // loop through all but the last + char c = Wire.read(); // receive byte as a character + Serial.print(c); // print the character + } + int x = Wire.read(); // receive byte as an integer + Serial.println(x); // print the integer +} diff --git a/hardware/arduino/avr/libraries/Wire/examples/slave_sender/slave_sender.ino b/hardware/arduino/avr/libraries/Wire/examples/slave_sender/slave_sender.ino new file mode 100644 index 0000000000000000000000000000000000000000..d2e72bbcf1bbfa7908ac4d7bb9a6d955259ff8e8 --- /dev/null +++ b/hardware/arduino/avr/libraries/Wire/examples/slave_sender/slave_sender.ino @@ -0,0 +1,29 @@ +// Wire Slave Sender +// by Nicholas Zambetti + +// Demonstrates use of the Wire library +// Sends data as an I2C/TWI slave device +// Refer to the "Wire Master Reader" example for use with this + +// Created 29 March 2006 + +// This example code is in the public domain. + + +#include + +void setup() { + Wire.begin(8); // join i2c bus with address #8 + Wire.onRequest(requestEvent); // register event +} + +void loop() { + delay(100); +} + +// function that executes whenever data is requested by master +// this function is registered as an event, see setup() +void requestEvent() { + Wire.write("hello "); // respond with message of 6 bytes + // as expected by master +} diff --git a/hardware/arduino/avr/libraries/Wire/keywords.txt b/hardware/arduino/avr/libraries/Wire/keywords.txt new file mode 100644 index 0000000000000000000000000000000000000000..5e3d2b1ca444ac5d495e1246bd14dd9891722199 --- /dev/null +++ b/hardware/arduino/avr/libraries/Wire/keywords.txt @@ -0,0 +1,30 @@ +####################################### +# Syntax Coloring Map For Wire +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +begin KEYWORD2 +setClock KEYWORD2 +beginTransmission KEYWORD2 +endTransmission KEYWORD2 +requestFrom KEYWORD2 +onReceive KEYWORD2 +onRequest KEYWORD2 + +####################################### +# Instances (KEYWORD2) +####################################### + +Wire KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### + diff --git a/hardware/arduino/avr/libraries/Wire/library.properties b/hardware/arduino/avr/libraries/Wire/library.properties new file mode 100644 index 0000000000000000000000000000000000000000..e19526e876fe5d3bdea92b330954532882cb4139 --- /dev/null +++ b/hardware/arduino/avr/libraries/Wire/library.properties @@ -0,0 +1,10 @@ +name=Wire +version=1.0 +author=Arduino +maintainer=Arduino +sentence=This library allows you to communicate with I2C and Two Wire Interface devices. +paragraph=It allows the communication with I2C devices like temperature sensors, realtime clocks and many others using SDA (Data Line) and SCL (Clock Line). +category=Communication +url=http://www.arduino.cc/en/Reference/Wire +architectures=avr + diff --git a/hardware/arduino/avr/libraries/Wire/src/Wire.cpp b/hardware/arduino/avr/libraries/Wire/src/Wire.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c407776e7b0d153d7e70c28ef8bad46615d90c5c --- /dev/null +++ b/hardware/arduino/avr/libraries/Wire/src/Wire.cpp @@ -0,0 +1,378 @@ +/* + TwoWire.cpp - TWI/I2C library for Wiring & Arduino + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts + Modified 2017 by Chuck Todd (ctodd@cableone.net) to correct Unconfigured Slave Mode reboot + Modified 2020 by Greyson Christoforo (grey@christoforo.net) to implement timeouts +*/ + +extern "C" { + #include + #include + #include + #include "utility/twi.h" +} + +#include "Wire.h" + +// Initialize Class Variables ////////////////////////////////////////////////// + +uint8_t TwoWire::rxBuffer[BUFFER_LENGTH]; +uint8_t TwoWire::rxBufferIndex = 0; +uint8_t TwoWire::rxBufferLength = 0; + +uint8_t TwoWire::txAddress = 0; +uint8_t TwoWire::txBuffer[BUFFER_LENGTH]; +uint8_t TwoWire::txBufferIndex = 0; +uint8_t TwoWire::txBufferLength = 0; + +uint8_t TwoWire::transmitting = 0; +void (*TwoWire::user_onRequest)(void); +void (*TwoWire::user_onReceive)(int); + +// Constructors //////////////////////////////////////////////////////////////// + +TwoWire::TwoWire() +{ +} + +// Public Methods ////////////////////////////////////////////////////////////// + +void TwoWire::begin(void) +{ + rxBufferIndex = 0; + rxBufferLength = 0; + + txBufferIndex = 0; + txBufferLength = 0; + + twi_init(); + twi_attachSlaveTxEvent(onRequestService); // default callback must exist + twi_attachSlaveRxEvent(onReceiveService); // default callback must exist +} + +void TwoWire::begin(uint8_t address) +{ + begin(); + twi_setAddress(address); +} + +void TwoWire::begin(int address) +{ + begin((uint8_t)address); +} + +void TwoWire::end(void) +{ + twi_disable(); +} + +void TwoWire::setClock(uint32_t clock) +{ + twi_setFrequency(clock); +} + +/*** + * Sets the TWI timeout. + * + * This limits the maximum time to wait for the TWI hardware. If more time passes, the bus is assumed + * to have locked up (e.g. due to noise-induced glitches or faulty slaves) and the transaction is aborted. + * Optionally, the TWI hardware is also reset, which can be required to allow subsequent transactions to + * succeed in some cases (in particular when noise has made the TWI hardware think there is a second + * master that has claimed the bus). + * + * When a timeout is triggered, a flag is set that can be queried with `getWireTimeoutFlag()` and is cleared + * when `clearWireTimeoutFlag()` or `setWireTimeoutUs()` is called. + * + * Note that this timeout can also trigger while waiting for clock stretching or waiting for a second master + * to complete its transaction. So make sure to adapt the timeout to accomodate for those cases if needed. + * A typical timeout would be 25ms (which is the maximum clock stretching allowed by the SMBus protocol), + * but (much) shorter values will usually also work. + * + * In the future, a timeout will be enabled by default, so if you require the timeout to be disabled, it is + * recommended you disable it by default using `setWireTimeoutUs(0)`, even though that is currently + * the default. + * + * @param timeout a timeout value in microseconds, if zero then timeout checking is disabled + * @param reset_with_timeout if true then TWI interface will be automatically reset on timeout + * if false then TWI interface will not be reset on timeout + + */ +void TwoWire::setWireTimeout(uint32_t timeout, bool reset_with_timeout){ + twi_setTimeoutInMicros(timeout, reset_with_timeout); +} + +/*** + * Returns the TWI timeout flag. + * + * @return true if timeout has occured since the flag was last cleared. + */ +bool TwoWire::getWireTimeoutFlag(void){ + return(twi_manageTimeoutFlag(false)); +} + +/*** + * Clears the TWI timeout flag. + */ +void TwoWire::clearWireTimeoutFlag(void){ + twi_manageTimeoutFlag(true); +} + +uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity, uint32_t iaddress, uint8_t isize, uint8_t sendStop) +{ + if (isize > 0) { + // send internal address; this mode allows sending a repeated start to access + // some devices' internal registers. This function is executed by the hardware + // TWI module on other processors (for example Due's TWI_IADR and TWI_MMR registers) + + beginTransmission(address); + + // the maximum size of internal address is 3 bytes + if (isize > 3){ + isize = 3; + } + + // write internal register address - most significant byte first + while (isize-- > 0) + write((uint8_t)(iaddress >> (isize*8))); + endTransmission(false); + } + + // clamp to buffer length + if(quantity > BUFFER_LENGTH){ + quantity = BUFFER_LENGTH; + } + // perform blocking read into buffer + uint8_t read = twi_readFrom(address, rxBuffer, quantity, sendStop); + // set rx buffer iterator vars + rxBufferIndex = 0; + rxBufferLength = read; + + return read; +} + +uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity, uint8_t sendStop) { + return requestFrom((uint8_t)address, (uint8_t)quantity, (uint32_t)0, (uint8_t)0, (uint8_t)sendStop); +} + +uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity) +{ + return requestFrom((uint8_t)address, (uint8_t)quantity, (uint8_t)true); +} + +uint8_t TwoWire::requestFrom(int address, int quantity) +{ + return requestFrom((uint8_t)address, (uint8_t)quantity, (uint8_t)true); +} + +uint8_t TwoWire::requestFrom(int address, int quantity, int sendStop) +{ + return requestFrom((uint8_t)address, (uint8_t)quantity, (uint8_t)sendStop); +} + +void TwoWire::beginTransmission(uint8_t address) +{ + // indicate that we are transmitting + transmitting = 1; + // set address of targeted slave + txAddress = address; + // reset tx buffer iterator vars + txBufferIndex = 0; + txBufferLength = 0; +} + +void TwoWire::beginTransmission(int address) +{ + beginTransmission((uint8_t)address); +} + +// +// Originally, 'endTransmission' was an f(void) function. +// It has been modified to take one parameter indicating +// whether or not a STOP should be performed on the bus. +// Calling endTransmission(false) allows a sketch to +// perform a repeated start. +// +// WARNING: Nothing in the library keeps track of whether +// the bus tenure has been properly ended with a STOP. It +// is very possible to leave the bus in a hung state if +// no call to endTransmission(true) is made. Some I2C +// devices will behave oddly if they do not see a STOP. +// +uint8_t TwoWire::endTransmission(uint8_t sendStop) +{ + // transmit buffer (blocking) + uint8_t ret = twi_writeTo(txAddress, txBuffer, txBufferLength, 1, sendStop); + // reset tx buffer iterator vars + txBufferIndex = 0; + txBufferLength = 0; + // indicate that we are done transmitting + transmitting = 0; + return ret; +} + +// This provides backwards compatibility with the original +// definition, and expected behaviour, of endTransmission +// +uint8_t TwoWire::endTransmission(void) +{ + return endTransmission(true); +} + +// must be called in: +// slave tx event callback +// or after beginTransmission(address) +size_t TwoWire::write(uint8_t data) +{ + if(transmitting){ + // in master transmitter mode + // don't bother if buffer is full + if(txBufferLength >= BUFFER_LENGTH){ + setWriteError(); + return 0; + } + // put byte in tx buffer + txBuffer[txBufferIndex] = data; + ++txBufferIndex; + // update amount in buffer + txBufferLength = txBufferIndex; + }else{ + // in slave send mode + // reply to master + twi_transmit(&data, 1); + } + return 1; +} + +// must be called in: +// slave tx event callback +// or after beginTransmission(address) +size_t TwoWire::write(const uint8_t *data, size_t quantity) +{ + if(transmitting){ + // in master transmitter mode + for(size_t i = 0; i < quantity; ++i){ + write(data[i]); + } + }else{ + // in slave send mode + // reply to master + twi_transmit(data, quantity); + } + return quantity; +} + +// must be called in: +// slave rx event callback +// or after requestFrom(address, numBytes) +int TwoWire::available(void) +{ + return rxBufferLength - rxBufferIndex; +} + +// must be called in: +// slave rx event callback +// or after requestFrom(address, numBytes) +int TwoWire::read(void) +{ + int value = -1; + + // get each successive byte on each call + if(rxBufferIndex < rxBufferLength){ + value = rxBuffer[rxBufferIndex]; + ++rxBufferIndex; + } + + return value; +} + +// must be called in: +// slave rx event callback +// or after requestFrom(address, numBytes) +int TwoWire::peek(void) +{ + int value = -1; + + if(rxBufferIndex < rxBufferLength){ + value = rxBuffer[rxBufferIndex]; + } + + return value; +} + +void TwoWire::flush(void) +{ + // XXX: to be implemented. +} + +// behind the scenes function that is called when data is received +void TwoWire::onReceiveService(uint8_t* inBytes, int numBytes) +{ + // don't bother if user hasn't registered a callback + if(!user_onReceive){ + return; + } + // don't bother if rx buffer is in use by a master requestFrom() op + // i know this drops data, but it allows for slight stupidity + // meaning, they may not have read all the master requestFrom() data yet + if(rxBufferIndex < rxBufferLength){ + return; + } + // copy twi rx buffer into local read buffer + // this enables new reads to happen in parallel + for(uint8_t i = 0; i < numBytes; ++i){ + rxBuffer[i] = inBytes[i]; + } + // set rx iterator vars + rxBufferIndex = 0; + rxBufferLength = numBytes; + // alert user program + user_onReceive(numBytes); +} + +// behind the scenes function that is called when data is requested +void TwoWire::onRequestService(void) +{ + // don't bother if user hasn't registered a callback + if(!user_onRequest){ + return; + } + // reset tx buffer iterator vars + // !!! this will kill any pending pre-master sendTo() activity + txBufferIndex = 0; + txBufferLength = 0; + // alert user program + user_onRequest(); +} + +// sets function called on slave write +void TwoWire::onReceive( void (*function)(int) ) +{ + user_onReceive = function; +} + +// sets function called on slave read +void TwoWire::onRequest( void (*function)(void) ) +{ + user_onRequest = function; +} + +// Preinstantiate Objects ////////////////////////////////////////////////////// + +TwoWire Wire = TwoWire(); + diff --git a/hardware/arduino/avr/libraries/Wire/src/Wire.h b/hardware/arduino/avr/libraries/Wire/src/Wire.h new file mode 100644 index 0000000000000000000000000000000000000000..e70d72edb6c4f69d9537a0ba6076dc3f9d196eef --- /dev/null +++ b/hardware/arduino/avr/libraries/Wire/src/Wire.h @@ -0,0 +1,89 @@ +/* + TwoWire.h - TWI/I2C library for Arduino & Wiring + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts + Modified 2020 by Greyson Christoforo (grey@christoforo.net) to implement timeouts +*/ + +#ifndef TwoWire_h +#define TwoWire_h + +#include +#include "Stream.h" + +#define BUFFER_LENGTH 32 + +// WIRE_HAS_END means Wire has end() +#define WIRE_HAS_END 1 + +class TwoWire : public Stream +{ + private: + static uint8_t rxBuffer[]; + static uint8_t rxBufferIndex; + static uint8_t rxBufferLength; + + static uint8_t txAddress; + static uint8_t txBuffer[]; + static uint8_t txBufferIndex; + static uint8_t txBufferLength; + + static uint8_t transmitting; + static void (*user_onRequest)(void); + static void (*user_onReceive)(int); + static void onRequestService(void); + static void onReceiveService(uint8_t*, int); + public: + TwoWire(); + void begin(); + void begin(uint8_t); + void begin(int); + void end(); + void setClock(uint32_t); + void setWireTimeout(uint32_t timeout = 25000, bool reset_with_timeout = false); + bool getWireTimeoutFlag(void); + void clearWireTimeoutFlag(void); + void beginTransmission(uint8_t); + void beginTransmission(int); + uint8_t endTransmission(void); + uint8_t endTransmission(uint8_t); + uint8_t requestFrom(uint8_t, uint8_t); + uint8_t requestFrom(uint8_t, uint8_t, uint8_t); + uint8_t requestFrom(uint8_t, uint8_t, uint32_t, uint8_t, uint8_t); + uint8_t requestFrom(int, int); + uint8_t requestFrom(int, int, int); + virtual size_t write(uint8_t); + virtual size_t write(const uint8_t *, size_t); + virtual int available(void); + virtual int read(void); + virtual int peek(void); + virtual void flush(void); + void onReceive( void (*)(int) ); + void onRequest( void (*)(void) ); + + inline size_t write(unsigned long n) { return write((uint8_t)n); } + inline size_t write(long n) { return write((uint8_t)n); } + inline size_t write(unsigned int n) { return write((uint8_t)n); } + inline size_t write(int n) { return write((uint8_t)n); } + using Print::write; +}; + +extern TwoWire Wire; + +#endif + diff --git a/hardware/arduino/avr/libraries/Wire/src/utility/twi.c b/hardware/arduino/avr/libraries/Wire/src/utility/twi.c new file mode 100644 index 0000000000000000000000000000000000000000..5539633a7bfacd487b3ef59788b3ba7493a86558 --- /dev/null +++ b/hardware/arduino/avr/libraries/Wire/src/utility/twi.c @@ -0,0 +1,666 @@ +/* + twi.c - TWI/I2C library for Wiring & Arduino + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts + Modified 2020 by Greyson Christoforo (grey@christoforo.net) to implement timeouts +*/ + +#include +#include +#include +#include +#include +#include +#include +#include "Arduino.h" // for digitalWrite and micros + +#ifndef cbi +#define cbi(sfr, bit) (_SFR_BYTE(sfr) &= ~_BV(bit)) +#endif + +#ifndef sbi +#define sbi(sfr, bit) (_SFR_BYTE(sfr) |= _BV(bit)) +#endif + +#include "pins_arduino.h" +#include "twi.h" + +static volatile uint8_t twi_state; +static volatile uint8_t twi_slarw; +static volatile uint8_t twi_sendStop; // should the transaction end with a stop +static volatile uint8_t twi_inRepStart; // in the middle of a repeated start + +// twi_timeout_us > 0 prevents the code from getting stuck in various while loops here +// if twi_timeout_us == 0 then timeout checking is disabled (the previous Wire lib behavior) +// at some point in the future, the default twi_timeout_us value could become 25000 +// and twi_do_reset_on_timeout could become true +// to conform to the SMBus standard +// http://smbus.org/specs/SMBus_3_1_20180319.pdf +static volatile uint32_t twi_timeout_us = 0ul; +static volatile bool twi_timed_out_flag = false; // a timeout has been seen +static volatile bool twi_do_reset_on_timeout = false; // reset the TWI registers on timeout + +static void (*twi_onSlaveTransmit)(void); +static void (*twi_onSlaveReceive)(uint8_t*, int); + +static uint8_t twi_masterBuffer[TWI_BUFFER_LENGTH]; +static volatile uint8_t twi_masterBufferIndex; +static volatile uint8_t twi_masterBufferLength; + +static uint8_t twi_txBuffer[TWI_BUFFER_LENGTH]; +static volatile uint8_t twi_txBufferIndex; +static volatile uint8_t twi_txBufferLength; + +static uint8_t twi_rxBuffer[TWI_BUFFER_LENGTH]; +static volatile uint8_t twi_rxBufferIndex; + +static volatile uint8_t twi_error; + +/* + * Function twi_init + * Desc readys twi pins and sets twi bitrate + * Input none + * Output none + */ +void twi_init(void) +{ + // initialize state + twi_state = TWI_READY; + twi_sendStop = true; // default value + twi_inRepStart = false; + + // activate internal pullups for twi. + digitalWrite(SDA, 1); + digitalWrite(SCL, 1); + + // initialize twi prescaler and bit rate + cbi(TWSR, TWPS0); + cbi(TWSR, TWPS1); + TWBR = ((F_CPU / TWI_FREQ) - 16) / 2; + + /* twi bit rate formula from atmega128 manual pg 204 + SCL Frequency = CPU Clock Frequency / (16 + (2 * TWBR)) + note: TWBR should be 10 or higher for master mode + It is 72 for a 16mhz Wiring board with 100kHz TWI */ + + // enable twi module, acks, and twi interrupt + TWCR = _BV(TWEN) | _BV(TWIE) | _BV(TWEA); +} + +/* + * Function twi_disable + * Desc disables twi pins + * Input none + * Output none + */ +void twi_disable(void) +{ + // disable twi module, acks, and twi interrupt + TWCR &= ~(_BV(TWEN) | _BV(TWIE) | _BV(TWEA)); + + // deactivate internal pullups for twi. + digitalWrite(SDA, 0); + digitalWrite(SCL, 0); +} + +/* + * Function twi_slaveInit + * Desc sets slave address and enables interrupt + * Input none + * Output none + */ +void twi_setAddress(uint8_t address) +{ + // set twi slave address (skip over TWGCE bit) + TWAR = address << 1; +} + +/* + * Function twi_setClock + * Desc sets twi bit rate + * Input Clock Frequency + * Output none + */ +void twi_setFrequency(uint32_t frequency) +{ + TWBR = ((F_CPU / frequency) - 16) / 2; + + /* twi bit rate formula from atmega128 manual pg 204 + SCL Frequency = CPU Clock Frequency / (16 + (2 * TWBR)) + note: TWBR should be 10 or higher for master mode + It is 72 for a 16mhz Wiring board with 100kHz TWI */ +} + +/* + * Function twi_readFrom + * Desc attempts to become twi bus master and read a + * series of bytes from a device on the bus + * Input address: 7bit i2c device address + * data: pointer to byte array + * length: number of bytes to read into array + * sendStop: Boolean indicating whether to send a stop at the end + * Output number of bytes read + */ +uint8_t twi_readFrom(uint8_t address, uint8_t* data, uint8_t length, uint8_t sendStop) +{ + uint8_t i; + + // ensure data will fit into buffer + if(TWI_BUFFER_LENGTH < length){ + return 0; + } + + // wait until twi is ready, become master receiver + uint32_t startMicros = micros(); + while(TWI_READY != twi_state){ + if((twi_timeout_us > 0ul) && ((micros() - startMicros) > twi_timeout_us)) { + twi_handleTimeout(twi_do_reset_on_timeout); + return 0; + } + } + twi_state = TWI_MRX; + twi_sendStop = sendStop; + // reset error state (0xFF.. no error occured) + twi_error = 0xFF; + + // initialize buffer iteration vars + twi_masterBufferIndex = 0; + twi_masterBufferLength = length-1; // This is not intuitive, read on... + // On receive, the previously configured ACK/NACK setting is transmitted in + // response to the received byte before the interrupt is signalled. + // Therefor we must actually set NACK when the _next_ to last byte is + // received, causing that NACK to be sent in response to receiving the last + // expected byte of data. + + // build sla+w, slave device address + w bit + twi_slarw = TW_READ; + twi_slarw |= address << 1; + + if (true == twi_inRepStart) { + // if we're in the repeated start state, then we've already sent the start, + // (@@@ we hope), and the TWI statemachine is just waiting for the address byte. + // We need to remove ourselves from the repeated start state before we enable interrupts, + // since the ISR is ASYNC, and we could get confused if we hit the ISR before cleaning + // up. Also, don't enable the START interrupt. There may be one pending from the + // repeated start that we sent ourselves, and that would really confuse things. + twi_inRepStart = false; // remember, we're dealing with an ASYNC ISR + startMicros = micros(); + do { + TWDR = twi_slarw; + if((twi_timeout_us > 0ul) && ((micros() - startMicros) > twi_timeout_us)) { + twi_handleTimeout(twi_do_reset_on_timeout); + return 0; + } + } while(TWCR & _BV(TWWC)); + TWCR = _BV(TWINT) | _BV(TWEA) | _BV(TWEN) | _BV(TWIE); // enable INTs, but not START + } else { + // send start condition + TWCR = _BV(TWEN) | _BV(TWIE) | _BV(TWEA) | _BV(TWINT) | _BV(TWSTA); + } + + // wait for read operation to complete + startMicros = micros(); + while(TWI_MRX == twi_state){ + if((twi_timeout_us > 0ul) && ((micros() - startMicros) > twi_timeout_us)) { + twi_handleTimeout(twi_do_reset_on_timeout); + return 0; + } + } + + if (twi_masterBufferIndex < length) { + length = twi_masterBufferIndex; + } + + // copy twi buffer to data + for(i = 0; i < length; ++i){ + data[i] = twi_masterBuffer[i]; + } + + return length; +} + +/* + * Function twi_writeTo + * Desc attempts to become twi bus master and write a + * series of bytes to a device on the bus + * Input address: 7bit i2c device address + * data: pointer to byte array + * length: number of bytes in array + * wait: boolean indicating to wait for write or not + * sendStop: boolean indicating whether or not to send a stop at the end + * Output 0 .. success + * 1 .. length to long for buffer + * 2 .. address send, NACK received + * 3 .. data send, NACK received + * 4 .. other twi error (lost bus arbitration, bus error, ..) + * 5 .. timeout + */ +uint8_t twi_writeTo(uint8_t address, uint8_t* data, uint8_t length, uint8_t wait, uint8_t sendStop) +{ + uint8_t i; + + // ensure data will fit into buffer + if(TWI_BUFFER_LENGTH < length){ + return 1; + } + + // wait until twi is ready, become master transmitter + uint32_t startMicros = micros(); + while(TWI_READY != twi_state){ + if((twi_timeout_us > 0ul) && ((micros() - startMicros) > twi_timeout_us)) { + twi_handleTimeout(twi_do_reset_on_timeout); + return (5); + } + } + twi_state = TWI_MTX; + twi_sendStop = sendStop; + // reset error state (0xFF.. no error occured) + twi_error = 0xFF; + + // initialize buffer iteration vars + twi_masterBufferIndex = 0; + twi_masterBufferLength = length; + + // copy data to twi buffer + for(i = 0; i < length; ++i){ + twi_masterBuffer[i] = data[i]; + } + + // build sla+w, slave device address + w bit + twi_slarw = TW_WRITE; + twi_slarw |= address << 1; + + // if we're in a repeated start, then we've already sent the START + // in the ISR. Don't do it again. + // + if (true == twi_inRepStart) { + // if we're in the repeated start state, then we've already sent the start, + // (@@@ we hope), and the TWI statemachine is just waiting for the address byte. + // We need to remove ourselves from the repeated start state before we enable interrupts, + // since the ISR is ASYNC, and we could get confused if we hit the ISR before cleaning + // up. Also, don't enable the START interrupt. There may be one pending from the + // repeated start that we sent outselves, and that would really confuse things. + twi_inRepStart = false; // remember, we're dealing with an ASYNC ISR + startMicros = micros(); + do { + TWDR = twi_slarw; + if((twi_timeout_us > 0ul) && ((micros() - startMicros) > twi_timeout_us)) { + twi_handleTimeout(twi_do_reset_on_timeout); + return (5); + } + } while(TWCR & _BV(TWWC)); + TWCR = _BV(TWINT) | _BV(TWEA) | _BV(TWEN) | _BV(TWIE); // enable INTs, but not START + } else { + // send start condition + TWCR = _BV(TWINT) | _BV(TWEA) | _BV(TWEN) | _BV(TWIE) | _BV(TWSTA); // enable INTs + } + + // wait for write operation to complete + startMicros = micros(); + while(wait && (TWI_MTX == twi_state)){ + if((twi_timeout_us > 0ul) && ((micros() - startMicros) > twi_timeout_us)) { + twi_handleTimeout(twi_do_reset_on_timeout); + return (5); + } + } + + if (twi_error == 0xFF) + return 0; // success + else if (twi_error == TW_MT_SLA_NACK) + return 2; // error: address send, nack received + else if (twi_error == TW_MT_DATA_NACK) + return 3; // error: data send, nack received + else + return 4; // other twi error +} + +/* + * Function twi_transmit + * Desc fills slave tx buffer with data + * must be called in slave tx event callback + * Input data: pointer to byte array + * length: number of bytes in array + * Output 1 length too long for buffer + * 2 not slave transmitter + * 0 ok + */ +uint8_t twi_transmit(const uint8_t* data, uint8_t length) +{ + uint8_t i; + + // ensure data will fit into buffer + if(TWI_BUFFER_LENGTH < (twi_txBufferLength+length)){ + return 1; + } + + // ensure we are currently a slave transmitter + if(TWI_STX != twi_state){ + return 2; + } + + // set length and copy data into tx buffer + for(i = 0; i < length; ++i){ + twi_txBuffer[twi_txBufferLength+i] = data[i]; + } + twi_txBufferLength += length; + + return 0; +} + +/* + * Function twi_attachSlaveRxEvent + * Desc sets function called before a slave read operation + * Input function: callback function to use + * Output none + */ +void twi_attachSlaveRxEvent( void (*function)(uint8_t*, int) ) +{ + twi_onSlaveReceive = function; +} + +/* + * Function twi_attachSlaveTxEvent + * Desc sets function called before a slave write operation + * Input function: callback function to use + * Output none + */ +void twi_attachSlaveTxEvent( void (*function)(void) ) +{ + twi_onSlaveTransmit = function; +} + +/* + * Function twi_reply + * Desc sends byte or readys receive line + * Input ack: byte indicating to ack or to nack + * Output none + */ +void twi_reply(uint8_t ack) +{ + // transmit master read ready signal, with or without ack + if(ack){ + TWCR = _BV(TWEN) | _BV(TWIE) | _BV(TWINT) | _BV(TWEA); + }else{ + TWCR = _BV(TWEN) | _BV(TWIE) | _BV(TWINT); + } +} + +/* + * Function twi_stop + * Desc relinquishes bus master status + * Input none + * Output none + */ +void twi_stop(void) +{ + // send stop condition + TWCR = _BV(TWEN) | _BV(TWIE) | _BV(TWEA) | _BV(TWINT) | _BV(TWSTO); + + // wait for stop condition to be exectued on bus + // TWINT is not set after a stop condition! + // We cannot use micros() from an ISR, so approximate the timeout with cycle-counted delays + const uint8_t us_per_loop = 8; + uint32_t counter = (twi_timeout_us + us_per_loop - 1)/us_per_loop; // Round up + while(TWCR & _BV(TWSTO)){ + if(twi_timeout_us > 0ul){ + if (counter > 0ul){ + _delay_us(10); + counter--; + } else { + twi_handleTimeout(twi_do_reset_on_timeout); + return; + } + } + } + + // update twi state + twi_state = TWI_READY; +} + +/* + * Function twi_releaseBus + * Desc releases bus control + * Input none + * Output none + */ +void twi_releaseBus(void) +{ + // release bus + TWCR = _BV(TWEN) | _BV(TWIE) | _BV(TWEA) | _BV(TWINT); + + // update twi state + twi_state = TWI_READY; +} + +/* + * Function twi_setTimeoutInMicros + * Desc set a timeout for while loops that twi might get stuck in + * Input timeout value in microseconds (0 means never time out) + * Input reset_with_timeout: true causes timeout events to reset twi + * Output none + */ +void twi_setTimeoutInMicros(uint32_t timeout, bool reset_with_timeout){ + twi_timed_out_flag = false; + twi_timeout_us = timeout; + twi_do_reset_on_timeout = reset_with_timeout; +} + +/* + * Function twi_handleTimeout + * Desc this gets called whenever a while loop here has lasted longer than + * twi_timeout_us microseconds. always sets twi_timed_out_flag + * Input reset: true causes this function to reset the twi hardware interface + * Output none + */ +void twi_handleTimeout(bool reset){ + twi_timed_out_flag = true; + + if (reset) { + // remember bitrate and address settings + uint8_t previous_TWBR = TWBR; + uint8_t previous_TWAR = TWAR; + + // reset the interface + twi_disable(); + twi_init(); + + // reapply the previous register values + TWAR = previous_TWAR; + TWBR = previous_TWBR; + } +} + +/* + * Function twi_manageTimeoutFlag + * Desc returns true if twi has seen a timeout + * optionally clears the timeout flag + * Input clear_flag: true if we should reset the hardware + * Output none + */ +bool twi_manageTimeoutFlag(bool clear_flag){ + bool flag = twi_timed_out_flag; + if (clear_flag){ + twi_timed_out_flag = false; + } + return(flag); +} + +ISR(TWI_vect) +{ + switch(TW_STATUS){ + // All Master + case TW_START: // sent start condition + case TW_REP_START: // sent repeated start condition + // copy device address and r/w bit to output register and ack + TWDR = twi_slarw; + twi_reply(1); + break; + + // Master Transmitter + case TW_MT_SLA_ACK: // slave receiver acked address + case TW_MT_DATA_ACK: // slave receiver acked data + // if there is data to send, send it, otherwise stop + if(twi_masterBufferIndex < twi_masterBufferLength){ + // copy data to output register and ack + TWDR = twi_masterBuffer[twi_masterBufferIndex++]; + twi_reply(1); + }else{ + if (twi_sendStop){ + twi_stop(); + } else { + twi_inRepStart = true; // we're gonna send the START + // don't enable the interrupt. We'll generate the start, but we + // avoid handling the interrupt until we're in the next transaction, + // at the point where we would normally issue the start. + TWCR = _BV(TWINT) | _BV(TWSTA)| _BV(TWEN) ; + twi_state = TWI_READY; + } + } + break; + case TW_MT_SLA_NACK: // address sent, nack received + twi_error = TW_MT_SLA_NACK; + twi_stop(); + break; + case TW_MT_DATA_NACK: // data sent, nack received + twi_error = TW_MT_DATA_NACK; + twi_stop(); + break; + case TW_MT_ARB_LOST: // lost bus arbitration + twi_error = TW_MT_ARB_LOST; + twi_releaseBus(); + break; + + // Master Receiver + case TW_MR_DATA_ACK: // data received, ack sent + // put byte into buffer + twi_masterBuffer[twi_masterBufferIndex++] = TWDR; + __attribute__ ((fallthrough)); + case TW_MR_SLA_ACK: // address sent, ack received + // ack if more bytes are expected, otherwise nack + if(twi_masterBufferIndex < twi_masterBufferLength){ + twi_reply(1); + }else{ + twi_reply(0); + } + break; + case TW_MR_DATA_NACK: // data received, nack sent + // put final byte into buffer + twi_masterBuffer[twi_masterBufferIndex++] = TWDR; + if (twi_sendStop){ + twi_stop(); + } else { + twi_inRepStart = true; // we're gonna send the START + // don't enable the interrupt. We'll generate the start, but we + // avoid handling the interrupt until we're in the next transaction, + // at the point where we would normally issue the start. + TWCR = _BV(TWINT) | _BV(TWSTA)| _BV(TWEN) ; + twi_state = TWI_READY; + } + break; + case TW_MR_SLA_NACK: // address sent, nack received + twi_stop(); + break; + // TW_MR_ARB_LOST handled by TW_MT_ARB_LOST case + + // Slave Receiver + case TW_SR_SLA_ACK: // addressed, returned ack + case TW_SR_GCALL_ACK: // addressed generally, returned ack + case TW_SR_ARB_LOST_SLA_ACK: // lost arbitration, returned ack + case TW_SR_ARB_LOST_GCALL_ACK: // lost arbitration, returned ack + // enter slave receiver mode + twi_state = TWI_SRX; + // indicate that rx buffer can be overwritten and ack + twi_rxBufferIndex = 0; + twi_reply(1); + break; + case TW_SR_DATA_ACK: // data received, returned ack + case TW_SR_GCALL_DATA_ACK: // data received generally, returned ack + // if there is still room in the rx buffer + if(twi_rxBufferIndex < TWI_BUFFER_LENGTH){ + // put byte in buffer and ack + twi_rxBuffer[twi_rxBufferIndex++] = TWDR; + twi_reply(1); + }else{ + // otherwise nack + twi_reply(0); + } + break; + case TW_SR_STOP: // stop or repeated start condition received + // ack future responses and leave slave receiver state + twi_releaseBus(); + // put a null char after data if there's room + if(twi_rxBufferIndex < TWI_BUFFER_LENGTH){ + twi_rxBuffer[twi_rxBufferIndex] = '\0'; + } + // callback to user defined callback + twi_onSlaveReceive(twi_rxBuffer, twi_rxBufferIndex); + // since we submit rx buffer to "wire" library, we can reset it + twi_rxBufferIndex = 0; + break; + case TW_SR_DATA_NACK: // data received, returned nack + case TW_SR_GCALL_DATA_NACK: // data received generally, returned nack + // nack back at master + twi_reply(0); + break; + + // Slave Transmitter + case TW_ST_SLA_ACK: // addressed, returned ack + case TW_ST_ARB_LOST_SLA_ACK: // arbitration lost, returned ack + // enter slave transmitter mode + twi_state = TWI_STX; + // ready the tx buffer index for iteration + twi_txBufferIndex = 0; + // set tx buffer length to be zero, to verify if user changes it + twi_txBufferLength = 0; + // request for txBuffer to be filled and length to be set + // note: user must call twi_transmit(bytes, length) to do this + twi_onSlaveTransmit(); + // if they didn't change buffer & length, initialize it + if(0 == twi_txBufferLength){ + twi_txBufferLength = 1; + twi_txBuffer[0] = 0x00; + } + __attribute__ ((fallthrough)); + // transmit first byte from buffer, fall + case TW_ST_DATA_ACK: // byte sent, ack returned + // copy data to output register + TWDR = twi_txBuffer[twi_txBufferIndex++]; + // if there is more to send, ack, otherwise nack + if(twi_txBufferIndex < twi_txBufferLength){ + twi_reply(1); + }else{ + twi_reply(0); + } + break; + case TW_ST_DATA_NACK: // received nack, we are done + case TW_ST_LAST_DATA: // received ack, but we are done already! + // ack future responses + twi_reply(1); + // leave slave receiver state + twi_state = TWI_READY; + break; + + // All + case TW_NO_INFO: // no state information + break; + case TW_BUS_ERROR: // bus error, illegal stop/start + twi_error = TW_BUS_ERROR; + twi_stop(); + break; + } +} diff --git a/hardware/arduino/avr/libraries/Wire/src/utility/twi.h b/hardware/arduino/avr/libraries/Wire/src/utility/twi.h new file mode 100644 index 0000000000000000000000000000000000000000..85b983794a172ef850237f180275b2de30955fa2 --- /dev/null +++ b/hardware/arduino/avr/libraries/Wire/src/utility/twi.h @@ -0,0 +1,59 @@ +/* + twi.h - TWI/I2C library for Wiring & Arduino + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 2020 by Greyson Christoforo (grey@christoforo.net) to implement timeouts +*/ + +#ifndef twi_h +#define twi_h + + #include + + //#define ATMEGA8 + + #ifndef TWI_FREQ + #define TWI_FREQ 100000L + #endif + + #ifndef TWI_BUFFER_LENGTH + #define TWI_BUFFER_LENGTH 32 + #endif + + #define TWI_READY 0 + #define TWI_MRX 1 + #define TWI_MTX 2 + #define TWI_SRX 3 + #define TWI_STX 4 + + void twi_init(void); + void twi_disable(void); + void twi_setAddress(uint8_t); + void twi_setFrequency(uint32_t); + uint8_t twi_readFrom(uint8_t, uint8_t*, uint8_t, uint8_t); + uint8_t twi_writeTo(uint8_t, uint8_t*, uint8_t, uint8_t, uint8_t); + uint8_t twi_transmit(const uint8_t*, uint8_t); + void twi_attachSlaveRxEvent( void (*)(uint8_t*, int) ); + void twi_attachSlaveTxEvent( void (*)(void) ); + void twi_reply(uint8_t); + void twi_stop(void); + void twi_releaseBus(void); + void twi_setTimeoutInMicros(uint32_t, bool); + void twi_handleTimeout(bool); + bool twi_manageTimeoutFlag(bool); + +#endif diff --git a/hardware/arduino/avr/platform.txt b/hardware/arduino/avr/platform.txt new file mode 100644 index 0000000000000000000000000000000000000000..8f46fbcffc585da6c7751055682dbfde8a2de6ed --- /dev/null +++ b/hardware/arduino/avr/platform.txt @@ -0,0 +1,131 @@ + +# Arduino AVR Core and platform. +# ------------------------------ +# +# For more info: +# https://github.com/arduino/Arduino/wiki/Arduino-IDE-1.5-3rd-party-Hardware-specification + +name=Arduino AVR Boards +version=1.8.3 + +# AVR compile variables +# --------------------- + +compiler.warning_flags=-w +compiler.warning_flags.none=-w +compiler.warning_flags.default= +compiler.warning_flags.more=-Wall +compiler.warning_flags.all=-Wall -Wextra + +# Default "compiler.path" is correct, change only if you want to override the initial value +compiler.path={runtime.tools.avr-gcc.path}/bin/ +compiler.c.cmd=avr-gcc +compiler.c.flags=-c -g -Os {compiler.warning_flags} -std=gnu11 -ffunction-sections -fdata-sections -MMD -flto -fno-fat-lto-objects +compiler.c.elf.flags={compiler.warning_flags} -Os -g -flto -fuse-linker-plugin -Wl,--gc-sections +compiler.c.elf.cmd=avr-gcc +compiler.S.flags=-c -g -x assembler-with-cpp -flto -MMD +compiler.cpp.cmd=avr-g++ +compiler.cpp.flags=-c -g -Os {compiler.warning_flags} -std=gnu++11 -fpermissive -fno-exceptions -ffunction-sections -fdata-sections -fno-threadsafe-statics -Wno-error=narrowing -MMD -flto +compiler.ar.cmd=avr-gcc-ar +compiler.ar.flags=rcs +compiler.objcopy.cmd=avr-objcopy +compiler.objcopy.eep.flags=-O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0 +compiler.elf2hex.flags=-O ihex -R .eeprom +compiler.elf2hex.cmd=avr-objcopy +compiler.ldflags= +compiler.libraries.ldflags= +compiler.size.cmd=avr-size + +# This can be overridden in boards.txt +build.extra_flags= + +# These can be overridden in platform.local.txt +compiler.c.extra_flags= +compiler.c.elf.extra_flags= +compiler.S.extra_flags= +compiler.cpp.extra_flags= +compiler.ar.extra_flags= +compiler.objcopy.eep.extra_flags= +compiler.elf2hex.extra_flags= + +# AVR compile patterns +# -------------------- + +## Compile c files +recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" + +## Compile c++ files +recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" + +## Compile S files +recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.S.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.S.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" + +## Create archives +# archive_file_path is needed for backwards compatibility with IDE 1.6.5 or older, IDE 1.6.6 or newer overrides this value +archive_file_path={build.path}/{archive_file} +recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}" + +## Combine gc-sections, archives, and objects +recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} -mmcu={build.mcu} {compiler.c.elf.extra_flags} {compiler.ldflags} -o "{build.path}/{build.project_name}.elf" {object_files} {compiler.libraries.ldflags} "{build.path}/{archive_file}" "-L{build.path}" -lm + +## Create output files (.eep and .hex) +recipe.objcopy.eep.pattern="{compiler.path}{compiler.objcopy.cmd}" {compiler.objcopy.eep.flags} {compiler.objcopy.eep.extra_flags} "{build.path}/{build.project_name}.elf" "{build.path}/{build.project_name}.eep" +recipe.objcopy.hex.pattern="{compiler.path}{compiler.elf2hex.cmd}" {compiler.elf2hex.flags} {compiler.elf2hex.extra_flags} "{build.path}/{build.project_name}.elf" "{build.path}/{build.project_name}.hex" + +## Save hex +recipe.output.tmp_file={build.project_name}.hex +recipe.output.save_file={build.project_name}.{build.variant}.hex + +## Compute size +recipe.size.pattern="{compiler.path}{compiler.size.cmd}" -A "{build.path}/{build.project_name}.elf" +recipe.size.regex=^(?:\.text|\.data|\.bootloader)\s+([0-9]+).* +recipe.size.regex.data=^(?:\.data|\.bss|\.noinit)\s+([0-9]+).* +recipe.size.regex.eeprom=^(?:\.eeprom)\s+([0-9]+).* + +## Preprocessor +preproc.includes.flags=-w -x c++ -M -MG -MP +recipe.preproc.includes="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} {preproc.includes.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} "{source_file}" + +preproc.macros.flags=-w -x c++ -E -CC +recipe.preproc.macros="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} {preproc.macros.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{preprocessed_file_path}" + +# AVR Uploader/Programmers tools +# ------------------------------ + +tools.avrdude.path={runtime.tools.avrdude.path} +tools.avrdude.cmd.path={path}/bin/avrdude +tools.avrdude.config.path={path}/etc/avrdude.conf + +tools.avrdude.network_cmd={runtime.tools.arduinoOTA.path}/bin/arduinoOTA + +tools.avrdude.upload.params.verbose=-v +tools.avrdude.upload.params.quiet=-q -q +# tools.avrdude.upload.verify is needed for backwards compatibility with IDE 1.6.8 or older, IDE 1.6.9 or newer overrides this value +tools.avrdude.upload.verify= +tools.avrdude.upload.params.noverify=-V +tools.avrdude.upload.pattern="{cmd.path}" "-C{config.path}" {upload.verbose} {upload.verify} -p{build.mcu} -c{upload.protocol} "-P{serial.port}" -b{upload.speed} -D "-Uflash:w:{build.path}/{build.project_name}.hex:i" + +tools.avrdude.program.params.verbose=-v +tools.avrdude.program.params.quiet=-q -q +# tools.avrdude.program.verify is needed for backwards compatibility with IDE 1.6.8 or older, IDE 1.6.9 or newer overrides this value +tools.avrdude.program.verify= +tools.avrdude.program.params.noverify=-V +tools.avrdude.program.pattern="{cmd.path}" "-C{config.path}" {program.verbose} {program.verify} -p{build.mcu} -c{protocol} {program.extra_params} "-Uflash:w:{build.path}/{build.project_name}.hex:i" + +tools.avrdude.erase.params.verbose=-v +tools.avrdude.erase.params.quiet=-q -q +tools.avrdude.erase.pattern="{cmd.path}" "-C{config.path}" {erase.verbose} -p{build.mcu} -c{protocol} {program.extra_params} -e -Ulock:w:{bootloader.unlock_bits}:m -Uefuse:w:{bootloader.extended_fuses}:m -Uhfuse:w:{bootloader.high_fuses}:m -Ulfuse:w:{bootloader.low_fuses}:m + +tools.avrdude.bootloader.params.verbose=-v +tools.avrdude.bootloader.params.quiet=-q -q +tools.avrdude.bootloader.pattern="{cmd.path}" "-C{config.path}" {bootloader.verbose} -p{build.mcu} -c{protocol} {program.extra_params} "-Uflash:w:{runtime.platform.path}/bootloaders/{bootloader.file}:i" -Ulock:w:{bootloader.lock_bits}:m + +tools.avrdude_remote.upload.pattern=/usr/bin/run-avrdude /tmp/sketch.hex {upload.verbose} -p{build.mcu} + +tools.avrdude.upload.network_pattern="{network_cmd}" -address {serial.port} -port {upload.network.port} -sketch "{build.path}/{build.project_name}.hex" -upload {upload.network.endpoint_upload} -sync {upload.network.endpoint_sync} -reset {upload.network.endpoint_reset} -sync_exp {upload.network.sync_return} + +# USB Default Flags +# Default blank usb manufacturer will be filled in at compile time +# - from numeric vendor ID, set to Unknown otherwise +build.usb_manufacturer="Unknown" +build.usb_flags=-DUSB_VID={build.vid} -DUSB_PID={build.pid} '-DUSB_MANUFACTURER={build.usb_manufacturer}' '-DUSB_PRODUCT={build.usb_product}' diff --git a/hardware/arduino/avr/programmers.txt b/hardware/arduino/avr/programmers.txt new file mode 100644 index 0000000000000000000000000000000000000000..69ddf692c9649064d44d9b43fd56ea5e5c79e59d --- /dev/null +++ b/hardware/arduino/avr/programmers.txt @@ -0,0 +1,115 @@ +avrisp.name=AVR ISP +avrisp.communication=serial +avrisp.protocol=stk500v1 +avrisp.program.protocol=stk500v1 +avrisp.program.tool=avrdude +avrisp.program.extra_params=-P{serial.port} + +avrispmkii.name=AVRISP mkII +avrispmkii.communication=usb +avrispmkii.protocol=stk500v2 +avrispmkii.program.protocol=stk500v2 +avrispmkii.program.tool=avrdude +avrispmkii.program.extra_params=-Pusb + +usbtinyisp.name=USBtinyISP +usbtinyisp.protocol=usbtiny +usbtinyisp.program.tool=avrdude +usbtinyisp.program.extra_params= + +arduinoisp.name=ArduinoISP +arduinoisp.protocol=arduinoisp +arduinoisp.program.tool=avrdude +arduinoisp.program.extra_params= + +arduinoisporg.name=ArduinoISP.org +arduinoisporg.protocol=arduinoisporg +arduinoisporg.program.tool=avrdude +arduinoisporg.program.extra_params= + +usbasp.name=USBasp +usbasp.communication=usb +usbasp.protocol=usbasp +usbasp.program.protocol=usbasp +usbasp.program.tool=avrdude +usbasp.program.extra_params=-Pusb + +parallel.name=Parallel Programmer +parallel.protocol=dapa +parallel.force=true +# parallel.delay=200 +parallel.program.tool=avrdude +parallel.program.extra_params=-F + +arduinoasisp.name=Arduino as ISP +arduinoasisp.communication=serial +arduinoasisp.protocol=stk500v1 +arduinoasisp.speed=19200 +arduinoasisp.program.protocol=stk500v1 +arduinoasisp.program.speed=19200 +arduinoasisp.program.tool=avrdude +arduinoasisp.program.extra_params=-P{serial.port} -b{program.speed} + +arduinoasispatmega32u4.name=Arduino as ISP (ATmega32U4) +arduinoasispatmega32u4.communication=serial +arduinoasispatmega32u4.protocol=arduino +arduinoasispatmega32u4.speed=19200 +arduinoasispatmega32u4.program.protocol=arduino +arduinoasispatmega32u4.program.speed=19200 +arduinoasispatmega32u4.program.tool=avrdude +arduinoasispatmega32u4.program.extra_params=-P{serial.port} -b{program.speed} + +usbGemma.name=Arduino Gemma +usbGemma.protocol=arduinogemma +usbGemma.program.tool=avrdude +usbGemma.program.extra_params= +usbGemma.config.path={runtime.platform.path}/bootloaders/gemma/avrdude.conf + +## Notes about Dangerous Prototypes Bus Pirate as ISP +## Bus Pirate V3 need Firmware v5.10 or later +## Bus Pirate V4 need Firmware v6.3-r2151 or later +## Could happen that BP does not have enough current to power an Arduino board +## through the ICSP connector. In this case disconnect the +Vcc from ICSP connector +## and power Arduino board in the normal way. +buspirate.name=BusPirate as ISP +buspirate.communication=serial +buspirate.protocol=buspirate +buspirate.program.protocol=buspirate +buspirate.program.tool=avrdude +buspirate.program.extra_params=-P{serial.port} + +# STK500 firmware version v1 and v2 use different serial protocols. +# Using the 'stk500' protocol tells avrdude to try and autodetect the +# firmware version. If this leads to problems, we might need to add +# stk500v1 and stk500v2 entries to allow explicitely selecting the +# firmware version. +stk500.name=Atmel STK500 development board +stk500.communication=serial +stk500.protocol=stk500 +stk500.program.protocol=stk500 +stk500.program.tool=avrdude +stk500.program.extra_params=-P{serial.port} + +jtag3isp.name=Atmel JTAGICE3 (ISP mode) +jtag3isp.communication=usb +jtag3isp.protocol=jtag3isp +jtag3isp.program.protocol=jtag3isp +jtag3isp.program.tool=avrdude +jtag3isp.program.extra_params= + +jtag3.name=Atmel JTAGICE3 (JTAG mode) +jtag3.communication=usb +jtag3.protocol=jtag3 +jtag3.program.protocol=jtag3 +jtag3.program.tool=avrdude +# Set a bitclock of 0.1us (the fastest supported value). This should +# work regardless of the crystal used, since JTAG doesn't use the MCU +# clock but dictates its own clock. +jtag3.program.extra_params=-B0.1 + +atmel_ice.name=Atmel-ICE (AVR) +atmel_ice.communication=usb +atmel_ice.protocol=atmelice_isp +atmel_ice.program.protocol=atmelice_isp +atmel_ice.program.tool=avrdude +atmel_ice.program.extra_params=-Pusb diff --git a/hardware/arduino/avr/variants/circuitplay32u4/pins_arduino.h b/hardware/arduino/avr/variants/circuitplay32u4/pins_arduino.h new file mode 100644 index 0000000000000000000000000000000000000000..1da15a9d32d83a942e21db40f6e3e53c6472cd88 --- /dev/null +++ b/hardware/arduino/avr/variants/circuitplay32u4/pins_arduino.h @@ -0,0 +1,387 @@ +/* + pins_arduino.h - Pin definition functions for Arduino + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2007 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.h 249 2007-02-03 16:52:51Z mellis $ +*/ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// Workaround for wrong definitions in "iom32u4.h". +// This should be fixed in the AVR toolchain. +#undef UHCON +#undef UHINT +#undef UHIEN +#undef UHADDR +#undef UHFNUM +#undef UHFNUML +#undef UHFNUMH +#undef UHFLEN +#undef UPINRQX +#undef UPINTX +#undef UPNUM +#undef UPRST +#undef UPCONX +#undef UPCFG0X +#undef UPCFG1X +#undef UPSTAX +#undef UPCFG2X +#undef UPIENX +#undef UPDATX +#undef TCCR2A +#undef WGM20 +#undef WGM21 +#undef COM2B0 +#undef COM2B1 +#undef COM2A0 +#undef COM2A1 +#undef TCCR2B +#undef CS20 +#undef CS21 +#undef CS22 +#undef WGM22 +#undef FOC2B +#undef FOC2A +#undef TCNT2 +#undef TCNT2_0 +#undef TCNT2_1 +#undef TCNT2_2 +#undef TCNT2_3 +#undef TCNT2_4 +#undef TCNT2_5 +#undef TCNT2_6 +#undef TCNT2_7 +#undef OCR2A +#undef OCR2_0 +#undef OCR2_1 +#undef OCR2_2 +#undef OCR2_3 +#undef OCR2_4 +#undef OCR2_5 +#undef OCR2_6 +#undef OCR2_7 +#undef OCR2B +#undef OCR2_0 +#undef OCR2_1 +#undef OCR2_2 +#undef OCR2_3 +#undef OCR2_4 +#undef OCR2_5 +#undef OCR2_6 +#undef OCR2_7 + +#define NUM_DIGITAL_PINS 31 +#define NUM_ANALOG_INPUTS 12 + +#define TXLED0 0 +#define TXLED1 0 +#define RXLED0 0 +#define RXLED1 0 +#define TX_RX_LED_INIT 0 + +static const uint8_t SDA = 2; +static const uint8_t SCL = 3; +#define LED_BUILTIN 13 + +// Map SPI port to 'new' pins D14..D17 +static const uint8_t SS = 17; +static const uint8_t MOSI = 16; +static const uint8_t MISO = 14; +static const uint8_t SCK = 15; + +// Mapping of analog pins as digital I/O +// A6-A11 share with digital pins +static const uint8_t A0 = 18; +static const uint8_t A1 = 19; +static const uint8_t A2 = 20; +static const uint8_t A3 = 21; +static const uint8_t A4 = 22; +static const uint8_t A5 = 23; +static const uint8_t A6 = 24; // D4 +static const uint8_t A7 = 25; // D6 +static const uint8_t A8 = 26; // D8 +static const uint8_t A9 = 27; // D9 +static const uint8_t A10 = 28; // D10 +static const uint8_t A11 = 29; // D12 + +#define digitalPinToPCICR(p) ((((p) >= 8 && (p) <= 11) || ((p) >= 14 && (p) <= 17) || ((p) >= A8 && (p) <= A10)) ? (&PCICR) : ((uint8_t *)0)) +#define digitalPinToPCICRbit(p) 0 +#define digitalPinToPCMSK(p) ((((p) >= 8 && (p) <= 11) || ((p) >= 14 && (p) <= 17) || ((p) >= A8 && (p) <= A10)) ? (&PCMSK0) : ((uint8_t *)0)) +#define digitalPinToPCMSKbit(p) ( ((p) >= 8 && (p) <= 11) ? (p) - 4 : ((p) == 14 ? 3 : ((p) == 15 ? 1 : ((p) == 16 ? 2 : ((p) == 17 ? 0 : (p - A8 + 4)))))) + +// __AVR_ATmega32U4__ has an unusual mapping of pins to channels +extern const uint8_t PROGMEM analog_pin_to_channel_PGM[]; +#define analogPinToChannel(P) ( pgm_read_byte( analog_pin_to_channel_PGM + (P) ) ) + +#define digitalPinHasPWM(p) ((p) == 3 || (p) == 5 || (p) == 6 || (p) == 9 || (p) == 10 || (p) == 11 || (p) == 13) + +#define digitalPinToInterrupt(p) ((p) == 0 ? 2 : ((p) == 1 ? 3 : ((p) == 2 ? 1 : ((p) == 3 ? 0 : ((p) == 7 ? 4 : NOT_AN_INTERRUPT))))) + +#ifdef ARDUINO_MAIN + +// On the Arduino board, digital pins are also used +// for the analog output (software PWM). Analog input +// pins are a separate set. + +// ATMEL ATMEGA32U4 / ARDUINO LEONARDO / Flora +// +// D0 PD2 RXD1/INT2 +// D1 PD3 TXD1/INT3 +// D2 PD1 SDA SDA/INT1 +// D3# PD0 PWM8/SCL OC0B/SCL/INT0 +// D4 A6 PD4 ADC8 +// D5# PC6 ??? OC3A/#OC4A +// D6# A7 PD7 FastPWM #OC4D/ADC10 +// D7 PE6 INT6/AIN0 +// +// D8 A8 PB4 ADC11/PCINT4 +// D9# A9 PB5 PWM16 OC1A/#OC4B/ADC12/PCINT5 +// D10# A10 PB6 PWM16 OC1B/0c4B/ADC13/PCINT6 +// D11# PB7 PWM8/16 0C0A/OC1C/#RTS/PCINT7 +// D12 A11 PD6 T1/#OC4D/ADC9 +// D13# PC7 PWM10 CLK0/OC4A +// +// A0 D18 PF7 ADC7 +// A1 D19 PF6 ADC6 +// A2 D20 PF5 ADC5 +// A3 D21 PF4 ADC4 +// A4 D22 PF1 ADC1 +// A5 D23 PF0 ADC0 +// +// New pins D14..D17 to map SPI port to digital pins +// +// MISO D14 PB3 MISO,PCINT3 +// SCK D15 PB1 SCK,PCINT1 +// MOSI D16 PB2 MOSI,PCINT2 +// SS D17 PB0 RXLED,SS/PCINT0 +// +// TXLED D30 PD5 +// RXLED PB0 +// HWB PE2 HWB + +// these arrays map port names (e.g. port B) to the +// appropriate addresses for various functions (e.g. reading +// and writing) +const uint16_t PROGMEM port_to_mode_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &DDRB, + (uint16_t) &DDRC, + (uint16_t) &DDRD, + (uint16_t) &DDRE, + (uint16_t) &DDRF, +}; + +const uint16_t PROGMEM port_to_output_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &PORTB, + (uint16_t) &PORTC, + (uint16_t) &PORTD, + (uint16_t) &PORTE, + (uint16_t) &PORTF, +}; + +const uint16_t PROGMEM port_to_input_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &PINB, + (uint16_t) &PINC, + (uint16_t) &PIND, + (uint16_t) &PINE, + (uint16_t) &PINF, +}; + +const uint8_t PROGMEM digital_pin_to_port_PGM[] = { + PD, // D0 - PD2 + PD, // D1 - PD3 + PD, // D2 - PD1 + PD, // D3 - PD0 + PD, // D4 - PD4 + PC, // D5 - PC6 + PD, // D6 - PD7 + PE, // D7 - PE6 + + PB, // D8 - PB4 + PB, // D9 - PB5 + PB, // D10 - PB6 + PB, // D11 - PB7 + PD, // D12 - PD6 + PC, // D13 - PC7 + + PB, // D14 - MISO - PB3 + PB, // D15 - SCK - PB1 + PB, // D16 - MOSI - PB2 + PB, // D17 - SS - PB0 + + PF, // D18 - A0 - PF7 + PF, // D19 - A1 - PF6 + PF, // D20 - A2 - PF5 + PF, // D21 - A3 - PF4 + PF, // D22 - A4 - PF1 + PF, // D23 - A5 - PF0 + + PD, // D24 / D4 - A6 - PD4 + PD, // D25 / D6 - A7 - PD7 + PB, // D26 / D8 - A8 - PB4 + PB, // D27 / D9 - A9 - PB5 + PB, // D28 / D10 - A10 - PB6 + PD, // D29 / D12 - A11 - PD6 + PD, // D30 - PD5 +}; + +const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[] = { + _BV(2), // D0 - PD2 + _BV(3), // D1 - PD3 + _BV(1), // D2 - PD1 + _BV(0), // D3 - PD0 + _BV(4), // D4 - PD4 + _BV(6), // D5 - PC6 + _BV(7), // D6 - PD7 + _BV(6), // D7 - PE6 + + _BV(4), // D8 - PB4 + _BV(5), // D9 - PB5 + _BV(6), // D10 - PB6 + _BV(7), // D11 - PB7 + _BV(6), // D12 - PD6 + _BV(7), // D13 - PC7 + + _BV(3), // D14 - MISO - PB3 + _BV(1), // D15 - SCK - PB1 + _BV(2), // D16 - MOSI - PB2 + _BV(0), // D17 - SS - PB0 + + _BV(7), // D18 - A0 - PF7 + _BV(6), // D19 - A1 - PF6 + _BV(5), // D20 - A2 - PF5 + _BV(4), // D21 - A3 - PF4 + _BV(1), // D22 - A4 - PF1 + _BV(0), // D23 - A5 - PF0 + + _BV(4), // D24 / D4 - A6 - PD4 + _BV(7), // D25 / D6 - A7 - PD7 + _BV(4), // D26 / D8 - A8 - PB4 + _BV(5), // D27 / D9 - A9 - PB5 + _BV(6), // D28 / D10 - A10 - PB6 + _BV(6), // D29 / D12 - A11 - PD6 + _BV(5), // D30 - PD5 +}; + +const uint8_t PROGMEM digital_pin_to_timer_PGM[] = { + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + TIMER0B, /* 3 */ + NOT_ON_TIMER, + TIMER3A, /* 5 */ + TIMER4D, /* 6 */ + NOT_ON_TIMER, + + NOT_ON_TIMER, + TIMER1A, /* 9 */ + TIMER1B, /* 10 */ + TIMER0A, /* 11 */ + + NOT_ON_TIMER, + TIMER4A, /* 13 */ + + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, +}; + +const uint8_t PROGMEM analog_pin_to_channel_PGM[] = { + 7, // A0 PF7 ADC7 + 6, // A1 PF6 ADC6 + 5, // A2 PF5 ADC5 + 4, // A3 PF4 ADC4 + 1, // A4 PF1 ADC1 + 0, // A5 PF0 ADC0 + 8, // A6 D4 PD4 ADC8 + 10, // A7 D6 PD7 ADC10 + 11, // A8 D8 PB4 ADC11 + 12, // A9 D9 PB5 ADC12 + 13, // A10 D10 PB6 ADC13 + 9 // A11 D12 PD6 ADC9 +}; + +#endif /* ARDUINO_MAIN */ + +// These serial port names are intended to allow libraries and architecture-neutral +// sketches to automatically default to the correct port name for a particular type +// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, +// the first hardware serial port whose RX/TX pins are not dedicated to another use. +// +// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor +// +// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial +// +// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library +// +// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. +// +// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX +// pins are NOT connected to anything by default. +#define SERIAL_PORT_MONITOR Serial +#define SERIAL_PORT_USBVIRTUAL Serial +#define SERIAL_PORT_HARDWARE Serial1 +#define SERIAL_PORT_HARDWARE_OPEN Serial1 + +// Alias SerialUSB to Serial +#define SerialUSB SERIAL_PORT_USBVIRTUAL + +// Bootloader related fields +// Old Caterina bootloader places the MAGIC key into unsafe RAM locations (it can be rewritten +// by the running sketch before to actual reboot). +// Newer bootloaders, recognizable by the LUFA "signature" at the end of the flash, can handle both +// the usafe and the safe location. Check once (in USBCore.cpp) if the bootloader in new, then set the global +// _updatedLUFAbootloader variable to true/false and place the magic key consequently +#ifndef MAGIC_KEY +#define MAGIC_KEY 0x7777 +#endif + +#ifndef MAGIC_KEY_POS +#define MAGIC_KEY_POS 0x0800 +#endif + +#ifndef NEW_LUFA_SIGNATURE +#define NEW_LUFA_SIGNATURE 0xDCFB +#endif + +#endif /* Pins_Arduino_h */ diff --git a/hardware/arduino/avr/variants/eightanaloginputs/pins_arduino.h b/hardware/arduino/avr/variants/eightanaloginputs/pins_arduino.h new file mode 100644 index 0000000000000000000000000000000000000000..4ccf8ba27b02180fd9c9ba3bc59ac9a9e0663796 --- /dev/null +++ b/hardware/arduino/avr/variants/eightanaloginputs/pins_arduino.h @@ -0,0 +1,25 @@ +/* + pins_arduino.h - Pin definition functions for Arduino + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2007 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA +*/ + +#include "../standard/pins_arduino.h" +#undef NUM_ANALOG_INPUTS +#define NUM_ANALOG_INPUTS 8 diff --git a/hardware/arduino/avr/variants/ethernet/pins_arduino.h b/hardware/arduino/avr/variants/ethernet/pins_arduino.h new file mode 100644 index 0000000000000000000000000000000000000000..f12f3215bf6d7f3c100a5681e3f87ffbb62581f1 --- /dev/null +++ b/hardware/arduino/avr/variants/ethernet/pins_arduino.h @@ -0,0 +1,255 @@ +/* + pins_arduino.h - Pin definition functions for Arduino + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2007 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA +*/ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define NUM_DIGITAL_PINS 20 +#define NUM_ANALOG_INPUTS 6 +#define analogInputToDigitalPin(p) ((p < 6) ? (p) + 14 : -1) + +#if defined(__AVR_ATmega8__) +#define digitalPinHasPWM(p) ((p) == 9 || (p) == 10 || (p) == 11) +#else +#define digitalPinHasPWM(p) ((p) == 3 || (p) == 5 || (p) == 6 || (p) == 9 || (p) == 10 || (p) == 11) +#endif + +#define PIN_SPI_SS (10) +#define PIN_SPI_MOSI (11) +#define PIN_SPI_MISO (12) +#define PIN_SPI_SCK (13) + +static const uint8_t SS = PIN_SPI_SS; +static const uint8_t MOSI = PIN_SPI_MOSI; +static const uint8_t MISO = PIN_SPI_MISO; +static const uint8_t SCK = PIN_SPI_SCK; + +#define PIN_WIRE_SDA (18) +#define PIN_WIRE_SCL (19) + +static const uint8_t SDA = PIN_WIRE_SDA; +static const uint8_t SCL = PIN_WIRE_SCL; + +#define LED_BUILTIN 9 + +#define PIN_A0 (14) +#define PIN_A1 (15) +#define PIN_A2 (16) +#define PIN_A3 (17) +#define PIN_A4 (18) +#define PIN_A5 (19) +#define PIN_A6 (20) +#define PIN_A7 (21) + +static const uint8_t A0 = PIN_A0; +static const uint8_t A1 = PIN_A1; +static const uint8_t A2 = PIN_A2; +static const uint8_t A3 = PIN_A3; +static const uint8_t A4 = PIN_A4; +static const uint8_t A5 = PIN_A5; +static const uint8_t A6 = PIN_A6; +static const uint8_t A7 = PIN_A7; + +#define digitalPinToPCICR(p) (((p) >= 0 && (p) <= 21) ? (&PCICR) : ((uint8_t *)0)) +#define digitalPinToPCICRbit(p) (((p) <= 7) ? 2 : (((p) <= 13) ? 0 : 1)) +#define digitalPinToPCMSK(p) (((p) <= 7) ? (&PCMSK2) : (((p) <= 13) ? (&PCMSK0) : (((p) <= 21) ? (&PCMSK1) : ((uint8_t *)0)))) +#define digitalPinToPCMSKbit(p) (((p) <= 7) ? (p) : (((p) <= 13) ? ((p) - 8) : ((p) - 14))) + +#define digitalPinToInterrupt(p) ((p) == 2 ? 0 : ((p) == 3 ? 1 : NOT_AN_INTERRUPT)) + +#ifdef ARDUINO_MAIN + +// On the Arduino board, digital pins are also used +// for the analog output (software PWM). Analog input +// pins are a separate set. + +// ATMEL ATMEGA8 & 168 / ARDUINO +// +// +-\/-+ +// PC6 1| |28 PC5 (AI 5) +// (D 0) PD0 2| |27 PC4 (AI 4) +// (D 1) PD1 3| |26 PC3 (AI 3) +// (D 2) PD2 4| |25 PC2 (AI 2) +// PWM+ (D 3) PD3 5| |24 PC1 (AI 1) +// (D 4) PD4 6| |23 PC0 (AI 0) +// VCC 7| |22 GND +// GND 8| |21 AREF +// PB6 9| |20 AVCC +// PB7 10| |19 PB5 (D 13) +// PWM+ (D 5) PD5 11| |18 PB4 (D 12) +// PWM+ (D 6) PD6 12| |17 PB3 (D 11) PWM +// (D 7) PD7 13| |16 PB2 (D 10) PWM +// (D 8) PB0 14| |15 PB1 (D 9) PWM +// +----+ +// +// (PWM+ indicates the additional PWM pins on the ATmega168.) + +// ATMEL ATMEGA1280 / ARDUINO +// +// 0-7 PE0-PE7 works +// 8-13 PB0-PB5 works +// 14-21 PA0-PA7 works +// 22-29 PH0-PH7 works +// 30-35 PG5-PG0 works +// 36-43 PC7-PC0 works +// 44-51 PJ7-PJ0 works +// 52-59 PL7-PL0 works +// 60-67 PD7-PD0 works +// A0-A7 PF0-PF7 +// A8-A15 PK0-PK7 + + +// these arrays map port names (e.g. port B) to the +// appropriate addresses for various functions (e.g. reading +// and writing) +const uint16_t PROGMEM port_to_mode_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &DDRB, + (uint16_t) &DDRC, + (uint16_t) &DDRD, +}; + +const uint16_t PROGMEM port_to_output_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &PORTB, + (uint16_t) &PORTC, + (uint16_t) &PORTD, +}; + +const uint16_t PROGMEM port_to_input_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &PINB, + (uint16_t) &PINC, + (uint16_t) &PIND, +}; + +const uint8_t PROGMEM digital_pin_to_port_PGM[] = { + PD, /* 0 */ + PD, + PD, + PD, + PD, + PD, + PD, + PD, + PB, /* 8 */ + PB, + PB, + PB, + PB, + PB, + PC, /* 14 */ + PC, + PC, + PC, + PC, + PC, +}; + +const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[] = { + _BV(0), /* 0, port D */ + _BV(1), + _BV(2), + _BV(3), + _BV(4), + _BV(5), + _BV(6), + _BV(7), + _BV(0), /* 8, port B */ + _BV(1), + _BV(2), + _BV(3), + _BV(4), + _BV(5), + _BV(0), /* 14, port C */ + _BV(1), + _BV(2), + _BV(3), + _BV(4), + _BV(5), +}; + +const uint8_t PROGMEM digital_pin_to_timer_PGM[] = { + NOT_ON_TIMER, /* 0 - port D */ + NOT_ON_TIMER, + NOT_ON_TIMER, + // on the ATmega168, digital pin 3 has hardware pwm +#if defined(__AVR_ATmega8__) + NOT_ON_TIMER, +#else + TIMER2B, +#endif + NOT_ON_TIMER, + // on the ATmega168, digital pins 5 and 6 have hardware pwm +#if defined(__AVR_ATmega8__) + NOT_ON_TIMER, + NOT_ON_TIMER, +#else + TIMER0B, + TIMER0A, +#endif + NOT_ON_TIMER, + NOT_ON_TIMER, /* 8 - port B */ + TIMER1A, + TIMER1B, +#if defined(__AVR_ATmega8__) + TIMER2, +#else + TIMER2A, +#endif + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, /* 14 - port C */ + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, +}; + +#endif + +// These serial port names are intended to allow libraries and architecture-neutral +// sketches to automatically default to the correct port name for a particular type +// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, +// the first hardware serial port whose RX/TX pins are not dedicated to another use. +// +// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor +// +// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial +// +// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library +// +// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. +// +// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX +// pins are NOT connected to anything by default. +#define SERIAL_PORT_HARDWARE Serial +#define SERIAL_PORT_HARDWARE_OPEN Serial +#define SERIAL_PORT_MONITOR Serial + +#endif diff --git a/hardware/arduino/avr/variants/gemma/pins_arduino.h b/hardware/arduino/avr/variants/gemma/pins_arduino.h new file mode 100644 index 0000000000000000000000000000000000000000..e0ec217aebd40e92a6bada1dae2aec83a53be4a1 --- /dev/null +++ b/hardware/arduino/avr/variants/gemma/pins_arduino.h @@ -0,0 +1,140 @@ +/* + pins_arduino.c - pin definitions for the Arduino board + Part of Arduino / Wiring Lite + + Copyright (c) 2005 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + Modified 28-08-2009 for attiny84 R.Wiersma + Modified 09-10-2009 for attiny45 A.Saporetti +*/ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// Defines to make D4 support PWM +// See for more info: http://forums.adafruit.com/viewtopic.php?f=52&t=43951 +//#define TCCR1A GTCCR +//#define WGM10 PWM1B + +// ATMEL ATTINY45 / ARDUINO +// +// +-\/-+ +// Ain0 (D 5) PB5 1| |8 Vcc +// Ain3 (D 3) PB3 2| |7 PB2 (D 2) Ain1 +// Ain2 (D 4) PB4 3| |6 PB1 (D 1) pwm1 +// GND 4| |5 PB0 (D 0) pwm0 +// +----+ + +#define NUM_DIGITAL_PINS 3 +#define NUM_ANALOG_INPUTS 1 +#define LED_BUILTIN 1 + +#define PIN_A0 (6) +#define PIN_A1 (7) +#define PIN_A2 (8) +#define PIN_A3 (9) + +static const uint8_t A0 = PIN_A0; +static const uint8_t A1 = PIN_A1; +static const uint8_t A2 = PIN_A2; +static const uint8_t A3 = PIN_A3; + +#define digitalPinToPCICR(p) ( ((p) >= 0 && (p) <= 4) ? (&GIMSK) : ((uint8_t *)0) ) +#define digitalPinToPCICRbit(p) ( PCIE ) +#define digitalPinToPCMSK(p) ( ((p) <= 4) ? (&PCMSK) : ((uint8_t *)0) ) +#define digitalPinToPCMSKbit(p) ( (p) ) + +#define digitalPinToInterrupt(p) ((p) == 2 ? 0 : NOT_AN_INTERRUPT) + +#define analogPinToChannel(p) ( (p) < 6 ? (p) : (p) - 6 ) + +#define TCCR1A GTCCR + +#ifdef ARDUINO_MAIN + +void initVariant() +{ + GTCCR |= (1 << PWM1B); +} + +// these arrays map port names (e.g. port B) to the +// appropriate addresses for various functions (e.g. reading +// and writing) tiny45 only port B +const uint16_t PROGMEM port_to_mode_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &DDRB, +}; + +const uint16_t PROGMEM port_to_output_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &PORTB, +}; + +const uint16_t PROGMEM port_to_input_PGM[] = { + NOT_A_PIN, + NOT_A_PIN, + (uint16_t) &PINB, +}; + +const uint8_t PROGMEM digital_pin_to_port_PGM[] = { + PB, /* 0 */ + PB, + PB, + PB, + PB, + PB, // 5 + PB, // A0 + PB, + PB, + PB, // A4 + +}; + +const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[] = { + _BV(0), /* 0, port B */ + _BV(1), + _BV(2), + _BV(3), /* 3 port B */ + _BV(4), + _BV(5), + _BV(5), + _BV(2), + _BV(4), + _BV(3), +}; + +const uint8_t PROGMEM digital_pin_to_timer_PGM[] = { + TIMER0A, /* OC0A */ + TIMER0B, + NOT_ON_TIMER, + NOT_ON_TIMER, + TIMER1B, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, +}; + +#endif + +#endif diff --git a/hardware/arduino/avr/variants/leonardo/pins_arduino.h b/hardware/arduino/avr/variants/leonardo/pins_arduino.h new file mode 100644 index 0000000000000000000000000000000000000000..8586dac0a7a5534fb980586a5c0e3dfc5834a491 --- /dev/null +++ b/hardware/arduino/avr/variants/leonardo/pins_arduino.h @@ -0,0 +1,391 @@ +/* + pins_arduino.h - Pin definition functions for Arduino + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2007 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA +*/ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// Workaround for wrong definitions in "iom32u4.h". +// This should be fixed in the AVR toolchain. +#undef UHCON +#undef UHINT +#undef UHIEN +#undef UHADDR +#undef UHFNUM +#undef UHFNUML +#undef UHFNUMH +#undef UHFLEN +#undef UPINRQX +#undef UPINTX +#undef UPNUM +#undef UPRST +#undef UPCONX +#undef UPCFG0X +#undef UPCFG1X +#undef UPSTAX +#undef UPCFG2X +#undef UPIENX +#undef UPDATX +#undef TCCR2A +#undef WGM20 +#undef WGM21 +#undef COM2B0 +#undef COM2B1 +#undef COM2A0 +#undef COM2A1 +#undef TCCR2B +#undef CS20 +#undef CS21 +#undef CS22 +#undef WGM22 +#undef FOC2B +#undef FOC2A +#undef TCNT2 +#undef TCNT2_0 +#undef TCNT2_1 +#undef TCNT2_2 +#undef TCNT2_3 +#undef TCNT2_4 +#undef TCNT2_5 +#undef TCNT2_6 +#undef TCNT2_7 +#undef OCR2A +#undef OCR2_0 +#undef OCR2_1 +#undef OCR2_2 +#undef OCR2_3 +#undef OCR2_4 +#undef OCR2_5 +#undef OCR2_6 +#undef OCR2_7 +#undef OCR2B +#undef OCR2_0 +#undef OCR2_1 +#undef OCR2_2 +#undef OCR2_3 +#undef OCR2_4 +#undef OCR2_5 +#undef OCR2_6 +#undef OCR2_7 + +#define NUM_DIGITAL_PINS 31 +#define NUM_ANALOG_INPUTS 12 + +#define TX_RX_LED_INIT DDRD |= (1<<5), DDRB |= (1<<0) +#define TXLED0 PORTD |= (1<<5) +#define TXLED1 PORTD &= ~(1<<5) +#define RXLED0 PORTB |= (1<<0) +#define RXLED1 PORTB &= ~(1<<0) + +#define PIN_WIRE_SDA (2) +#define PIN_WIRE_SCL (3) + +static const uint8_t SDA = PIN_WIRE_SDA; +static const uint8_t SCL = PIN_WIRE_SCL; + +#define LED_BUILTIN 13 +#define LED_BUILTIN_RX 17 +#define LED_BUILTIN_TX 30 + +// Map SPI port to 'new' pins D14..D17 +#define PIN_SPI_SS (17) +#define PIN_SPI_MOSI (16) +#define PIN_SPI_MISO (14) +#define PIN_SPI_SCK (15) + +static const uint8_t SS = PIN_SPI_SS; +static const uint8_t MOSI = PIN_SPI_MOSI; +static const uint8_t MISO = PIN_SPI_MISO; +static const uint8_t SCK = PIN_SPI_SCK; + +// Mapping of analog pins as digital I/O +// A6-A11 share with digital pins +#define PIN_A0 (18) +#define PIN_A1 (19) +#define PIN_A2 (20) +#define PIN_A3 (21) +#define PIN_A4 (22) +#define PIN_A5 (23) +#define PIN_A6 (24) +#define PIN_A7 (25) +#define PIN_A8 (26) +#define PIN_A9 (27) +#define PIN_A10 (28) +#define PIN_A11 (29) + +static const uint8_t A0 = PIN_A0; +static const uint8_t A1 = PIN_A1; +static const uint8_t A2 = PIN_A2; +static const uint8_t A3 = PIN_A3; +static const uint8_t A4 = PIN_A4; +static const uint8_t A5 = PIN_A5; +static const uint8_t A6 = PIN_A6; // D4 +static const uint8_t A7 = PIN_A7; // D6 +static const uint8_t A8 = PIN_A8; // D8 +static const uint8_t A9 = PIN_A9; // D9 +static const uint8_t A10 = PIN_A10; // D10 +static const uint8_t A11 = PIN_A11; // D12 + +#define digitalPinToPCICR(p) ((((p) >= 8 && (p) <= 11) || ((p) >= 14 && (p) <= 17) || ((p) >= A8 && (p) <= A10)) ? (&PCICR) : ((uint8_t *)0)) +#define digitalPinToPCICRbit(p) 0 +#define digitalPinToPCMSK(p) ((((p) >= 8 && (p) <= 11) || ((p) >= 14 && (p) <= 17) || ((p) >= A8 && (p) <= A10)) ? (&PCMSK0) : ((uint8_t *)0)) +#define digitalPinToPCMSKbit(p) ( ((p) >= 8 && (p) <= 11) ? (p) - 4 : ((p) == 14 ? 3 : ((p) == 15 ? 1 : ((p) == 16 ? 2 : ((p) == 17 ? 0 : (p - A8 + 4)))))) + +// __AVR_ATmega32U4__ has an unusual mapping of pins to channels +extern const uint8_t PROGMEM analog_pin_to_channel_PGM[]; +#define analogPinToChannel(P) ( pgm_read_byte( analog_pin_to_channel_PGM + (P) ) ) + +#define digitalPinHasPWM(p) ((p) == 3 || (p) == 5 || (p) == 6 || (p) == 9 || (p) == 10 || (p) == 11 || (p) == 13) + +#define digitalPinToInterrupt(p) ((p) == 0 ? 2 : ((p) == 1 ? 3 : ((p) == 2 ? 1 : ((p) == 3 ? 0 : ((p) == 7 ? 4 : NOT_AN_INTERRUPT))))) + +#ifdef ARDUINO_MAIN + +// On the Arduino board, digital pins are also used +// for the analog output (software PWM). Analog input +// pins are a separate set. + +// ATMEL ATMEGA32U4 / ARDUINO LEONARDO +// +// D0 PD2 RXD1/INT2 +// D1 PD3 TXD1/INT3 +// D2 PD1 SDA SDA/INT1 +// D3# PD0 PWM8/SCL OC0B/SCL/INT0 +// D4 A6 PD4 ADC8 +// D5# PC6 ??? OC3A/#OC4A +// D6# A7 PD7 FastPWM #OC4D/ADC10 +// D7 PE6 INT6/AIN0 +// +// D8 A8 PB4 ADC11/PCINT4 +// D9# A9 PB5 PWM16 OC1A/#OC4B/ADC12/PCINT5 +// D10# A10 PB6 PWM16 OC1B/0c4B/ADC13/PCINT6 +// D11# PB7 PWM8/16 0C0A/OC1C/#RTS/PCINT7 +// D12 A11 PD6 T1/#OC4D/ADC9 +// D13# PC7 PWM10 CLK0/OC4A +// +// A0 D18 PF7 ADC7 +// A1 D19 PF6 ADC6 +// A2 D20 PF5 ADC5 +// A3 D21 PF4 ADC4 +// A4 D22 PF1 ADC1 +// A5 D23 PF0 ADC0 +// +// New pins D14..D17 to map SPI port to digital pins +// +// MISO D14 PB3 MISO,PCINT3 +// SCK D15 PB1 SCK,PCINT1 +// MOSI D16 PB2 MOSI,PCINT2 +// SS D17 PB0 RXLED,SS/PCINT0 +// +// TXLED D30 PD5 XCK1 +// RXLED D17 PB0 +// HWB PE2 HWB + +// these arrays map port names (e.g. port B) to the +// appropriate addresses for various functions (e.g. reading +// and writing) +const uint16_t PROGMEM port_to_mode_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &DDRB, + (uint16_t) &DDRC, + (uint16_t) &DDRD, + (uint16_t) &DDRE, + (uint16_t) &DDRF, +}; + +const uint16_t PROGMEM port_to_output_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &PORTB, + (uint16_t) &PORTC, + (uint16_t) &PORTD, + (uint16_t) &PORTE, + (uint16_t) &PORTF, +}; + +const uint16_t PROGMEM port_to_input_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &PINB, + (uint16_t) &PINC, + (uint16_t) &PIND, + (uint16_t) &PINE, + (uint16_t) &PINF, +}; + +const uint8_t PROGMEM digital_pin_to_port_PGM[] = { + PD, // D0 - PD2 + PD, // D1 - PD3 + PD, // D2 - PD1 + PD, // D3 - PD0 + PD, // D4 - PD4 + PC, // D5 - PC6 + PD, // D6 - PD7 + PE, // D7 - PE6 + + PB, // D8 - PB4 + PB, // D9 - PB5 + PB, // D10 - PB6 + PB, // D11 - PB7 + PD, // D12 - PD6 + PC, // D13 - PC7 + + PB, // D14 - MISO - PB3 + PB, // D15 - SCK - PB1 + PB, // D16 - MOSI - PB2 + PB, // D17 - SS - PB0 + + PF, // D18 - A0 - PF7 + PF, // D19 - A1 - PF6 + PF, // D20 - A2 - PF5 + PF, // D21 - A3 - PF4 + PF, // D22 - A4 - PF1 + PF, // D23 - A5 - PF0 + + PD, // D24 / D4 - A6 - PD4 + PD, // D25 / D6 - A7 - PD7 + PB, // D26 / D8 - A8 - PB4 + PB, // D27 / D9 - A9 - PB5 + PB, // D28 / D10 - A10 - PB6 + PD, // D29 / D12 - A11 - PD6 + PD, // D30 / TX Led - PD5 +}; + +const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[] = { + _BV(2), // D0 - PD2 + _BV(3), // D1 - PD3 + _BV(1), // D2 - PD1 + _BV(0), // D3 - PD0 + _BV(4), // D4 - PD4 + _BV(6), // D5 - PC6 + _BV(7), // D6 - PD7 + _BV(6), // D7 - PE6 + + _BV(4), // D8 - PB4 + _BV(5), // D9 - PB5 + _BV(6), // D10 - PB6 + _BV(7), // D11 - PB7 + _BV(6), // D12 - PD6 + _BV(7), // D13 - PC7 + + _BV(3), // D14 - MISO - PB3 + _BV(1), // D15 - SCK - PB1 + _BV(2), // D16 - MOSI - PB2 + _BV(0), // D17 - SS - PB0 + + _BV(7), // D18 - A0 - PF7 + _BV(6), // D19 - A1 - PF6 + _BV(5), // D20 - A2 - PF5 + _BV(4), // D21 - A3 - PF4 + _BV(1), // D22 - A4 - PF1 + _BV(0), // D23 - A5 - PF0 + + _BV(4), // D24 / D4 - A6 - PD4 + _BV(7), // D25 / D6 - A7 - PD7 + _BV(4), // D26 / D8 - A8 - PB4 + _BV(5), // D27 / D9 - A9 - PB5 + _BV(6), // D28 / D10 - A10 - PB6 + _BV(6), // D29 / D12 - A11 - PD6 + _BV(5), // D30 / TX Led - PD5 +}; + +const uint8_t PROGMEM digital_pin_to_timer_PGM[] = { + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + TIMER0B, /* 3 */ + NOT_ON_TIMER, + TIMER3A, /* 5 */ + TIMER4D, /* 6 */ + NOT_ON_TIMER, + + NOT_ON_TIMER, + TIMER1A, /* 9 */ + TIMER1B, /* 10 */ + TIMER0A, /* 11 */ + + NOT_ON_TIMER, + TIMER4A, /* 13 */ + + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, +}; + +const uint8_t PROGMEM analog_pin_to_channel_PGM[] = { + 7, // A0 PF7 ADC7 + 6, // A1 PF6 ADC6 + 5, // A2 PF5 ADC5 + 4, // A3 PF4 ADC4 + 1, // A4 PF1 ADC1 + 0, // A5 PF0 ADC0 + 8, // A6 D4 PD4 ADC8 + 10, // A7 D6 PD7 ADC10 + 11, // A8 D8 PB4 ADC11 + 12, // A9 D9 PB5 ADC12 + 13, // A10 D10 PB6 ADC13 + 9 // A11 D12 PD6 ADC9 +}; + +#endif /* ARDUINO_MAIN */ + +// These serial port names are intended to allow libraries and architecture-neutral +// sketches to automatically default to the correct port name for a particular type +// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, +// the first hardware serial port whose RX/TX pins are not dedicated to another use. +// +// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor +// +// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial +// +// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library +// +// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. +// +// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX +// pins are NOT connected to anything by default. +#define SERIAL_PORT_MONITOR Serial +#define SERIAL_PORT_USBVIRTUAL Serial +#define SERIAL_PORT_HARDWARE Serial1 +#define SERIAL_PORT_HARDWARE_OPEN Serial1 + +// Alias SerialUSB to Serial +#define SerialUSB SERIAL_PORT_USBVIRTUAL + +#endif /* Pins_Arduino_h */ diff --git a/hardware/arduino/avr/variants/mega/pins_arduino.h b/hardware/arduino/avr/variants/mega/pins_arduino.h new file mode 100644 index 0000000000000000000000000000000000000000..5115c044a4c8a9913e1a0bd3cb571d455c1df4c1 --- /dev/null +++ b/hardware/arduino/avr/variants/mega/pins_arduino.h @@ -0,0 +1,413 @@ +/* + pins_arduino.h - Pin definition functions for Arduino + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2007 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA +*/ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define NUM_DIGITAL_PINS 70 +#define NUM_ANALOG_INPUTS 16 +#define analogInputToDigitalPin(p) ((p < 16) ? (p) + 54 : -1) +#define digitalPinHasPWM(p) (((p) >= 2 && (p) <= 13) || ((p) >= 44 && (p)<= 46)) + +#define PIN_SPI_SS (53) +#define PIN_SPI_MOSI (51) +#define PIN_SPI_MISO (50) +#define PIN_SPI_SCK (52) + +static const uint8_t SS = PIN_SPI_SS; +static const uint8_t MOSI = PIN_SPI_MOSI; +static const uint8_t MISO = PIN_SPI_MISO; +static const uint8_t SCK = PIN_SPI_SCK; + +#define PIN_WIRE_SDA (20) +#define PIN_WIRE_SCL (21) + +static const uint8_t SDA = PIN_WIRE_SDA; +static const uint8_t SCL = PIN_WIRE_SCL; + +#define LED_BUILTIN 13 + +#define PIN_A0 (54) +#define PIN_A1 (55) +#define PIN_A2 (56) +#define PIN_A3 (57) +#define PIN_A4 (58) +#define PIN_A5 (59) +#define PIN_A6 (60) +#define PIN_A7 (61) +#define PIN_A8 (62) +#define PIN_A9 (63) +#define PIN_A10 (64) +#define PIN_A11 (65) +#define PIN_A12 (66) +#define PIN_A13 (67) +#define PIN_A14 (68) +#define PIN_A15 (69) + +static const uint8_t A0 = PIN_A0; +static const uint8_t A1 = PIN_A1; +static const uint8_t A2 = PIN_A2; +static const uint8_t A3 = PIN_A3; +static const uint8_t A4 = PIN_A4; +static const uint8_t A5 = PIN_A5; +static const uint8_t A6 = PIN_A6; +static const uint8_t A7 = PIN_A7; +static const uint8_t A8 = PIN_A8; +static const uint8_t A9 = PIN_A9; +static const uint8_t A10 = PIN_A10; +static const uint8_t A11 = PIN_A11; +static const uint8_t A12 = PIN_A12; +static const uint8_t A13 = PIN_A13; +static const uint8_t A14 = PIN_A14; +static const uint8_t A15 = PIN_A15; + +// A majority of the pins are NOT PCINTs, SO BE WARNED (i.e. you cannot use them as receive pins) +// Only pins available for RECEIVE (TRANSMIT can be on any pin): +// (I've deliberately left out pin mapping to the Hardware USARTs - seems senseless to me) +// Pins: 10, 11, 12, 13, 50, 51, 52, 53, 62, 63, 64, 65, 66, 67, 68, 69 + +#define digitalPinToPCICR(p) ( (((p) >= 10) && ((p) <= 13)) || \ + (((p) >= 50) && ((p) <= 53)) || \ + (((p) >= 62) && ((p) <= 69)) ? (&PCICR) : ((uint8_t *)0) ) + +#define digitalPinToPCICRbit(p) ( (((p) >= 10) && ((p) <= 13)) || (((p) >= 50) && ((p) <= 53)) ? 0 : \ + ( (((p) >= 62) && ((p) <= 69)) ? 2 : \ + 0 ) ) + +#define digitalPinToPCMSK(p) ( (((p) >= 10) && ((p) <= 13)) || (((p) >= 50) && ((p) <= 53)) ? (&PCMSK0) : \ + ( (((p) >= 62) && ((p) <= 69)) ? (&PCMSK2) : \ + ((uint8_t *)0) ) ) + +#define digitalPinToPCMSKbit(p) ( (((p) >= 10) && ((p) <= 13)) ? ((p) - 6) : \ + ( ((p) == 50) ? 3 : \ + ( ((p) == 51) ? 2 : \ + ( ((p) == 52) ? 1 : \ + ( ((p) == 53) ? 0 : \ + ( (((p) >= 62) && ((p) <= 69)) ? ((p) - 62) : \ + 0 ) ) ) ) ) ) + +#define digitalPinToInterrupt(p) ((p) == 2 ? 0 : ((p) == 3 ? 1 : ((p) >= 18 && (p) <= 21 ? 23 - (p) : NOT_AN_INTERRUPT))) + +#ifdef ARDUINO_MAIN + +const uint16_t PROGMEM port_to_mode_PGM[] = { + NOT_A_PORT, + (uint16_t) &DDRA, + (uint16_t) &DDRB, + (uint16_t) &DDRC, + (uint16_t) &DDRD, + (uint16_t) &DDRE, + (uint16_t) &DDRF, + (uint16_t) &DDRG, + (uint16_t) &DDRH, + NOT_A_PORT, + (uint16_t) &DDRJ, + (uint16_t) &DDRK, + (uint16_t) &DDRL, +}; + +const uint16_t PROGMEM port_to_output_PGM[] = { + NOT_A_PORT, + (uint16_t) &PORTA, + (uint16_t) &PORTB, + (uint16_t) &PORTC, + (uint16_t) &PORTD, + (uint16_t) &PORTE, + (uint16_t) &PORTF, + (uint16_t) &PORTG, + (uint16_t) &PORTH, + NOT_A_PORT, + (uint16_t) &PORTJ, + (uint16_t) &PORTK, + (uint16_t) &PORTL, +}; + +const uint16_t PROGMEM port_to_input_PGM[] = { + NOT_A_PIN, + (uint16_t) &PINA, + (uint16_t) &PINB, + (uint16_t) &PINC, + (uint16_t) &PIND, + (uint16_t) &PINE, + (uint16_t) &PINF, + (uint16_t) &PING, + (uint16_t) &PINH, + NOT_A_PIN, + (uint16_t) &PINJ, + (uint16_t) &PINK, + (uint16_t) &PINL, +}; + +const uint8_t PROGMEM digital_pin_to_port_PGM[] = { + // PORTLIST + // ------------------------------------------- + PE , // PE 0 ** 0 ** USART0_RX + PE , // PE 1 ** 1 ** USART0_TX + PE , // PE 4 ** 2 ** PWM2 + PE , // PE 5 ** 3 ** PWM3 + PG , // PG 5 ** 4 ** PWM4 + PE , // PE 3 ** 5 ** PWM5 + PH , // PH 3 ** 6 ** PWM6 + PH , // PH 4 ** 7 ** PWM7 + PH , // PH 5 ** 8 ** PWM8 + PH , // PH 6 ** 9 ** PWM9 + PB , // PB 4 ** 10 ** PWM10 + PB , // PB 5 ** 11 ** PWM11 + PB , // PB 6 ** 12 ** PWM12 + PB , // PB 7 ** 13 ** PWM13 + PJ , // PJ 1 ** 14 ** USART3_TX + PJ , // PJ 0 ** 15 ** USART3_RX + PH , // PH 1 ** 16 ** USART2_TX + PH , // PH 0 ** 17 ** USART2_RX + PD , // PD 3 ** 18 ** USART1_TX + PD , // PD 2 ** 19 ** USART1_RX + PD , // PD 1 ** 20 ** I2C_SDA + PD , // PD 0 ** 21 ** I2C_SCL + PA , // PA 0 ** 22 ** D22 + PA , // PA 1 ** 23 ** D23 + PA , // PA 2 ** 24 ** D24 + PA , // PA 3 ** 25 ** D25 + PA , // PA 4 ** 26 ** D26 + PA , // PA 5 ** 27 ** D27 + PA , // PA 6 ** 28 ** D28 + PA , // PA 7 ** 29 ** D29 + PC , // PC 7 ** 30 ** D30 + PC , // PC 6 ** 31 ** D31 + PC , // PC 5 ** 32 ** D32 + PC , // PC 4 ** 33 ** D33 + PC , // PC 3 ** 34 ** D34 + PC , // PC 2 ** 35 ** D35 + PC , // PC 1 ** 36 ** D36 + PC , // PC 0 ** 37 ** D37 + PD , // PD 7 ** 38 ** D38 + PG , // PG 2 ** 39 ** D39 + PG , // PG 1 ** 40 ** D40 + PG , // PG 0 ** 41 ** D41 + PL , // PL 7 ** 42 ** D42 + PL , // PL 6 ** 43 ** D43 + PL , // PL 5 ** 44 ** D44 + PL , // PL 4 ** 45 ** D45 + PL , // PL 3 ** 46 ** D46 + PL , // PL 2 ** 47 ** D47 + PL , // PL 1 ** 48 ** D48 + PL , // PL 0 ** 49 ** D49 + PB , // PB 3 ** 50 ** SPI_MISO + PB , // PB 2 ** 51 ** SPI_MOSI + PB , // PB 1 ** 52 ** SPI_SCK + PB , // PB 0 ** 53 ** SPI_SS + PF , // PF 0 ** 54 ** A0 + PF , // PF 1 ** 55 ** A1 + PF , // PF 2 ** 56 ** A2 + PF , // PF 3 ** 57 ** A3 + PF , // PF 4 ** 58 ** A4 + PF , // PF 5 ** 59 ** A5 + PF , // PF 6 ** 60 ** A6 + PF , // PF 7 ** 61 ** A7 + PK , // PK 0 ** 62 ** A8 + PK , // PK 1 ** 63 ** A9 + PK , // PK 2 ** 64 ** A10 + PK , // PK 3 ** 65 ** A11 + PK , // PK 4 ** 66 ** A12 + PK , // PK 5 ** 67 ** A13 + PK , // PK 6 ** 68 ** A14 + PK , // PK 7 ** 69 ** A15 +}; + +const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[] = { + // PIN IN PORT + // ------------------------------------------- + _BV( 0 ) , // PE 0 ** 0 ** USART0_RX + _BV( 1 ) , // PE 1 ** 1 ** USART0_TX + _BV( 4 ) , // PE 4 ** 2 ** PWM2 + _BV( 5 ) , // PE 5 ** 3 ** PWM3 + _BV( 5 ) , // PG 5 ** 4 ** PWM4 + _BV( 3 ) , // PE 3 ** 5 ** PWM5 + _BV( 3 ) , // PH 3 ** 6 ** PWM6 + _BV( 4 ) , // PH 4 ** 7 ** PWM7 + _BV( 5 ) , // PH 5 ** 8 ** PWM8 + _BV( 6 ) , // PH 6 ** 9 ** PWM9 + _BV( 4 ) , // PB 4 ** 10 ** PWM10 + _BV( 5 ) , // PB 5 ** 11 ** PWM11 + _BV( 6 ) , // PB 6 ** 12 ** PWM12 + _BV( 7 ) , // PB 7 ** 13 ** PWM13 + _BV( 1 ) , // PJ 1 ** 14 ** USART3_TX + _BV( 0 ) , // PJ 0 ** 15 ** USART3_RX + _BV( 1 ) , // PH 1 ** 16 ** USART2_TX + _BV( 0 ) , // PH 0 ** 17 ** USART2_RX + _BV( 3 ) , // PD 3 ** 18 ** USART1_TX + _BV( 2 ) , // PD 2 ** 19 ** USART1_RX + _BV( 1 ) , // PD 1 ** 20 ** I2C_SDA + _BV( 0 ) , // PD 0 ** 21 ** I2C_SCL + _BV( 0 ) , // PA 0 ** 22 ** D22 + _BV( 1 ) , // PA 1 ** 23 ** D23 + _BV( 2 ) , // PA 2 ** 24 ** D24 + _BV( 3 ) , // PA 3 ** 25 ** D25 + _BV( 4 ) , // PA 4 ** 26 ** D26 + _BV( 5 ) , // PA 5 ** 27 ** D27 + _BV( 6 ) , // PA 6 ** 28 ** D28 + _BV( 7 ) , // PA 7 ** 29 ** D29 + _BV( 7 ) , // PC 7 ** 30 ** D30 + _BV( 6 ) , // PC 6 ** 31 ** D31 + _BV( 5 ) , // PC 5 ** 32 ** D32 + _BV( 4 ) , // PC 4 ** 33 ** D33 + _BV( 3 ) , // PC 3 ** 34 ** D34 + _BV( 2 ) , // PC 2 ** 35 ** D35 + _BV( 1 ) , // PC 1 ** 36 ** D36 + _BV( 0 ) , // PC 0 ** 37 ** D37 + _BV( 7 ) , // PD 7 ** 38 ** D38 + _BV( 2 ) , // PG 2 ** 39 ** D39 + _BV( 1 ) , // PG 1 ** 40 ** D40 + _BV( 0 ) , // PG 0 ** 41 ** D41 + _BV( 7 ) , // PL 7 ** 42 ** D42 + _BV( 6 ) , // PL 6 ** 43 ** D43 + _BV( 5 ) , // PL 5 ** 44 ** D44 + _BV( 4 ) , // PL 4 ** 45 ** D45 + _BV( 3 ) , // PL 3 ** 46 ** D46 + _BV( 2 ) , // PL 2 ** 47 ** D47 + _BV( 1 ) , // PL 1 ** 48 ** D48 + _BV( 0 ) , // PL 0 ** 49 ** D49 + _BV( 3 ) , // PB 3 ** 50 ** SPI_MISO + _BV( 2 ) , // PB 2 ** 51 ** SPI_MOSI + _BV( 1 ) , // PB 1 ** 52 ** SPI_SCK + _BV( 0 ) , // PB 0 ** 53 ** SPI_SS + _BV( 0 ) , // PF 0 ** 54 ** A0 + _BV( 1 ) , // PF 1 ** 55 ** A1 + _BV( 2 ) , // PF 2 ** 56 ** A2 + _BV( 3 ) , // PF 3 ** 57 ** A3 + _BV( 4 ) , // PF 4 ** 58 ** A4 + _BV( 5 ) , // PF 5 ** 59 ** A5 + _BV( 6 ) , // PF 6 ** 60 ** A6 + _BV( 7 ) , // PF 7 ** 61 ** A7 + _BV( 0 ) , // PK 0 ** 62 ** A8 + _BV( 1 ) , // PK 1 ** 63 ** A9 + _BV( 2 ) , // PK 2 ** 64 ** A10 + _BV( 3 ) , // PK 3 ** 65 ** A11 + _BV( 4 ) , // PK 4 ** 66 ** A12 + _BV( 5 ) , // PK 5 ** 67 ** A13 + _BV( 6 ) , // PK 6 ** 68 ** A14 + _BV( 7 ) , // PK 7 ** 69 ** A15 +}; + +const uint8_t PROGMEM digital_pin_to_timer_PGM[] = { + // TIMERS + // ------------------------------------------- + NOT_ON_TIMER , // PE 0 ** 0 ** USART0_RX + NOT_ON_TIMER , // PE 1 ** 1 ** USART0_TX + TIMER3B , // PE 4 ** 2 ** PWM2 + TIMER3C , // PE 5 ** 3 ** PWM3 + TIMER0B , // PG 5 ** 4 ** PWM4 + TIMER3A , // PE 3 ** 5 ** PWM5 + TIMER4A , // PH 3 ** 6 ** PWM6 + TIMER4B , // PH 4 ** 7 ** PWM7 + TIMER4C , // PH 5 ** 8 ** PWM8 + TIMER2B , // PH 6 ** 9 ** PWM9 + TIMER2A , // PB 4 ** 10 ** PWM10 + TIMER1A , // PB 5 ** 11 ** PWM11 + TIMER1B , // PB 6 ** 12 ** PWM12 + TIMER0A , // PB 7 ** 13 ** PWM13 + NOT_ON_TIMER , // PJ 1 ** 14 ** USART3_TX + NOT_ON_TIMER , // PJ 0 ** 15 ** USART3_RX + NOT_ON_TIMER , // PH 1 ** 16 ** USART2_TX + NOT_ON_TIMER , // PH 0 ** 17 ** USART2_RX + NOT_ON_TIMER , // PD 3 ** 18 ** USART1_TX + NOT_ON_TIMER , // PD 2 ** 19 ** USART1_RX + NOT_ON_TIMER , // PD 1 ** 20 ** I2C_SDA + NOT_ON_TIMER , // PD 0 ** 21 ** I2C_SCL + NOT_ON_TIMER , // PA 0 ** 22 ** D22 + NOT_ON_TIMER , // PA 1 ** 23 ** D23 + NOT_ON_TIMER , // PA 2 ** 24 ** D24 + NOT_ON_TIMER , // PA 3 ** 25 ** D25 + NOT_ON_TIMER , // PA 4 ** 26 ** D26 + NOT_ON_TIMER , // PA 5 ** 27 ** D27 + NOT_ON_TIMER , // PA 6 ** 28 ** D28 + NOT_ON_TIMER , // PA 7 ** 29 ** D29 + NOT_ON_TIMER , // PC 7 ** 30 ** D30 + NOT_ON_TIMER , // PC 6 ** 31 ** D31 + NOT_ON_TIMER , // PC 5 ** 32 ** D32 + NOT_ON_TIMER , // PC 4 ** 33 ** D33 + NOT_ON_TIMER , // PC 3 ** 34 ** D34 + NOT_ON_TIMER , // PC 2 ** 35 ** D35 + NOT_ON_TIMER , // PC 1 ** 36 ** D36 + NOT_ON_TIMER , // PC 0 ** 37 ** D37 + NOT_ON_TIMER , // PD 7 ** 38 ** D38 + NOT_ON_TIMER , // PG 2 ** 39 ** D39 + NOT_ON_TIMER , // PG 1 ** 40 ** D40 + NOT_ON_TIMER , // PG 0 ** 41 ** D41 + NOT_ON_TIMER , // PL 7 ** 42 ** D42 + NOT_ON_TIMER , // PL 6 ** 43 ** D43 + TIMER5C , // PL 5 ** 44 ** D44 + TIMER5B , // PL 4 ** 45 ** D45 + TIMER5A , // PL 3 ** 46 ** D46 + NOT_ON_TIMER , // PL 2 ** 47 ** D47 + NOT_ON_TIMER , // PL 1 ** 48 ** D48 + NOT_ON_TIMER , // PL 0 ** 49 ** D49 + NOT_ON_TIMER , // PB 3 ** 50 ** SPI_MISO + NOT_ON_TIMER , // PB 2 ** 51 ** SPI_MOSI + NOT_ON_TIMER , // PB 1 ** 52 ** SPI_SCK + NOT_ON_TIMER , // PB 0 ** 53 ** SPI_SS + NOT_ON_TIMER , // PF 0 ** 54 ** A0 + NOT_ON_TIMER , // PF 1 ** 55 ** A1 + NOT_ON_TIMER , // PF 2 ** 56 ** A2 + NOT_ON_TIMER , // PF 3 ** 57 ** A3 + NOT_ON_TIMER , // PF 4 ** 58 ** A4 + NOT_ON_TIMER , // PF 5 ** 59 ** A5 + NOT_ON_TIMER , // PF 6 ** 60 ** A6 + NOT_ON_TIMER , // PF 7 ** 61 ** A7 + NOT_ON_TIMER , // PK 0 ** 62 ** A8 + NOT_ON_TIMER , // PK 1 ** 63 ** A9 + NOT_ON_TIMER , // PK 2 ** 64 ** A10 + NOT_ON_TIMER , // PK 3 ** 65 ** A11 + NOT_ON_TIMER , // PK 4 ** 66 ** A12 + NOT_ON_TIMER , // PK 5 ** 67 ** A13 + NOT_ON_TIMER , // PK 6 ** 68 ** A14 + NOT_ON_TIMER , // PK 7 ** 69 ** A15 +}; + +#endif + +// These serial port names are intended to allow libraries and architecture-neutral +// sketches to automatically default to the correct port name for a particular type +// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, +// the first hardware serial port whose RX/TX pins are not dedicated to another use. +// +// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor +// +// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial +// +// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library +// +// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. +// +// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX +// pins are NOT connected to anything by default. +#define SERIAL_PORT_MONITOR Serial +#define SERIAL_PORT_HARDWARE Serial +#define SERIAL_PORT_HARDWARE1 Serial1 +#define SERIAL_PORT_HARDWARE2 Serial2 +#define SERIAL_PORT_HARDWARE3 Serial3 +#define SERIAL_PORT_HARDWARE_OPEN Serial1 +#define SERIAL_PORT_HARDWARE_OPEN1 Serial2 +#define SERIAL_PORT_HARDWARE_OPEN2 Serial3 + +#endif diff --git a/hardware/arduino/avr/variants/micro/pins_arduino.h b/hardware/arduino/avr/variants/micro/pins_arduino.h new file mode 100644 index 0000000000000000000000000000000000000000..f83ef1f850b1720069eb04b57d3051bdff4f6554 --- /dev/null +++ b/hardware/arduino/avr/variants/micro/pins_arduino.h @@ -0,0 +1,35 @@ +/* + pins_arduino.h - Pin definition functions for Arduino + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2007 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA +*/ + +#include "../leonardo/pins_arduino.h" + +#undef TXLED0 +#undef TXLED1 +#undef RXLED0 +#undef RXLED1 +#undef TX_RX_LED_INIT + +#define TXLED0 PORTD &= ~(1<<5) +#define TXLED1 PORTD |= (1<<5) +#define RXLED0 PORTB &= ~(1<<0) +#define RXLED1 PORTB |= (1<<0) +#define TX_RX_LED_INIT DDRD |= (1<<5), DDRB |= (1<<0), TXLED0, RXLED0 diff --git a/hardware/arduino/avr/variants/robot_control/pins_arduino.h b/hardware/arduino/avr/variants/robot_control/pins_arduino.h new file mode 100644 index 0000000000000000000000000000000000000000..3e3610351066712f8419ae67b369b2b4b7682488 --- /dev/null +++ b/hardware/arduino/avr/variants/robot_control/pins_arduino.h @@ -0,0 +1,326 @@ +/* + pins_arduino.h - Pin definition functions for Arduino Robot Control Board + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2913 D. Cuartielles, X. Yang (Arduino Verkstad) + Copyright (c) 2012 D. Cuartielles, N. de la Riva, I. Gallego, E. Gallego + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA +*/ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define ARDUINO_MODEL_USB_PID 0x0038 + +#define TX_RX_LED_INIT DDRD |= (1<<5), DDRB |= (1<<0) +#define TXLED0 PORTD |= (1<<5) +#define TXLED1 PORTD &= ~(1<<5) +#define RXLED0 PORTB |= (1<<0) +#define RXLED1 PORTB &= ~(1<<0) + +#define D0 TKD0 +#define D1 TKD1 +#define D2 TKD2 +#define D3 TKD3 +#define D4 TKD4 +#define D5 TKD5 + +#define PIN_SERIAL_RX (0) +#define PIN_SERIAL_TX (1) + +static const uint8_t RX = PIN_SERIAL_RX; +static const uint8_t TX = PIN_SERIAL_TX; + +#define PIN_WIRE_SDA (2) +#define PIN_WIRE_SCL (3) + +static const uint8_t SDA = PIN_WIRE_SDA; +static const uint8_t SCL = PIN_WIRE_SCL; + +// Map SPI port to 'new' pins D14..D17 +#define PIN_SPI_SS (17) +#define PIN_SPI_MOSI (16) +#define PIN_SPI_MISO (14) +#define PIN_SPI_SCK (15) + +static const uint8_t SS = PIN_SPI_SS; +static const uint8_t MOSI = PIN_SPI_MOSI; +static const uint8_t MISO = PIN_SPI_MISO; +static const uint8_t SCK = PIN_SPI_SCK; + +// Mapping of analog pins as digital I/O +// A6-A11 share with digital pins +#define PIN_A0 (18) +#define PIN_A1 (19) +#define PIN_A2 (20) +#define PIN_A3 (21) +#define PIN_A4 (22) +#define PIN_A5 (23) +#define PIN_A6 (24) +#define PIN_A7 (25) +#define PIN_A8 (26) +#define PIN_A9 (27) +#define PIN_A10 (28) +#define PIN_A11 (29) + +static const uint8_t A0 = PIN_A0; +static const uint8_t A1 = PIN_A1; +static const uint8_t A2 = PIN_A2; +static const uint8_t A3 = PIN_A3; +static const uint8_t A4 = PIN_A4; +static const uint8_t A5 = PIN_A5; +static const uint8_t A6 = PIN_A6; // D4 +static const uint8_t A7 = PIN_A7; // D6 +static const uint8_t A8 = PIN_A8; // D8 +static const uint8_t A9 = PIN_A9; // D9 +static const uint8_t A10 = PIN_A10; // D10 +static const uint8_t A11 = PIN_A11; // D12 + +// Specific Mapping for the Control Board +static const uint8_t KEY = 18; // AD0 +static const uint8_t MUX_IN = 24; // ADC8 - A6 +static const uint8_t MUXA = 6; // D5 - TKD4 +static const uint8_t MUXB = 11; // D11 +static const uint8_t MUXC = 12; // D12 - TKD5 +static const uint8_t MUXD = 13; // D13 +static const uint8_t BUZZ = 5; // D5 +static const uint8_t POT = 23; // AD5 +static const uint8_t DC_LCD = 10; // D10 +static const uint8_t LCD_CS = 9; // D9 +static const uint8_t RST_LCD = 7; // D6 +static const uint8_t CARD_CS = 8; // D8 +static const uint8_t TKD0 = 19; // ADC6 - A1 +static const uint8_t TKD1 = 20; // ADC5 - A2 +static const uint8_t TKD2 = 21; // ADC4 - A3 +static const uint8_t TKD3 = 22; // ADC1 - A4 +static const uint8_t TKD4 = 6; // D5 - MUXA +static const uint8_t TKD5 = 12; // D12 - MUXC +static const uint8_t LED1 = 17; // D17 - RX_Led + +// __AVR_ATmega32U4__ has an unusual mapping of pins to channels +extern const uint8_t PROGMEM analog_pin_to_channel_PGM[]; +#define analogPinToChannel(P) ( pgm_read_byte( analog_pin_to_channel_PGM + (P) ) ) + +#define digitalPinToInterrupt(p) ((p) == 0 ? 2 : ((p) == 1 ? 3 : ((p) == 2 ? 1 : ((p) == 3 ? 0 : ((p) == 7 ? 4 : NOT_AN_INTERRUPT))))) + +#ifdef ARDUINO_MAIN + +// On the Arduino board, digital pins are also used +// for the analog output (software PWM). Analog input +// pins are a separate set. + +// ARDUINO LEONARDO / ARDUINO ROBOT CONTROL / ATMEGA 32U4 / FUNCTION / REGISTER +// +// D0 RX PD2 RX RXD1/INT2 +// D1 TX PD3 TX TXD1/INT3 +// D2 SDA PD1 SDA SDA/INT1 +// D3# SCL PD0 PWM8/SCL OC0B/SCL/INT0 +// D4 MUX_IN A6 PD4 ADC8 +// D5# BUZZ PC6 ??? OC3A/#OC4A +// D6# MUXA/TKD4 A7 PD7 FastPWM #OC4D/ADC10 +// D7 RST_LCD PE6 INT6/AIN0 +// +// D8 CARD_CS A8 PB4 ADC11/PCINT4 +// D9# LCD_CS A9 PB5 PWM16 OC1A/#OC4B/ADC12/PCINT5 +// D10# DC_LCD A10 PB6 PWM16 OC1B/0c4B/ADC13/PCINT6 +// D11# MUXB PB7 PWM8/16 0C0A/OC1C/#RTS/PCINT7 +// D12 MUXC/TKD5 A11 PD6 T1/#OC4D/ADC9 +// D13# MUXD PC7 PWM10 CLK0/OC4A +// +// A0 KEY D18 PF7 ADC7 +// A1 TKD0 D19 PF6 ADC6 +// A2 TKD1 D20 PF5 ADC5 +// A3 TKD2 D21 PF4 ADC4 +// A4 TKD3 D22 PF1 ADC1 +// A5 POT D23 PF0 ADC0 +// +// MISO MISO D14 PB3 MISO,PCINT3 +// SCK SCK D15 PB1 SCK,PCINT1 +// MOSI MOSI D16 PB2 MOSI,PCINT2 +// SS RX_LED D17 PB0 RXLED,SS/PCINT0 +// +// TXLED TX_LED PD5 +// HWB PE2 HWB + +// these arrays map port names (e.g. port B) to the +// appropriate addresses for various functions (e.g. reading +// and writing) +const uint16_t PROGMEM port_to_mode_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &DDRB, + (uint16_t) &DDRC, + (uint16_t) &DDRD, + (uint16_t) &DDRE, + (uint16_t) &DDRF, +}; + +const uint16_t PROGMEM port_to_output_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &PORTB, + (uint16_t) &PORTC, + (uint16_t) &PORTD, + (uint16_t) &PORTE, + (uint16_t) &PORTF, +}; + +const uint16_t PROGMEM port_to_input_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &PINB, + (uint16_t) &PINC, + (uint16_t) &PIND, + (uint16_t) &PINE, + (uint16_t) &PINF, +}; + +const uint8_t PROGMEM digital_pin_to_port_PGM[30] = { + PD, // D0 - PD2 + PD, // D1 - PD3 + PD, // D2 - PD1 + PD, // D3 - PD0 + PD, // D4 - PD4 + PC, // D5 - PC6 + PD, // D6 - PD7 + PE, // D7 - PE6 + + PB, // D8 - PB4 + PB, // D9 - PB5 + PB, // D10 - PB6 + PB, // D11 - PB7 + PD, // D12 - PD6 + PC, // D13 - PC7 + + PB, // D14 - MISO - PB3 + PB, // D15 - SCK - PB1 + PB, // D16 - MOSI - PB2 + PB, // D17 - SS - PB0 + + PF, // D18 - A0 - PF7 + PF, // D19 - A1 - PF6 + PF, // D20 - A2 - PF5 + PF, // D21 - A3 - PF4 + PF, // D22 - A4 - PF1 + PF, // D23 - A5 - PF0 + + PD, // D24 / D4 - A6 - PD4 + PD, // D25 / D6 - A7 - PD7 + PB, // D26 / D8 - A8 - PB4 + PB, // D27 / D9 - A9 - PB5 + PB, // D28 / D10 - A10 - PB6 + PD, // D29 / D12 - A11 - PD6 +}; + +const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[30] = { + _BV(2), // D0 - PD2 + _BV(3), // D1 - PD3 + _BV(1), // D2 - PD1 + _BV(0), // D3 - PD0 + _BV(4), // D4 - PD4 + _BV(6), // D5 - PC6 + _BV(7), // D6 - PD7 + _BV(6), // D7 - PE6 + + _BV(4), // D8 - PB4 + _BV(5), // D9 - PB5 + _BV(6), // D10 - PB6 + _BV(7), // D11 - PB7 + _BV(6), // D12 - PD6 + _BV(7), // D13 - PC7 + + _BV(3), // D14 - MISO - PB3 + _BV(1), // D15 - SCK - PB1 + _BV(2), // D16 - MOSI - PB2 + _BV(0), // D17 - SS - PB0 + + _BV(7), // D18 - A0 - PF7 + _BV(6), // D19 - A1 - PF6 + _BV(5), // D20 - A2 - PF5 + _BV(4), // D21 - A3 - PF4 + _BV(1), // D22 - A4 - PF1 + _BV(0), // D23 - A5 - PF0 + + _BV(4), // D24 / D4 - A6 - PD4 + _BV(7), // D25 / D6 - A7 - PD7 + _BV(4), // D26 / D8 - A8 - PB4 + _BV(5), // D27 / D9 - A9 - PB5 + _BV(6), // D28 / D10 - A10 - PB6 + _BV(6), // D29 / D12 - A11 - PD6 +}; + +const uint8_t PROGMEM digital_pin_to_timer_PGM[18] = { + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + TIMER0B, /* 3 */ + NOT_ON_TIMER, + TIMER3A, /* 5 */ + TIMER4D, /* 6 */ + NOT_ON_TIMER, + + NOT_ON_TIMER, + TIMER1A, /* 9 */ + TIMER1B, /* 10 */ + TIMER0A, /* 11 */ + + NOT_ON_TIMER, + TIMER4A, /* 13 */ + + NOT_ON_TIMER, + NOT_ON_TIMER, +}; + +const uint8_t PROGMEM analog_pin_to_channel_PGM[12] = { + 7, // A0 PF7 ADC7 + 6, // A1 PF6 ADC6 + 5, // A2 PF5 ADC5 + 4, // A3 PF4 ADC4 + 1, // A4 PF1 ADC1 + 0, // A5 PF0 ADC0 + 8, // A6 D4 PD4 ADC8 + 10, // A7 D6 PD7 ADC10 + 11, // A8 D8 PB4 ADC11 + 12, // A9 D9 PB5 ADC12 + 13, // A10 D10 PB6 ADC13 + 9 // A11 D12 PD6 ADC9 +}; + +#endif /* ARDUINO_MAIN */ + +// These serial port names are intended to allow libraries and architecture-neutral +// sketches to automatically default to the correct port name for a particular type +// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, +// the first hardware serial port whose RX/TX pins are not dedicated to another use. +// +// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor +// +// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial +// +// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library +// +// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. +// +// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX +// pins are NOT connected to anything by default. +#define SERIAL_PORT_MONITOR Serial +#define SERIAL_PORT_USBVIRTUAL Serial +#define SERIAL_PORT_HARDWARE Serial1 + +#endif /* Pins_Arduino_h */ diff --git a/hardware/arduino/avr/variants/robot_motor/pins_arduino.h b/hardware/arduino/avr/variants/robot_motor/pins_arduino.h new file mode 100644 index 0000000000000000000000000000000000000000..2686b69557c1de5a45f61031b927c01da48fa082 --- /dev/null +++ b/hardware/arduino/avr/variants/robot_motor/pins_arduino.h @@ -0,0 +1,321 @@ +/* + pins_arduino.h - Pin definition functions for Arduino Robot Control Board + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2913 D. Cuartielles, X. Yang (Arduino Verkstad) + Copyright (c) 2012 D. Cuartielles, N. de la Riva, I. Gallego, E. Gallego + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA +*/ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define ARDUINO_MODEL_USB_PID 0x0039 + +#define TX_RX_LED_INIT DDRD |= (1<<5), DDRB |= (1<<0) +#define TXLED0 PORTD |= (1<<5) +#define TXLED1 PORTD &= ~(1<<5) +#define RXLED0 PORTB |= (1<<0) +#define RXLED1 PORTB &= ~(1<<0) + +#define D10 TK1 +#define D9 TK2 +#define D8 TK4 +#define D7 TK3 + +#define PIN_SERIAL_RX (0) +#define PIN_SERIAL_TX (1) + +static const uint8_t RX = PIN_SERIAL_RX; +static const uint8_t TX = PIN_SERIAL_TX; + +#define PIN_WIRE_SDA (2) +#define PIN_WIRE_SCL (3) + +static const uint8_t SDA = PIN_WIRE_SDA; +static const uint8_t SCL = PIN_WIRE_SCL; + +// Map SPI port to 'new' pins D14..D17 +#define PIN_SPI_SS (17) +#define PIN_SPI_MOSI (16) +#define PIN_SPI_MISO (14) +#define PIN_SPI_SCK (15) + +static const uint8_t SS = PIN_SPI_SS; +static const uint8_t MOSI = PIN_SPI_MOSI; +static const uint8_t MISO = PIN_SPI_MISO; +static const uint8_t SCK = PIN_SPI_SCK; + +// Mapping of analog pins as digital I/O +// A6-A11 share with digital pins +#define PIN_A0 (18) +#define PIN_A1 (19) +#define PIN_A2 (20) +#define PIN_A3 (21) +#define PIN_A4 (22) +#define PIN_A5 (23) +#define PIN_A6 (24) +#define PIN_A7 (25) +#define PIN_A8 (26) +#define PIN_A9 (27) +#define PIN_A10 (28) +#define PIN_A11 (29) + +static const uint8_t A0 = PIN_A0; +static const uint8_t A1 = PIN_A1; +static const uint8_t A2 = PIN_A2; +static const uint8_t A3 = PIN_A3; +static const uint8_t A4 = PIN_A4; +static const uint8_t A5 = PIN_A5; +static const uint8_t A6 = PIN_A6; // D4 +static const uint8_t A7 = PIN_A7; // D6 +static const uint8_t A8 = PIN_A8; // D8 +static const uint8_t A9 = PIN_A9; // D9 +static const uint8_t A10 = PIN_A10; // D10 +static const uint8_t A11 = PIN_A11; // D12 + +// Specific Mapping for the Motor Board +static const uint8_t MUX_IN = 20; // A2 +static const uint8_t MUXA = 7; // D7 +static const uint8_t MUXB = 8; // D8 +static const uint8_t MUXC = 11; // D11 +static const uint8_t MUXI = 13; // D13 +static const uint8_t TRIM = 21; // A3 +static const uint8_t SENSE_A = 22; // A4 +static const uint8_t SENSE_B = 23; // A5 +static const uint8_t IN_A1 = 6; // D6 - A7 +static const uint8_t IN_A2 = 5; // D5 +static const uint8_t IN_B1 = 10; // D10 +static const uint8_t IN_B2 = 9; // D9 +static const uint8_t TK1 = 18; // A0 +static const uint8_t TK2 = 19; // A1 +static const uint8_t TK3 = 4; // A6 +static const uint8_t TK4 = 12; // A11 + +// __AVR_ATmega32U4__ has an unusual mapping of pins to channels +extern const uint8_t PROGMEM analog_pin_to_channel_PGM[]; +#define analogPinToChannel(P) ( pgm_read_byte( analog_pin_to_channel_PGM + (P) ) ) + +#define digitalPinToInterrupt(p) ((p) == 0 ? 2 : ((p) == 1 ? 3 : ((p) == 2 ? 1 : ((p) == 3 ? 0 : ((p) == 7 ? 4 : NOT_AN_INTERRUPT))))) + +#ifdef ARDUINO_MAIN + +// On the Arduino board, digital pins are also used +// for the analog output (software PWM). Analog input +// pins are a separate set. + +// ARDUINO LEONARDO / ARDUINO ROBOT CONTROL / ATMEGA 32U4 / FUNCTION / REGISTER +// +// D0 RX PD2 RX RXD1/INT2 +// D1 TX PD3 TX TXD1/INT3 +// D2 SDA PD1 SDA SDA/INT1 +// D3# SCL PD0 PWM8/SCL OC0B/SCL/INT0 +// D4 TK3 A6 PD4 ADC8 +// D5# INA2 PC6 ??? OC3A/#OC4A +// D6# INA1 A7 PD7 FastPWM #OC4D/ADC10 +// D7 MUXA PE6 INT6/AIN0 +// +// D8 MUXB A8 PB4 ADC11/PCINT4 +// D9# INB2 A9 PB5 PWM16 OC1A/#OC4B/ADC12/PCINT5 +// D10# INB1 A10 PB6 PWM16 OC1B/0c4B/ADC13/PCINT6 +// D11# MUXC PB7 PWM8/16 0C0A/OC1C/#RTS/PCINT7 +// D12 TK4 A11 PD6 T1/#OC4D/ADC9 +// D13# MUXI PC7 PWM10 CLK0/OC4A +// +// A0 TK1 D18 PF7 ADC7 +// A1 TK2 D19 PF6 ADC6 +// A2 MUX_IN D20 PF5 ADC5 +// A3 TRIM D21 PF4 ADC4 +// A4 SENSE_A D22 PF1 ADC1 +// A5 SENSE_B D23 PF0 ADC0 +// +// MISO MISO D14 PB3 MISO,PCINT3 +// SCK SCK D15 PB1 SCK,PCINT1 +// MOSI MOSI D16 PB2 MOSI,PCINT2 +// SS RX_LED D17 PB0 RXLED,SS/PCINT0 +// +// TXLED TX_LED PD5 +// HWB PE2 HWB + +// these arrays map port names (e.g. port B) to the +// appropriate addresses for various functions (e.g. reading +// and writing) +const uint16_t PROGMEM port_to_mode_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &DDRB, + (uint16_t) &DDRC, + (uint16_t) &DDRD, + (uint16_t) &DDRE, + (uint16_t) &DDRF, +}; + +const uint16_t PROGMEM port_to_output_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &PORTB, + (uint16_t) &PORTC, + (uint16_t) &PORTD, + (uint16_t) &PORTE, + (uint16_t) &PORTF, +}; + +const uint16_t PROGMEM port_to_input_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &PINB, + (uint16_t) &PINC, + (uint16_t) &PIND, + (uint16_t) &PINE, + (uint16_t) &PINF, +}; + +const uint8_t PROGMEM digital_pin_to_port_PGM[30] = { + PD, // D0 - PD2 + PD, // D1 - PD3 + PD, // D2 - PD1 + PD, // D3 - PD0 + PD, // D4 - PD4 + PC, // D5 - PC6 + PD, // D6 - PD7 + PE, // D7 - PE6 + + PB, // D8 - PB4 + PB, // D9 - PB5 + PB, // D10 - PB6 + PB, // D11 - PB7 + PD, // D12 - PD6 + PC, // D13 - PC7 + + PB, // D14 - MISO - PB3 + PB, // D15 - SCK - PB1 + PB, // D16 - MOSI - PB2 + PB, // D17 - SS - PB0 + + PF, // D18 - A0 - PF7 + PF, // D19 - A1 - PF6 + PF, // D20 - A2 - PF5 + PF, // D21 - A3 - PF4 + PF, // D22 - A4 - PF1 + PF, // D23 - A5 - PF0 + + PD, // D24 / D4 - A6 - PD4 + PD, // D25 / D6 - A7 - PD7 + PB, // D26 / D8 - A8 - PB4 + PB, // D27 / D9 - A9 - PB5 + PB, // D28 / D10 - A10 - PB6 + PD, // D29 / D12 - A11 - PD6 +}; + +const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[30] = { + _BV(2), // D0 - PD2 + _BV(3), // D1 - PD3 + _BV(1), // D2 - PD1 + _BV(0), // D3 - PD0 + _BV(4), // D4 - PD4 + _BV(6), // D5 - PC6 + _BV(7), // D6 - PD7 + _BV(6), // D7 - PE6 + + _BV(4), // D8 - PB4 + _BV(5), // D9 - PB5 + _BV(6), // D10 - PB6 + _BV(7), // D11 - PB7 + _BV(6), // D12 - PD6 + _BV(7), // D13 - PC7 + + _BV(3), // D14 - MISO - PB3 + _BV(1), // D15 - SCK - PB1 + _BV(2), // D16 - MOSI - PB2 + _BV(0), // D17 - SS - PB0 + + _BV(7), // D18 - A0 - PF7 + _BV(6), // D19 - A1 - PF6 + _BV(5), // D20 - A2 - PF5 + _BV(4), // D21 - A3 - PF4 + _BV(1), // D22 - A4 - PF1 + _BV(0), // D23 - A5 - PF0 + + _BV(4), // D24 / D4 - A6 - PD4 + _BV(7), // D25 / D6 - A7 - PD7 + _BV(4), // D26 / D8 - A8 - PB4 + _BV(5), // D27 / D9 - A9 - PB5 + _BV(6), // D28 / D10 - A10 - PB6 + _BV(6), // D29 / D12 - A11 - PD6 +}; + +const uint8_t PROGMEM digital_pin_to_timer_PGM[18] = { + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + TIMER0B, /* 3 */ + NOT_ON_TIMER, + TIMER3A, /* 5 */ + TIMER4D, /* 6 */ + NOT_ON_TIMER, + + NOT_ON_TIMER, + TIMER1A, /* 9 */ + TIMER1B, /* 10 */ + TIMER0A, /* 11 */ + + NOT_ON_TIMER, + TIMER4A, /* 13 */ + + NOT_ON_TIMER, + NOT_ON_TIMER, +}; + +const uint8_t PROGMEM analog_pin_to_channel_PGM[12] = { + 7, // A0 PF7 ADC7 + 6, // A1 PF6 ADC6 + 5, // A2 PF5 ADC5 + 4, // A3 PF4 ADC4 + 1, // A4 PF1 ADC1 + 0, // A5 PF0 ADC0 + 8, // A6 D4 PD4 ADC8 + 10, // A7 D6 PD7 ADC10 + 11, // A8 D8 PB4 ADC11 + 12, // A9 D9 PB5 ADC12 + 13, // A10 D10 PB6 ADC13 + 9 // A11 D12 PD6 ADC9 +}; + +#endif /* ARDUINO_MAIN */ + +// These serial port names are intended to allow libraries and architecture-neutral +// sketches to automatically default to the correct port name for a particular type +// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, +// the first hardware serial port whose RX/TX pins are not dedicated to another use. +// +// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor +// +// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial +// +// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library +// +// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. +// +// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX +// pins are NOT connected to anything by default. +#define SERIAL_PORT_MONITOR Serial +#define SERIAL_PORT_USBVIRTUAL Serial +#define SERIAL_PORT_HARDWARE Serial1 + +#endif /* Pins_Arduino_h */ diff --git a/hardware/arduino/avr/variants/standard/pins_arduino.h b/hardware/arduino/avr/variants/standard/pins_arduino.h new file mode 100644 index 0000000000000000000000000000000000000000..2ea019054350e7137829bcaeba4118c20429dfd8 --- /dev/null +++ b/hardware/arduino/avr/variants/standard/pins_arduino.h @@ -0,0 +1,254 @@ +/* + pins_arduino.h - Pin definition functions for Arduino + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2007 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA +*/ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define NUM_DIGITAL_PINS 20 +#define NUM_ANALOG_INPUTS 6 +#define analogInputToDigitalPin(p) ((p < 6) ? (p) + 14 : -1) + +#if defined(__AVR_ATmega8__) +#define digitalPinHasPWM(p) ((p) == 9 || (p) == 10 || (p) == 11) +#else +#define digitalPinHasPWM(p) ((p) == 3 || (p) == 5 || (p) == 6 || (p) == 9 || (p) == 10 || (p) == 11) +#endif + +#define PIN_SPI_SS (10) +#define PIN_SPI_MOSI (11) +#define PIN_SPI_MISO (12) +#define PIN_SPI_SCK (13) + +static const uint8_t SS = PIN_SPI_SS; +static const uint8_t MOSI = PIN_SPI_MOSI; +static const uint8_t MISO = PIN_SPI_MISO; +static const uint8_t SCK = PIN_SPI_SCK; + +#define PIN_WIRE_SDA (18) +#define PIN_WIRE_SCL (19) + +static const uint8_t SDA = PIN_WIRE_SDA; +static const uint8_t SCL = PIN_WIRE_SCL; + +#define LED_BUILTIN 13 + +#define PIN_A0 (14) +#define PIN_A1 (15) +#define PIN_A2 (16) +#define PIN_A3 (17) +#define PIN_A4 (18) +#define PIN_A5 (19) +#define PIN_A6 (20) +#define PIN_A7 (21) + +static const uint8_t A0 = PIN_A0; +static const uint8_t A1 = PIN_A1; +static const uint8_t A2 = PIN_A2; +static const uint8_t A3 = PIN_A3; +static const uint8_t A4 = PIN_A4; +static const uint8_t A5 = PIN_A5; +static const uint8_t A6 = PIN_A6; +static const uint8_t A7 = PIN_A7; + +#define digitalPinToPCICR(p) (((p) >= 0 && (p) <= 21) ? (&PCICR) : ((uint8_t *)0)) +#define digitalPinToPCICRbit(p) (((p) <= 7) ? 2 : (((p) <= 13) ? 0 : 1)) +#define digitalPinToPCMSK(p) (((p) <= 7) ? (&PCMSK2) : (((p) <= 13) ? (&PCMSK0) : (((p) <= 21) ? (&PCMSK1) : ((uint8_t *)0)))) +#define digitalPinToPCMSKbit(p) (((p) <= 7) ? (p) : (((p) <= 13) ? ((p) - 8) : ((p) - 14))) + +#define digitalPinToInterrupt(p) ((p) == 2 ? 0 : ((p) == 3 ? 1 : NOT_AN_INTERRUPT)) + +#ifdef ARDUINO_MAIN + +// On the Arduino board, digital pins are also used +// for the analog output (software PWM). Analog input +// pins are a separate set. + +// ATMEL ATMEGA8 & 168 / ARDUINO +// +// +-\/-+ +// PC6 1| |28 PC5 (AI 5) +// (D 0) PD0 2| |27 PC4 (AI 4) +// (D 1) PD1 3| |26 PC3 (AI 3) +// (D 2) PD2 4| |25 PC2 (AI 2) +// PWM+ (D 3) PD3 5| |24 PC1 (AI 1) +// (D 4) PD4 6| |23 PC0 (AI 0) +// VCC 7| |22 GND +// GND 8| |21 AREF +// PB6 9| |20 AVCC +// PB7 10| |19 PB5 (D 13) +// PWM+ (D 5) PD5 11| |18 PB4 (D 12) +// PWM+ (D 6) PD6 12| |17 PB3 (D 11) PWM +// (D 7) PD7 13| |16 PB2 (D 10) PWM +// (D 8) PB0 14| |15 PB1 (D 9) PWM +// +----+ +// +// (PWM+ indicates the additional PWM pins on the ATmega168.) + +// ATMEL ATMEGA1280 / ARDUINO +// +// 0-7 PE0-PE7 works +// 8-13 PB0-PB5 works +// 14-21 PA0-PA7 works +// 22-29 PH0-PH7 works +// 30-35 PG5-PG0 works +// 36-43 PC7-PC0 works +// 44-51 PJ7-PJ0 works +// 52-59 PL7-PL0 works +// 60-67 PD7-PD0 works +// A0-A7 PF0-PF7 +// A8-A15 PK0-PK7 + + +// these arrays map port names (e.g. port B) to the +// appropriate addresses for various functions (e.g. reading +// and writing) +const uint16_t PROGMEM port_to_mode_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &DDRB, + (uint16_t) &DDRC, + (uint16_t) &DDRD, +}; + +const uint16_t PROGMEM port_to_output_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &PORTB, + (uint16_t) &PORTC, + (uint16_t) &PORTD, +}; + +const uint16_t PROGMEM port_to_input_PGM[] = { + NOT_A_PORT, + NOT_A_PORT, + (uint16_t) &PINB, + (uint16_t) &PINC, + (uint16_t) &PIND, +}; + +const uint8_t PROGMEM digital_pin_to_port_PGM[] = { + PD, /* 0 */ + PD, + PD, + PD, + PD, + PD, + PD, + PD, + PB, /* 8 */ + PB, + PB, + PB, + PB, + PB, + PC, /* 14 */ + PC, + PC, + PC, + PC, + PC, +}; + +const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[] = { + _BV(0), /* 0, port D */ + _BV(1), + _BV(2), + _BV(3), + _BV(4), + _BV(5), + _BV(6), + _BV(7), + _BV(0), /* 8, port B */ + _BV(1), + _BV(2), + _BV(3), + _BV(4), + _BV(5), + _BV(0), /* 14, port C */ + _BV(1), + _BV(2), + _BV(3), + _BV(4), + _BV(5), +}; + +const uint8_t PROGMEM digital_pin_to_timer_PGM[] = { + NOT_ON_TIMER, /* 0 - port D */ + NOT_ON_TIMER, + NOT_ON_TIMER, + // on the ATmega168, digital pin 3 has hardware pwm +#if defined(__AVR_ATmega8__) + NOT_ON_TIMER, +#else + TIMER2B, +#endif + NOT_ON_TIMER, + // on the ATmega168, digital pins 5 and 6 have hardware pwm +#if defined(__AVR_ATmega8__) + NOT_ON_TIMER, + NOT_ON_TIMER, +#else + TIMER0B, + TIMER0A, +#endif + NOT_ON_TIMER, + NOT_ON_TIMER, /* 8 - port B */ + TIMER1A, + TIMER1B, +#if defined(__AVR_ATmega8__) + TIMER2, +#else + TIMER2A, +#endif + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, /* 14 - port C */ + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, +}; + +#endif + +// These serial port names are intended to allow libraries and architecture-neutral +// sketches to automatically default to the correct port name for a particular type +// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, +// the first hardware serial port whose RX/TX pins are not dedicated to another use. +// +// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor +// +// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial +// +// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library +// +// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. +// +// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX +// pins are NOT connected to anything by default. +#define SERIAL_PORT_MONITOR Serial +#define SERIAL_PORT_HARDWARE Serial + +#endif diff --git a/hardware/arduino/avr/variants/yun/pins_arduino.h b/hardware/arduino/avr/variants/yun/pins_arduino.h new file mode 100644 index 0000000000000000000000000000000000000000..7fabb7fac33b485a5e299e4ec0e2c42b158280ef --- /dev/null +++ b/hardware/arduino/avr/variants/yun/pins_arduino.h @@ -0,0 +1,44 @@ +/* + pins_arduino.h - Pin definition functions for Arduino + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2013 Arduino LLC + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA +*/ + +#include "../leonardo/pins_arduino.h" + +// These serial port names are intended to allow libraries and architecture-neutral +// sketches to automatically default to the correct port name for a particular type +// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, +// the first hardware serial port whose RX/TX pins are not dedicated to another use. +// +// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor +// +// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial +// +// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library +// +// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. +// +// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX +// pins are NOT connected to anything by default. +#define SERIAL_PORT_LINUXBRIDGE Serial1 + +// defined in the Leonardo variant +#undef SERIAL_PORT_HARDWARE_OPEN + diff --git a/hardware/package_index_bundled.json b/hardware/package_index_bundled.json new file mode 100644 index 0000000000000000000000000000000000000000..a7b29bf3787aec51c775f79a6790e2afcc718ada --- /dev/null +++ b/hardware/package_index_bundled.json @@ -0,0 +1,219 @@ +{ + "packages": [ + { + "name": "arduino", + "maintainer": "Arduino", + "websiteURL": "http://www.arduino.cc/", + "email": "packages@arduino.cc", + "help": { + "online": "http://www.arduino.cc/en/Reference/HomePage" + }, + "platforms": [ + { + "name": "Arduino AVR Boards", + "architecture": "avr", + "version": "1.8.3", + "category": "Arduino", + "help": { + "online": "http://www.arduino.cc/en/Reference/HomePage" + }, + "url": "http://downloads.arduino.cc/cores/avr-1.8.3.tar.bz2", + "archiveFileName": "avr-1.8.3.tar.bz2", + "checksum": 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+old.2.tools.avrdude.config.path={runtime.ide.path}/hardware/tools/avr/etc/avrdude.conf +new.2.tools.avrdude.config.path={path}/etc/avrdude.conf + +old.3.compiler.path={runtime.ide.path}/hardware/tools/gcc-arm-none-eabi-4.8.3-2014q1/bin/ +new.3.compiler.path={runtime.tools.arm-none-eabi-gcc.path}/bin/ + +old.4.tools.bossac.path={runtime.ide.path}/hardware/tools +new.4.tools.bossac.path={runtime.tools.bossac.path} + +old.5.recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} -mcpu={build.mcu} "-T{build.variant.path}/{build.ldscript}" "-Wl,-Map,{build.path}/{build.project_name}.map" {compiler.c.elf.extra_flags} -o "{build.path}/{build.project_name}.elf" "-L{build.path}" -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols -Wl,--start-group "{build.path}/syscalls_sam3.c.o" {object_files} "{build.variant.path}/{build.variant_system_lib}" "{build.path}/{archive_file}" -Wl,--end-group -lm -gcc +new.5.recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} -mcpu={build.mcu} "-T{build.variant.path}/{build.ldscript}" "-Wl,-Map,{build.path}/{build.project_name}.map" {compiler.c.elf.extra_flags} -o "{build.path}/{build.project_name}.elf" "-L{build.path}" -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols -Wl,--start-group "{build.path}/core/syscalls_sam3.c.o" {object_files} "{build.variant.path}/{build.variant_system_lib}" "{build.path}/{archive_file}" -Wl,--end-group -lm -gcc + +#specific to RedBearLab nRF51822 Boards +old.6.recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" -mcpu={build.mcu} -mthumb -Wl,--gc-sections --specs=nano.specs -Wl,--wrap,main -Wl,-Map={build.path}/{build.project_name}.map,--cref "-T{build.variant.path}/{build.ldscript}" -o "{build.path}/{build.project_name}.elf" -Wl,--start-group "{build.path}/system_nrf51.c.o" {object_files} "{build.path}/startup_NRF51822.s.o" "{build.path}/{archive_file}" -Wl,--end-group -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys +new.6.recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" -mcpu={build.mcu} -mthumb -Wl,--gc-sections --specs=nano.specs -Wl,--wrap,main -Wl,-Map={build.path}/{build.project_name}.map,--cref "-T{build.variant.path}/{build.ldscript}" -o "{build.path}/{build.project_name}.elf" -Wl,--start-group "{build.path}/core/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.c.o" {object_files} "{build.path}/core/startup_NRF51822.S.o" "{build.path}/{archive_file}" -Wl,--end-group -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys + +#specific to RFduino 1.6.3 +old.7.recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} -mcpu={build.mcu} {build.extra_flags} "-T{build.variant.path}/{build.ldscript}" "-Wl,-Map,{build.path}/{build.project_name}.map" -Wl,--cref -o "{build.path}/{build.project_name}.elf" "-L{build.path}" -Wl,--warn-common -Wl,--warn-section-align -Wl,--start-group "{build.path}/syscalls.c.o" {object_files} "{build.variant.path}/{build.variant_system_lib}" "{build.variant.path}/libRFduino.a" "{build.variant.path}/libRFduinoBLE.a" "{build.variant.path}/libRFduinoGZLL.a" "{build.path}/{archive_file}" -Wl,--end-group +new.7.recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} -mcpu={build.mcu} {build.extra_flags} "-T{build.variant.path}/{build.ldscript}" "-Wl,-Map,{build.path}/{build.project_name}.map" -Wl,--cref -o "{build.path}/{build.project_name}.elf" "-L{build.path}" -Wl,--warn-common -Wl,--warn-section-align -Wl,--start-group "{build.path}/core/syscalls.c.o" {object_files} "{build.variant.path}/{build.variant_system_lib}" "{build.variant.path}/libRFduino.a" "{build.variant.path}/libRFduinoBLE.a" "{build.variant.path}/libRFduinoGZLL.a" "{build.path}/{archive_file}" -Wl,--end-group + +old.8.recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{build.path}/{archive_file}" "{object_file}" +new.8.recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}" + +old.9.recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} -mcpu={build.mcu} "-T{build.variant.path}/{build.ldscript}" "-Wl,-Map,{build.path}/{build.project_name}.map" {compiler.c.elf.extra_flags} -o "{build.path}/{build.project_name}.elf" "-L{build.path}" -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--start-group "{build.path}/syscalls_sam3.c.o" {object_files} "{build.variant.path}/{build.variant_system_lib}" "{build.path}/{archive_file}" -Wl,--end-group -lm -gcc +new.9.recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} -mcpu={build.mcu} "-T{build.variant.path}/{build.ldscript}" "-Wl,-Map,{build.path}/{build.project_name}.map" {compiler.c.elf.extra_flags} -o "{build.path}/{build.project_name}.elf" "-L{build.path}" -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--start-group "{build.path}/core/syscalls_sam3.c.o" {object_files} "{build.variant.path}/{build.variant_system_lib}" "{build.path}/{archive_file}" -Wl,--end-group -lm -gcc + +#specific to Digistump AVR Boards 1.5.4 +old.10.recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} "{build.path}/{archive_file}" "{object_file}" +new.10.recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} "{archive_file_path}" "{object_file}" + +old.11.recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} -mmcu={build.mcu} -o "{build.path}/{build.project_name}.elf" {object_files} "{build.path}/{archive_file}" "-L{build.path}" -lm +new.11.recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} -mmcu={build.mcu} -o "{build.path}/{build.project_name}.elf" {object_files} "{archive_file_path}" "-L{build.path}" -lm + +#generic again +old.12.recipe.preproc.macros="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} {preproc.macros.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} "{source_file}" +new.12.recipe.preproc.macros="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} {preproc.macros.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{preprocessed_file_path}" \ No newline at end of file diff --git a/hardware/tools/avr/avr/bin/ar.exe b/hardware/tools/avr/avr/bin/ar.exe new file mode 100644 index 0000000000000000000000000000000000000000..4d647613d0e828fa6acaf6db6302d2d0349eb263 --- /dev/null +++ b/hardware/tools/avr/avr/bin/ar.exe @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:81b1ddffc28e7d8d34ae0cb5cbe92ec9bae1ae852b2f498fb0a40e169ae7c0d2 +size 630784 diff --git a/hardware/tools/avr/avr/bin/as.exe b/hardware/tools/avr/avr/bin/as.exe new file mode 100644 index 0000000000000000000000000000000000000000..82e918b57349f8f18f7c15d591bcdac94cfb5c10 --- /dev/null +++ b/hardware/tools/avr/avr/bin/as.exe @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f4742917d141a23f4863086e6c0a3803b4da3c444cf1935303165b6f7e7e754e +size 815104 diff --git a/hardware/tools/avr/avr/bin/ld.exe b/hardware/tools/avr/avr/bin/ld.exe new file mode 100644 index 0000000000000000000000000000000000000000..92d69ee9b40bee369850ce5cfe7a2835f06df851 --- /dev/null +++ b/hardware/tools/avr/avr/bin/ld.exe @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b8aa2ff51061ff713976e6db14e9adb492436e5b463679a8b9e718c8ff0f2bdf +size 1103360 diff --git a/hardware/tools/avr/avr/bin/libiconv-2.dll b/hardware/tools/avr/avr/bin/libiconv-2.dll new file mode 100644 index 0000000000000000000000000000000000000000..829ed7605d294201d372c3ead2774011ffd54395 --- /dev/null +++ b/hardware/tools/avr/avr/bin/libiconv-2.dll @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:cb016e794d3311c71f21d87803e10a0e1133995f62a485eb37b321cd9b9e1087 +size 978432 diff --git a/hardware/tools/avr/avr/bin/libwinpthread-1.dll b/hardware/tools/avr/avr/bin/libwinpthread-1.dll new file mode 100644 index 0000000000000000000000000000000000000000..10e567029cc38fec7ec022bacee151369cd03fde Binary files /dev/null and b/hardware/tools/avr/avr/bin/libwinpthread-1.dll differ diff --git a/hardware/tools/avr/avr/bin/nm.exe b/hardware/tools/avr/avr/bin/nm.exe new file mode 100644 index 0000000000000000000000000000000000000000..c48a5a929edd1024470fd8a2f6f1e043b82a0822 --- /dev/null +++ b/hardware/tools/avr/avr/bin/nm.exe @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:4cf4392a0c0c44144668a1d8b70144708e32fa74b6279bab4e3041cb5345b593 +size 617472 diff --git a/hardware/tools/avr/avr/bin/objcopy.exe b/hardware/tools/avr/avr/bin/objcopy.exe new file mode 100644 index 0000000000000000000000000000000000000000..9aa22434df891c02028890cacbbea4bb738743cb --- /dev/null +++ b/hardware/tools/avr/avr/bin/objcopy.exe @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:5bc07336d3dc78ef13a36db73b66ca206447fc9a40035ba8f481901084f737d5 +size 766976 diff --git a/hardware/tools/avr/avr/bin/objdump.exe b/hardware/tools/avr/avr/bin/objdump.exe new file mode 100644 index 0000000000000000000000000000000000000000..e6ae6fcecd5d8353b215c4bebcc69532f0be6427 --- /dev/null +++ b/hardware/tools/avr/avr/bin/objdump.exe @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:6379ac8e391b100febd0be4f30461e0148cbd59435aa574c1e96ece55eac3726 +size 888832 diff --git a/hardware/tools/avr/avr/bin/ranlib.exe b/hardware/tools/avr/avr/bin/ranlib.exe new file mode 100644 index 0000000000000000000000000000000000000000..c5a99f9519bff0877ef892cc1d4d3bea7802f0b7 --- /dev/null +++ b/hardware/tools/avr/avr/bin/ranlib.exe @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b7499e3b55c6f7916e66f6f32d38ca45d788c185e1209a63f57c532a921900d2 +size 630784 diff --git a/hardware/tools/avr/avr/bin/readelf.exe b/hardware/tools/avr/avr/bin/readelf.exe new file mode 100644 index 0000000000000000000000000000000000000000..c3dd7c6ac94fd2a9dd1785f6bb071fe22754f120 --- /dev/null +++ b/hardware/tools/avr/avr/bin/readelf.exe @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:2adf1e28b9d91cbcc34ea762de24920c074ed4f8e244869342fca20274ee24d3 +size 456192 diff --git a/hardware/tools/avr/avr/bin/strip.exe b/hardware/tools/avr/avr/bin/strip.exe new file mode 100644 index 0000000000000000000000000000000000000000..b80519a9ffaedfd0cd121b2ef1e4b5aa0897c7c9 --- /dev/null +++ b/hardware/tools/avr/avr/bin/strip.exe @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:d5b92846612697cb8f0ec4286093cea0de3051bc2462c4dc0f30eadf166de79a +size 767488 diff --git a/hardware/tools/avr/avr/include/alloca.h b/hardware/tools/avr/avr/include/alloca.h new file mode 100644 index 0000000000000000000000000000000000000000..a213c0c2a1db699f67d06bdef278bfacec69968e --- /dev/null +++ b/hardware/tools/avr/avr/include/alloca.h @@ -0,0 +1,59 @@ +/* Copyright (c) 2007, Dmitry Xmelkov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef _ALLOCA_H +#define _ALLOCA_H 1 + +#include + +/** \defgroup alloca : Allocate space in the stack */ + +/** \ingroup alloca + \brief Allocate \a __size bytes of space in the stack frame of the caller. + + This temporary space is automatically freed when the function that + called alloca() returns to its caller. Avr-libc defines the alloca() as + a macro, which is translated into the inlined \c __builtin_alloca() + function. The fact that the code is inlined, means that it is impossible + to take the address of this function, or to change its behaviour by + linking with a different library. + + \return alloca() returns a pointer to the beginning of the allocated + space. If the allocation causes stack overflow, program behaviour is + undefined. + + \warning Avoid use alloca() inside the list of arguments of a function + call. + */ +extern void *alloca (size_t __size); + +#define alloca(size) __builtin_alloca (size) + +#endif /* alloca.h */ diff --git a/hardware/tools/avr/avr/include/assert.h b/hardware/tools/avr/avr/include/assert.h new file mode 100644 index 0000000000000000000000000000000000000000..9ae1cc6c1413d05076a7d44d76bd5efd0ae9e8b1 --- /dev/null +++ b/hardware/tools/avr/avr/include/assert.h @@ -0,0 +1,120 @@ +/* Copyright (c) 2005,2007 Joerg Wunsch + All rights reserved. + + Portions of documentation Copyright (c) 1991, 1993 + The Regents of the University of California. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + + $Id$ +*/ + +/** \file */ +/** \defgroup avr_assert : Diagnostics + \code #include \endcode + + This header file defines a debugging aid. + + As there is no standard error output stream available for many + applications using this library, the generation of a printable + error message is not enabled by default. These messages will + only be generated if the application defines the macro + + \code __ASSERT_USE_STDERR \endcode + + before including the \c header file. By default, + only abort() will be called to halt the application. +*/ + +/*@{*/ + +/* + * The ability to include this file (with or without NDEBUG) is a + * feature. + */ + +#undef assert + +#include + +#if defined(__DOXYGEN__) +/** + * \def assert + * \param expression Expression to test for. + * + * The assert() macro tests the given expression and if it is false, + * the calling process is terminated. A diagnostic message is written + * to stderr and the function abort() is called, effectively + * terminating the program. + * + * If expression is true, the assert() macro does nothing. + * + * The assert() macro may be removed at compile time by defining + * NDEBUG as a macro (e.g., by using the compiler option -DNDEBUG). + */ +# define assert(expression) + +#else /* !DOXYGEN */ + +# if defined(NDEBUG) +# define assert(e) ((void)0) +# else /* !NDEBUG */ +# if defined(__ASSERT_USE_STDERR) +# define assert(e) ((e) ? (void)0 : \ + __assert(__func__, __FILE__, __LINE__, #e)) +# else /* !__ASSERT_USE_STDERR */ +# define assert(e) ((e) ? (void)0 : abort()) +# endif /* __ASSERT_USE_STDERR */ +# endif /* NDEBUG */ +#endif /* DOXYGEN */ + +#if (defined __STDC_VERSION__ && __STDC_VERSION__ >= 201112L) || \ + ((_GNUC_ > 4 || (_GNUC_ == 4 && _GNUC_MINOR_ >= 6)) && !defined __cplusplus) +# undef static_assert +# define static_assert _Static_assert +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(__DOXYGEN__) + +extern void __assert(const char *__func, const char *__file, + int __lineno, const char *__sexp); + +#endif /* not __DOXYGEN__ */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ +/* EOF */ diff --git a/hardware/tools/avr/avr/include/avr/boot.h b/hardware/tools/avr/avr/include/avr/boot.h new file mode 100644 index 0000000000000000000000000000000000000000..eed57291769c1ffb132b801ccb4f072b65d765ed --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/boot.h @@ -0,0 +1,684 @@ +/* Copyright (c) 2002,2003,2004,2005,2006,2007,2008,2009 Eric B. Weddington + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef _AVR_BOOT_H_ +#define _AVR_BOOT_H_ 1 + +/** \file */ +/** \defgroup avr_boot : Bootloader Support Utilities + \code + #include + #include + \endcode + + The macros in this module provide a C language interface to the + bootloader support functionality of certain AVR processors. These + macros are designed to work with all sizes of flash memory. + + Global interrupts are not automatically disabled for these macros. It + is left up to the programmer to do this. See the code example below. + Also see the processor datasheet for caveats on having global interrupts + enabled during writing of the Flash. + + \note Not all AVR processors provide bootloader support. See your + processor datasheet to see if it provides bootloader support. + + \todo From email with Marek: On smaller devices (all except ATmega64/128), + __SPM_REG is in the I/O space, accessible with the shorter "in" and "out" + instructions - since the boot loader has a limited size, this could be an + important optimization. + + \par API Usage Example + The following code shows typical usage of the boot API. + + \code + #include + #include + #include + + void boot_program_page (uint32_t page, uint8_t *buf) + { + uint16_t i; + uint8_t sreg; + + // Disable interrupts. + + sreg = SREG; + cli(); + + eeprom_busy_wait (); + + boot_page_erase (page); + boot_spm_busy_wait (); // Wait until the memory is erased. + + for (i=0; i +#include +#include +#include + +/* Check for SPM Control Register in processor. */ +#if defined (SPMCSR) +# define __SPM_REG SPMCSR +#else +# if defined (SPMCR) +# define __SPM_REG SPMCR +# else +# error AVR processor does not provide bootloader support! +# endif +#endif + + +/* Check for SPM Enable bit. */ +#if defined(SPMEN) +# define __SPM_ENABLE SPMEN +#elif defined(SELFPRGEN) +# define __SPM_ENABLE SELFPRGEN +#else +# error Cannot find SPM Enable bit definition! +#endif + +/** \ingroup avr_boot + \def BOOTLOADER_SECTION + + Used to declare a function or variable to be placed into a + new section called .bootloader. This section and its contents + can then be relocated to any address (such as the bootloader + NRWW area) at link-time. */ + +#define BOOTLOADER_SECTION __attribute__ ((section (".bootloader"))) + +#ifndef __DOXYGEN__ +/* Create common bit definitions. */ +#ifdef ASB +#define __COMMON_ASB ASB +#else +#define __COMMON_ASB RWWSB +#endif + +#ifdef ASRE +#define __COMMON_ASRE ASRE +#else +#define __COMMON_ASRE RWWSRE +#endif + +/* Define the bit positions of the Boot Lock Bits. */ + +#define BLB12 5 +#define BLB11 4 +#define BLB02 3 +#define BLB01 2 +#endif /* __DOXYGEN__ */ + +/** \ingroup avr_boot + \def boot_spm_interrupt_enable() + Enable the SPM interrupt. */ + +#define boot_spm_interrupt_enable() (__SPM_REG |= (uint8_t)_BV(SPMIE)) + +/** \ingroup avr_boot + \def boot_spm_interrupt_disable() + Disable the SPM interrupt. */ + +#define boot_spm_interrupt_disable() (__SPM_REG &= (uint8_t)~_BV(SPMIE)) + +/** \ingroup avr_boot + \def boot_is_spm_interrupt() + Check if the SPM interrupt is enabled. */ + +#define boot_is_spm_interrupt() (__SPM_REG & (uint8_t)_BV(SPMIE)) + +/** \ingroup avr_boot + \def boot_rww_busy() + Check if the RWW section is busy. */ + +#define boot_rww_busy() (__SPM_REG & (uint8_t)_BV(__COMMON_ASB)) + +/** \ingroup avr_boot + \def boot_spm_busy() + Check if the SPM instruction is busy. */ + +#define boot_spm_busy() (__SPM_REG & (uint8_t)_BV(__SPM_ENABLE)) + +/** \ingroup avr_boot + \def boot_spm_busy_wait() + Wait while the SPM instruction is busy. */ + +#define boot_spm_busy_wait() do{}while(boot_spm_busy()) + +#ifndef __DOXYGEN__ +#define __BOOT_PAGE_ERASE (_BV(__SPM_ENABLE) | _BV(PGERS)) +#define __BOOT_PAGE_WRITE (_BV(__SPM_ENABLE) | _BV(PGWRT)) +#define __BOOT_PAGE_FILL _BV(__SPM_ENABLE) +#define __BOOT_RWW_ENABLE (_BV(__SPM_ENABLE) | _BV(__COMMON_ASRE)) +#if defined(BLBSET) +#define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(BLBSET)) +#elif defined(RFLB) /* Some devices have RFLB defined instead of BLBSET. */ +#define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(RFLB)) +#endif + +#define __boot_page_fill_normal(address, data) \ +(__extension__({ \ + __asm__ __volatile__ \ + ( \ + "movw r0, %3\n\t" \ + "sts %0, %1\n\t" \ + "spm\n\t" \ + "clr r1\n\t" \ + : \ + : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ + "r" ((uint8_t)(__BOOT_PAGE_FILL)), \ + "z" ((uint16_t)(address)), \ + "r" ((uint16_t)(data)) \ + : "r0" \ + ); \ +})) + +#define __boot_page_fill_alternate(address, data)\ +(__extension__({ \ + __asm__ __volatile__ \ + ( \ + "movw r0, %3\n\t" \ + "sts %0, %1\n\t" \ + "spm\n\t" \ + ".word 0xffff\n\t" \ + "nop\n\t" \ + "clr r1\n\t" \ + : \ + : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ + "r" ((uint8_t)(__BOOT_PAGE_FILL)), \ + "z" ((uint16_t)(address)), \ + "r" ((uint16_t)(data)) \ + : "r0" \ + ); \ +})) + +#define __boot_page_fill_extended(address, data) \ +(__extension__({ \ + __asm__ __volatile__ \ + ( \ + "movw r0, %4\n\t" \ + "movw r30, %A3\n\t" \ + "sts %1, %C3\n\t" \ + "sts %0, %2\n\t" \ + "spm\n\t" \ + "clr r1\n\t" \ + : \ + : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ + "i" (_SFR_MEM_ADDR(RAMPZ)), \ + "r" ((uint8_t)(__BOOT_PAGE_FILL)), \ + "r" ((uint32_t)(address)), \ + "r" ((uint16_t)(data)) \ + : "r0", "r30", "r31" \ + ); \ +})) + +#define __boot_page_erase_normal(address) \ +(__extension__({ \ + __asm__ __volatile__ \ + ( \ + "sts %0, %1\n\t" \ + "spm\n\t" \ + : \ + : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ + "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \ + "z" ((uint16_t)(address)) \ + ); \ +})) + +#define __boot_page_erase_alternate(address) \ +(__extension__({ \ + __asm__ __volatile__ \ + ( \ + "sts %0, %1\n\t" \ + "spm\n\t" \ + ".word 0xffff\n\t" \ + "nop\n\t" \ + : \ + : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ + "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \ + "z" ((uint16_t)(address)) \ + ); \ +})) + +#define __boot_page_erase_extended(address) \ +(__extension__({ \ + __asm__ __volatile__ \ + ( \ + "movw r30, %A3\n\t" \ + "sts %1, %C3\n\t" \ + "sts %0, %2\n\t" \ + "spm\n\t" \ + : \ + : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ + "i" (_SFR_MEM_ADDR(RAMPZ)), \ + "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \ + "r" ((uint32_t)(address)) \ + : "r30", "r31" \ + ); \ +})) + +#define __boot_page_write_normal(address) \ +(__extension__({ \ + __asm__ __volatile__ \ + ( \ + "sts %0, %1\n\t" \ + "spm\n\t" \ + : \ + : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ + "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \ + "z" ((uint16_t)(address)) \ + ); \ +})) + +#define __boot_page_write_alternate(address) \ +(__extension__({ \ + __asm__ __volatile__ \ + ( \ + "sts %0, %1\n\t" \ + "spm\n\t" \ + ".word 0xffff\n\t" \ + "nop\n\t" \ + : \ + : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ + "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \ + "z" ((uint16_t)(address)) \ + ); \ +})) + +#define __boot_page_write_extended(address) \ +(__extension__({ \ + __asm__ __volatile__ \ + ( \ + "movw r30, %A3\n\t" \ + "sts %1, %C3\n\t" \ + "sts %0, %2\n\t" \ + "spm\n\t" \ + : \ + : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ + "i" (_SFR_MEM_ADDR(RAMPZ)), \ + "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \ + "r" ((uint32_t)(address)) \ + : "r30", "r31" \ + ); \ +})) + +#define __boot_rww_enable() \ +(__extension__({ \ + __asm__ __volatile__ \ + ( \ + "sts %0, %1\n\t" \ + "spm\n\t" \ + : \ + : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ + "r" ((uint8_t)(__BOOT_RWW_ENABLE)) \ + ); \ +})) + +#define __boot_rww_enable_alternate() \ +(__extension__({ \ + __asm__ __volatile__ \ + ( \ + "sts %0, %1\n\t" \ + "spm\n\t" \ + ".word 0xffff\n\t" \ + "nop\n\t" \ + : \ + : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ + "r" ((uint8_t)(__BOOT_RWW_ENABLE)) \ + ); \ +})) + +/* From the mega16/mega128 data sheets (maybe others): + + Bits by SPM To set the Boot Loader Lock bits, write the desired data to + R0, write "X0001001" to SPMCR and execute SPM within four clock cycles + after writing SPMCR. The only accessible Lock bits are the Boot Lock bits + that may prevent the Application and Boot Loader section from any + software update by the MCU. + + If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit + will be programmed if an SPM instruction is executed within four cycles + after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is + don't care during this operation, but for future compatibility it is + recommended to load the Z-pointer with $0001 (same as used for reading the + Lock bits). For future compatibility It is also recommended to set bits 7, + 6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the + Lock bits the entire Flash can be read during the operation. */ + +#define __boot_lock_bits_set(lock_bits) \ +(__extension__({ \ + uint8_t value = (uint8_t)(~(lock_bits)); \ + __asm__ __volatile__ \ + ( \ + "ldi r30, 1\n\t" \ + "ldi r31, 0\n\t" \ + "mov r0, %2\n\t" \ + "sts %0, %1\n\t" \ + "spm\n\t" \ + : \ + : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ + "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \ + "r" (value) \ + : "r0", "r30", "r31" \ + ); \ +})) + +#define __boot_lock_bits_set_alternate(lock_bits) \ +(__extension__({ \ + uint8_t value = (uint8_t)(~(lock_bits)); \ + __asm__ __volatile__ \ + ( \ + "ldi r30, 1\n\t" \ + "ldi r31, 0\n\t" \ + "mov r0, %2\n\t" \ + "sts %0, %1\n\t" \ + "spm\n\t" \ + ".word 0xffff\n\t" \ + "nop\n\t" \ + : \ + : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ + "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \ + "r" (value) \ + : "r0", "r30", "r31" \ + ); \ +})) +#endif /* __DOXYGEN__ */ + +/* + Reading lock and fuse bits: + + Similarly to writing the lock bits above, set BLBSET and SPMEN (or + SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an + LPM instruction. + + Z address: contents: + 0x0000 low fuse bits + 0x0001 lock bits + 0x0002 extended fuse bits + 0x0003 high fuse bits + + Sounds confusing, doesn't it? + + Unlike the macros in pgmspace.h, no need to care for non-enhanced + cores here as these old cores do not provide SPM support anyway. + */ + +/** \ingroup avr_boot + \def GET_LOW_FUSE_BITS + address to read the low fuse bits, using boot_lock_fuse_bits_get + */ +#define GET_LOW_FUSE_BITS (0x0000) +/** \ingroup avr_boot + \def GET_LOCK_BITS + address to read the lock bits, using boot_lock_fuse_bits_get + */ +#define GET_LOCK_BITS (0x0001) +/** \ingroup avr_boot + \def GET_EXTENDED_FUSE_BITS + address to read the extended fuse bits, using boot_lock_fuse_bits_get + */ +#define GET_EXTENDED_FUSE_BITS (0x0002) +/** \ingroup avr_boot + \def GET_HIGH_FUSE_BITS + address to read the high fuse bits, using boot_lock_fuse_bits_get + */ +#define GET_HIGH_FUSE_BITS (0x0003) + +/** \ingroup avr_boot + \def boot_lock_fuse_bits_get(address) + + Read the lock or fuse bits at \c address. + + Parameter \c address can be any of GET_LOW_FUSE_BITS, + GET_LOCK_BITS, GET_EXTENDED_FUSE_BITS, or GET_HIGH_FUSE_BITS. + + \note The lock and fuse bits returned are the physical values, + i.e. a bit returned as 0 means the corresponding fuse or lock bit + is programmed. + */ +#define boot_lock_fuse_bits_get(address) \ +(__extension__({ \ + uint8_t __result; \ + __asm__ __volatile__ \ + ( \ + "sts %1, %2\n\t" \ + "lpm %0, Z\n\t" \ + : "=r" (__result) \ + : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ + "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \ + "z" ((uint16_t)(address)) \ + ); \ + __result; \ +})) + +#ifndef __DOXYGEN__ +#define __BOOT_SIGROW_READ (_BV(__SPM_ENABLE) | _BV(SIGRD)) +#endif +/** \ingroup avr_boot + \def boot_signature_byte_get(address) + + Read the Signature Row byte at \c address. For some MCU types, + this function can also retrieve the factory-stored oscillator + calibration bytes. + + Parameter \c address can be 0-0x1f as documented by the datasheet. + \note The values are MCU type dependent. +*/ + +#define boot_signature_byte_get(addr) \ +(__extension__({ \ + uint8_t __result; \ + __asm__ __volatile__ \ + ( \ + "sts %1, %2\n\t" \ + "lpm %0, Z" "\n\t" \ + : "=r" (__result) \ + : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ + "r" ((uint8_t)(__BOOT_SIGROW_READ)), \ + "z" ((uint16_t)(addr)) \ + ); \ + __result; \ +})) + +/** \ingroup avr_boot + \def boot_page_fill(address, data) + + Fill the bootloader temporary page buffer for flash + address with data word. + + \note The address is a byte address. The data is a word. The AVR + writes data to the buffer a word at a time, but addresses the buffer + per byte! So, increment your address by 2 between calls, and send 2 + data bytes in a word format! The LSB of the data is written to the lower + address; the MSB of the data is written to the higher address.*/ + +/** \ingroup avr_boot + \def boot_page_erase(address) + + Erase the flash page that contains address. + + \note address is a byte address in flash, not a word address. */ + +/** \ingroup avr_boot + \def boot_page_write(address) + + Write the bootloader temporary page buffer + to flash page that contains address. + + \note address is a byte address in flash, not a word address. */ + +/** \ingroup avr_boot + \def boot_rww_enable() + + Enable the Read-While-Write memory section. */ + +/** \ingroup avr_boot + \def boot_lock_bits_set(lock_bits) + + Set the bootloader lock bits. + + \param lock_bits A mask of which Boot Loader Lock Bits to set. + + \note In this context, a 'set bit' will be written to a zero value. + Note also that only BLBxx bits can be programmed by this command. + + For example, to disallow the SPM instruction from writing to the Boot + Loader memory section of flash, you would use this macro as such: + + \code + boot_lock_bits_set (_BV (BLB11)); + \endcode + + \note Like any lock bits, the Boot Loader Lock Bits, once set, + cannot be cleared again except by a chip erase which will in turn + also erase the boot loader itself. */ + +/* Normal versions of the macros use 16-bit addresses. + Extended versions of the macros use 32-bit addresses. + Alternate versions of the macros use 16-bit addresses and require special + instruction sequences after LPM. + + FLASHEND is defined in the ioXXXX.h file. + USHRT_MAX is defined in . */ + +#if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \ + || defined(__AVR_ATmega323__) + +/* Alternate: ATmega161/163/323 and 16 bit address */ +#define boot_page_fill(address, data) __boot_page_fill_alternate(address, data) +#define boot_page_erase(address) __boot_page_erase_alternate(address) +#define boot_page_write(address) __boot_page_write_alternate(address) +#define boot_rww_enable() __boot_rww_enable_alternate() +#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_alternate(lock_bits) + +#elif (FLASHEND > USHRT_MAX) + +/* Extended: >16 bit address */ +#define boot_page_fill(address, data) __boot_page_fill_extended(address, data) +#define boot_page_erase(address) __boot_page_erase_extended(address) +#define boot_page_write(address) __boot_page_write_extended(address) +#define boot_rww_enable() __boot_rww_enable() +#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits) + +#else + +/* Normal: 16 bit address */ +#define boot_page_fill(address, data) __boot_page_fill_normal(address, data) +#define boot_page_erase(address) __boot_page_erase_normal(address) +#define boot_page_write(address) __boot_page_write_normal(address) +#define boot_rww_enable() __boot_rww_enable() +#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits) + +#endif + +/** \ingroup avr_boot + + Same as boot_page_fill() except it waits for eeprom and spm operations to + complete before filling the page. */ + +#define boot_page_fill_safe(address, data) \ +do { \ + boot_spm_busy_wait(); \ + eeprom_busy_wait(); \ + boot_page_fill(address, data); \ +} while (0) + +/** \ingroup avr_boot + + Same as boot_page_erase() except it waits for eeprom and spm operations to + complete before erasing the page. */ + +#define boot_page_erase_safe(address) \ +do { \ + boot_spm_busy_wait(); \ + eeprom_busy_wait(); \ + boot_page_erase (address); \ +} while (0) + +/** \ingroup avr_boot + + Same as boot_page_write() except it waits for eeprom and spm operations to + complete before writing the page. */ + +#define boot_page_write_safe(address) \ +do { \ + boot_spm_busy_wait(); \ + eeprom_busy_wait(); \ + boot_page_write (address); \ +} while (0) + +/** \ingroup avr_boot + + Same as boot_rww_enable() except waits for eeprom and spm operations to + complete before enabling the RWW mameory. */ + +#define boot_rww_enable_safe() \ +do { \ + boot_spm_busy_wait(); \ + eeprom_busy_wait(); \ + boot_rww_enable(); \ +} while (0) + +/** \ingroup avr_boot + + Same as boot_lock_bits_set() except waits for eeprom and spm operations to + complete before setting the lock bits. */ + +#define boot_lock_bits_set_safe(lock_bits) \ +do { \ + boot_spm_busy_wait(); \ + eeprom_busy_wait(); \ + boot_lock_bits_set (lock_bits); \ +} while (0) + +#endif /* _AVR_BOOT_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/builtins.h b/hardware/tools/avr/avr/include/avr/builtins.h new file mode 100644 index 0000000000000000000000000000000000000000..f0f554f1406755b248890c09501eace48ded31e6 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/builtins.h @@ -0,0 +1,113 @@ +/* Copyright (c) 2008 Anatoly Sokolov + Copyright (c) 2010 Joerg Wunsch + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +/* + avr/builtins.h - Intrinsic functions built into the compiler + */ + +#ifndef _AVR_BUILTINS_H_ +#define _AVR_BUILTINS_H_ + +#ifndef __HAS_DELAY_CYCLES +#define __HAS_DELAY_CYCLES 1 +#endif + +/** \file */ +/** \defgroup avr_builtins : GCC builtins + \code #include \endcode + + This header file declares AVR builtins. + All the functions documented here are built into the + compiler, and cause it to emit the corresponding assembly + code instructions. +*/ + +/** + \ingroup avr_builtins + + Enables interrupts by setting the global interrupt mask. */ +extern void __builtin_avr_sei(void); + +/** + \ingroup avr_builtins + + Disables all interrupts by clearing the global interrupt mask. */ +extern void __builtin_avr_cli(void); + +/** + \ingroup avr_builtins + + Emits a \c SLEEP instruction. */ + +extern void __builtin_avr_sleep(void); + +/** + \ingroup avr_builtins + + Emits a WDR (watchdog reset) instruction. */ +extern void __builtin_avr_wdr(void); + +/** + \ingroup avr_builtins + + Emits a SWAP (nibble swap) instruction on __b. */ +extern unsigned char __builtin_avr_swap(unsigned char __b); + +/** + \ingroup avr_builtins + + Emits an FMUL (fractional multiply unsigned) instruction. */ +extern unsigned int __builtin_avr_fmul(unsigned char __a, unsigned char __b); + +/** + \ingroup avr_builtins + + Emits an FMUL (fractional multiply signed) instruction. */ +extern int __builtin_avr_fmuls(char __a, char __b); + +/** + \ingroup avr_builtins + + Emits an FMUL (fractional multiply signed with unsigned) instruction. */ +extern int __builtin_avr_fmulsu(char __a, unsigned char __b); + +#if __HAS_DELAY_CYCLES || defined(__DOXYGEN__) +/** + \ingroup avr_builtins + + Emits a sequence of instructions causing the CPU to spend + \c __n cycles on it. */ +extern void __builtin_avr_delay_cycles(unsigned long __n); +#endif + +#endif /* _AVR_BUILTINS_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/common.h b/hardware/tools/avr/avr/include/avr/common.h new file mode 100644 index 0000000000000000000000000000000000000000..358b32892c59a3c08d911f34d2382895eddcd7c4 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/common.h @@ -0,0 +1,335 @@ +/* Copyright (c) 2007 Eric B. Weddington + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + + +#ifndef _AVR_COMMON_H +#define _AVR_COMMON_H + +#include + +/* +This purpose of this header is to define registers that have not been +previously defined in the individual device IO header files, and to define +other symbols that are common across AVR device families. + +This file is designed to be included in after the individual +device IO header files, and after + +*/ + +/*------------ Registers Not Previously Defined ------------*/ + +/* +These are registers that are not previously defined in the individual +IO header files, OR they are defined here because they are used in parts of +avr-libc even if a device is not selected but a general architecture has +been selected. +*/ + + +/* +Stack pointer register. + +AVR architecture 1 has no RAM, thus no stack pointer. + +All other architectures do have a stack pointer. Some devices have only +less than 256 bytes of possible RAM locations (128 Bytes of SRAM +and no option for external RAM), thus SPH is officially "reserved" +for them. +*/ +#if __AVR_ARCH__ >= 100 +# ifndef SPL +# define SPL _SFR_MEM8(0x3D) +# endif +# ifndef SPH +# define SPH _SFR_MEM8(0x3E) +# endif +# ifndef SP +# define SP _SFR_MEM16(0x3D) +# endif +#elif __AVR_ARCH__ != 1 +# ifndef SPL +# define SPL _SFR_IO8(0x3D) +# endif +# if XRAMEND < 0x100 && !defined(__COMPILING_AVR_LIBC__) +# ifndef SP +# define SP _SFR_IO8(0x3D) +# endif +# else +# ifndef SP +# define SP _SFR_IO16(0x3D) +# endif +# ifndef SPH +# define SPH _SFR_IO8(0x3E) +# endif +# endif /* XRAMEND < 0x100 && !defined(__COMPILING_AVR_LIBC__) */ +#endif /* __AVR_ARCH__ != 1 */ + + +/* Status Register */ +#ifndef SREG +# if __AVR_ARCH__ >= 100 +# define SREG _SFR_MEM8(0x3F) +# else +# define SREG _SFR_IO8(0x3F) +# endif +#endif + + +/* SREG bit definitions */ +#ifndef SREG_C +# define SREG_C (0) +#endif +#ifndef SREG_Z +# define SREG_Z (1) +#endif +#ifndef SREG_N +# define SREG_N (2) +#endif +#ifndef SREG_V +# define SREG_V (3) +#endif +#ifndef SREG_S +# define SREG_S (4) +#endif +#ifndef SREG_H +# define SREG_H (5) +#endif +#ifndef SREG_T +# define SREG_T (6) +#endif +#ifndef SREG_I +# define SREG_I (7) +#endif + + +#if defined(__COMPILING_AVR_LIBC__) + +/* AVR 6 Architecture */ +# if __AVR_ARCH__ == 6 +# ifndef EIND +# define EIND _SFR_IO8(0X3C) +# endif +/* XMEGA Architectures */ +# elif __AVR_ARCH__ >= 100 +# ifndef EIND +# define EIND _SFR_MEM8(0x3C) +# endif +# endif + +/* +Only few devices come without EEPROM. In order to assemble the +EEPROM library components without defining a specific device, we +keep the EEPROM-related definitions here. +*/ + +/* EEPROM Control Register */ +# ifndef EECR +# define EECR _SFR_IO8(0x1C) +# endif + +/* EEPROM Data Register */ +# ifndef EEDR +# define EEDR _SFR_IO8(0x1D) +# endif + +/* EEPROM Address Register */ +# ifndef EEAR +# define EEAR _SFR_IO16(0x1E) +# endif +# ifndef EEARL +# define EEARL _SFR_IO8(0x1E) +# endif +# ifndef EEARH +# define EEARH _SFR_IO8(0x1F) +# endif + +/* EEPROM Control Register bits */ +# ifndef EERE +# define EERE (0) +# endif +# ifndef EEWE +# define EEWE (1) +# endif +# ifndef EEMWE +# define EEMWE (2) +# endif +# ifndef EERIE +# define EERIE (3) +# endif + + +/* RAM Page Z Select Register */ +#ifndef RAMPZ +# if defined(__AVR_HAVE_RAMPZ__) && __AVR_HAVE_RAMPZ__ +# if __AVR_ARCH__ >= 100 +# define RAMPZ _SFR_MEM8(0x3B) +# else +# define RAMPZ _SFR_IO8(0x3B) +# endif +# endif +#endif + +#endif /* __COMPILING_AVR_LIBC__ */ + + + +/*------------ Common Symbols ------------*/ + +/* +Generic definitions for registers that are common across multiple AVR devices +and families. +*/ + +/* Pointer registers definitions */ +#if __AVR_ARCH__ != 1 /* avr1 does not have X and Y pointers */ +# define XL r26 +# define XH r27 +# define YL r28 +# define YH r29 +#endif /* #if __AVR_ARCH__ != 1 */ +#define ZL r30 +#define ZH r31 + + +/* Status Register */ +#if defined(SREG) +# define AVR_STATUS_REG SREG +# if __AVR_ARCH__ >= 100 +# define AVR_STATUS_ADDR _SFR_MEM_ADDR(SREG) +# else +# define AVR_STATUS_ADDR _SFR_IO_ADDR(SREG) +# endif +#endif + +/* Stack Pointer (combined) Register */ +#if defined(SP) +# define AVR_STACK_POINTER_REG SP +# if __AVR_ARCH__ >= 100 +# define AVR_STACK_POINTER_ADDR _SFR_MEM_ADDR(SP) +# else +# define AVR_STACK_POINTER_ADDR _SFR_IO_ADDR(SP) +# endif +#endif + +/* Stack Pointer High Register */ +#if defined(SPH) +# define _HAVE_AVR_STACK_POINTER_HI 1 +# define AVR_STACK_POINTER_HI_REG SPH +# if __AVR_ARCH__ >= 100 +# define AVR_STACK_POINTER_HI_ADDR _SFR_MEM_ADDR(SPH) +# else +# define AVR_STACK_POINTER_HI_ADDR _SFR_IO_ADDR(SPH) +# endif +#endif + +/* Stack Pointer Low Register */ +#if defined(SPL) +# define AVR_STACK_POINTER_LO_REG SPL +# if __AVR_ARCH__ >= 100 +# define AVR_STACK_POINTER_LO_ADDR _SFR_MEM_ADDR(SPL) +# else +# define AVR_STACK_POINTER_LO_ADDR _SFR_IO_ADDR(SPL) +# endif +#endif + +/* RAMPD Register */ +#if defined(RAMPD) +# define AVR_RAMPD_REG RAMPD +# if __AVR_ARCH__ >= 100 +# define AVR_RAMPD_ADDR _SFR_MEM_ADDR(RAMPD) +# else +# define AVR_RAMPD_ADDR _SFR_IO_ADDR(RAMPD) +# endif +#endif + +/* RAMPX Register */ +#if defined(RAMPX) +# define AVR_RAMPX_REG RAMPX +# if __AVR_ARCH__ >= 100 +# define AVR_RAMPX_ADDR _SFR_MEM_ADDR(RAMPX) +# else +# define AVR_RAMPX_ADDR _SFR_IO_ADDR(RAMPX) +# endif +#endif + +/* RAMPY Register */ +#if defined(RAMPY) +# define AVR_RAMPY_REG RAMPY +# if __AVR_ARCH__ >= 100 +# define AVR_RAMPY_ADDR _SFR_MEM_ADDR(RAMPY) +# else +# define AVR_RAMPY_ADDR _SFR_IO_ADDR(RAMPY) +# endif +#endif + +/* RAMPZ Register */ +#if defined(RAMPZ) +# define AVR_RAMPZ_REG RAMPZ +# if __AVR_ARCH__ >= 100 +# define AVR_RAMPZ_ADDR _SFR_MEM_ADDR(RAMPZ) +# else +# define AVR_RAMPZ_ADDR _SFR_IO_ADDR(RAMPZ) +# endif +#endif + +/* Extended Indirect Register */ +#if defined(EIND) +# define AVR_EXTENDED_INDIRECT_REG EIND +# if __AVR_ARCH__ >= 100 +# define AVR_EXTENDED_INDIRECT_ADDR _SFR_MEM_ADDR(EIND) +# else +# define AVR_EXTENDED_INDIRECT_ADDR _SFR_IO_ADDR(EIND) +# endif +#endif + +/*------------ Workaround to old compilers (4.1.2 and earlier) ------------*/ + +#ifndef __AVR_HAVE_MOVW__ +# if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ +# define __AVR_HAVE_MOVW__ 1 +# endif +#endif + +#ifndef __AVR_HAVE_LPMX__ +# if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ +# define __AVR_HAVE_LPMX__ 1 +# endif +#endif + +#ifndef __AVR_HAVE_MUL__ +# if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ +# define __AVR_HAVE_MUL__ 1 +# endif +#endif + +#endif /* _AVR_COMMON_H */ diff --git a/hardware/tools/avr/avr/include/avr/cpufunc.h b/hardware/tools/avr/avr/include/avr/cpufunc.h new file mode 100644 index 0000000000000000000000000000000000000000..3e255aaae0bc3f25010778e293027f1c4fdcbfe5 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/cpufunc.h @@ -0,0 +1,93 @@ +/* Copyright (c) 2010, Joerg Wunsch + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +/* avr/cpufunc.h - Special CPU functions */ + +#ifndef _AVR_CPUFUNC_H_ +#define _AVR_CPUFUNC_H_ 1 + +#include + +/** \file */ +/** \defgroup avr_cpufunc : Special AVR CPU functions + \code #include \endcode + + This header file contains macros that access special functions of + the AVR CPU which do not fit into any of the other header files. + +*/ + +#if defined(__DOXYGEN__) +/** + \ingroup avr_cpufunc + \def _NOP + + Execute a no operation (NOP) CPU instruction. This + should not be used to implement delays, better use the functions + from or for this. For + debugging purposes, a NOP can be useful to have an instruction that + is guaranteed to be not optimized away by the compiler, so it can + always become a breakpoint in the debugger. +*/ +#define _NOP() +#else /* real code */ +#define _NOP() __asm__ __volatile__("nop") +#endif /* __DOXYGEN__ */ + +#if defined(__DOXYGEN__) +/** + \ingroup avr_cpufunc + \def _MemoryBarrier + + Implement a read/write memory barrier. A memory + barrier instructs the compiler to not cache any memory data in + registers beyond the barrier. This can sometimes be more effective + than blocking certain optimizations by declaring some object with a + \c volatile qualifier. + + See \ref optim_code_reorder for things to be taken into account + with respect to compiler optimizations. +*/ +#define _MemoryBarrier() +#else /* real code */ +#define _MemoryBarrier() __asm__ __volatile__("":::"memory") +#endif /* __DOXYGEN__ */ + +/** + \ingroup avr_cpufunc + + Write \a __value to Configuration Change Protected (CCP) IO register + at \a __ioaddr. + */ +void ccp_write_io (uint8_t *__ioaddr, uint8_t __value); + +#endif /* _AVR_CPUFUNC_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/crc16.h b/hardware/tools/avr/avr/include/avr/crc16.h new file mode 100644 index 0000000000000000000000000000000000000000..6c8de25ea04c4039e8df20512d980b154b1d6565 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/crc16.h @@ -0,0 +1,39 @@ +/* Copyright (c) 2005 Joerg Wunsch + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef _AVR_CRC16_H_ +#define _AVR_CRC16_H_ + +#warning "This file has been moved to ." +#include + +#endif /* _AVR_CRC16_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/delay.h b/hardware/tools/avr/avr/include/avr/delay.h new file mode 100644 index 0000000000000000000000000000000000000000..2847cebb97c3459df463d676a4f9fa05f3a447c2 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/delay.h @@ -0,0 +1,39 @@ +/* Copyright (c) 2005 Joerg Wunsch + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef _AVR_DELAY_H_ +#define _AVR_DELAY_H_ + +#warning "This file has been moved to ." +#include + +#endif /* _AVR_DELAY_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/eeprom.h b/hardware/tools/avr/avr/include/avr/eeprom.h new file mode 100644 index 0000000000000000000000000000000000000000..6f435d3c65095786018b4196b647620bc795327e --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/eeprom.h @@ -0,0 +1,248 @@ +/* Copyright (c) 2002, 2003, 2004, 2007 Marek Michalkiewicz + Copyright (c) 2005, 2006 Bjoern Haase + Copyright (c) 2008 Atmel Corporation + Copyright (c) 2008 Wouter van Gulik + Copyright (c) 2009 Dmitry Xmelkov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef _AVR_EEPROM_H_ +#define _AVR_EEPROM_H_ 1 + +#include + +#if !E2END && !defined(__DOXYGEN__) && !defined(__COMPILING_AVR_LIBC__) +# warning "Device does not have EEPROM available." +#else + +#if defined (EEAR) && !defined (EEARL) && !defined (EEARH) +#define EEARL EEAR +#endif + +#ifndef __ASSEMBLER__ + +#include /* size_t */ +#include + +/** \defgroup avr_eeprom : EEPROM handling + \code #include \endcode + + This header file declares the interface to some simple library + routines suitable for handling the data EEPROM contained in the + AVR microcontrollers. The implementation uses a simple polled + mode interface. Applications that require interrupt-controlled + EEPROM access to ensure that no time will be wasted in spinloops + will have to deploy their own implementation. + + \par Notes: + + - In addition to the write functions there is a set of update ones. + This functions read each byte first and skip the burning if the + old value is the same with new. The scaning direction is from + high address to low, to obtain quick return in common cases. + + - All of the read/write functions first make sure the EEPROM is + ready to be accessed. Since this may cause long delays if a + write operation is still pending, time-critical applications + should first poll the EEPROM e. g. using eeprom_is_ready() before + attempting any actual I/O. But this functions are not wait until + SELFPRGEN in SPMCSR becomes zero. Do this manually, if your + softwate contains the Flash burning. + + - As these functions modify IO registers, they are known to be + non-reentrant. If any of these functions are used from both, + standard and interrupt context, the applications must ensure + proper protection (e.g. by disabling interrupts before accessing + them). + + - All write functions force erase_and_write programming mode. + + - For Xmega the EEPROM start address is 0, like other architectures. + The reading functions add the 0x2000 value to use EEPROM mapping into + data space. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __ATTR_PURE__ +# ifdef __DOXYGEN__ +# define __ATTR_PURE__ +# else +# define __ATTR_PURE__ __attribute__((__pure__)) +# endif +#endif + +/** \def EEMEM + \ingroup avr_eeprom + Attribute expression causing a variable to be allocated within the + .eeprom section. */ +#define EEMEM __attribute__((section(".eeprom"))) + +/** \def eeprom_is_ready + \ingroup avr_eeprom + \returns 1 if EEPROM is ready for a new read/write operation, 0 if not. + */ +#if defined (__DOXYGEN__) +# define eeprom_is_ready() +#elif defined (NVM_STATUS) +# define eeprom_is_ready() bit_is_clear (NVM_STATUS, NVM_NVMBUSY_bp) +#elif defined (NVMCTRL_STATUS) +# define eeprom_is_ready() bit_is_clear (NVMCTRL_STATUS, NVMCTRL_EEBUSY_bp) +#elif defined (DEECR) +# define eeprom_is_ready() bit_is_clear (DEECR, BSY) +#elif defined (EEPE) +# define eeprom_is_ready() bit_is_clear (EECR, EEPE) +#else +# define eeprom_is_ready() bit_is_clear (EECR, EEWE) +#endif + + +/** \def eeprom_busy_wait + \ingroup avr_eeprom + Loops until the eeprom is no longer busy. + \returns Nothing. + */ +#define eeprom_busy_wait() do {} while (!eeprom_is_ready()) + + +/** \ingroup avr_eeprom + Read one byte from EEPROM address \a __p. + */ +uint8_t eeprom_read_byte (const uint8_t *__p) __ATTR_PURE__; + +/** \ingroup avr_eeprom + Read one 16-bit word (little endian) from EEPROM address \a __p. + */ +uint16_t eeprom_read_word (const uint16_t *__p) __ATTR_PURE__; + +/** \ingroup avr_eeprom + Read one 32-bit double word (little endian) from EEPROM address \a __p. + */ +uint32_t eeprom_read_dword (const uint32_t *__p) __ATTR_PURE__; + +/** \ingroup avr_eeprom + Read one float value (little endian) from EEPROM address \a __p. + */ +float eeprom_read_float (const float *__p) __ATTR_PURE__; + +/** \ingroup avr_eeprom + Read a block of \a __n bytes from EEPROM address \a __src to SRAM + \a __dst. + */ +void eeprom_read_block (void *__dst, const void *__src, size_t __n); + + +/** \ingroup avr_eeprom + Write a byte \a __value to EEPROM address \a __p. + */ +void eeprom_write_byte (uint8_t *__p, uint8_t __value); + +/** \ingroup avr_eeprom + Write a word \a __value to EEPROM address \a __p. + */ +void eeprom_write_word (uint16_t *__p, uint16_t __value); + +/** \ingroup avr_eeprom + Write a 32-bit double word \a __value to EEPROM address \a __p. + */ +void eeprom_write_dword (uint32_t *__p, uint32_t __value); + +/** \ingroup avr_eeprom + Write a float \a __value to EEPROM address \a __p. + */ +void eeprom_write_float (float *__p, float __value); + +/** \ingroup avr_eeprom + Write a block of \a __n bytes to EEPROM address \a __dst from \a __src. + \note The argument order is mismatch with common functions like strcpy(). + */ +void eeprom_write_block (const void *__src, void *__dst, size_t __n); + + +/** \ingroup avr_eeprom + Update a byte \a __value to EEPROM address \a __p. + */ +void eeprom_update_byte (uint8_t *__p, uint8_t __value); + +/** \ingroup avr_eeprom + Update a word \a __value to EEPROM address \a __p. + */ +void eeprom_update_word (uint16_t *__p, uint16_t __value); + +/** \ingroup avr_eeprom + Update a 32-bit double word \a __value to EEPROM address \a __p. + */ +void eeprom_update_dword (uint32_t *__p, uint32_t __value); + +/** \ingroup avr_eeprom + Update a float \a __value to EEPROM address \a __p. + */ +void eeprom_update_float (float *__p, float __value); + +/** \ingroup avr_eeprom + Update a block of \a __n bytes to EEPROM address \a __dst from \a __src. + \note The argument order is mismatch with common functions like strcpy(). + */ +void eeprom_update_block (const void *__src, void *__dst, size_t __n); + + +/** \name IAR C compatibility defines */ +/*@{*/ + +/** \def _EEPUT + \ingroup avr_eeprom + Write a byte to EEPROM. Compatibility define for IAR C. */ +#define _EEPUT(addr, val) eeprom_write_byte ((uint8_t *)(addr), (uint8_t)(val)) + +/** \def __EEPUT + \ingroup avr_eeprom + Write a byte to EEPROM. Compatibility define for IAR C. */ +#define __EEPUT(addr, val) eeprom_write_byte ((uint8_t *)(addr), (uint8_t)(val)) + +/** \def _EEGET + \ingroup avr_eeprom + Read a byte from EEPROM. Compatibility define for IAR C. */ +#define _EEGET(var, addr) (var) = eeprom_read_byte ((const uint8_t *)(addr)) + +/** \def __EEGET + \ingroup avr_eeprom + Read a byte from EEPROM. Compatibility define for IAR C. */ +#define __EEGET(var, addr) (var) = eeprom_read_byte ((const uint8_t *)(addr)) + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* !__ASSEMBLER__ */ +#endif /* E2END || defined(__DOXYGEN__) || defined(__COMPILING_AVR_LIBC__) */ +#endif /* !_AVR_EEPROM_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/fuse.h b/hardware/tools/avr/avr/include/avr/fuse.h new file mode 100644 index 0000000000000000000000000000000000000000..22888a03ee4d00c67a4d6e3c196dbde952e69716 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/fuse.h @@ -0,0 +1,274 @@ +/* Copyright (c) 2007, Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +/* avr/fuse.h - Fuse API */ + +#ifndef _AVR_FUSE_H_ +#define _AVR_FUSE_H_ 1 + +/* This file must be explicitly included by . */ +#if !defined(_AVR_IO_H_) +#error "You must #include and not by itself." +#endif + + +/** \file */ +/** \defgroup avr_fuse : Fuse Support + + \par Introduction + + The Fuse API allows a user to specify the fuse settings for the specific + AVR device they are compiling for. These fuse settings will be placed + in a special section in the ELF output file, after linking. + + Programming tools can take advantage of the fuse information embedded in + the ELF file, by extracting this information and determining if the fuses + need to be programmed before programming the Flash and EEPROM memories. + This also allows a single ELF file to contain all the + information needed to program an AVR. + + To use the Fuse API, include the header file, which in turn + automatically includes the individual I/O header file and the + file. These other two files provides everything necessary to set the AVR + fuses. + + \par Fuse API + + Each I/O header file must define the FUSE_MEMORY_SIZE macro which is + defined to the number of fuse bytes that exist in the AVR device. + + A new type, __fuse_t, is defined as a structure. The number of fields in + this structure are determined by the number of fuse bytes in the + FUSE_MEMORY_SIZE macro. + + If FUSE_MEMORY_SIZE == 1, there is only a single field: byte, of type + unsigned char. + + If FUSE_MEMORY_SIZE == 2, there are two fields: low, and high, of type + unsigned char. + + If FUSE_MEMORY_SIZE == 3, there are three fields: low, high, and extended, + of type unsigned char. + + If FUSE_MEMORY_SIZE > 3, there is a single field: byte, which is an array + of unsigned char with the size of the array being FUSE_MEMORY_SIZE. + + A convenience macro, FUSEMEM, is defined as a GCC attribute for a + custom-named section of ".fuse". + + A convenience macro, FUSES, is defined that declares a variable, __fuse, of + type __fuse_t with the attribute defined by FUSEMEM. This variable + allows the end user to easily set the fuse data. + + \note If a device-specific I/O header file has previously defined FUSEMEM, + then FUSEMEM is not redefined. If a device-specific I/O header file has + previously defined FUSES, then FUSES is not redefined. + + Each AVR device I/O header file has a set of defined macros which specify the + actual fuse bits available on that device. The AVR fuses have inverted + values, logical 1 for an unprogrammed (disabled) bit and logical 0 for a + programmed (enabled) bit. The defined macros for each individual fuse + bit represent this in their definition by a bit-wise inversion of a mask. + For example, the FUSE_EESAVE fuse in the ATmega128 is defined as: + \code + #define FUSE_EESAVE ~_BV(3) + \endcode + \note The _BV macro creates a bit mask from a bit number. It is then + inverted to represent logical values for a fuse memory byte. + + To combine the fuse bits macros together to represent a whole fuse byte, + use the bitwise AND operator, like so: + \code + (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN) + \endcode + + Each device I/O header file also defines macros that provide default values + for each fuse byte that is available. LFUSE_DEFAULT is defined for a Low + Fuse byte. HFUSE_DEFAULT is defined for a High Fuse byte. EFUSE_DEFAULT + is defined for an Extended Fuse byte. + + If FUSE_MEMORY_SIZE > 3, then the I/O header file defines macros that + provide default values for each fuse byte like so: + FUSE0_DEFAULT + FUSE1_DEFAULT + FUSE2_DEFAULT + FUSE3_DEFAULT + FUSE4_DEFAULT + .... + + \par API Usage Example + + Putting all of this together is easy. Using C99's designated initializers: + + \code + #include + + FUSES = + { + .low = LFUSE_DEFAULT, + .high = (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN), + .extended = EFUSE_DEFAULT, + }; + + int main(void) + { + return 0; + } + \endcode + + Or, using the variable directly instead of the FUSES macro, + + \code + #include + + __fuse_t __fuse __attribute__((section (".fuse"))) = + { + .low = LFUSE_DEFAULT, + .high = (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN), + .extended = EFUSE_DEFAULT, + }; + + int main(void) + { + return 0; + } + \endcode + + If you are compiling in C++, you cannot use the designated intializers so + you must do: + + \code + #include + + FUSES = + { + LFUSE_DEFAULT, // .low + (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN), // .high + EFUSE_DEFAULT, // .extended + }; + + int main(void) + { + return 0; + } + \endcode + + + However there are a number of caveats that you need to be aware of to + use this API properly. + + Be sure to include to get all of the definitions for the API. + The FUSES macro defines a global variable to store the fuse data. This + variable is assigned to its own linker section. Assign the desired fuse + values immediately in the variable initialization. + + The .fuse section in the ELF file will get its values from the initial + variable assignment ONLY. This means that you can NOT assign values to + this variable in functions and the new values will not be put into the + ELF .fuse section. + + The global variable is declared in the FUSES macro has two leading + underscores, which means that it is reserved for the "implementation", + meaning the library, so it will not conflict with a user-named variable. + + You must initialize ALL fields in the __fuse_t structure. This is because + the fuse bits in all bytes default to a logical 1, meaning unprogrammed. + Normal uninitialized data defaults to all locgial zeros. So it is vital that + all fuse bytes are initialized, even with default data. If they are not, + then the fuse bits may not programmed to the desired settings. + + Be sure to have the -mmcu=device flag in your compile command line and + your linker command line to have the correct device selected and to have + the correct I/O header file included when you include . + + You can print out the contents of the .fuse section in the ELF file by + using this command line: + \code + avr-objdump -s -j .fuse + \endcode + The section contents shows the address on the left, then the data going from + lower address to a higher address, left to right. + +*/ + +#if !(defined(__ASSEMBLER__) || defined(__DOXYGEN__)) + +#ifndef FUSEMEM +#define FUSEMEM __attribute__((__used__, __section__ (".fuse"))) +#endif + +#if FUSE_MEMORY_SIZE > 3 + +typedef struct +{ + unsigned char byte[FUSE_MEMORY_SIZE]; +} __fuse_t; + + +#elif FUSE_MEMORY_SIZE == 3 + +typedef struct +{ + unsigned char low; + unsigned char high; + unsigned char extended; +} __fuse_t; + +#elif FUSE_MEMORY_SIZE == 2 + +typedef struct +{ + unsigned char low; + unsigned char high; +} __fuse_t; + +#elif FUSE_MEMORY_SIZE == 1 + +typedef struct +{ + unsigned char byte; +} __fuse_t; + +#endif + +#if !defined(FUSES) + #if defined(__AVR_XMEGA__) + #define FUSES NVM_FUSES_t __fuse FUSEMEM + #else + #define FUSES __fuse_t __fuse FUSEMEM + #endif +#endif + + +#endif /* !(__ASSEMBLER__ || __DOXYGEN__) */ + +#endif /* _AVR_FUSE_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/interrupt.h b/hardware/tools/avr/avr/include/avr/interrupt.h new file mode 100644 index 0000000000000000000000000000000000000000..ce9a4bdfdf8ba7db0ef8d865b23d23af300b08ca --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/interrupt.h @@ -0,0 +1,344 @@ +/* Copyright (c) 2002,2005,2007 Marek Michalkiewicz + Copyright (c) 2007, Dean Camera + + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef _AVR_INTERRUPT_H_ +#define _AVR_INTERRUPT_H_ + +#include + +#if !defined(__DOXYGEN__) && !defined(__STRINGIFY) +/* Auxiliary macro for ISR_ALIAS(). */ +#define __STRINGIFY(x) #x +#endif /* !defined(__DOXYGEN__) */ + +/** +\file +\@{ +*/ + + +/** \name Global manipulation of the interrupt flag + + The global interrupt flag is maintained in the I bit of the status + register (SREG). + + Handling interrupts frequently requires attention regarding atomic + access to objects that could be altered by code running within an + interrupt context, see . + + Frequently, interrupts are being disabled for periods of time in + order to perform certain operations without being disturbed; see + \ref optim_code_reorder for things to be taken into account with + respect to compiler optimizations. +*/ + +#if defined(__DOXYGEN__) +/** \def sei() + \ingroup avr_interrupts + + Enables interrupts by setting the global interrupt mask. This function + actually compiles into a single line of assembly, so there is no function + call overhead. However, the macro also implies a memory barrier + which can cause additional loss of optimization. + + In order to implement atomic access to multi-byte objects, + consider using the macros from , rather than + implementing them manually with cli() and sei(). +*/ +#define sei() +#else /* !DOXYGEN */ +# define sei() __asm__ __volatile__ ("sei" ::: "memory") +#endif /* DOXYGEN */ + +#if defined(__DOXYGEN__) +/** \def cli() + \ingroup avr_interrupts + + Disables all interrupts by clearing the global interrupt mask. This function + actually compiles into a single line of assembly, so there is no function + call overhead. However, the macro also implies a memory barrier + which can cause additional loss of optimization. + + In order to implement atomic access to multi-byte objects, + consider using the macros from , rather than + implementing them manually with cli() and sei(). +*/ +#define cli() +#else /* !DOXYGEN */ +# define cli() __asm__ __volatile__ ("cli" ::: "memory") +#endif /* DOXYGEN */ + + +/** \name Macros for writing interrupt handler functions */ + + +#if defined(__DOXYGEN__) +/** \def ISR(vector [, attributes]) + \ingroup avr_interrupts + + Introduces an interrupt handler function (interrupt service + routine) that runs with global interrupts initially disabled + by default with no attributes specified. + + The attributes are optional and alter the behaviour and resultant + generated code of the interrupt routine. Multiple attributes may + be used for a single function, with a space seperating each + attribute. + + Valid attributes are ISR_BLOCK, ISR_NOBLOCK, ISR_NAKED and + ISR_ALIASOF(vect). + + \c vector must be one of the interrupt vector names that are + valid for the particular MCU type. +*/ +# define ISR(vector, [attributes]) +#else /* real code */ + +#if (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4) +# define __INTR_ATTRS used, externally_visible +#else /* GCC < 4.1 */ +# define __INTR_ATTRS used +#endif + +#ifdef __cplusplus +# define ISR(vector, ...) \ + extern "C" void vector (void) __attribute__ ((signal,__INTR_ATTRS)) __VA_ARGS__; \ + void vector (void) +#else +# define ISR(vector, ...) \ + void vector (void) __attribute__ ((signal,__INTR_ATTRS)) __VA_ARGS__; \ + void vector (void) +#endif + +#endif /* DOXYGEN */ + +#if defined(__DOXYGEN__) +/** \def SIGNAL(vector) + \ingroup avr_interrupts + + Introduces an interrupt handler function that runs with global interrupts + initially disabled. + + This is the same as the ISR macro without optional attributes. + \deprecated Do not use SIGNAL() in new code. Use ISR() instead. +*/ +# define SIGNAL(vector) +#else /* real code */ + +#ifdef __cplusplus +# define SIGNAL(vector) \ + extern "C" void vector(void) __attribute__ ((signal, __INTR_ATTRS)); \ + void vector (void) +#else +# define SIGNAL(vector) \ + void vector (void) __attribute__ ((signal, __INTR_ATTRS)); \ + void vector (void) +#endif + +#endif /* DOXYGEN */ + +#if defined(__DOXYGEN__) +/** \def EMPTY_INTERRUPT(vector) + \ingroup avr_interrupts + + Defines an empty interrupt handler function. This will not generate + any prolog or epilog code and will only return from the ISR. Do not + define a function body as this will define it for you. + Example: + \code EMPTY_INTERRUPT(ADC_vect);\endcode */ +# define EMPTY_INTERRUPT(vector) +#else /* real code */ + +#ifdef __cplusplus +# define EMPTY_INTERRUPT(vector) \ + extern "C" void vector(void) __attribute__ ((signal,naked,__INTR_ATTRS)); \ + void vector (void) { __asm__ __volatile__ ("reti" ::); } +#else +# define EMPTY_INTERRUPT(vector) \ + void vector (void) __attribute__ ((signal,naked,__INTR_ATTRS)); \ + void vector (void) { __asm__ __volatile__ ("reti" ::); } +#endif + +#endif /* DOXYGEN */ + +#if defined(__DOXYGEN__) +/** \def ISR_ALIAS(vector, target_vector) + \ingroup avr_interrupts + + Aliases a given vector to another one in the same manner as the + ISR_ALIASOF attribute for the ISR() macro. Unlike the ISR_ALIASOF + attribute macro however, this is compatible for all versions of + GCC rather than just GCC version 4.2 onwards. + + \note This macro creates a trampoline function for the aliased + macro. This will result in a two cycle penalty for the aliased + vector compared to the ISR the vector is aliased to, due to the + JMP/RJMP opcode used. + + \deprecated + For new code, the use of ISR(..., ISR_ALIASOF(...)) is + recommended. + + Example: + \code + ISR(INT0_vect) + { + PORTB = 42; + } + + ISR_ALIAS(INT1_vect, INT0_vect); + \endcode + +*/ +# define ISR_ALIAS(vector, target_vector) +#else /* real code */ + +#ifdef __cplusplus +# if defined(__AVR_MEGA__) && __AVR_MEGA__ +# define ISR_ALIAS(vector, tgt) extern "C" void vector (void) \ + __attribute__((signal, naked, __INTR_ATTRS)); \ + void vector (void) { asm volatile ("jmp " __STRINGIFY(tgt) ::); } +# else /* !__AVR_MEGA */ +# define ISR_ALIAS(vector, tgt) extern "C" void vector (void) \ + __attribute__((signal, naked, __INTR_ATTRS)); \ + void vector (void) { asm volatile ("rjmp " __STRINGIFY(tgt) ::); } +# endif /* __AVR_MEGA__ */ +#else /* !__cplusplus */ +# if defined(__AVR_MEGA__) && __AVR_MEGA__ +# define ISR_ALIAS(vector, tgt) void vector (void) \ + __attribute__((signal, naked, __INTR_ATTRS)); \ + void vector (void) { asm volatile ("jmp " __STRINGIFY(tgt) ::); } +# else /* !__AVR_MEGA */ +# define ISR_ALIAS(vector, tgt) void vector (void) \ + __attribute__((signal, naked, __INTR_ATTRS)); \ + void vector (void) { asm volatile ("rjmp " __STRINGIFY(tgt) ::); } +# endif /* __AVR_MEGA__ */ +#endif /* __cplusplus */ + +#endif /* DOXYGEN */ + +#if defined(__DOXYGEN__) +/** \def reti() + \ingroup avr_interrupts + + Returns from an interrupt routine, enabling global interrupts. This should + be the last command executed before leaving an ISR defined with the ISR_NAKED + attribute. + + This macro actually compiles into a single line of assembly, so there is + no function call overhead. +*/ +# define reti() +#else /* !DOXYGEN */ +# define reti() __asm__ __volatile__ ("reti" ::) +#endif /* DOXYGEN */ + +#if defined(__DOXYGEN__) +/** \def BADISR_vect + \ingroup avr_interrupts + + \code #include \endcode + + This is a vector which is aliased to __vector_default, the vector + executed when an ISR fires with no accompanying ISR handler. This + may be used along with the ISR() macro to create a catch-all for + undefined but used ISRs for debugging purposes. +*/ +# define BADISR_vect +#else /* !DOXYGEN */ +# define BADISR_vect __vector_default +#endif /* DOXYGEN */ + +/** \name ISR attributes */ + +#if defined(__DOXYGEN__) +/** \def ISR_BLOCK + \ingroup avr_interrupts + + Identical to an ISR with no attributes specified. Global + interrupts are initially disabled by the AVR hardware when + entering the ISR, without the compiler modifying this state. + + Use this attribute in the attributes parameter of the ISR macro. +*/ +# define ISR_BLOCK + +/** \def ISR_NOBLOCK + \ingroup avr_interrupts + + ISR runs with global interrupts initially enabled. The interrupt + enable flag is activated by the compiler as early as possible + within the ISR to ensure minimal processing delay for nested + interrupts. + + This may be used to create nested ISRs, however care should be + taken to avoid stack overflows, or to avoid infinitely entering + the ISR for those cases where the AVR hardware does not clear the + respective interrupt flag before entering the ISR. + + Use this attribute in the attributes parameter of the ISR macro. +*/ +# define ISR_NOBLOCK + +/** \def ISR_NAKED + \ingroup avr_interrupts + + ISR is created with no prologue or epilogue code. The user code is + responsible for preservation of the machine state including the + SREG register, as well as placing a reti() at the end of the + interrupt routine. + + Use this attribute in the attributes parameter of the ISR macro. +*/ +# define ISR_NAKED + +/** \def ISR_ALIASOF(target_vector) + \ingroup avr_interrupts + + The ISR is linked to another ISR, specified by the vect parameter. + This is compatible with GCC 4.2 and greater only. + + Use this attribute in the attributes parameter of the ISR macro. +*/ +# define ISR_ALIASOF(target_vector) +#else /* !DOXYGEN */ +# define ISR_BLOCK +# define ISR_NOBLOCK __attribute__((interrupt)) +# define ISR_NAKED __attribute__((naked)) +# define ISR_ALIASOF(v) __attribute__((alias(__STRINGIFY(v)))) +#endif /* DOXYGEN */ + +/* \@} */ + +#endif diff --git a/hardware/tools/avr/avr/include/avr/io.h b/hardware/tools/avr/avr/include/avr/io.h new file mode 100644 index 0000000000000000000000000000000000000000..30b3fa671b548c51e6df752add642031b5342854 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/io.h @@ -0,0 +1,731 @@ +/* Copyright (c) 2002,2003,2005,2006,2007 Marek Michalkiewicz, Joerg Wunsch + Copyright (c) 2007 Eric B. Weddington + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +/** \file */ +/** \defgroup avr_io : AVR device-specific IO definitions + \code #include \endcode + + This header file includes the apropriate IO definitions for the + device that has been specified by the -mmcu= compiler + command-line switch. This is done by diverting to the appropriate + file <avr/ioXXXX.h> which should + never be included directly. Some register names common to all + AVR devices are defined directly within <avr/common.h>, + which is included in <avr/io.h>, + but most of the details come from the respective include file. + + Note that this file always includes the following files: + \code + #include + #include + #include + #include + \endcode + See \ref avr_sfr for more details about that header file. + + Included are definitions of the IO register set and their + respective bit values as specified in the Atmel documentation. + Note that inconsistencies in naming conventions, + so even identical functions sometimes get different names on + different devices. + + Also included are the specific names useable for interrupt + function definitions as documented + \ref avr_signames "here". + + Finally, the following macros are defined: + + - \b RAMEND +
+ The last on-chip RAM address. +
+ - \b XRAMEND +
+ The last possible RAM location that is addressable. This is equal to + RAMEND for devices that do not allow for external RAM. For devices + that allow external RAM, this will be larger than RAMEND. +
+ - \b E2END +
+ The last EEPROM address. +
+ - \b FLASHEND +
+ The last byte address in the Flash program space. +
+ - \b SPM_PAGESIZE +
+ For devices with bootloader support, the flash pagesize + (in bytes) to be used for the \c SPM instruction. + - \b E2PAGESIZE +
+ The size of the EEPROM page. + +*/ + +#ifndef _AVR_IO_H_ +#define _AVR_IO_H_ + +#include + +#if defined (__AVR_AT94K__) +# include +#elif defined (__AVR_AT43USB320__) +# include +#elif defined (__AVR_AT43USB355__) +# include +#elif defined (__AVR_AT76C711__) +# include +#elif defined (__AVR_AT86RF401__) +# include +#elif defined (__AVR_AT90PWM1__) +# include +#elif defined (__AVR_AT90PWM2__) +# include +#elif defined (__AVR_AT90PWM2B__) +# include +#elif defined (__AVR_AT90PWM3__) +# include +#elif defined (__AVR_AT90PWM3B__) +# include +#elif defined (__AVR_AT90PWM216__) +# include +#elif defined (__AVR_AT90PWM316__) +# include +#elif defined (__AVR_AT90PWM161__) +# include +#elif defined (__AVR_AT90PWM81__) +# include +#elif defined (__AVR_ATmega8U2__) +# include +#elif defined (__AVR_ATmega16M1__) +# include +#elif defined (__AVR_ATmega16U2__) +# include +#elif defined (__AVR_ATmega16U4__) +# include +#elif defined (__AVR_ATmega32C1__) +# include +#elif defined (__AVR_ATmega32M1__) +# include +#elif defined (__AVR_ATmega32U2__) +# include +#elif defined (__AVR_ATmega32U4__) +# include +#elif defined (__AVR_ATmega32U6__) +# include +#elif defined (__AVR_ATmega64C1__) +# include +#elif defined (__AVR_ATmega64M1__) +# include +#elif defined (__AVR_ATmega128__) +# include +#elif defined (__AVR_ATmega128A__) +# include +#elif defined (__AVR_ATmega1280__) +# include +#elif defined (__AVR_ATmega1281__) +# include +#elif defined (__AVR_ATmega1284__) +# include +#elif defined (__AVR_ATmega1284P__) +# include +#elif defined (__AVR_ATmega128RFA1__) +# include +#elif defined (__AVR_ATmega1284RFR2__) +# include +#elif defined (__AVR_ATmega128RFR2__) +# include +#elif defined (__AVR_ATmega2564RFR2__) +# include +#elif defined (__AVR_ATmega256RFR2__) +# include +#elif defined (__AVR_ATmega2560__) +# include +#elif defined (__AVR_ATmega2561__) +# include +#elif defined (__AVR_AT90CAN32__) +# include +#elif defined (__AVR_AT90CAN64__) +# include +#elif defined (__AVR_AT90CAN128__) +# include +#elif defined (__AVR_AT90USB82__) +# include +#elif defined (__AVR_AT90USB162__) +# include +#elif defined (__AVR_AT90USB646__) +# include +#elif defined (__AVR_AT90USB647__) +# include +#elif defined (__AVR_AT90USB1286__) +# include +#elif defined (__AVR_AT90USB1287__) +# include +#elif defined (__AVR_ATmega644RFR2__) +# include +#elif defined (__AVR_ATmega64RFR2__) +# include +#elif defined (__AVR_ATmega64__) +# include +#elif defined (__AVR_ATmega64A__) +# include +#elif defined (__AVR_ATmega640__) +# include +#elif defined (__AVR_ATmega644__) +# include +#elif defined (__AVR_ATmega644A__) +# include +#elif defined (__AVR_ATmega644P__) +# include +#elif defined (__AVR_ATmega644PA__) +# include +#elif defined (__AVR_ATmega645__) +# include +#elif (defined __AVR_ATmega645A__) +#include +#elif (defined __AVR_ATmega645P__) +#include +#elif defined (__AVR_ATmega6450__) +# include +#elif (defined __AVR_ATmega6450A__) +#include +#elif (defined __AVR_ATmega6450P__) +#include +#elif defined (__AVR_ATmega649__) +# include +#elif (defined __AVR_ATmega649A__) +#include +#elif defined (__AVR_ATmega6490__) +# include +#elif (defined __AVR_ATmega6490A__) +#include +#elif (defined __AVR_ATmega6490P__) +#include +#elif defined (__AVR_ATmega649P__) +# include +#elif defined (__AVR_ATmega64HVE__) +# include +#elif defined (__AVR_ATmega64HVE2__) +# include +#elif defined (__AVR_ATmega103__) +# include +#elif defined (__AVR_ATmega32__) +# include +#elif defined (__AVR_ATmega32A__) +# include +#elif defined (__AVR_ATmega323__) +# include +#elif defined (__AVR_ATmega324P__) +# include +#elif (defined __AVR_ATmega324A__) +#include +#elif defined (__AVR_ATmega324PA__) +# include +#elif defined (__AVR_ATmega325__) +# include +#elif (defined __AVR_ATmega325A__) +#include +#elif defined (__AVR_ATmega325P__) +# include +#elif defined (__AVR_ATmega325PA__) +# include +#elif defined (__AVR_ATmega3250__) +# include +#elif (defined __AVR_ATmega3250A__) +#include +#elif defined (__AVR_ATmega3250P__) +# include +#elif defined (__AVR_ATmega3250PA__) +# include +#elif defined (__AVR_ATmega328P__) +# include +#elif (defined __AVR_ATmega328__) +#include +#elif defined (__AVR_ATmega329__) +# include +#elif (defined __AVR_ATmega329A__) +#include +#elif defined (__AVR_ATmega329P__) +# include +#elif (defined __AVR_ATmega329PA__) +#include +#elif (defined __AVR_ATmega3290PA__) +#include +#elif defined (__AVR_ATmega3290__) +# include +#elif (defined __AVR_ATmega3290A__) +#include +#elif defined (__AVR_ATmega3290P__) +# include +#elif defined (__AVR_ATmega32HVB__) +# include +#elif defined (__AVR_ATmega32HVBREVB__) +# include +#elif defined (__AVR_ATmega406__) +# include +#elif defined (__AVR_ATmega16__) +# include +#elif defined (__AVR_ATmega16A__) +# include +#elif defined (__AVR_ATmega161__) +# include +#elif defined (__AVR_ATmega162__) +# include +#elif defined (__AVR_ATmega163__) +# include +#elif defined (__AVR_ATmega164P__) +# include +#elif (defined __AVR_ATmega164A__) +#include +#elif defined (__AVR_ATmega164PA__) +# include +#elif defined (__AVR_ATmega165__) +# include +#elif defined (__AVR_ATmega165A__) +# include +#elif defined (__AVR_ATmega165P__) +# include +#elif defined (__AVR_ATmega165PA__) +# include +#elif defined (__AVR_ATmega168__) +# include +#elif defined (__AVR_ATmega168A__) +# include +#elif defined (__AVR_ATmega168P__) +# include +#elif defined (__AVR_ATmega168PA__) +# include +#elif defined (__AVR_ATmega168PB__) +# include +#elif defined (__AVR_ATmega169__) +# include +#elif (defined __AVR_ATmega169A__) +#include +#elif defined (__AVR_ATmega169P__) +# include +#elif defined (__AVR_ATmega169PA__) +# include +#elif defined (__AVR_ATmega8HVA__) +# include +#elif defined (__AVR_ATmega16HVA__) +# include +#elif defined (__AVR_ATmega16HVA2__) +# include +#elif defined (__AVR_ATmega16HVB__) +# include +#elif defined (__AVR_ATmega16HVBREVB__) +# include +#elif defined (__AVR_ATmega8__) +# include +#elif defined (__AVR_ATmega8A__) +# include +#elif defined (__AVR_ATmega48__) +# include +#elif defined (__AVR_ATmega48A__) +# include +#elif defined (__AVR_ATmega48PA__) +# include +#elif defined (__AVR_ATmega48PB__) +# include +#elif defined (__AVR_ATmega48P__) +# include +#elif defined (__AVR_ATmega88__) +# include +#elif defined (__AVR_ATmega88A__) +# include +#elif defined (__AVR_ATmega88P__) +# include +#elif defined (__AVR_ATmega88PA__) +# include +#elif defined (__AVR_ATmega88PB__) +# include +#elif defined (__AVR_ATmega8515__) +# include +#elif defined (__AVR_ATmega8535__) +# include +#elif defined (__AVR_AT90S8535__) +# include +#elif defined (__AVR_AT90C8534__) +# include +#elif defined (__AVR_AT90S8515__) +# include +#elif defined (__AVR_AT90S4434__) +# include +#elif defined (__AVR_AT90S4433__) +# include +#elif defined (__AVR_AT90S4414__) +# include +#elif defined (__AVR_ATtiny22__) +# include +#elif defined (__AVR_ATtiny26__) +# include +#elif defined (__AVR_AT90S2343__) +# include +#elif defined (__AVR_AT90S2333__) +# include +#elif defined (__AVR_AT90S2323__) +# include +#elif defined (__AVR_AT90S2313__) +# include +#elif defined (__AVR_ATtiny4__) +# include +#elif defined (__AVR_ATtiny5__) +# include +#elif defined (__AVR_ATtiny9__) +# include +#elif defined (__AVR_ATtiny10__) +# include +#elif defined (__AVR_ATtiny20__) +# include +#elif defined (__AVR_ATtiny40__) +# include +#elif defined (__AVR_ATtiny2313__) +# include +#elif defined (__AVR_ATtiny2313A__) +# include +#elif defined (__AVR_ATtiny13__) +# include +#elif defined (__AVR_ATtiny13A__) +# include +#elif defined (__AVR_ATtiny25__) +# include +#elif defined (__AVR_ATtiny4313__) +# include +#elif defined (__AVR_ATtiny45__) +# include +#elif defined (__AVR_ATtiny85__) +# include +#elif defined (__AVR_ATtiny24__) +# include +#elif defined (__AVR_ATtiny24A__) +# include +#elif defined (__AVR_ATtiny44__) +# include +#elif defined (__AVR_ATtiny44A__) +# include +#elif defined (__AVR_ATtiny441__) +# include +#elif defined (__AVR_ATtiny84__) +# include +#elif defined (__AVR_ATtiny84A__) +# include +#elif defined (__AVR_ATtiny841__) +# include +#elif defined (__AVR_ATtiny261__) +# include +#elif defined (__AVR_ATtiny261A__) +# include +#elif defined (__AVR_ATtiny461__) +# include +#elif defined (__AVR_ATtiny461A__) +# include +#elif defined (__AVR_ATtiny861__) +# include +#elif defined (__AVR_ATtiny861A__) +# include +#elif defined (__AVR_ATtiny43U__) +# include +#elif defined (__AVR_ATtiny48__) +# include +#elif defined (__AVR_ATtiny88__) +# include +#elif defined (__AVR_ATtiny828__) +# include +#elif defined (__AVR_ATtiny87__) +# include +#elif defined (__AVR_ATtiny167__) +# include +#elif defined (__AVR_ATtiny1634__) +# include +#elif defined (__AVR_AT90SCR100__) +# include +#elif defined (__AVR_ATxmega8E5__) +# include +#elif defined (__AVR_ATxmega16A4__) +# include +#elif defined (__AVR_ATxmega16A4U__) +# include +#elif defined (__AVR_ATxmega16C4__) +# include +#elif defined (__AVR_ATxmega16D4__) +# include +#elif defined (__AVR_ATxmega16E5__) +# include +#elif defined (__AVR_ATxmega32A4__) +# include +#elif defined (__AVR_ATxmega32A4U__) +# include +#elif defined (__AVR_ATxmega32C3__) +# include +#elif defined (__AVR_ATxmega32C4__) +# include +#elif defined (__AVR_ATxmega32D3__) +# include +#elif defined (__AVR_ATxmega32D4__) +# include +#elif defined (__AVR_ATxmega32E5__) +# include +#elif defined (__AVR_ATxmega64A1__) +# include +#elif defined (__AVR_ATxmega64A1U__) +# include +#elif defined (__AVR_ATxmega64A3__) +# include +#elif defined (__AVR_ATxmega64A3U__) +# include +#elif defined (__AVR_ATxmega64A4U__) +# include +#elif defined (__AVR_ATxmega64B1__) +# include +#elif defined (__AVR_ATxmega64B3__) +# include +#elif defined (__AVR_ATxmega64C3__) +# include +#elif defined (__AVR_ATxmega64D3__) +# include +#elif defined (__AVR_ATxmega64D4__) +# include +#elif defined (__AVR_ATxmega128A1__) +# include +#elif defined (__AVR_ATxmega128A1U__) +# include +#elif defined (__AVR_ATxmega128A4U__) +# include +#elif defined (__AVR_ATxmega128A3__) +# include +#elif defined (__AVR_ATxmega128A3U__) +# include +#elif defined (__AVR_ATxmega128B1__) +# include +#elif defined (__AVR_ATxmega128B3__) +# include +#elif defined (__AVR_ATxmega128C3__) +# include +#elif defined (__AVR_ATxmega128D3__) +# include +#elif defined (__AVR_ATxmega128D4__) +# include +#elif defined (__AVR_ATxmega192A3__) +# include +#elif defined (__AVR_ATxmega192A3U__) +# include +#elif defined (__AVR_ATxmega192C3__) +# include +#elif defined (__AVR_ATxmega192D3__) +# include +#elif defined (__AVR_ATxmega256A3__) +# include +#elif defined (__AVR_ATxmega256A3U__) +# include +#elif defined (__AVR_ATxmega256A3B__) +# include +#elif defined (__AVR_ATxmega256A3BU__) +# include +#elif defined (__AVR_ATxmega256C3__) +# include +#elif defined (__AVR_ATxmega256D3__) +# include +#elif defined (__AVR_ATxmega384C3__) +# include +#elif defined (__AVR_ATxmega384D3__) +# include +#elif defined (__AVR_ATA5702M322__) +# include +#elif defined (__AVR_ATA5782__) +# include +#elif defined (__AVR_ATA5790__) +# include +#elif defined (__AVR_ATA5790N__) +# include +#elif defined (__AVR_ATA5791__) +# include +#elif defined (__AVR_ATA5831__) +# include +#elif defined (__AVR_ATA5272__) +# include +#elif defined (__AVR_ATA5505__) +# include +#elif defined (__AVR_ATA5795__) +# include +#elif defined (__AVR_ATA6285__) +# include +#elif defined (__AVR_ATA6286__) +# include +#elif defined (__AVR_ATA6289__) +# include +#elif defined (__AVR_ATA6612C__) +# include +#elif defined (__AVR_ATA6613C__) +# include +#elif defined (__AVR_ATA6614Q__) +# include +#elif defined (__AVR_ATA6616C__) +# include +#elif defined (__AVR_ATA6617C__) +# include +#elif defined (__AVR_ATA664251__) +# include +#elif defined (__AVR_ATA8210__) +# include +#elif defined (__AVR_ATA8510__) +# include +/* avr1: the following only supported for assembler programs */ +#elif defined (__AVR_ATtiny28__) +# include +#elif defined (__AVR_AT90S1200__) +# include +#elif defined (__AVR_ATtiny15__) +# include +#elif defined (__AVR_ATtiny12__) +# include +#elif defined (__AVR_ATtiny11__) +# include +#elif defined (__AVR_M3000__) +# include +#elif defined (__AVR_AVR128DA64__) +# include +#elif defined (__AVR_AVR128DA48__) +# include +#elif defined (__AVR_AVR128DA32__) +# include +#elif defined (__AVR_AVR128DA28__) +# include +#elif defined (__AVR_ATtiny817__) +# include +#elif defined (__AVR_ATtiny816__) +# include +#elif defined (__AVR_ATtiny814__) +# include +#elif defined (__AVR_ATtiny807__) +# include +#elif defined (__AVR_ATtiny806__) +# include +#elif defined (__AVR_ATtiny804__) +# include +#elif defined (__AVR_ATtiny417__) +# include +#elif defined (__AVR_ATtiny416__) +# include +#elif defined (__AVR_ATtiny414__) +# include +#elif defined (__AVR_ATtiny412__) +# include +#elif defined (__AVR_ATtiny406__) +# include +#elif defined (__AVR_ATtiny404__) +# include +#elif defined (__AVR_ATtiny402__) +# include +#elif defined (__AVR_ATtiny3217__) +# include +#elif defined (__AVR_ATtiny3216__) +# include +#elif defined (__AVR_ATtiny214__) +# include +#elif defined (__AVR_ATtiny212__) +# include +#elif defined (__AVR_ATtiny204__) +# include +#elif defined (__AVR_ATtiny202__) +# include +#elif defined (__AVR_ATtiny1627__) +# include +#elif defined (__AVR_ATtiny1626__) +# include +#elif defined (__AVR_ATtiny1624__) +# include +#elif defined (__AVR_ATtiny1617__) +# include +#elif defined (__AVR_ATtiny1616__) +# include +#elif defined (__AVR_ATtiny1614__) +# include +#elif defined (__AVR_ATtiny1607__) +# include +#elif defined (__AVR_ATtiny1606__) +# include +#elif defined (__AVR_ATtiny1604__) +# include +#elif defined (__AVR_ATtiny104__) +# include +#elif defined (__AVR_ATtiny102__) +# include +#elif defined (__AVR_ATmega809__) +# include +#elif defined (__AVR_ATmega808__) +# include +#elif defined (__AVR_ATmega4809__) +# include +#elif defined (__AVR_ATmega4808__) +# include +#elif defined (__AVR_ATmega328PB__) +# include +#elif defined (__AVR_ATmega324PB__) +# include +#elif defined (__AVR_ATmega3209__) +# include +#elif defined (__AVR_ATmega3208__) +# include +#elif defined (__AVR_ATmega1609__) +# include +#elif defined (__AVR_ATmega1608__) +# include +#elif defined (__AVR_DEV_LIB_NAME__) +# define __concat__(a,b) a##b +# define __header1__(a,b) __concat__(a,b) +# define __AVR_DEVICE_HEADER__ +# include __AVR_DEVICE_HEADER__ +#else +# if !defined(__COMPILING_AVR_LIBC__) +# warning "device type not defined" +# endif +#endif + +#include + +#include + +#include + +#if __AVR_ARCH__ >= 100 +# include +#endif + +/* Include fuse.h after individual IO header files. */ +#include + +/* Include lock.h after individual IO header files. */ +#include + +#endif /* _AVR_IO_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/io1200.h b/hardware/tools/avr/avr/include/avr/io1200.h new file mode 100644 index 0000000000000000000000000000000000000000..aeaf7d6d9c57d4e2ff6b1bfc238490acf3ee43ae --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/io1200.h @@ -0,0 +1,274 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: io1200.h 2225 2011-03-02 16:27:26Z arcanum $ */ + +/* avr/io1200.h - definitions for AT90S1200 */ + +#ifndef _AVR_IO1200_H_ +#define _AVR_IO1200_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io1200.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef __ASSEMBLER__ +# warning "MCU not supported by the C compiler" +#endif + +/* I/O registers */ + +/* 0x00..0x07 reserved */ + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) + +/* 0x09..0x0F reserved */ + +#define PIND _SFR_IO8(0x10) +#define DDRD _SFR_IO8(0x11) +#define PORTD _SFR_IO8(0x12) + +/* 0x13..0x15 reserved */ + +#define PINB _SFR_IO8(0x16) +#define DDRB _SFR_IO8(0x17) +#define PORTB _SFR_IO8(0x18) + +/* 0x19..0x1B reserved */ + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO8(0x1E) +#define EEARL _SFR_IO8(0x1E) + +/* 0x1F..0x20 reserved */ + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* 0x22..0x31 reserved */ + +#define TCNT0 _SFR_IO8(0x32) +#define TCCR0 _SFR_IO8(0x33) + +/* 0x34 reserved */ + +#define MCUCR _SFR_IO8(0x35) + +/* 0x36..0x37 reserved */ + +/* Timer/Counter Interrupt Flag Register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK Register */ +#define TIMSK _SFR_IO8(0x39) + +/* 0x3A reserved */ + +#define GIMSK _SFR_IO8(0x3B) + +/* 0x3C..0x3E reserved */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 2 +#define TIMER0_OVF_vect _VECTOR(2) +#define SIG_OVERFLOW0 _VECTOR(2) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 3 +#define ANA_COMP_vect _VECTOR(3) +#define SIG_COMPARATOR _VECTOR(3) + +#define _VECTORS_SIZE 8 + +/* Bit numbers */ + +/* GIMSK */ +#define INT0 6 + +/* TIMSK */ +#define TOIE0 1 + +/* TIFR */ +#define TOV0 1 + +/* MCUCR */ +#define SE 5 +#define SM 4 +#define ISC01 1 +#define ISC00 0 + +/* TCCR0 */ +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* WDTCR */ +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* EECR */ +#undef EEMWE + +/* + PB7 = SCK + PB6 = MISO + PB5 = MOSI + PB1 = AIN1 + PB0 = AIN0 + */ + +/* PORTB */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* DDRB */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* PINB */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* PORTD */ +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* DDRD */ +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* PIND */ +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* ACSR */ +#define ACD 7 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIS1 1 +#define ACIS0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +#undef ZH + +#define RAMSTART 0x60 +/* Last memory addresses */ +#define RAMEND 0x1F +#define XRAMEND 0x0 +#define E2END 0x3F +#define E2PAGESIZE 0 +#define FLASHEND 0x3FF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 1 + +/* Low Fuse Byte */ +#define FUSE_RCEN (unsigned char)~_BV(0) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define LFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x90 +#define SIGNATURE_2 0x01 + + +#endif /* _AVR_IO1200_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/io2313.h b/hardware/tools/avr/avr/include/avr/io2313.h new file mode 100644 index 0000000000000000000000000000000000000000..a469f2035fc3fa11a813f07a963c82f9ccd7b4e6 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/io2313.h @@ -0,0 +1,385 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: io2313.h 2225 2011-03-02 16:27:26Z arcanum $ */ + +/* avr/io2313.h - definitions for AT90S2313 */ + +#ifndef _AVR_IO2313_H_ +#define _AVR_IO2313_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io2313.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) + +/* UART Baud Rate Register */ +#define UBRR _SFR_IO8(0x09) + +/* UART Control Register */ +#define UCR _SFR_IO8(0x0A) + +/* UART Status Register */ +#define USR _SFR_IO8(0x0B) + +/* UART I/O Data Register */ +#define UDR _SFR_IO8(0x0C) + +/* Input Pins, Port D */ +#define PIND _SFR_IO8(0x10) + +/* Data Direction Register, Port D */ +#define DDRD _SFR_IO8(0x11) + +/* Data Register, Port D */ +#define PORTD _SFR_IO8(0x12) + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO8(0x1E) +#define EEARL _SFR_IO8(0x1E) + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* T/C 1 Input Capture Register */ +#define ICR1 _SFR_IO16(0x24) +#define ICR1L _SFR_IO8(0x24) +#define ICR1H _SFR_IO8(0x25) + +/* Output Compare Register 1 */ +#define OCR1 _SFR_IO16(0x2A) +#define OCR1L _SFR_IO8(0x2A) +#define OCR1H _SFR_IO8(0x2B) +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Timer/Counter 1 */ +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +/* Timer/Counter 1 Control and Status Register */ +#define TCCR1B _SFR_IO8(0x2E) + +/* Timer/Counter 1 Control Register */ +#define TCCR1A _SFR_IO8(0x2F) + +/* Timer/Counter 0 */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter 0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* Timer/Counter Interrupt Flag register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK register */ +#define TIMSK _SFR_IO8(0x39) + +/* General Interrupt Flag Register */ +#define GIFR _SFR_IO8(0x3A) + +/* General Interrupt MaSK register */ +#define GIMSK _SFR_IO8(0x3B) + +/* 0x3C..0x3D SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt Request 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt Request 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT1_vect_num 3 +#define TIMER1_CAPT1_vect _VECTOR(3) +#define SIG_INPUT_CAPTURE1 _VECTOR(3) + +/* Timer/Counter1 Compare Match */ +#define TIMER1_COMP1_vect_num 4 +#define TIMER1_COMP1_vect _VECTOR(4) +#define SIG_OUTPUT_COMPARE1A _VECTOR(4) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF1_vect_num 5 +#define TIMER1_OVF1_vect _VECTOR(5) +#define SIG_OVERFLOW1 _VECTOR(5) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF0_vect_num 6 +#define TIMER0_OVF0_vect _VECTOR(6) +#define SIG_OVERFLOW0 _VECTOR(6) + +/* UART, Rx Complete */ +#define UART_RX_vect_num 7 +#define UART_RX_vect _VECTOR(7) +#define SIG_UART_RECV _VECTOR(7) + +/* UART Data Register Empty */ +#define UART_UDRE_vect_num 8 +#define UART_UDRE_vect _VECTOR(8) +#define SIG_UART_DATA _VECTOR(8) + +/* UART, Tx Complete */ +#define UART_TX_vect_num 9 +#define UART_TX_vect _VECTOR(9) +#define SIG_UART_TRANS _VECTOR(9) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 10 +#define ANA_COMP_vect _VECTOR(10) +#define SIG_COMPARATOR _VECTOR(10) + +#define _VECTORS_SIZE 22 + +/* + * The Register Bit names are represented by their bit number (0-7). + */ + +/* General Interrupt MaSK register */ +#define INT1 7 +#define INT0 6 + +/* General Interrupt Flag Register */ +#define INTF1 7 +#define INTF0 6 + +/* Timer/Counter Interrupt MaSK register */ +#define TOIE1 7 +#define OCIE1A 6 +#define TICIE 3 /* old name */ +#define TICIE1 3 +#define TOIE0 1 + +/* Timer/Counter Interrupt Flag register */ +#define TOV1 7 +#define OCF1A 6 +#define ICF1 3 +#define TOV0 1 + +/* MCU general Control Register */ +#define SE 5 +#define SM 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/* Timer/Counter 0 Control Register */ +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* Timer/Counter 1 Control Register */ +#define COM1A1 7 +#define COM1A0 6 +#define PWM11 1 +#define PWM10 0 + +/* Timer/Counter 1 Control and Status Register */ +#define ICNC1 7 +#define ICES1 6 +#define CTC1 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* Watchdog Timer Control Register */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* EEPROM Control Register */ +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Data Register, Port B */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Data Direction Register, Port B */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Input Pins, Port B */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* Data Register, Port D */ +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* Data Direction Register, Port D */ +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* Input Pins, Port D */ +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* UART Status Register */ +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 + +/* UART Control Register */ +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define CHR9 2 +#define RXB8 1 +#define TXB8 0 + +/* Analog Comparator Control and Status Register */ +#define ACD 7 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define RAMSTART 0x60 +#define RAMEND 0xDF +#define XRAMEND RAMEND +#define E2END 0x7F +#define E2PAGESIZE 0 +#define FLASHEND 0x07FF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 1 + +/* Low Fuse Byte */ +#define FUSE_FSTRT (unsigned char)~_BV(0) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define LFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x91 +#define SIGNATURE_2 0x01 + +#define SLEEP_MODE_IDLE 0 +#define SLEEP_MODE_PWR_DOWN _BV(SM) + + +#endif /* _AVR_IO2313_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/io2323.h b/hardware/tools/avr/avr/include/avr/io2323.h new file mode 100644 index 0000000000000000000000000000000000000000..cd1311f3404e87abcc5a506d5c0a5f79023a614c --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/io2323.h @@ -0,0 +1,210 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: io2323.h 2225 2011-03-02 16:27:26Z arcanum $ */ + +/* avr/io2323.h - definitions for AT90S2323 */ + +#ifndef _AVR_IO2323_H_ +#define _AVR_IO2323_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io2323.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO8(0x1E) +#define EEARL _SFR_IO8(0x1E) + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* Timer/Counter 0 */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter 0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU Status Register */ +#define MCUSR _SFR_IO8(0x34) + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* Timer/Counter Interrupt Flag register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK register */ +#define TIMSK _SFR_IO8(0x39) + +/* General Interrupt Flag register */ +#define GIFR _SFR_IO8(0x3A) + +/* General Interrupt MaSK register */ +#define GIMSK _SFR_IO8(0x3B) + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF0_vect_num 2 +#define TIMER0_OVF0_vect _VECTOR(2) +#define SIG_OVERFLOW0 _VECTOR(2) + +#define _VECTORS_SIZE 6 + +/* + The Register Bit names are represented by their bit number (0-7). + */ + +/* General Interrupt MaSK register */ +#define INT0 6 +#define INTF0 6 + +/* General Interrupt Flag Register */ +#define TOIE0 1 +#define TOV0 1 + +/* MCU general Control Register */ +#define SE 5 +#define SM 4 +#define ISC01 1 +#define ISC00 0 + +/* Timer/Counter 0 Control Register */ +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* Watchdog Timer Control Register */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* + PB2 = SCK/T0 + PB1 = MISO/INT0 + PB0 = MOSI + */ + +/* Data Register, Port B */ +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Data Direction Register, Port B */ +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Input Pins, Port B */ +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define RAMSTART 0x60 +#define RAMEND 0xDF +#define XRAMEND RAMEND +#define E2END 0x7F +#define E2PAGESIZE 0 +#define FLASHEND 0x07FF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 1 + +/* Low Fuse Byte */ +#define FUSE_FSTRT (unsigned char)~_BV(0) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define LFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x91 +#define SIGNATURE_2 0x02 + +#define SLEEP_MODE_IDLE 0 +#define SLEEP_MODE_PWR_DOWN _BV(SM) + + +#endif /* _AVR_IO2323_H_ */ + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x91 +#define SIGNATURE_2 0x02 + diff --git a/hardware/tools/avr/avr/include/avr/io2333.h b/hardware/tools/avr/avr/include/avr/io2333.h new file mode 100644 index 0000000000000000000000000000000000000000..7dccf429bcb515d6eec0bb3449f115908ea31e26 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/io2333.h @@ -0,0 +1,461 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: io2333.h 2225 2011-03-02 16:27:26Z arcanum $ */ + +/* avr/io2333.h - definitions for AT90S2333 */ + +#ifndef _AVR_IO2333_H_ +#define _AVR_IO2333_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io2333.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* UART Baud Rate Register high */ +#define UBRRH _SFR_IO8(0x03) + +/* ADC Data register */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) + +/* ADC Control and Status Register */ +#define ADCSR _SFR_IO8(0x06) + +/* ADC MUX */ +#define ADMUX _SFR_IO8(0x07) + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) + +/* UART Baud Rate Register */ +#define UBRR _SFR_IO8(0x09) + +/* UART Control/Status Registers */ +#define UCSRB _SFR_IO8(0x0A) +#define UCSRA _SFR_IO8(0x0B) + +/* UART I/O Data Register */ +#define UDR _SFR_IO8(0x0C) + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x0D) + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x0E) + +/* SPI I/O Data Register */ +#define SPDR _SFR_IO8(0x0F) + +/* Input Pins, Port D */ +#define PIND _SFR_IO8(0x10) + +/* Data Direction Register, Port D */ +#define DDRD _SFR_IO8(0x11) + +/* Data Register, Port D */ +#define PORTD _SFR_IO8(0x12) + +/* Input Pins, Port C */ +#define PINC _SFR_IO8(0x13) + +/* Data Direction Register, Port C */ +#define DDRC _SFR_IO8(0x14) + +/* Data Register, Port C */ +#define PORTC _SFR_IO8(0x15) + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO8(0x1E) +#define EEARL _SFR_IO8(0x1E) + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* T/C 1 Input Capture Register */ +#define ICR1 _SFR_IO16(0x26) +#define ICR1L _SFR_IO8(0x26) +#define ICR1H _SFR_IO8(0x27) + +/* Timer/Counter1 Output Compare Register A */ +#define OCR1 _SFR_IO16(0x2A) +#define OCR1L _SFR_IO8(0x2A) +#define OCR1H _SFR_IO8(0x2B) + +/* Timer/Counter 1 */ +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +/* Timer/Counter 1 Control and Status Register */ +#define TCCR1B _SFR_IO8(0x2E) + +/* Timer/Counter 1 Control Register */ +#define TCCR1A _SFR_IO8(0x2F) + +/* Timer/Counter 0 */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter 0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU general Status Register */ +#define MCUSR _SFR_IO8(0x34) + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* Timer/Counter Interrupt Flag register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK register */ +#define TIMSK _SFR_IO8(0x39) + +/* General Interrupt Flag Register */ +#define GIFR _SFR_IO8(0x3A) + +/* General Interrupt MaSK register */ +#define GIMSK _SFR_IO8(0x3B) + +/* Interrupt vectors */ + +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* Timer/Counter Capture Event */ +#define TIMER1_CAPT_vect_num 3 +#define TIMER1_CAPT_vect _VECTOR(3) +#define SIG_INPUT_CAPTURE1 _VECTOR(3) + +/* Timer/Counter1 Compare Match */ +#define TIMER1_COMP_vect_num 4 +#define TIMER1_COMP_vect _VECTOR(4) +#define SIG_OUTPUT_COMPARE1A _VECTOR(4) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 5 +#define TIMER1_OVF_vect _VECTOR(5) +#define SIG_OVERFLOW1 _VECTOR(5) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 6 +#define TIMER0_OVF_vect _VECTOR(6) +#define SIG_OVERFLOW0 _VECTOR(6) + +/* Serial Transfer Complete */ +#define SPI_STC_vect_num 7 +#define SPI_STC_vect _VECTOR(7) +#define SIG_SPI _VECTOR(7) + +/* UART, Rx Complete */ +#define UART_RX_vect_num 8 +#define UART_RX_vect _VECTOR(8) +#define SIG_UART_RECV _VECTOR(8) + +/* UART Data Register Empty */ +#define UART_UDRE_vect_num 9 +#define UART_UDRE_vect _VECTOR(9) +#define SIG_UART_DATA _VECTOR(9) + +/* UART, Tx Complete */ +#define UART_TX_vect_num 10 +#define UART_TX_vect _VECTOR(10) +#define SIG_UART_TRANS _VECTOR(10) + +/* ADC Conversion Complete */ +#define ADC_vect_num 11 +#define ADC_vect _VECTOR(11) +#define SIG_ADC _VECTOR(11) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 12 +#define EE_RDY_vect _VECTOR(12) +#define SIG_EEPROM_READY _VECTOR(12) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 13 +#define ANA_COMP_vect _VECTOR(13) +#define SIG_COMPARATOR _VECTOR(13) + +#define _VECTORS_SIZE 28 + +/* + The Register Bit names are represented by their bit number (0-7). +*/ + +/* MCU general Status Register */ +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +/* General Interrupt MaSK register */ +#define INT1 7 +#define INT0 6 + +/* General Interrupt Flag Register */ +#define INTF1 7 +#define INTF0 6 + +/* Timer/Counter Interrupt MaSK register */ +#define TOIE1 7 +#define OCIE1 6 +#define TICIE1 3 +#define TOIE0 1 + +/* Timer/Counter Interrupt Flag register */ +#define TOV1 7 +#define OCF1 6 +#define ICF1 3 +#define TOV0 1 + +/* MCU general Control Register */ +#define SE 5 +#define SM 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/* Timer/Counter 0 Control Register */ +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* Timer/Counter 1 Control Register */ +#define COM11 7 +#define COM10 6 +#define PWM11 1 +#define PWM10 0 + +/* Timer/Counter 1 Control and Status Register */ +#define ICNC1 7 +#define ICES1 6 +#define CTC1 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* Watchdog Timer Control Register */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* SPI Control Register */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* SPI Status Register */ +#define SPIF 7 +#define WCOL 6 + +/* UART Status Register */ +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 +#define MPCM 0 + +/* UART Control Register */ +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define CHR9 2 +#define RXB8 1 +#define TXB8 0 + +/* Analog Comparator Control and Status Register */ +#define ACD 7 +#define AINBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +/* ADC MUX */ +#define ACDBG 6 +#define MUX2 2 +#define MUX1 1 +#define MUX0 0 + +/* ADC Control and Status Register */ +#define ADEN 7 +#define ADSC 6 +#define ADFR 5 +#define ADIF 4 +#define ADIE 3 +#define ADPS2 2 +#define ADPS1 1 +#define ADPS0 0 + +/* Data Register, Port B */ +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Data Direction Register, Port B */ +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Input Pins, Port B */ +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* Data Register, Port C */ +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* Data Direction Register, Port C */ +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +/* Input Pins, Port C */ +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +/* Data Register, Port D */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* Data Direction Register, Port D */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* Input Pins, Port D */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define RAMSTART 0x60 +#define RAMEND 0xDF /*Last On-Chip SRAM location*/ +#define XRAMEND RAMEND +#define E2END 0x7F +#define FLASHEND 0x7FF + +#define SLEEP_MODE_IDLE 0 +#define SLEEP_MODE_PWR_DOWN _BV(SM) + +#endif /* _AVR_IO2333_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/io2343.h b/hardware/tools/avr/avr/include/avr/io2343.h new file mode 100644 index 0000000000000000000000000000000000000000..da40c62f92b18e4d7916cba595e874a2dc046d1b --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/io2343.h @@ -0,0 +1,214 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: io2343.h 2225 2011-03-02 16:27:26Z arcanum $ */ + +/* avr/io2343.h - definitions for AT90S2343 */ + +#ifndef _AVR_IO2343_H_ +#define _AVR_IO2343_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io2343.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO8(0x1E) +#define EEARL _SFR_IO8(0x1E) + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* Timer/Counter 0 */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter 0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU Status Register */ +#define MCUSR _SFR_IO8(0x34) + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* Timer/Counter Interrupt Flag register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK register */ +#define TIMSK _SFR_IO8(0x39) + +/* General Interrupt Flag register */ +#define GIFR _SFR_IO8(0x3A) + +/* General Interrupt MaSK register */ +#define GIMSK _SFR_IO8(0x3B) + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF0_vect_num 2 +#define TIMER0_OVF0_vect _VECTOR(2) +#define SIG_OVERFLOW0 _VECTOR(2) + +#define _VECTORS_SIZE 6 + +/* + The Register Bit names are represented by their bit number (0-7). + */ + +/* General Interrupt MaSK register */ +#define INT0 6 +#define INTF0 6 + +/* General Interrupt Flag Register */ +#define TOIE0 1 +#define TOV0 1 + +/* MCU general Control Register */ +#define SE 5 +#define SM 4 +#define ISC01 1 +#define ISC00 0 + +/* MCU Status Register */ +#define PORF 0 +#define EXTRF 1 + +/* Timer/Counter 0 Control Register */ +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* Watchdog Timer Control Register */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* + PB3 = CLOCK + PB2 = SCK/T0 + PB1 = MISO/INT0 + PB0 = MOSI + */ + +/* Data Register, Port B */ +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Data Direction Register, Port B */ +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Input Pins, Port B */ +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define RAMSTART 0x60 +#define RAMEND 0xDF +#define XRAMEND RAMEND +#define E2END 0x7F +#define E2PAGESIZE 0 +#define FLASHEND 0x07FF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 1 + +/* Low Fuse Byte */ +#define FUSE_RCEN (unsigned char)~_BV(0) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define LFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x91 +#define SIGNATURE_2 0x03 + +#define SLEEP_MODE_IDLE 0 +#define SLEEP_MODE_PWR_DOWN _BV(SM) + +#endif /* _AVR_IO2343_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/io43u32x.h b/hardware/tools/avr/avr/include/avr/io43u32x.h new file mode 100644 index 0000000000000000000000000000000000000000..96d2308278229816ccab7ac1499c142cae000ff1 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/io43u32x.h @@ -0,0 +1,440 @@ +/* Copyright (c) 2003,2005 Keith Gudger + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: io43u32x.h 1873 2009-02-11 17:53:39Z arcanum $ */ + +/* avr/io43u32x.h - definitions for AT43USB32x */ + +#ifndef _AVR_IO43U32X_H_ +#define _AVR_IO43U32X_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io43u32x.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) + +/* UART Baud Rate Register */ +#define UBRR _SFR_IO8(0x09) + +/* UART Control Register */ +#define UCR _SFR_IO8(0x0A) + +/* UART Status Register */ +#define USR _SFR_IO8(0x0B) + +/* UART I/O Data Register */ +#define UDR _SFR_IO8(0x0C) + +/* Input Pins, Port E */ // new port for 43324/6 +#define PINE _SFR_IO8(0x01) + +/* Data Direction Register, Port E */ +#define DDRE _SFR_IO8(0x02) + +/* Data Register, Port E */ +#define PORTE _SFR_IO8(0x03) + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x0D) + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x0E) + +/* SPI I/O Data Register */ +#define SPDR _SFR_IO8(0x0F) + +/* Input Pins, Port D */ +#define PIND _SFR_IO8(0x10) + +/* Data Direction Register, Port D */ +#define DDRD _SFR_IO8(0x11) + +/* Data Register, Port D */ +#define PORTD _SFR_IO8(0x12) + +/* Input Pins, Port C */ +#define PINC _SFR_IO8(0x13) + +/* Data Direction Register, Port C */ +#define DDRC _SFR_IO8(0x14) + +/* Data Register, Port C */ +#define PORTC _SFR_IO8(0x15) + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* Input Pins, Port A */ +#define PINA _SFR_IO8(0x19) + +/* Data Direction Register, Port A */ +#define DDRA _SFR_IO8(0x1A) + +/* Data Register, Port A */ +#define PORTA _SFR_IO8(0x1B) + +/* 0x1C..0x1F reserved */ + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* T/C 1 Input Capture Register */ +#define ICR1 _SFR_IO16(0x24) +#define ICR1L _SFR_IO8(0x24) +#define ICR1H _SFR_IO8(0x25) + +/* Timer/Counter1 Output Compare Register B */ +#define OCR1B _SFR_IO16(0x28) +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Timer/Counter1 Output Compare Register A */ +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Timer/Counter 1 */ +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +/* Timer/Counter 1 Control and Status Register */ +#define TCCR1B _SFR_IO8(0x2E) + +/* Timer/Counter 1 Control Register */ +#define TCCR1A _SFR_IO8(0x2F) + +/* Timer/Counter 0 */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter 0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* Timer/Counter Interrupt Flag Register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK register */ +#define TIMSK _SFR_IO8(0x39) + +/* General Interrupt Control Register */ +#define GIFR _SFR_IO8(0x3A) + +/* General Interrupt Mask register */ +#define GIMSK _SFR_IO8(0x3B) + +/* Interrupt vectors */ + +#define SIG_INTERRUPT0 _VECTOR(1) +#define SIG_INTERRUPT1 _VECTOR(2) +#define SIG_TIMER1_CAPT1 _VECTOR(3) +#define SIG_INPUT_CAPTURE1 _VECTOR(3) +#define SIG_OUTPUT_COMPARE1A _VECTOR(4) +#define SIG_OUTPUT_COMPARE1B _VECTOR(5) +#define SIG_OVERFLOW1 _VECTOR(6) +#define SIG_OVERFLOW0 _VECTOR(7) +#define SIG_SPI _VECTOR(8) +#define SIG_UART_RECV _VECTOR(9) +#define SIG_UART_DATA _VECTOR(10) +#define SIG_UART_TRANS _VECTOR(11) +#define SIG_USB_INT _VECTOR(12) + +#define _VECTORS_SIZE 52 + +/* + The Register Bit names are represented by their bit number (0-7). +*/ + +/* Timer/Counter Interrupt MaSK register */ +#define TICIE1 3 +#define OCIE1A 6 +#define OCIE1B 5 +#define TOIE1 7 +#define TOIE0 1 + +/* Timer/Counter Interrupt Flag Register */ +#define ICF1 3 +#define OCF1A 6 +#define OCF1B 5 +#define TOV1 7 +#define TOV0 1 + +/* MCU general Control Register */ +#define SE 5 +#define SM 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/* Timer/Counter 0 Control Register */ +#define CS02 2 +#define CS01 1 +#define CS00 0 + + +/* Timer/Counter 1 Control Register */ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define PWM11 1 +#define PWM10 0 + +/* Timer/Counter 1 Control and Status Register */ +#define ICNC1 7 +#define ICES1 6 +#define CTC1 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* Watchdog Timer Control Register */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* Data Register, Port A */ +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* Data Direction Register, Port A */ +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +/* Input Pins, Port A */ +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +/* Data Register, Port B */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Data Direction Register, Port B */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Input Pins, Port B */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* Data Direction Register, Port C */ +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +/* Input Pins, Port C */ +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +/* Data Register, Port C */ +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* Data Register, Port D */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* Data Direction Register, Port D */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* Input Pins, Port D */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* Data Register, Port E */ +#define PE7 7 +#define PE6 6 +#define PE5 5 +#define PE4 4 +#define PE3 3 +#define PE2 2 +#define PE1 1 +#define PE0 0 + +/* Data Direction Register, Port E */ +#define DDE7 7 +#define DDE6 6 +#define DDE5 5 +#define DDE4 4 +#define DDE3 3 +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +/* Input Pins, Port E */ +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +/* SPI Status Register */ +#define SPIF 7 +#define WCOL 6 + +/* SPI Control Register */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* UART Status Register */ +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 + +/* UART Control Register */ +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define CHR9 2 +#define RXB8 1 +#define TXB8 0 + +/* Constants */ +#define RAMSTART 0x60 +#define RAMEND 0x025F /*Last On-Chip SRAM Location*/ +#define XRAMEND RAMEND +#define E2END 0x0000 + +/* FIXME: should be 0x1FFFF for max 128K (64K*16) external program memory, + but no RAMPZ causes gcrt1.S build to fail, so assume 64K for now... */ +#define FLASHEND 0x0FFFF + +#define SLEEP_MODE_IDLE 0 +#define SLEEP_MODE_PWR_DOWN _BV(SM) + +#endif /* _AVR_43USB32X_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/io43u35x.h b/hardware/tools/avr/avr/include/avr/io43u35x.h new file mode 100644 index 0000000000000000000000000000000000000000..231d08c52a2f53c267b7302614e612d07d8cc8a5 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/io43u35x.h @@ -0,0 +1,432 @@ +/* Copyright (c) 2003,2005 Keith Gudger + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: io43u35x.h 1873 2009-02-11 17:53:39Z arcanum $ */ + +/* avr/io43u35x.h - definitions for AT43USB35x */ + +#ifndef _AVR_IO43U35X_H_ +#define _AVR_IO43U35X_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io43u35x.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* ADC Data Register */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x02) +#endif +#define ADCW _SFR_IO16(0x02) +#define ADCL _SFR_IO8(0x02) +#define ADCH _SFR_IO8(0x03) + +/* ADC Control and status register */ +#define ADCSR _SFR_IO8(0x07) + +/* ADC Multiplexer select */ +#define ADMUX _SFR_IO8(0x08) + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) + +/* Input Pins, Port F */ +#define PINF _SFR_IO8(0x04) + +/* Data Direction Register, Port F */ +#define DDRF _SFR_IO8(0x05) + +/* Data Register, Port F */ +#define PORTF _SFR_IO8(0x06) + +/* Input Pins, Port E */ +#define PINE _SFR_IO8(0x01) + +/* Data Direction Register, Port E */ +#define DDRE _SFR_IO8(0x02) + +/* Data Register, Port E */ +#define PORTE _SFR_IO8(0x03) + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x0D) + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x0E) + +/* SPI I/O Data Register */ +#define SPDR _SFR_IO8(0x0F) + +/* Input Pins, Port D */ +#define PIND _SFR_IO8(0x10) + +/* Data Direction Register, Port D */ +#define DDRD _SFR_IO8(0x11) + +/* Data Register, Port D */ +#define PORTD _SFR_IO8(0x12) + +/* Input Pins, Port C */ +#define PINC _SFR_IO8(0x13) + +/* Data Direction Register, Port C */ +#define DDRC _SFR_IO8(0x14) + +/* Data Register, Port C */ +#define PORTC _SFR_IO8(0x15) + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* Input Pins, Port A */ +#define PINA _SFR_IO8(0x19) + +/* Data Direction Register, Port A */ +#define DDRA _SFR_IO8(0x1A) + +/* Data Register, Port A */ +#define PORTA _SFR_IO8(0x1B) + +/* 0x1C..0x1F reserved */ + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* T/C 1 Input Capture Register */ +#define ICR1 _SFR_IO16(0x24) +#define ICR1L _SFR_IO8(0x24) +#define ICR1H _SFR_IO8(0x25) + +/* Timer/Counter1 Output Compare Register B */ +#define OCR1B _SFR_IO16(0x28) +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Timer/Counter1 Output Compare Register A */ +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Timer/Counter 1 */ +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +/* Timer/Counter 1 Control and Status Register */ +#define TCCR1B _SFR_IO8(0x2E) + +/* Timer/Counter 1 Control Register */ +#define TCCR1A _SFR_IO8(0x2F) + +/* Timer/Counter 0 */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter 0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* Timer/Counter Interrupt Flag Register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK register */ +#define TIMSK _SFR_IO8(0x39) + +/* General Interrupt Control Register */ +#define GIFR _SFR_IO8(0x3A) + +/* General Interrupt Mask register */ +#define GIMSK _SFR_IO8(0x3B) + +/* Interrupt vectors */ + +#define SIG_INTERRUPT0 _VECTOR(1) /* suspend/resume */ +#define SIG_INTERRUPT1 _VECTOR(2) +#define SIG_TIMER1_CAPT1 _VECTOR(3) +#define SIG_INPUT_CAPTURE1 _VECTOR(3) +#define SIG_OUTPUT_COMPARE1A _VECTOR(4) +#define SIG_OUTPUT_COMPARE1B _VECTOR(5) +#define SIG_OVERFLOW1 _VECTOR(6) +#define SIG_OVERFLOW0 _VECTOR(7) +#define SIG_SPI _VECTOR(8) +/* 9, 10: reserved */ +#define SIG_ADC _VECTOR(11) +#define SIG_USB_INT _VECTOR(12) + +#define _VECTORS_SIZE 52 + +/* + The Register Bit names are represented by their bit number (0-7). +*/ + +/* Timer/Counter Interrupt MaSK register */ +#define TICIE1 3 +#define OCIE1A 6 +#define OCIE1B 5 +#define TOIE1 7 +#define TOIE0 1 + +/* Timer/Counter Interrupt Flag Register */ +#define ICF1 3 +#define OCF1A 6 +#define OCF1B 5 +#define TOV1 7 +#define TOV0 1 + +/* MCU general Control Register */ +#define SE 5 +#define SM 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/* Timer/Counter 0 Control Register */ +#define CS02 2 +#define CS01 1 +#define CS00 0 + + +/* Timer/Counter 1 Control Register */ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define PWM11 1 +#define PWM10 0 + +/* Timer/Counter 1 Control and Status Register */ +#define ICNC1 7 +#define ICES1 6 +#define CTC1 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* Watchdog Timer Control Register */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* Data Register, Port A */ +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* Data Direction Register, Port A */ +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +/* Input Pins, Port A */ +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +/* Data Register, Port B */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Data Direction Register, Port B */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Input Pins, Port B */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* Data Direction Register, Port C */ +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +/* Input Pins, Port C */ +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +/* Data Register, Port C */ +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* Data Register, Port D */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* Data Direction Register, Port D */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* Input Pins, Port D */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* Data Register, Port F */ +#define PF3 3 +#define PF2 2 +#define PF1 1 +#define PF0 0 + +/* Data Direction Register, Port F */ +#define DDF3 3 +#define DDF2 2 +#define DDF1 1 + +/* Input Pins, Port F */ +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +/* SPI Status Register */ +#define SPIF 7 +#define WCOL 6 + +/* SPI Control Register */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* ADC Multiplexer select */ +#define MUX2 2 +#define MUX1 1 +#define MUX0 0 + +/* ADC Control and Status Register */ +#define ADEN 7 +#define ADSC 6 +#define ADFR 5 +#define ADIF 4 +#define ADIE 3 +#define ADPS2 2 +#define ADPS1 1 +#define ADPS0 0 + +/* Constants */ +#define RAMSTART 0x60 +#define RAMEND 0x045F /*Last On-Chip SRAM Location*/ +#define XRAMEND RAMEND +#define E2END 0x0000 +#define FLASHEND 0x5FFF + +#define SLEEP_MODE_IDLE 0 +#define SLEEP_MODE_PWR_DOWN _BV(SM) + +#endif /* _AVR_43USB355_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/io4414.h b/hardware/tools/avr/avr/include/avr/io4414.h new file mode 100644 index 0000000000000000000000000000000000000000..98e0c3b64b6935dc7f941a311c041761aed964b1 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/io4414.h @@ -0,0 +1,500 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: io4414.h 2225 2011-03-02 16:27:26Z arcanum $ */ + +/* avr/io4414.h - definitions for AT90S4414 */ + +#ifndef _AVR_IO4414_H_ +#define _AVR_IO4414_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io4414.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) + +/* UART Baud Rate Register */ +#define UBRR _SFR_IO8(0x09) + +/* UART Control Register */ +#define UCR _SFR_IO8(0x0A) + +/* UART Status Register */ +#define USR _SFR_IO8(0x0B) + +/* UART I/O Data Register */ +#define UDR _SFR_IO8(0x0C) + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x0D) + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x0E) + +/* SPI I/O Data Register */ +#define SPDR _SFR_IO8(0x0F) + +/* Input Pins, Port D */ +#define PIND _SFR_IO8(0x10) + +/* Data Direction Register, Port D */ +#define DDRD _SFR_IO8(0x11) + +/* Data Register, Port D */ +#define PORTD _SFR_IO8(0x12) + +/* Input Pins, Port C */ +#define PINC _SFR_IO8(0x13) + +/* Data Direction Register, Port C */ +#define DDRC _SFR_IO8(0x14) + +/* Data Register, Port C */ +#define PORTC _SFR_IO8(0x15) + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* Input Pins, Port A */ +#define PINA _SFR_IO8(0x19) + +/* Data Direction Register, Port A */ +#define DDRA _SFR_IO8(0x1A) + +/* Data Register, Port A */ +#define PORTA _SFR_IO8(0x1B) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO8(0x1E) +#define EEARL _SFR_IO8(0x1E) + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* T/C 1 Input Capture Register */ +#define ICR1 _SFR_IO16(0x24) +#define ICR1L _SFR_IO8(0x24) +#define ICR1H _SFR_IO8(0x25) + +/* Timer/Counter1 Output Compare Register B */ +#define OCR1B _SFR_IO16(0x28) +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Timer/Counter1 Output Compare Register A */ +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Timer/Counter 1 */ +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +/* Timer/Counter 1 Control and Status Register */ +#define TCCR1B _SFR_IO8(0x2E) + +/* Timer/Counter 1 Control Register */ +#define TCCR1A _SFR_IO8(0x2F) + +/* Timer/Counter 0 */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter 0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* Timer/Counter Interrupt Flag register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK register */ +#define TIMSK _SFR_IO8(0x39) + +/* General Interrupt Flag Register */ +#define GIFR _SFR_IO8(0x3A) + +/* General Interrupt MaSK register */ +#define GIMSK _SFR_IO8(0x3B) + +/* 0x3C..0x3D SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt Request 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt Request 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* Timer/Counter Capture Event */ +#define TIMER1_CAPT_vect_num 3 +#define TIMER1_CAPT_vect _VECTOR(3) +#define SIG_INPUT_CAPTURE1 _VECTOR(3) + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect_num 4 +#define TIMER1_COMPA_vect _VECTOR(4) +#define SIG_OUTPUT_COMPARE1A _VECTOR(4) + +/* Timer/Counter1 Compare MatchB */ +#define TIMER1_COMPB_vect_num 5 +#define TIMER1_COMPB_vect _VECTOR(5) +#define SIG_OUTPUT_COMPARE1B _VECTOR(5) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 6 +#define TIMER1_OVF_vect _VECTOR(6) +#define SIG_OVERFLOW1 _VECTOR(6) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 7 +#define TIMER0_OVF_vect _VECTOR(7) +#define SIG_OVERFLOW0 _VECTOR(7) + +/* Serial Transfer Complete */ +#define SPI_STC_vect_num 8 +#define SPI_STC_vect _VECTOR(8) +#define SIG_SPI _VECTOR(8) + +/* UART, Rx Complete */ +#define UART_RX_vect_num 9 +#define UART_RX_vect _VECTOR(9) +#define SIG_UART_RECV _VECTOR(9) + +/* UART Data Register Empty */ +#define UART_UDRE_vect_num 10 +#define UART_UDRE_vect _VECTOR(10) +#define SIG_UART_DATA _VECTOR(10) + +/* UART, Tx Complete */ +#define UART_TX_vect_num 11 +#define UART_TX_vect _VECTOR(11) +#define SIG_UART_TRANS _VECTOR(11) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 12 +#define ANA_COMP_vect _VECTOR(12) +#define SIG_COMPARATOR _VECTOR(12) + +#define _VECTORS_SIZE 26 + +/* + The Register Bit names are represented by their bit number (0-7). +*/ + +/* General Interrupt MaSK register */ +#define INT1 7 +#define INT0 6 + +/* General Interrupt Flag Register */ +#define INTF1 7 +#define INTF0 6 + +/* Timer/Counter Interrupt MaSK register */ +#define TOIE1 7 +#define OCIE1A 6 +#define OCIE1B 5 +#define TICIE1 3 +#define TOIE0 1 + +/* Timer/Counter Interrupt Flag register */ +#define TOV1 7 +#define OCF1A 6 +#define OCF1B 5 +#define ICF1 3 +#define TOV0 1 + +/* MCU general Control Register */ +#define SRE 7 +#define SRW 6 +#define SE 5 +#define SM 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/* Timer/Counter 0 Control Register */ +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* Timer/Counter 1 Control Register */ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define PWM11 1 +#define PWM10 0 + +/* Timer/Counter 1 Control and Status Register */ +#define ICNC1 7 +#define ICES1 6 +#define CTC1 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* Watchdog Timer Control Register */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* Data Register, Port A */ +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* Data Direction Register, Port A */ +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +/* Input Pins, Port A */ +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +/* Data Register, Port B */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Data Direction Register, Port B */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Input Pins, Port B */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* Data Register, Port C */ +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* Data Direction Register, Port C */ +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +/* Input Pins, Port C */ +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +/* Data Register, Port D */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* Data Direction Register, Port D */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* Input Pins, Port D */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* SPI Status Register */ +#define SPIF 7 +#define WCOL 6 + +/* SPI Control Register */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* UART Status Register */ +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 + +/* UART Control Register */ +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define CHR9 2 +#define RXB8 1 +#define TXB8 0 + +/* Analog Comparator Control and Status Register */ +#define ACD 7 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define RAMSTART 0x60 +#define RAMEND 0x15F /* Last On-Chip SRAM Location */ +#define XRAMEND 0xFFFF +#define E2END 0xFF +#define E2PAGESIZE 0 +#define FLASHEND 0xFFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 1 + +/* Low Fuse Byte */ +#define FUSE_SPIEN (unsigned char)~_BV(1) /* Serial Program Downloading Enabled */ +#define FUSE_FSTRT (unsigned char)~_BV(2) /* Short Start-up time selected */ +#define LFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x92 +#define SIGNATURE_2 0x01 + +#define SLEEP_MODE_IDLE 0 +#define SLEEP_MODE_PWR_DOWN _BV(SM) + +#endif /* _AVR_IO4414_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/io4433.h b/hardware/tools/avr/avr/include/avr/io4433.h new file mode 100644 index 0000000000000000000000000000000000000000..805cd46d7e604127eb05f9d7f3138d12dd27283e --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/io4433.h @@ -0,0 +1,489 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: io4433.h 2225 2011-03-02 16:27:26Z arcanum $ */ + +/* avr/io4433.h - definitions for AT90S4433 */ + +#ifndef _AVR_IO4433_H_ +#define _AVR_IO4433_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io4433.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* UART Baud Rate Register high */ +#define UBRRH _SFR_IO8(0x03) + +/* ADC Data register */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) + +/* ADC Control and Status Register */ +#define ADCSR _SFR_IO8(0x06) + +/* ADC MUX */ +#define ADMUX _SFR_IO8(0x07) + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) + +/* UART Baud Rate Register */ +#define UBRR _SFR_IO8(0x09) + +/* UART Control/Status Registers */ +#define UCSRB _SFR_IO8(0x0A) +#define UCSRA _SFR_IO8(0x0B) + +/* UART I/O Data Register */ +#define UDR _SFR_IO8(0x0C) + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x0D) + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x0E) + +/* SPI I/O Data Register */ +#define SPDR _SFR_IO8(0x0F) + +/* Input Pins, Port D */ +#define PIND _SFR_IO8(0x10) + +/* Data Direction Register, Port D */ +#define DDRD _SFR_IO8(0x11) + +/* Data Register, Port D */ +#define PORTD _SFR_IO8(0x12) + +/* Input Pins, Port C */ +#define PINC _SFR_IO8(0x13) + +/* Data Direction Register, Port C */ +#define DDRC _SFR_IO8(0x14) + +/* Data Register, Port C */ +#define PORTC _SFR_IO8(0x15) + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO8(0x1E) +#define EEARL _SFR_IO8(0x1E) + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* T/C 1 Input Capture Register */ +#define ICR1 _SFR_IO16(0x26) +#define ICR1L _SFR_IO8(0x26) +#define ICR1H _SFR_IO8(0x27) + +/* Timer/Counter1 Output Compare Register A */ +#define OCR1 _SFR_IO16(0x2A) +#define OCR1L _SFR_IO8(0x2A) +#define OCR1H _SFR_IO8(0x2B) + +/* Timer/Counter 1 */ +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +/* Timer/Counter 1 Control and Status Register */ +#define TCCR1B _SFR_IO8(0x2E) + +/* Timer/Counter 1 Control Register */ +#define TCCR1A _SFR_IO8(0x2F) + +/* Timer/Counter 0 */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter 0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU general Status Register */ +#define MCUSR _SFR_IO8(0x34) + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* Timer/Counter Interrupt Flag register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK register */ +#define TIMSK _SFR_IO8(0x39) + +/* General Interrupt Flag Register */ +#define GIFR _SFR_IO8(0x3A) + +/* General Interrupt MaSK register */ +#define GIMSK _SFR_IO8(0x3B) + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* Timer/Counter Capture Event */ +#define TIMER1_CAPT_vect_num 3 +#define TIMER1_CAPT_vect _VECTOR(3) +#define SIG_INPUT_CAPTURE1 _VECTOR(3) + +/* Timer/Counter1 Compare Match */ +#define TIMER1_COMP_vect_num 4 +#define TIMER1_COMP_vect _VECTOR(4) +#define SIG_OUTPUT_COMPARE1A _VECTOR(4) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 5 +#define TIMER1_OVF_vect _VECTOR(5) +#define SIG_OVERFLOW1 _VECTOR(5) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 6 +#define TIMER0_OVF_vect _VECTOR(6) +#define SIG_OVERFLOW0 _VECTOR(6) + +/* Serial Transfer Complete */ +#define SPI_STC_vect_num 7 +#define SPI_STC_vect _VECTOR(7) +#define SIG_SPI _VECTOR(7) + +/* UART, Rx Complete */ +#define UART_RX_vect_num 8 +#define UART_RX_vect _VECTOR(8) +#define SIG_UART_RECV _VECTOR(8) + +/* UART Data Register Empty */ +#define UART_UDRE_vect_num 9 +#define UART_UDRE_vect _VECTOR(9) +#define SIG_UART_DATA _VECTOR(9) + +/* UART, Tx Complete */ +#define UART_TX_vect_num 10 +#define UART_TX_vect _VECTOR(10) +#define SIG_UART_TRANS _VECTOR(10) + +/* ADC Conversion Complete */ +#define ADC_vect_num 11 +#define ADC_vect _VECTOR(11) +#define SIG_ADC _VECTOR(11) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 12 +#define EE_RDY_vect _VECTOR(12) +#define SIG_EEPROM_READY _VECTOR(12) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 13 +#define ANA_COMP_vect _VECTOR(13) +#define SIG_COMPARATOR _VECTOR(13) + +#define _VECTORS_SIZE 28 + +/* + The Register Bit names are represented by their bit number (0-7). +*/ + +/* MCU general Status Register */ +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +/* General Interrupt MaSK register */ +#define INT1 7 +#define INT0 6 + +/* General Interrupt Flag Register */ +#define INTF1 7 +#define INTF0 6 + +/* Timer/Counter Interrupt MaSK register */ +#define TOIE1 7 +#define OCIE1 6 +#define TICIE1 3 +#define TOIE0 1 + +/* Timer/Counter Interrupt Flag register */ +#define TOV1 7 +#define OCF1 6 +#define ICF1 3 +#define TOV0 1 + +/* MCU general Control Register */ +#define SE 5 +#define SM 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/* Timer/Counter 0 Control Register */ +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* Timer/Counter 1 Control Register */ +#define COM11 7 +#define COM10 6 +#define PWM11 1 +#define PWM10 0 + +/* Timer/Counter 1 Control and Status Register */ +#define ICNC1 7 +#define ICES1 6 +#define CTC1 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* Watchdog Timer Control Register */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* SPI Control Register */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* SPI Status Register */ +#define SPIF 7 +#define WCOL 6 + +/* UART Status Register */ +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 +#define MPCM 0 + +/* UART Control Register */ +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define CHR9 2 +#define RXB8 1 +#define TXB8 0 + +/* Analog Comparator Control and Status Register */ +#define ACD 7 +#define AINBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +/* ADC MUX */ +#define ACDBG 6 +#define MUX2 2 +#define MUX1 1 +#define MUX0 0 + +/* ADC Control and Status Register */ +#define ADEN 7 +#define ADSC 6 +#define ADFR 5 +#define ADIF 4 +#define ADIE 3 +#define ADPS2 2 +#define ADPS1 1 +#define ADPS0 0 + +/* Data Register, Port B */ +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Data Direction Register, Port B */ +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Input Pins, Port B */ +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* Data Register, Port C */ +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* Data Direction Register, Port C */ +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +/* Input Pins, Port C */ +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +/* Data Register, Port D */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* Data Direction Register, Port D */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* Input Pins, Port D */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define RAMSTART 0x60 +#define RAMEND 0xDF /*Last On-Chip SRAM location*/ +#define XRAMEND RAMEND +#define E2END 0xFF +#define E2PAGESIZE 0 +#define FLASHEND 0xFFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 1 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_BODEN (unsigned char)~_BV(3) +#define FUSE_BODLEVEL (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define LFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x92 +#define SIGNATURE_2 0x03 + +#define SLEEP_MODE_IDLE 0 +#define SLEEP_MODE_PWR_DOWN _BV(SM) + +#endif /* _AVR_IO4433_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/io4434.h b/hardware/tools/avr/avr/include/avr/io4434.h new file mode 100644 index 0000000000000000000000000000000000000000..db1005d6359adfa749f62b87fee58dc0c43d9d0f --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/io4434.h @@ -0,0 +1,588 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: io4434.h 2225 2011-03-02 16:27:26Z arcanum $ */ + +/* avr/io4434.h - definitions for AT90S4434 */ + +#ifndef _AVR_IO4434_H_ +#define _AVR_IO4434_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io4434.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* ADC Data register */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) + +/* ADC Control and Status Register */ +#define ADCSR _SFR_IO8(0x06) + +/* ADC MUX */ +#define ADMUX _SFR_IO8(0x07) + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) + +/* UART Baud Rate Register */ +#define UBRR _SFR_IO8(0x09) + +/* UART Control Register */ +#define UCR _SFR_IO8(0x0A) + +/* UART Status Register */ +#define USR _SFR_IO8(0x0B) + +/* UART I/O Data Register */ +#define UDR _SFR_IO8(0x0C) + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x0D) + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x0E) + +/* SPI I/O Data Register */ +#define SPDR _SFR_IO8(0x0F) + +/* Input Pins, Port D */ +#define PIND _SFR_IO8(0x10) + +/* Data Direction Register, Port D */ +#define DDRD _SFR_IO8(0x11) + +/* Data Register, Port D */ +#define PORTD _SFR_IO8(0x12) + +/* Input Pins, Port C */ +#define PINC _SFR_IO8(0x13) + +/* Data Direction Register, Port C */ +#define DDRC _SFR_IO8(0x14) + +/* Data Register, Port C */ +#define PORTC _SFR_IO8(0x15) + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* Input Pins, Port A */ +#define PINA _SFR_IO8(0x19) + +/* Data Direction Register, Port A */ +#define DDRA _SFR_IO8(0x1A) + +/* Data Register, Port A */ +#define PORTA _SFR_IO8(0x1B) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO8(0x1E) +#define EEARL _SFR_IO8(0x1E) + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* Asynchronous mode Status Register */ +#define ASSR _SFR_IO8(0x22) + +/* Timer/Counter2 Output Compare Register */ +#define OCR2 _SFR_IO8(0x23) + +/* Timer/Counter 2 */ +#define TCNT2 _SFR_IO8(0x24) + +/* Timer/Counter 2 Control Register */ +#define TCCR2 _SFR_IO8(0x25) + +/* T/C 1 Input Capture Register */ +#define ICR1 _SFR_IO16(0x26) +#define ICR1L _SFR_IO8(0x26) +#define ICR1H _SFR_IO8(0x27) + +/* Timer/Counter1 Output Compare Register B */ +#define OCR1B _SFR_IO16(0x28) +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Timer/Counter1 Output Compare Register A */ +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Timer/Counter 1 */ +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +/* Timer/Counter 1 Control and Status Register */ +#define TCCR1B _SFR_IO8(0x2E) + +/* Timer/Counter 1 Control Register */ +#define TCCR1A _SFR_IO8(0x2F) + +/* Timer/Counter 0 */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter 0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU general Status Register */ +#define MCUSR _SFR_IO8(0x34) + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* Timer/Counter Interrupt Flag register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK register */ +#define TIMSK _SFR_IO8(0x39) + +/* General Interrupt Flag Register */ +#define GIFR _SFR_IO8(0x3A) + +/* General Interrupt MaSK register */ +#define GIMSK _SFR_IO8(0x3B) + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* Timer/Counter2 Compare Match */ +#define TIMER2_COMP_vect_num 3 +#define TIMER2_COMP_vect _VECTOR(3) +#define SIG_OUTPUT_COMPARE2 _VECTOR(3) + +/* Timer/Counter2 Overflow */ +#define TIMER2_OVF_vect_num 4 +#define TIMER2_OVF_vect _VECTOR(4) +#define SIG_OVERFLOW2 _VECTOR(4) + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect_num 5 +#define TIMER1_CAPT_vect _VECTOR(5) +#define SIG_INPUT_CAPTURE1 _VECTOR(5) + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect_num 6 +#define TIMER1_COMPA_vect _VECTOR(6) +#define SIG_OUTPUT_COMPARE1A _VECTOR(6) + +/* Timer/Counter1 Compare Match B */ +#define TIMER1_COMPB_vect_num 7 +#define TIMER1_COMPB_vect _VECTOR(7) +#define SIG_OUTPUT_COMPARE1B _VECTOR(7) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 8 +#define TIMER1_OVF_vect _VECTOR(8) +#define SIG_OVERFLOW1 _VECTOR(8) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 9 +#define TIMER0_OVF_vect _VECTOR(9) +#define SIG_OVERFLOW0 _VECTOR(9) + +/* SPI Serial Transfer Complete */ +#define SPI_STC_vect_num 10 +#define SPI_STC_vect _VECTOR(10) +#define SIG_SPI _VECTOR(10) + +/* UART, RX Complete */ +#define UART_RX_vect_num 11 +#define UART_RX_vect _VECTOR(11) +#define SIG_UART_RECV _VECTOR(11) + +/* UART Data Register Empty */ +#define UART_UDRE_vect_num 12 +#define UART_UDRE_vect _VECTOR(12) +#define SIG_UART_DATA _VECTOR(12) + +/* UART, TX Complete */ +#define UART_TX_vect_num 13 +#define UART_TX_vect _VECTOR(13) +#define SIG_UART_TRANS _VECTOR(13) + +/* ADC Conversion Complete */ +#define ADC_vect_num 14 +#define ADC_vect _VECTOR(14) +#define SIG_ADC _VECTOR(14) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 15 +#define EE_RDY_vect _VECTOR(15) +#define SIG_EEPROM_READY _VECTOR(15) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 16 +#define ANA_COMP_vect _VECTOR(16) +#define SIG_COMPARATOR _VECTOR(16) + +#define _VECTORS_SIZE 34 + +/* + The Register Bit names are represented by their bit number (0-7). +*/ + +/* MCU general Status Register */ +#define EXTRF 1 +#define PORF 0 + +/* General Interrupt MaSK register */ +#define INT1 7 +#define INT0 6 + +/* General Interrupt Flag Register */ +#define INTF1 7 +#define INTF0 6 + +/* Timer/Counter Interrupt MaSK register */ +#define OCIE2 7 +#define TOIE2 6 +#define TICIE1 5 +#define OCIE1A 4 +#define OCIE1B 3 +#define TOIE1 2 +#define TOIE0 0 + +/* Timer/Counter Interrupt Flag register */ +#define OCF2 7 +#define TOV2 6 +#define ICF1 5 +#define OCF1A 4 +#define OCF1B 3 +#define TOV1 2 +#define TOV0 0 + +/* MCU general Control Register */ +#define SE 6 +#define SM1 5 +#define SM0 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/* Timer/Counter 0 Control Register */ +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* Timer/Counter 1 Control Register */ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define PWM11 1 +#define PWM10 0 + +/* Timer/Counter 1 Control and Status Register */ +#define ICNC1 7 +#define ICES1 6 +#define CTC1 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* Timer/Counter 2 Control Register */ +#define PWM2 6 +#define COM21 5 +#define COM20 4 +#define CTC2 3 +#define CS22 2 +#define CS21 1 +#define CS20 0 + +/* Asynchronous mode Status Register */ +#define AS2 3 +#define TCN2UB 2 +#define OCR2UB 1 +#define TCR2UB 0 + +/* Watchdog Timer Control Register */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* Data Register, Port A */ +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* Data Direction Register, Port A */ +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +/* Input Pins, Port A */ +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +/* Data Register, Port B */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Data Direction Register, Port B */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Input Pins, Port B */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* Data Register, Port C */ +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* Data Direction Register, Port C */ +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +/* Input Pins, Port C */ +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +/* Data Register, Port D */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* Data Direction Register, Port D */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* Input Pins, Port D */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* SPI Control Register */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* SPI Status Register */ +#define SPIF 7 +#define WCOL 6 + +/* UART Status Register */ +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 + +/* UART Control Register */ +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define CHR9 2 +#define RXB8 1 +#define TXB8 0 + +/* Analog Comparator Control and Status Register */ +#define ACD 7 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +/* ADC MUX */ +#define MUX2 2 +#define MUX1 1 +#define MUX0 0 + +/* ADC Control and Status Register */ +#define ADEN 7 +#define ADSC 6 +#define ADFR 5 +#define ADIF 4 +#define ADIE 3 +#define ADPS2 2 +#define ADPS1 1 +#define ADPS0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define RAMSTART 0x60 +#define RAMEND 0x15F /*Last On-Chip SRAM location*/ +#define XRAMEND RAMEND +#define E2END 0xFF +#define E2PAGESIZE 0 +#define FLASHEND 0xFFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 1 + +/* Low Fuse Byte */ +#define FUSE_SPIEN ~_BV(1) /* Serial Program Downloading Enabled */ +#define FUSE_FSTRT ~_BV(2) /* Short Start-up time selected */ +#define LFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x03 + +#define SLEEP_MODE_IDLE 0 +#define SLEEP_MODE_ADC _BV(SM0) +#define SLEEP_MODE_PWR_DOWN _BV(SM1) +#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) + +#endif /* _AVR_IO4434_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/io76c711.h b/hardware/tools/avr/avr/include/avr/io76c711.h new file mode 100644 index 0000000000000000000000000000000000000000..1c2edf25ca338bd1b7cb483614884816151c41f9 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/io76c711.h @@ -0,0 +1,499 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: io76c711.h 1873 2009-02-11 17:53:39Z arcanum $ */ + +/* avr/io76c711.h - definitions for AT76C711 */ + +#ifndef _AVR_IO76C711_H_ +#define _AVR_IO76C711_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io76c711.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* 0x00-0x0C reserved */ + +/* SPI */ +#define SPCR _SFR_IO8(0x0D) +#define SPSR _SFR_IO8(0x0E) +#define SPDR _SFR_IO8(0x0F) + +/* Port D */ +#define PIND _SFR_IO8(0x10) +#define DDRD _SFR_IO8(0x11) +#define PORTD _SFR_IO8(0x12) + +/* Peripheral Enable Register */ +#define PERIPHEN _SFR_IO8(0x13) + +/* Clock Control Register */ +#define CLK_CNTR _SFR_IO8(0x14) + +/* Data Register, Port C */ +#define PORTC _SFR_IO8(0x15) + +/* Port B */ +#define PINB _SFR_IO8(0x16) +#define DDRB _SFR_IO8(0x17) +#define PORTB _SFR_IO8(0x18) + +/* Port A */ +#define PINA _SFR_IO8(0x19) +#define DDRA _SFR_IO8(0x1A) +#define PORTA _SFR_IO8(0x1B) + +/* 0x1C-0x1F reserved */ + +#define IRDAMOD _SFR_IO8(0x20) + +#define WDTCR _SFR_IO8(0x21) + +/* 0x22-0x25 reserved */ +/* Timer 1 */ +#define ICR1 _SFR_IO16(0x26) +#define ICR1L _SFR_IO8(0x26) +#define ICR1H _SFR_IO8(0x27) +#define OCR1B _SFR_IO16(0x28) +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) +#define TCCR1B _SFR_IO8(0x2E) +#define TCCR1A _SFR_IO8(0x2F) + +/* 0x30 reserved */ + +/* Timer 0 */ +#define PRELD _SFR_IO8(0x31) +#define TCNT0 _SFR_IO8(0x32) +#define TCCR0 _SFR_IO8(0x33) + +#define MCUSR _SFR_IO8(0x34) +#define MCUCR _SFR_IO8(0x35) + +#define TIFR _SFR_IO8(0x36) +#define TIMSK _SFR_IO8(0x37) + +/* 0x38 reserved */ + +#define EIMSK _SFR_IO8(0x39) + +/* 0x3A-0x3C reserved */ + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +#define SIG_SUSPEND_RESUME _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(2) +#define SIG_INPUT_CAPTURE1 _VECTOR(3) +#define SIG_OUTPUT_COMPARE1A _VECTOR(4) +#define SIG_OUTPUT_COMPARE1B _VECTOR(5) +#define SIG_OVERFLOW1 _VECTOR(6) +#define SIG_OVERFLOW0 _VECTOR(7) +#define SIG_SPI _VECTOR(8) +#define SIG_TDMAC _VECTOR(9) +#define SIG_UART0 _VECTOR(10) +#define SIG_RDMAC _VECTOR(11) +#define SIG_USB_HW _VECTOR(12) +#define SIG_UART1 _VECTOR(13) +#define SIG_INTERRUPT1 _VECTOR(14) + +#define _VECTORS_SIZE 60 + +/* Bit numbers */ + +/* EIMSK */ +/* bits 7-4 reserved */ +#define POL1 3 +#define POL0 2 +#define INT1 1 +#define INT0 0 + +/* TIMSK */ +#define TOIE1 7 +#define OCIE1A 6 +#define OCIE1B 5 +/* bit 4 reserved */ +#define TICIE1 3 +/* bit 2 reserved */ +#define TOIE0 1 +/* bit 0 reserved */ + +/* TIFR */ +#define TOV1 7 +#define OCF1A 6 +#define OCF1B 5 +/* bit 4 reserved */ +#define ICF1 3 +/* bit 2 reserved */ +#define TOV0 1 +/* bit 0 reserved */ + +/* MCUCR */ +/* bits 7-6 reserved */ +#define SE 5 +#define SM1 4 +#define SM0 3 +/* bits 2-0 reserved */ + +/* MCUSR */ +/* bits 7-2 reserved */ +#define EXTRF 1 +#define PORF 0 + +/* TCCR0 */ +/* bits 7-6 reserved */ +#define COM01 5 +#define COM00 4 +#define CTC0 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* TCCR1A */ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +/* bits 3-0 reserved */ + +/* TCCR1B */ +#define ICNC1 7 +#define ICES1 6 +/* bits 5-4 reserved */ +#define CTC1 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* WDTCR */ +/* bits 7-5 reserved */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* IRDAMOD */ +/* bits 7-3 reserved */ +#define POL 2 +#define MODE 1 +#define EN 0 + +/* PORTA */ +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* DDRA */ +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +/* PINA */ +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +/* + PB7 = SCK + PB6 = MISO + PB5 = MOSI + PB4 = SS# + PB2 = ICP + PB1 = T1 + PB0 = T0 + */ + +/* PORTB */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* DDRB */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* PINB */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* PORTC */ +/* bits 7-4 reserved */ +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* + PD7 = INT1 / OC1B + PD6 = INT0 / OC1A + PD1 = TXD + PD0 = RXD + */ + +/* PORTD */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* DDRD */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* PIND */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* CLK_CNTR */ +/* bits 7-5 reserved */ +#define UOSC 4 +#define UCK 3 +#define IRCK 2 +/* bits 1-0 reserved */ + +/* PERIPHEN */ +/* bits 7-3 reserved */ +#define IRDA 2 +#define UART 1 +#define USB 0 + +/* SPSR */ +#define SPIF 7 +#define WCOL 6 +/* bits 5-0 reserved */ + +/* SPCR */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* Memory mapped registers (XXX - not yet changed to use _SFR_MEM8() macros) */ + +/* UART */ +#define UART0_BASE 0x2020 +#define UART1_BASE 0x2030 +/* offsets from the base address */ +#define US_RHR 0x00 +#define US_THR 0x00 +#define US_IER 0x01 +#define US_FCR 0x02 +#define US_PMR 0x03 +#define US_MR 0x04 +#define US_CSR 0x05 +#define US_CR 0x06 +#define US_BL 0x07 +#define US_BM 0x08 +#define US_RTO 0x09 +#define US_TTG 0x0A + +/* DMA */ +#define DMA_BASE 0x2000 +/* offsets from the base address */ +#define TXTADL 0x01 +#define TXPLL 0x03 +#define TXPLM 0x04 +#define TXTPLL 0x05 +#define TXTPLM 0x06 +#define RXTADL 0x07 +#define RXTADMEN 0x08 +#define RSPLL 0x09 +#define RXPLM 0x0A +#define RXTPLL 0x0B +#define RXTPLM 0x0C +#define INTCST 0x0D +/* XXX DPORG register mentioned on page 20, but undocumented */ + +/* XXX Program Memory Control Bit mentioned on page 20, but undocumented */ +#define PROGRAM_MEMORY_CONTROL_BIT 0x2040 + +/* USB */ +#define USB_BASE 0x1000 +/* offsets from the base address */ +#define FRM_NUM_H 0x0FD +#define FRM_NUM_L 0x0FC +#define GLB_STATE 0x0FB +#define SPRSR 0x0FA +#define SPRSIE 0x0F9 +#define UISR 0x0F7 +#define UIAR 0x0F5 +#define FADDR 0x0F2 +#define ENDPPGPG 0x0F1 +#define ECR0 0x0EF +#define ECR1 0x0EE +#define ECR2 0x0ED +#define ECR3 0x0EC +#define ECR4 0x0EB +#define ECR5 0x0EA +#define ECR6 0x0E9 +#define ECR7 0x0E8 +#define CSR0 0x0DF +#define CSR1 0x0DE +#define CSR2 0x0DD +#define CSR3 0x0DC +#define CSR4 0x0DB +#define CSR5 0x0DA +#define CSR6 0x0D9 +#define CSR7 0x0D8 +#define FDR0 0x0CF +#define FDR1 0x0CE +#define FDR2 0x0CD +#define FDR3 0x0CC +#define FDR4 0x0CB +#define FDR5 0x0CA +#define FDR6 0x0C9 +#define FDR7 0x0C8 +#define FBYTE_CNT0_L 0x0BF +#define FBYTE_CNT1_L 0x0BE +#define FBYTE_CNT2_L 0x0BD +#define FBYTE_CNT3_L 0x0BC +#define FBYTE_CNT4_L 0x0BB +#define FBYTE_CNT5_L 0x0BA +#define FBYTE_CNT6_L 0x0B9 +#define FBYTE_CNT7_L 0x0B8 +#define FBYTE_CNT0_H 0x0AF +#define FBYTE_CNT1_H 0x0AE +#define FBYTE_CNT2_H 0x0AD +#define FBYTE_CNT3_H 0x0AC +#define FBYTE_CNT4_H 0x0AB +#define FBYTE_CNT5_H 0x0AA +#define FBYTE_CNT6_H 0x0A9 +#define FBYTE_CNT7_H 0x0A8 +#define SLP_MD_EN 0x100 +#define IRQ_EN 0x101 +#define IRQ_STAT 0x102 +#define SUSP_WUP 0x103 +#define PA_EN 0x104 +#define USB_DMA_ADL 0x105 +#define USB_DMA_ADH 0x106 +#define USB_DMA_PLR 0x107 +#define USB_DMA_EAD 0x108 +#define USB_DMA_PLT 0x109 +#define USB_DMA_EN 0x10A + +/* Last memory addresses */ +#define RAMSTART 0x60 +#define RAMEND 0x07FF +#define XRAMEND RAMEND +#define E2END 0 +#define FLASHEND 0x3FFF + +#define SLEEP_MODE_IDLE 0 +#define SLEEP_MODE_ADC _BV(SM0) +#define SLEEP_MODE_PWR_DOWN _BV(SM1) +#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) + +/* + AT76C711 data space memory map (ranges not listed are reserved): + 0x0000 - 0x001F - AVR registers + 0x0020 - 0x005F - AVR I/O space + 0x0060 - 0x07FF - AVR data SRAM + 0x1000 - 0x1FFF - USB (not all locations used) + 0x2000 - 0x201F - DMA controller + 0x2020 - 0x202F - UART0 + 0x2030 - 0x203F - UART1 (IRDA) + 0x2040 - the mysterious Program Memory Control bit (???) + 0x3000 - 0x37FF - DPRAM + 0x8000 - 0xBFFF - program SRAM (read/write), would be nice if other + AVR devices did that as well (no need to use LPM!) + */ +#endif /* _AVR_IO76C711_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/io8515.h b/hardware/tools/avr/avr/include/avr/io8515.h new file mode 100644 index 0000000000000000000000000000000000000000..8aa1d9dbbdc3c41e730e04f5915f2df86e5d5b26 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/io8515.h @@ -0,0 +1,501 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: io8515.h 2225 2011-03-02 16:27:26Z arcanum $ */ + +/* avr/io8515.h - definitions for AT90S8515 */ + +#ifndef _AVR_IO8515_H_ +#define _AVR_IO8515_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io8515.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) + +/* UART Baud Rate Register */ +#define UBRR _SFR_IO8(0x09) + +/* UART Control Register */ +#define UCR _SFR_IO8(0x0A) + +/* UART Status Register */ +#define USR _SFR_IO8(0x0B) + +/* UART I/O Data Register */ +#define UDR _SFR_IO8(0x0C) + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x0D) + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x0E) + +/* SPI I/O Data Register */ +#define SPDR _SFR_IO8(0x0F) + +/* Input Pins, Port D */ +#define PIND _SFR_IO8(0x10) + +/* Data Direction Register, Port D */ +#define DDRD _SFR_IO8(0x11) + +/* Data Register, Port D */ +#define PORTD _SFR_IO8(0x12) + +/* Input Pins, Port C */ +#define PINC _SFR_IO8(0x13) + +/* Data Direction Register, Port C */ +#define DDRC _SFR_IO8(0x14) + +/* Data Register, Port C */ +#define PORTC _SFR_IO8(0x15) + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* Input Pins, Port A */ +#define PINA _SFR_IO8(0x19) + +/* Data Direction Register, Port A */ +#define DDRA _SFR_IO8(0x1A) + +/* Data Register, Port A */ +#define PORTA _SFR_IO8(0x1B) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO16(0x1E) +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* T/C 1 Input Capture Register */ +#define ICR1 _SFR_IO16(0x24) +#define ICR1L _SFR_IO8(0x24) +#define ICR1H _SFR_IO8(0x25) + +/* Timer/Counter1 Output Compare Register B */ +#define OCR1B _SFR_IO16(0x28) +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Timer/Counter1 Output Compare Register A */ +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Timer/Counter 1 */ +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +/* Timer/Counter 1 Control and Status Register */ +#define TCCR1B _SFR_IO8(0x2E) + +/* Timer/Counter 1 Control Register */ +#define TCCR1A _SFR_IO8(0x2F) + +/* Timer/Counter 0 */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter 0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* Timer/Counter Interrupt Flag register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK register */ +#define TIMSK _SFR_IO8(0x39) + +/* General Interrupt Flag Register */ +#define GIFR _SFR_IO8(0x3A) + +/* General Interrupt MaSK register */ +#define GIMSK _SFR_IO8(0x3B) + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt Request 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt Request 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* Timer/Counter Capture Event */ +#define TIMER1_CAPT_vect_num 3 +#define TIMER1_CAPT_vect _VECTOR(3) +#define SIG_INPUT_CAPTURE1 _VECTOR(3) + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect_num 4 +#define TIMER1_COMPA_vect _VECTOR(4) +#define SIG_OUTPUT_COMPARE1A _VECTOR(4) + +/* Timer/Counter1 Compare MatchB */ +#define TIMER1_COMPB_vect_num 5 +#define TIMER1_COMPB_vect _VECTOR(5) +#define SIG_OUTPUT_COMPARE1B _VECTOR(5) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 6 +#define TIMER1_OVF_vect _VECTOR(6) +#define SIG_OVERFLOW1 _VECTOR(6) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 7 +#define TIMER0_OVF_vect _VECTOR(7) +#define SIG_OVERFLOW0 _VECTOR(7) + +/* Serial Transfer Complete */ +#define SPI_STC_vect_num 8 +#define SPI_STC_vect _VECTOR(8) +#define SIG_SPI _VECTOR(8) + +/* UART, Rx Complete */ +#define UART_RX_vect_num 9 +#define UART_RX_vect _VECTOR(9) +#define SIG_UART_RECV _VECTOR(9) + +/* UART Data Register Empty */ +#define UART_UDRE_vect_num 10 +#define UART_UDRE_vect _VECTOR(10) +#define SIG_UART_DATA _VECTOR(10) + +/* UART, Tx Complete */ +#define UART_TX_vect_num 11 +#define UART_TX_vect _VECTOR(11) +#define SIG_UART_TRANS _VECTOR(11) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 12 +#define ANA_COMP_vect _VECTOR(12) +#define SIG_COMPARATOR _VECTOR(12) + +#define _VECTORS_SIZE 26 + +/* + The Register Bit names are represented by their bit number (0-7). +*/ + +/* General Interrupt MaSK register */ +#define INT1 7 +#define INT0 6 + +/* General Interrupt Flag Register */ +#define INTF1 7 +#define INTF0 6 + +/* Timer/Counter Interrupt MaSK register */ +#define TOIE1 7 +#define OCIE1A 6 +#define OCIE1B 5 +#define TICIE1 3 +#define TOIE0 1 + +/* Timer/Counter Interrupt Flag register */ +#define TOV1 7 +#define OCF1A 6 +#define OCF1B 5 +#define ICF1 3 +#define TOV0 1 + +/* MCU general Control Register */ +#define SRE 7 +#define SRW 6 +#define SE 5 +#define SM 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/* Timer/Counter 0 Control Register */ +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* Timer/Counter 1 Control Register */ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define PWM11 1 +#define PWM10 0 + +/* Timer/Counter 1 Control and Status Register */ +#define ICNC1 7 +#define ICES1 6 +#define CTC1 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* Watchdog Timer Control Register */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* Data Register, Port A */ +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* Data Direction Register, Port A */ +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +/* Input Pins, Port A */ +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +/* Data Register, Port B */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Data Direction Register, Port B */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Input Pins, Port B */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* Data Register, Port C */ +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* Data Direction Register, Port C */ +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +/* Input Pins, Port C */ +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +/* Data Register, Port D */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* Data Direction Register, Port D */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* Input Pins, Port D */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* SPI Status Register */ +#define SPIF 7 +#define WCOL 6 + +/* SPI Control Register */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* UART Status Register */ +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 + +/* UART Control Register */ +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define CHR9 2 +#define RXB8 1 +#define TXB8 0 + +/* Analog Comparator Control and Status Register */ +#define ACD 7 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define RAMSTART 0x60 +#define RAMEND 0x25F /* Last On-Chip SRAM Location */ +#define XRAMEND 0xFFFF +#define E2END 0x1FF +#define E2PAGESIZE 0 +#define FLASHEND 0x1FFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 1 + +/* Low Fuse Byte */ +#define FUSE_SPIEN ~_BV(1) /* Serial Program Downloading Enabled */ +#define FUSE_FSTRT ~_BV(2) /* Short Start-up time selected */ +#define LFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x01 + +#define SLEEP_MODE_IDLE 0 +#define SLEEP_MODE_PWR_DOWN _BV(SM) + +#endif /* _AVR_IO8515_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/io8534.h b/hardware/tools/avr/avr/include/avr/io8534.h new file mode 100644 index 0000000000000000000000000000000000000000..63d4ad0b3a321ed6b03a127a0058625542109c78 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/io8534.h @@ -0,0 +1,217 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: io8534.h 1873 2009-02-11 17:53:39Z arcanum $ */ + +/* avr/io8534.h - definitions for AT90C8534 */ + +#ifndef _AVR_IO8534_ +#define _AVR_IO8534_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io8534.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* 0x00..0x03 reserved */ + +/* ADC Data Register */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) + +/* ADC Control and Status Register */ +#define ADCSR _SFR_IO8(0x06) + +/* ADC Multiplexer Select Register */ +#define ADMUX _SFR_IO8(0x07) + +/* 0x08..0x0F reserved */ + +/* General Interrupt Pin Register */ +#define GIPR _SFR_IO8(0x10) + +/* 0x11..0x19 reserved */ + +/* Data Direction Register, Port A */ +#define DDRA _SFR_IO8(0x1A) + +/* Data Register, Port A */ +#define PORTA _SFR_IO8(0x1B) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO16(0x1E) +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +/* 0x20..0x2B reserved */ + +/* Timer/Counter1 */ +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +/* Timer/Counter1 Control Register */ +#define TCCR1 _SFR_IO8(0x2E) + +/* 0x2F..0x31 reserved */ + +/* Timer/Counter0 (8-bit) */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* 0x34 reserved */ + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* 0x36..0x37 reserved */ + +/* Timer/Counter Interrupt Flag Register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK Register */ +#define TIMSK _SFR_IO8(0x39) + +/* General Interrupt Flag Register */ +#define GIFR _SFR_IO8(0x3A) + +/* General Interrupt MaSK register */ +#define GIMSK _SFR_IO8(0x3B) + +/* 0x3C reserved */ + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +#define SIG_INTERRUPT0 _VECTOR(1) +#define SIG_INTERRUPT1 _VECTOR(2) +#define SIG_OVERFLOW1 _VECTOR(3) +#define SIG_OVERFLOW0 _VECTOR(4) +#define SIG_ADC _VECTOR(5) +#define SIG_EEPROM_READY _VECTOR(6) + +#define _VECTORS_SIZE 14 + +/* Bit numbers */ + +/* GIMSK */ +#define INT1 7 +#define INT0 6 + +/* GIFR */ +#define INTF1 7 +#define INTF0 6 + +/* GIPR */ +#define IPIN1 3 +#define IPIN0 2 + +/* TIMSK */ +#define TOIE1 2 +#define TOIE0 0 + +/* TIFR */ +#define TOV1 2 +#define TOV0 0 + +/* MCUCR */ +#define SE 6 +#define SM 5 +#define ISC1 2 +#define ISC0 0 + +/* TCCR0 */ +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* TCCR1 */ +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* PORTA */ +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* DDRA */ +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Last memory addresses */ +#define RAMSTART 0x60 +#define RAMEND 0x15F +#define XRAMEND RAMEND +#define E2END 0x1FF +#define FLASHEND 0x1FFF + +#endif /* _AVR_IO8534_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/io8535.h b/hardware/tools/avr/avr/include/avr/io8535.h new file mode 100644 index 0000000000000000000000000000000000000000..df7784cbe33c8d4e2e4f6f3ddf553b8a4b0bd96c --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/io8535.h @@ -0,0 +1,589 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: io8535.h 2225 2011-03-02 16:27:26Z arcanum $ */ + +/* avr/io8535.h - definitions for AT90S8535 */ + +#ifndef _AVR_IO8535_H_ +#define _AVR_IO8535_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io8535.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* ADC Data register */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) + +/* ADC Control and Status Register */ +#define ADCSR _SFR_IO8(0x06) + +/* ADC MUX */ +#define ADMUX _SFR_IO8(0x07) + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) + +/* UART Baud Rate Register */ +#define UBRR _SFR_IO8(0x09) + +/* UART Control Register */ +#define UCR _SFR_IO8(0x0A) + +/* UART Status Register */ +#define USR _SFR_IO8(0x0B) + +/* UART I/O Data Register */ +#define UDR _SFR_IO8(0x0C) + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x0D) + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x0E) + +/* SPI I/O Data Register */ +#define SPDR _SFR_IO8(0x0F) + +/* Input Pins, Port D */ +#define PIND _SFR_IO8(0x10) + +/* Data Direction Register, Port D */ +#define DDRD _SFR_IO8(0x11) + +/* Data Register, Port D */ +#define PORTD _SFR_IO8(0x12) + +/* Input Pins, Port C */ +#define PINC _SFR_IO8(0x13) + +/* Data Direction Register, Port C */ +#define DDRC _SFR_IO8(0x14) + +/* Data Register, Port C */ +#define PORTC _SFR_IO8(0x15) + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* Input Pins, Port A */ +#define PINA _SFR_IO8(0x19) + +/* Data Direction Register, Port A */ +#define DDRA _SFR_IO8(0x1A) + +/* Data Register, Port A */ +#define PORTA _SFR_IO8(0x1B) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO16(0x1E) +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* Asynchronous mode Status Register */ +#define ASSR _SFR_IO8(0x22) + +/* Timer/Counter2 Output Compare Register */ +#define OCR2 _SFR_IO8(0x23) + +/* Timer/Counter 2 */ +#define TCNT2 _SFR_IO8(0x24) + +/* Timer/Counter 2 Control Register */ +#define TCCR2 _SFR_IO8(0x25) + +/* T/C 1 Input Capture Register */ +#define ICR1 _SFR_IO16(0x26) +#define ICR1L _SFR_IO8(0x26) +#define ICR1H _SFR_IO8(0x27) + +/* Timer/Counter1 Output Compare Register B */ +#define OCR1B _SFR_IO16(0x28) +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Timer/Counter1 Output Compare Register A */ +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Timer/Counter 1 */ +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +/* Timer/Counter 1 Control and Status Register */ +#define TCCR1B _SFR_IO8(0x2E) + +/* Timer/Counter 1 Control Register */ +#define TCCR1A _SFR_IO8(0x2F) + +/* Timer/Counter 0 */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter 0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU general Status Register */ +#define MCUSR _SFR_IO8(0x34) + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* Timer/Counter Interrupt Flag register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK register */ +#define TIMSK _SFR_IO8(0x39) + +/* General Interrupt Flag Register */ +#define GIFR _SFR_IO8(0x3A) + +/* General Interrupt MaSK register */ +#define GIMSK _SFR_IO8(0x3B) + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* Timer/Counter2 Compare Match */ +#define TIMER2_COMP_vect_num 3 +#define TIMER2_COMP_vect _VECTOR(3) +#define SIG_OUTPUT_COMPARE2 _VECTOR(3) + +/* Timer/Counter2 Overflow */ +#define TIMER2_OVF_vect_num 4 +#define TIMER2_OVF_vect _VECTOR(4) +#define SIG_OVERFLOW2 _VECTOR(4) + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect_num 5 +#define TIMER1_CAPT_vect _VECTOR(5) +#define SIG_INPUT_CAPTURE1 _VECTOR(5) + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect_num 6 +#define TIMER1_COMPA_vect _VECTOR(6) +#define SIG_OUTPUT_COMPARE1A _VECTOR(6) + +/* Timer/Counter1 Compare Match B */ +#define TIMER1_COMPB_vect_num 7 +#define TIMER1_COMPB_vect _VECTOR(7) +#define SIG_OUTPUT_COMPARE1B _VECTOR(7) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 8 +#define TIMER1_OVF_vect _VECTOR(8) +#define SIG_OVERFLOW1 _VECTOR(8) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 9 +#define TIMER0_OVF_vect _VECTOR(9) +#define SIG_OVERFLOW0 _VECTOR(9) + +/* SPI Serial Transfer Complete */ +#define SPI_STC_vect_num 10 +#define SPI_STC_vect _VECTOR(10) +#define SIG_SPI _VECTOR(10) + +/* UART, RX Complete */ +#define UART_RX_vect_num 11 +#define UART_RX_vect _VECTOR(11) +#define SIG_UART_RECV _VECTOR(11) + +/* UART Data Register Empty */ +#define UART_UDRE_vect_num 12 +#define UART_UDRE_vect _VECTOR(12) +#define SIG_UART_DATA _VECTOR(12) + +/* UART, TX Complete */ +#define UART_TX_vect_num 13 +#define UART_TX_vect _VECTOR(13) +#define SIG_UART_TRANS _VECTOR(13) + +/* ADC Conversion Complete */ +#define ADC_vect_num 14 +#define ADC_vect _VECTOR(14) +#define SIG_ADC _VECTOR(14) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 15 +#define EE_RDY_vect _VECTOR(15) +#define SIG_EEPROM_READY _VECTOR(15) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 16 +#define ANA_COMP_vect _VECTOR(16) +#define SIG_COMPARATOR _VECTOR(16) + +#define _VECTORS_SIZE 34 + +/* + The Register Bit names are represented by their bit number (0-7). +*/ + +/* MCU general Status Register */ +#define EXTRF 1 +#define PORF 0 + +/* General Interrupt MaSK register */ +#define INT1 7 +#define INT0 6 + +/* General Interrupt Flag Register */ +#define INTF1 7 +#define INTF0 6 + +/* Timer/Counter Interrupt MaSK register */ +#define OCIE2 7 +#define TOIE2 6 +#define TICIE1 5 +#define OCIE1A 4 +#define OCIE1B 3 +#define TOIE1 2 +#define TOIE0 0 + +/* Timer/Counter Interrupt Flag register */ +#define OCF2 7 +#define TOV2 6 +#define ICF1 5 +#define OCF1A 4 +#define OCF1B 3 +#define TOV1 2 +#define TOV0 0 + +/* MCU general Control Register */ +#define SE 6 +#define SM1 5 +#define SM0 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/* Timer/Counter 0 Control Register */ +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* Timer/Counter 1 Control Register */ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define PWM11 1 +#define PWM10 0 + +/* Timer/Counter 1 Control and Status Register */ +#define ICNC1 7 +#define ICES1 6 +#define CTC1 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* Timer/Counter 2 Control Register */ +#define PWM2 6 +#define COM21 5 +#define COM20 4 +#define CTC2 3 +#define CS22 2 +#define CS21 1 +#define CS20 0 + +/* Asynchronous mode Status Register */ +#define AS2 3 +#define TCN2UB 2 +#define OCR2UB 1 +#define TCR2UB 0 + +/* Watchdog Timer Control Register */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* Data Register, Port A */ +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* Data Direction Register, Port A */ +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +/* Input Pins, Port A */ +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +/* Data Register, Port B */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Data Direction Register, Port B */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Input Pins, Port B */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* Data Register, Port C */ +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* Data Direction Register, Port C */ +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +/* Input Pins, Port C */ +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +/* Data Register, Port D */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* Data Direction Register, Port D */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* Input Pins, Port D */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* SPI Control Register */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* SPI Status Register */ +#define SPIF 7 +#define WCOL 6 + +/* UART Status Register */ +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 + +/* UART Control Register */ +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define CHR9 2 +#define RXB8 1 +#define TXB8 0 + +/* Analog Comparator Control and Status Register */ +#define ACD 7 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +/* ADC MUX */ +#define MUX2 2 +#define MUX1 1 +#define MUX0 0 + +/* ADC Control and Status Register */ +#define ADEN 7 +#define ADSC 6 +#define ADFR 5 +#define ADIF 4 +#define ADIE 3 +#define ADPS2 2 +#define ADPS1 1 +#define ADPS0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define RAMSTART 0x60 +#define RAMEND 0x25F /*Last On-Chip SRAM location*/ +#define XRAMEND RAMEND +#define E2END 0x1FF +#define E2PAGESIZE 0 +#define FLASHEND 0x1FFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 1 + +/* Low Fuse Byte */ +#define FUSE_SPIEN (unsigned char)~_BV(1) /* Serial Program Downloading Enabled */ +#define FUSE_FSTRT (unsigned char)~_BV(2) /* Short Start-up time selected */ +#define LFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x03 + +#define SLEEP_MODE_IDLE 0 +#define SLEEP_MODE_ADC _BV(SM0) +#define SLEEP_MODE_PWR_DOWN _BV(SM1) +#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) + +#endif /* _AVR_IO8535_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/io86r401.h b/hardware/tools/avr/avr/include/avr/io86r401.h new file mode 100644 index 0000000000000000000000000000000000000000..f1c58eb482c2b00ea032501480d94c1c6983ed8c --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/io86r401.h @@ -0,0 +1,311 @@ +/* Copyright (c) 2002, Colin O'Flynn + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* avr/io86r401.h - definitions for AT86RF401 */ + +#ifndef _AVR_IO86RF401_H_ +#define _AVR_IO86RF401_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io86r401.h" +#else +# error "Attempt to include more than one file." +#endif + +#include + +/* Status REGister */ +#define SREG _SFR_IO8(0x3F) + +/* Stack Pointer */ +#define SP _SFR_IO16(0x3D) +#define SPH _SFR_IO8(0x3E) +#define SPL _SFR_IO8(0x3D) + +/*Battery low configeration register */ +#define BL_CONFIG _SFR_IO8(0x35) + +/*Button detect register*/ +#define B_DET _SFR_IO8(0x34) + +/*AVR Configeration register*/ +#define AVR_CONFIG _SFR_IO8(0x33) + +/* I/O registers */ + +/*Data in register */ +#define IO_DATIN _SFR_IO8(0x32) + +/*Data out register */ +#define IO_DATOUT _SFR_IO8(0x31) + +/*IO Enable register */ +#define IO_ENAB _SFR_IO8(0x30) + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x22) + +/* Bit Timer Control Register */ +#define BTCR _SFR_IO8(0x21) + +#define BTCNT _SFR_IO8(0x20) + +/* +NOTE: EEPROM name's changed to have D in front on them, per datasheet, but +you may want to remove the leading D. +*/ +/* EEPROM Control Register */ + +/* EEPROM Address Register */ +#define DEEAR _SFR_IO8(0x1E) +#define DEEARL _SFR_IO8(0x1E) + +/* EEPROM Data Register */ +#define DEEDR _SFR_IO8(0x1D) +/* EEPROM Control Register */ +#define DEECR _SFR_IO8(0x1C) + +/* Lock Detector Configuration Register 2 */ +#define LOCKDET2 _SFR_IO8(0x17) + +/* VCO Tuning Register*/ +#define VCOTUNE _SFR_IO8(0x16) + +/* Power Attenuation Control Register */ +#define PWR_ATTEN _SFR_IO8(0x14) + +/* Transmitter Control Register */ +#define TX_CNTL _SFR_IO8(0x12) + +/* Lock Detector Configuration Register 1 */ +#define LOCKDET1 _SFR_IO8(0x10) + + +/* Interrupt vectors */ + +/* Transmission Done, Bit Timer Flag 2 Interrupt */ +#define TXDONE_vect_num 1 +#define TXDONE_vect _VECTOR(1) +#define SIG_TXDONE _VECTOR(1) + +/* Transmit Buffer Empty, Bit Itmer Flag 0 Interrupt */ +#define TXEMPTY_vect_num 2 +#define TXEMPTY_vect _VECTOR(2) +#define SIG_TXBE _VECTOR(2) + +#define _VECTORS_SIZE 12 + +/* + * The Register Bit names are represented by their bit number (0-7). + */ + +/* Lock Detector Configuration Register 1 - LOCKDET1 */ +#define UPOK 4 +#define ENKO 3 +#define BOD 2 +#define CS1 1 +#define CS0 0 + +/* Transmit Control Register - TX_CNTL */ +#define TXE 5 +#define TXK 4 +#define LOC 2 + +/* Power Attenuation Control Register - PWR_ATTEN */ +#define PCC2 5 +#define PCC1 4 +#define PCC0 3 +#define PCF2 2 +#define PCF1 1 +#define PCF0 0 + +/* VCO Tuning Register 6 - VCOTUNE --NOTE: [] removed from names*/ +#define VCOVDET1 7 +#define VCOVDET0 6 +#define VCOTUNE4 4 +#define VCOTUNE3 3 +#define VCOTUNE2 2 +#define VCOTUNE1 1 +#define VCOTUNE0 0 + +/* Lock Detector Configuration Register 2 - LOCKDET2 --NOTE: [] removed from names*/ +#define EUD 7 +#define LAT 6 +#define ULC2 5 +#define ULC1 4 +#define ULC0 3 +#define LC2 2 +#define LC1 1 +#define LC0 0 + +/* Data EEPROM Control Register - DEECR */ +#define BSY 3 +#define EEU 2 +#define EEL 1 +#define EER 0 + +/* Data EEPROM Data Register - DEEDR */ +#define ED7 7 +#define ED6 6 +#define ED5 5 +#define ED4 4 +#define ED3 3 +#define ED2 2 +#define ED1 1 +#define ED0 0 + +/* Data EEPROM Address Register - DEEAR */ +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define BA2 2 /* B is not a typo! */ +#define BA1 1 +#define BA0 0 + +/* Bit Timer Count Register - BTCNT */ +#define C7 7 +#define C6 6 +#define C5 5 +#define C4 4 +#define C3 3 +#define C2 2 +#define C1 1 +#define C0 0 + +/* Bit Timer Control Register - BTCR */ +#define C9 7 +#define C8 6 +#define M1 5 +#define M0 4 +#define IE 3 +#define F2 2 +#define DATA 1 +#define F0 0 + +/* Watchdog Timer Control Register - WDTCR */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* I/O Enable Register - IO_ENAB */ +#define BOHYST 6 +#define IOE5 5 +#define IOE4 4 +#define IOE3 3 +#define IOE2 2 +#define IOE1 1 +#define IOE0 0 + +/* Note: No PORTB or whatever, this is the equivalent. */ +/* I/O Data Out Register - IO_DATOUT */ +#define IOO5 5 +#define IOO4 4 +#define IOO3 3 +#define IOO2 2 +#define IOO1 1 +#define IOO0 0 + +/* Note: No PINB or whatever, this is the equivalent. */ +/* I/O Data In Register - IO_DATIN */ +#define IOI5 5 +#define IOI4 4 +#define IOI3 3 +#define IOI2 2 +#define IOI1 1 +#define IOI0 0 + +/* AVR Configuration Register - AVR_CONFIG */ +#define ACS1 6 +#define ACS0 5 +#define TM 4 +#define BD 3 +#define BLI 2 +#define SLEEP 1 +#define BBM 0 + +/* Button Detect Register - B_DET */ +#define BD5 5 +#define BD4 4 +#define BD3 3 +#define BD2 2 +#define BD1 1 +#define BD0 0 + +/* Battery Low Configuration Register - BL_CONFIG */ +#define BL 7 +#define BLV 6 +#define BL5 5 +#define BL4 4 +#define BL3 3 +#define BL2 2 +#define BL1 1 +#define BL0 0 + +/* Pointer definition */ +#define XL r26 +#define XH r27 +#define YL r28 +#define YH r29 +#define ZL r30 +#define ZH r31 + +/* Constants */ +#define RAMSTART 0x60 +#define RAMEND 0xDF +#define XRAMEND RAMEND +#define E2END 0x7F +#define E2PAGESIZE 0 +#define FLASHEND 0x07FF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 0 + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x91 +#define SIGNATURE_2 0x81 + + +#endif /* _AVR_IO86RF401_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/io90pwm1.h b/hardware/tools/avr/avr/include/avr/io90pwm1.h new file mode 100644 index 0000000000000000000000000000000000000000..bdb64c2fe26c556a0e822b17ccd93eac4bfedbdb --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/io90pwm1.h @@ -0,0 +1,1157 @@ +/* Copyright (c) 2005, Andrey Pashchenko + Copyright (c) 2007, Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: io90pwm1.h 2225 2011-03-02 16:27:26Z arcanum $ */ + +/* avr/iopwm1.h - definitions for AT90PWM1 device */ + +#ifndef _AVR_IOPWM1_H_ +#define _AVR_IOPWM1_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iopwm1.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* Reserved [0x00..0x02] */ + +/* Port B Input Pins Address */ +#define PINB _SFR_IO8(0x03) +/* PINB */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* Port B Data Direction Register */ +#define DDRB _SFR_IO8(0x04) +/* DDRB */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Port B Data Register */ +#define PORTB _SFR_IO8(0x05) +/* PORTB */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Reserved [0x06..0x08] */ + +/* Port D Input Pins Address */ +#define PIND _SFR_IO8(0x09) +/* PIND */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* Port D Data Direction Register */ +#define DDRD _SFR_IO8(0x0A) +/* DDRD */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* Port D Data Register */ +#define PORTD _SFR_IO8(0x0B) +/* PORTD */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* Port E Input Pins Address */ +#define PINE _SFR_IO8(0x0C) +/* PINE */ +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +/* Port E Data Direction Register */ +#define DDRE _SFR_IO8(0x0D) +/* DDRE */ +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +/* Port E Data Register */ +#define PORTE _SFR_IO8(0x0E) +/* PORTE */ +#define PE2 2 +#define PE1 1 +#define PE0 0 + +/* Reserved [0x0F..0x14] */ + +/* Timer/Counter 0 Interrupt Flag Register */ +#define TIFR0 _SFR_IO8(0x15) +/* TIFR0 */ +#define OCF0B 2 /* Output Compare Flag 0B */ +#define OCF0A 1 /* Output Compare Flag 0A */ +#define TOV0 0 /* Overflow Flag */ + +/* Timer/Counter1 Interrupt Flag Register */ +#define TIFR1 _SFR_IO8(0x16) +/* TIFR1 */ +#define ICF1 5 /* Input Capture Flag 1 */ +#define OCF1B 2 /* Output Compare Flag 1B*/ +#define OCF1A 1 /* Output Compare Flag 1A*/ +#define TOV1 0 /* Overflow Flag */ + +/* Reserved [0x17..0x18] */ + +/* General Purpose I/O Register 1 */ +#define GPIOR1 _SFR_IO8(0x19) +/* GPIOR1 */ +#define GPIOR17 7 +#define GPIOR16 6 +#define GPIOR15 5 +#define GPIOR14 4 +#define GPIOR13 3 +#define GPIOR12 2 +#define GPIOR11 1 +#define GPIOR10 0 + +/* General Purpose I/O Register 2 */ +#define GPIOR2 _SFR_IO8(0x1A) +/* GPIOR2 */ +#define GPIOR27 7 +#define GPIOR26 6 +#define GPIOR25 5 +#define GPIOR24 4 +#define GPIOR23 3 +#define GPIOR22 2 +#define GPIOR21 1 +#define GPIOR20 0 + +/* General Purpose I/O Register 3 */ +#define GPIOR3 _SFR_IO8(0x1B) +/* GPIOR3 */ +#define GPIOR37 7 +#define GPIOR36 6 +#define GPIOR35 5 +#define GPIOR34 4 +#define GPIOR33 3 +#define GPIOR32 2 +#define GPIOR31 1 +#define GPIOR30 0 + +/* External Interrupt Flag Register */ +#define EIFR _SFR_IO8(0x1C) +/* EIFR */ +#define INTF3 3 +#define INTF2 2 +#define INTF1 1 +#define INTF0 0 + +/* External Interrupt Mask Register */ +#define EIMSK _SFR_IO8(0x1D) +/* EIMSK */ +#define INT3 3 /* External Interrupt Request 3 Enable */ +#define INT2 2 /* External Interrupt Request 2 Enable */ +#define INT1 1 /* External Interrupt Request 1 Enable */ +#define INT0 0 /* External Interrupt Request 0 Enable */ + +/* General Purpose I/O Register 0 */ +#define GPIOR0 _SFR_IO8(0x1E) +/* GPIOR0 */ +#define GPIOR07 7 +#define GPIOR06 6 +#define GPIOR05 5 +#define GPIOR04 4 +#define GPIOR03 3 +#define GPIOR02 2 +#define GPIOR01 1 +#define GPIOR00 0 + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1F) +/* EECR */ +#define EERIE 3 /* EEPROM Ready Interrupt Enable */ +#define EEMWE 2 /* EEPROM Master Write Enable */ +#define EEWE 1 /* EEPROM Write Enable */ +#define EERE 0 /* EEPROM Read Enable */ + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x20) +/* EEDR */ +#define EEDR7 7 +#define EEDR6 6 +#define EEDR5 5 +#define EEDR4 4 +#define EEDR3 3 +#define EEDR2 2 +#define EEDR1 1 +#define EEDR0 0 + +/* The EEPROM Address Registers */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) +/* EEARH */ +#define EEAR11 3 +#define EEAR10 2 +#define EEAR9 1 +#define EEAR8 0 +/* EEARL */ +#define EEAR7 7 +#define EEAR6 6 +#define EEAR5 5 +#define EEAR4 4 +#define EEAR3 3 +#define EEAR2 2 +#define EEAR1 1 +#define EEAR0 0 + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +/* General Timer/Counter Control Register */ +#define GTCCR _SFR_IO8(0x23) +/* GTCCR */ +#define TSM 7 /* Timer/Counter Synchronization Mode */ +#define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ +#define PSRSYNC 0 + +/* Timer/Counter Control Register A */ +#define TCCR0A _SFR_IO8(0x24) +/* TCCR0A */ +#define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ +#define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ +#define COM0B1 5 /* Compare Output Mode, Fast PWm */ +#define COM0B0 4 /* Compare Output Mode, Fast PWm */ +#define WGM01 1 /* Waveform Generation Mode */ +#define WGM00 0 /* Waveform Generation Mode */ + +/* Timer/Counter Control Register B */ +#define TCCR0B _SFR_IO8(0x25) +/* TCCR0B */ +#define FOC0A 7 /* Force Output Compare A */ +#define FOC0B 6 /* Force Output Compare B */ +#define WGM02 3 /* Waveform Generation Mode */ +#define CS02 2 /* Clock Select */ +#define CS01 1 /* Clock Select */ +#define CS00 0 /* Clock Select */ + +/* Timer/Counter0 Register */ +#define TCNT0 _SFR_IO8(0x26) +/* TCNT0 */ +#define TCNT07 7 +#define TCNT06 6 +#define TCNT05 5 +#define TCNT04 4 +#define TCNT03 3 +#define TCNT02 2 +#define TCNT01 1 +#define TCNT00 0 + +/* Timer/Counter0 Output Compare Register A */ +#define OCR0A _SFR_IO8(0x27) +/* OCR0A */ +#define OCR0A7 7 +#define OCR0A6 6 +#define OCR0A5 5 +#define OCR0A4 4 +#define OCR0A3 3 +#define OCR0A2 2 +#define OCR0A1 1 +#define OCR0A0 0 + +/* Timer/Counter0 Output Compare Register B */ +#define OCR0B _SFR_IO8(0x28) +/* OCR0B */ +#define OCR0B7 7 +#define OCR0B6 6 +#define OCR0B5 5 +#define OCR0B4 4 +#define OCR0B3 3 +#define OCR0B2 2 +#define OCR0B1 1 +#define OCR0B0 0 + +/* PLL Control and Status Register */ +#define PLLCSR _SFR_IO8(0x29) +/* PLLCSR */ +#define PLLF 2 +#define PLLE 1 /* PLL Enable */ +#define PLOCK 0 /* PLL Lock Detector */ + +/* Reserved [0x2A..0x2B] */ + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x2C) +/* SPCR */ +#define SPIE 7 /* SPI Interrupt Enable */ +#define SPE 6 /* SPI Enable */ +#define DORD 5 /* Data Order */ +#define MSTR 4 /* Master/Slave Select */ +#define CPOL 3 /* Clock polarity */ +#define CPHA 2 /* Clock Phase */ +#define SPR1 1 /* SPI Clock Rate Select 1 */ +#define SPR0 0 /* SPI Clock Rate Select 0 */ + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x2D) +/* SPSR */ +#define SPIF 7 /* SPI Interrupt Flag */ +#define WCOL 6 /* Write Collision Flag */ +#define SPI2X 0 /* Double SPI Speed Bit */ + +/* SPI Data Register */ +#define SPDR _SFR_IO8(0x2E) +/* SPDR */ +#define SPD7 7 +#define SPD6 6 +#define SPD5 5 +#define SPD4 4 +#define SPD3 3 +#define SPD2 2 +#define SPD1 1 +#define SPD0 0 + +/* Reserved [0x2F] */ + +/* Analog Comparator Status Register */ +#define ACSR _SFR_IO8(0x30) +/* ACSR */ +#define ACCKDIV 7 /* Analog Comparator Clock Divider */ +#define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ +#define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ +#define AC2O 2 /* Analog Comparator 2 Output Bit */ +#define AC0O 0 /* Analog Comparator 0 Output Bit */ + +/* Monitor Data Register */ +#define MONDR _SFR_IO8(0x31) + +/* Monitor Stop Mode Control Register */ +#define MSMCR _SFR_IO8(0x32) + +/* Sleep Mode Control Register */ +#define SMCR _SFR_IO8(0x33) +/* SMCR */ +#define SM2 3 /* Sleep Mode Select bit2 */ +#define SM1 2 /* Sleep Mode Select bit1 */ +#define SM0 1 /* Sleep Mode Select bit0 */ +#define SE 0 /* Sleep Enable */ + +/* MCU Status Register */ +#define MCUSR _SFR_IO8(0x34) +/* MCUSR */ +#define WDRF 3 /* Watchdog Reset Flag */ +#define BORF 2 /* Brown-out Reset Flag */ +#define EXTRF 1 /* External Reset Flag */ +#define PORF 0 /* Power-on reset flag */ + +/* MCU Control Register */ +#define MCUCR _SFR_IO8(0x35) +/* MCUCR */ +#define SPIPS 7 /* SPI Pin Select */ +#define PUD 4 /* Pull-up disable */ +#define IVSEL 1 /* Interrupt Vector Select */ +#define IVCE 0 /* Interrupt Vector Change Enable */ + +/* Reserved [0x36] */ + +/* Store Program Memory Control Register */ +#define SPMCSR _SFR_IO8(0x37) +/* SPMCSR */ +#define SPMIE 7 /* SPM Interrupt Enable */ +#define RWWSB 6 /* Read While Write Section Busy */ +#define RWWSRE 4 /* Read While Write section read enable */ +#define BLBSET 3 /* Boot Lock Bit Set */ +#define PGWRT 2 /* Page Write */ +#define PGERS 1 /* Page Erase */ +#define SPMEN 0 /* Store Program Memory Enable */ + +/* Reserved [0x38..0x3C] */ + +/* 0x3D..0x3E SP [defined in ] */ +/* 0x3F SREG [defined in ] */ + +/* Watchdog Timer Control Register */ +#define WDTCSR _SFR_MEM8(0x60) +/* WDTCSR */ +#define WDIF 7 /* Watchdog Timeout Interrupt Flag */ +#define WDIE 6 /* Watchdog Timeout Interrupt Enable */ +#define WDP3 5 /* Watchdog Timer Prescaler bit3 */ +#define WDCE 4 /* Watchdog Change Enable */ +#define WDE 3 /* Watchdog Enable */ +#define WDP2 2 /* Watchdog Timer Prescaler bit2 */ +#define WDP1 1 /* Watchdog Timer Prescaler bit1 */ +#define WDP0 0 /* Watchdog Timer Prescaler bit0 */ + +/* Clock Prescaler Register */ +#define CLKPR _SFR_MEM8(0x61) +/* CLKPR */ +#define CLKPCE 7 /* Clock Prescaler Change Enable */ +#define CLKPS3 3 /* Clock Prescaler Select bit3 */ +#define CLKPS2 2 /* Clock Prescaler Select bit2 */ +#define CLKPS1 1 /* Clock Prescaler Select bit1 */ +#define CLKPS0 0 /* Clock Prescaler Select bit0 */ + +/* Reserved [0x62..0x63] */ + +/* Power Reduction Register */ +#define PRR _SFR_MEM8(0x64) +/* PRR */ +#define PRPSC2 7 /* Power Reduction PSC2 */ +#define PRPSC1 6 /* Power Reduction PSC1 */ +#define PRPSC0 5 /* Power Reduction PSC0 */ +#define PRTIM1 4 /* Power Reduction Timer/Counter1 */ +#define PRTIM0 3 /* Power Reduction Timer/Counter0 */ +#define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ +#define PRADC 0 /* Power Reduction ADC */ + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io90pwm161.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define ACSR _SFR_IO8(0x00) +#define AC1O 1 +#define AC2O 2 +#define AC3O 3 +#define AC1IF 5 +#define AC2IF 6 +#define AC3IF 7 + +#define TIMSK1 _SFR_IO8(0x01) +#define TOIE1 0 +#define ICIE1 5 + +#define TIFR1 _SFR_IO8(0x02) +#define TOV1 0 +#define ICF1 5 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define ADCSRA _SFR_IO8(0x06) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +#define ADCSRB _SFR_IO8(0x07) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 +#define ADTS3 3 +#define ADSSEN 4 +#define ADNCDIS 6 +#define ADHSM 7 + +#define ADMUX _SFR_IO8(0x08) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define ADLAR 5 +#define REFS0 6 +#define REFS1 7 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PIM0 _SFR_IO8(0x0F) +#define PEOPE0 0 +#define PEOEPE0 1 +#define PEVE0A 3 +#define PEVE0B 4 + +#define PIFR0 _SFR_IO8(0x10) +#define PEOP0 0 +#define PRN00 1 +#define PRN01 2 +#define PEV0A 3 +#define PEV0B 4 +#define POAC0A 6 +#define POAC0B 7 + +#define PCNF0 _SFR_IO8(0x11) +#define PCLKSEL0 1 +#define POP0 2 +#define PMODE00 3 +#define PMODE01 4 +#define PLOCK0 5 +#define PALOCK0 6 +#define PFIFTY0 7 + +#define PCTL0 _SFR_IO8(0x12) +#define PRUN0 0 +#define PCCYC0 1 +#define PAOC0A 3 +#define PAOC0B 4 +#define PBFM00 2 +#define PBFM01 5 +#define PPRE00 6 +#define PPRE01 7 + +#define PIM2 _SFR_IO8(0x13) +#define PEOPE2 0 +#define PEOEPE2 1 +#define PEVE2A 3 +#define PEVE2B 4 +#define PSEIE2 5 + +#define PIFR2 _SFR_IO8(0x14) +#define PEOP2 0 +#define PRN20 1 +#define PRN21 2 +#define PEV2A 3 +#define PEV2B 4 +#define PSEI2 5 +#define POAC2A 6 +#define POAC2B 7 + +#define PCNF2 _SFR_IO8(0x15) +#define POME2 0 +#define PCLKSEL2 1 +#define POP2 2 +#define PMODE20 3 +#define PMODE21 4 +#define PLOCK2 5 +#define PALOCK2 6 +#define PFIFTY2 7 + +#define PCTL2 _SFR_IO8(0x16) +#define PRUN2 0 +#define PCCYC2 1 +#define PARUN2 2 +#define PAOC2A 3 +#define PAOC2B 4 +#define PBFM2 5 +#define PPRE20 6 +#define PPRE21 7 + +#define SPCR _SFR_IO8(0x17) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x18) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define GPIOR0 _SFR_IO8(0x19) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define GPIOR1 _SFR_IO8(0x1A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x1B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 +#define EEPAGE 6 +#define NVMBSY 7 + +#define EEDR _SFR_IO8(0x1D) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x1E) + +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +#define EIFR _SFR_IO8(0x20) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 + +#define EIMSK _SFR_IO8(0x21) +#define INT0 0 +#define INT1 1 +#define INT2 2 + +/* Combine OCR0SBL and OCR0SBH */ +#define OCR0SB _SFR_IO16(0x22) + +#define OCR0SBL _SFR_IO8(0x22) +#define OCR0SBH _SFR_IO8(0x23) + +/* Combine OCR0RBL and OCR0RBH */ +#define OCR0RB _SFR_IO16(0x24) + +#define OCR0RBL _SFR_IO8(0x24) +#define OCR0RBH _SFR_IO8(0x25) + +/* Combine OCR2SBL and OCR2SBH */ +#define OCR2SB _SFR_IO16(0x26) + +#define OCR2SBL _SFR_IO8(0x26) +#define OCR2SBH _SFR_IO8(0x27) + +/* Combine OCR2RBL and OCR2RBH */ +#define OCR2RB _SFR_IO16(0x28) + +#define OCR2RBL _SFR_IO8(0x28) +#define OCR2RBH _SFR_IO8(0x29) + +/* Combine OCR0RAL and OCR0RAH */ +#define OCR0RA _SFR_IO16(0x2A) + +#define OCR0RAL _SFR_IO8(0x2A) +#define OCR0RAH _SFR_IO8(0x2B) + +/* Combine ADCL and ADCH */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x2C) +#endif +#define ADCW _SFR_IO16(0x2C) + +#define ADCL _SFR_IO8(0x2C) +#define ADCH _SFR_IO8(0x2D) + +/* Combine OCR2RAL and OCR2RAH */ +#define OCR2RA _SFR_IO16(0x2E) + +#define OCR2RAL _SFR_IO8(0x2E) +#define OCR2RAH _SFR_IO8(0x2F) + +/* Reserved [0x30..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define CKRC81 2 +#define RSTDIS 3 +#define PUD 4 + +#define SPDR _SFR_IO8(0x36) + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define DACL _SFR_IO8(0x38) +#define DACL0 0 +#define DACL1 1 +#define DACL2 2 +#define DACL3 3 +#define DACL4 4 +#define DACL5 5 +#define DACL6 6 +#define DACL7 7 + +#define DACH _SFR_IO8(0x39) +#define DACH0 0 +#define DACH1 1 +#define DACH2 2 +#define DACH3 3 +#define DACH4 4 +#define DACH5 5 +#define DACH6 6 +#define DACH7 7 + +/* Combine TCNT1L and TCNT1H */ +#define TCNT1 _SFR_IO16(0x3A) + +#define TCNT1L _SFR_IO8(0x3A) +#define TCNT1H _SFR_IO8(0x3B) + +/* Reserved [0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +/* Combine OCR0SAL and OCR0SAH */ +#define OCR0SA _SFR_MEM16(0x60) + +#define OCR0SAL _SFR_MEM8(0x60) +#define OCR0SAH _SFR_MEM8(0x61) + +#define PFRC0A _SFR_MEM8(0x62) +#define PRFM0A0 0 +#define PRFM0A1 1 +#define PRFM0A2 2 +#define PRFM0A3 3 +#define PFLTE0A 4 +#define PELEV0A 5 +#define PISEL0A 6 +#define PCAE0A 7 + +#define PFRC0B _SFR_MEM8(0x63) +#define PRFM0B0 0 +#define PRFM0B1 1 +#define PRFM0B2 2 +#define PRFM0B3 3 +#define PFLTE0B 4 +#define PELEV0B 5 +#define PISEL0B 6 +#define PCAE0B 7 + +/* Combine OCR2SAL and OCR2SAH */ +#define OCR2SA _SFR_MEM16(0x64) + +#define OCR2SAL _SFR_MEM8(0x64) +#define OCR2SAH _SFR_MEM8(0x65) + +#define PFRC2A _SFR_MEM8(0x66) +#define PRFM2A0 0 +#define PRFM2A1 1 +#define PRFM2A2 2 +#define PRFM2A3 3 +#define PFLTE2A 4 +#define PELEV2A 5 +#define PISEL2A 6 +#define PCAE2A 7 + +#define PFRC2B _SFR_MEM8(0x67) +#define PRFM2B0 0 +#define PRFM2B1 1 +#define PRFM2B2 2 +#define PRFM2B3 3 +#define PFLTE2B 4 +#define PELEV2B 5 +#define PISEL2B 6 +#define PCAE2B 7 + +/* Combine PICR0L and PICR0H */ +#define PICR0 _SFR_MEM16(0x68) + +#define PICR0L _SFR_MEM8(0x68) +#define PICR0H _SFR_MEM8(0x69) + +#define PSOC0 _SFR_MEM8(0x6A) +#define POEN0A 0 +#define POEN0B 2 +#define PSYNC00 4 +#define PSYNC01 5 +#define PISEL0B1 6 +#define PISEL0A1 7 + +/* Reserved [0x6B] */ + +#define PICR2L _SFR_MEM8(0x6C) + +#define PICR2H _SFR_MEM8(0x6D) +#define PICR28 0 +#define PICR29 1 +#define PICR210 2 +#define PICR211 3 +#define PCST2 7 + +#define PSOC2 _SFR_MEM8(0x6E) +#define POEN2A 0 +#define POEN2C 1 +#define POEN2B 2 +#define POEN2D 3 +#define PSYNC20 4 +#define PSYNC21 5 +#define POS22 6 +#define POS23 7 + +#define POM2 _SFR_MEM8(0x6F) +#define POMV2A0 0 +#define POMV2A1 1 +#define POMV2A2 2 +#define POMV2A3 3 +#define POMV2B0 4 +#define POMV2B1 5 +#define POMV2B2 6 +#define POMV2B3 7 + +#define PCNFE2 _SFR_MEM8(0x70) +#define PISEL2B1 0 +#define PISEL2A1 1 +#define PELEV2B1 2 +#define PELEV2A1 3 +#define PBFM21 4 +#define PASDLK20 5 +#define PASDLK21 6 +#define PASDLK22 7 + +#define PASDLY2 _SFR_MEM8(0x71) + +/* Reserved [0x72..0x75] */ + +#define DACON _SFR_MEM8(0x76) +#define DAEN 0 +#define DALA 2 +#define DATS0 4 +#define DATS1 5 +#define DATS2 6 +#define DAATE 7 + +#define DIDR0 _SFR_MEM8(0x77) +#define ADC0D 0 +#define ADC1D 1 +#define ADC2D 2 +#define ADC3D 3 +#define ADC4D 4 +#define ADC5D 5 +#define ADC6D 6 +#define ADC7D 7 + +#define DIDR1 _SFR_MEM8(0x78) +#define ADC9D 0 +#define ADC10D 1 +#define AMP0POSD 2 +#define ACMP1MD 3 + +#define AMP0CSR _SFR_MEM8(0x79) +#define AMP0TS0 0 +#define AMP0TS1 1 +#define AMP0GS 3 +#define AMP0G0 4 +#define AMP0G1 5 +#define AMP0IS 6 +#define AMP0EN 7 + +#define AC1ECON _SFR_MEM8(0x7A) +#define AC1H0 0 +#define AC1H1 1 +#define AC1H2 2 +#define AC1ICE 3 +#define AC1OE 4 +#define AC1OI 5 + +#define AC2ECON _SFR_MEM8(0x7B) +#define AC2H0 0 +#define AC2H1 1 +#define AC2H2 2 +#define AC2OE 4 +#define AC2OI 5 + +#define AC3ECON _SFR_MEM8(0x7C) +#define AC3H0 0 +#define AC3H1 1 +#define AC3H2 2 +#define AC3OE 4 +#define AC3OI 5 + +#define AC1CON _SFR_MEM8(0x7D) +#define AC1M0 0 +#define AC1M1 1 +#define AC1M2 2 +#define AC1IS0 4 +#define AC1IS1 5 +#define AC1IE 6 +#define AC1EN 7 + +#define AC2CON _SFR_MEM8(0x7E) +#define AC2M0 0 +#define AC2M1 1 +#define AC2M2 2 +#define AC2IS0 4 +#define AC2IS1 5 +#define AC2IE 6 +#define AC2EN 7 + +#define AC3CON _SFR_MEM8(0x7F) +#define AC3M0 0 +#define AC3M1 1 +#define AC3M2 2 +#define AC3OEA 3 +#define AC3IS0 4 +#define AC3IS1 5 +#define AC3IE 6 +#define AC3EN 7 + +#define BGCRR _SFR_MEM8(0x80) +#define BGCR0 0 +#define BGCR1 1 +#define BGCR2 2 +#define BGCR3 3 + +#define BGCCR _SFR_MEM8(0x81) +#define BGCC0 0 +#define BGCC1 1 +#define BGCC2 2 +#define BGCC3 3 + +#define WDTCSR _SFR_MEM8(0x82) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x83) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define CLKCSR _SFR_MEM8(0x84) +#define CLKC0 0 +#define CLKC1 1 +#define CLKC2 2 +#define CLKC3 3 +#define CLKRDY 4 +#define CLKCCE 7 + +#define CLKSELR _SFR_MEM8(0x85) +#define CKSEL0 0 +#define CKSEL1 1 +#define CKSEL2 2 +#define CKSEL3 3 +#define CSUT0 4 +#define CSUT1 5 +#define COUT 6 + +#define PRR _SFR_MEM8(0x86) +#define PRADC 0 +#define PRSPI 2 +#define PRTIM1 4 +#define PRPSCR 5 +#define PRPSC2 7 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io90pwm216.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* Port B Input Pins Address */ +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +/* Port B Data Direction Register */ +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +/* Port B Data Register */ +#define PORTB _SFR_IO8(0x05) +#define PB0 0 +#define PB1 1 +#define PB2 2 +#define PB3 3 +#define PB4 4 +#define PB5 5 +#define PB6 6 +#define PB7 7 + +/* Port C Input Pins Address */ +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +/* Port C Data Direction Register */ +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +/* Port C Data Register */ +#define PORTC _SFR_IO8(0x08) +#define PC0 0 +#define PC1 1 +#define PC2 2 +#define PC3 3 +#define PC4 4 +#define PC5 5 +#define PC6 6 +#define PC7 7 + +/* Port D Input Pins Address */ +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +/* Port D Data Direction Register */ +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +/* Port D Data Register */ +#define PORTD _SFR_IO8(0x0B) +#define PD0 0 +#define PD1 1 +#define PD2 2 +#define PD3 3 +#define PD4 4 +#define PD5 5 +#define PD6 6 +#define PD7 7 + +/* Port E Input Pins Address */ +#define PINE _SFR_IO8(0x0C) +#define PINE0 0 +#define PINE1 1 +#define PINE2 2 + +/* Port E Data Direction Register */ +#define DDRE _SFR_IO8(0x0D) +#define DDE0 0 +#define DDE1 1 +#define DDE2 2 + +/* Port E Data Register */ +#define PORTE _SFR_IO8(0x0E) +#define PE0 0 +#define PE1 1 +#define PE2 2 + +/* Timer/Counter 0 Interrupt Flag Register */ +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 /* Overflow Flag */ +#define OCF0A 1 /* Output Compare Flag 0A */ +#define OCF0B 2 /* Output Compare Flag 0B */ + +/* Timer/Counter1 Interrupt Flag Register */ +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 /* Overflow Flag */ +#define OCF1A 1 /* Output Compare Flag 1A*/ +#define OCF1B 2 /* Output Compare Flag 1B*/ +#define ICF1 5 /* Input Capture Flag 1 */ + +/* General Purpose I/O Register 1 */ +#define GPIOR1 _SFR_IO8(0x19) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +/* General Purpose I/O Register 2 */ +#define GPIOR2 _SFR_IO8(0x1A) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +/* General Purpose I/O Register 3 */ +#define GPIOR3 _SFR_IO8(0x1B) +#define GPIOR30 0 +#define GPIOR31 1 +#define GPIOR32 2 +#define GPIOR33 3 +#define GPIOR34 4 +#define GPIOR35 5 +#define GPIOR36 6 +#define GPIOR37 7 + +/* External Interrupt Flag Register */ +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 + +/* External Interrupt Mask Register */ +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 /* External Interrupt Request 0 Enable */ +#define INT1 1 /* External Interrupt Request 1 Enable */ +#define INT2 2 /* External Interrupt Request 2 Enable */ +#define INT3 3 /* External Interrupt Request 3 Enable */ + +/* General Purpose I/O Register 0 */ +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1F) +#define EERE 0 /* EEPROM Read Enable */ +#define EEWE 1 /* EEPROM Write Enable */ +#define EEMWE 2 /* EEPROM Master Write Enable */ +#define EERIE 3 /* EEPROM Ready Interrupt Enable */ + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +/* The EEPROM Address Registers */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 +#define EEAR10 2 +#define EEAR11 3 + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +/* General Timer/Counter Control Register */ +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */ +#define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ +#define TSM 7 /* Timer/Counter Synchronization Mode */ + +/* Timer/Counter Control Register A */ +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 /* Waveform Generation Mode */ +#define WGM01 1 /* Waveform Generation Mode */ +#define COM0B0 4 /* Compare Output Mode, Fast PWm */ +#define COM0B1 5 /* Compare Output Mode, Fast PWm */ +#define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ +#define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ + +/* Timer/Counter Control Register B */ +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 /* Clock Select */ +#define CS01 1 /* Clock Select */ +#define CS02 2 /* Clock Select */ +#define WGM02 3 /* Waveform Generation Mode */ +#define FOC0B 6 /* Force Output Compare B */ +#define FOC0A 7 /* Force Output Compare A */ + +/* Timer/Counter0 Register */ +#define TCNT0 _SFR_IO8(0x26) +#define TCNT00 0 +#define TCNT01 1 +#define TCNT02 2 +#define TCNT03 3 +#define TCNT04 4 +#define TCNT05 5 +#define TCNT06 6 +#define TCNT07 7 + +/* Timer/Counter0 Output Compare Register A */ +#define OCR0A _SFR_IO8(0x27) +#define OCR0A0 0 +#define OCR0A1 1 +#define OCR0A2 2 +#define OCR0A3 3 +#define OCR0A4 4 +#define OCR0A5 5 +#define OCR0A6 6 +#define OCR0A7 7 + +/* Timer/Counter0 Output Compare Register B */ +#define OCR0B _SFR_IO8(0x28) +#define OCR0B0 0 +#define OCR0B1 1 +#define OCR0B2 2 +#define OCR0B3 3 +#define OCR0B4 4 +#define OCR0B5 5 +#define OCR0B6 6 +#define OCR0B7 7 + +/* PLL Control and Status Register */ +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 /* PLL Lock Detector */ +#define PLLE 1 /* PLL Enable */ +#define PLLF 2 /* PLL Factor */ + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 /* SPI Clock Rate Select 0 */ +#define SPR1 1 /* SPI Clock Rate Select 1 */ +#define CPHA 2 /* Clock Phase */ +#define CPOL 3 /* Clock polarity */ +#define MSTR 4 /* Master/Slave Select */ +#define DORD 5 /* Data Order */ +#define SPE 6 /* SPI Enable */ +#define SPIE 7 /* SPI Interrupt Enable */ + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 /* Double SPI Speed Bit */ +#define WCOL 6 /* Write Collision Flag */ +#define SPIF 7 /* SPI Interrupt Flag */ + +/* SPI Data Register */ +#define SPDR _SFR_IO8(0x2E) +#define SPD0 0 +#define SPD1 1 +#define SPD2 2 +#define SPD3 3 +#define SPD4 4 +#define SPD5 5 +#define SPD6 6 +#define SPD7 7 + +/* Analog Comparator Status Register */ +#define ACSR _SFR_IO8(0x30) +#define AC0O 0 /* Analog Comparator 0 Output Bit */ +#define AC1O 1 /* Analog Comparator 1 Output Bit */ +#define AC2O 2 /* Analog Comparator 2 Output Bit */ +#define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ +#define AC1IF 5 /* Analog Comparator 1 Interrupt Flag Bit */ +#define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ +#define ACCKDIV 7 /* Analog Comparator Clock Divider */ + +/* Sleep Mode Control Register */ +#define SMCR _SFR_IO8(0x33) +#define SE 0 /* Sleep Enable */ +#define SM0 1 /* Sleep Mode Select bit0 */ +#define SM1 2 /* Sleep Mode Select bit1 */ +#define SM2 3 /* Sleep Mode Select bit2 */ + +/* MCU Status Register */ +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 /* Power-on reset flag */ +#define EXTRF 1 /* External Reset Flag */ +#define BORF 2 /* Brown-out Reset Flag */ +#define WDRF 3 /* Watchdog Reset Flag */ + +/* MCU Control Register */ +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 /* Interrupt Vector Change Enable */ +#define IVSEL 1 /* Interrupt Vector Select */ +#define PUD 4 /* Pull-up disable */ +#define SPIPS 7 /* SPI Pin Select */ + +/* Store Program Memory Control Register */ +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 /* Store Program Memory Enable */ +#define PGERS 1 /* Page Erase */ +#define PGWRT 2 /* Page Write */ +#define BLBSET 3 /* Boot Lock Bit Set */ +#define RWWSRE 4 /* Read While Write section read enable */ +#define RWWSB 6 /* Read While Write Section Busy */ +#define SPMIE 7 /* SPM Interrupt Enable */ + +/* Watchdog Timer Control Register */ +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 /* Watchdog Timer Prescaler bit0 */ +#define WDP1 1 /* Watchdog Timer Prescaler bit1 */ +#define WDP2 2 /* Watchdog Timer Prescaler bit2 */ +#define WDE 3 /* Watchdog Enable */ +#define WDCE 4 /* Watchdog Change Enable */ +#define WDP3 5 /* Watchdog Timer Prescaler bit3 */ +#define WDIE 6 /* Watchdog Timeout Interrupt Enable */ +#define WDIF 7 /* Watchdog Timeout Interrupt Flag */ + +/* Clock Prescaler Register */ +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 /* Clock Prescaler Select bit0 */ +#define CLKPS1 1 /* Clock Prescaler Select bit1 */ +#define CLKPS2 2 /* Clock Prescaler Select bit2 */ +#define CLKPS3 3 /* Clock Prescaler Select bit3 */ +#define CLKPCE 7 /* Clock Prescaler Change Enable */ + +/* Power Reduction Register */ +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 /* Power Reduction ADC */ +#define PRUSART0 1 /* Power Reduction USART0 */ +#define PRUSART PRUSART0 /* Define to maintain backward-compatibility */ +#define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ +#define PRTIM0 3 /* Power Reduction Timer/Counter0 */ +#define PRTIM1 4 /* Power Reduction Timer/Counter1 */ +#define PRPSC0 5 /* Power Reduction PSC0 */ +#define PRPSC1 6 /* Power Reduction PSC1 */ +#define PRPSC2 7 /* Power Reduction PSC2 */ + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io90pwm2b.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_IO90PWM2B_H_ +#define _AVR_IO90PWM2B_H_ 1 + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define PINE _SFR_IO8(0x0C) +#define PINE0 0 +#define PINE1 1 +#define PINE2 2 + +#define DDRE _SFR_IO8(0x0D) +#define DDE0 0 +#define DDE1 1 +#define DDE2 2 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE0 0 +#define PORTE1 1 +#define PORTE2 2 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define GPIOR1 _SFR_IO8(0x19) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x1A) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define GPIOR3 _SFR_IO8(0x1B) +#define GPIOR30 0 +#define GPIOR31 1 +#define GPIOR32 2 +#define GPIOR33 3 +#define GPIOR34 4 +#define GPIOR35 5 +#define GPIOR36 6 +#define GPIOR37 7 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARL0 0 +#define EEARL1 1 +#define EEARL2 2 +#define EEARL3 3 +#define EEARL4 4 +#define EEARL5 5 +#define EEARL6 6 +#define EEARL7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 +#define EEAR10 2 +#define EEAR11 3 + +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 +#define PSRSYNC 0 +#define ICPSEL1 2 +#define TSM 3 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define OCR0_0 0 /* Deprecated */ +#define OCR0_1 1 /* Deprecated */ +#define OCR0_2 2 /* Deprecated */ +#define OCR0_3 3 /* Deprecated */ +#define OCR0_4 4 /* Deprecated */ +#define OCR0_5 5 /* Deprecated */ +#define OCR0_6 6 /* Deprecated */ +#define OCR0_7 7 /* Deprecated */ + +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 +#define PLLE 1 +#define PLLF 2 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define AC0O 0 +#define AC1O 1 +#define AC2O 2 +#define AC0IF 4 +#define AC1IF 5 +#define AC2IF 6 +#define ACCKDIV 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define SPIPS 7 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM0 3 +#define PRTIM1 4 +#define PRPSC0 5 +#define PRPSC1 6 +#define PRPSC2 7 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io90pwm316.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* Port B Input Pins Address */ +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +/* Port B Data Direction Register */ +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +/* Port B Data Register */ +#define PORTB _SFR_IO8(0x05) +#define PB0 0 +#define PB1 1 +#define PB2 2 +#define PB3 3 +#define PB4 4 +#define PB5 5 +#define PB6 6 +#define PB7 7 + +/* Port C Input Pins Address */ +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +/* Port C Data Direction Register */ +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +/* Port C Data Register */ +#define PORTC _SFR_IO8(0x08) +#define PC0 0 +#define PC1 1 +#define PC2 2 +#define PC3 3 +#define PC4 4 +#define PC5 5 +#define PC6 6 +#define PC7 7 + +/* Port D Input Pins Address */ +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +/* Port D Data Direction Register */ +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +/* Port D Data Register */ +#define PORTD _SFR_IO8(0x0B) +#define PD0 0 +#define PD1 1 +#define PD2 2 +#define PD3 3 +#define PD4 4 +#define PD5 5 +#define PD6 6 +#define PD7 7 + +/* Port E Input Pins Address */ +#define PINE _SFR_IO8(0x0C) +#define PINE0 0 +#define PINE1 1 +#define PINE2 2 + +/* Port E Data Direction Register */ +#define DDRE _SFR_IO8(0x0D) +#define DDE0 0 +#define DDE1 1 +#define DDE2 2 + +/* Port E Data Register */ +#define PORTE _SFR_IO8(0x0E) +#define PE0 0 +#define PE1 1 +#define PE2 2 + +/* Timer/Counter 0 Interrupt Flag Register */ +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 /* Overflow Flag */ +#define OCF0A 1 /* Output Compare Flag 0A */ +#define OCF0B 2 /* Output Compare Flag 0B */ + +/* Timer/Counter1 Interrupt Flag Register */ +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 /* Overflow Flag */ +#define OCF1A 1 /* Output Compare Flag 1A*/ +#define OCF1B 2 /* Output Compare Flag 1B*/ +#define ICF1 5 /* Input Capture Flag 1 */ + +/* General Purpose I/O Register 1 */ +#define GPIOR1 _SFR_IO8(0x19) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +/* General Purpose I/O Register 2 */ +#define GPIOR2 _SFR_IO8(0x1A) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +/* General Purpose I/O Register 3 */ +#define GPIOR3 _SFR_IO8(0x1B) +#define GPIOR30 0 +#define GPIOR31 1 +#define GPIOR32 2 +#define GPIOR33 3 +#define GPIOR34 4 +#define GPIOR35 5 +#define GPIOR36 6 +#define GPIOR37 7 + +/* External Interrupt Flag Register */ +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 + +/* External Interrupt Mask Register */ +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 /* External Interrupt Request 0 Enable */ +#define INT1 1 /* External Interrupt Request 1 Enable */ +#define INT2 2 /* External Interrupt Request 2 Enable */ +#define INT3 3 /* External Interrupt Request 3 Enable */ + +/* General Purpose I/O Register 0 */ +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1F) +#define EERE 0 /* EEPROM Read Enable */ +#define EEWE 1 /* EEPROM Write Enable */ +#define EEMWE 2 /* EEPROM Master Write Enable */ +#define EERIE 3 /* EEPROM Ready Interrupt Enable */ + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +/* The EEPROM Address Registers */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 +#define EEAR10 2 +#define EEAR11 3 + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +/* General Timer/Counter Control Register */ +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */ +#define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ +#define TSM 7 /* Timer/Counter Synchronization Mode */ + +/* Timer/Counter Control Register A */ +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 /* Waveform Generation Mode */ +#define WGM01 1 /* Waveform Generation Mode */ +#define COM0B0 4 /* Compare Output Mode, Fast PWm */ +#define COM0B1 5 /* Compare Output Mode, Fast PWm */ +#define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ +#define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ + +/* Timer/Counter Control Register B */ +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 /* Clock Select */ +#define CS01 1 /* Clock Select */ +#define CS02 2 /* Clock Select */ +#define WGM02 3 /* Waveform Generation Mode */ +#define FOC0B 6 /* Force Output Compare B */ +#define FOC0A 7 /* Force Output Compare A */ + +/* Timer/Counter0 Register */ +#define TCNT0 _SFR_IO8(0x26) +#define TCNT00 0 +#define TCNT01 1 +#define TCNT02 2 +#define TCNT03 3 +#define TCNT04 4 +#define TCNT05 5 +#define TCNT06 6 +#define TCNT07 7 + +/* Timer/Counter0 Output Compare Register A */ +#define OCR0A _SFR_IO8(0x27) +#define OCR0A0 0 +#define OCR0A1 1 +#define OCR0A2 2 +#define OCR0A3 3 +#define OCR0A4 4 +#define OCR0A5 5 +#define OCR0A6 6 +#define OCR0A7 7 + +/* Timer/Counter0 Output Compare Register B */ +#define OCR0B _SFR_IO8(0x28) +#define OCR0B0 0 +#define OCR0B1 1 +#define OCR0B2 2 +#define OCR0B3 3 +#define OCR0B4 4 +#define OCR0B5 5 +#define OCR0B6 6 +#define OCR0B7 7 + +/* PLL Control and Status Register */ +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 /* PLL Lock Detector */ +#define PLLE 1 /* PLL Enable */ +#define PLLF 2 /* PLL Factor */ + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 /* SPI Clock Rate Select 0 */ +#define SPR1 1 /* SPI Clock Rate Select 1 */ +#define CPHA 2 /* Clock Phase */ +#define CPOL 3 /* Clock polarity */ +#define MSTR 4 /* Master/Slave Select */ +#define DORD 5 /* Data Order */ +#define SPE 6 /* SPI Enable */ +#define SPIE 7 /* SPI Interrupt Enable */ + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 /* Double SPI Speed Bit */ +#define WCOL 6 /* Write Collision Flag */ +#define SPIF 7 /* SPI Interrupt Flag */ + +/* SPI Data Register */ +#define SPDR _SFR_IO8(0x2E) +#define SPD0 0 +#define SPD1 1 +#define SPD2 2 +#define SPD3 3 +#define SPD4 4 +#define SPD5 5 +#define SPD6 6 +#define SPD7 7 + +/* Analog Comparator Status Register */ +#define ACSR _SFR_IO8(0x30) +#define AC0O 0 /* Analog Comparator 0 Output Bit */ +#define AC1O 1 /* Analog Comparator 1 Output Bit */ +#define AC2O 2 /* Analog Comparator 2 Output Bit */ +#define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ +#define AC1IF 5 /* Analog Comparator 1 Interrupt Flag Bit */ +#define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ +#define ACCKDIV 7 /* Analog Comparator Clock Divider */ + +/* Sleep Mode Control Register */ +#define SMCR _SFR_IO8(0x33) +#define SE 0 /* Sleep Enable */ +#define SM0 1 /* Sleep Mode Select bit0 */ +#define SM1 2 /* Sleep Mode Select bit1 */ +#define SM2 3 /* Sleep Mode Select bit2 */ + +/* MCU Status Register */ +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 /* Power-on reset flag */ +#define EXTRF 1 /* External Reset Flag */ +#define BORF 2 /* Brown-out Reset Flag */ +#define WDRF 3 /* Watchdog Reset Flag */ + +/* MCU Control Register */ +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 /* Interrupt Vector Change Enable */ +#define IVSEL 1 /* Interrupt Vector Select */ +#define PUD 4 /* Pull-up disable */ +#define SPIPS 7 /* SPI Pin Select */ + +/* Store Program Memory Control Register */ +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 /* Store Program Memory Enable */ +#define PGERS 1 /* Page Erase */ +#define PGWRT 2 /* Page Write */ +#define BLBSET 3 /* Boot Lock Bit Set */ +#define RWWSRE 4 /* Read While Write section read enable */ +#define RWWSB 6 /* Read While Write Section Busy */ +#define SPMIE 7 /* SPM Interrupt Enable */ + +/* Watchdog Timer Control Register */ +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 /* Watchdog Timer Prescaler bit0 */ +#define WDP1 1 /* Watchdog Timer Prescaler bit1 */ +#define WDP2 2 /* Watchdog Timer Prescaler bit2 */ +#define WDE 3 /* Watchdog Enable */ +#define WDCE 4 /* Watchdog Change Enable */ +#define WDP3 5 /* Watchdog Timer Prescaler bit3 */ +#define WDIE 6 /* Watchdog Timeout Interrupt Enable */ +#define WDIF 7 /* Watchdog Timeout Interrupt Flag */ + +/* Clock Prescaler Register */ +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 /* Clock Prescaler Select bit0 */ +#define CLKPS1 1 /* Clock Prescaler Select bit1 */ +#define CLKPS2 2 /* Clock Prescaler Select bit2 */ +#define CLKPS3 3 /* Clock Prescaler Select bit3 */ +#define CLKPCE 7 /* Clock Prescaler Change Enable */ + +/* Power Reduction Register */ +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 /* Power Reduction ADC */ +#define PRUSART0 1 /* Power Reduction USART0 */ +#define PRUSART PRUSART0 /* Define to maintain backward-compatibility */ +#define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ +#define PRTIM0 3 /* Power Reduction Timer/Counter0 */ +#define PRTIM1 4 /* Power Reduction Timer/Counter1 */ +#define PRPSC0 5 /* Power Reduction PSC0 */ +#define PRPSC1 6 /* Power Reduction PSC1 */ +#define PRPSC2 7 /* Power Reduction PSC2 */ + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io90pwm3b.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_IO90PWM3B_H_ +#define _AVR_IO90PWM3B_H_ 1 + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define PINE _SFR_IO8(0x0C) +#define PINE0 0 +#define PINE1 1 +#define PINE2 2 + +#define DDRE _SFR_IO8(0x0D) +#define DDE0 0 +#define DDE1 1 +#define DDE2 2 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE0 0 +#define PORTE1 1 +#define PORTE2 2 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define GPIOR1 _SFR_IO8(0x19) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x1A) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define GPIOR3 _SFR_IO8(0x1B) +#define GPIOR30 0 +#define GPIOR31 1 +#define GPIOR32 2 +#define GPIOR33 3 +#define GPIOR34 4 +#define GPIOR35 5 +#define GPIOR36 6 +#define GPIOR37 7 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARL0 0 +#define EEARL1 1 +#define EEARL2 2 +#define EEARL3 3 +#define EEARL4 4 +#define EEARL5 5 +#define EEARL6 6 +#define EEARL7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 +#define EEAR10 2 +#define EEAR11 3 + +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 +#define PSRSYNC 0 +#define ICPSEL1 2 +#define TSM 3 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define OCR0_0 0 /* Deprecated */ +#define OCR0_1 1 /* Deprecated */ +#define OCR0_2 2 /* Deprecated */ +#define OCR0_3 3 /* Deprecated */ +#define OCR0_4 4 /* Deprecated */ +#define OCR0_5 5 /* Deprecated */ +#define OCR0_6 6 /* Deprecated */ +#define OCR0_7 7 /* Deprecated */ + +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 +#define PLLE 1 +#define PLLF 2 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define AC0O 0 +#define AC1O 1 +#define AC2O 2 +#define AC0IF 4 +#define AC1IF 5 +#define AC2IF 6 +#define ACCKDIV 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define SPIPS 7 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM0 3 +#define PRTIM1 4 +#define PRPSC0 5 +#define PRPSC1 6 +#define PRPSC2 7 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io90pwm81.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_AT90PWM81_H_ +#define _AVR_AT90PWM81_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define ACSR _SFR_IO8(0x00) +#define AC1O 1 +#define AC2O 2 +#define AC3O 3 +#define AC1IF 5 +#define AC2IF 6 +#define AC3IF 7 + +#define TIMSK1 _SFR_IO8(0x01) +#define TOIE1 0 +#define ICIE1 5 + +#define TIFR1 _SFR_IO8(0x02) +#define TOV1 0 +#define ICF1 5 + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define ADCSRA _SFR_IO8(0x06) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +#define ADCSRB _SFR_IO8(0x07) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 +#define ADTS3 3 +#define ADSSEN 4 +#define ADNCDIS 6 +#define ADHSM 7 + +#define ADMUX _SFR_IO8(0x08) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define ADLAR 5 +#define REFS0 6 +#define REFS1 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define PINE _SFR_IO8(0x0C) +#define PINE0 0 +#define PINE1 1 +#define PINE2 2 + +#define DDRE _SFR_IO8(0x0D) +#define DDE0 0 +#define DDE1 1 +#define DDE2 2 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE0 0 +#define PORTE1 1 +#define PORTE2 2 + +#define PIM0 _SFR_IO8(0x0F) +#define PEOPE0 0 +#define PEOEPE0 1 +#define PEVE0A 3 +#define PEVE0B 4 + +#define PIFR0 _SFR_IO8(0x10) +#define PEOP0 0 +#define PRN00 1 +#define PRN01 2 +#define PEV0A 3 +#define PEV0B 4 +#define POAC0A 6 +#define POAC0B 7 + +#define PCNF0 _SFR_IO8(0x11) +#define PCLKSEL0 1 +#define POP0 2 +#define PMODE00 3 +#define PMODE01 4 +#define PLOCK0 5 +#define PALOCK0 6 +#define PFIFTY0 7 + +#define PCTL0 _SFR_IO8(0x12) +#define PRUN0 0 +#define PCCYC0 1 +#define PBFM00 2 +#define PAOC0A 3 +#define PAOC0B 4 +#define PBFM01 5 +#define PPRE00 6 +#define PPRE01 7 + +#define PIM2 _SFR_IO8(0x13) +#define PEOPE2 0 +#define PEOEPE2 1 +#define PEVE2A 3 +#define PEVE2B 4 +#define PSEIE2 5 + +#define PIFR2 _SFR_IO8(0x14) +#define PEOP2 0 +#define PRN20 1 +#define PRN21 2 +#define PEV2A 3 +#define PEV2B 4 +#define PSEI2 5 +#define POAC2A 6 +#define POAC2B 7 + +#define PCNF2 _SFR_IO8(0x15) +#define POME2 0 +#define PCLKSEL2 1 +#define POP2 2 +#define PMODE20 3 +#define PMODE21 4 +#define PLOCK2 5 +#define PALOCK2 6 +#define PFIFTY2 7 + +#define PCTL2 _SFR_IO8(0x16) +#define PRUN2 0 +#define PCCYC2 1 +#define PARUN2 2 +#define PAOC2A 3 +#define PAOC2B 4 +#define PBFM2 5 +#define PPRE20 6 +#define PPRE21 7 + +#define SPCR _SFR_IO8(0x17) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x18) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define GPIOR0 _SFR_IO8(0x19) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define GPIOR1 _SFR_IO8(0x1A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x1B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 +#define EEPAGE 6 +#define NVMBSY 7 + +#define EEDR _SFR_IO8(0x1D) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x1E) + +#define EEARL _SFR_IO8(0x1E) +#define EEARL0 0 +#define EEARL1 1 +#define EEARL2 2 +#define EEARL3 3 +#define EEARL4 4 +#define EEARL5 5 +#define EEARL6 6 +#define EEARL7 7 + +#define EEARH _SFR_IO8(0x1F) +#define EEAR8 0 + +#define EIFR _SFR_IO8(0x20) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 + +#define EIMSK _SFR_IO8(0x21) +#define INT0 0 +#define INT1 1 +#define INT2 2 + +#define OCR0SB _SFR_IO16(0x22) + +#define OCR0SBL _SFR_IO8(0x22) +#define OCR0SB_0 0 +#define OCR0SB_1 1 +#define OCR0SB_2 2 +#define OCR0SB_3 3 +#define OCR0SB_4 4 +#define OCR0SB_5 5 +#define OCR0SB_6 6 +#define OCR0SB_7 7 + +#define OCR0SBH _SFR_IO8(0x23) +#define OCR0SB_8 0 +#define OCR0SB_9 1 +#define OCR0SB_00 2 +#define OCR0SB_01 3 + +#define OCR0RB _SFR_IO16(0x24) + +#define OCR0RBL _SFR_IO8(0x24) +#define OCR0RB_0 0 +#define OCR0RB_1 1 +#define OCR0RB_2 2 +#define OCR0RB_3 3 +#define OCR0RB_4 4 +#define OCR0RB_5 5 +#define OCR0RB_6 6 +#define OCR0RB_7 7 + +#define OCR0RBH _SFR_IO8(0x25) +#define OCR0RB_8 0 +#define OCR0RB_9 1 +#define OCR0RB_00 2 +#define OCR0RB_01 3 +#define OCR0RB_02 4 +#define OCR0RB_03 5 +#define OCR0RB_04 6 +#define OCR0RB_05 7 + +#define OCR2SB _SFR_IO16(0x26) + +#define OCR2SBL _SFR_IO8(0x26) +#define OCR2SB_0 0 +#define OCR2SB_1 1 +#define OCR2SB_2 2 +#define OCR2SB_3 3 +#define OCR2SB_4 4 +#define OCR2SB_5 5 +#define OCR2SB_6 6 +#define OCR2SB_7 7 + +#define OCR2SBH _SFR_IO8(0x27) +#define OCR2SB_8 0 +#define OCR2SB_9 1 +#define OCR2SB_10 2 +#define OCR2SB_11 3 + +#define OCR2RB _SFR_IO16(0x28) + +#define OCR2RBL _SFR_IO8(0x28) +#define OCR2RB_0 0 +#define OCR2RB_1 1 +#define OCR2RB_2 2 +#define OCR2RB_3 3 +#define OCR2RB_4 4 +#define OCR2RB_5 5 +#define OCR2RB_6 6 +#define OCR2RB_7 7 + +#define OCR2RBH _SFR_IO8(0x29) +#define OCR2RB_8 0 +#define OCR2RB_9 1 +#define OCR2RB_10 2 +#define OCR2RB_11 3 +#define OCR2RB_12 4 +#define OCR2RB_13 5 +#define OCR2RB_14 6 +#define OCR2RB_15 7 + +#define OCR0RA _SFR_IO16(0x2A) + +#define OCR0RAL _SFR_IO8(0x2A) +#define OCR0RA_0 0 +#define OCR0RA_1 1 +#define OCR0RA_2 2 +#define OCR0RA_3 3 +#define OCR0RA_4 4 +#define OCR0RA_5 5 +#define OCR0RA_6 6 +#define OCR0RA_7 7 + +#define OCR0RAH _SFR_IO8(0x2B) +#define OCR0RA_8 0 +#define OCR0RA_9 1 +#define OCR0RA_00 2 +#define OCR0RA_01 3 + +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x2C) +#endif +#define ADCW _SFR_IO16(0x2C) + +#define ADCL _SFR_IO8(0x2C) +#define ADCL0 0 +#define ADCL1 1 +#define ADCL2 2 +#define ADCL3 3 +#define ADCL4 4 +#define ADCL5 5 +#define ADCL6 6 +#define ADCL7 7 + +#define ADCH _SFR_IO8(0x2D) +#define ADCH0 0 +#define ADCH1 1 +#define ADCH2 2 +#define ADCH3 3 +#define ADCH4 4 +#define ADCH5 5 +#define ADCH6 6 +#define ADCH7 7 + +#define OCR2RA _SFR_IO16(0x2E) + +#define OCR2RAL _SFR_IO8(0x2E) +#define OCR2RA_0 0 +#define OCR2RA_1 1 +#define OCR2RA_2 2 +#define OCR2RA_3 3 +#define OCR2RA_4 4 +#define OCR2RA_5 5 +#define OCR2RA_6 6 +#define OCR2RA_7 7 + +#define OCR2RAH _SFR_IO8(0x2F) +#define OCR2RA_8 0 +#define OCR2RA_9 1 +#define OCR2RA_10 2 +#define OCR2RA_11 3 + +#define DWDR _SFR_IO8(0x31) + +#define MSMCR _SFR_IO8(0x32) + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define CKRC81 2 +#define RSTDIS 3 +#define PUD 4 + +#define SPDR _SFR_IO8(0x36) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define DAC _SFR_IO16(0x38) + +#define DACL _SFR_IO8(0x38) +#define DACL0 0 +#define DACL1 1 +#define DACL2 2 +#define DACL3 3 +#define DACL4 4 +#define DACL5 5 +#define DACL6 6 +#define DACL7 7 + +#define DACH _SFR_IO8(0x39) +#define DACH0 0 +#define DACH1 1 +#define DACH2 2 +#define DACH3 3 +#define DACH4 4 +#define DACH5 5 +#define DACH6 6 +#define DACH7 7 + +#define TCNT1 _SFR_IO16(0x3A) + +#define TCNT1L _SFR_IO8(0x3A) +#define TCNT1L0 0 +#define TCNT1L1 1 +#define TCNT1L2 2 +#define TCNT1L3 3 +#define TCNT1L4 4 +#define TCNT1L5 5 +#define TCNT1L6 6 +#define TCNT1L7 7 + +#define TCNT1H _SFR_IO8(0x3B) +#define TCNT1H0 0 +#define TCNT1H1 1 +#define TCNT1H2 2 +#define TCNT1H3 3 +#define TCNT1H4 4 +#define TCNT1H5 5 +#define TCNT1H6 6 +#define TCNT1H7 7 + +#define OCR0SA _SFR_MEM16(0x60) + +#define OCR0SAL _SFR_MEM8(0x60) +#define OCR0SA_0 0 +#define OCR0SA_1 1 +#define OCR0SA_2 2 +#define OCR0SA_3 3 +#define OCR0SA_4 4 +#define OCR0SA_5 5 +#define OCR0SA_6 6 +#define OCR0SA_7 7 + +#define OCR0SAH _SFR_MEM8(0x61) +#define OCR0SA_8 0 +#define OCR0SA_9 1 +#define OCR0SA_00 2 +#define OCR0SA_01 3 + +#define PFRC0A _SFR_MEM8(0x62) +#define PRFM0A0 0 +#define PRFM0A1 1 +#define PRFM0A2 2 +#define PRFM0A3 3 +#define PFLTE0A 4 +#define PELEV0A 5 +#define PISEL0A 6 +#define PCAE0A 7 + +#define PFRC0B _SFR_MEM8(0x63) +#define PRFM0B0 0 +#define PRFM0B1 1 +#define PRFM0B2 2 +#define PRFM0B3 3 +#define PFLTE0B 4 +#define PELEV0B 5 +#define PISEL0B 6 +#define PCAE0B 7 + +#define OCR2SA _SFR_MEM16(0x64) + +#define OCR2SAL _SFR_MEM8(0x64) +#define OCR2SA_0 0 +#define OCR2SA_1 1 +#define OCR2SA_2 2 +#define OCR2SA_3 3 +#define OCR2SA_4 4 +#define OCR2SA_5 5 +#define OCR2SA_6 6 +#define OCR2SA_7 7 + +#define OCR2SAH _SFR_MEM8(0x65) +#define OCR2SA_8 0 +#define OCR2SA_9 1 +#define OCR2SA_10 2 +#define OCR2SA_11 3 + +#define PFRC2A _SFR_MEM8(0x66) +#define PRFM2A0 0 +#define PRFM2A1 1 +#define PRFM2A2 2 +#define PRFM2A3 3 +#define PFLTE2A 4 +#define PELEV2A 5 +#define PISEL2A 6 +#define PCAE2A 7 + +#define PFRC2B _SFR_MEM8(0x67) +#define PRFM2B0 0 +#define PRFM2B1 1 +#define PRFM2B2 2 +#define PRFM2B3 3 +#define PFLTE2B 4 +#define PELEV2B 5 +#define PISEL2B 6 +#define PCAE2B 7 + +#define PICR0 _SFR_MEM16(0x68) + +#define PICR0L _SFR_MEM8(0x68) +#define PICR0_0 0 +#define PICR0_1 1 +#define PICR0_2 2 +#define PICR0_3 3 +#define PICR0_4 4 +#define PICR0_5 5 +#define PICR0_6 6 +#define PICR0_7 7 + +#define PICR0H _SFR_MEM8(0x69) +#define PICR0_8 0 +#define PICR0_9 1 +#define PICR0_10 2 +#define PICR0_11 3 +#define PCST0 7 + +#define PSOC0 _SFR_MEM8(0x6A) +#define POEN0A 0 +#define POEN0B 2 +#define PSYNC00 4 +#define PSYNC01 5 +#define PISEL0B1 6 +#define PISEL0A1 7 + +#define PICR2 _SFR_MEM16(0x6C) + +#define PICR2L _SFR_MEM8(0x6C) +#define PICR2_0 0 +#define PICR2_1 1 +#define PICR2_2 2 +#define PICR2_3 3 +#define PICR2_4 4 +#define PICR2_5 5 +#define PICR2_6 6 +#define PICR2_7 7 + +#define PICR2H _SFR_MEM8(0x6D) +#define PICR2_8 0 +#define PICR2_9 1 +#define PICR2_10 2 +#define PICR2_11 3 +#define PCST2 7 + +#define PSOC2 _SFR_MEM8(0x6E) +#define POEN2A 0 +#define POEN2C 1 +#define POEN2B 2 +#define POEN2D 3 +#define PSYNC2_0 4 +#define PSYNC2_1 5 +#define POS22 6 +#define POS23 7 + +#define POM2 _SFR_MEM8(0x6F) +#define POMV2A0 0 +#define POMV2A1 1 +#define POMV2A2 2 +#define POMV2A3 3 +#define POMV2B0 4 +#define POMV2B1 5 +#define POMV2B2 6 +#define POMV2B3 7 + +#define PCNFE2 _SFR_MEM8(0x70) +#define PISEL2B1 0 +#define PISEL2A1 1 +#define PELEV2B1 2 +#define PELEV2A1 3 +#define PBFM21 4 +#define PASDLK20 5 +#define PASDLK21 6 +#define PASDLK22 7 + +#define PASDLY2 _SFR_MEM8(0x71) +#define PASDLY2_0 0 +#define PASDLY2_1 1 +#define PASDLY2_2 2 +#define PASDLY2_3 3 +#define PASDLY2_4 4 +#define PASDLY2_5 5 +#define PASDLY2_6 6 +#define PASDLY2_7 7 + +#define DACON _SFR_MEM8(0x76) +#define DAEN 0 +#define DALA 2 +#define DATS0 4 +#define DATS1 5 +#define DATS2 6 +#define DAATE 7 + +#define DIDR0 _SFR_MEM8(0x77) +#define ADC0D 0 +#define ADC1D 1 +#define ADC2D 2 +#define ADC3D 3 +#define ADC4D 4 +#define ADC5D 5 +#define ADC7D 6 +#define ADC8D 7 + +#define DIDR1 _SFR_MEM8(0x78) +#define ADC9D 0 +#define ADC10D 1 +#define AMP0PD 2 +#define ACMP1MD 3 + +#define AMP0CSR _SFR_MEM8(0x79) +#define AMP0TS0 0 +#define AMP0TS1 1 +#define AMP0GS 3 +#define AMP0G0 4 +#define AMP0G1 5 +#define AMP0IS 6 +#define AMP0EN 7 + +#define AC1ECON _SFR_MEM8(0x7A) +#define AC1H0 0 +#define AC1H1 1 +#define AC1H2 2 +#define AC1ICE 3 +#define AC1OE 4 +#define AC1OI 5 + +#define AC2ECON _SFR_MEM8(0x7B) +#define AC2H0 0 +#define AC2H1 1 +#define AC2H2 2 +#define AC2OE 4 +#define AC2OI 5 + +#define AC3ECON _SFR_MEM8(0x7C) +#define AC3H0 0 +#define AC3H1 1 +#define AC3H2 2 +#define AC3OE 4 +#define AC3OI 5 + +#define AC1CON _SFR_MEM8(0x7D) +#define AC1M0 0 +#define AC1M1 1 +#define AC1M2 2 +#define AC1IS0 4 +#define AC1IS1 5 +#define AC1IE 6 +#define AC1EN 7 + +#define AC2CON _SFR_MEM8(0x7E) +#define AC2M0 0 +#define AC2M1 1 +#define AC2M2 2 +#define AC2IS0 4 +#define AC2IS1 5 +#define AC2IE 6 +#define AC2EN 7 + +#define AC3CON _SFR_MEM8(0x7F) +#define AC3M0 0 +#define AC3M1 1 +#define AC3M2 2 +#define AC3OEA 3 +#define AC3IS0 4 +#define AC3IS1 5 +#define AC3IE 6 +#define AC3EN 7 + +#define BGCRR _SFR_MEM8(0x80) +#define BGCR0 0 +#define BGCR1 1 +#define BGCR2 2 +#define BGCR3 3 + +#define BGCCR _SFR_MEM8(0x81) +#define BGCC0 0 +#define BGCC1 1 +#define BGCC2 2 +#define BGCC3 3 + +#define WDTCSR _SFR_MEM8(0x82) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x83) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define CLKCSR _SFR_MEM8(0x84) +#define CLKC0 0 +#define CLKC1 1 +#define CLKC2 2 +#define CLKC3 3 +#define CLKRDY 4 +#define CLKCCE 7 + +#define CLKSELR _SFR_MEM8(0x85) +#define CKSEL0 0 +#define CKSEL1 1 +#define CKSEL2 2 +#define CKSEL3 3 +#define CSUT0 4 +#define CSUT1 5 +#define COUT 6 + +#define PRR _SFR_MEM8(0x86) +#define PRADC 0 +#define PRSPI 2 +#define PRTIM1 4 +#define PRPSCR 5 +#define PRPSC2 7 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io90pwmX.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* Port B Input Pins Address */ +#define PINB _SFR_IO8(0x03) +/* PINB */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* Port B Data Direction Register */ +#define DDRB _SFR_IO8(0x04) +/* DDRB */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Port B Data Register */ +#define PORTB _SFR_IO8(0x05) +/* PORTB */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Port C Input Pins Address */ +#define PINC _SFR_IO8(0x06) +/* PINC */ +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +/* Port C Data Direction Register */ +#define DDRC _SFR_IO8(0x07) +/* DDRC */ +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +/* Port C Data Register */ +#define PORTC _SFR_IO8(0x08) +/* PORTC */ +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* Port D Input Pins Address */ +#define PIND _SFR_IO8(0x09) +/* PIND */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* Port D Data Direction Register */ +#define DDRD _SFR_IO8(0x0A) +/* DDRD */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* Port D Data Register */ +#define PORTD _SFR_IO8(0x0B) +/* PORTD */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* Port E Input Pins Address */ +#define PINE _SFR_IO8(0x0C) +/* PINE */ +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +/* Port E Data Direction Register */ +#define DDRE _SFR_IO8(0x0D) +/* DDRE */ +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +/* Port E Data Register */ +#define PORTE _SFR_IO8(0x0E) +/* PORTE */ +#define PE2 2 +#define PE1 1 +#define PE0 0 + +/* Timer/Counter 0 Interrupt Flag Register */ +#define TIFR0 _SFR_IO8(0x15) +/* TIFR0 */ +#define OCF0B 2 /* Output Compare Flag 0B */ +#define OCF0A 1 /* Output Compare Flag 0A */ +#define TOV0 0 /* Overflow Flag */ + +/* Timer/Counter1 Interrupt Flag Register */ +#define TIFR1 _SFR_IO8(0x16) +/* TIFR1 */ +#define ICF1 5 /* Input Capture Flag 1 */ +#define OCF1B 2 /* Output Compare Flag 1B*/ +#define OCF1A 1 /* Output Compare Flag 1A*/ +#define TOV1 0 /* Overflow Flag */ + +/* General Purpose I/O Register 1 */ +#define GPIOR1 _SFR_IO8(0x19) +/* GPIOR1 */ +#define GPIOR17 7 +#define GPIOR16 6 +#define GPIOR15 5 +#define GPIOR14 4 +#define GPIOR13 3 +#define GPIOR12 2 +#define GPIOR11 1 +#define GPIOR10 0 + +/* General Purpose I/O Register 2 */ +#define GPIOR2 _SFR_IO8(0x1A) +/* GPIOR2 */ +#define GPIOR27 7 +#define GPIOR26 6 +#define GPIOR25 5 +#define GPIOR24 4 +#define GPIOR23 3 +#define GPIOR22 2 +#define GPIOR21 1 +#define GPIOR20 0 + +/* General Purpose I/O Register 3 */ +#define GPIOR3 _SFR_IO8(0x1B) +/* GPIOR3 */ +#define GPIOR37 7 +#define GPIOR36 6 +#define GPIOR35 5 +#define GPIOR34 4 +#define GPIOR33 3 +#define GPIOR32 2 +#define GPIOR31 1 +#define GPIOR30 0 + +/* External Interrupt Flag Register */ +#define EIFR _SFR_IO8(0x1C) +/* EIFR */ +#define INTF3 3 +#define INTF2 2 +#define INTF1 1 +#define INTF0 0 + +/* External Interrupt Mask Register */ +#define EIMSK _SFR_IO8(0x1D) +/* EIMSK */ +#define INT3 3 /* External Interrupt Request 3 Enable */ +#define INT2 2 /* External Interrupt Request 2 Enable */ +#define INT1 1 /* External Interrupt Request 1 Enable */ +#define INT0 0 /* External Interrupt Request 0 Enable */ + +/* General Purpose I/O Register 0 */ +#define GPIOR0 _SFR_IO8(0x1E) +/* GPIOR0 */ +#define GPIOR07 7 +#define GPIOR06 6 +#define GPIOR05 5 +#define GPIOR04 4 +#define GPIOR03 3 +#define GPIOR02 2 +#define GPIOR01 1 +#define GPIOR00 0 + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1F) +/* EECR */ +#define EERIE 3 /* EEPROM Ready Interrupt Enable */ +#define EEMWE 2 /* EEPROM Master Write Enable */ +#define EEWE 1 /* EEPROM Write Enable */ +#define EERE 0 /* EEPROM Read Enable */ + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x20) +/* EEDR */ +#define EEDR7 7 +#define EEDR6 6 +#define EEDR5 5 +#define EEDR4 4 +#define EEDR3 3 +#define EEDR2 2 +#define EEDR1 1 +#define EEDR0 0 + +/* The EEPROM Address Registers */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) +/* EEARH */ +#define EEAR11 3 +#define EEAR10 2 +#define EEAR9 1 +#define EEAR8 0 +/* EEARL */ +#define EEAR7 7 +#define EEAR6 6 +#define EEAR5 5 +#define EEAR4 4 +#define EEAR3 3 +#define EEAR2 2 +#define EEAR1 1 +#define EEAR0 0 + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +/* General Timer/Counter Control Register */ +#define GTCCR _SFR_IO8(0x23) +/* GTCCR */ +#define TSM 7 /* Timer/Counter Synchronization Mode */ +#define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ +#define PSR10 0 /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */ + +/* Timer/Counter Control Register A */ +#define TCCR0A _SFR_IO8(0x24) +/* TCCR0A */ +#define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ +#define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ +#define COM0B1 5 /* Compare Output Mode, Fast PWm */ +#define COM0B0 4 /* Compare Output Mode, Fast PWm */ +#define WGM01 1 /* Waveform Generation Mode */ +#define WGM00 0 /* Waveform Generation Mode */ + +/* Timer/Counter Control Register B */ +#define TCCR0B _SFR_IO8(0x25) +/* TCCR0B */ +#define FOC0A 7 /* Force Output Compare A */ +#define FOC0B 6 /* Force Output Compare B */ +#define WGM02 3 /* Waveform Generation Mode */ +#define CS02 2 /* Clock Select */ +#define CS01 1 /* Clock Select */ +#define CS00 0 /* Clock Select */ + +/* Timer/Counter0 Register */ +#define TCNT0 _SFR_IO8(0x26) +/* TCNT0 */ +#define TCNT07 7 +#define TCNT06 6 +#define TCNT05 5 +#define TCNT04 4 +#define TCNT03 3 +#define TCNT02 2 +#define TCNT01 1 +#define TCNT00 0 + +/* Timer/Counter0 Output Compare Register A */ +#define OCR0A _SFR_IO8(0x27) +/* OCR0A */ +#define OCR0A7 7 +#define OCR0A6 6 +#define OCR0A5 5 +#define OCR0A4 4 +#define OCR0A3 3 +#define OCR0A2 2 +#define OCR0A1 1 +#define OCR0A0 0 + +/* Timer/Counter0 Output Compare Register B */ +#define OCR0B _SFR_IO8(0x28) +/* OCR0B */ +#define OCR0B7 7 +#define OCR0B6 6 +#define OCR0B5 5 +#define OCR0B4 4 +#define OCR0B3 3 +#define OCR0B2 2 +#define OCR0B1 1 +#define OCR0B0 0 + +/* PLL Control and Status Register */ +#define PLLCSR _SFR_IO8(0x29) +/* PLLCSR */ +#define PCKE 2 /* PCK Enable */ +/* Bit 2 has been renamed in later versions of the datasheet. */ +#define PLLF 2 /* PLL Factor */ +#define PLLE 1 /* PLL Enable */ +#define PLOCK 0 /* PLL Lock Detector */ + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x2C) +/* SPCR */ +#define SPIE 7 /* SPI Interrupt Enable */ +#define SPE 6 /* SPI Enable */ +#define DORD 5 /* Data Order */ +#define MSTR 4 /* Master/Slave Select */ +#define CPOL 3 /* Clock polarity */ +#define CPHA 2 /* Clock Phase */ +#define SPR1 1 /* SPI Clock Rate Select 1 */ +#define SPR0 0 /* SPI Clock Rate Select 0 */ + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x2D) +/* SPSR */ +#define SPIF 7 /* SPI Interrupt Flag */ +#define WCOL 6 /* Write Collision Flag */ +#define SPI2X 0 /* Double SPI Speed Bit */ + +/* SPI Data Register */ +#define SPDR _SFR_IO8(0x2E) +/* SPDR */ +#define SPD7 7 +#define SPD6 6 +#define SPD5 5 +#define SPD4 4 +#define SPD3 3 +#define SPD2 2 +#define SPD1 1 +#define SPD0 0 + +/* Analog Comparator Status Register */ +#define ACSR _SFR_IO8(0x30) +/* ACSR */ +#define ACCKDIV 7 /* Analog Comparator Clock Divider */ +#define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ +#define AC1IF 5 /* Analog Comparator 1 Interrupt Flag Bit */ +#define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ +#define AC2O 2 /* Analog Comparator 2 Output Bit */ +#define AC1O 1 /* Analog Comparator 1 Output Bit */ +#define AC0O 0 /* Analog Comparator 0 Output Bit */ + +/* Monitor Data Register */ +#define MONDR _SFR_IO8(0x31) + +/* Monitor Stop Mode Control Register */ +#define MSMCR _SFR_IO8(0x32) + +/* Sleep Mode Control Register */ +#define SMCR _SFR_IO8(0x33) +/* SMCR */ +#define SM2 3 /* Sleep Mode Select bit2 */ +#define SM1 2 /* Sleep Mode Select bit1 */ +#define SM0 1 /* Sleep Mode Select bit0 */ +#define SE 0 /* Sleep Enable */ + +/* MCU Status Register */ +#define MCUSR _SFR_IO8(0x34) +/* MCUSR */ +#define WDRF 3 /* Watchdog Reset Flag */ +#define BORF 2 /* Brown-out Reset Flag */ +#define EXTRF 1 /* External Reset Flag */ +#define PORF 0 /* Power-on reset flag */ + +/* MCU Control Register */ +#define MCUCR _SFR_IO8(0x35) +/* MCUCR */ +#define SPIPS 7 /* SPI Pin Select */ +#define PUD 4 /* Pull-up disable */ +#define IVSEL 1 /* Interrupt Vector Select */ +#define IVCE 0 /* Interrupt Vector Change Enable */ + +/* Store Program Memory Control Register */ +#define SPMCSR _SFR_IO8(0x37) +/* SPMCSR */ +#define SPMIE 7 /* SPM Interrupt Enable */ +#define RWWSB 6 /* Read While Write Section Busy */ +#define RWWSRE 4 /* Read While Write section read enable */ +#define BLBSET 3 /* Boot Lock Bit Set */ +#define PGWRT 2 /* Page Write */ +#define PGERS 1 /* Page Erase */ +#define SPMEN 0 /* Store Program Memory Enable */ + +/* 0x3D..0x3E SP [defined in ] */ +/* 0x3F SREG [defined in ] */ + +/* Watchdog Timer Control Register */ +#define WDTCSR _SFR_MEM8(0x60) +/* WDTCSR */ +#define WDIF 7 /* Watchdog Timeout Interrupt Flag */ +#define WDIE 6 /* Watchdog Timeout Interrupt Enable */ +#define WDP3 5 /* Watchdog Timer Prescaler bit3 */ +#define WDCE 4 /* Watchdog Change Enable */ +#define WDE 3 /* Watchdog Enable */ +#define WDP2 2 /* Watchdog Timer Prescaler bit2 */ +#define WDP1 1 /* Watchdog Timer Prescaler bit1 */ +#define WDP0 0 /* Watchdog Timer Prescaler bit0 */ + +/* Clock Prescaler Register */ +#define CLKPR _SFR_MEM8(0x61) +/* CLKPR */ +#define CLKPCE 7 /* Clock Prescaler Change Enable */ +#define CLKPS3 3 /* Clock Prescaler Select bit3 */ +#define CLKPS2 2 /* Clock Prescaler Select bit2 */ +#define CLKPS1 1 /* Clock Prescaler Select bit1 */ +#define CLKPS0 0 /* Clock Prescaler Select bit0 */ + +/* Power Reduction Register */ +#define PRR _SFR_MEM8(0x64) +/* PRR */ +#define PRPSC2 7 /* Power Reduction PSC2 */ +#define PRPSC1 6 /* Power Reduction PSC1 */ +#define PRPSC0 5 /* Power Reduction PSC0 */ +#define PRTIM1 4 /* Power Reduction Timer/Counter1 */ +#define PRTIM0 3 /* Power Reduction Timer/Counter0 */ +#define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ +#define PRUSART0 1 /* Power Reduction USART */ +#define PRUSART PRUSART0 /* Define to maintain backward-compatibility */ +#define PRADC 0 /* Power Reduction ADC */ + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "io90scr100.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_AT90SCR100_H_ +#define _AVR_AT90SCR100_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINA _SFR_IO8(0x00) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 +#define PINA4 4 +#define PINA5 5 +#define PINA6 6 +#define PINA7 7 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 +#define PORTA4 4 +#define PORTA5 5 +#define PORTA6 6 +#define PORTA7 7 + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define PINE _SFR_IO8(0x0C) +#define PINE0 0 +#define PINE1 1 +#define PINE2 2 +#define PINE3 3 +#define PINE4 4 +#define PINE5 5 +#define PINE6 6 +#define PINE7 7 + +#define DDRE _SFR_IO8(0x0D) +#define DDE0 0 +#define DDE1 1 +#define DDE2 2 +#define DDE3 3 +#define DDE4 4 +#define DDE5 5 +#define DDE6 6 +#define DDE7 7 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE0 0 +#define PORTE1 1 +#define PORTE2 2 +#define PORTE3 3 +#define PORTE4 4 +#define PORTE5 5 +#define PORTE6 6 +#define PORTE7 7 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define EIRR _SFR_IO8(0x1A) +#define INTD2 2 +#define INTD3 3 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 +#define EEAR10 2 +#define EEAR11 3 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 +#define JTD 7 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define RAMPZ _SFR_IO8(0x3B) +#define RAMPZ0 0 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PLLCR _SFR_MEM8(0x62) +#define ON 0 +#define LOCK 1 +#define PLLMUX 7 + +#define SMONCR _SFR_MEM8(0x63) +#define SMONEN 0 +#define SMONIE 1 +#define SMONIF 4 + +#define PRR0 _SFR_MEM8(0x64) +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa5272.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +/* Reserved [0x06..0x11] */ + +#define PORTCR _SFR_IO8(0x12) +#define PUDA 0 +#define PUDB 1 +#define BBMA 4 +#define BBMB 5 + +/* Reserved [0x13..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +/* Reserved [0x17..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSR1 0 +#define PSR0 1 +#define TSM 7 + +/* Reserved [0x24] */ + +#define TCCR0A _SFR_IO8(0x25) +#define WGM00 0 +#define WGM01 1 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x26) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define FOC0A 7 + +#define TCNT2 _SFR_IO8(0x27) + +#define OCR0A _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACIRS 6 +#define ACD 7 + +#define DWDR _SFR_IO8(0x31) + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define SIGRD 5 +#define RWWSB 6 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define CLKCSR _SFR_MEM8(0x62) +#define CLKC0 0 +#define CLKC1 1 +#define CLKC2 2 +#define CLKC3 3 +#define CLKRDY 4 +#define CLKCCE 7 + +#define CLKSELR _SFR_MEM8(0x63) +#define CSEL0 0 +#define CSEL1 1 +#define CSEL2 2 +#define CSEL3 3 +#define CSUT0 4 +#define CSUT1 5 +#define COUT 6 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 +#define PRSPI 4 +#define PRLIN 5 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa5505.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +/* Reserved [0x06..0x11] */ + +#define PORTCR _SFR_IO8(0x12) +#define PUDA 0 +#define PUDB 1 +#define BBMA 4 +#define BBMB 5 + +/* Reserved [0x13..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +/* Reserved [0x17..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSR1 0 +#define PSR0 1 +#define TSM 7 + +/* Reserved [0x24] */ + +#define TCCR0A _SFR_IO8(0x25) +#define WGM00 0 +#define WGM01 1 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x26) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define FOC0A 7 + +#define TCNT2 _SFR_IO8(0x27) + +#define OCR0A _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACIRS 6 +#define ACD 7 + +#define DWDR _SFR_IO8(0x31) + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define SIGRD 5 +#define RWWSB 6 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define CLKCSR _SFR_MEM8(0x62) +#define CLKC0 0 +#define CLKC1 1 +#define CLKC2 2 +#define CLKC3 3 +#define CLKRDY 4 +#define CLKCCE 7 + +#define CLKSELR _SFR_MEM8(0x63) +#define CSEL0 0 +#define CSEL1 1 +#define CSEL2 2 +#define CSEL3 3 +#define CSUT0 4 +#define CSUT1 5 +#define COUT 6 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 +#define PRSPI 4 +#define PRLIN 5 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa5702m322.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define GPIOR0 _SFR_IO8(0x00) + +#define PRR1 _SFR_IO8(0x01) +#define PRT1 0 +#define PRT2 1 +#define PRT3 2 +#define PRT4 3 +#define PRT5 4 +#define PRLFR 5 +#define PRLFTP 6 +#define PRLFPH 7 + +#define __AVR_HAVE_PRR1 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa5782.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PRR0 _SFR_IO8(0x01) +#define PRSPI 0 +#define PRRXDC 1 +#define PRTXDC 2 +#define PRCRC 3 +#define PRVM 4 +#define PRCO 5 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa5790.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C] */ + +#define TPCR _SFR_IO8(0x0D) +#define TPMA 0 +#define TPMOD 1 +#define TPMS0 2 +#define TPMS1 3 +#define TPMD0 4 +#define TPMD1 5 +#define TPPSD 6 +#define TPD 7 + +#define TPFR _SFR_IO8(0x0E) +#define TPF 0 +#define TPA 1 +#define TPGAP 2 +#define TPPSW 3 + +#define CMCR _SFR_IO8(0x0F) +#define CMM0 0 +#define CMM1 1 +#define SRCD 2 +#define CO32D 3 +#define CCS 4 +#define ECINS 5 +#define CMONEN 6 +#define CMCCE 7 + +#define CMSR _SFR_IO8(0x10) +#define ECF 0 +#define SXF 1 +#define RTCF 2 + +#define T2CR _SFR_IO8(0x11) +#define T2OTM 0 +#define T2CTM 1 +#define T2CRM 2 +#define T2GRM 3 +#define T2TOP 4 +#define T2RES 5 +#define T2TS 6 +#define T2E 7 + +#define T3CR _SFR_IO8(0x12) +#define T3OTM 0 +#define T3CTM 1 +#define T3CRM 2 +#define T3CPRM 3 +#define T3TOP 4 +#define T3RES 5 +#define T3CPTM 6 +#define T3E 7 + +#define AESCR _SFR_IO8(0x13) +#define AESWK 0 +#define AESWD 1 +#define AESIM 2 +#define AESD 3 +#define AESXOR 4 +#define AESRES 5 +#define AESE 7 + +#define AESSR _SFR_IO8(0x14) +#define AESRF 0 +#define AESERF 7 + +#define TMIFR _SFR_IO8(0x15) +#define TMRXF 0 +#define TMTXF 1 +#define TMTCF 2 +#define TMRXS 3 +#define TMTXS 4 + +#define VMSR _SFR_IO8(0x16) +#define VMF 0 + +#define PCIFR _SFR_IO8(0x17) +#define PCIF0 0 +#define PCIF1 1 + +#define LFFR _SFR_IO8(0x18) +#define LFID0F 0 +#define LFID1F 1 +#define LFFEF 2 +#define LFDBF 3 +#define LFRSF 4 +#define LFSDF 5 +#define LFMDF 6 +#define LFCAF 7 + +#define T0IFR _SFR_IO8(0x19) +#define T0F 0 + +#define T1IFR _SFR_IO8(0x1A) +#define T1F 0 + +#define T2IFR _SFR_IO8(0x1B) +#define T2OFF 0 +#define T2COF 1 + +#define T3IFR _SFR_IO8(0x1C) +#define T3OFF 0 +#define T3COF 1 +#define T3ICF 2 + +#define EIFR _SFR_IO8(0x1D) +#define INTF0 0 + +#define GPIOR _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 +#define EELP 6 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define EEPR _SFR_IO8(0x23) +#define EEAP0 0 +#define EEAP1 1 +#define EEAP2 2 +#define EEAP3 3 + +#define EECCR _SFR_IO8(0x24) +#define EEL0 0 +#define EEL1 1 +#define EEL2 2 +#define EEL3 3 + +/* Reserved [0x25] */ + +#define PCICR _SFR_IO8(0x26) +#define PCIE0 0 +#define PCIE1 1 + +#define EIMSK _SFR_IO8(0x27) +#define INT0 0 + +#define TMDR _SFR_IO8(0x28) + +#define AESDR _SFR_IO8(0x29) + +#define AESKR _SFR_IO8(0x2A) +#define AESKR0 0 +#define AESKR1 1 +#define AESKR2 2 +#define AESKR3 3 +#define AESKR4 4 +#define AESKR5 5 +#define AESKR6 6 +#define AESKR7 7 + +#define VMCR _SFR_IO8(0x2B) +#define VMLS0 0 +#define VMLS1 1 +#define VMLS2 2 +#define VMLS3 3 +#define VMIM 4 +#define VMPS 5 +#define BODPD 6 +#define BODLS 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +#define LFCR0 _SFR_IO8(0x2F) +#define LFCE1 0 +#define LFCE2 1 +#define LFCE3 2 +#define LFBRS 3 +#define LFRBS 4 +#define LFMG 5 +#define LFVC0 6 +#define LFVC1 7 + +#define LFCR1 _SFR_IO8(0x30) +#define LFM0 0 +#define LFM1 1 +#define LFFM0 2 +#define LFFM1 3 +#define LFRMS 4 +#define LFRMSA 5 +#define LFQCE 6 +#define LFRE 7 + +/* Reserved [0x31] */ + +#define LFRDB _SFR_IO8(0x32) + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define TPRF 5 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +#define LFSR _SFR_IO8(0x36) +#define LFES 0 +#define LFSD 1 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define T1CR _SFR_IO8(0x38) +#define T1PS0 0 +#define T1PS1 1 +#define T1IE 2 +#define T1CS0 3 +#define T1CS1 4 +#define T1E 7 + +#define T0CR _SFR_IO8(0x39) +#define T0PS0 0 +#define T0PS1 1 +#define T0PS2 2 +#define T0IE 3 +#define T0PR 4 + +/* Reserved [0x3A] */ + +#define CMIMR _SFR_IO8(0x3B) +#define ECIE 0 +#define SXIE 1 +#define RTCIE 2 + +#define CLKPR _SFR_IO8(0x3C) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLTPS0 3 +#define CLTPS1 4 +#define CLTPS2 5 +#define CLKPCE 7 + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDPS0 0 +#define WDPS1 1 +#define WDPS2 2 +#define WDE 3 +#define WDCE 4 + +/* Reserved [0x61..0x62] */ + +#define PRR0 _SFR_MEM8(0x63) +#define PRLFR 0 +#define PRT1 1 +#define PRT2 2 +#define PRT3 3 +#define PRTM 4 +#define PRCU 5 +#define PRDS 6 +#define PRVM 7 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa5790n.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define T3CR2 _SFR_IO8(0x0C) +#define T3GRES 0 +#define T3C2TM 1 +#define T3C2RM 2 + +#define TPCR _SFR_IO8(0x0D) +#define TPMA 0 +#define TPMOD 1 +#define TPMS0 2 +#define TPMS1 3 +#define TPMD0 4 +#define TPMD1 5 +#define TPPSD 6 +#define TPD 7 + +#define TPFR _SFR_IO8(0x0E) +#define TPF 0 +#define TPA 1 +#define TPGAP 2 +#define TPPSW 3 + +#define CMCR _SFR_IO8(0x0F) +#define CMM0 0 +#define CMM1 1 +#define SRCD 2 +#define CO32D 3 +#define CCS 4 +#define ECINS 5 +#define CMONEN 6 +#define CMCCE 7 + +#define CMSR _SFR_IO8(0x10) +#define ECF 0 +#define SXF 1 +#define RTCF 2 + +#define T2CR _SFR_IO8(0x11) +#define T2OTM 0 +#define T2CTM 1 +#define T2CRM 2 +#define T2GRM 3 +#define T2TOP 4 +#define T2RES 5 +#define T2TS 6 +#define T2E 7 + +#define T3CR _SFR_IO8(0x12) +#define T3OTM 0 +#define T3CTM 1 +#define T3CRM 2 +#define T3CPRM 3 +#define T3TOP 4 +#define T3RES 5 +#define T3CPTM 6 +#define T3E 7 + +#define AESCR _SFR_IO8(0x13) +#define AESWK 0 +#define AESWD 1 +#define AESIM 2 +#define AESD 3 +#define AESXOR 4 +#define AESRES 5 +#define AESE 7 + +#define AESSR _SFR_IO8(0x14) +#define AESRF 0 +#define AESERF 7 + +#define TMIFR _SFR_IO8(0x15) +#define TMRXF 0 +#define TMTXF 1 +#define TMTCF 2 +#define TMRXS 3 +#define TMTXS 4 + +#define VMSR _SFR_IO8(0x16) +#define VMF 0 + +#define PCIFR _SFR_IO8(0x17) +#define PCIF0 0 +#define PCIF1 1 + +#define LFFR _SFR_IO8(0x18) +#define LFID0F 0 +#define LFID1F 1 +#define LFFEF 2 +#define LFDBF 3 +#define LFRSF 4 +#define LFSDF 5 +#define LFMDF 6 +#define LFCAF 7 + +#define T0IFR _SFR_IO8(0x19) +#define T0F 0 + +#define T1IFR _SFR_IO8(0x1A) +#define T1F 0 + +#define T2IFR _SFR_IO8(0x1B) +#define T2OFF 0 +#define T2COF 1 + +#define T3IFR _SFR_IO8(0x1C) +#define T3OFF 0 +#define T3COF 1 +#define T3ICF 2 +#define T3CO2F 3 + +#define EIFR _SFR_IO8(0x1D) +#define INTF0 0 + +#define GPIOR _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 +#define EELP 6 +#define NVMBSY 7 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define EEPR _SFR_IO8(0x23) +#define EEAP0 0 +#define EEAP1 1 +#define EEAP2 2 +#define EEAP3 3 + +#define EECCR _SFR_IO8(0x24) +#define EEL0 0 +#define EEL1 1 +#define EEL2 2 +#define EEL3 3 + +#define EECR2 _SFR_IO8(0x25) +#define EEBRE 0 +#define EEPAGE 1 + +#define PCICR _SFR_IO8(0x26) +#define PCIE0 0 +#define PCIE1 1 + +#define EIMSK _SFR_IO8(0x27) +#define INT0 0 + +#define TMDR _SFR_IO8(0x28) + +#define AESDR _SFR_IO8(0x29) + +#define AESKR _SFR_IO8(0x2A) +#define AESKR0 0 +#define AESKR1 1 +#define AESKR2 2 +#define AESKR3 3 +#define AESKR4 4 +#define AESKR5 5 +#define AESKR6 6 +#define AESKR7 7 + +#define VMCR _SFR_IO8(0x2B) +#define VMLS0 0 +#define VMLS1 1 +#define VMLS2 2 +#define VMLS3 3 +#define VMIM 4 +#define VMPS 5 +#define BODPD 6 +#define BODLS 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +#define LFCR0 _SFR_IO8(0x2F) +#define LFCE1 0 +#define LFCE2 1 +#define LFCE3 2 +#define LFBRS 3 +#define LFRBS 4 +#define LFMG 5 +#define LFVC0 6 +#define LFVC1 7 + +#define LFCR1 _SFR_IO8(0x30) +#define LFM0 0 +#define LFM1 1 +#define LFFM0 2 +#define LFFM1 3 +#define LFRMS 4 +#define LFRMSA 5 +#define LFQCE 6 +#define LFRE 7 + +/* Reserved [0x31] */ + +#define LFRDB _SFR_IO8(0x32) + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define TPRF 5 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +#define LFSR _SFR_IO8(0x36) +#define LFES 0 +#define LFSD 1 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define T1CR _SFR_IO8(0x38) +#define T1PS0 0 +#define T1PS1 1 +#define T1IE 2 +#define T1CS0 3 +#define T1CS1 4 +#define T1E 7 + +#define T0CR _SFR_IO8(0x39) +#define T0PS0 0 +#define T0PS1 1 +#define T0PS2 2 +#define T0IE 3 +#define T0PR 4 + +/* Reserved [0x3A] */ + +#define CMIMR _SFR_IO8(0x3B) +#define ECIE 0 +#define SXIE 1 +#define RTCIE 2 + +#define CLKPR _SFR_IO8(0x3C) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLTPS0 3 +#define CLTPS1 4 +#define CLTPS2 5 +#define CLKPCE 7 + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDPS0 0 +#define WDPS1 1 +#define WDPS2 2 +#define WDE 3 +#define WDCE 4 + +/* Reserved [0x61..0x62] */ + +#define PRR0 _SFR_MEM8(0x63) +#define PRLFR 0 +#define PRT1 1 +#define PRT2 2 +#define PRT3 3 +#define PRTM 4 +#define PRCU 5 +#define PRDS 6 +#define PRVM 7 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa5791.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define T3CR2 _SFR_IO8(0x0C) +#define T3GRES 0 +#define T3C2TM 1 +#define T3C2RM 2 + +#define TPCR _SFR_IO8(0x0D) +#define TPMA 0 +#define TPMOD 1 +#define TPMS0 2 +#define TPMS1 3 +#define TPMD0 4 +#define TPMD1 5 +#define TPPSD 6 +#define TPD 7 + +#define TPFR _SFR_IO8(0x0E) +#define TPF 0 +#define TPA 1 +#define TPGAP 2 +#define TPPSW 3 + +#define CMCR _SFR_IO8(0x0F) +#define CMM0 0 +#define CMM1 1 +#define SRCD 2 +#define CO32D 3 +#define CCS 4 +#define ECINS 5 +#define CMONEN 6 +#define CMCCE 7 + +#define CMSR _SFR_IO8(0x10) +#define ECF 0 +#define SXF 1 +#define RTCF 2 + +#define T2CR _SFR_IO8(0x11) +#define T2OTM 0 +#define T2CTM 1 +#define T2CRM 2 +#define T2GRM 3 +#define T2TOP 4 +#define T2RES 5 +#define T2TS 6 +#define T2E 7 + +#define T3CR _SFR_IO8(0x12) +#define T3OTM 0 +#define T3CTM 1 +#define T3CRM 2 +#define T3CPRM 3 +#define T3TOP 4 +#define T3RES 5 +#define T3CPTM 6 +#define T3E 7 + +#define AESCR _SFR_IO8(0x13) +#define AESWK 0 +#define AESWD 1 +#define AESIM 2 +#define AESD 3 +#define AESXOR 4 +#define AESRES 5 +#define AESE 7 + +#define AESSR _SFR_IO8(0x14) +#define AESRF 0 +#define AESERF 7 + +#define TMIFR _SFR_IO8(0x15) +#define TMRXF 0 +#define TMTXF 1 +#define TMTCF 2 +#define TMRXS 3 +#define TMTXS 4 + +#define VMSR _SFR_IO8(0x16) +#define VMF 0 + +#define PCIFR _SFR_IO8(0x17) +#define PCIF0 0 +#define PCIF1 1 + +#define LFFR _SFR_IO8(0x18) +#define LFID0F 0 +#define LFID1F 1 +#define LFFEF 2 +#define LFDBF 3 +#define LFRSF 4 +#define LFSDF 5 +#define LFMDF 6 +#define LFCAF 7 + +#define T0IFR _SFR_IO8(0x19) +#define T0F 0 + +#define T1IFR _SFR_IO8(0x1A) +#define T1F 0 + +#define T2IFR _SFR_IO8(0x1B) +#define T2OFF 0 +#define T2COF 1 + +#define T3IFR _SFR_IO8(0x1C) +#define T3OFF 0 +#define T3COF 1 +#define T3ICF 2 +#define T3CO2F 3 + +#define EIFR _SFR_IO8(0x1D) +#define INTF0 0 + +#define GPIOR _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 +#define EELP 6 +#define NVMBSY 7 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define EEPR _SFR_IO8(0x23) +#define EEAP0 0 +#define EEAP1 1 +#define EEAP2 2 +#define EEAP3 3 + +#define EECCR _SFR_IO8(0x24) +#define EEL0 0 +#define EEL1 1 +#define EEL2 2 +#define EEL3 3 + +#define EECR2 _SFR_IO8(0x25) +#define EEBRE 0 +#define EEPAGE 1 + +#define PCICR _SFR_IO8(0x26) +#define PCIE0 0 +#define PCIE1 1 + +#define EIMSK _SFR_IO8(0x27) +#define INT0 0 + +#define TMDR _SFR_IO8(0x28) + +#define AESDR _SFR_IO8(0x29) + +#define AESKR _SFR_IO8(0x2A) +#define AESKR0 0 +#define AESKR1 1 +#define AESKR2 2 +#define AESKR3 3 +#define AESKR4 4 +#define AESKR5 5 +#define AESKR6 6 +#define AESKR7 7 + +#define VMCR _SFR_IO8(0x2B) +#define VMLS0 0 +#define VMLS1 1 +#define VMLS2 2 +#define VMLS3 3 +#define VMIM 4 +#define VMPS 5 +#define BODPD 6 +#define BODLS 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +#define LFCR0 _SFR_IO8(0x2F) +#define LFCE1 0 +#define LFCE2 1 +#define LFCE3 2 +#define LFBRS 3 +#define LFRBS 4 +#define LFMG 5 +#define LFVC0 6 +#define LFVC1 7 + +#define LFCR1 _SFR_IO8(0x30) +#define LFM0 0 +#define LFM1 1 +#define LFFM0 2 +#define LFFM1 3 +#define LFRMS 4 +#define LFRMSA 5 +#define LFQCE 6 +#define LFRE 7 + +/* Reserved [0x31] */ + +#define LFRDB _SFR_IO8(0x32) + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define TPRF 5 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +#define LFSR _SFR_IO8(0x36) +#define LFES 0 +#define LFSD 1 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define T1CR _SFR_IO8(0x38) +#define T1PS0 0 +#define T1PS1 1 +#define T1IE 2 +#define T1CS0 3 +#define T1CS1 4 +#define T1E 7 + +#define T0CR _SFR_IO8(0x39) +#define T0PS0 0 +#define T0PS1 1 +#define T0PS2 2 +#define T0IE 3 +#define T0PR 4 + +/* Reserved [0x3A] */ + +#define CMIMR _SFR_IO8(0x3B) +#define ECIE 0 +#define SXIE 1 +#define RTCIE 2 + +#define CLKPR _SFR_IO8(0x3C) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLTPS0 3 +#define CLTPS1 4 +#define CLTPS2 5 +#define CLKPCE 7 + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDPS0 0 +#define WDPS1 1 +#define WDPS2 2 +#define WDE 3 +#define WDCE 4 + +/* Reserved [0x61..0x62] */ + +#define PRR0 _SFR_MEM8(0x63) +#define PRLFR 0 +#define PRT1 1 +#define PRT2 2 +#define PRT3 3 +#define PRTM 4 +#define PRCU 5 +#define PRDS 6 +#define PRVM 7 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa5795.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C] */ + +#define TPCR _SFR_IO8(0x0D) +#define TPMA 0 +#define TPMOD 1 +#define TPMS0 2 +#define TPMS1 3 +#define TPMD0 4 +#define TPMD1 5 +#define TPPSD 6 +#define TPD 7 + +#define TPFR _SFR_IO8(0x0E) +#define TPF 0 +#define TPA 1 +#define TPGAP 2 +#define TPPSW 3 + +#define CMCR _SFR_IO8(0x0F) +#define CMM0 0 +#define CMM1 1 +#define SRCD 2 +#define CO32D 3 +#define CCS 4 +#define ECINS 5 +#define CMONEN 6 +#define CMCCE 7 + +#define CMSR _SFR_IO8(0x10) +#define ECF 0 +#define SXF 1 +#define RTCF 2 + +#define T2CR _SFR_IO8(0x11) +#define T2OTM 0 +#define T2CTM 1 +#define T2CRM 2 +#define T2GRM 3 +#define T2TOP 4 +#define T2RES 5 +#define T2TS 6 +#define T2E 7 + +#define T3CR _SFR_IO8(0x12) +#define T3OTM 0 +#define T3CTM 1 +#define T3CRM 2 +#define T3CPRM 3 +#define T3TOP 4 +#define T3RES 5 +#define T3CPTM 6 +#define T3E 7 + +#define AESCR _SFR_IO8(0x13) +#define AESWK 0 +#define AESWD 1 +#define AESIM 2 +#define AESD 3 +#define AESXOR 4 +#define AESRES 5 +#define AESE 7 + +#define AESSR _SFR_IO8(0x14) +#define AESRF 0 +#define AESERF 7 + +#define TMIFR _SFR_IO8(0x15) +#define TMRXF 0 +#define TMTXF 1 +#define TMTCF 2 +#define TMRXS 3 +#define TMTXS 4 + +#define VMSR _SFR_IO8(0x16) +#define VMF 0 + +#define PCIFR _SFR_IO8(0x17) +#define PCIF0 0 +#define PCIF1 1 + +/* Reserved [0x18] */ + +#define T0IFR _SFR_IO8(0x19) +#define T0F 0 + +#define T1IFR _SFR_IO8(0x1A) +#define T1F 0 + +#define T2IFR _SFR_IO8(0x1B) +#define T2OFF 0 +#define T2COF 1 + +#define T3IFR _SFR_IO8(0x1C) +#define T3OFF 0 +#define T3COF 1 +#define T3ICF 2 + +#define EIFR _SFR_IO8(0x1D) +#define INTF0 0 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 +#define EELP 6 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define EEPR _SFR_IO8(0x23) +#define EEAP0 0 +#define EEAP1 1 +#define EEAP2 2 +#define EEAP3 3 + +#define EECCR _SFR_IO8(0x24) +#define EEL0 0 +#define EEL1 1 +#define EEL2 2 +#define EEL3 3 + +/* Reserved [0x25] */ + +#define PCICR _SFR_IO8(0x26) +#define PCIE0 0 +#define PCIE1 1 + +#define EIMSK _SFR_IO8(0x27) +#define INT0 0 + +#define TMDR _SFR_IO8(0x28) + +#define AESDR _SFR_IO8(0x29) + +#define AESKR _SFR_IO8(0x2A) +#define AESKR0 0 +#define AESKR1 1 +#define AESKR2 2 +#define AESKR3 3 +#define AESKR4 4 +#define AESKR5 5 +#define AESKR6 6 +#define AESKR7 7 + +#define VMCR _SFR_IO8(0x2B) +#define VMLS0 0 +#define VMLS1 1 +#define VMLS2 2 +#define VMLS3 3 +#define VMIM 4 +#define VMPS 5 +#define BODPD 6 +#define BODLS 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define TPRF 5 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define T1CR _SFR_IO8(0x38) +#define T1PS0 0 +#define T1PS1 1 +#define T1IE 2 +#define T1CS0 3 +#define T1CS1 4 +#define T1E 7 + +#define T0CR _SFR_IO8(0x39) +#define T0PS0 0 +#define T0PS1 1 +#define T0PS2 2 +#define T0IE 3 +#define T0PR 4 + +/* Reserved [0x3A] */ + +#define CMIMR _SFR_IO8(0x3B) +#define ECIE 0 +#define SXIE 1 +#define RTCIE 2 + +#define CLKPR _SFR_IO8(0x3C) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLTPS0 3 +#define CLTPS1 4 +#define CLTPS2 5 +#define CLKPCE 7 + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDPS0 0 +#define WDPS1 1 +#define WDPS2 2 +#define WDE 3 +#define WDCE 4 + +/* Reserved [0x61..0x62] */ + +#define PRR0 _SFR_MEM8(0x63) +#define PRT1 1 +#define PRT2 2 +#define PRT3 3 +#define PRTM 4 +#define PRCU 5 +#define PRDS 6 +#define PRVM 7 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa5831.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PRR0 _SFR_IO8(0x01) +#define PRSPI 0 +#define PRRXDC 1 +#define PRTXDC 2 +#define PRCRC 3 +#define PRVM 4 +#define PRCO 5 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa6285.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C..0x0E] */ + +#define CMCR _SFR_IO8(0x0F) +#define CMM0 0 +#define CMM1 1 +#define SRCD 2 +#define CMONEN 3 +#define CCS 4 +#define ECINS 5 +#define CMCCE 7 + +#define CMSR _SFR_IO8(0x10) +#define ECF 0 + +#define T2CRA _SFR_IO8(0x11) +#define T2OTM 0 +#define T2CTM 1 +#define T2CR 2 +#define T2CRM 3 +#define T2ICS 5 +#define T2TS 6 +#define T2E 7 + +#define T2CRB _SFR_IO8(0x12) +#define T2SCE 0 + +/* Reserved [0x13] */ + +#define T3CRA _SFR_IO8(0x14) +#define T3AC 0 +#define T3SCE 1 +#define T3CR 2 +#define T3TS 6 +#define T3E 7 + +/* Reserved [0x15] */ + +#define VMCSR _SFR_IO8(0x16) +#define VMEN 0 +#define VMLS0 1 +#define VMLS1 2 +#define VMLS2 3 +#define VMIM 4 +#define VMF 5 +#define BODPD 6 +#define BODLS 7 + +#define PCIFR _SFR_IO8(0x17) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define LFFR _SFR_IO8(0x18) +#define LFWPF 0 +#define LFBF 1 +#define LFEDF 2 +#define LFRF 3 + +#define SSFR _SFR_IO8(0x19) +#define MSENF 0 +#define MSENO 1 + +#define T10IFR _SFR_IO8(0x1A) +#define T0F 0 +#define T1F 1 + +#define T2IFR _SFR_IO8(0x1B) +#define T2OFF 0 +#define T2COF 1 +#define T2ICF 2 +#define T2RXF 3 +#define T2TXF 4 +#define T2TCF 5 + +#define T3IFR _SFR_IO8(0x1C) +#define T3OFF 0 +#define T3COAF 1 +#define T3COBF 2 +#define T3ICF 3 + +#define EIFR _SFR_IO8(0x1D) +#define INTF0 0 +#define INTF1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define PCICR _SFR_IO8(0x23) +#define PCIE0 0 +#define PCIE1 1 +#define PCIE2 2 + +#define EIMSK _SFR_IO8(0x24) +#define INT0 0 +#define INT1 1 + +/* Reserved [0x25..0x26] */ + +#define SVCR _SFR_IO8(0x27) + +#define SCR _SFR_IO8(0x28) +#define SMS 0 +#define SEN0 1 +#define SEN1 2 +#define SMEN 3 + +#define SCCR _SFR_IO8(0x29) +#define SRCC0 0 +#define SRCC1 1 +#define SCCS0 2 +#define SCCS1 3 +#define SCCS2 4 + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +#define T2MDR _SFR_IO8(0x2F) + +#define LFRR _SFR_IO8(0x30) + +/* Reserved [0x31] */ + +#define LFCDR _SFR_IO8(0x32) +#define LFDO 0 +#define LFRST 6 +#define LFSCE 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define TSRF 5 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +#define LFRB _SFR_IO8(0x36) + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +#define T1CR _SFR_IO8(0x38) +#define T1PS0 0 +#define T1PS1 1 +#define T1PS2 2 +#define T1CS0 3 +#define T1CS1 4 +#define T1CS2 5 +#define T1IE 7 + +#define T0CR _SFR_IO8(0x39) +#define T0PAS0 0 +#define T0PAS1 1 +#define T0PAS2 2 +#define T0IE 3 +#define T0PR 4 +#define T0PBS0 5 +#define T0PBS1 6 +#define T0PBS2 7 + +/* Reserved [0x3A] */ + +#define CMIMR _SFR_IO8(0x3B) +#define ECIE 0 + +#define CLKPR _SFR_IO8(0x3C) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLTPS0 3 +#define CLTPS1 4 +#define CLTPS2 5 +#define CLPCE 7 + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDPS0 0 +#define WDPS1 1 +#define WDPS2 2 +#define WDE 3 +#define WDCE 4 + +#define SIMSK _SFR_MEM8(0x61) +#define MSIE 0 + +/* Reserved [0x62..0x63] */ + +#define TSCR _SFR_MEM8(0x64) +#define TSSD 0 + +#define SRCCAL _SFR_MEM8(0x65) + +#define FRCCAL _SFR_MEM8(0x66) + +#define MSVCAL _SFR_MEM8(0x67) + +/* Reserved [0x68] */ + +#define EICRA _SFR_MEM8(0x69) +#define ISC00 0 +#define ISC01 1 +#define ISC10 2 +#define ISC11 3 + +#define PCMSK0 _SFR_MEM8(0x6A) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 +#define PCINT4 4 +#define PCINT5 5 +#define PCINT6 6 +#define PCINT7 7 + +#define PCMSK1 _SFR_MEM8(0x6B) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 + +#define PCMSK2 _SFR_MEM8(0x6C) +#define PCINT16 0 +#define PCINT17 1 +#define PCINT18 2 +#define PCINT19 3 +#define PCINT20 4 +#define PCINT21 5 +#define PCINT22 6 +#define PCINT23 7 + +/* Reserved [0x6D] */ + +#define T2ICRL _SFR_MEM8(0x6E) + +#define T2ICR _SFR_MEM8(0x6F) + +/* Combine T2CORL and T2CORH */ +#define T2COR _SFR_MEM16(0x70) + +#define T2CORL _SFR_MEM8(0x70) +#define T2CORH _SFR_MEM8(0x71) + +#define T2MRA _SFR_MEM8(0x72) +#define T2CS0 0 +#define T2CS1 1 +#define T2CS2 2 +#define T2CE0 3 +#define T2CE1 4 +#define T2CNC 5 +#define T2TP0 6 +#define T2TP1 7 + +#define T2MRB _SFR_MEM8(0x73) +#define T2M0 0 +#define T2M1 1 +#define T2M2 2 +#define T2M3 3 +#define T2TOP 4 +#define T2CPOL 6 +#define T2SSIE 7 + +#define T2IMR _SFR_MEM8(0x74) +#define T2OIM 0 +#define T2CIM 1 +#define T2CPIM 2 +#define T2RXIM 3 +#define T2TXIM 4 +#define T2TCIM 5 + +/* Reserved [0x75] */ + +/* Combine T3ICRL and T3ICRH */ +#define T3ICR _SFR_MEM16(0x76) + +#define T3ICRL _SFR_MEM8(0x76) +#define T3ICRH _SFR_MEM8(0x77) + +/* Combine T3CORAL and T3CORAH */ +#define T3CORA _SFR_MEM16(0x78) + +#define T3CORAL _SFR_MEM8(0x78) +#define T3CORAH _SFR_MEM8(0x79) + +/* Combine T3CORBL and T3CORBH */ +#define T3CORB _SFR_MEM16(0x7A) + +#define T3CORBL _SFR_MEM8(0x7A) +#define T3CORBH _SFR_MEM8(0x7B) + +#define T3MRA _SFR_MEM8(0x7C) +#define T3CS0 0 +#define T3CS1 1 +#define T3CS2 2 +#define T3CE0 3 +#define T3CE1 4 +#define T3CNC 5 +#define T3ICS0 6 +#define T3ICS1 7 + +#define T3MRB _SFR_MEM8(0x7D) +#define T3M0 0 +#define T3M1 1 +#define T3M2 2 +#define T3TOP 4 + +#define T3CRB _SFR_MEM8(0x7E) +#define T3CTMA 0 +#define T3SAMA 1 +#define T3CRMA 2 +#define T3CTMB 3 +#define T3SAMB 4 +#define T3CRMB 5 +#define T3CPRM 6 + +#define T3IMR _SFR_MEM8(0x7F) +#define T3OIM 0 +#define T3CAIM 1 +#define T3CBIM 2 +#define T3CPIM 3 + +/* Reserved [0x80] */ + +#define LFIMR _SFR_MEM8(0x81) +#define LFWIM 0 +#define LFBIM 1 +#define LFEIM 2 + +#define LFRCR _SFR_MEM8(0x82) +#define LFEN 0 +#define LFBM 1 +#define LFWM0 2 +#define LFWM1 3 +#define LFRSS 4 +#define LFCS0 5 +#define LFCS1 6 +#define LFCS2 7 + +#define LFHCR _SFR_MEM8(0x83) + +/* Combine LFIDCL and LFIDCH */ +#define LFIDC _SFR_MEM16(0x84) + +#define LFIDCL _SFR_MEM8(0x84) +#define LFIDCH _SFR_MEM8(0x85) + +/* Combine LFCALL and LFCALH */ +#define LFCAL _SFR_MEM16(0x86) + +#define LFCALL _SFR_MEM8(0x86) +#define LFCALH _SFR_MEM8(0x87) + + + +/* Values and associated defines */ + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_SENSOR_NOISE_REDUCTION (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) + +/* Interrupt vectors */ +/* Vector 0 is the reset vector */ +/* External Interrupt Request 0 */ +#define INT0_vect _VECTOR(1) +#define INT0_vect_num 1 + +/* External Interrupt Request 1 */ +#define INT1_vect _VECTOR(2) +#define INT1_vect_num 2 + +/* Pin Change Interrupt Request 0 */ +#define PCINT0_vect _VECTOR(3) +#define PCINT0_vect_num 3 + +/* Pin Change Interrupt Request 1 */ +#define PCINT1_vect _VECTOR(4) +#define PCINT1_vect_num 4 + +/* Pin Change Interrupt Request 2 */ +#define PCINT2_vect _VECTOR(5) +#define PCINT2_vect_num 5 + +/* Voltage Monitor Interrupt */ +#define INTVM_vect _VECTOR(6) +#define INTVM_vect_num 6 + +/* Sensor Interface Interrupt */ +#define SENINT_vect _VECTOR(7) +#define SENINT_vect_num 7 + +/* Timer0 Interval Interrupt */ +#define INTT0_vect _VECTOR(8) +#define INTT0_vect_num 8 + +/* LF-Receiver Wake-up Interrupt */ +#define LFWP_vect _VECTOR(9) +#define LFWP_vect_num 9 + +/* Timer/Counter3 Capture Event */ +#define T3CAP_vect _VECTOR(10) +#define T3CAP_vect_num 10 + +/* Timer/Counter3 Compare Match A */ +#define T3COMA_vect _VECTOR(11) +#define T3COMA_vect_num 11 + +/* Timer/Counter3 Compare Match B */ +#define T3COMB_vect _VECTOR(12) +#define T3COMB_vect_num 12 + +/* Timer/Counter3 Overflow */ +#define T3OVF_vect _VECTOR(13) +#define T3OVF_vect_num 13 + +/* Timer/Counter2 Capture Event */ +#define T2CAP_vect _VECTOR(14) +#define T2CAP_vect_num 14 + +/* Timer/Counter2 Compare Match */ +#define T2COM_vect _VECTOR(15) +#define T2COM_vect_num 15 + +/* Timer/Counter2 Overflow */ +#define T2OVF_vect _VECTOR(16) +#define T2OVF_vect_num 16 + +/* SPI Serial Transfer Complete */ +#define SPISTC_vect _VECTOR(17) +#define SPISTC_vect_num 17 + +/* LF Receive Buffer Interrupt */ +#define LFRXB_vect _VECTOR(18) +#define LFRXB_vect_num 18 + +/* Timer1 Interval Interrupt */ +#define INTT1_vect _VECTOR(19) +#define INTT1_vect_num 19 + +/* Timer2 SSI Receive Buffer Interrupt */ +#define T2RXB_vect _VECTOR(20) +#define T2RXB_vect_num 20 + +/* Timer2 SSI Transmit Buffer Interrupt */ +#define T2TXB_vect _VECTOR(21) +#define T2TXB_vect_num 21 + +/* Timer2 SSI Transmit Complete Interrupt */ +#define T2TXC_vect _VECTOR(22) +#define T2TXC_vect_num 22 + +/* LF-Receiver End of Burst Interrupt */ +#define LFREOB_vect _VECTOR(23) +#define LFREOB_vect_num 23 + +/* External Input Clock break down Interrupt */ +#define EXCM_vect _VECTOR(24) +#define EXCM_vect_num 24 + +/* EEPROM Ready Interrupt */ +#define EEREADY_vect _VECTOR(25) +#define EEREADY_vect_num 25 + +/* Store Program Memory Ready */ +#define SPM_RDY_vect _VECTOR(26) +#define SPM_RDY_vect_num 26 + +#define _VECTORS_SIZE 54 + + +/* Constants */ + +#define SPM_PAGESIZE 64 +#define FLASHSTART 0x0000 +#define FLASHEND 0x1FFF +#define RAMSTART 0x0100 +#define RAMSIZE 512 +#define RAMEND 0x02FF +#define E2START 0 +#define E2SIZE 320 +#define E2PAGESIZE 4 +#define E2END 0x013F +#define XRAMEND RAMEND + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 2 + +/* Low Fuse Byte */ +#define FUSE_TSRDI (unsigned char)~_BV(0) +#define FUSE_BODEN (unsigned char)~_BV(1) +#define FUSE_FRCFS (unsigned char)~_BV(2) +#define FUSE_WDRCON (unsigned char)~_BV(3) +#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(4) +#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_BODEN & FUSE_FRCFS & FUSE_WDRCON & FUSE_SUT_CKSEL0 & FUSE_CKDIV8) + + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_DWEN (unsigned char)~_BV(6) +#define FUSE_EELOCK (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) + + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x82 + + +#endif /* #ifdef _AVR_ATA6285_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/ioa6286.h b/hardware/tools/avr/avr/include/avr/ioa6286.h new file mode 100644 index 0000000000000000000000000000000000000000..b4837d454f76a8ed114433b8279fe22a5b5ab459 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/ioa6286.h @@ -0,0 +1,740 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_ATA6286_H_INCLUDED +#define _AVR_ATA6286_H_INCLUDED + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa6286.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C..0x0E] */ + +#define CMCR _SFR_IO8(0x0F) +#define CMM0 0 +#define CMM1 1 +#define SRCD 2 +#define CMONEN 3 +#define CCS 4 +#define ECINS 5 +#define CMCCE 7 + +#define CMSR _SFR_IO8(0x10) +#define ECF 0 + +#define T2CRA _SFR_IO8(0x11) +#define T2OTM 0 +#define T2CTM 1 +#define T2CR 2 +#define T2CRM 3 +#define T2ICS 5 +#define T2TS 6 +#define T2E 7 + +#define T2CRB _SFR_IO8(0x12) +#define T2SCE 0 + +/* Reserved [0x13] */ + +#define T3CRA _SFR_IO8(0x14) +#define T3AC 0 +#define T3SCE 1 +#define T3CR 2 +#define T3TS 6 +#define T3E 7 + +/* Reserved [0x15] */ + +#define VMCSR _SFR_IO8(0x16) +#define VMEN 0 +#define VMLS0 1 +#define VMLS1 2 +#define VMLS2 3 +#define VMIM 4 +#define VMF 5 +#define BODPD 6 +#define BODLS 7 + +#define PCIFR _SFR_IO8(0x17) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define LFFR _SFR_IO8(0x18) +#define LFWPF 0 +#define LFBF 1 +#define LFEDF 2 +#define LFRF 3 + +#define SSFR _SFR_IO8(0x19) +#define MSENF 0 +#define MSENO 1 + +#define T10IFR _SFR_IO8(0x1A) +#define T0F 0 +#define T1F 1 + +#define T2IFR _SFR_IO8(0x1B) +#define T2OFF 0 +#define T2COF 1 +#define T2ICF 2 +#define T2RXF 3 +#define T2TXF 4 +#define T2TCF 5 + +#define T3IFR _SFR_IO8(0x1C) +#define T3OFF 0 +#define T3COAF 1 +#define T3COBF 2 +#define T3ICF 3 + +#define EIFR _SFR_IO8(0x1D) +#define INTF0 0 +#define INTF1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define PCICR _SFR_IO8(0x23) +#define PCIE0 0 +#define PCIE1 1 +#define PCIE2 2 + +#define EIMSK _SFR_IO8(0x24) +#define INT0 0 +#define INT1 1 + +/* Reserved [0x25..0x26] */ + +#define SVCR _SFR_IO8(0x27) + +#define SCR _SFR_IO8(0x28) +#define SMS 0 +#define SEN0 1 +#define SEN1 2 +#define SMEN 3 + +#define SCCR _SFR_IO8(0x29) +#define SRCC0 0 +#define SRCC1 1 +#define SCCS0 2 +#define SCCS1 3 +#define SCCS2 4 + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +#define T2MDR _SFR_IO8(0x2F) + +#define LFRR _SFR_IO8(0x30) + +/* Reserved [0x31] */ + +#define LFCDR _SFR_IO8(0x32) +#define LFDO 0 +#define LFRST 6 +#define LFSCE 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define TSRF 5 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +#define LFRB _SFR_IO8(0x36) + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +#define T1CR _SFR_IO8(0x38) +#define T1PS0 0 +#define T1PS1 1 +#define T1PS2 2 +#define T1CS0 3 +#define T1CS1 4 +#define T1CS2 5 +#define T1IE 7 + +#define T0CR _SFR_IO8(0x39) +#define T0PAS0 0 +#define T0PAS1 1 +#define T0PAS2 2 +#define T0IE 3 +#define T0PR 4 +#define T0PBS0 5 +#define T0PBS1 6 +#define T0PBS2 7 + +/* Reserved [0x3A] */ + +#define CMIMR _SFR_IO8(0x3B) +#define ECIE 0 + +#define CLKPR _SFR_IO8(0x3C) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLTPS0 3 +#define CLTPS1 4 +#define CLTPS2 5 +#define CLPCE 7 + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDPS0 0 +#define WDPS1 1 +#define WDPS2 2 +#define WDE 3 +#define WDCE 4 + +#define SIMSK _SFR_MEM8(0x61) +#define MSIE 0 + +/* Reserved [0x62..0x63] */ + +#define TSCR _SFR_MEM8(0x64) +#define TSSD 0 + +#define SRCCAL _SFR_MEM8(0x65) + +#define FRCCAL _SFR_MEM8(0x66) + +#define MSVCAL _SFR_MEM8(0x67) + +/* Reserved [0x68] */ + +#define EICRA _SFR_MEM8(0x69) +#define ISC00 0 +#define ISC01 1 +#define ISC10 2 +#define ISC11 3 + +#define PCMSK0 _SFR_MEM8(0x6A) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 +#define PCINT4 4 +#define PCINT5 5 +#define PCINT6 6 +#define PCINT7 7 + +#define PCMSK1 _SFR_MEM8(0x6B) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 + +#define PCMSK2 _SFR_MEM8(0x6C) +#define PCINT16 0 +#define PCINT17 1 +#define PCINT18 2 +#define PCINT19 3 +#define PCINT20 4 +#define PCINT21 5 +#define PCINT22 6 +#define PCINT23 7 + +/* Reserved [0x6D] */ + +#define T2ICRL _SFR_MEM8(0x6E) + +#define T2ICR _SFR_MEM8(0x6F) + +/* Combine T2CORL and T2CORH */ +#define T2COR _SFR_MEM16(0x70) + +#define T2CORL _SFR_MEM8(0x70) +#define T2CORH _SFR_MEM8(0x71) + +#define T2MRA _SFR_MEM8(0x72) +#define T2CS0 0 +#define T2CS1 1 +#define T2CS2 2 +#define T2CE0 3 +#define T2CE1 4 +#define T2CNC 5 +#define T2TP0 6 +#define T2TP1 7 + +#define T2MRB _SFR_MEM8(0x73) +#define T2M0 0 +#define T2M1 1 +#define T2M2 2 +#define T2M3 3 +#define T2TOP 4 +#define T2CPOL 6 +#define T2SSIE 7 + +#define T2IMR _SFR_MEM8(0x74) +#define T2OIM 0 +#define T2CIM 1 +#define T2CPIM 2 +#define T2RXIM 3 +#define T2TXIM 4 +#define T2TCIM 5 + +/* Reserved [0x75] */ + +/* Combine T3ICRL and T3ICRH */ +#define T3ICR _SFR_MEM16(0x76) + +#define T3ICRL _SFR_MEM8(0x76) +#define T3ICRH _SFR_MEM8(0x77) + +/* Combine T3CORAL and T3CORAH */ +#define T3CORA _SFR_MEM16(0x78) + +#define T3CORAL _SFR_MEM8(0x78) +#define T3CORAH _SFR_MEM8(0x79) + +/* Combine T3CORBL and T3CORBH */ +#define T3CORB _SFR_MEM16(0x7A) + +#define T3CORBL _SFR_MEM8(0x7A) +#define T3CORBH _SFR_MEM8(0x7B) + +#define T3MRA _SFR_MEM8(0x7C) +#define T3CS0 0 +#define T3CS1 1 +#define T3CS2 2 +#define T3CE0 3 +#define T3CE1 4 +#define T3CNC 5 +#define T3ICS0 6 +#define T3ICS1 7 + +#define T3MRB _SFR_MEM8(0x7D) +#define T3M0 0 +#define T3M1 1 +#define T3M2 2 +#define T3TOP 4 + +#define T3CRB _SFR_MEM8(0x7E) +#define T3CTMA 0 +#define T3SAMA 1 +#define T3CRMA 2 +#define T3CTMB 3 +#define T3SAMB 4 +#define T3CRMB 5 +#define T3CPRM 6 + +#define T3IMR _SFR_MEM8(0x7F) +#define T3OIM 0 +#define T3CAIM 1 +#define T3CBIM 2 +#define T3CPIM 3 + +/* Reserved [0x80] */ + +#define LFIMR _SFR_MEM8(0x81) +#define LFWIM 0 +#define LFBIM 1 +#define LFEIM 2 + +#define LFRCR _SFR_MEM8(0x82) +#define LFEN 0 +#define LFBM 1 +#define LFWM0 2 +#define LFWM1 3 +#define LFRSS 4 +#define LFCS0 5 +#define LFCS1 6 +#define LFCS2 7 + +#define LFHCR _SFR_MEM8(0x83) + +/* Combine LFIDCL and LFIDCH */ +#define LFIDC _SFR_MEM16(0x84) + +#define LFIDCL _SFR_MEM8(0x84) +#define LFIDCH _SFR_MEM8(0x85) + +/* Combine LFCALL and LFCALH */ +#define LFCAL _SFR_MEM16(0x86) + +#define LFCALL _SFR_MEM8(0x86) +#define LFCALH _SFR_MEM8(0x87) + + + +/* Values and associated defines */ + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_SENSOR_NOISE_REDUCTION (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) + +/* Interrupt vectors */ +/* Vector 0 is the reset vector */ +/* External Interrupt Request 0 */ +#define INT0_vect _VECTOR(1) +#define INT0_vect_num 1 + +/* External Interrupt Request 1 */ +#define INT1_vect _VECTOR(2) +#define INT1_vect_num 2 + +/* Pin Change Interrupt Request 0 */ +#define PCINT0_vect _VECTOR(3) +#define PCINT0_vect_num 3 + +/* Pin Change Interrupt Request 1 */ +#define PCINT1_vect _VECTOR(4) +#define PCINT1_vect_num 4 + +/* Pin Change Interrupt Request 2 */ +#define PCINT2_vect _VECTOR(5) +#define PCINT2_vect_num 5 + +/* Voltage Monitor Interrupt */ +#define INTVM_vect _VECTOR(6) +#define INTVM_vect_num 6 + +/* Sensor Interface Interrupt */ +#define SENINT_vect _VECTOR(7) +#define SENINT_vect_num 7 + +/* Timer0 Interval Interrupt */ +#define INTT0_vect _VECTOR(8) +#define INTT0_vect_num 8 + +/* LF-Receiver Wake-up Interrupt */ +#define LFWP_vect _VECTOR(9) +#define LFWP_vect_num 9 + +/* Timer/Counter3 Capture Event */ +#define T3CAP_vect _VECTOR(10) +#define T3CAP_vect_num 10 + +/* Timer/Counter3 Compare Match A */ +#define T3COMA_vect _VECTOR(11) +#define T3COMA_vect_num 11 + +/* Timer/Counter3 Compare Match B */ +#define T3COMB_vect _VECTOR(12) +#define T3COMB_vect_num 12 + +/* Timer/Counter3 Overflow */ +#define T3OVF_vect _VECTOR(13) +#define T3OVF_vect_num 13 + +/* Timer/Counter2 Capture Event */ +#define T2CAP_vect _VECTOR(14) +#define T2CAP_vect_num 14 + +/* Timer/Counter2 Compare Match */ +#define T2COM_vect _VECTOR(15) +#define T2COM_vect_num 15 + +/* Timer/Counter2 Overflow */ +#define T2OVF_vect _VECTOR(16) +#define T2OVF_vect_num 16 + +/* SPI Serial Transfer Complete */ +#define SPISTC_vect _VECTOR(17) +#define SPISTC_vect_num 17 + +/* LF Receive Buffer Interrupt */ +#define LFRXB_vect _VECTOR(18) +#define LFRXB_vect_num 18 + +/* Timer1 Interval Interrupt */ +#define INTT1_vect _VECTOR(19) +#define INTT1_vect_num 19 + +/* Timer2 SSI Receive Buffer Interrupt */ +#define T2RXB_vect _VECTOR(20) +#define T2RXB_vect_num 20 + +/* Timer2 SSI Transmit Buffer Interrupt */ +#define T2TXB_vect _VECTOR(21) +#define T2TXB_vect_num 21 + +/* Timer2 SSI Transmit Complete Interrupt */ +#define T2TXC_vect _VECTOR(22) +#define T2TXC_vect_num 22 + +/* LF-Receiver End of Burst Interrupt */ +#define LFREOB_vect _VECTOR(23) +#define LFREOB_vect_num 23 + +/* External Input Clock break down Interrupt */ +#define EXCM_vect _VECTOR(24) +#define EXCM_vect_num 24 + +/* EEPROM Ready Interrupt */ +#define EEREADY_vect _VECTOR(25) +#define EEREADY_vect_num 25 + +/* Store Program Memory Ready */ +#define SPM_RDY_vect _VECTOR(26) +#define SPM_RDY_vect_num 26 + +#define _VECTORS_SIZE 54 + + +/* Constants */ + +#define SPM_PAGESIZE 64 +#define FLASHSTART 0x0000 +#define FLASHEND 0x1FFF +#define RAMSTART 0x0100 +#define RAMSIZE 512 +#define RAMEND 0x02FF +#define E2START 0 +#define E2SIZE 320 +#define E2PAGESIZE 4 +#define E2END 0x013F +#define XRAMEND RAMEND + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 2 + +/* Low Fuse Byte */ +#define FUSE_TSRDI (unsigned char)~_BV(0) +#define FUSE_BODEN (unsigned char)~_BV(1) +#define FUSE_FRCFS (unsigned char)~_BV(2) +#define FUSE_WDRCON (unsigned char)~_BV(3) +#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(4) +#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_BODEN & FUSE_FRCFS & FUSE_WDRCON & FUSE_SUT_CKSEL0 & FUSE_CKDIV8) + + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_DWEN (unsigned char)~_BV(6) +#define FUSE_EELOCK (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) + + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x82 + + +#endif /* #ifdef _AVR_ATA6286_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/ioa6289.h b/hardware/tools/avr/avr/include/avr/ioa6289.h new file mode 100644 index 0000000000000000000000000000000000000000..75c76306bdd29b62daf62ef2a471881ed228afea --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/ioa6289.h @@ -0,0 +1,847 @@ +/* Copyright (c) 2008 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: ioa6289.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ + +/* avr/ioa6289.h - definitions for ATA6289 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa6289.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATA6289_H_ +#define _AVR_ATA6289_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 + +#define DDRC _SFR_IO8(0x07) + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define CMCR _SFR_IO8(0x0F) +#define CMM0 0 +#define CMM1 1 +#define SRCD 2 +#define CMONEN 3 +#define CCS 4 +#define ECINS 5 +#define CMCCE 7 + +#define CMSR _SFR_IO8(0x10) +#define ECF 0 + +#define T2CRA _SFR_IO8(0x11) +#define T2OTM 0 +#define T2CTM 1 +#define T2CR 2 +#define T2CRM 3 +#define T2CPRM 4 +#define T2ICS 5 +#define T2TS 6 +#define T2E 7 + +#define T2CRB _SFR_IO8(0x12) +#define T2SCE 0 + +#define T3CRA _SFR_IO8(0x14) +#define T3AC 0 +#define T3SCE 1 +#define T3CR 2 +#define T3TS 6 +#define T3E 7 + +#define VMCSR _SFR_IO8(0x16) +#define VMEN 0 +#define VMLS0 1 +#define VMLS1 2 +#define VMLS2 3 +#define VMIM 4 +#define VMF 5 +#define BODPD 6 +#define BODLS 7 + +#define PCIFR _SFR_IO8(0x17) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define LFFR _SFR_IO8(0x18) +#define LFWPF 0 +#define LFBF 1 +#define LFEDF 2 +#define LFRF 3 + +#define SSFR _SFR_IO8(0x19) +#define MSENF 0 +#define MSENO 1 + +#define T10IFR _SFR_IO8(0x1A) +#define T0F 0 +#define T1F 1 + +#define T2IFR _SFR_IO8(0x1B) +#define T2OFF 0 +#define T2COF 1 +#define T2ICF 2 +#define T2RXF 3 +#define T2TXF 4 +#define T2TCF 5 + +#define T3IFR _SFR_IO8(0x1C) +#define T3OFF 0 +#define T3COAF 1 +#define T3COBF 2 +#define T3ICF 3 + +#define EIFR _SFR_IO8(0x1D) +#define INTF0 0 +#define INTF1 1 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 + +#define PCICR _SFR_IO8(0x23) +#define PCIE0 0 +#define PCIE1 1 +#define PCIE2 2 + +#define EIMSK _SFR_IO8(0x24) +#define INT0 0 +#define INT1 1 + +#define SVCR _SFR_IO8(0x27) +#define SVCS0 0 +#define SVCS1 1 +#define SVCS2 2 +#define SVCS3 3 +#define SVCS4 4 + +#define SCR _SFR_IO8(0x28) +#define SMS 0 +#define SEN0 1 +#define SEN1 2 +#define SMEN 3 + +#define SCCR _SFR_IO8(0x29) +#define SRCC0 0 +#define SRCC1 1 +#define SCCS0 2 +#define SCCS1 3 +#define SCCS2 4 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define T2MDR _SFR_IO8(0x2F) +#define T2MDR0 0 +#define T2MDR1 1 +#define T2MDR2 2 +#define T2MDR3 3 +#define T2MDR4 4 +#define T2MDR5 5 +#define T2MDR6 6 +#define T2MDR7 7 + +#define LFRR _SFR_IO8(0x30) +#define LFRR0 0 +#define LFRR1 1 +#define LFRR2 2 +#define LFRR3 3 +#define LFRR4 4 +#define LFRR5 5 +#define LFRR6 6 + +#define LFCDR _SFR_IO8(0x32) +#define LFDO 0 +#define LFRST 6 +#define LFSCE 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define TSRF 5 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +#define LFRB _SFR_IO8(0x36) +#define LFRB0 0 +#define LFRB1 1 +#define LFRB2 2 +#define LFRB3 3 +#define LFRB4 4 +#define LFRB5 5 +#define LFRB6 6 +#define LFRB7 7 + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +#define T1CR _SFR_IO8(0x38) +#define T1PS0 0 +#define T1PS1 1 +#define T1PS2 2 +#define T1CS0 3 +#define T1CS1 4 +#define T1CS2 5 +#define T1IE 7 + +#define T0CR _SFR_IO8(0x39) +#define T0PAS0 0 +#define T0PAS1 1 +#define T0PAS2 2 +#define T0IE 3 +#define T0PR 4 +#define T0PBS0 5 +#define T0PBS1 6 +#define T0PBS2 7 + +#define CMIMR _SFR_IO8(0x3B) +#define ECIE 0 + +#define CLKPR _SFR_IO8(0x3C) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLTPS0 3 +#define CLTPS1 4 +#define CLTPS2 5 +#define CLPCE 7 + +#define WDTCR _SFR_MEM8(0x60) +#define WDPS0 0 +#define WDPS1 1 +#define WDPS2 2 +#define WDE 3 +#define WDCE 4 + +#define SIMSK _SFR_MEM8(0x61) +#define MSIE 0 + +#define TSCR _SFR_MEM8(0x64) +#define TSSD 0 + +#define SRCCAL _SFR_MEM8(0x65) +#define SCAL0 0 +#define SCAL1 1 +#define SCAL2 2 +#define SCAL3 3 +#define SCAL4 4 +#define SCAL5 5 +#define SCAL6 6 +#define SCAL7 7 + +#define FRCCAL _SFR_MEM8(0x66) +#define FCAL0 0 +#define FCAL1 1 +#define FCAL2 2 +#define FCAL3 3 +#define FCAL4 4 +#define FCAL5 5 +#define FCAL6 6 +#define FCAL7 7 + +#define MSVCAL _SFR_MEM8(0x67) +#define VRCAL0 0 +#define VRCAL1 1 +#define VRCAL2 2 +#define VRCAL3 3 +#define VRCAL4 4 +#define VRCAL5 5 +#define VRCAL6 6 +#define VRCAL7 7 + +#define BGCAL _SFR_MEM8(0x68) +#define BGCAL0 0 +#define BGCAL1 1 +#define BGCAL2 2 +#define BGCAL3 3 +#define BGCAL4 4 +#define BGCAL5 5 +#define BGCAL6 6 +#define BGCAL7 7 + +#define EICRA _SFR_MEM8(0x69) +#define ISC00 0 +#define ISC01 1 +#define ISC10 2 +#define ISC11 3 + +#define PCMSK0 _SFR_MEM8(0x6A) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 +#define PCINT4 4 +#define PCINT5 5 +#define PCINT6 6 +#define PCINT7 7 + +#define PCMSK1 _SFR_MEM8(0x6B) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 + +#define PCMSK2 _SFR_MEM8(0x6C) +#define PCINT16 0 +#define PCINT17 1 +#define PCINT18 2 +#define PCINT19 3 +#define PCINT20 4 +#define PCINT21 5 +#define PCINT22 6 +#define PCINT23 7 + +#define T2ICR _SFR_MEM16(0x6E) + +#define T2ICRL _SFR_MEM8(0x6E) +#define T2ICRL0 0 +#define T2ICRL1 1 +#define T2ICRL2 2 +#define T2ICRL3 3 +#define T2ICRL4 4 +#define T2ICRL5 5 +#define T2ICRL6 6 +#define T2ICRL7 7 + +#define T2ICRH _SFR_MEM8(0x6F) +#define T2ICRH0 0 +#define T2ICRH1 1 +#define T2ICRH2 2 +#define T2ICRH3 3 +#define T2ICRH4 4 +#define T2ICRH5 5 +#define T2ICRH6 6 +#define T2ICRH7 7 + +#define T2COR _SFR_MEM16(0x70) + +#define T2CORL _SFR_MEM8(0x70) +#define T2CORL0 0 +#define T2CORL1 1 +#define T2CORL2 2 +#define T2CORL3 3 +#define T2CORL4 4 +#define T2CORL5 5 +#define T2CORL6 6 +#define T2CORL7 7 + +#define T2CORH _SFR_MEM8(0x71) +#define T2CORH0 0 +#define T2CORH1 1 +#define T2CORH2 2 +#define T2CORH3 3 +#define T2CORH4 4 +#define T2CORH5 5 +#define T2CORH6 6 +#define T2CORH7 7 + +#define T2MRA _SFR_MEM8(0x72) +#define T2CS0 0 +#define T2CS1 1 +#define T2CS2 2 +#define T2CE0 3 +#define T2CE1 4 +#define T2CNC 5 +#define T2TP0 6 +#define T2TP1 7 + +#define T2MRB _SFR_MEM8(0x73) +#define T2M0 0 +#define T2M1 1 +#define T2M2 2 +#define T2M3 3 +#define T2TOP 4 +#define T2CPOL 6 +#define T2SSIE 7 + +#define T2IMR _SFR_MEM8(0x74) +#define T2OIM 0 +#define T2CIM 1 +#define T2CPIM 2 +#define T2RXIM 3 +#define T2TXIM 4 +#define T2TCIM 5 + +#define T3ICR _SFR_MEM16(0x76) + +#define T3ICRL _SFR_MEM8(0x76) +#define T3ICRL0 0 +#define T3ICRL1 1 +#define T3ICRL2 2 +#define T3ICRL3 3 +#define T3ICRL4 4 +#define T3ICRL5 5 +#define T3ICRL6 6 +#define T3ICRL7 7 + +#define T3ICRH _SFR_MEM8(0x77) +#define T3ICRH0 0 +#define T3ICRH1 1 +#define T3ICRH2 2 +#define T3ICRH3 3 +#define T3ICRH4 4 +#define T3ICRH5 5 +#define T3ICRH6 6 +#define T3ICRH7 7 + +#define T3CORA _SFR_MEM16(0x78) + +#define T3CORAL _SFR_MEM8(0x78) +#define T3CORAL0 0 +#define T3CORAL1 1 +#define T3CORAL2 2 +#define T3CORAL3 3 +#define T3CORAL4 4 +#define T3CORAL5 5 +#define T3CORAL6 6 +#define T3CORAL7 7 + +#define T3CORAH _SFR_MEM8(0x79) +#define T3CORAH0 0 +#define T3CORAH1 1 +#define T3CORAH2 2 +#define T3CORAH3 3 +#define T3CORAH4 4 +#define T3CORAH5 5 +#define T3CORAH6 6 +#define T3CORAH7 7 + +#define T3CORB _SFR_MEM16(0x7A) + +#define T3CORBL _SFR_MEM8(0x7A) +#define T3CORBL0 0 +#define T3CORBL1 1 +#define T3CORBL2 2 +#define T3CORBL3 3 +#define T3CORBL4 4 +#define T3CORBL5 5 +#define T3CORBL6 6 +#define T3CORBL7 7 + +#define T3CORBH _SFR_MEM8(0x7B) +#define T3CORBH0 0 +#define T3CORBH1 1 +#define T3CORBH2 2 +#define T3CORBH3 3 +#define T3CORBH4 4 +#define T3CORBH5 5 +#define T3CORBH6 6 +#define T3CORBH7 7 + +#define T3MRA _SFR_MEM8(0x7C) +#define T3CS0 0 +#define T3CS1 1 +#define T3CS2 2 +#define T3CE0 3 +#define T3CE1 4 +#define T3CNC 5 +#define T3ICS0 6 +#define T3ICS1 7 + +#define T3MRB _SFR_MEM8(0x7D) +#define T3M0 0 +#define T3M1 1 +#define T3M2 2 +#define T3TOP 4 + +#define T3CRB _SFR_MEM8(0x7E) +#define T3CTMA 0 +#define T3SAMA 1 +#define T3CRMA 2 +#define T3CTMB 3 +#define T3SAMB 4 +#define T3CRMB 5 +#define T3CPRM 6 + +#define T3IMR _SFR_MEM8(0x7F) +#define T3OIM 0 +#define T3CAIM 1 +#define T3CBIM 2 +#define T3CPIM 3 + +#define LFIMR _SFR_MEM8(0x81) +#define LFWIM 0 +#define LFBIM 1 +#define LFEIM 2 + +#define LFRCR _SFR_MEM8(0x82) +#define LFEN 0 +#define LFBM 1 +#define LFWM0 2 +#define LFWM1 3 +#define LFRSS 4 +#define LFCS0 5 +#define LFCS1 6 +#define LFCS2 7 + +#define LFHCR _SFR_MEM8(0x83) +#define LFHCR0 0 +#define LFHCR1 1 +#define LFHCR2 2 +#define LFHCR3 3 +#define LFHCR4 4 +#define LFHCR5 5 +#define LFHCR6 6 + +#define LFIDC _SFR_MEM16(0x84) + +#define LFIDCL _SFR_MEM8(0x84) +#define LFIDCL_0 0 +#define LFIDCL_1 1 +#define LFIDCL_2 2 +#define LFIDCL_3 3 +#define LFIDCL_4 4 +#define LFIDCL_5 5 +#define LFIDCL_6 6 +#define LFIDCL_7 7 + +#define LFIDCH _SFR_MEM8(0x85) +#define LFIDCH_8 0 +#define LFIDCH_9 1 +#define LFIDCH_10 2 +#define LFIDCH_11 3 +#define LFIDCH_12 4 +#define LFIDCH_13 5 +#define LFIDCH_14 6 +#define LFIDCH_15 7 + +#define LFCAL _SFR_MEM16(0x86) + +#define LFCALL _SFR_MEM8(0x86) +#define LFCAL_00 0 +#define LFCAL_01 1 +#define LFCAL_02 2 +#define LFCAL_03 3 +#define LFCAL_04 4 +#define LFCAL_05 5 +#define LFCAL_06 6 +#define LFCAL_07 7 + +#define LFCALH _SFR_MEM8(0x87) +#define LFCAL_08 0 +#define LFCAL_09 1 +#define LFCAL_10 2 +#define LFCAL_11 3 +#define LFCAL_12 4 +#define LFCAL_13 5 +#define LFCAL_14 6 +#define LFCAL_15 7 + + +/* Interrupt vectors */ +/* Vector 0 is the reset vector */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +#define PCINT0_vect_num 3 +#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ +#define PCINT1_vect_num 4 +#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 1 */ +#define PCINT2_vect_num 5 +#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 2 */ +#define INTVM_vect_num 6 +#define INTVM_vect _VECTOR(6) /* Voltage Monitor Interrupt */ +#define SENINT_vect_num 7 +#define SENINT_vect _VECTOR(7) /* Sensor Interface Interrupt */ +#define INTT0_vect_num 8 +#define INTT0_vect _VECTOR(8) /* Timer0 Interval Interrupt */ +#define LFWP_vect_num 9 +#define LFWP_vect _VECTOR(9) /* LF-Receiver Wake-up Interrupt */ +#define T3CAP_vect_num 10 +#define T3CAP_vect _VECTOR(10) /* Timer/Counter3 Capture Event */ +#define T3COMA_vect_num 11 +#define T3COMA_vect _VECTOR(11) /* Timer/Counter3 Compare Match A */ +#define T3COMB_vect_num 12 +#define T3COMB_vect _VECTOR(12) /* Timer/Counter3 Compare Match B */ +#define T3OVF_vect_num 13 +#define T3OVF_vect _VECTOR(13) /* Timer/Counter3 Overflow */ +#define T2CAP_vect_num 14 +#define T2CAP_vect _VECTOR(14) /* Timer/Counter2 Capture Event */ +#define T2COM_vect_num 15 +#define T2COM_vect _VECTOR(15) /* Timer/Counter2 Compare Match */ +#define T2OVF_vect_num 16 +#define T2OVF_vect _VECTOR(16) /* Timer/Counter2 Overflow */ +#define SPISTC_vect_num 17 +#define SPISTC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ +#define LFRXB_vect_num 18 +#define LFRXB_vect _VECTOR(18) /* LF Receive Buffer Interrupt */ +#define INTT1_vect_num 19 +#define INTT1_vect _VECTOR(19) /* Timer1 Interval Interrupt */ +#define T2RXB_vect_num 20 +#define T2RXB_vect _VECTOR(20) /* Timer2 SSI Receive Buffer Interrupt */ +#define T2TXB_vect_num 21 +#define T2TXB_vect _VECTOR(21) /* Timer2 SSI Transmit Buffer Interrupt */ +#define T2TXC_vect_num 22 +#define T2TXC_vect _VECTOR(22) /* Timer2 SSI Transmit Complete Interrupt */ +#define LFREOB_vect_num 23 +#define LFREOB_vect _VECTOR(23) /* LF-Receiver End of Burst Interrupt */ +#define EXCM_vect_num 24 +#define EXCM_vect _VECTOR(24) /* External Input Clock break down Interrupt */ +#define EEREADY_vect_num 25 +#define EEREADY_vect _VECTOR(25) /* EEPROM Ready Interrupt */ +#define SPM_RDY_vect_num 26 +#define SPM_RDY_vect _VECTOR(26) /* Store Program Memory Ready */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (27 * _VECTOR_SIZE) + + +/* Constants */ +#define SPM_PAGESIZE (64) +#define RAMSTART (0x100) +#define RAMSIZE (512) +#define RAMEND (RAMSTART + RAMSIZE - 1) +#define XRAMSTART (NA) +#define XRAMSIZE (0) +#define XRAMEND RAMEND +#define E2END (320 - 1) +#define E2PAGESIZE (4) +#define FLASHEND (8192 - 1) + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 2 + +/* Low Fuse Byte */ +#define FUSE_TSRDI ~_BV(0) /* Disable Temperature shutdown Reset */ +#define FUSE_BODEN ~_BV(1) /* Enable Brown-out detection */ +#define FUSE_FRCFS ~_BV(2) /* Fast RC-Oscillator Frequency select */ +#define FUSE_WDRCON ~_BV(3) /* Enable Watchdog RC-Oscillator */ +#define FUSE_SUT0 ~_BV(4) /* Select start-up time */ +#define FUSE_SUT1 ~_BV(5) /* Select start-up time */ +#define FUSE_CKOUT ~_BV(6) /* Clock output */ +#define FUSE_CKDIV8 ~_BV(7) /* Divide clock by 8 */ +#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_WDRCON & FUSE_BODEN) + +/* High Fuse Byte */ +#define FUSE_BOOTRST ~_BV(0) /* Select reset vector */ +#define FUSE_BOOTSZ0 ~_BV(1) /* Boot size select */ +#define FUSE_BOOTSZ1 ~_BV(2) /* Boot size select */ +#define FUSE_EESAVE ~_BV(3) /* EEPROM memory is preserved through chip erase */ +#define FUSE_WDTON ~_BV(4) /* Watchdog Timer Always On */ +#define FUSE_SPIEN ~_BV(5) /* Enable Serial programming and Data Downloading */ +#define FUSE_DWEN ~_BV(6) /* debugWIRE Enable */ +#define FUSE_EELOCK ~_BV(7) /* Upper EEPROM Locked (disabled) */ +#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x82 + +#define SLEEP_MODE_IDLE (0) +#define SLEEP_MODE_SENSOR_NOISE_REDUCTION (_BV(SM0)) +#define SLEEP_MODE_PWR_DOWN (_BV(SM1)) + +#endif /* _AVR_ATA6289_H_ */ + diff --git a/hardware/tools/avr/avr/include/avr/ioa6612c.h b/hardware/tools/avr/avr/include/avr/ioa6612c.h new file mode 100644 index 0000000000000000000000000000000000000000..19a72099f4037b24d0ab32a2f304f0bec142f033 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/ioa6612c.h @@ -0,0 +1,795 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_ATA6612C_H_INCLUDED +#define _AVR_ATA6612C_H_INCLUDED + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa6612c.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa6613c.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa6614q.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa6616c.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +/* Reserved [0x06..0x11] */ + +#define PORTCR _SFR_IO8(0x12) +#define PUDA 0 +#define PUDB 1 +#define BBMA 4 +#define BBMB 5 + +/* Reserved [0x13..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +/* Reserved [0x17..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSR1 0 +#define PSR0 1 +#define TSM 7 + +/* Reserved [0x24] */ + +#define TCCR0A _SFR_IO8(0x25) +#define WGM00 0 +#define WGM01 1 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x26) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x27) +#define TCNT00 0 +#define TCNT01 1 +#define TCNT02 2 +#define TCNT03 3 +#define TCNT04 4 +#define TCNT05 5 +#define TCNT06 6 +#define TCNT07 7 + +#define OCR0A _SFR_IO8(0x28) +#define OCR00 0 +#define OCR01 1 +#define OCR02 2 +#define OCR03 3 +#define OCR04 4 +#define OCR05 5 +#define OCR06 6 +#define OCR07 7 + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACIRS 6 +#define ACD 7 + +#define DWDR _SFR_IO8(0x31) +#define DWDR0 0 +#define DWDR1 1 +#define DWDR2 2 +#define DWDR3 3 +#define DWDR4 4 +#define DWDR5 5 +#define DWDR6 6 +#define DWDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define SIGRD 5 +#define RWWSB 6 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define CLKCSR _SFR_MEM8(0x62) +#define CLKC0 0 +#define CLKC1 1 +#define CLKC2 2 +#define CLKC3 3 +#define CLKRDY 4 +#define CLKCCE 7 + +#define CLKSELR _SFR_MEM8(0x63) +#define CSEL0 0 +#define CSEL1 1 +#define CSEL2 2 +#define CSEL3 3 +#define CSUT0 4 +#define CSUT1 5 +#define COUT 6 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 +#define PRSPI 4 +#define PRLIN 5 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa6617c.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +/* Reserved [0x06..0x11] */ + +#define PORTCR _SFR_IO8(0x12) +#define PUDA 0 +#define PUDB 1 +#define BBMA 4 +#define BBMB 5 + +/* Reserved [0x13..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +/* Reserved [0x17..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSR1 0 +#define PSR0 1 +#define TSM 7 + +/* Reserved [0x24] */ + +#define TCCR0A _SFR_IO8(0x25) +#define WGM00 0 +#define WGM01 1 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x26) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x27) +#define TCNT00 0 +#define TCNT01 1 +#define TCNT02 2 +#define TCNT03 3 +#define TCNT04 4 +#define TCNT05 5 +#define TCNT06 6 +#define TCNT07 7 + +#define OCR0A _SFR_IO8(0x28) +#define OCR00 0 +#define OCR01 1 +#define OCR02 2 +#define OCR03 3 +#define OCR04 4 +#define OCR05 5 +#define OCR06 6 +#define OCR07 7 + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACIRS 6 +#define ACD 7 + +#define DWDR _SFR_IO8(0x31) +#define DWDR0 0 +#define DWDR1 1 +#define DWDR2 2 +#define DWDR3 3 +#define DWDR4 4 +#define DWDR5 5 +#define DWDR6 6 +#define DWDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define SIGRD 5 +#define RWWSB 6 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define CLKCSR _SFR_MEM8(0x62) +#define CLKC0 0 +#define CLKC1 1 +#define CLKC2 2 +#define CLKC3 3 +#define CLKRDY 4 +#define CLKCCE 7 + +#define CLKSELR _SFR_MEM8(0x63) +#define CSEL0 0 +#define CSEL1 1 +#define CSEL2 2 +#define CSEL3 3 +#define CSUT0 4 +#define CSUT1 5 +#define COUT 6 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 +#define PRSPI 4 +#define PRLIN 5 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa664251.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +/* Reserved [0x06..0x11] */ + +#define PORTCR _SFR_IO8(0x12) +#define PUDA 0 +#define PUDB 1 +#define BBMA 4 +#define BBMB 5 + +/* Reserved [0x13..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +/* Reserved [0x17..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSR1 0 +#define PSR0 1 +#define TSM 7 + +/* Reserved [0x24] */ + +#define TCCR0A _SFR_IO8(0x25) +#define WGM00 0 +#define WGM01 1 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x26) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x27) +#define TCNT00 0 +#define TCNT01 1 +#define TCNT02 2 +#define TCNT03 3 +#define TCNT04 4 +#define TCNT05 5 +#define TCNT06 6 +#define TCNT07 7 + +#define OCR0A _SFR_IO8(0x28) +#define OCR00 0 +#define OCR01 1 +#define OCR02 2 +#define OCR03 3 +#define OCR04 4 +#define OCR05 5 +#define OCR06 6 +#define OCR07 7 + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACIRS 6 +#define ACD 7 + +#define DWDR _SFR_IO8(0x31) +#define DWDR0 0 +#define DWDR1 1 +#define DWDR2 2 +#define DWDR3 3 +#define DWDR4 4 +#define DWDR5 5 +#define DWDR6 6 +#define DWDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define SIGRD 5 +#define RWWSB 6 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define CLKCSR _SFR_MEM8(0x62) +#define CLKC0 0 +#define CLKC1 1 +#define CLKC2 2 +#define CLKC3 3 +#define CLKRDY 4 +#define CLKCCE 7 + +#define CLKSELR _SFR_MEM8(0x63) +#define CSEL0 0 +#define CSEL1 1 +#define CSEL2 2 +#define CSEL3 3 +#define CSUT0 4 +#define CSUT1 5 +#define COUT 6 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 +#define PRSPI 4 +#define PRLIN 5 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa8210.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PRR0 _SFR_IO8(0x01) +#define PRSPI 0 +#define PRRXDC 1 +#define PRTXDC 2 +#define PRCRC 3 +#define PRVM 4 +#define PRCO 5 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa8510.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PRR0 _SFR_IO8(0x01) +#define PRSPI 0 +#define PRRXDC 1 +#define PRTXDC 2 +#define PRCRC 3 +#define PRVM 4 +#define PRCO 5 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioat94k.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* UART1 Baud Rate Register */ +#define UBRR1 _SFR_IO8(0x00) + +/* UART1 Control and Status Registers */ +#define UCSR1B _SFR_IO8(0x01) +#define UCSR1A _SFR_IO8(0x02) + +/* UART1 I/O Data Register */ +#define UDR1 _SFR_IO8(0x03) + +/* 0x04 reserved */ + +/* Input Pins, Port E */ +#define PINE _SFR_IO8(0x05) + +/* Data Direction Register, Port E */ +#define DDRE _SFR_IO8(0x06) + +/* Data Register, Port E */ +#define PORTE _SFR_IO8(0x07) + +/* On Chip Debug Register (reserved) */ +#define OCDR _SFR_IO8(0x08) + +/* UART0 Baud Rate Register */ +#define UBRR0 _SFR_IO8(0x09) + +/* UART0 Control and Status Registers */ +#define UCSR0B _SFR_IO8(0x0A) +#define UCSR0A _SFR_IO8(0x0B) + +/* UART0 I/O Data Register */ +#define UDR0 _SFR_IO8(0x0C) + +/* 0x0D..0x0F reserved */ + +/* Input Pins, Port D */ +#define PIND _SFR_IO8(0x10) + +/* Data Direction Register, Port D */ +#define DDRD _SFR_IO8(0x11) + +/* Data Register, Port D */ +#define PORTD _SFR_IO8(0x12) + +/* FPGA I/O Select Control Register */ +#define FISCR _SFR_IO8(0x13) + +/* FPGA I/O Select Registers A, B, C, D */ +#define FISUA _SFR_IO8(0x14) +#define FISUB _SFR_IO8(0x15) +#define FISUC _SFR_IO8(0x16) +#define FISUD _SFR_IO8(0x17) + +/* FPGA Cache Logic(R) registers (top secret, under NDA) */ +#define FPGAX _SFR_IO8(0x18) +#define FPGAY _SFR_IO8(0x19) +#define FPGAZ _SFR_IO8(0x1A) +#define FPGAD _SFR_IO8(0x1B) + +/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ + +/* 2-wire Serial Bit Rate Register */ +#define TWBR _SFR_IO8(0x1C) + +/* 2-wire Serial Status Register */ +#define TWSR _SFR_IO8(0x1D) + +/* 2-wire Serial (Slave) Address Register */ +#define TWAR _SFR_IO8(0x1E) + +/* 2-wire Serial Data Register */ +#define TWDR _SFR_IO8(0x1F) + +/* UART Baud Register High */ +#define UBRRH _SFR_IO8(0x20) +#define UBRRHI UBRRH /* New name in datasheet (1138F-FPSLI-06/02) */ + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* Timer/Counter2 Output Compare Register */ +#define OCR2 _SFR_IO8(0x22) + +/* Timer/Counter2 (8-bit) */ +#define TCNT2 _SFR_IO8(0x23) + +/* Timer/Counter1 Input Capture Register */ +#define ICR1 _SFR_IO16(0x24) +#define ICR1L _SFR_IO8(0x24) +#define ICR1H _SFR_IO8(0x25) + +/* Asynchronous mode StatuS Register */ +#define ASSR _SFR_IO8(0x26) + +/* Timer/Counter2 Control Register */ +#define TCCR2 _SFR_IO8(0x27) + +/* Timer/Counter1 Output Compare RegisterB */ +#define OCR1B _SFR_IO16(0x28) +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Timer/Counter1 Output Compare RegisterA */ +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Timer/Counter1 */ +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +/* Timer/Counter1 Control Register B */ +#define TCCR1B _SFR_IO8(0x2E) + +/* Timer/Counter1 Control Register A */ +#define TCCR1A _SFR_IO8(0x2F) + +/* Special Function IO Register */ +#define SFIOR _SFR_IO8(0x30) + +/* Timer/Counter0 Output Compare Register */ +#define OCR0 _SFR_IO8(0x31) + +/* Timer/Counter0 (8-bit) */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* 0x34 reserved */ + +/* MCU Control/Status Register */ +#define MCUR _SFR_IO8(0x35) + +/* 2-wire Serial Control Register */ +#define TWCR _SFR_IO8(0x36) + +/* 0x37 reserved */ + +/* Timer/Counter Interrupt Flag Register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK Register */ +#define TIMSK _SFR_IO8(0x39) + +/* Software Control Register */ +#define SFTCR _SFR_IO8(0x3A) + +/* External Interrupt Mask/Flag Register */ +#define EIMF _SFR_IO8(0x3B) + +/* 0x3C reserved */ + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +#define SIG_FPGA_INTERRUPT0 _VECTOR(1) /* FPGA_INT0 */ +#define SIG_INTERRUPT0 _VECTOR(2) /* EXT_INT0 */ +#define SIG_FPGA_INTERRUPT1 _VECTOR(3) /* FPGA_INT1 */ +#define SIG_INTERRUPT1 _VECTOR(4) /* EXT_INT1 */ +#define SIG_FPGA_INTERRUPT2 _VECTOR(5) /* FPGA_INT2 */ +#define SIG_INTERRUPT2 _VECTOR(6) /* EXT_INT2 */ +#define SIG_FPGA_INTERRUPT3 _VECTOR(7) /* FPGA_INT3 */ +#define SIG_INTERRUPT3 _VECTOR(8) /* EXT_INT3 */ +#define SIG_OUTPUT_COMPARE2 _VECTOR(9) /* TIM2_COMP */ +#define SIG_OVERFLOW2 _VECTOR(10) /* TIM2_OVF */ +#define SIG_INPUT_CAPTURE1 _VECTOR(11) /* TIM1_CAPT */ +#define SIG_OUTPUT_COMPARE1A _VECTOR(12) /* TIM1_COMPA */ +#define SIG_OUTPUT_COMPARE1B _VECTOR(13) /* TIM1_COMPB */ +#define SIG_OVERFLOW1 _VECTOR(14) /* TIM1_OVF */ +#define SIG_OUTPUT_COMPARE0 _VECTOR(15) /* TIM0_COMP */ +#define SIG_OVERFLOW0 _VECTOR(16) /* TIM0_OVF */ +#define SIG_FPGA_INTERRUPT4 _VECTOR(17) /* FPGA_INT4 */ +#define SIG_FPGA_INTERRUPT5 _VECTOR(18) /* FPGA_INT5 */ +#define SIG_FPGA_INTERRUPT6 _VECTOR(19) /* FPGA_INT6 */ +#define SIG_FPGA_INTERRUPT7 _VECTOR(20) /* FPGA_INT7 */ +#define SIG_UART0_RECV _VECTOR(21) /* UART0_RXC */ +#define SIG_UART0_DATA _VECTOR(22) /* UART0_DRE */ +#define SIG_UART0_TRANS _VECTOR(23) /* UART0_TXC */ +#define SIG_FPGA_INTERRUPT8 _VECTOR(24) /* FPGA_INT8 */ +#define SIG_FPGA_INTERRUPT9 _VECTOR(25) /* FPGA_INT9 */ +#define SIG_FPGA_INTERRUPT10 _VECTOR(26) /* FPGA_INT10 */ +#define SIG_FPGA_INTERRUPT11 _VECTOR(27) /* FPGA_INT11 */ +#define SIG_UART1_RECV _VECTOR(28) /* UART1_RXC */ +#define SIG_UART1_DATA _VECTOR(29) /* UART1_DRE */ +#define SIG_UART1_TRANS _VECTOR(30) /* UART1_TXC */ +#define SIG_FPGA_INTERRUPT12 _VECTOR(31) /* FPGA_INT12 */ +#define SIG_FPGA_INTERRUPT13 _VECTOR(32) /* FPGA_INT13 */ +#define SIG_FPGA_INTERRUPT14 _VECTOR(33) /* FPGA_INT14 */ +#define SIG_FPGA_INTERRUPT15 _VECTOR(34) /* FPGA_INT15 */ +#define SIG_2WIRE_SERIAL _VECTOR(35) /* TWS_INT */ + +#define _VECTORS_SIZE 144 + +/* Bit numbers (SFRs alphabetically sorted) */ + +/* ASSR */ +#define AS2 3 +#define TCN2UB 2 +#define OCR2UB 1 +#define TCR2UB 0 + +/* DDRD */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* DDRE */ +#define DDE7 7 +#define DDE6 6 +#define DDE5 5 +#define DDE4 4 +#define DDE3 3 +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +/* EIMF */ +#define INTF3 7 +#define INTF2 6 +#define INTF1 5 +#define INTF0 4 +#define INT3 3 +#define INT2 2 +#define INT1 1 +#define INT0 0 + +/* FISCR */ +#define FIADR 7 +#define XFIS1 1 +#define XFIS0 0 + +/* FISUA */ +#define FIF3 7 +#define FIF2 6 +#define FIF1 5 +#define FIF0 4 +#define FINT3 3 +#define FINT2 2 +#define FINT1 1 +#define FINT0 0 + +/* FISUB */ +#define FIF7 7 +#define FIF6 6 +#define FIF5 5 +#define FIF4 4 +#define FINT7 3 +#define FINT6 2 +#define FINT5 1 +#define FINT4 0 + +/* FISUC */ +#define FIF11 7 +#define FIF10 6 +#define FIF9 5 +#define FIF8 4 +#define FINT11 3 +#define FINT10 2 +#define FINT9 1 +#define FINT8 0 + +/* FISUD */ +#define FIF15 7 +#define FIF14 6 +#define FIF13 5 +#define FIF12 4 +#define FINT15 3 +#define FINT14 2 +#define FINT13 1 +#define FINT12 0 + +/* MCUR */ +#define JTRF 7 +#define JTD 6 +#define SE 5 +#define SM1 4 +#define SM0 3 +#define PORF 2 +#define WDRF 1 +#define EXTRF 0 + +/* OCDR (reserved) */ +#define IDRD 7 + +/* PIND */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* PINE */ +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +/* PORTD */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* PORTE */ +/* + PE7 = IC1 / INT3 (alternate) + PE6 = OC1A / INT2 (alternate) + PE5 = OC1B / INT1 (alternate) + PE4 = ET11 / INT0 (alternate) + PE3 = OC2 / RX1 (alternate) + PE2 = / TX1 (alternate) + PE1 = OC0 / RX0 (alternate) + PE0 = ET0 / TX0 (alternate) + */ +#define PE7 7 +#define PE6 6 +#define PE5 5 +#define PE4 4 +#define PE3 3 +#define PE2 2 +#define PE1 1 +#define PE0 0 + +/* SFIOR */ +#define PSR2 1 +#define PSR10 0 + +/* SFTCR */ +#define FMXOR 3 +#define WDTS 2 +#define DBG 1 +#define SRST 0 + +/* TCCR0 */ +#define FOC0 7 +#define PWM0 6 +#define COM01 5 +#define COM00 4 +#define CTC0 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* TCCR1A */ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define FOC1A 3 +#define FOC1B 2 +#define PWM11 1 +#define PWM10 0 + +/* TCCR1B */ +#define ICNC1 7 +#define ICES1 6 +#define ICPE 5 +#define CTC1 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* TCCR2 */ +#define FOC2 7 +#define PWM2 6 +#define COM21 5 +#define COM20 4 +#define CTC2 3 +#define CS22 2 +#define CS21 1 +#define CS20 0 + +/* TIFR */ +#define TOV1 7 +#define OCF1A 6 +#define OCF1B 5 +#define TOV2 4 +#define ICF1 3 +#define OCF2 2 +#define TOV0 1 +#define OCF0 0 + +/* TIMSK */ +#define TOIE1 7 +#define OCIE1A 6 +#define OCIE1B 5 +#define TOIE2 4 +#define TICIE1 3 +#define OCIE2 2 +#define TOIE0 1 +#define OCIE0 0 + +/* TWAR */ +/* #define TWA 1 */ /* TWA is bits 7:1 */ +#define TWGCE 0 + +/* TWCR */ +#define TWINT 7 +#define TWEA 6 +#define TWSTA 5 +#define TWSTO 4 +#define TWWC 3 +#define TWEN 2 +#define TWIE 0 + +/* TWSR */ +#define TWS7 7 +#define TWS6 6 +#define TWS5 5 +#define TWS4 4 +#define TWS3 3 + +/* UBRRHI + Bits 11..8 of UART1 are bits 7..4 of UBRRHI. + Bits 11..8 of UART0 are bits 3..0 of UBRRHI. */ +/* #define UBRRHI1 4 */ +/* #define UBRRHI0 0 */ + +/* UCSR0A */ +#define RXC0 7 +#define TXC0 6 +#define UDRE0 5 +#define FE0 4 +#define OR0 3 +#define U2X0 1 +#define MPCM0 0 + +/* UCSR0B */ +#define RXCIE0 7 +#define TXCIE0 6 +#define UDRIE0 5 +#define RXEN0 4 +#define TXEN0 3 +#define CHR90 2 +#define RXB80 1 +#define TXB80 0 + +/* UCSR1A */ +#define RXC1 7 +#define TXC1 6 +#define UDRE1 5 +#define FE1 4 +#define OR1 3 +#define U2X1 1 +#define MPCM1 0 + +/* UCSR1B */ +#define RXCIE1 7 +#define TXCIE1 6 +#define UDRIE1 5 +#define RXEN1 4 +#define TXEN1 3 +#define CHR91 2 +#define RXB81 1 +#define TXB81 0 + +/* WDTCR */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* + Last memory addresses - depending on configuration, it is possible + to have 20K-32K of program memory and 4K-16K of data memory + (all in the same 36K total of SRAM, loaded from external EEPROM). + */ + +#ifndef RAMSTART +#define RAMSTART 0x60 +#endif + +#ifndef RAMEND +#define RAMEND 0x0FFF +#endif + +#ifndef XRAMEND +#define XRAMEND RAMEND +#endif + +#define E2END 0 + +#ifndef FLASHEND +#define FLASHEND 0x7FFF +#endif + +#define SLEEP_MODE_IDLE 0 +#define SLEEP_MODE_PWR_DOWN _BV(SM1) +#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) + +#endif /* _AVR_IOAT94K_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/ioavr128da28.h b/hardware/tools/avr/avr/include/avr/ioavr128da28.h new file mode 100644 index 0000000000000000000000000000000000000000..e502a9c70aa23e20f0c503e0a004c2b20231cb2f --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/ioavr128da28.h @@ -0,0 +1,7128 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioavr128da28.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_AVR128DA28_H_INCLUDED +#define _AVR_AVR128DA28_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPZ _SFR_MEM8(0x003B) /* Extended Z-pointer Register */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t MUXCTRL; /* Mux Control A */ + register8_t reserved_1[2]; + register8_t DACREF; /* DAC Voltage Reference */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NONE_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_MEDIUM_gc = (0x02<<1), /* Medium hysteresis */ + AC_HYSMODE_LARGE_gc = (0x03<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* AC Output Initial Value select */ +typedef enum AC_INITVAL_enum +{ + AC_INITVAL_LOW_gc = (0x00<<6), /* Output initialized to 0 */ + AC_INITVAL_HIGH_gc = (0x01<<6), /* Output initialized to 1 */ +} AC_INITVAL_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_ABOVE_gc = (0x00<<4), /* Entering window state above */ + AC_INTMODE_INSIDE_gc = (0x01<<4), /* Entering window state inside */ + AC_INTMODE_BELOW_gc = (0x02<<4), /* Entering window state below */ + AC_INTMODE_OUTSIDE_gc = (0x03<<4), /* Entering window state above or below */ +} AC_INTMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_AINN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_AINN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_AINN2_gc = (0x02<<0), /* Negative Pin 2 */ + AC_MUXNEG_DACREF_gc = (0x03<<0), /* DAC Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_AINP0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_AINP1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_AINP2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_AINP3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* Power profile select */ +typedef enum AC_POWER_enum +{ + AC_POWER_PROFILE0_gc = (0x00<<3), /* Power profile 0, lowest consumption and highest response time. */ + AC_POWER_PROFILE1_gc = (0x01<<3), /* Power profile 1 */ + AC_POWER_PROFILE2_gc = (0x02<<3), /* Power profile 2 */ + AC_POWER_PROFILE3_gc = (0x03<<3), /* Power profile 3 */ +} AC_POWER_t; + +/* Window selection mode select */ +typedef enum AC_WINSEL_enum +{ + AC_WINSEL_DISABLED_gc = (0x00<<0), /* Window function disabled */ + AC_WINSEL_UPSEL1_gc = (0x01<<0), /* Select ACn+1 as upper limit in window compare. */ + AC_WINSEL_UPSEL2_gc = (0x02<<0), /* Select ACn+2 as upper limit in window compare. */ +} AC_WINSEL_t; + +/* Analog Comparator Window State select */ +typedef enum AC_WINSTATE_enum +{ + AC_WINSTATE_ABOVE_gc = (0x00<<6), /* Above window */ + AC_WINSTATE_INSIDE_gc = (0x01<<6), /* Inside window */ + AC_WINSTATE_BELOW_gc = (0x02<<6), /* Below window */ +} AC_WINSTATE_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t reserved_1[2]; + register8_t MUXPOS; /* Positive mux input */ + register8_t MUXNEG; /* Negative mux input */ + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t reserved_2[2]; +} ADC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXNEG_enum +{ + ADC_MUXNEG_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXNEG_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXNEG_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXNEG_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXNEG_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXNEG_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXNEG_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXNEG_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXNEG_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXNEG_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXNEG_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXNEG_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXNEG_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ + ADC_MUXNEG_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ + ADC_MUXNEG_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ + ADC_MUXNEG_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ + ADC_MUXNEG_GND_gc = (0x40<<0), /* Ground */ + ADC_MUXNEG_DAC0_gc = (0x48<<0), /* DAC0 */ +} ADC_MUXNEG_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ + ADC_MUXPOS_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ + ADC_MUXPOS_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ + ADC_MUXPOS_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ + ADC_MUXPOS_AIN16_gc = (0x10<<0), /* ADC input pin 16 */ + ADC_MUXPOS_AIN17_gc = (0x11<<0), /* ADC input pin 17 */ + ADC_MUXPOS_AIN18_gc = (0x12<<0), /* ADC input pin 18 */ + ADC_MUXPOS_AIN19_gc = (0x13<<0), /* ADC input pin 19 */ + ADC_MUXPOS_AIN20_gc = (0x14<<0), /* ADC input pin 20 */ + ADC_MUXPOS_AIN21_gc = (0x15<<0), /* ADC input pin 21 */ + ADC_MUXPOS_GND_gc = (0x40<<0), /* Ground */ + ADC_MUXPOS_TEMPSENSE_gc = (0x42<<0), /* Temperature sensor */ + ADC_MUXPOS_DAC0_gc = (0x48<<0), /* DAC0 */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV12_gc = (0x03<<0), /* CLK_PER divided by 12 */ + ADC_PRESC_DIV16_gc = (0x04<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV20_gc = (0x05<<0), /* CLK_PER divided by 20 */ + ADC_PRESC_DIV24_gc = (0x06<<0), /* CLK_PER divided by 24 */ + ADC_PRESC_DIV28_gc = (0x07<<0), /* CLK_PER divided by 28 */ + ADC_PRESC_DIV32_gc = (0x08<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV48_gc = (0x09<<0), /* CLK_PER divided by 48 */ + ADC_PRESC_DIV64_gc = (0x0A<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV96_gc = (0x0B<<0), /* CLK_PER divided by 96 */ + ADC_PRESC_DIV128_gc = (0x0C<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x0D<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Resolution selection select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_12BIT_gc = (0x00<<2), /* 12-bit mode */ + ADC_RESSEL_10BIT_gc = (0x01<<2), /* 10-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_NONE_gc = (0x00<<0), /* No accumulation */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* 2 results accumulated */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* 4 results accumulated */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* 8 results accumulated */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* 16 results accumulated */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* 32 results accumulated */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* 64 results accumulated */ + ADC_SAMPNUM_ACC128_gc = (0x07<<0), /* 128 results accumulated */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.9 V */ + BOD_LVL_BODLEVEL1_gc = (0x01<<0), /* 2.45 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.7 V */ + BOD_LVL_BODLEVEL3_gc = (0x03<<0), /* 2.85 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_128HZ_gc = (0x00<<4), /* 128Hz sampling frequency */ + BOD_SAMPFREQ_32HZ_gc = (0x01<<4), /* 32Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_FALLING_gc = (0x00<<1), /* VDD falls below VLM threshold */ + BOD_VLMCFG_RISING_gc = (0x01<<1), /* VDD rises above VLM threshold */ + BOD_VLMCFG_BOTH_gc = (0x02<<1), /* VDD crosses VLM threshold */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_OFF_gc = (0x00<<0), /* VLM Disabled */ + BOD_VLMLVL_5ABOVE_gc = (0x01<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x02<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x03<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* Voltage level monitor status select */ +typedef enum BOD_VLMS_enum +{ + BOD_VLMS_ABOVE_gc = (0x00<<0), /* The voltage is above the VLM threshold level */ + BOD_VLMS_BELOW_gc = (0x01<<0), /* The voltage is below the VLM threshold level */ +} BOD_VLMS_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t SEQCTRL1; /* Sequential Control 1 */ + register8_t reserved_1[2]; + register8_t INTCTRL0; /* Interrupt Control 0 */ + register8_t reserved_2[1]; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t LUT2CTRLA; /* LUT Control 2 A */ + register8_t LUT2CTRLB; /* LUT Control 2 B */ + register8_t LUT2CTRLC; /* LUT Control 2 C */ + register8_t TRUTH2; /* Truth 2 */ + register8_t LUT3CTRLA; /* LUT Control 3 A */ + register8_t LUT3CTRLB; /* LUT Control 3 B */ + register8_t LUT3CTRLC; /* LUT Control 3 C */ + register8_t TRUTH3; /* Truth 3 */ + register8_t reserved_3[40]; +} CCL_t; + +/* Clock Source Selection select */ +typedef enum CCL_CLKSRC_enum +{ + CCL_CLKSRC_CLKPER_gc = (0x00<<1), /* CLK_PER is clocking the LUT */ + CCL_CLKSRC_IN2_gc = (0x01<<1), /* IN[2] is clocking the LUT */ + CCL_CLKSRC_OSCHF_gc = (0x04<<1), /* Internal high-frequency oscillator before prescaler is clocking LUT */ + CCL_CLKSRC_OSC32K_gc = (0x05<<1), /* Internal 32.768 kHz oscillator */ + CCL_CLKSRC_OSC1K_gc = (0x06<<1), /* Internal 32.768 kHz oscillator divided by 32 */ +} CCL_CLKSRC_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL0_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL0_IN0_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_ZCD0_gc = (0x07<<0), /* ZCD0 OUT input source */ + CCL_INSEL0_USART0_gc = (0x08<<0), /* USART0 TXD input source */ + CCL_INSEL0_SPI0_gc = (0x09<<0), /* SPI0 MOSI input source */ + CCL_INSEL0_TCA0_gc = (0x0A<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCB0_gc = (0x0C<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCD0_gc = (0x0D<<0), /* TCD0 WOA input source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENTA_gc = (0x03<<4), /* Event input source A */ + CCL_INSEL1_EVENTB_gc = (0x04<<4), /* Event input source B */ + CCL_INSEL1_IN1_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC1_gc = (0x06<<4), /* AC1 OUT input source */ + CCL_INSEL1_ZCD1_gc = (0x07<<4), /* ZCD1 OUT input source */ + CCL_INSEL1_USART1_gc = (0x08<<4), /* USART1 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x09<<4), /* SPI0 MOSI input source */ + CCL_INSEL1_TCA0_gc = (0x0A<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCB1_gc = (0x0C<<4), /* TCB1 WO input source */ + CCL_INSEL1_TCD0_gc = (0x0D<<4), /* TCD0 WOB input soruce */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL2_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL2_IN2_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC2_gc = (0x06<<0), /* AC2 OUT input source */ + CCL_INSEL2_ZCD2_gc = (0x07<<0), /* ZCD2 OUT input source */ + CCL_INSEL2_USART2_gc = (0x08<<0), /* USART2 TXD input source */ + CCL_INSEL2_SPI0_gc = (0x09<<0), /* SPI0 SCK input source */ + CCL_INSEL2_TCA0_gc = (0x0A<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCB2_gc = (0x0C<<0), /* TCB2 WO input source */ + CCL_INSEL2_TCD0_gc = (0x0D<<0), /* TCD0 WOC input source */ +} CCL_INSEL2_t; + +/* Interrupt Mode for LUT0 select */ +typedef enum CCL_INTMODE0_enum +{ + CCL_INTMODE0_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled */ + CCL_INTMODE0_RISING_gc = (0x01<<0), /* Sense rising edge */ + CCL_INTMODE0_FALLING_gc = (0x02<<0), /* Sense falling edge */ + CCL_INTMODE0_BOTH_gc = (0x03<<0), /* Sense both edges */ +} CCL_INTMODE0_t; + +/* Interrupt Mode for LUT1 select */ +typedef enum CCL_INTMODE1_enum +{ + CCL_INTMODE1_INTDISABLE_gc = (0x00<<2), /* Interrupt disabled */ + CCL_INTMODE1_RISING_gc = (0x01<<2), /* Sense rising edge */ + CCL_INTMODE1_FALLING_gc = (0x02<<2), /* Sense falling edge */ + CCL_INTMODE1_BOTH_gc = (0x03<<2), /* Sense both edges */ +} CCL_INTMODE1_t; + +/* Interrupt Mode for LUT2 select */ +typedef enum CCL_INTMODE2_enum +{ + CCL_INTMODE2_INTDISABLE_gc = (0x00<<4), /* Interrupt disabled */ + CCL_INTMODE2_RISING_gc = (0x01<<4), /* Sense rising edge */ + CCL_INTMODE2_FALLING_gc = (0x02<<4), /* Sense falling edge */ + CCL_INTMODE2_BOTH_gc = (0x03<<4), /* Sense both edges */ +} CCL_INTMODE2_t; + +/* Interrupt Mode for LUT3 select */ +typedef enum CCL_INTMODE3_enum +{ + CCL_INTMODE3_INTDISABLE_gc = (0x00<<6), /* Interrupt disabled */ + CCL_INTMODE3_RISING_gc = (0x01<<6), /* Sense rising edge */ + CCL_INTMODE3_FALLING_gc = (0x02<<6), /* Sense falling edge */ + CCL_INTMODE3_BOTH_gc = (0x03<<6), /* Sense both edges */ +} CCL_INTMODE3_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL0_enum +{ + CCL_SEQSEL0_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL0_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL0_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL0_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL0_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL0_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL1_enum +{ + CCL_SEQSEL1_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL1_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL1_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL1_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL1_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL1_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[4]; + register8_t OSCHFCTRLA; /* OSCHF Control A */ + register8_t OSCHFTUNE; /* OSCHF Tune */ + register8_t reserved_2[6]; + register8_t PLLCTRLA; /* PLL Control A */ + register8_t reserved_3[7]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_4[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_5[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSCHF_gc = (0x00<<0), /* Internal high-frequency oxcillator */ + CLKCTRL_CLKSEL_OSC32K_gc = (0x01<<0), /* Internal 32.768 kHz oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768 kHz crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1k cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16k cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32k cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ +} CLKCTRL_CSUT_t; + +/* Frequency select select */ +typedef enum CLKCTRL_FREQSEL_enum +{ + CLKCTRL_FREQSEL_1M_gc = (0x00<<2), /* 1 MHz system clock */ + CLKCTRL_FREQSEL_2M_gc = (0x01<<2), /* 2 MHz system clock */ + CLKCTRL_FREQSEL_3M_gc = (0x02<<2), /* 3 MHz system clock */ + CLKCTRL_FREQSEL_4M_gc = (0x03<<2), /* 4 MHz system clock (default) */ + CLKCTRL_FREQSEL_8M_gc = (0x05<<2), /* 8 MHz system clock */ + CLKCTRL_FREQSEL_12M_gc = (0x06<<2), /* 12 MHz system clock */ + CLKCTRL_FREQSEL_16M_gc = (0x07<<2), /* 16 MHz system clock */ + CLKCTRL_FREQSEL_20M_gc = (0x08<<2), /* 20 MHz system clock */ + CLKCTRL_FREQSEL_24M_gc = (0x09<<2), /* 24 MHz system clock */ +} CLKCTRL_FREQSEL_t; + +/* Multiplication factor select */ +typedef enum CLKCTRL_MULFAC_enum +{ + CLKCTRL_MULFAC_DISABLE_gc = (0x00<<0), /* PLL is disabled */ + CLKCTRL_MULFAC_2x_gc = (0x01<<0), /* 2 x multiplication factor */ + CLKCTRL_MULFAC_3x_gc = (0x02<<0), /* 3 x multiplication factor */ + CLKCTRL_MULFAC_4x_gc = (0x03<<0), /* 4 x multiplication factor */ +} CLKCTRL_MULFAC_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* DATA Register */ +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t SWEVENTA; /* Software Event A */ + register8_t SWEVENTB; /* Software Event B */ + register8_t reserved_1[14]; + register8_t CHANNEL0; /* Multiplexer Channel 0 */ + register8_t CHANNEL1; /* Multiplexer Channel 1 */ + register8_t CHANNEL2; /* Multiplexer Channel 2 */ + register8_t CHANNEL3; /* Multiplexer Channel 3 */ + register8_t CHANNEL4; /* Multiplexer Channel 4 */ + register8_t CHANNEL5; /* Multiplexer Channel 5 */ + register8_t CHANNEL6; /* Multiplexer Channel 6 */ + register8_t CHANNEL7; /* Multiplexer Channel 7 */ + register8_t CHANNEL8; /* Multiplexer Channel 8 */ + register8_t CHANNEL9; /* Multiplexer Channel 9 */ + register8_t reserved_2[6]; + register8_t USERCCLLUT0A; /* User 0 - CCL0 Event A */ + register8_t USERCCLLUT0B; /* User 1 - CCL0 Event B */ + register8_t USERCCLLUT1A; /* User 2 - CCL1 Event A */ + register8_t USERCCLLUT1B; /* User 3 - CCL1 Event B */ + register8_t USERCCLLUT2A; /* User 4 - CCL2 Event A */ + register8_t USERCCLLUT2B; /* User 5 - CCL2 Event B */ + register8_t USERCCLLUT3A; /* User 6 - CCL3 Event A */ + register8_t USERCCLLUT3B; /* User 7 - CCL3 Event B */ + register8_t USERCCLLUT4A; /* User 8 - CCL4 Event A */ + register8_t USERCCLLUT4B; /* User 9 - CCL4 Event B */ + register8_t USERCCLLUT5A; /* User 10 - CCL5 Event A */ + register8_t USERCCLLUT5B; /* User 11 - CCL5 Event B */ + register8_t USERADC0START; /* User 12 - ADC0 */ + register8_t USERPTCSTART; /* User 13 - PTC */ + register8_t USEREVSYSEVOUTA; /* User 14 - EVOUTA */ + register8_t USEREVSYSEVOUTB; /* User 15 - EVOUTB */ + register8_t USEREVSYSEVOUTC; /* User 16 - EVOUTC */ + register8_t USEREVSYSEVOUTD; /* User 17 - EVOUTD */ + register8_t USEREVSYSEVOUTE; /* User 18 - EVOUTE */ + register8_t USEREVSYSEVOUTF; /* User 19 - EVOUTF */ + register8_t USEREVSYSEVOUTG; /* User 20 - EVOUTG */ + register8_t USERUSART0IRDA; /* User 21 - USART0 */ + register8_t USERUSART1IRDA; /* User 22 - USART1 */ + register8_t USERUSART2IRDA; /* User 23 - USART2 */ + register8_t USERUSART3IRDA; /* User 24 - USART3 */ + register8_t USERUSART4IRDA; /* User 25 - USART4 */ + register8_t USERUSART5IRDA; /* User 26 - USART5 */ + register8_t USERTCA0CNTA; /* User 27 - TCA0 Event A */ + register8_t USERTCA0CNTB; /* User 28 - TCA0 Event B */ + register8_t USERTCA1CNTA; /* User 29 - TCA1 Event A */ + register8_t USERTCA1CNTB; /* User 30 - TCA1 Event B */ + register8_t USERTCB0CAPT; /* User 31 - TCB0 Event A */ + register8_t USERTCB0COUNT; /* User 32 - TCB0 Event B */ + register8_t USERTCB1CAPT; /* User 33 - TCB1 Event A */ + register8_t USERTCB1COUNT; /* User 34 - TCB1 Event B */ + register8_t USERTCB2CAPT; /* User 35 - TCB2 Event A */ + register8_t USERTCB2COUNT; /* User 36 - TCB2 Event B */ + register8_t USERTCB3CAPT; /* User 37 - TCB3 Event A */ + register8_t USERTCB3COUNT; /* User 38 - TCB3 Event B */ + register8_t USERTCB4CAPT; /* User 39 - TCB4 Event A */ + register8_t USERTCB4COUNT; /* User 40 - TCB4 Event B */ + register8_t USERTCD0INPUTA; /* User 41 - TCD0 Event A */ + register8_t USERTCD0INPUTB; /* User 42 - TCD0 Event B */ + register8_t USEROSCTEST; /* User 43 - OSCTEST */ +} EVSYS_t; + +/* Channel 0 generator select select */ +typedef enum EVSYS_CHANNEL0_enum +{ + EVSYS_CHANNEL0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL0_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL0_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL0_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL0_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL0_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL0_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL0_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL0_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL0_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL0_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL0_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL0_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL0_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL0_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL0_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL0_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL0_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL0_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL0_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL0_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL0_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL0_PORTA_PIN0_gc = (0x40<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL0_PORTA_PIN1_gc = (0x41<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL0_PORTA_PIN2_gc = (0x42<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL0_PORTA_PIN3_gc = (0x43<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL0_PORTA_PIN4_gc = (0x44<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL0_PORTA_PIN5_gc = (0x45<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL0_PORTA_PIN6_gc = (0x46<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL0_PORTA_PIN7_gc = (0x47<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL0_PORTB_PIN0_gc = (0x48<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL0_PORTB_PIN1_gc = (0x49<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL0_PORTB_PIN2_gc = (0x4A<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL0_PORTB_PIN3_gc = (0x4B<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL0_PORTB_PIN4_gc = (0x4C<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL0_PORTB_PIN5_gc = (0x4D<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL0_PORTB_PIN6_gc = (0x4E<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL0_PORTB_PIN7_gc = (0x4F<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL0_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL0_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL0_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL0_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL0_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL0_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL0_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL0_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL0_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL0_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL0_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL0_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL0_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL0_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL0_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL0_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL0_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL0_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL0_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL0_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL0_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL0_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL0_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL0_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL0_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL0_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL0_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL0_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL0_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL0_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL0_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL0_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL0_t; + +/* Channel 1 generator select select */ +typedef enum EVSYS_CHANNEL1_enum +{ + EVSYS_CHANNEL1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL1_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL1_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL1_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL1_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL1_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL1_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL1_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL1_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL1_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL1_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL1_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL1_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL1_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL1_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL1_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL1_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL1_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL1_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL1_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL1_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL1_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL1_PORTA_PIN0_gc = (0x40<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL1_PORTA_PIN1_gc = (0x41<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL1_PORTA_PIN2_gc = (0x42<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL1_PORTA_PIN3_gc = (0x43<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL1_PORTA_PIN4_gc = (0x44<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL1_PORTA_PIN5_gc = (0x45<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL1_PORTA_PIN6_gc = (0x46<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL1_PORTA_PIN7_gc = (0x47<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL1_PORTB_PIN0_gc = (0x48<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL1_PORTB_PIN1_gc = (0x49<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL1_PORTB_PIN2_gc = (0x4A<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL1_PORTB_PIN3_gc = (0x4B<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL1_PORTB_PIN4_gc = (0x4C<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL1_PORTB_PIN5_gc = (0x4D<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL1_PORTB_PIN6_gc = (0x4E<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL1_PORTB_PIN7_gc = (0x4F<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL1_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL1_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL1_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL1_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL1_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL1_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL1_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL1_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL1_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL1_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL1_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL1_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL1_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL1_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL1_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL1_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL1_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL1_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL1_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL1_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL1_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL1_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL1_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL1_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL1_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL1_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL1_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL1_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL1_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL1_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL1_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL1_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL1_t; + +/* Channel 2 generator select select */ +typedef enum EVSYS_CHANNEL2_enum +{ + EVSYS_CHANNEL2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL2_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL2_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL2_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL2_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL2_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL2_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL2_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL2_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL2_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL2_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL2_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL2_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL2_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL2_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL2_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL2_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL2_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL2_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL2_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL2_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL2_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL2_PORTC_PIN0_gc = (0x40<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL2_PORTC_PIN1_gc = (0x41<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL2_PORTC_PIN2_gc = (0x42<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL2_PORTC_PIN3_gc = (0x43<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL2_PORTC_PIN4_gc = (0x44<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL2_PORTC_PIN5_gc = (0x45<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL2_PORTC_PIN6_gc = (0x46<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL2_PORTC_PIN7_gc = (0x47<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL2_PORTD_PIN0_gc = (0x48<<0), /* Port D Pin 0 */ + EVSYS_CHANNEL2_PORTD_PIN1_gc = (0x49<<0), /* Port D Pin 1 */ + EVSYS_CHANNEL2_PORTD_PIN2_gc = (0x4A<<0), /* Port D Pin 2 */ + EVSYS_CHANNEL2_PORTD_PIN3_gc = (0x4B<<0), /* Port D Pin 3 */ + EVSYS_CHANNEL2_PORTD_PIN4_gc = (0x4C<<0), /* Port D Pin 4 */ + EVSYS_CHANNEL2_PORTD_PIN5_gc = (0x4D<<0), /* Port D Pin 5 */ + EVSYS_CHANNEL2_PORTD_PIN6_gc = (0x4E<<0), /* Port D Pin 6 */ + EVSYS_CHANNEL2_PORTD_PIN7_gc = (0x4F<<0), /* Port D Pin 7 */ + EVSYS_CHANNEL2_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL2_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL2_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL2_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL2_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL2_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL2_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL2_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL2_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL2_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL2_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL2_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL2_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL2_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL2_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL2_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL2_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL2_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL2_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL2_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL2_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL2_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL2_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL2_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL2_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL2_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL2_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL2_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL2_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL2_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL2_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL2_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL2_t; + +/* Channel 3 generator select select */ +typedef enum EVSYS_CHANNEL3_enum +{ + EVSYS_CHANNEL3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL3_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL3_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL3_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL3_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL3_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL3_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL3_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL3_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL3_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL3_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL3_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL3_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL3_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL3_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL3_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL3_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL3_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL3_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL3_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL3_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL3_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL3_PORTC_PIN0_gc = (0x40<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL3_PORTC_PIN1_gc = (0x41<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL3_PORTC_PIN2_gc = (0x42<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL3_PORTC_PIN3_gc = (0x43<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL3_PORTC_PIN4_gc = (0x44<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL3_PORTC_PIN5_gc = (0x45<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL3_PORTC_PIN6_gc = (0x46<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL3_PORTC_PIN7_gc = (0x47<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL3_PORTD_PIN0_gc = (0x48<<0), /* Port D Pin 0 */ + EVSYS_CHANNEL3_PORTD_PIN1_gc = (0x49<<0), /* Port D Pin 1 */ + EVSYS_CHANNEL3_PORTD_PIN2_gc = (0x4A<<0), /* Port D Pin 2 */ + EVSYS_CHANNEL3_PORTD_PIN3_gc = (0x4B<<0), /* Port D Pin 3 */ + EVSYS_CHANNEL3_PORTD_PIN4_gc = (0x4C<<0), /* Port D Pin 4 */ + EVSYS_CHANNEL3_PORTD_PIN5_gc = (0x4D<<0), /* Port D Pin 5 */ + EVSYS_CHANNEL3_PORTD_PIN6_gc = (0x4E<<0), /* Port D Pin 6 */ + EVSYS_CHANNEL3_PORTD_PIN7_gc = (0x4F<<0), /* Port D Pin 7 */ + EVSYS_CHANNEL3_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL3_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL3_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL3_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL3_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL3_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL3_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL3_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL3_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL3_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL3_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL3_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL3_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL3_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL3_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL3_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL3_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL3_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL3_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL3_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL3_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL3_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL3_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL3_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL3_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL3_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL3_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL3_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL3_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL3_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL3_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL3_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL3_t; + +/* Channel 4 generator select select */ +typedef enum EVSYS_CHANNEL4_enum +{ + EVSYS_CHANNEL4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL4_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL4_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL4_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL4_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL4_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL4_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL4_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL4_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL4_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL4_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL4_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL4_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL4_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL4_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL4_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL4_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL4_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL4_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL4_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL4_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL4_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL4_PORTE_PIN0_gc = (0x40<<0), /* Port E Pin 0 */ + EVSYS_CHANNEL4_PORTE_PIN1_gc = (0x41<<0), /* Port E Pin 1 */ + EVSYS_CHANNEL4_PORTE_PIN2_gc = (0x42<<0), /* Port E Pin 2 */ + EVSYS_CHANNEL4_PORTE_PIN3_gc = (0x43<<0), /* Port E Pin 3 */ + EVSYS_CHANNEL4_PORTE_PIN4_gc = (0x44<<0), /* Port E Pin 4 */ + EVSYS_CHANNEL4_PORTE_PIN5_gc = (0x45<<0), /* Port E Pin 5 */ + EVSYS_CHANNEL4_PORTE_PIN6_gc = (0x46<<0), /* Port E Pin 6 */ + EVSYS_CHANNEL4_PORTE_PIN7_gc = (0x47<<0), /* Port E Pin 7 */ + EVSYS_CHANNEL4_PORTF_PIN0_gc = (0x48<<0), /* Port F Pin 0 */ + EVSYS_CHANNEL4_PORTF_PIN1_gc = (0x49<<0), /* Port F Pin 1 */ + EVSYS_CHANNEL4_PORTF_PIN2_gc = (0x4A<<0), /* Port F Pin 2 */ + EVSYS_CHANNEL4_PORTF_PIN3_gc = (0x4B<<0), /* Port F Pin 3 */ + EVSYS_CHANNEL4_PORTF_PIN4_gc = (0x4C<<0), /* Port F Pin 4 */ + EVSYS_CHANNEL4_PORTF_PIN5_gc = (0x4D<<0), /* Port F Pin 5 */ + EVSYS_CHANNEL4_PORTF_PIN6_gc = (0x4E<<0), /* Port F Pin 6 */ + EVSYS_CHANNEL4_PORTF_PIN7_gc = (0x4F<<0), /* Port F Pin 7 */ + EVSYS_CHANNEL4_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL4_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL4_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL4_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL4_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL4_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL4_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL4_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL4_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL4_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL4_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL4_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL4_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL4_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL4_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL4_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL4_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL4_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL4_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL4_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL4_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL4_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL4_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL4_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL4_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL4_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL4_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL4_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL4_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL4_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL4_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL4_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL4_t; + +/* Channel 5 generator select select */ +typedef enum EVSYS_CHANNEL5_enum +{ + EVSYS_CHANNEL5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL5_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL5_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL5_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL5_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL5_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL5_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL5_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL5_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL5_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL5_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL5_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL5_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL5_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL5_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL5_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL5_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL5_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL5_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL5_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL5_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL5_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL5_PORTE_PIN0_gc = (0x40<<0), /* Port E Pin 0 */ + EVSYS_CHANNEL5_PORTE_PIN1_gc = (0x41<<0), /* Port E Pin 1 */ + EVSYS_CHANNEL5_PORTE_PIN2_gc = (0x42<<0), /* Port E Pin 2 */ + EVSYS_CHANNEL5_PORTE_PIN3_gc = (0x43<<0), /* Port E Pin 3 */ + EVSYS_CHANNEL5_PORTE_PIN4_gc = (0x44<<0), /* Port E Pin 4 */ + EVSYS_CHANNEL5_PORTE_PIN5_gc = (0x45<<0), /* Port E Pin 5 */ + EVSYS_CHANNEL5_PORTE_PIN6_gc = (0x46<<0), /* Port E Pin 6 */ + EVSYS_CHANNEL5_PORTA_PIN7_gc = (0x47<<0), /* Port E Pin 7 */ + EVSYS_CHANNEL5_PORTF_PIN0_gc = (0x48<<0), /* Port F Pin 0 */ + EVSYS_CHANNEL5_PORTF_PIN1_gc = (0x49<<0), /* Port F Pin 1 */ + EVSYS_CHANNEL5_PORTF_PIN2_gc = (0x4A<<0), /* Port F Pin 2 */ + EVSYS_CHANNEL5_PORTF_PIN3_gc = (0x4B<<0), /* Port F Pin 3 */ + EVSYS_CHANNEL5_PORTF_PIN4_gc = (0x4C<<0), /* Port F Pin 4 */ + EVSYS_CHANNEL5_PORTF_PIN5_gc = (0x4D<<0), /* Port F Pin 5 */ + EVSYS_CHANNEL5_PORTF_PIN6_gc = (0x4E<<0), /* Port F Pin 6 */ + EVSYS_CHANNEL5_PORTF_PIN7_gc = (0x4F<<0), /* Port F Pin 7 */ + EVSYS_CHANNEL5_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL5_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL5_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL5_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL5_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL5_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL5_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL5_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL5_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL5_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL5_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL5_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL5_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL5_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL5_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL5_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL5_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL5_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL5_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL5_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL5_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL5_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL5_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL5_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL5_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL5_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL5_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL5_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL5_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL5_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL5_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL5_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL5_t; + +/* Channel 6 generator select select */ +typedef enum EVSYS_CHANNEL6_enum +{ + EVSYS_CHANNEL6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL6_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL6_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL6_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL6_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL6_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL6_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL6_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL6_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL6_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL6_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL6_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL6_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL6_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL6_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL6_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL6_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL6_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL6_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL6_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL6_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL6_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL6_PORTG_PIN0_gc = (0x40<<0), /* Port G Pin 0 */ + EVSYS_CHANNEL6_PORTG_PIN1_gc = (0x41<<0), /* Port G Pin 1 */ + EVSYS_CHANNEL6_PORTG_PIN2_gc = (0x42<<0), /* Port G Pin 2 */ + EVSYS_CHANNEL6_PORTG_PIN3_gc = (0x43<<0), /* Port G Pin 3 */ + EVSYS_CHANNEL6_PORTG_PIN4_gc = (0x44<<0), /* Port G Pin 4 */ + EVSYS_CHANNEL6_PORTG_PIN5_gc = (0x45<<0), /* Port G Pin 5 */ + EVSYS_CHANNEL6_PORTG_PIN6_gc = (0x46<<0), /* Port G Pin 6 */ + EVSYS_CHANNEL6_PORTG_PIN7_gc = (0x47<<0), /* Port G Pin 7 */ + EVSYS_CHANNEL6_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL6_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL6_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL6_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL6_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL6_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL6_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL6_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL6_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL6_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL6_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL6_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL6_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL6_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL6_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL6_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL6_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL6_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL6_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL6_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL6_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL6_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL6_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL6_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL6_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL6_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL6_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL6_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL6_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL6_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL6_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL6_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL6_t; + +/* Channel 7 generator select select */ +typedef enum EVSYS_CHANNEL7_enum +{ + EVSYS_CHANNEL7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL7_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL7_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL7_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL7_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL7_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL7_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL7_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL7_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL7_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL7_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL7_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL7_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL7_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL7_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL7_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL7_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL7_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL7_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL7_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL7_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL7_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL7_PORTG_PIN0_gc = (0x40<<0), /* Port G Pin 0 */ + EVSYS_CHANNEL7_PORTG_PIN1_gc = (0x41<<0), /* Port G Pin 1 */ + EVSYS_CHANNEL7_PORTG_PIN2_gc = (0x42<<0), /* Port G Pin 2 */ + EVSYS_CHANNEL7_PORTG_PIN3_gc = (0x43<<0), /* Port G Pin 3 */ + EVSYS_CHANNEL7_PORTG_PIN4_gc = (0x44<<0), /* Port G Pin 4 */ + EVSYS_CHANNEL7_PORTG_PIN5_gc = (0x45<<0), /* Port G Pin 5 */ + EVSYS_CHANNEL7_PORTG_PIN6_gc = (0x46<<0), /* Port G Pin 6 */ + EVSYS_CHANNEL7_PORTG_PIN7_gc = (0x47<<0), /* Port G Pin 7 */ + EVSYS_CHANNEL7_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL7_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL7_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL7_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL7_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL7_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL7_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL7_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL7_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL7_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL7_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL7_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL7_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL7_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL7_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL7_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL7_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL7_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL7_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL7_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL7_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL7_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL7_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL7_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL7_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL7_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL7_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL7_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL7_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL7_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL7_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL7_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL7_t; + +/* Channel 8 generator select select */ +typedef enum EVSYS_CHANNEL8_enum +{ + EVSYS_CHANNEL8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL8_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL8_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL8_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL8_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL8_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL8_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL8_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL8_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL8_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL8_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL8_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL8_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL8_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL8_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL8_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL8_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL8_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL8_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL8_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL8_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL8_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL8_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL8_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL8_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL8_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL8_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL8_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL8_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL8_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL8_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL8_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL8_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL8_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL8_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL8_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL8_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL8_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL8_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL8_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL8_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL8_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL8_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL8_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL8_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL8_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL8_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL8_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL8_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL8_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL8_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL8_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL8_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL8_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL8_t; + +/* Channel 9 generator select select */ +typedef enum EVSYS_CHANNEL9_enum +{ + EVSYS_CHANNEL9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL9_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL9_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL9_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL9_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL9_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL9_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL9_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL9_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL9_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL9_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL9_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL9_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL9_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL9_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL9_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL9_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL9_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL9_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL9_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL9_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL9_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL9_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL9_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL9_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL9_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL9_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL9_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL9_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL9_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL9_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL9_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL9_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL9_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL9_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL9_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL9_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL9_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL9_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL9_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL9_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL9_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL9_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL9_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL9_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL9_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL9_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL9_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL9_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL9_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL9_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL9_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL9_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL9_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL9_t; + +/* Software event on channel select select */ +typedef enum EVSYS_SWEVENTA_enum +{ + EVSYS_SWEVENTA_CH0_gc = (0x01<<0), /* Software event on channel 0 */ + EVSYS_SWEVENTA_CH1_gc = (0x02<<0), /* Software event on channel 1 */ + EVSYS_SWEVENTA_CH2_gc = (0x04<<0), /* Software event on channel 2 */ + EVSYS_SWEVENTA_CH3_gc = (0x08<<0), /* Software event on channel 3 */ + EVSYS_SWEVENTA_CH4_gc = (0x10<<0), /* Software event on channel 4 */ + EVSYS_SWEVENTA_CH5_gc = (0x20<<0), /* Software event on channel 5 */ + EVSYS_SWEVENTA_CH6_gc = (0x40<<0), /* Software event on channel 6 */ + EVSYS_SWEVENTA_CH7_gc = (0x80<<0), /* Software event on channel 7 */ +} EVSYS_SWEVENTA_t; + +/* Software event on channel select select */ +typedef enum EVSYS_SWEVENTB_enum +{ + EVSYS_SWEVENTB_CH8_gc = (0x00<<0), /* Software event on channel 8 */ + EVSYS_SWEVENTB_CH9_gc = (0x01<<0), /* Software event on channel 9 */ +} EVSYS_SWEVENTB_t; + +/* User channel select select */ +typedef enum EVSYS_USER_enum +{ + EVSYS_USER_OFF_gc = (0x00<<0), /* Off */ + EVSYS_USER_CHANNEL0_gc = (0x01<<0), /* Connect user to event channel 0 */ + EVSYS_USER_CHANNEL1_gc = (0x02<<0), /* Connect user to event channel 1 */ + EVSYS_USER_CHANNEL2_gc = (0x03<<0), /* Connect user to event channel 2 */ + EVSYS_USER_CHANNEL3_gc = (0x04<<0), /* Connect user to event channel 3 */ + EVSYS_USER_CHANNEL4_gc = (0x05<<0), /* Connect user to event channel 4 */ + EVSYS_USER_CHANNEL5_gc = (0x06<<0), /* Connect user to event channel 5 */ + EVSYS_USER_CHANNEL6_gc = (0x07<<0), /* Connect user to event channel 6 */ + EVSYS_USER_CHANNEL7_gc = (0x08<<0), /* Connect user to event channel 7 */ + EVSYS_USER_CHANNEL8_gc = (0x09<<0), /* Connect user to event channel 8 */ + EVSYS_USER_CHANNEL9_gc = (0x0A<<0), /* Connect user to event channel 9 */ +} EVSYS_USER_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t CODESIZE; /* Code Section Size */ + register8_t BOOTSIZE; /* Boot Section Size */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DISABLE_gc = (0x00<<2), /* BOD disabled */ + ACTIVE_ENABLE_gc = (0x01<<2), /* BOD enabled in continiuous mode */ + ACTIVE_SAMPLE_gc = (0x02<<2), /* BOD enabled in sampled mode */ + ACTIVE_ENABLEWAIT_gc = (0x03<<2), /* BOD enabled in continiuous mode. Execution is halted at wake-up until BOD is running. */ +} ACTIVE_t; + +/* Frequency Select select */ +typedef enum CLKSEL_enum +{ + CLKSEL_OSCHF_gc = (0x00<<0), /* 1-32MHz internal oscillator */ + CLKSEL_OSC32K_gc = (0x01<<0), /* 32.768kHz internal oscillator */ +} CLKSEL_t; + +/* CRC Select select */ +typedef enum CRCSEL_enum +{ + CRCSEL_CRC16_gc = (0x00<<5), /* Enable CRC16 */ + CRCSEL_CRC32_gc = (0x01<<5), /* Enable CRC32 */ +} CRCSEL_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* CRC of full Flash (boot, application code and application data) */ + CRCSRC_BOOT_gc = (0x01<<6), /* CRC of boot section */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* CRC of application code and boot sections */ + CRCSRC_NOCRC_gc = (0x03<<6), /* No CRC */ +} CRCSRC_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.9V */ + LVL_BODLEVEL1_gc = (0x01<<5), /* 2.45V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.7V */ + LVL_BODLEVEL3_gc = (0x03<<5), /* 2.85V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.0s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.0s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_128Hz_gc = (0x00<<4), /* Sample frequency is 128 Hz */ + SAMPFREQ_32Hz_gc = (0x01<<4), /* Sample frequency is 32 Hz */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DISABLE_gc = (0x00<<0), /* BOD disabled */ + SLEEP_ENABLE_gc = (0x01<<0), /* BOD enabled in continiuous mode */ + SLEEP_SAMPLE_gc = (0x02<<0), /* BOD enabled in sampled mode */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.0s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.0s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +GPR - General Purpose Registers +-------------------------------------------------------------------------- +*/ + +/* General Purpose Registers */ +typedef struct GPR_struct +{ + register8_t GPR0; /* General Purpose Register 0 */ + register8_t GPR1; /* General Purpose Register 1 */ + register8_t GPR2; /* General Purpose Register 2 */ + register8_t GPR3; /* General Purpose Register 3 */ +} GPR_t; + + +/* +-------------------------------------------------------------------------- +LOCK - Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lockbits */ +typedef struct LOCK_struct +{ + _DWORDREGISTER(KEY); /* Lock Key Bits */ +} LOCK_t; + +/* Lock Key select */ +typedef enum LOCK_KEY_enum +{ + LOCK_KEY_NOLOCK_gc = (0x5CC5C55C<<0), /* No locks */ + LOCK_KEY_RWLOCK_gc = (0xA33A3AA3<<0), /* Read and write lock */ +} LOCK_KEY_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _DWORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[4]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_NOOP_gc = (0x01<<0), /* No Operation */ + NVMCTRL_CMD_FLWR_gc = (0x02<<0), /* Flash Write */ + NVMCTRL_CMD_FLPER_gc = (0x08<<0), /* Flash Page Erase */ + NVMCTRL_CMD_FLMPER2_gc = (0x09<<0), /* Flash Multi-Page Erase 2 pages */ + NVMCTRL_CMD_FLMPER4_gc = (0x0A<<0), /* Flash Multi-Page Erase 4 pages */ + NVMCTRL_CMD_FLMPER8_gc = (0x0B<<0), /* Flash Multi-Page Erase 8 pages */ + NVMCTRL_CMD_FLMPER16_gc = (0x0C<<0), /* Flash Multi-Page Erase 16 pages */ + NVMCTRL_CMD_FLMPER32_gc = (0x0D<<0), /* Flash Multi-Page Erase 32 pages */ + NVMCTRL_CMD_EEWR_gc = (0x12<<0), /* EEPROM Write */ + NVMCTRL_CMD_EEERWR_gc = (0x13<<0), /* EEPROM Erase and Write */ + NVMCTRL_CMD_EEBER_gc = (0x18<<0), /* EEPROM Byte Erase */ + NVMCTRL_CMD_EEMBER2_gc = (0x19<<0), /* EEPROM Multi-Byte Erase 2 bytes */ + NVMCTRL_CMD_EEMBER4_gc = (0x1A<<0), /* EEPROM Multi-Byte Erase 4 bytes */ + NVMCTRL_CMD_EEMBER8_gc = (0x1B<<0), /* EEPROM Multi-Byte Erase 8 bytes */ + NVMCTRL_CMD_EEMBER16_gc = (0x1C<<0), /* EEPROM Multi-Byte Erase 16 bytes */ + NVMCTRL_CMD_EEMBER32_gc = (0x1D<<0), /* EEPROM Multi-Byte Erase 32 bytes */ + NVMCTRL_CMD_CHER_gc = (0x20<<0), /* Chip Erase Command */ + NVMCTRL_CMD_EECHER_gc = (0x30<<0), /* EEPROM Erase Command */ +} NVMCTRL_CMD_t; + +/* Write error select */ +typedef enum NVMCTRL_ERROR_enum +{ + NVMCTRL_ERROR_NOERROR_gc = (0x00<<4), /* No Error */ + NVMCTRL_ERROR_ILLEGALCMD_gc = (0x01<<4), /* Write command not selected */ + NVMCTRL_ERROR_ILLEGALSADDR_gc = (0x02<<4), /* Write to section not allowed */ + NVMCTRL_ERROR_DOUBLESELECT_gc = (0x03<<4), /* Selecting new write command while write command already seleted */ + NVMCTRL_ERROR_ONGOINGPROG_gc = (0x04<<4), /* Starting a new programming operation before previous is completed */ +} NVMCTRL_ERROR_t; + +/* Flash Mapping in Data space select */ +typedef enum NVMCTRL_FLMAP_enum +{ + NVMCTRL_FLMAP_SECTION0_gc = (0x00<<4), /* Flash section 0, 0 - 32KB */ + NVMCTRL_FLMAP_SECTION1_gc = (0x01<<4), /* Flash section 1, 32 - 64KB */ + NVMCTRL_FLMAP_SECTION2_gc = (0x02<<4), /* Flash section 2, 64 - 96KB */ + NVMCTRL_FLMAP_SECTION3_gc = (0x03<<4), /* Flash section 3, 96 - 128KB */ +} NVMCTRL_FLMAP_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t PORTCTRL; /* Port Control */ + register8_t PINCONFIG; /* Pin Control Config */ + register8_t PINCTRLUPD; /* Pin Control Update */ + register8_t PINCTRLSET; /* Pin Control Set */ + register8_t PINCTRLCLR; /* Pin Control Clear */ + register8_t reserved_1[1]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t EVSYSROUTEA; /* EVSYS route A */ + register8_t CCLROUTEA; /* CCL route A */ + register8_t USARTROUTEA; /* USART route A */ + register8_t USARTROUTEB; /* USART route B */ + register8_t SPIROUTEA; /* SPI route A */ + register8_t TWIROUTEA; /* TWI route A */ + register8_t TCAROUTEA; /* TCA route A */ + register8_t TCBROUTEA; /* TCB route A */ + register8_t TCDROUTEA; /* TCD route A */ + register8_t ACROUTEA; /* AC route A */ + register8_t ZCDROUTEA; /* ZCD route A */ + register8_t reserved_1[5]; +} PORTMUX_t; + +/* Analog Comparator 0 Output select */ +typedef enum PORTMUX_AC0_enum +{ + PORTMUX_AC0_DEFAULT_gc = (0x00<<0), /* OUT on PA7 */ + PORTMUX_AC0_ALT1_gc = (0x01<<0), /* OUT on PC6 */ +} PORTMUX_AC0_t; + +/* Analog Comparator 1 Output select */ +typedef enum PORTMUX_AC1_enum +{ + PORTMUX_AC1_DEFAULT_gc = (0x00<<1), /* OUT on PA7 */ + PORTMUX_AC1_ALT1_gc = (0x01<<1), /* OUT on PC6 */ +} PORTMUX_AC1_t; + +/* Analog Comparator 2 Output select */ +typedef enum PORTMUX_AC2_enum +{ + PORTMUX_AC2_DEFAULT_gc = (0x00<<2), /* OUT on PA7 */ + PORTMUX_AC2_ALT1_gc = (0x01<<2), /* OUT on PC6 */ +} PORTMUX_AC2_t; + +/* Event Output A select */ +typedef enum PORTMUX_EVOUTA_enum +{ + PORTMUX_EVOUTA_DEFAULT_gc = (0x00<<0), /* EVOUT on PA2 */ + PORTMUX_EVOUTA_ALT1_gc = (0x01<<0), /* EVOUT on PA7 */ +} PORTMUX_EVOUTA_t; + +/* Event Output B select */ +typedef enum PORTMUX_EVOUTB_enum +{ + PORTMUX_EVOUTB_DEFAULT_gc = (0x00<<1), /* EVOUT on PB2 */ + PORTMUX_EVOUTB_ALT1_gc = (0x01<<1), /* EVOUT on PB7 */ +} PORTMUX_EVOUTB_t; + +/* Event Output C select */ +typedef enum PORTMUX_EVOUTC_enum +{ + PORTMUX_EVOUTC_DEFAULT_gc = (0x00<<2), /* EVOUT on PC2 */ + PORTMUX_EVOUTC_ALT1_gc = (0x01<<2), /* EVOUT on PC7 */ +} PORTMUX_EVOUTC_t; + +/* Event Output D select */ +typedef enum PORTMUX_EVOUTD_enum +{ + PORTMUX_EVOUTD_DEFAULT_gc = (0x00<<3), /* EVOUT on PD2 */ + PORTMUX_EVOUTD_ALT1_gc = (0x01<<3), /* EVOUT on PD7 */ +} PORTMUX_EVOUTD_t; + +/* Event Output E select */ +typedef enum PORTMUX_EVOUTE_enum +{ + PORTMUX_EVOUTE_DEFAULT_gc = (0x00<<4), /* EVOUT on PE2 */ + PORTMUX_EVOUTE_ALT1_gc = (0x01<<4), /* EVOUT on PE7 */ +} PORTMUX_EVOUTE_t; + +/* Event Output F select */ +typedef enum PORTMUX_EVOUTF_enum +{ + PORTMUX_EVOUTF_DEFAULT_gc = (0x00<<5), /* EVOUT on PF2 */ +} PORTMUX_EVOUTF_t; + +/* Event Output G select */ +typedef enum PORTMUX_EVOUTG_enum +{ + PORTMUX_EVOUTG_DEFAULT_gc = (0x00<<6), /* EVOUT on PG2 */ + PORTMUX_EVOUTG_ALT1_gc = (0x01<<6), /* EVOUT on PG7 */ +} PORTMUX_EVOUTG_t; + +/* CCL Look-Up Table 0 Signals select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<0), /* Out: PA3 In: PA0, PA1, PA2 */ + PORTMUX_LUT0_ALT1_gc = (0x01<<0), /* Out: PA6 In: PA0, PA1, PA2 */ +} PORTMUX_LUT0_t; + +/* CCL Look-Up Table 1 Signals select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<1), /* Out: PC3 In: PC0, PC1, PC2 */ + PORTMUX_LUT1_ALT1_gc = (0x01<<1), /* Out: PC6 In: PC0, PC1, PC2 */ +} PORTMUX_LUT1_t; + +/* CCL Look-Up Table 2 Signals select */ +typedef enum PORTMUX_LUT2_enum +{ + PORTMUX_LUT2_DEFAULT_gc = (0x00<<2), /* Out: PD3 In: PD0, PD1, PD2 */ + PORTMUX_LUT2_ALT1_gc = (0x01<<2), /* Out: PD6 In: PD0, PD1, PD2 */ +} PORTMUX_LUT2_t; + +/* CCL Look-Up Table 3 Signals select */ +typedef enum PORTMUX_LUT3_enum +{ + PORTMUX_LUT3_DEFAULT_gc = (0x00<<3), /* Out: PF3 In: PF0, PF1, PF2 */ +} PORTMUX_LUT3_t; + +/* CCL Look-Up Table 4 Signals select */ +typedef enum PORTMUX_LUT4_enum +{ + PORTMUX_LUT4_DEFAULT_gc = (0x00<<4), /* Out: PB3 In: PB0, PB1, PB2 */ + PORTMUX_LUT4_ALT1_gc = (0x01<<4), /* Out: PB6 In: PB0, PB1, PB2 */ +} PORTMUX_LUT4_t; + +/* CCL Look-Up Table 5 Signals select */ +typedef enum PORTMUX_LUT5_enum +{ + PORTMUX_LUT5_DEFAULT_gc = (0x00<<5), /* Out: PG3 In: PG0, PG1, PG2 */ + PORTMUX_LUT5_ALT1_gc = (0x01<<5), /* Out: PG6 In: PG0, PG1, PG2 */ +} PORTMUX_LUT5_t; + +/* SPI0 Signals select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<0), /* PA4, PA5, PA6, PA7 */ + PORTMUX_SPI0_ALT1_gc = (0x01<<0), /* PE0, PE1, PE2, PE3 */ + PORTMUX_SPI0_ALT2_gc = (0x02<<0), /* PG4, PG5, PG6, PG7 */ + PORTMUX_SPI0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_SPI0_t; + +/* SPI1 Signals select */ +typedef enum PORTMUX_SPI1_enum +{ + PORTMUX_SPI1_DEFAULT_gc = (0x00<<2), /* PC0, PC1, PC2, PC3 */ + PORTMUX_SPI1_ALT1_gc = (0x01<<2), /* PC4, PC5, PC6, PC7 */ + PORTMUX_SPI1_ALT2_gc = (0x02<<2), /* PB4, PB5, PB6, PB7 */ + PORTMUX_SPI1_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_SPI1_t; + +/* TCA0 Signals select */ +typedef enum PORTMUX_TCA0_enum +{ + PORTMUX_TCA0_PORTA_gc = (0x00<<0), /* PA0, PA1, PA2, PA3, PA4, PA5 */ + PORTMUX_TCA0_PORTB_gc = (0x01<<0), /* PB0, PB1, PB2, PB3, PB4, PB5 */ + PORTMUX_TCA0_PORTC_gc = (0x02<<0), /* PC0, PC1, PC2, PC3, PC4, PC5 */ + PORTMUX_TCA0_PORTD_gc = (0x03<<0), /* PD0, PD1, PD2, PD3, PD4, PD5 */ + PORTMUX_TCA0_PORTE_gc = (0x04<<0), /* PE0, PE1, PE2, PE3, PE4, PE5 */ + PORTMUX_TCA0_PORTF_gc = (0x05<<0), /* PF0, PF1, PF2, PF3, PF4, PF5 */ + PORTMUX_TCA0_PORTG_gc = (0x06<<0), /* PG0, PG1, PG2, PG3, PG4, PG5 */ +} PORTMUX_TCA0_t; + +/* TCB0 Output select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* WO on PA2 */ + PORTMUX_TCB0_ALT1_gc = (0x01<<0), /* WO on PF4 */ +} PORTMUX_TCB0_t; + +/* TCB1 Output select */ +typedef enum PORTMUX_TCB1_enum +{ + PORTMUX_TCB1_DEFAULT_gc = (0x00<<1), /* WO on PA3 */ + PORTMUX_TCB1_ALT1_gc = (0x01<<1), /* WO on PF5 */ +} PORTMUX_TCB1_t; + +/* TCB2 Output select */ +typedef enum PORTMUX_TCB2_enum +{ + PORTMUX_TCB2_DEFAULT_gc = (0x00<<2), /* WO on PC0 */ + PORTMUX_TCB2_ALT1_gc = (0x01<<2), /* WO on PB4 */ +} PORTMUX_TCB2_t; + +/* TCD0 Signals select */ +typedef enum PORTMUX_TCD0_enum +{ + PORTMUX_TCD0_DEFAULT_gc = (0x00<<0), /* PA4, PA5, PA6, PA7 */ + PORTMUX_TCD0_ALT1_gc = (0x01<<0), /* PB4, PB5, PB6, PB7 */ + PORTMUX_TCD0_ALT2_gc = (0x02<<0), /* PF0, PF1, PF2, PF3 */ + PORTMUX_TCD0_ALT3_gc = (0x03<<0), /* PG4, PG5, PG6, PG7 */ +} PORTMUX_TCD0_t; + +/* TWI0 Signals select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<0), /* PA2, PA3, PC2, PC3 */ + PORTMUX_TWI0_ALT1_gc = (0x01<<0), /* PA2, PA3, PC6, PC7 */ + PORTMUX_TWI0_ALT2_gc = (0x02<<0), /* PC2, PC3, PC6, PC7 */ +} PORTMUX_TWI0_t; + +/* USART0 Signals select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* PA0, PA1, PA2, PA3 */ + PORTMUX_USART0_ALT1_gc = (0x01<<0), /* PA4, PA5, PA6, PA7 */ + PORTMUX_USART0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_USART0_t; + +/* USART1 Signals select */ +typedef enum PORTMUX_USART1_enum +{ + PORTMUX_USART1_DEFAULT_gc = (0x00<<2), /* PC0, PC1, PC2, PC3 */ + PORTMUX_USART1_ALT1_gc = (0x01<<2), /* PC4, PC5, PC6, PC7 */ + PORTMUX_USART1_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_USART1_t; + +/* USART2 Signals select */ +typedef enum PORTMUX_USART2_enum +{ + PORTMUX_USART2_DEFAULT_gc = (0x00<<4), /* PF0, PF1, PF2, PF3 */ + PORTMUX_USART2_ALT1_gc = (0x01<<4), /* PF4, PF5 */ + PORTMUX_USART2_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_USART2_t; + +/* Zero Cross Detector 0 Output select */ +typedef enum PORTMUX_ZCD0_enum +{ + PORTMUX_ZCD0_DEFAULT_gc = (0x00<<0), /* OUT on PA7 */ + PORTMUX_ZCD0_ALT1_gc = (0x01<<0), /* OUT on PC7 */ +} PORTMUX_ZCD0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t CALIB; /* Calibration */ + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_1[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_2[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_3[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_OSC32K_gc = (0x00<<0), /* Internal 32.768 kHz oscillator */ + RTC_CLKSEL_OSC1K_gc = (0x01<<0), /* Internal 1.024 kHz oscillator */ + RTC_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768 kHz crystal oscillator */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t reserved_1[1]; + _WORDREGISTER(TEMPSENSE0); /* Temperature Calibration 0 */ + _WORDREGISTER(TEMPSENSE1); /* Temperature Calibration 1 */ + register8_t reserved_2[8]; + register8_t SERNUM0; /* LOTNUM0 */ + register8_t SERNUM1; /* LOTNUM1 */ + register8_t SERNUM2; /* LOTNUM2 */ + register8_t SERNUM3; /* LOTNUM3 */ + register8_t SERNUM4; /* LOTNUM4 */ + register8_t SERNUM5; /* LOTNUM5 */ + register8_t SERNUM6; /* RANDOM */ + register8_t SERNUM7; /* SCRIBE */ + register8_t SERNUM8; /* XPOS0 */ + register8_t SERNUM9; /* XPOS1 */ + register8_t SERNUM10; /* YPOS0 */ + register8_t SERNUM11; /* YPOS1 */ + register8_t SERNUM12; /* RES0 */ + register8_t SERNUM13; /* RES1 */ + register8_t SERNUM14; /* RES2 */ + register8_t SERNUM15; /* RES3 */ + register8_t reserved_3[32]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t VREGCTRL; /* Control B */ +} SLPCTRL_t; + +/* Performance Mode select */ +typedef enum SLPCTRL_PMODE_enum +{ + SLPCTRL_PMODE_AUTO_gc = (0x00<<0), /* */ + SLPCTRL_PMODE_FULL_gc = (0x01<<0), /* */ +} SLPCTRL_PMODE_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t reserved_2[22]; + register8_t OCDMCTRL; /* OCD Message Control */ + register8_t OCDMSTATUS; /* OCD Message Status */ + register8_t reserved_3[6]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action A select */ +typedef enum TCA_SINGLE_EVACTA_enum +{ + TCA_SINGLE_EVACTA_CNT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACTA_CNT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACTA_CNT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACTA_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACTA_t; + +/* Event Action B select */ +typedef enum TCA_SINGLE_EVACTB_enum +{ + TCA_SINGLE_EVACTB_UPDOWN_gc = (0x03<<5), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ + TCA_SINGLE_EVACTB_RESTART_POSEDGE_gc = (0x04<<5), /* Restart counter at positive edge event */ + TCA_SINGLE_EVACTB_RESTART_ANYEDGE_gc = (0x05<<5), /* Restart counter on any edge event */ + TCA_SINGLE_EVACTB_RESTART_HIGHLVL_gc = (0x06<<5), /* Restart counter while event line is 1. */ +} TCA_SINGLE_EVACTB_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* Command Enable select */ +typedef enum TCA_SPLIT_CMDEN_enum +{ + TCA_SPLIT_CMDEN_NONE_gc = (0x00<<0), /* None */ + TCA_SPLIT_CMDEN_BOTH_gc = (0x03<<0), /* Both low byte and high byte counter */ +} TCA_SPLIT_CMDEN_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_DIV1_gc = (0x00<<1), /* CLK_PEP */ + TCB_CLKSEL_DIV2_gc = (0x01<<1), /* CLK_PER/2 */ + TCB_CLKSEL_TCA0_gc = (0x02<<1), /* Use CLK_TCA from TCA0 */ + TCB_CLKSEL_EVENT_gc = (0x07<<1), /* Count on event edge */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_OSCHF_gc = (0x00<<5), /* Internal High-Frequency Oscillator */ + TCD_CLKSEL_PLL_gc = (0x01<<5), /* PLL */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External Clock */ + TCD_CLKSEL_CLKPER_gc = (0x03<<5), /* Peripheral Clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Synchronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selected clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selected clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selected clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selected clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t DUALCTRL; /* Dual Control */ + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baud Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_1[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Input Voltage Transition Level select */ +typedef enum TWI_INPUTLVL_enum +{ + TWI_INPUTLVL_I2C_gc = (0x00<<6), /* I2C input voltage transition level */ + TWI_INPUTLVL_SMBUS_gc = (0x01<<6), /* SMBus 3.0 input voltage transition level */ +} TWI_INPUTLVL_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t CTRLD; /* Control D */ + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_1[1]; +} USART_t; + +/* Auto Baud Window select */ +typedef enum USART_ABW_enum +{ + USART_ABW_WDW0_gc = (0x00<<6), /* 18% tolerance */ + USART_ABW_WDW1_gc = (0x01<<6), /* 15% tolerance */ + USART_ABW_WDW2_gc = (0x02<<6), /* 21% tolerance */ + USART_ABW_WDW3_gc = (0x03<<6), /* 25% tolerance */ +} USART_ABW_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t ADC0REF; /* ADC0 Reference */ + register8_t reserved_1[1]; + register8_t DAC0REF; /* DAC0 Reference */ + register8_t reserved_2[1]; + register8_t ACREF; /* AC Reference */ +} VREF_t; + +/* Reference select select */ +typedef enum VREF_REFSEL_enum +{ + VREF_REFSEL_1V024_gc = (0x00<<0), /* Internal 1.024V reference */ + VREF_REFSEL_2V048_gc = (0x01<<0), /* Internal 2.048V reference */ + VREF_REFSEL_4V096_gc = (0x02<<0), /* Internal 4.096V reference */ + VREF_REFSEL_2V500_gc = (0x03<<0), /* Internal 2.500V reference */ + VREF_REFSEL_VDD_gc = (0x05<<0), /* VDD as reference */ + VREF_REFSEL_VREFA_gc = (0x06<<0), /* External referance on VREFA pin */ +} VREF_REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; + +/* +-------------------------------------------------------------------------- +ZCD - Zero Cross Detect +-------------------------------------------------------------------------- +*/ + +/* Zero Cross Detect */ +typedef struct ZCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ + register8_t reserved_2[4]; +} ZCD_t; + +/* Interrupt Mode select */ +typedef enum ZCD_INTMODE_enum +{ + ZCD_INTMODE_NONE_gc = (0x00<<0), /* No interrupt */ + ZCD_INTMODE_RISING_gc = (0x01<<0), /* Interrupt on rising input signal */ + ZCD_INTMODE_FALLING_gc = (0x02<<0), /* Interrupt on falling input signal */ + ZCD_INTMODE_BOTH_gc = (0x03<<0), /* Interrupt on both rising and falling input signal */ +} ZCD_INTMODE_t; + +/* ZCD State select */ +typedef enum ZCD_STATE_enum +{ + ZCD_STATE_LOW_gc = (0x00<<4), /* Output is 0 */ + ZCD_STATE_HIGH_gc = (0x01<<4), /* Output is 1 */ +} ZCD_STATE_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define VPORTD (*(VPORT_t *) 0x000C) /* Virtual Ports */ +#define VPORTE (*(VPORT_t *) 0x0010) /* Virtual Ports */ +#define VPORTF (*(VPORT_t *) 0x0014) /* Virtual Ports */ +#define VPORTG (*(VPORT_t *) 0x0018) /* Virtual Ports */ +#define GPR (*(GPR_t *) 0x001C) /* General Purpose Registers */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define EVSYS (*(EVSYS_t *) 0x0200) /* Event System */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0460) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0480) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x04A0) /* I/O Ports */ +#define PORTG (*(PORT_t *) 0x04C0) /* I/O Ports */ +#define PORTMUX (*(PORTMUX_t *) 0x05E0) /* Port Multiplexer */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define AC1 (*(AC_t *) 0x0688) /* Analog Comparator */ +#define AC2 (*(AC_t *) 0x0690) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x06A0) /* Digital to Analog Converter */ +#define ZCD0 (*(ZCD_t *) 0x06C0) /* Zero Cross Detect */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1 (*(USART_t *) 0x0820) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2 (*(USART_t *) 0x0840) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0900) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0940) /* Serial Peripheral Interface */ +#define SPI1 (*(SPI_t *) 0x0960) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0B00) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0B10) /* 16-bit Timer Type B */ +#define TCB2 (*(TCB_t *) 0x0B20) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0B80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define LOCK (*(LOCK_t *) 0x1040) /* Lockbits */ +#define FUSE (*(FUSE_t *) 0x1050) /* Fuses */ +#define USERROW (*(USERROW_t *) 0x1080) /* User Row */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* VPORT (VPORTD) - Virtual Ports */ +#define VPORTD_DIR _SFR_MEM8(0x000C) +#define VPORTD_OUT _SFR_MEM8(0x000D) +#define VPORTD_IN _SFR_MEM8(0x000E) +#define VPORTD_INTFLAGS _SFR_MEM8(0x000F) + + +/* VPORT (VPORTE) - Virtual Ports */ +#define VPORTE_DIR _SFR_MEM8(0x0010) +#define VPORTE_OUT _SFR_MEM8(0x0011) +#define VPORTE_IN _SFR_MEM8(0x0012) +#define VPORTE_INTFLAGS _SFR_MEM8(0x0013) + + +/* VPORT (VPORTF) - Virtual Ports */ +#define VPORTF_DIR _SFR_MEM8(0x0014) +#define VPORTF_OUT _SFR_MEM8(0x0015) +#define VPORTF_IN _SFR_MEM8(0x0016) +#define VPORTF_INTFLAGS _SFR_MEM8(0x0017) + + +/* VPORT (VPORTG) - Virtual Ports */ +#define VPORTG_DIR _SFR_MEM8(0x0018) +#define VPORTG_OUT _SFR_MEM8(0x0019) +#define VPORTG_IN _SFR_MEM8(0x001A) +#define VPORTG_INTFLAGS _SFR_MEM8(0x001B) + + +/* GPR - General Purpose Registers */ +#define GPR_GPR0 _SFR_MEM8(0x001C) +#define GPR_GPR1 _SFR_MEM8(0x001D) +#define GPR_GPR2 _SFR_MEM8(0x001E) +#define GPR_GPR3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) +#define SLPCTRL_VREGCTRL _SFR_MEM8(0x0051) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSCHFCTRLA _SFR_MEM8(0x0068) +#define CLKCTRL_OSCHFTUNE _SFR_MEM8(0x0069) +#define CLKCTRL_PLLCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_ADC0REF _SFR_MEM8(0x00A0) +#define VREF_DAC0REF _SFR_MEM8(0x00A2) +#define VREF_ACREF _SFR_MEM8(0x00A4) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CALIB _SFR_MEM8(0x0146) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_SEQCTRL1 _SFR_MEM8(0x01C2) +#define CCL_INTCTRL0 _SFR_MEM8(0x01C5) +#define CCL_INTFLAGS _SFR_MEM8(0x01C7) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C8) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C9) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01CA) +#define CCL_TRUTH0 _SFR_MEM8(0x01CB) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01CC) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CD) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CE) +#define CCL_TRUTH1 _SFR_MEM8(0x01CF) +#define CCL_LUT2CTRLA _SFR_MEM8(0x01D0) +#define CCL_LUT2CTRLB _SFR_MEM8(0x01D1) +#define CCL_LUT2CTRLC _SFR_MEM8(0x01D2) +#define CCL_TRUTH2 _SFR_MEM8(0x01D3) +#define CCL_LUT3CTRLA _SFR_MEM8(0x01D4) +#define CCL_LUT3CTRLB _SFR_MEM8(0x01D5) +#define CCL_LUT3CTRLC _SFR_MEM8(0x01D6) +#define CCL_TRUTH3 _SFR_MEM8(0x01D7) + + +/* EVSYS - Event System */ +#define EVSYS_SWEVENTA _SFR_MEM8(0x0200) +#define EVSYS_SWEVENTB _SFR_MEM8(0x0201) +#define EVSYS_CHANNEL0 _SFR_MEM8(0x0210) +#define EVSYS_CHANNEL1 _SFR_MEM8(0x0211) +#define EVSYS_CHANNEL2 _SFR_MEM8(0x0212) +#define EVSYS_CHANNEL3 _SFR_MEM8(0x0213) +#define EVSYS_CHANNEL4 _SFR_MEM8(0x0214) +#define EVSYS_CHANNEL5 _SFR_MEM8(0x0215) +#define EVSYS_CHANNEL6 _SFR_MEM8(0x0216) +#define EVSYS_CHANNEL7 _SFR_MEM8(0x0217) +#define EVSYS_CHANNEL8 _SFR_MEM8(0x0218) +#define EVSYS_CHANNEL9 _SFR_MEM8(0x0219) +#define EVSYS_USERCCLLUT0A _SFR_MEM8(0x0220) +#define EVSYS_USERCCLLUT0B _SFR_MEM8(0x0221) +#define EVSYS_USERCCLLUT1A _SFR_MEM8(0x0222) +#define EVSYS_USERCCLLUT1B _SFR_MEM8(0x0223) +#define EVSYS_USERCCLLUT2A _SFR_MEM8(0x0224) +#define EVSYS_USERCCLLUT2B _SFR_MEM8(0x0225) +#define EVSYS_USERCCLLUT3A _SFR_MEM8(0x0226) +#define EVSYS_USERCCLLUT3B _SFR_MEM8(0x0227) +#define EVSYS_USERCCLLUT4A _SFR_MEM8(0x0228) +#define EVSYS_USERCCLLUT4B _SFR_MEM8(0x0229) +#define EVSYS_USERCCLLUT5A _SFR_MEM8(0x022A) +#define EVSYS_USERCCLLUT5B _SFR_MEM8(0x022B) +#define EVSYS_USERADC0START _SFR_MEM8(0x022C) +#define EVSYS_USERPTCSTART _SFR_MEM8(0x022D) +#define EVSYS_USEREVSYSEVOUTA _SFR_MEM8(0x022E) +#define EVSYS_USEREVSYSEVOUTB _SFR_MEM8(0x022F) +#define EVSYS_USEREVSYSEVOUTC _SFR_MEM8(0x0230) +#define EVSYS_USEREVSYSEVOUTD _SFR_MEM8(0x0231) +#define EVSYS_USEREVSYSEVOUTE _SFR_MEM8(0x0232) +#define EVSYS_USEREVSYSEVOUTF _SFR_MEM8(0x0233) +#define EVSYS_USEREVSYSEVOUTG _SFR_MEM8(0x0234) +#define EVSYS_USERUSART0IRDA _SFR_MEM8(0x0235) +#define EVSYS_USERUSART1IRDA _SFR_MEM8(0x0236) +#define EVSYS_USERUSART2IRDA _SFR_MEM8(0x0237) +#define EVSYS_USERUSART3IRDA _SFR_MEM8(0x0238) +#define EVSYS_USERUSART4IRDA _SFR_MEM8(0x0239) +#define EVSYS_USERUSART5IRDA _SFR_MEM8(0x023A) +#define EVSYS_USERTCA0CNTA _SFR_MEM8(0x023B) +#define EVSYS_USERTCA0CNTB _SFR_MEM8(0x023C) +#define EVSYS_USERTCA1CNTA _SFR_MEM8(0x023D) +#define EVSYS_USERTCA1CNTB _SFR_MEM8(0x023E) +#define EVSYS_USERTCB0CAPT _SFR_MEM8(0x023F) +#define EVSYS_USERTCB0COUNT _SFR_MEM8(0x0240) +#define EVSYS_USERTCB1CAPT _SFR_MEM8(0x0241) +#define EVSYS_USERTCB1COUNT _SFR_MEM8(0x0242) +#define EVSYS_USERTCB2CAPT _SFR_MEM8(0x0243) +#define EVSYS_USERTCB2COUNT _SFR_MEM8(0x0244) +#define EVSYS_USERTCB3CAPT _SFR_MEM8(0x0245) +#define EVSYS_USERTCB3COUNT _SFR_MEM8(0x0246) +#define EVSYS_USERTCB4CAPT _SFR_MEM8(0x0247) +#define EVSYS_USERTCB4COUNT _SFR_MEM8(0x0248) +#define EVSYS_USERTCD0INPUTA _SFR_MEM8(0x0249) +#define EVSYS_USERTCD0INPUTB _SFR_MEM8(0x024A) +#define EVSYS_USEROSCTEST _SFR_MEM8(0x024B) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PORTCTRL _SFR_MEM8(0x040A) +#define PORTA_PINCONFIG _SFR_MEM8(0x040B) +#define PORTA_PINCTRLUPD _SFR_MEM8(0x040C) +#define PORTA_PINCTRLSET _SFR_MEM8(0x040D) +#define PORTA_PINCTRLCLR _SFR_MEM8(0x040E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PORTCTRL _SFR_MEM8(0x042A) +#define PORTB_PINCONFIG _SFR_MEM8(0x042B) +#define PORTB_PINCTRLUPD _SFR_MEM8(0x042C) +#define PORTB_PINCTRLSET _SFR_MEM8(0x042D) +#define PORTB_PINCTRLCLR _SFR_MEM8(0x042E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PORTCTRL _SFR_MEM8(0x044A) +#define PORTC_PINCONFIG _SFR_MEM8(0x044B) +#define PORTC_PINCTRLUPD _SFR_MEM8(0x044C) +#define PORTC_PINCTRLSET _SFR_MEM8(0x044D) +#define PORTC_PINCTRLCLR _SFR_MEM8(0x044E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* PORT (PORTD) - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0460) +#define PORTD_DIRSET _SFR_MEM8(0x0461) +#define PORTD_DIRCLR _SFR_MEM8(0x0462) +#define PORTD_DIRTGL _SFR_MEM8(0x0463) +#define PORTD_OUT _SFR_MEM8(0x0464) +#define PORTD_OUTSET _SFR_MEM8(0x0465) +#define PORTD_OUTCLR _SFR_MEM8(0x0466) +#define PORTD_OUTTGL _SFR_MEM8(0x0467) +#define PORTD_IN _SFR_MEM8(0x0468) +#define PORTD_INTFLAGS _SFR_MEM8(0x0469) +#define PORTD_PORTCTRL _SFR_MEM8(0x046A) +#define PORTD_PINCONFIG _SFR_MEM8(0x046B) +#define PORTD_PINCTRLUPD _SFR_MEM8(0x046C) +#define PORTD_PINCTRLSET _SFR_MEM8(0x046D) +#define PORTD_PINCTRLCLR _SFR_MEM8(0x046E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0470) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0471) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0472) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0473) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0474) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0475) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0476) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0477) + + +/* PORT (PORTE) - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0480) +#define PORTE_DIRSET _SFR_MEM8(0x0481) +#define PORTE_DIRCLR _SFR_MEM8(0x0482) +#define PORTE_DIRTGL _SFR_MEM8(0x0483) +#define PORTE_OUT _SFR_MEM8(0x0484) +#define PORTE_OUTSET _SFR_MEM8(0x0485) +#define PORTE_OUTCLR _SFR_MEM8(0x0486) +#define PORTE_OUTTGL _SFR_MEM8(0x0487) +#define PORTE_IN _SFR_MEM8(0x0488) +#define PORTE_INTFLAGS _SFR_MEM8(0x0489) +#define PORTE_PORTCTRL _SFR_MEM8(0x048A) +#define PORTE_PINCONFIG _SFR_MEM8(0x048B) +#define PORTE_PINCTRLUPD _SFR_MEM8(0x048C) +#define PORTE_PINCTRLSET _SFR_MEM8(0x048D) +#define PORTE_PINCTRLCLR _SFR_MEM8(0x048E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0490) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0491) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0492) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0493) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0494) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0495) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0496) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0497) + + +/* PORT (PORTF) - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x04A0) +#define PORTF_DIRSET _SFR_MEM8(0x04A1) +#define PORTF_DIRCLR _SFR_MEM8(0x04A2) +#define PORTF_DIRTGL _SFR_MEM8(0x04A3) +#define PORTF_OUT _SFR_MEM8(0x04A4) +#define PORTF_OUTSET _SFR_MEM8(0x04A5) +#define PORTF_OUTCLR _SFR_MEM8(0x04A6) +#define PORTF_OUTTGL _SFR_MEM8(0x04A7) +#define PORTF_IN _SFR_MEM8(0x04A8) +#define PORTF_INTFLAGS _SFR_MEM8(0x04A9) +#define PORTF_PORTCTRL _SFR_MEM8(0x04AA) +#define PORTF_PINCONFIG _SFR_MEM8(0x04AB) +#define PORTF_PINCTRLUPD _SFR_MEM8(0x04AC) +#define PORTF_PINCTRLSET _SFR_MEM8(0x04AD) +#define PORTF_PINCTRLCLR _SFR_MEM8(0x04AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x04B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x04B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x04B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x04B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x04B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x04B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x04B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x04B7) + + +/* PORT (PORTG) - I/O Ports */ +#define PORTG_DIR _SFR_MEM8(0x04C0) +#define PORTG_DIRSET _SFR_MEM8(0x04C1) +#define PORTG_DIRCLR _SFR_MEM8(0x04C2) +#define PORTG_DIRTGL _SFR_MEM8(0x04C3) +#define PORTG_OUT _SFR_MEM8(0x04C4) +#define PORTG_OUTSET _SFR_MEM8(0x04C5) +#define PORTG_OUTCLR _SFR_MEM8(0x04C6) +#define PORTG_OUTTGL _SFR_MEM8(0x04C7) +#define PORTG_IN _SFR_MEM8(0x04C8) +#define PORTG_INTFLAGS _SFR_MEM8(0x04C9) +#define PORTG_PORTCTRL _SFR_MEM8(0x04CA) +#define PORTG_PINCONFIG _SFR_MEM8(0x04CB) +#define PORTG_PINCTRLUPD _SFR_MEM8(0x04CC) +#define PORTG_PINCTRLSET _SFR_MEM8(0x04CD) +#define PORTG_PINCTRLCLR _SFR_MEM8(0x04CE) +#define PORTG_PIN0CTRL _SFR_MEM8(0x04D0) +#define PORTG_PIN1CTRL _SFR_MEM8(0x04D1) +#define PORTG_PIN2CTRL _SFR_MEM8(0x04D2) +#define PORTG_PIN3CTRL _SFR_MEM8(0x04D3) +#define PORTG_PIN4CTRL _SFR_MEM8(0x04D4) +#define PORTG_PIN5CTRL _SFR_MEM8(0x04D5) +#define PORTG_PIN6CTRL _SFR_MEM8(0x04D6) +#define PORTG_PIN7CTRL _SFR_MEM8(0x04D7) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_EVSYSROUTEA _SFR_MEM8(0x05E0) +#define PORTMUX_CCLROUTEA _SFR_MEM8(0x05E1) +#define PORTMUX_USARTROUTEA _SFR_MEM8(0x05E2) +#define PORTMUX_USARTROUTEB _SFR_MEM8(0x05E3) +#define PORTMUX_SPIROUTEA _SFR_MEM8(0x05E4) +#define PORTMUX_TWIROUTEA _SFR_MEM8(0x05E5) +#define PORTMUX_TCAROUTEA _SFR_MEM8(0x05E6) +#define PORTMUX_TCBROUTEA _SFR_MEM8(0x05E7) +#define PORTMUX_TCDROUTEA _SFR_MEM8(0x05E8) +#define PORTMUX_ACROUTEA _SFR_MEM8(0x05E9) +#define PORTMUX_ZCDROUTEA _SFR_MEM8(0x05EA) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0608) +#define ADC0_MUXNEG _SFR_MEM8(0x0609) +#define ADC0_COMMAND _SFR_MEM8(0x060A) +#define ADC0_EVCTRL _SFR_MEM8(0x060B) +#define ADC0_INTCTRL _SFR_MEM8(0x060C) +#define ADC0_INTFLAGS _SFR_MEM8(0x060D) +#define ADC0_DBGCTRL _SFR_MEM8(0x060E) +#define ADC0_TEMP _SFR_MEM8(0x060F) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_CTRLB _SFR_MEM8(0x0681) +#define AC0_MUXCTRL _SFR_MEM8(0x0682) +#define AC0_DACREF _SFR_MEM8(0x0685) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* AC (AC1) - Analog Comparator */ +#define AC1_CTRLA _SFR_MEM8(0x0688) +#define AC1_CTRLB _SFR_MEM8(0x0689) +#define AC1_MUXCTRL _SFR_MEM8(0x068A) +#define AC1_DACREF _SFR_MEM8(0x068D) +#define AC1_INTCTRL _SFR_MEM8(0x068E) +#define AC1_STATUS _SFR_MEM8(0x068F) + + +/* AC (AC2) - Analog Comparator */ +#define AC2_CTRLA _SFR_MEM8(0x0690) +#define AC2_CTRLB _SFR_MEM8(0x0691) +#define AC2_MUXCTRL _SFR_MEM8(0x0692) +#define AC2_DACREF _SFR_MEM8(0x0695) +#define AC2_INTCTRL _SFR_MEM8(0x0696) +#define AC2_STATUS _SFR_MEM8(0x0697) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x06A0) +#define DAC0_DATA _SFR_MEM16(0x06A2) +#define DAC0_DATAL _SFR_MEM8(0x06A2) +#define DAC0_DATAH _SFR_MEM8(0x06A3) + + +/* ZCD (ZCD0) - Zero Cross Detect */ +#define ZCD0_CTRLA _SFR_MEM8(0x06C0) +#define ZCD0_INTCTRL _SFR_MEM8(0x06C2) +#define ZCD0_STATUS _SFR_MEM8(0x06C3) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_CTRLD _SFR_MEM8(0x080A) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* USART (USART1) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1_RXDATAL _SFR_MEM8(0x0820) +#define USART1_RXDATAH _SFR_MEM8(0x0821) +#define USART1_TXDATAL _SFR_MEM8(0x0822) +#define USART1_TXDATAH _SFR_MEM8(0x0823) +#define USART1_STATUS _SFR_MEM8(0x0824) +#define USART1_CTRLA _SFR_MEM8(0x0825) +#define USART1_CTRLB _SFR_MEM8(0x0826) +#define USART1_CTRLC _SFR_MEM8(0x0827) +#define USART1_BAUD _SFR_MEM16(0x0828) +#define USART1_BAUDL _SFR_MEM8(0x0828) +#define USART1_BAUDH _SFR_MEM8(0x0829) +#define USART1_CTRLD _SFR_MEM8(0x082A) +#define USART1_DBGCTRL _SFR_MEM8(0x082B) +#define USART1_EVCTRL _SFR_MEM8(0x082C) +#define USART1_TXPLCTRL _SFR_MEM8(0x082D) +#define USART1_RXPLCTRL _SFR_MEM8(0x082E) + + +/* USART (USART2) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2_RXDATAL _SFR_MEM8(0x0840) +#define USART2_RXDATAH _SFR_MEM8(0x0841) +#define USART2_TXDATAL _SFR_MEM8(0x0842) +#define USART2_TXDATAH _SFR_MEM8(0x0843) +#define USART2_STATUS _SFR_MEM8(0x0844) +#define USART2_CTRLA _SFR_MEM8(0x0845) +#define USART2_CTRLB _SFR_MEM8(0x0846) +#define USART2_CTRLC _SFR_MEM8(0x0847) +#define USART2_BAUD _SFR_MEM16(0x0848) +#define USART2_BAUDL _SFR_MEM8(0x0848) +#define USART2_BAUDH _SFR_MEM8(0x0849) +#define USART2_CTRLD _SFR_MEM8(0x084A) +#define USART2_DBGCTRL _SFR_MEM8(0x084B) +#define USART2_EVCTRL _SFR_MEM8(0x084C) +#define USART2_TXPLCTRL _SFR_MEM8(0x084D) +#define USART2_RXPLCTRL _SFR_MEM8(0x084E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0900) +#define TWI0_DUALCTRL _SFR_MEM8(0x0901) +#define TWI0_DBGCTRL _SFR_MEM8(0x0902) +#define TWI0_MCTRLA _SFR_MEM8(0x0903) +#define TWI0_MCTRLB _SFR_MEM8(0x0904) +#define TWI0_MSTATUS _SFR_MEM8(0x0905) +#define TWI0_MBAUD _SFR_MEM8(0x0906) +#define TWI0_MADDR _SFR_MEM8(0x0907) +#define TWI0_MDATA _SFR_MEM8(0x0908) +#define TWI0_SCTRLA _SFR_MEM8(0x0909) +#define TWI0_SCTRLB _SFR_MEM8(0x090A) +#define TWI0_SSTATUS _SFR_MEM8(0x090B) +#define TWI0_SADDR _SFR_MEM8(0x090C) +#define TWI0_SDATA _SFR_MEM8(0x090D) +#define TWI0_SADDRMASK _SFR_MEM8(0x090E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0940) +#define SPI0_CTRLB _SFR_MEM8(0x0941) +#define SPI0_INTCTRL _SFR_MEM8(0x0942) +#define SPI0_INTFLAGS _SFR_MEM8(0x0943) +#define SPI0_DATA _SFR_MEM8(0x0944) + + +/* SPI (SPI1) - Serial Peripheral Interface */ +#define SPI1_CTRLA _SFR_MEM8(0x0960) +#define SPI1_CTRLB _SFR_MEM8(0x0961) +#define SPI1_INTCTRL _SFR_MEM8(0x0962) +#define SPI1_INTFLAGS _SFR_MEM8(0x0963) +#define SPI1_DATA _SFR_MEM8(0x0964) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0B00) +#define TCB0_CTRLB _SFR_MEM8(0x0B01) +#define TCB0_EVCTRL _SFR_MEM8(0x0B04) +#define TCB0_INTCTRL _SFR_MEM8(0x0B05) +#define TCB0_INTFLAGS _SFR_MEM8(0x0B06) +#define TCB0_STATUS _SFR_MEM8(0x0B07) +#define TCB0_DBGCTRL _SFR_MEM8(0x0B08) +#define TCB0_TEMP _SFR_MEM8(0x0B09) +#define TCB0_CNT _SFR_MEM16(0x0B0A) +#define TCB0_CNTL _SFR_MEM8(0x0B0A) +#define TCB0_CNTH _SFR_MEM8(0x0B0B) +#define TCB0_CCMP _SFR_MEM16(0x0B0C) +#define TCB0_CCMPL _SFR_MEM8(0x0B0C) +#define TCB0_CCMPH _SFR_MEM8(0x0B0D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0B10) +#define TCB1_CTRLB _SFR_MEM8(0x0B11) +#define TCB1_EVCTRL _SFR_MEM8(0x0B14) +#define TCB1_INTCTRL _SFR_MEM8(0x0B15) +#define TCB1_INTFLAGS _SFR_MEM8(0x0B16) +#define TCB1_STATUS _SFR_MEM8(0x0B17) +#define TCB1_DBGCTRL _SFR_MEM8(0x0B18) +#define TCB1_TEMP _SFR_MEM8(0x0B19) +#define TCB1_CNT _SFR_MEM16(0x0B1A) +#define TCB1_CNTL _SFR_MEM8(0x0B1A) +#define TCB1_CNTH _SFR_MEM8(0x0B1B) +#define TCB1_CCMP _SFR_MEM16(0x0B1C) +#define TCB1_CCMPL _SFR_MEM8(0x0B1C) +#define TCB1_CCMPH _SFR_MEM8(0x0B1D) + + +/* TCB (TCB2) - 16-bit Timer Type B */ +#define TCB2_CTRLA _SFR_MEM8(0x0B20) +#define TCB2_CTRLB _SFR_MEM8(0x0B21) +#define TCB2_EVCTRL _SFR_MEM8(0x0B24) +#define TCB2_INTCTRL _SFR_MEM8(0x0B25) +#define TCB2_INTFLAGS _SFR_MEM8(0x0B26) +#define TCB2_STATUS _SFR_MEM8(0x0B27) +#define TCB2_DBGCTRL _SFR_MEM8(0x0B28) +#define TCB2_TEMP _SFR_MEM8(0x0B29) +#define TCB2_CNT _SFR_MEM16(0x0B2A) +#define TCB2_CNTL _SFR_MEM8(0x0B2A) +#define TCB2_CNTH _SFR_MEM8(0x0B2B) +#define TCB2_CCMP _SFR_MEM16(0x0B2C) +#define TCB2_CCMPL _SFR_MEM8(0x0B2C) +#define TCB2_CCMPH _SFR_MEM8(0x0B2D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0B80) +#define TCD0_CTRLB _SFR_MEM8(0x0B81) +#define TCD0_CTRLC _SFR_MEM8(0x0B82) +#define TCD0_CTRLD _SFR_MEM8(0x0B83) +#define TCD0_CTRLE _SFR_MEM8(0x0B84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0B88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0B89) +#define TCD0_INTCTRL _SFR_MEM8(0x0B8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0B8D) +#define TCD0_STATUS _SFR_MEM8(0x0B8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0B90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0B91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0B92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0B94) +#define TCD0_DLYVAL _SFR_MEM8(0x0B95) +#define TCD0_DITCTRL _SFR_MEM8(0x0B98) +#define TCD0_DITVAL _SFR_MEM8(0x0B99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0B9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0BA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0BA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0BA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0BA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0BA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0BA5) +#define TCD0_CMPASET _SFR_MEM16(0x0BA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0BA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0BA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0BAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0BAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0BAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0BAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0BAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0BAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0BAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0BAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0BAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_OCDMCTRL _SFR_MEM8(0x0F18) +#define SYSCFG_OCDMSTATUS _SFR_MEM8(0x0F19) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM32(0x1008) +#define NVMCTRL_ADDR0 _SFR_MEM8(0x1008) +#define NVMCTRL_ADDR1 _SFR_MEM8(0x1009) +#define NVMCTRL_ADDR2 _SFR_MEM8(0x100A) +#define NVMCTRL_ADDR3 _SFR_MEM8(0x100B) + + +/* LOCK - Lockbits */ +#define LOCK_KEY _SFR_MEM32(0x1040) +#define LOCK_KEY0 _SFR_MEM8(0x1040) +#define LOCK_KEY1 _SFR_MEM8(0x1041) +#define LOCK_KEY2 _SFR_MEM8(0x1042) +#define LOCK_KEY3 _SFR_MEM8(0x1043) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1050) +#define FUSE_BODCFG _SFR_MEM8(0x1051) +#define FUSE_OSCCFG _SFR_MEM8(0x1052) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1055) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1056) +#define FUSE_CODESIZE _SFR_MEM8(0x1057) +#define FUSE_BOOTSIZE _SFR_MEM8(0x1058) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1080) +#define USERROW_USERROW1 _SFR_MEM8(0x1081) +#define USERROW_USERROW2 _SFR_MEM8(0x1082) +#define USERROW_USERROW3 _SFR_MEM8(0x1083) +#define USERROW_USERROW4 _SFR_MEM8(0x1084) +#define USERROW_USERROW5 _SFR_MEM8(0x1085) +#define USERROW_USERROW6 _SFR_MEM8(0x1086) +#define USERROW_USERROW7 _SFR_MEM8(0x1087) +#define USERROW_USERROW8 _SFR_MEM8(0x1088) +#define USERROW_USERROW9 _SFR_MEM8(0x1089) +#define USERROW_USERROW10 _SFR_MEM8(0x108A) +#define USERROW_USERROW11 _SFR_MEM8(0x108B) +#define USERROW_USERROW12 _SFR_MEM8(0x108C) +#define USERROW_USERROW13 _SFR_MEM8(0x108D) +#define USERROW_USERROW14 _SFR_MEM8(0x108E) +#define USERROW_USERROW15 _SFR_MEM8(0x108F) +#define USERROW_USERROW16 _SFR_MEM8(0x1090) +#define USERROW_USERROW17 _SFR_MEM8(0x1091) +#define USERROW_USERROW18 _SFR_MEM8(0x1092) +#define USERROW_USERROW19 _SFR_MEM8(0x1093) +#define USERROW_USERROW20 _SFR_MEM8(0x1094) +#define USERROW_USERROW21 _SFR_MEM8(0x1095) +#define USERROW_USERROW22 _SFR_MEM8(0x1096) +#define USERROW_USERROW23 _SFR_MEM8(0x1097) +#define USERROW_USERROW24 _SFR_MEM8(0x1098) +#define USERROW_USERROW25 _SFR_MEM8(0x1099) +#define USERROW_USERROW26 _SFR_MEM8(0x109A) +#define USERROW_USERROW27 _SFR_MEM8(0x109B) +#define USERROW_USERROW28 _SFR_MEM8(0x109C) +#define USERROW_USERROW29 _SFR_MEM8(0x109D) +#define USERROW_USERROW30 _SFR_MEM8(0x109E) +#define USERROW_USERROW31 _SFR_MEM8(0x109F) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_TEMPSENSE0 _SFR_MEM16(0x1104) +#define SIGROW_TEMPSENSE0L _SFR_MEM8(0x1104) +#define SIGROW_TEMPSENSE0H _SFR_MEM8(0x1105) +#define SIGROW_TEMPSENSE1 _SFR_MEM16(0x1106) +#define SIGROW_TEMPSENSE1L _SFR_MEM8(0x1106) +#define SIGROW_TEMPSENSE1H _SFR_MEM8(0x1107) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1110) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1111) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1112) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1113) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1114) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1115) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1116) +#define SIGROW_SERNUM7 _SFR_MEM8(0x1117) +#define SIGROW_SERNUM8 _SFR_MEM8(0x1118) +#define SIGROW_SERNUM9 _SFR_MEM8(0x1119) +#define SIGROW_SERNUM10 _SFR_MEM8(0x111A) +#define SIGROW_SERNUM11 _SFR_MEM8(0x111B) +#define SIGROW_SERNUM12 _SFR_MEM8(0x111C) +#define SIGROW_SERNUM13 _SFR_MEM8(0x111D) +#define SIGROW_SERNUM14 _SFR_MEM8(0x111E) +#define SIGROW_SERNUM15 _SFR_MEM8(0x111F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_POWER_gm 0x18 /* Power profile group mask. */ +#define AC_POWER_gp 3 /* Power profile group position. */ +#define AC_POWER0_bm (1<<3) /* Power profile bit 0 mask. */ +#define AC_POWER0_bp 3 /* Power profile bit 0 position. */ +#define AC_POWER1_bm (1<<4) /* Power profile bit 1 mask. */ +#define AC_POWER1_bp 4 /* Power profile bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Pad Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Pad Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_WINSEL_gm 0x03 /* Window selection mode group mask. */ +#define AC_WINSEL_gp 0 /* Window selection mode group position. */ +#define AC_WINSEL0_bm (1<<0) /* Window selection mode bit 0 mask. */ +#define AC_WINSEL0_bp 0 /* Window selection mode bit 0 position. */ +#define AC_WINSEL1_bm (1<<1) /* Window selection mode bit 1 mask. */ +#define AC_WINSEL1_bp 1 /* Window selection mode bit 1 position. */ + +/* AC.MUXCTRL bit masks and bit positions */ +#define AC_MUXNEG_gm 0x07 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* Negative Input MUX Selection bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* Negative Input MUX Selection bit 2 position. */ +#define AC_MUXPOS_gm 0x38 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* Positive Input MUX Selection bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* Positive Input MUX Selection bit 2 position. */ +#define AC_INITVAL_bm 0x40 /* AC Output Initial Value bit mask. */ +#define AC_INITVAL_bp 6 /* AC Output Initial Value bit position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.DACREF bit masks and bit positions */ +#define AC_DACREF_gm 0xFF /* DACREF group mask. */ +#define AC_DACREF_gp 0 /* DACREF group position. */ +#define AC_DACREF0_bm (1<<0) /* DACREF bit 0 mask. */ +#define AC_DACREF0_bp 0 /* DACREF bit 0 position. */ +#define AC_DACREF1_bm (1<<1) /* DACREF bit 1 mask. */ +#define AC_DACREF1_bp 1 /* DACREF bit 1 position. */ +#define AC_DACREF2_bm (1<<2) /* DACREF bit 2 mask. */ +#define AC_DACREF2_bp 2 /* DACREF bit 2 position. */ +#define AC_DACREF3_bm (1<<3) /* DACREF bit 3 mask. */ +#define AC_DACREF3_bp 3 /* DACREF bit 3 position. */ +#define AC_DACREF4_bm (1<<4) /* DACREF bit 4 mask. */ +#define AC_DACREF4_bp 4 /* DACREF bit 4 position. */ +#define AC_DACREF5_bm (1<<5) /* DACREF bit 5 mask. */ +#define AC_DACREF5_bp 5 /* DACREF bit 5 position. */ +#define AC_DACREF6_bm (1<<6) /* DACREF bit 6 mask. */ +#define AC_DACREF6_bp 6 /* DACREF bit 6 position. */ +#define AC_DACREF7_bm (1<<7) /* DACREF bit 7 mask. */ +#define AC_DACREF7_bp 7 /* DACREF bit 7 position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_CMPIF_bm 0x01 /* Analog Comparator Interrupt Flag bit mask. */ +#define AC_CMPIF_bp 0 /* Analog Comparator Interrupt Flag bit position. */ +#define AC_CMPSTATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_CMPSTATE_bp 4 /* Analog Comparator State bit position. */ +#define AC_WINSTATE_gm 0xC0 /* Analog Comparator Window State group mask. */ +#define AC_WINSTATE_gp 6 /* Analog Comparator Window State group position. */ +#define AC_WINSTATE0_bm (1<<6) /* Analog Comparator Window State bit 0 mask. */ +#define AC_WINSTATE0_bp 6 /* Analog Comparator Window State bit 0 position. */ +#define AC_WINSTATE1_bm (1<<7) /* Analog Comparator Window State bit 1 mask. */ +#define AC_WINSTATE1_bp 7 /* Analog Comparator Window State bit 1 position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* Free running mode bit mask. */ +#define ADC_FREERUN_bp 1 /* Free running mode bit position. */ +#define ADC_RESSEL_gm 0x0C /* Resolution selection group mask. */ +#define ADC_RESSEL_gp 2 /* Resolution selection group position. */ +#define ADC_RESSEL0_bm (1<<2) /* Resolution selection bit 0 mask. */ +#define ADC_RESSEL0_bp 2 /* Resolution selection bit 0 position. */ +#define ADC_RESSEL1_bm (1<<3) /* Resolution selection bit 1 mask. */ +#define ADC_RESSEL1_bp 3 /* Resolution selection bit 1 position. */ +#define ADC_LEFTADJ_bm 0x10 /* Left adjust result bit mask. */ +#define ADC_LEFTADJ_bp 4 /* Left adjust result bit position. */ +#define ADC_CONVMODE_bm 0x20 /* Conversion mode bit mask. */ +#define ADC_CONVMODE_bp 5 /* Conversion mode bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x0F /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_PRESC3_bm (1<<3) /* Clock Pre-scaler bit 3 mask. */ +#define ADC_PRESC3_bp 3 /* Clock Pre-scaler bit 3 position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0xFF /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ +#define ADC_SAMPLEN5_bm (1<<5) /* Sample lenght bit 5 mask. */ +#define ADC_SAMPLEN5_bp 5 /* Sample lenght bit 5 position. */ +#define ADC_SAMPLEN6_bm (1<<6) /* Sample lenght bit 6 mask. */ +#define ADC_SAMPLEN6_bp 6 /* Sample lenght bit 6 position. */ +#define ADC_SAMPLEN7_bm (1<<7) /* Sample lenght bit 7 mask. */ +#define ADC_SAMPLEN7_bp 7 /* Sample lenght bit 7 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x7F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ +#define ADC_MUXPOS5_bm (1<<5) /* Analog Channel Selection Bits bit 5 mask. */ +#define ADC_MUXPOS5_bp 5 /* Analog Channel Selection Bits bit 5 position. */ +#define ADC_MUXPOS6_bm (1<<6) /* Analog Channel Selection Bits bit 6 mask. */ +#define ADC_MUXPOS6_bp 6 /* Analog Channel Selection Bits bit 6 position. */ + +/* ADC.MUXNEG bit masks and bit positions */ +#define ADC_MUXNEG_gm 0x7F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXNEG_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXNEG0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXNEG0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXNEG1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXNEG1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXNEG2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXNEG2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXNEG3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXNEG3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXNEG4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXNEG4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ +#define ADC_MUXNEG5_bm (1<<5) /* Analog Channel Selection Bits bit 5 mask. */ +#define ADC_MUXNEG5_bp 5 /* Analog Channel Selection Bits bit 5 position. */ +#define ADC_MUXNEG6_bm (1<<6) /* Analog Channel Selection Bits bit 6 mask. */ +#define ADC_MUXNEG6_bp 6 /* Analog Channel Selection Bits bit 6 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion bit position. */ +#define ADC_SPCONV_bm 0x02 /* Stop Conversion bit mask. */ +#define ADC_SPCONV_bp 1 /* Stop Conversion bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL0_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL0_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL00_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL00_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL01_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL01_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL02_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL02_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.SEQCTRL1 bit masks and bit positions */ +#define CCL_SEQSEL1_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL1_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL10_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL10_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL11_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL11_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL12_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL12_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.INTCTRL0 bit masks and bit positions */ +#define CCL_INTMODE0_gm 0x03 /* Interrupt Mode for LUT0 group mask. */ +#define CCL_INTMODE0_gp 0 /* Interrupt Mode for LUT0 group position. */ +#define CCL_INTMODE00_bm (1<<0) /* Interrupt Mode for LUT0 bit 0 mask. */ +#define CCL_INTMODE00_bp 0 /* Interrupt Mode for LUT0 bit 0 position. */ +#define CCL_INTMODE01_bm (1<<1) /* Interrupt Mode for LUT0 bit 1 mask. */ +#define CCL_INTMODE01_bp 1 /* Interrupt Mode for LUT0 bit 1 position. */ +#define CCL_INTMODE1_gm 0x0C /* Interrupt Mode for LUT1 group mask. */ +#define CCL_INTMODE1_gp 2 /* Interrupt Mode for LUT1 group position. */ +#define CCL_INTMODE10_bm (1<<2) /* Interrupt Mode for LUT1 bit 0 mask. */ +#define CCL_INTMODE10_bp 2 /* Interrupt Mode for LUT1 bit 0 position. */ +#define CCL_INTMODE11_bm (1<<3) /* Interrupt Mode for LUT1 bit 1 mask. */ +#define CCL_INTMODE11_bp 3 /* Interrupt Mode for LUT1 bit 1 position. */ +#define CCL_INTMODE2_gm 0x30 /* Interrupt Mode for LUT2 group mask. */ +#define CCL_INTMODE2_gp 4 /* Interrupt Mode for LUT2 group position. */ +#define CCL_INTMODE20_bm (1<<4) /* Interrupt Mode for LUT2 bit 0 mask. */ +#define CCL_INTMODE20_bp 4 /* Interrupt Mode for LUT2 bit 0 position. */ +#define CCL_INTMODE21_bm (1<<5) /* Interrupt Mode for LUT2 bit 1 mask. */ +#define CCL_INTMODE21_bp 5 /* Interrupt Mode for LUT2 bit 1 position. */ +#define CCL_INTMODE3_gm 0xC0 /* Interrupt Mode for LUT3 group mask. */ +#define CCL_INTMODE3_gp 6 /* Interrupt Mode for LUT3 group position. */ +#define CCL_INTMODE30_bm (1<<6) /* Interrupt Mode for LUT3 bit 0 mask. */ +#define CCL_INTMODE30_bp 6 /* Interrupt Mode for LUT3 bit 0 position. */ +#define CCL_INTMODE31_bm (1<<7) /* Interrupt Mode for LUT3 bit 1 mask. */ +#define CCL_INTMODE31_bp 7 /* Interrupt Mode for LUT3 bit 1 position. */ + +/* CCL.INTFLAGS bit masks and bit positions */ +#define CCL_INT_gm 0xFF /* Interrupt Flags group mask. */ +#define CCL_INT_gp 0 /* Interrupt Flags group position. */ +#define CCL_INT0_bm (1<<0) /* Interrupt Flags bit 0 mask. */ +#define CCL_INT0_bp 0 /* Interrupt Flags bit 0 position. */ +#define CCL_INT1_bm (1<<1) /* Interrupt Flags bit 1 mask. */ +#define CCL_INT1_bp 1 /* Interrupt Flags bit 1 position. */ +#define CCL_INT2_bm (1<<2) /* Interrupt Flags bit 2 mask. */ +#define CCL_INT2_bp 2 /* Interrupt Flags bit 2 position. */ +#define CCL_INT3_bm (1<<3) /* Interrupt Flags bit 3 mask. */ +#define CCL_INT3_bp 3 /* Interrupt Flags bit 3 position. */ +#define CCL_INT4_bm (1<<4) /* Interrupt Flags bit 4 mask. */ +#define CCL_INT4_bp 4 /* Interrupt Flags bit 4 position. */ +#define CCL_INT5_bm (1<<5) /* Interrupt Flags bit 5 mask. */ +#define CCL_INT5_bp 5 /* Interrupt Flags bit 5 position. */ +#define CCL_INT6_bm (1<<6) /* Interrupt Flags bit 6 mask. */ +#define CCL_INT6_bp 6 /* Interrupt Flags bit 6 position. */ +#define CCL_INT7_bm (1<<7) /* Interrupt Flags bit 7 mask. */ +#define CCL_INT7_bp 7 /* Interrupt Flags bit 7 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_CLKSRC_gm 0x0E /* Clock Source Selection group mask. */ +#define CCL_CLKSRC_gp 1 /* Clock Source Selection group position. */ +#define CCL_CLKSRC0_bm (1<<1) /* Clock Source Selection bit 0 mask. */ +#define CCL_CLKSRC0_bp 1 /* Clock Source Selection bit 0 position. */ +#define CCL_CLKSRC1_bm (1<<2) /* Clock Source Selection bit 1 mask. */ +#define CCL_CLKSRC1_bp 2 /* Clock Source Selection bit 1 position. */ +#define CCL_CLKSRC2_bm (1<<3) /* Clock Source Selection bit 2 mask. */ +#define CCL_CLKSRC2_bp 3 /* Clock Source Selection bit 2 position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_OUTEN_bm 0x40 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 6 /* Output Enable bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT2CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT2CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT2CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT3CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT3CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT3CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x07 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKSEL2_bm (1<<2) /* clock select bit 2 mask. */ +#define CLKCTRL_CLKSEL2_bp 2 /* clock select bit 2 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSCHFS_bm 0x02 /* High frequency oscillator status bit mask. */ +#define CLKCTRL_OSCHFS_bp 1 /* High frequency oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x04 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 2 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x08 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 3 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x10 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 4 /* External Clock status bit position. */ +#define CLKCTRL_PLLS_bm 0x20 /* PLL oscillator status bit mask. */ +#define CLKCTRL_PLLS_bp 5 /* PLL oscillator status bit position. */ + +/* CLKCTRL.OSCHFCTRLA bit masks and bit positions */ +#define CLKCTRL_AUTOTUNE_bm 0x01 /* Autotune bit mask. */ +#define CLKCTRL_AUTOTUNE_bp 0 /* Autotune bit position. */ +#define CLKCTRL_FREQSEL_gm 0x3C /* Frequency select group mask. */ +#define CLKCTRL_FREQSEL_gp 2 /* Frequency select group position. */ +#define CLKCTRL_FREQSEL0_bm (1<<2) /* Frequency select bit 0 mask. */ +#define CLKCTRL_FREQSEL0_bp 2 /* Frequency select bit 0 position. */ +#define CLKCTRL_FREQSEL1_bm (1<<3) /* Frequency select bit 1 mask. */ +#define CLKCTRL_FREQSEL1_bp 3 /* Frequency select bit 1 position. */ +#define CLKCTRL_FREQSEL2_bm (1<<4) /* Frequency select bit 2 mask. */ +#define CLKCTRL_FREQSEL2_bp 4 /* Frequency select bit 2 position. */ +#define CLKCTRL_FREQSEL3_bm (1<<5) /* Frequency select bit 3 mask. */ +#define CLKCTRL_FREQSEL3_bp 5 /* Frequency select bit 3 position. */ +#define CLKCTRL_RUNSTDBY_bm 0x80 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 7 /* Run standby bit position. */ + +/* CLKCTRL.OSCHFTUNE bit masks and bit positions */ +#define CLKCTRL_TUNE_gm 0xFF /* Tune group mask. */ +#define CLKCTRL_TUNE_gp 0 /* Tune group position. */ +#define CLKCTRL_TUNE0_bm (1<<0) /* Tune bit 0 mask. */ +#define CLKCTRL_TUNE0_bp 0 /* Tune bit 0 position. */ +#define CLKCTRL_TUNE1_bm (1<<1) /* Tune bit 1 mask. */ +#define CLKCTRL_TUNE1_bp 1 /* Tune bit 1 position. */ +#define CLKCTRL_TUNE2_bm (1<<2) /* Tune bit 2 mask. */ +#define CLKCTRL_TUNE2_bp 2 /* Tune bit 2 position. */ +#define CLKCTRL_TUNE3_bm (1<<3) /* Tune bit 3 mask. */ +#define CLKCTRL_TUNE3_bp 3 /* Tune bit 3 position. */ +#define CLKCTRL_TUNE4_bm (1<<4) /* Tune bit 4 mask. */ +#define CLKCTRL_TUNE4_bp 4 /* Tune bit 4 position. */ +#define CLKCTRL_TUNE5_bm (1<<5) /* Tune bit 5 mask. */ +#define CLKCTRL_TUNE5_bp 5 /* Tune bit 5 position. */ +#define CLKCTRL_TUNE6_bm (1<<6) /* Tune bit 6 mask. */ +#define CLKCTRL_TUNE6_bp 6 /* Tune bit 6 position. */ +#define CLKCTRL_TUNE7_bm (1<<7) /* Tune bit 7 mask. */ +#define CLKCTRL_TUNE7_bp 7 /* Tune bit 7 position. */ + +/* CLKCTRL.PLLCTRLA bit masks and bit positions */ +#define CLKCTRL_MULFAC_gm 0x03 /* Multiplication factor group mask. */ +#define CLKCTRL_MULFAC_gp 0 /* Multiplication factor group position. */ +#define CLKCTRL_MULFAC0_bm (1<<0) /* Multiplication factor bit 0 mask. */ +#define CLKCTRL_MULFAC0_bp 0 /* Multiplication factor bit 0 position. */ +#define CLKCTRL_MULFAC1_bm (1<<1) /* Multiplication factor bit 1 mask. */ +#define CLKCTRL_MULFAC1_bp 1 /* Multiplication factor bit 1 position. */ +#define CLKCTRL_SOURCE_bm 0x10 /* Source bit mask. */ +#define CLKCTRL_SOURCE_bp 4 /* Source bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +#define CLKCTRL_LPMODE_bm 0x02 /* Low power mode bit mask. */ +#define CLKCTRL_LPMODE_bp 1 /* Low power mode bit position. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* DAC.DATA bit masks and bit positions */ +#define DAC_DATA_gm 0xFFC0 /* Data group mask. */ +#define DAC_DATA_gp 6 /* Data group position. */ +#define DAC_DATA0_bm (1<<6) /* Data bit 0 mask. */ +#define DAC_DATA0_bp 6 /* Data bit 0 position. */ +#define DAC_DATA1_bm (1<<7) /* Data bit 1 mask. */ +#define DAC_DATA1_bp 7 /* Data bit 1 position. */ +#define DAC_DATA2_bm (1<<8) /* Data bit 2 mask. */ +#define DAC_DATA2_bp 8 /* Data bit 2 position. */ +#define DAC_DATA3_bm (1<<9) /* Data bit 3 mask. */ +#define DAC_DATA3_bp 9 /* Data bit 3 position. */ +#define DAC_DATA4_bm (1<<10) /* Data bit 4 mask. */ +#define DAC_DATA4_bp 10 /* Data bit 4 position. */ +#define DAC_DATA5_bm (1<<11) /* Data bit 5 mask. */ +#define DAC_DATA5_bp 11 /* Data bit 5 position. */ +#define DAC_DATA6_bm (1<<12) /* Data bit 6 mask. */ +#define DAC_DATA6_bp 12 /* Data bit 6 position. */ +#define DAC_DATA7_bm (1<<13) /* Data bit 7 mask. */ +#define DAC_DATA7_bp 13 /* Data bit 7 position. */ +#define DAC_DATA8_bm (1<<14) /* Data bit 8 mask. */ +#define DAC_DATA8_bp 14 /* Data bit 8 position. */ +#define DAC_DATA9_bm (1<<15) /* Data bit 9 mask. */ +#define DAC_DATA9_bp 15 /* Data bit 9 position. */ + +/* EVSYS - Event System */ +/* EVSYS.SWEVENTA bit masks and bit positions */ +#define EVSYS_SWEVENTA_gm 0xFF /* Software event on channel select group mask. */ +#define EVSYS_SWEVENTA_gp 0 /* Software event on channel select group position. */ +#define EVSYS_SWEVENTA0_bm (1<<0) /* Software event on channel select bit 0 mask. */ +#define EVSYS_SWEVENTA0_bp 0 /* Software event on channel select bit 0 position. */ +#define EVSYS_SWEVENTA1_bm (1<<1) /* Software event on channel select bit 1 mask. */ +#define EVSYS_SWEVENTA1_bp 1 /* Software event on channel select bit 1 position. */ +#define EVSYS_SWEVENTA2_bm (1<<2) /* Software event on channel select bit 2 mask. */ +#define EVSYS_SWEVENTA2_bp 2 /* Software event on channel select bit 2 position. */ +#define EVSYS_SWEVENTA3_bm (1<<3) /* Software event on channel select bit 3 mask. */ +#define EVSYS_SWEVENTA3_bp 3 /* Software event on channel select bit 3 position. */ +#define EVSYS_SWEVENTA4_bm (1<<4) /* Software event on channel select bit 4 mask. */ +#define EVSYS_SWEVENTA4_bp 4 /* Software event on channel select bit 4 position. */ +#define EVSYS_SWEVENTA5_bm (1<<5) /* Software event on channel select bit 5 mask. */ +#define EVSYS_SWEVENTA5_bp 5 /* Software event on channel select bit 5 position. */ +#define EVSYS_SWEVENTA6_bm (1<<6) /* Software event on channel select bit 6 mask. */ +#define EVSYS_SWEVENTA6_bp 6 /* Software event on channel select bit 6 position. */ +#define EVSYS_SWEVENTA7_bm (1<<7) /* Software event on channel select bit 7 mask. */ +#define EVSYS_SWEVENTA7_bp 7 /* Software event on channel select bit 7 position. */ + +/* EVSYS.SWEVENTB bit masks and bit positions */ +#define EVSYS_SWEVENTB_gm 0x03 /* Software event on channel select group mask. */ +#define EVSYS_SWEVENTB_gp 0 /* Software event on channel select group position. */ +#define EVSYS_SWEVENTB0_bm (1<<0) /* Software event on channel select bit 0 mask. */ +#define EVSYS_SWEVENTB0_bp 0 /* Software event on channel select bit 0 position. */ +#define EVSYS_SWEVENTB1_bm (1<<1) /* Software event on channel select bit 1 mask. */ +#define EVSYS_SWEVENTB1_bp 1 /* Software event on channel select bit 1 position. */ + +/* EVSYS.CHANNEL0 bit masks and bit positions */ +#define EVSYS_CHANNEL0_gm 0xFF /* Channel 0 generator select group mask. */ +#define EVSYS_CHANNEL0_gp 0 /* Channel 0 generator select group position. */ +#define EVSYS_CHANNEL00_bm (1<<0) /* Channel 0 generator select bit 0 mask. */ +#define EVSYS_CHANNEL00_bp 0 /* Channel 0 generator select bit 0 position. */ +#define EVSYS_CHANNEL01_bm (1<<1) /* Channel 0 generator select bit 1 mask. */ +#define EVSYS_CHANNEL01_bp 1 /* Channel 0 generator select bit 1 position. */ +#define EVSYS_CHANNEL02_bm (1<<2) /* Channel 0 generator select bit 2 mask. */ +#define EVSYS_CHANNEL02_bp 2 /* Channel 0 generator select bit 2 position. */ +#define EVSYS_CHANNEL03_bm (1<<3) /* Channel 0 generator select bit 3 mask. */ +#define EVSYS_CHANNEL03_bp 3 /* Channel 0 generator select bit 3 position. */ +#define EVSYS_CHANNEL04_bm (1<<4) /* Channel 0 generator select bit 4 mask. */ +#define EVSYS_CHANNEL04_bp 4 /* Channel 0 generator select bit 4 position. */ +#define EVSYS_CHANNEL05_bm (1<<5) /* Channel 0 generator select bit 5 mask. */ +#define EVSYS_CHANNEL05_bp 5 /* Channel 0 generator select bit 5 position. */ +#define EVSYS_CHANNEL06_bm (1<<6) /* Channel 0 generator select bit 6 mask. */ +#define EVSYS_CHANNEL06_bp 6 /* Channel 0 generator select bit 6 position. */ +#define EVSYS_CHANNEL07_bm (1<<7) /* Channel 0 generator select bit 7 mask. */ +#define EVSYS_CHANNEL07_bp 7 /* Channel 0 generator select bit 7 position. */ + +/* EVSYS.CHANNEL1 bit masks and bit positions */ +#define EVSYS_CHANNEL1_gm 0xFF /* Channel 1 generator select group mask. */ +#define EVSYS_CHANNEL1_gp 0 /* Channel 1 generator select group position. */ +#define EVSYS_CHANNEL10_bm (1<<0) /* Channel 1 generator select bit 0 mask. */ +#define EVSYS_CHANNEL10_bp 0 /* Channel 1 generator select bit 0 position. */ +#define EVSYS_CHANNEL11_bm (1<<1) /* Channel 1 generator select bit 1 mask. */ +#define EVSYS_CHANNEL11_bp 1 /* Channel 1 generator select bit 1 position. */ +#define EVSYS_CHANNEL12_bm (1<<2) /* Channel 1 generator select bit 2 mask. */ +#define EVSYS_CHANNEL12_bp 2 /* Channel 1 generator select bit 2 position. */ +#define EVSYS_CHANNEL13_bm (1<<3) /* Channel 1 generator select bit 3 mask. */ +#define EVSYS_CHANNEL13_bp 3 /* Channel 1 generator select bit 3 position. */ +#define EVSYS_CHANNEL14_bm (1<<4) /* Channel 1 generator select bit 4 mask. */ +#define EVSYS_CHANNEL14_bp 4 /* Channel 1 generator select bit 4 position. */ +#define EVSYS_CHANNEL15_bm (1<<5) /* Channel 1 generator select bit 5 mask. */ +#define EVSYS_CHANNEL15_bp 5 /* Channel 1 generator select bit 5 position. */ +#define EVSYS_CHANNEL16_bm (1<<6) /* Channel 1 generator select bit 6 mask. */ +#define EVSYS_CHANNEL16_bp 6 /* Channel 1 generator select bit 6 position. */ +#define EVSYS_CHANNEL17_bm (1<<7) /* Channel 1 generator select bit 7 mask. */ +#define EVSYS_CHANNEL17_bp 7 /* Channel 1 generator select bit 7 position. */ + +/* EVSYS.CHANNEL2 bit masks and bit positions */ +#define EVSYS_CHANNEL2_gm 0xFF /* Channel 2 generator select group mask. */ +#define EVSYS_CHANNEL2_gp 0 /* Channel 2 generator select group position. */ +#define EVSYS_CHANNEL20_bm (1<<0) /* Channel 2 generator select bit 0 mask. */ +#define EVSYS_CHANNEL20_bp 0 /* Channel 2 generator select bit 0 position. */ +#define EVSYS_CHANNEL21_bm (1<<1) /* Channel 2 generator select bit 1 mask. */ +#define EVSYS_CHANNEL21_bp 1 /* Channel 2 generator select bit 1 position. */ +#define EVSYS_CHANNEL22_bm (1<<2) /* Channel 2 generator select bit 2 mask. */ +#define EVSYS_CHANNEL22_bp 2 /* Channel 2 generator select bit 2 position. */ +#define EVSYS_CHANNEL23_bm (1<<3) /* Channel 2 generator select bit 3 mask. */ +#define EVSYS_CHANNEL23_bp 3 /* Channel 2 generator select bit 3 position. */ +#define EVSYS_CHANNEL24_bm (1<<4) /* Channel 2 generator select bit 4 mask. */ +#define EVSYS_CHANNEL24_bp 4 /* Channel 2 generator select bit 4 position. */ +#define EVSYS_CHANNEL25_bm (1<<5) /* Channel 2 generator select bit 5 mask. */ +#define EVSYS_CHANNEL25_bp 5 /* Channel 2 generator select bit 5 position. */ +#define EVSYS_CHANNEL26_bm (1<<6) /* Channel 2 generator select bit 6 mask. */ +#define EVSYS_CHANNEL26_bp 6 /* Channel 2 generator select bit 6 position. */ +#define EVSYS_CHANNEL27_bm (1<<7) /* Channel 2 generator select bit 7 mask. */ +#define EVSYS_CHANNEL27_bp 7 /* Channel 2 generator select bit 7 position. */ + +/* EVSYS.CHANNEL3 bit masks and bit positions */ +#define EVSYS_CHANNEL3_gm 0xFF /* Channel 3 generator select group mask. */ +#define EVSYS_CHANNEL3_gp 0 /* Channel 3 generator select group position. */ +#define EVSYS_CHANNEL30_bm (1<<0) /* Channel 3 generator select bit 0 mask. */ +#define EVSYS_CHANNEL30_bp 0 /* Channel 3 generator select bit 0 position. */ +#define EVSYS_CHANNEL31_bm (1<<1) /* Channel 3 generator select bit 1 mask. */ +#define EVSYS_CHANNEL31_bp 1 /* Channel 3 generator select bit 1 position. */ +#define EVSYS_CHANNEL32_bm (1<<2) /* Channel 3 generator select bit 2 mask. */ +#define EVSYS_CHANNEL32_bp 2 /* Channel 3 generator select bit 2 position. */ +#define EVSYS_CHANNEL33_bm (1<<3) /* Channel 3 generator select bit 3 mask. */ +#define EVSYS_CHANNEL33_bp 3 /* Channel 3 generator select bit 3 position. */ +#define EVSYS_CHANNEL34_bm (1<<4) /* Channel 3 generator select bit 4 mask. */ +#define EVSYS_CHANNEL34_bp 4 /* Channel 3 generator select bit 4 position. */ +#define EVSYS_CHANNEL35_bm (1<<5) /* Channel 3 generator select bit 5 mask. */ +#define EVSYS_CHANNEL35_bp 5 /* Channel 3 generator select bit 5 position. */ +#define EVSYS_CHANNEL36_bm (1<<6) /* Channel 3 generator select bit 6 mask. */ +#define EVSYS_CHANNEL36_bp 6 /* Channel 3 generator select bit 6 position. */ +#define EVSYS_CHANNEL37_bm (1<<7) /* Channel 3 generator select bit 7 mask. */ +#define EVSYS_CHANNEL37_bp 7 /* Channel 3 generator select bit 7 position. */ + +/* EVSYS.CHANNEL4 bit masks and bit positions */ +#define EVSYS_CHANNEL4_gm 0xFF /* Channel 4 generator select group mask. */ +#define EVSYS_CHANNEL4_gp 0 /* Channel 4 generator select group position. */ +#define EVSYS_CHANNEL40_bm (1<<0) /* Channel 4 generator select bit 0 mask. */ +#define EVSYS_CHANNEL40_bp 0 /* Channel 4 generator select bit 0 position. */ +#define EVSYS_CHANNEL41_bm (1<<1) /* Channel 4 generator select bit 1 mask. */ +#define EVSYS_CHANNEL41_bp 1 /* Channel 4 generator select bit 1 position. */ +#define EVSYS_CHANNEL42_bm (1<<2) /* Channel 4 generator select bit 2 mask. */ +#define EVSYS_CHANNEL42_bp 2 /* Channel 4 generator select bit 2 position. */ +#define EVSYS_CHANNEL43_bm (1<<3) /* Channel 4 generator select bit 3 mask. */ +#define EVSYS_CHANNEL43_bp 3 /* Channel 4 generator select bit 3 position. */ +#define EVSYS_CHANNEL44_bm (1<<4) /* Channel 4 generator select bit 4 mask. */ +#define EVSYS_CHANNEL44_bp 4 /* Channel 4 generator select bit 4 position. */ +#define EVSYS_CHANNEL45_bm (1<<5) /* Channel 4 generator select bit 5 mask. */ +#define EVSYS_CHANNEL45_bp 5 /* Channel 4 generator select bit 5 position. */ +#define EVSYS_CHANNEL46_bm (1<<6) /* Channel 4 generator select bit 6 mask. */ +#define EVSYS_CHANNEL46_bp 6 /* Channel 4 generator select bit 6 position. */ +#define EVSYS_CHANNEL47_bm (1<<7) /* Channel 4 generator select bit 7 mask. */ +#define EVSYS_CHANNEL47_bp 7 /* Channel 4 generator select bit 7 position. */ + +/* EVSYS.CHANNEL5 bit masks and bit positions */ +#define EVSYS_CHANNEL5_gm 0xFF /* Channel 5 generator select group mask. */ +#define EVSYS_CHANNEL5_gp 0 /* Channel 5 generator select group position. */ +#define EVSYS_CHANNEL50_bm (1<<0) /* Channel 5 generator select bit 0 mask. */ +#define EVSYS_CHANNEL50_bp 0 /* Channel 5 generator select bit 0 position. */ +#define EVSYS_CHANNEL51_bm (1<<1) /* Channel 5 generator select bit 1 mask. */ +#define EVSYS_CHANNEL51_bp 1 /* Channel 5 generator select bit 1 position. */ +#define EVSYS_CHANNEL52_bm (1<<2) /* Channel 5 generator select bit 2 mask. */ +#define EVSYS_CHANNEL52_bp 2 /* Channel 5 generator select bit 2 position. */ +#define EVSYS_CHANNEL53_bm (1<<3) /* Channel 5 generator select bit 3 mask. */ +#define EVSYS_CHANNEL53_bp 3 /* Channel 5 generator select bit 3 position. */ +#define EVSYS_CHANNEL54_bm (1<<4) /* Channel 5 generator select bit 4 mask. */ +#define EVSYS_CHANNEL54_bp 4 /* Channel 5 generator select bit 4 position. */ +#define EVSYS_CHANNEL55_bm (1<<5) /* Channel 5 generator select bit 5 mask. */ +#define EVSYS_CHANNEL55_bp 5 /* Channel 5 generator select bit 5 position. */ +#define EVSYS_CHANNEL56_bm (1<<6) /* Channel 5 generator select bit 6 mask. */ +#define EVSYS_CHANNEL56_bp 6 /* Channel 5 generator select bit 6 position. */ +#define EVSYS_CHANNEL57_bm (1<<7) /* Channel 5 generator select bit 7 mask. */ +#define EVSYS_CHANNEL57_bp 7 /* Channel 5 generator select bit 7 position. */ + +/* EVSYS.CHANNEL6 bit masks and bit positions */ +#define EVSYS_CHANNEL6_gm 0xFF /* Channel 6 generator select group mask. */ +#define EVSYS_CHANNEL6_gp 0 /* Channel 6 generator select group position. */ +#define EVSYS_CHANNEL60_bm (1<<0) /* Channel 6 generator select bit 0 mask. */ +#define EVSYS_CHANNEL60_bp 0 /* Channel 6 generator select bit 0 position. */ +#define EVSYS_CHANNEL61_bm (1<<1) /* Channel 6 generator select bit 1 mask. */ +#define EVSYS_CHANNEL61_bp 1 /* Channel 6 generator select bit 1 position. */ +#define EVSYS_CHANNEL62_bm (1<<2) /* Channel 6 generator select bit 2 mask. */ +#define EVSYS_CHANNEL62_bp 2 /* Channel 6 generator select bit 2 position. */ +#define EVSYS_CHANNEL63_bm (1<<3) /* Channel 6 generator select bit 3 mask. */ +#define EVSYS_CHANNEL63_bp 3 /* Channel 6 generator select bit 3 position. */ +#define EVSYS_CHANNEL64_bm (1<<4) /* Channel 6 generator select bit 4 mask. */ +#define EVSYS_CHANNEL64_bp 4 /* Channel 6 generator select bit 4 position. */ +#define EVSYS_CHANNEL65_bm (1<<5) /* Channel 6 generator select bit 5 mask. */ +#define EVSYS_CHANNEL65_bp 5 /* Channel 6 generator select bit 5 position. */ +#define EVSYS_CHANNEL66_bm (1<<6) /* Channel 6 generator select bit 6 mask. */ +#define EVSYS_CHANNEL66_bp 6 /* Channel 6 generator select bit 6 position. */ +#define EVSYS_CHANNEL67_bm (1<<7) /* Channel 6 generator select bit 7 mask. */ +#define EVSYS_CHANNEL67_bp 7 /* Channel 6 generator select bit 7 position. */ + +/* EVSYS.CHANNEL7 bit masks and bit positions */ +#define EVSYS_CHANNEL7_gm 0xFF /* Channel 7 generator select group mask. */ +#define EVSYS_CHANNEL7_gp 0 /* Channel 7 generator select group position. */ +#define EVSYS_CHANNEL70_bm (1<<0) /* Channel 7 generator select bit 0 mask. */ +#define EVSYS_CHANNEL70_bp 0 /* Channel 7 generator select bit 0 position. */ +#define EVSYS_CHANNEL71_bm (1<<1) /* Channel 7 generator select bit 1 mask. */ +#define EVSYS_CHANNEL71_bp 1 /* Channel 7 generator select bit 1 position. */ +#define EVSYS_CHANNEL72_bm (1<<2) /* Channel 7 generator select bit 2 mask. */ +#define EVSYS_CHANNEL72_bp 2 /* Channel 7 generator select bit 2 position. */ +#define EVSYS_CHANNEL73_bm (1<<3) /* Channel 7 generator select bit 3 mask. */ +#define EVSYS_CHANNEL73_bp 3 /* Channel 7 generator select bit 3 position. */ +#define EVSYS_CHANNEL74_bm (1<<4) /* Channel 7 generator select bit 4 mask. */ +#define EVSYS_CHANNEL74_bp 4 /* Channel 7 generator select bit 4 position. */ +#define EVSYS_CHANNEL75_bm (1<<5) /* Channel 7 generator select bit 5 mask. */ +#define EVSYS_CHANNEL75_bp 5 /* Channel 7 generator select bit 5 position. */ +#define EVSYS_CHANNEL76_bm (1<<6) /* Channel 7 generator select bit 6 mask. */ +#define EVSYS_CHANNEL76_bp 6 /* Channel 7 generator select bit 6 position. */ +#define EVSYS_CHANNEL77_bm (1<<7) /* Channel 7 generator select bit 7 mask. */ +#define EVSYS_CHANNEL77_bp 7 /* Channel 7 generator select bit 7 position. */ + +/* EVSYS.CHANNEL8 bit masks and bit positions */ +#define EVSYS_CHANNEL8_gm 0xFF /* Channel 8 generator select group mask. */ +#define EVSYS_CHANNEL8_gp 0 /* Channel 8 generator select group position. */ +#define EVSYS_CHANNEL80_bm (1<<0) /* Channel 8 generator select bit 0 mask. */ +#define EVSYS_CHANNEL80_bp 0 /* Channel 8 generator select bit 0 position. */ +#define EVSYS_CHANNEL81_bm (1<<1) /* Channel 8 generator select bit 1 mask. */ +#define EVSYS_CHANNEL81_bp 1 /* Channel 8 generator select bit 1 position. */ +#define EVSYS_CHANNEL82_bm (1<<2) /* Channel 8 generator select bit 2 mask. */ +#define EVSYS_CHANNEL82_bp 2 /* Channel 8 generator select bit 2 position. */ +#define EVSYS_CHANNEL83_bm (1<<3) /* Channel 8 generator select bit 3 mask. */ +#define EVSYS_CHANNEL83_bp 3 /* Channel 8 generator select bit 3 position. */ +#define EVSYS_CHANNEL84_bm (1<<4) /* Channel 8 generator select bit 4 mask. */ +#define EVSYS_CHANNEL84_bp 4 /* Channel 8 generator select bit 4 position. */ +#define EVSYS_CHANNEL85_bm (1<<5) /* Channel 8 generator select bit 5 mask. */ +#define EVSYS_CHANNEL85_bp 5 /* Channel 8 generator select bit 5 position. */ +#define EVSYS_CHANNEL86_bm (1<<6) /* Channel 8 generator select bit 6 mask. */ +#define EVSYS_CHANNEL86_bp 6 /* Channel 8 generator select bit 6 position. */ +#define EVSYS_CHANNEL87_bm (1<<7) /* Channel 8 generator select bit 7 mask. */ +#define EVSYS_CHANNEL87_bp 7 /* Channel 8 generator select bit 7 position. */ + +/* EVSYS.CHANNEL9 bit masks and bit positions */ +#define EVSYS_CHANNEL9_gm 0xFF /* Channel 9 generator select group mask. */ +#define EVSYS_CHANNEL9_gp 0 /* Channel 9 generator select group position. */ +#define EVSYS_CHANNEL90_bm (1<<0) /* Channel 9 generator select bit 0 mask. */ +#define EVSYS_CHANNEL90_bp 0 /* Channel 9 generator select bit 0 position. */ +#define EVSYS_CHANNEL91_bm (1<<1) /* Channel 9 generator select bit 1 mask. */ +#define EVSYS_CHANNEL91_bp 1 /* Channel 9 generator select bit 1 position. */ +#define EVSYS_CHANNEL92_bm (1<<2) /* Channel 9 generator select bit 2 mask. */ +#define EVSYS_CHANNEL92_bp 2 /* Channel 9 generator select bit 2 position. */ +#define EVSYS_CHANNEL93_bm (1<<3) /* Channel 9 generator select bit 3 mask. */ +#define EVSYS_CHANNEL93_bp 3 /* Channel 9 generator select bit 3 position. */ +#define EVSYS_CHANNEL94_bm (1<<4) /* Channel 9 generator select bit 4 mask. */ +#define EVSYS_CHANNEL94_bp 4 /* Channel 9 generator select bit 4 position. */ +#define EVSYS_CHANNEL95_bm (1<<5) /* Channel 9 generator select bit 5 mask. */ +#define EVSYS_CHANNEL95_bp 5 /* Channel 9 generator select bit 5 position. */ +#define EVSYS_CHANNEL96_bm (1<<6) /* Channel 9 generator select bit 6 mask. */ +#define EVSYS_CHANNEL96_bp 6 /* Channel 9 generator select bit 6 position. */ +#define EVSYS_CHANNEL97_bm (1<<7) /* Channel 9 generator select bit 7 mask. */ +#define EVSYS_CHANNEL97_bp 7 /* Channel 9 generator select bit 7 position. */ + +/* EVSYS.USERCCLLUT0A bit masks and bit positions */ +#define EVSYS_USER_gm 0xFF /* User channel select group mask. */ +#define EVSYS_USER_gp 0 /* User channel select group position. */ +#define EVSYS_USER0_bm (1<<0) /* User channel select bit 0 mask. */ +#define EVSYS_USER0_bp 0 /* User channel select bit 0 position. */ +#define EVSYS_USER1_bm (1<<1) /* User channel select bit 1 mask. */ +#define EVSYS_USER1_bp 1 /* User channel select bit 1 position. */ +#define EVSYS_USER2_bm (1<<2) /* User channel select bit 2 mask. */ +#define EVSYS_USER2_bp 2 /* User channel select bit 2 position. */ +#define EVSYS_USER3_bm (1<<3) /* User channel select bit 3 mask. */ +#define EVSYS_USER3_bp 3 /* User channel select bit 3 position. */ +#define EVSYS_USER4_bm (1<<4) /* User channel select bit 4 mask. */ +#define EVSYS_USER4_bp 4 /* User channel select bit 4 position. */ +#define EVSYS_USER5_bm (1<<5) /* User channel select bit 5 mask. */ +#define EVSYS_USER5_bp 5 /* User channel select bit 5 position. */ +#define EVSYS_USER6_bm (1<<6) /* User channel select bit 6 mask. */ +#define EVSYS_USER6_bp 6 /* User channel select bit 6 position. */ +#define EVSYS_USER7_bm (1<<7) /* User channel select bit 7 mask. */ +#define EVSYS_USER7_bp 7 /* User channel select bit 7 position. */ + +/* EVSYS.USERCCLLUT0B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT1A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT1B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT2A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT2B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT3A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT3B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT4A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT4B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT5A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT5B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERADC0START bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERPTCSTART bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTC bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTD bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTE bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTF bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTG bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART0IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART1IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART2IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART3IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART4IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART5IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA0CNTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA0CNTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA1CNTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA1CNTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB0CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB0COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB1CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB1COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB2CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB2COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB3CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB3COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB4CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB4COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCD0INPUTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCD0INPUTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEROSCTEST bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_CLKSEL_gm 0x07 /* Frequency Select group mask. */ +#define FUSE_CLKSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_CLKSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_CLKSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_CLKSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_CLKSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_CLKSEL2_bm (1<<2) /* Frequency Select bit 2 mask. */ +#define FUSE_CLKSEL2_bp 2 /* Frequency Select bit 2 position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSEL_bm 0x20 /* CRC Select bit mask. */ +#define FUSE_CRCSEL_bp 5 /* CRC Select bit position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCK - Lockbits */ +/* LOCK.KEY bit masks and bit positions */ +#define LOCK_KEY_gm 0xFFFFFFFF /* Lock Key group mask. */ +#define LOCK_KEY_gp 0 /* Lock Key group position. */ +#define LOCK_KEY0_bm (1<<0) /* Lock Key bit 0 mask. */ +#define LOCK_KEY0_bp 0 /* Lock Key bit 0 position. */ +#define LOCK_KEY1_bm (1<<1) /* Lock Key bit 1 mask. */ +#define LOCK_KEY1_bp 1 /* Lock Key bit 1 position. */ +#define LOCK_KEY2_bm (1<<2) /* Lock Key bit 2 mask. */ +#define LOCK_KEY2_bp 2 /* Lock Key bit 2 position. */ +#define LOCK_KEY3_bm (1<<3) /* Lock Key bit 3 mask. */ +#define LOCK_KEY3_bp 3 /* Lock Key bit 3 position. */ +#define LOCK_KEY4_bm (1<<4) /* Lock Key bit 4 mask. */ +#define LOCK_KEY4_bp 4 /* Lock Key bit 4 position. */ +#define LOCK_KEY5_bm (1<<5) /* Lock Key bit 5 mask. */ +#define LOCK_KEY5_bp 5 /* Lock Key bit 5 position. */ +#define LOCK_KEY6_bm (1<<6) /* Lock Key bit 6 mask. */ +#define LOCK_KEY6_bp 6 /* Lock Key bit 6 position. */ +#define LOCK_KEY7_bm (1<<7) /* Lock Key bit 7 mask. */ +#define LOCK_KEY7_bp 7 /* Lock Key bit 7 position. */ +#define LOCK_KEY8_bm (1<<8) /* Lock Key bit 8 mask. */ +#define LOCK_KEY8_bp 8 /* Lock Key bit 8 position. */ +#define LOCK_KEY9_bm (1<<9) /* Lock Key bit 9 mask. */ +#define LOCK_KEY9_bp 9 /* Lock Key bit 9 position. */ +#define LOCK_KEY10_bm (1<<10) /* Lock Key bit 10 mask. */ +#define LOCK_KEY10_bp 10 /* Lock Key bit 10 position. */ +#define LOCK_KEY11_bm (1<<11) /* Lock Key bit 11 mask. */ +#define LOCK_KEY11_bp 11 /* Lock Key bit 11 position. */ +#define LOCK_KEY12_bm (1<<12) /* Lock Key bit 12 mask. */ +#define LOCK_KEY12_bp 12 /* Lock Key bit 12 position. */ +#define LOCK_KEY13_bm (1<<13) /* Lock Key bit 13 mask. */ +#define LOCK_KEY13_bp 13 /* Lock Key bit 13 position. */ +#define LOCK_KEY14_bm (1<<14) /* Lock Key bit 14 mask. */ +#define LOCK_KEY14_bp 14 /* Lock Key bit 14 position. */ +#define LOCK_KEY15_bm (1<<15) /* Lock Key bit 15 mask. */ +#define LOCK_KEY15_bp 15 /* Lock Key bit 15 position. */ +#define LOCK_KEY16_bm (1<<16) /* Lock Key bit 16 mask. */ +#define LOCK_KEY16_bp 16 /* Lock Key bit 16 position. */ +#define LOCK_KEY17_bm (1<<17) /* Lock Key bit 17 mask. */ +#define LOCK_KEY17_bp 17 /* Lock Key bit 17 position. */ +#define LOCK_KEY18_bm (1<<18) /* Lock Key bit 18 mask. */ +#define LOCK_KEY18_bp 18 /* Lock Key bit 18 position. */ +#define LOCK_KEY19_bm (1<<19) /* Lock Key bit 19 mask. */ +#define LOCK_KEY19_bp 19 /* Lock Key bit 19 position. */ +#define LOCK_KEY20_bm (1<<20) /* Lock Key bit 20 mask. */ +#define LOCK_KEY20_bp 20 /* Lock Key bit 20 position. */ +#define LOCK_KEY21_bm (1<<21) /* Lock Key bit 21 mask. */ +#define LOCK_KEY21_bp 21 /* Lock Key bit 21 position. */ +#define LOCK_KEY22_bm (1<<22) /* Lock Key bit 22 mask. */ +#define LOCK_KEY22_bp 22 /* Lock Key bit 22 position. */ +#define LOCK_KEY23_bm (1<<23) /* Lock Key bit 23 mask. */ +#define LOCK_KEY23_bp 23 /* Lock Key bit 23 position. */ +#define LOCK_KEY24_bm (1<<24) /* Lock Key bit 24 mask. */ +#define LOCK_KEY24_bp 24 /* Lock Key bit 24 position. */ +#define LOCK_KEY25_bm (1<<25) /* Lock Key bit 25 mask. */ +#define LOCK_KEY25_bp 25 /* Lock Key bit 25 position. */ +#define LOCK_KEY26_bm (1<<26) /* Lock Key bit 26 mask. */ +#define LOCK_KEY26_bp 26 /* Lock Key bit 26 position. */ +#define LOCK_KEY27_bm (1<<27) /* Lock Key bit 27 mask. */ +#define LOCK_KEY27_bp 27 /* Lock Key bit 27 position. */ +#define LOCK_KEY28_bm (1<<28) /* Lock Key bit 28 mask. */ +#define LOCK_KEY28_bp 28 /* Lock Key bit 28 position. */ +#define LOCK_KEY29_bm (1<<29) /* Lock Key bit 29 mask. */ +#define LOCK_KEY29_bp 29 /* Lock Key bit 29 position. */ +#define LOCK_KEY30_bm (1<<30) /* Lock Key bit 30 mask. */ +#define LOCK_KEY30_bp 30 /* Lock Key bit 30 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x7F /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ +#define NVMCTRL_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVMCTRL_CMD3_bp 3 /* Command bit 3 position. */ +#define NVMCTRL_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVMCTRL_CMD4_bp 4 /* Command bit 4 position. */ +#define NVMCTRL_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVMCTRL_CMD5_bp 5 /* Command bit 5 position. */ +#define NVMCTRL_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVMCTRL_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APPCODEWP_bm 0x01 /* Application Code Write Protect bit mask. */ +#define NVMCTRL_APPCODEWP_bp 0 /* Application Code Write Protect bit position. */ +#define NVMCTRL_BOOTRP_bm 0x02 /* Boot Read Protect bit mask. */ +#define NVMCTRL_BOOTRP_bp 1 /* Boot Read Protect bit position. */ +#define NVMCTRL_APPDATAWP_bm 0x04 /* Application Data Write Protect bit mask. */ +#define NVMCTRL_APPDATAWP_bp 2 /* Application Data Write Protect bit position. */ +#define NVMCTRL_FLMAP_gm 0x30 /* Flash Mapping in Data space group mask. */ +#define NVMCTRL_FLMAP_gp 4 /* Flash Mapping in Data space group position. */ +#define NVMCTRL_FLMAP0_bm (1<<4) /* Flash Mapping in Data space bit 0 mask. */ +#define NVMCTRL_FLMAP0_bp 4 /* Flash Mapping in Data space bit 0 position. */ +#define NVMCTRL_FLMAP1_bm (1<<5) /* Flash Mapping in Data space bit 1 mask. */ +#define NVMCTRL_FLMAP1_bp 5 /* Flash Mapping in Data space bit 1 position. */ +#define NVMCTRL_FLMAPLOCK_bm 0x80 /* Flash Mapping Lock bit mask. */ +#define NVMCTRL_FLMAPLOCK_bp 7 /* Flash Mapping Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_ERROR_gm 0x70 /* Write error group mask. */ +#define NVMCTRL_ERROR_gp 4 /* Write error group position. */ +#define NVMCTRL_ERROR0_bm (1<<4) /* Write error bit 0 mask. */ +#define NVMCTRL_ERROR0_bp 4 /* Write error bit 0 position. */ +#define NVMCTRL_ERROR1_bm (1<<5) /* Write error bit 1 mask. */ +#define NVMCTRL_ERROR1_bp 5 /* Write error bit 1 position. */ +#define NVMCTRL_ERROR2_bm (1<<6) /* Write error bit 2 mask. */ +#define NVMCTRL_ERROR2_bp 6 /* Write error bit 2 position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PORTCTRL bit masks and bit positions */ +#define PORT_SRL_bm 0x01 /* Slew Rate Limit Enable bit mask. */ +#define PORT_SRL_bp 0 /* Slew Rate Limit Enable bit position. */ + +/* PORT.PINCONFIG bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PINCTRLUPD bit masks and bit positions */ +#define PORT_PINCTRLUPD_gm 0xFF /* Pin control update mask group mask. */ +#define PORT_PINCTRLUPD_gp 0 /* Pin control update mask group position. */ +#define PORT_PINCTRLUPD0_bm (1<<0) /* Pin control update mask bit 0 mask. */ +#define PORT_PINCTRLUPD0_bp 0 /* Pin control update mask bit 0 position. */ +#define PORT_PINCTRLUPD1_bm (1<<1) /* Pin control update mask bit 1 mask. */ +#define PORT_PINCTRLUPD1_bp 1 /* Pin control update mask bit 1 position. */ +#define PORT_PINCTRLUPD2_bm (1<<2) /* Pin control update mask bit 2 mask. */ +#define PORT_PINCTRLUPD2_bp 2 /* Pin control update mask bit 2 position. */ +#define PORT_PINCTRLUPD3_bm (1<<3) /* Pin control update mask bit 3 mask. */ +#define PORT_PINCTRLUPD3_bp 3 /* Pin control update mask bit 3 position. */ +#define PORT_PINCTRLUPD4_bm (1<<4) /* Pin control update mask bit 4 mask. */ +#define PORT_PINCTRLUPD4_bp 4 /* Pin control update mask bit 4 position. */ +#define PORT_PINCTRLUPD5_bm (1<<5) /* Pin control update mask bit 5 mask. */ +#define PORT_PINCTRLUPD5_bp 5 /* Pin control update mask bit 5 position. */ +#define PORT_PINCTRLUPD6_bm (1<<6) /* Pin control update mask bit 6 mask. */ +#define PORT_PINCTRLUPD6_bp 6 /* Pin control update mask bit 6 position. */ +#define PORT_PINCTRLUPD7_bm (1<<7) /* Pin control update mask bit 7 mask. */ +#define PORT_PINCTRLUPD7_bp 7 /* Pin control update mask bit 7 position. */ + +/* PORT.PINCTRLSET bit masks and bit positions */ +#define PORT_PINCTRLSET_gm 0xFF /* Pin control set mask group mask. */ +#define PORT_PINCTRLSET_gp 0 /* Pin control set mask group position. */ +#define PORT_PINCTRLSET0_bm (1<<0) /* Pin control set mask bit 0 mask. */ +#define PORT_PINCTRLSET0_bp 0 /* Pin control set mask bit 0 position. */ +#define PORT_PINCTRLSET1_bm (1<<1) /* Pin control set mask bit 1 mask. */ +#define PORT_PINCTRLSET1_bp 1 /* Pin control set mask bit 1 position. */ +#define PORT_PINCTRLSET2_bm (1<<2) /* Pin control set mask bit 2 mask. */ +#define PORT_PINCTRLSET2_bp 2 /* Pin control set mask bit 2 position. */ +#define PORT_PINCTRLSET3_bm (1<<3) /* Pin control set mask bit 3 mask. */ +#define PORT_PINCTRLSET3_bp 3 /* Pin control set mask bit 3 position. */ +#define PORT_PINCTRLSET4_bm (1<<4) /* Pin control set mask bit 4 mask. */ +#define PORT_PINCTRLSET4_bp 4 /* Pin control set mask bit 4 position. */ +#define PORT_PINCTRLSET5_bm (1<<5) /* Pin control set mask bit 5 mask. */ +#define PORT_PINCTRLSET5_bp 5 /* Pin control set mask bit 5 position. */ +#define PORT_PINCTRLSET6_bm (1<<6) /* Pin control set mask bit 6 mask. */ +#define PORT_PINCTRLSET6_bp 6 /* Pin control set mask bit 6 position. */ +#define PORT_PINCTRLSET7_bm (1<<7) /* Pin control set mask bit 7 mask. */ +#define PORT_PINCTRLSET7_bp 7 /* Pin control set mask bit 7 position. */ + +/* PORT.PINCTRLCLR bit masks and bit positions */ +#define PORT_PINCTRLCLR_gm 0xFF /* Pin control clear mask group mask. */ +#define PORT_PINCTRLCLR_gp 0 /* Pin control clear mask group position. */ +#define PORT_PINCTRLCLR0_bm (1<<0) /* Pin control clear mask bit 0 mask. */ +#define PORT_PINCTRLCLR0_bp 0 /* Pin control clear mask bit 0 position. */ +#define PORT_PINCTRLCLR1_bm (1<<1) /* Pin control clear mask bit 1 mask. */ +#define PORT_PINCTRLCLR1_bp 1 /* Pin control clear mask bit 1 position. */ +#define PORT_PINCTRLCLR2_bm (1<<2) /* Pin control clear mask bit 2 mask. */ +#define PORT_PINCTRLCLR2_bp 2 /* Pin control clear mask bit 2 position. */ +#define PORT_PINCTRLCLR3_bm (1<<3) /* Pin control clear mask bit 3 mask. */ +#define PORT_PINCTRLCLR3_bp 3 /* Pin control clear mask bit 3 position. */ +#define PORT_PINCTRLCLR4_bm (1<<4) /* Pin control clear mask bit 4 mask. */ +#define PORT_PINCTRLCLR4_bp 4 /* Pin control clear mask bit 4 position. */ +#define PORT_PINCTRLCLR5_bm (1<<5) /* Pin control clear mask bit 5 mask. */ +#define PORT_PINCTRLCLR5_bp 5 /* Pin control clear mask bit 5 position. */ +#define PORT_PINCTRLCLR6_bm (1<<6) /* Pin control clear mask bit 6 mask. */ +#define PORT_PINCTRLCLR6_bp 6 /* Pin control clear mask bit 6 position. */ +#define PORT_PINCTRLCLR7_bm (1<<7) /* Pin control clear mask bit 7 mask. */ +#define PORT_PINCTRLCLR7_bp 7 /* Pin control clear mask bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.EVSYSROUTEA bit masks and bit positions */ +#define PORTMUX_EVOUTA_bm 0x01 /* Event Output A bit mask. */ +#define PORTMUX_EVOUTA_bp 0 /* Event Output A bit position. */ +#define PORTMUX_EVOUTB_bm 0x02 /* Event Output B bit mask. */ +#define PORTMUX_EVOUTB_bp 1 /* Event Output B bit position. */ +#define PORTMUX_EVOUTC_bm 0x04 /* Event Output C bit mask. */ +#define PORTMUX_EVOUTC_bp 2 /* Event Output C bit position. */ +#define PORTMUX_EVOUTD_bm 0x08 /* Event Output D bit mask. */ +#define PORTMUX_EVOUTD_bp 3 /* Event Output D bit position. */ +#define PORTMUX_EVOUTE_bm 0x10 /* Event Output E bit mask. */ +#define PORTMUX_EVOUTE_bp 4 /* Event Output E bit position. */ +#define PORTMUX_EVOUTF_bm 0x20 /* Event Output F bit mask. */ +#define PORTMUX_EVOUTF_bp 5 /* Event Output F bit position. */ +#define PORTMUX_EVOUTG_bm 0x40 /* Event Output G bit mask. */ +#define PORTMUX_EVOUTG_bp 6 /* Event Output G bit position. */ + +/* PORTMUX.CCLROUTEA bit masks and bit positions */ +#define PORTMUX_LUT0_bm 0x01 /* CCL Look-Up Table 0 Signals bit mask. */ +#define PORTMUX_LUT0_bp 0 /* CCL Look-Up Table 0 Signals bit position. */ +#define PORTMUX_LUT1_bm 0x02 /* CCL Look-Up Table 1 Signals bit mask. */ +#define PORTMUX_LUT1_bp 1 /* CCL Look-Up Table 1 Signals bit position. */ +#define PORTMUX_LUT2_bm 0x04 /* CCL Look-Up Table 2 Signals bit mask. */ +#define PORTMUX_LUT2_bp 2 /* CCL Look-Up Table 2 Signals bit position. */ +#define PORTMUX_LUT3_bm 0x08 /* CCL Look-Up Table 3 Signals bit mask. */ +#define PORTMUX_LUT3_bp 3 /* CCL Look-Up Table 3 Signals bit position. */ +#define PORTMUX_LUT4_bm 0x10 /* CCL Look-Up Table 4 Signals bit mask. */ +#define PORTMUX_LUT4_bp 4 /* CCL Look-Up Table 4 Signals bit position. */ +#define PORTMUX_LUT5_bm 0x20 /* CCL Look-Up Table 5 Signals bit mask. */ +#define PORTMUX_LUT5_bp 5 /* CCL Look-Up Table 5 Signals bit position. */ + +/* PORTMUX.USARTROUTEA bit masks and bit positions */ +#define PORTMUX_USART0_gm 0x03 /* USART0 Signals group mask. */ +#define PORTMUX_USART0_gp 0 /* USART0 Signals group position. */ +#define PORTMUX_USART00_bm (1<<0) /* USART0 Signals bit 0 mask. */ +#define PORTMUX_USART00_bp 0 /* USART0 Signals bit 0 position. */ +#define PORTMUX_USART01_bm (1<<1) /* USART0 Signals bit 1 mask. */ +#define PORTMUX_USART01_bp 1 /* USART0 Signals bit 1 position. */ +#define PORTMUX_USART1_gm 0x0C /* USART1 Signals group mask. */ +#define PORTMUX_USART1_gp 2 /* USART1 Signals group position. */ +#define PORTMUX_USART10_bm (1<<2) /* USART1 Signals bit 0 mask. */ +#define PORTMUX_USART10_bp 2 /* USART1 Signals bit 0 position. */ +#define PORTMUX_USART11_bm (1<<3) /* USART1 Signals bit 1 mask. */ +#define PORTMUX_USART11_bp 3 /* USART1 Signals bit 1 position. */ +#define PORTMUX_USART2_gm 0x30 /* USART2 Signals group mask. */ +#define PORTMUX_USART2_gp 4 /* USART2 Signals group position. */ +#define PORTMUX_USART20_bm (1<<4) /* USART2 Signals bit 0 mask. */ +#define PORTMUX_USART20_bp 4 /* USART2 Signals bit 0 position. */ +#define PORTMUX_USART21_bm (1<<5) /* USART2 Signals bit 1 mask. */ +#define PORTMUX_USART21_bp 5 /* USART2 Signals bit 1 position. */ + + +/* PORTMUX.SPIROUTEA bit masks and bit positions */ +#define PORTMUX_SPI0_gm 0x03 /* SPI0 Signals group mask. */ +#define PORTMUX_SPI0_gp 0 /* SPI0 Signals group position. */ +#define PORTMUX_SPI00_bm (1<<0) /* SPI0 Signals bit 0 mask. */ +#define PORTMUX_SPI00_bp 0 /* SPI0 Signals bit 0 position. */ +#define PORTMUX_SPI01_bm (1<<1) /* SPI0 Signals bit 1 mask. */ +#define PORTMUX_SPI01_bp 1 /* SPI0 Signals bit 1 position. */ +#define PORTMUX_SPI1_gm 0x0C /* SPI1 Signals group mask. */ +#define PORTMUX_SPI1_gp 2 /* SPI1 Signals group position. */ +#define PORTMUX_SPI10_bm (1<<2) /* SPI1 Signals bit 0 mask. */ +#define PORTMUX_SPI10_bp 2 /* SPI1 Signals bit 0 position. */ +#define PORTMUX_SPI11_bm (1<<3) /* SPI1 Signals bit 1 mask. */ +#define PORTMUX_SPI11_bp 3 /* SPI1 Signals bit 1 position. */ + +/* PORTMUX.TWIROUTEA bit masks and bit positions */ +#define PORTMUX_TWI0_gm 0x03 /* TWI0 Signals group mask. */ +#define PORTMUX_TWI0_gp 0 /* TWI0 Signals group position. */ +#define PORTMUX_TWI00_bm (1<<0) /* TWI0 Signals bit 0 mask. */ +#define PORTMUX_TWI00_bp 0 /* TWI0 Signals bit 0 position. */ +#define PORTMUX_TWI01_bm (1<<1) /* TWI0 Signals bit 1 mask. */ +#define PORTMUX_TWI01_bp 1 /* TWI0 Signals bit 1 position. */ + +/* PORTMUX.TCAROUTEA bit masks and bit positions */ +#define PORTMUX_TCA0_gm 0x07 /* TCA0 Signals group mask. */ +#define PORTMUX_TCA0_gp 0 /* TCA0 Signals group position. */ +#define PORTMUX_TCA00_bm (1<<0) /* TCA0 Signals bit 0 mask. */ +#define PORTMUX_TCA00_bp 0 /* TCA0 Signals bit 0 position. */ +#define PORTMUX_TCA01_bm (1<<1) /* TCA0 Signals bit 1 mask. */ +#define PORTMUX_TCA01_bp 1 /* TCA0 Signals bit 1 position. */ +#define PORTMUX_TCA02_bm (1<<2) /* TCA0 Signals bit 2 mask. */ +#define PORTMUX_TCA02_bp 2 /* TCA0 Signals bit 2 position. */ + +/* PORTMUX.TCBROUTEA bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* TCB0 Output bit mask. */ +#define PORTMUX_TCB0_bp 0 /* TCB0 Output bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* TCB1 Output bit mask. */ +#define PORTMUX_TCB1_bp 1 /* TCB1 Output bit position. */ +#define PORTMUX_TCB2_bm 0x04 /* TCB2 Output bit mask. */ +#define PORTMUX_TCB2_bp 2 /* TCB2 Output bit position. */ + +/* PORTMUX.TCDROUTEA bit masks and bit positions */ +#define PORTMUX_TCD0_gm 0x07 /* TCD0 Signals group mask. */ +#define PORTMUX_TCD0_gp 0 /* TCD0 Signals group position. */ +#define PORTMUX_TCD00_bm (1<<0) /* TCD0 Signals bit 0 mask. */ +#define PORTMUX_TCD00_bp 0 /* TCD0 Signals bit 0 position. */ +#define PORTMUX_TCD01_bm (1<<1) /* TCD0 Signals bit 1 mask. */ +#define PORTMUX_TCD01_bp 1 /* TCD0 Signals bit 1 position. */ +#define PORTMUX_TCD02_bm (1<<2) /* TCD0 Signals bit 2 mask. */ +#define PORTMUX_TCD02_bp 2 /* TCD0 Signals bit 2 position. */ + +/* PORTMUX.ACROUTEA bit masks and bit positions */ +#define PORTMUX_AC0_bm 0x01 /* Analog Comparator 0 Output bit mask. */ +#define PORTMUX_AC0_bp 0 /* Analog Comparator 0 Output bit position. */ +#define PORTMUX_AC1_bm 0x02 /* Analog Comparator 1 Output bit mask. */ +#define PORTMUX_AC1_bp 1 /* Analog Comparator 1 Output bit position. */ +#define PORTMUX_AC2_bm 0x04 /* Analog Comparator 2 Output bit mask. */ +#define PORTMUX_AC2_bp 2 /* Analog Comparator 2 Output bit position. */ + +/* PORTMUX.ZCDROUTEA bit masks and bit positions */ +#define PORTMUX_ZCD0_bm 0x01 /* Zero Cross Detector 0 Output bit mask. */ +#define PORTMUX_ZCD0_bp 0 /* Zero Cross Detector 0 Output bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRST_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRST_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_CORREN_bm 0x04 /* Correction enable bit mask. */ +#define RTC_CORREN_bp 2 /* Correction enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_ERROR_gm 0x7F /* Error Correction Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Correction Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Correction Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Correction Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Correction Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Correction Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Correction Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Correction Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Correction Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Correction Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Correction Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Correction Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Correction Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Correction Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Correction Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Correction Value bit 6 position. */ +#define RTC_SIGN_bm 0x80 /* Error Correction Sign Bit bit mask. */ +#define RTC_SIGN_bp 7 /* Error Correction Sign Bit bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + +/* SIGROW - Signature row */ +/* SIGROW.TEMPSENSE0 bit masks and bit positions */ +#define SIGROW_TEMPSENSE0_gm 0xFFFF /* Temperature Calibration 0 group mask. */ +#define SIGROW_TEMPSENSE0_gp 0 /* Temperature Calibration 0 group position. */ +#define SIGROW_TEMPSENSE00_bm (1<<0) /* Temperature Calibration 0 bit 0 mask. */ +#define SIGROW_TEMPSENSE00_bp 0 /* Temperature Calibration 0 bit 0 position. */ +#define SIGROW_TEMPSENSE01_bm (1<<1) /* Temperature Calibration 0 bit 1 mask. */ +#define SIGROW_TEMPSENSE01_bp 1 /* Temperature Calibration 0 bit 1 position. */ +#define SIGROW_TEMPSENSE02_bm (1<<2) /* Temperature Calibration 0 bit 2 mask. */ +#define SIGROW_TEMPSENSE02_bp 2 /* Temperature Calibration 0 bit 2 position. */ +#define SIGROW_TEMPSENSE03_bm (1<<3) /* Temperature Calibration 0 bit 3 mask. */ +#define SIGROW_TEMPSENSE03_bp 3 /* Temperature Calibration 0 bit 3 position. */ +#define SIGROW_TEMPSENSE04_bm (1<<4) /* Temperature Calibration 0 bit 4 mask. */ +#define SIGROW_TEMPSENSE04_bp 4 /* Temperature Calibration 0 bit 4 position. */ +#define SIGROW_TEMPSENSE05_bm (1<<5) /* Temperature Calibration 0 bit 5 mask. */ +#define SIGROW_TEMPSENSE05_bp 5 /* Temperature Calibration 0 bit 5 position. */ +#define SIGROW_TEMPSENSE06_bm (1<<6) /* Temperature Calibration 0 bit 6 mask. */ +#define SIGROW_TEMPSENSE06_bp 6 /* Temperature Calibration 0 bit 6 position. */ +#define SIGROW_TEMPSENSE07_bm (1<<7) /* Temperature Calibration 0 bit 7 mask. */ +#define SIGROW_TEMPSENSE07_bp 7 /* Temperature Calibration 0 bit 7 position. */ +#define SIGROW_TEMPSENSE08_bm (1<<8) /* Temperature Calibration 0 bit 8 mask. */ +#define SIGROW_TEMPSENSE08_bp 8 /* Temperature Calibration 0 bit 8 position. */ +#define SIGROW_TEMPSENSE09_bm (1<<9) /* Temperature Calibration 0 bit 9 mask. */ +#define SIGROW_TEMPSENSE09_bp 9 /* Temperature Calibration 0 bit 9 position. */ +#define SIGROW_TEMPSENSE010_bm (1<<10) /* Temperature Calibration 0 bit 10 mask. */ +#define SIGROW_TEMPSENSE010_bp 10 /* Temperature Calibration 0 bit 10 position. */ +#define SIGROW_TEMPSENSE011_bm (1<<11) /* Temperature Calibration 0 bit 11 mask. */ +#define SIGROW_TEMPSENSE011_bp 11 /* Temperature Calibration 0 bit 11 position. */ +#define SIGROW_TEMPSENSE012_bm (1<<12) /* Temperature Calibration 0 bit 12 mask. */ +#define SIGROW_TEMPSENSE012_bp 12 /* Temperature Calibration 0 bit 12 position. */ +#define SIGROW_TEMPSENSE013_bm (1<<13) /* Temperature Calibration 0 bit 13 mask. */ +#define SIGROW_TEMPSENSE013_bp 13 /* Temperature Calibration 0 bit 13 position. */ +#define SIGROW_TEMPSENSE014_bm (1<<14) /* Temperature Calibration 0 bit 14 mask. */ +#define SIGROW_TEMPSENSE014_bp 14 /* Temperature Calibration 0 bit 14 position. */ +#define SIGROW_TEMPSENSE015_bm (1<<15) /* Temperature Calibration 0 bit 15 mask. */ +#define SIGROW_TEMPSENSE015_bp 15 /* Temperature Calibration 0 bit 15 position. */ + +/* SIGROW.TEMPSENSE1 bit masks and bit positions */ +#define SIGROW_TEMPSENSE1_gm 0xFFFF /* Temperature Calibration 1 group mask. */ +#define SIGROW_TEMPSENSE1_gp 0 /* Temperature Calibration 1 group position. */ +#define SIGROW_TEMPSENSE10_bm (1<<0) /* Temperature Calibration 1 bit 0 mask. */ +#define SIGROW_TEMPSENSE10_bp 0 /* Temperature Calibration 1 bit 0 position. */ +#define SIGROW_TEMPSENSE11_bm (1<<1) /* Temperature Calibration 1 bit 1 mask. */ +#define SIGROW_TEMPSENSE11_bp 1 /* Temperature Calibration 1 bit 1 position. */ +#define SIGROW_TEMPSENSE12_bm (1<<2) /* Temperature Calibration 1 bit 2 mask. */ +#define SIGROW_TEMPSENSE12_bp 2 /* Temperature Calibration 1 bit 2 position. */ +#define SIGROW_TEMPSENSE13_bm (1<<3) /* Temperature Calibration 1 bit 3 mask. */ +#define SIGROW_TEMPSENSE13_bp 3 /* Temperature Calibration 1 bit 3 position. */ +#define SIGROW_TEMPSENSE14_bm (1<<4) /* Temperature Calibration 1 bit 4 mask. */ +#define SIGROW_TEMPSENSE14_bp 4 /* Temperature Calibration 1 bit 4 position. */ +#define SIGROW_TEMPSENSE15_bm (1<<5) /* Temperature Calibration 1 bit 5 mask. */ +#define SIGROW_TEMPSENSE15_bp 5 /* Temperature Calibration 1 bit 5 position. */ +#define SIGROW_TEMPSENSE16_bm (1<<6) /* Temperature Calibration 1 bit 6 mask. */ +#define SIGROW_TEMPSENSE16_bp 6 /* Temperature Calibration 1 bit 6 position. */ +#define SIGROW_TEMPSENSE17_bm (1<<7) /* Temperature Calibration 1 bit 7 mask. */ +#define SIGROW_TEMPSENSE17_bp 7 /* Temperature Calibration 1 bit 7 position. */ +#define SIGROW_TEMPSENSE18_bm (1<<8) /* Temperature Calibration 1 bit 8 mask. */ +#define SIGROW_TEMPSENSE18_bp 8 /* Temperature Calibration 1 bit 8 position. */ +#define SIGROW_TEMPSENSE19_bm (1<<9) /* Temperature Calibration 1 bit 9 mask. */ +#define SIGROW_TEMPSENSE19_bp 9 /* Temperature Calibration 1 bit 9 position. */ +#define SIGROW_TEMPSENSE110_bm (1<<10) /* Temperature Calibration 1 bit 10 mask. */ +#define SIGROW_TEMPSENSE110_bp 10 /* Temperature Calibration 1 bit 10 position. */ +#define SIGROW_TEMPSENSE111_bm (1<<11) /* Temperature Calibration 1 bit 11 mask. */ +#define SIGROW_TEMPSENSE111_bp 11 /* Temperature Calibration 1 bit 11 position. */ +#define SIGROW_TEMPSENSE112_bm (1<<12) /* Temperature Calibration 1 bit 12 mask. */ +#define SIGROW_TEMPSENSE112_bp 12 /* Temperature Calibration 1 bit 12 position. */ +#define SIGROW_TEMPSENSE113_bm (1<<13) /* Temperature Calibration 1 bit 13 mask. */ +#define SIGROW_TEMPSENSE113_bp 13 /* Temperature Calibration 1 bit 13 position. */ +#define SIGROW_TEMPSENSE114_bm (1<<14) /* Temperature Calibration 1 bit 14 mask. */ +#define SIGROW_TEMPSENSE114_bp 14 /* Temperature Calibration 1 bit 14 position. */ +#define SIGROW_TEMPSENSE115_bm (1<<15) /* Temperature Calibration 1 bit 15 mask. */ +#define SIGROW_TEMPSENSE115_bp 15 /* Temperature Calibration 1 bit 15 position. */ + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SLPCTRL.VREGCTRL bit masks and bit positions */ +#define SLPCTRL_PMODE_gm 0x07 /* Performance Mode group mask. */ +#define SLPCTRL_PMODE_gp 0 /* Performance Mode group position. */ +#define SLPCTRL_PMODE0_bm (1<<0) /* Performance Mode bit 0 mask. */ +#define SLPCTRL_PMODE0_bp 0 /* Performance Mode bit 0 position. */ +#define SLPCTRL_PMODE1_bm (1<<1) /* Performance Mode bit 1 mask. */ +#define SLPCTRL_PMODE1_bp 1 /* Performance Mode bit 1 position. */ +#define SLPCTRL_PMODE2_bm (1<<2) /* Performance Mode bit 2 mask. */ +#define SLPCTRL_PMODE2_bp 2 /* Performance Mode bit 2 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Mode Wait for Receive bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Mode Wait for Receive bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.OCDMSTATUS bit masks and bit positions */ +#define SYSCFG_OCDMR_bm 0x01 /* OCD Message Read bit mask. */ +#define SYSCFG_OCDMR_bp 0 /* OCD Message Read bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ +#define TCA_SINGLE_RUNSTDBY_bm 0x80 /* Run in Standby bit mask. */ +#define TCA_SINGLE_RUNSTDBY_bp 7 /* Run in Standby bit position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTAEI_bm 0x01 /* Count on Event Input A bit mask. */ +#define TCA_SINGLE_CNTAEI_bp 0 /* Count on Event Input A bit position. */ +#define TCA_SINGLE_EVACTA_gm 0x0E /* Event Action A group mask. */ +#define TCA_SINGLE_EVACTA_gp 1 /* Event Action A group position. */ +#define TCA_SINGLE_EVACTA0_bm (1<<1) /* Event Action A bit 0 mask. */ +#define TCA_SINGLE_EVACTA0_bp 1 /* Event Action A bit 0 position. */ +#define TCA_SINGLE_EVACTA1_bm (1<<2) /* Event Action A bit 1 mask. */ +#define TCA_SINGLE_EVACTA1_bp 2 /* Event Action A bit 1 position. */ +#define TCA_SINGLE_EVACTA2_bm (1<<3) /* Event Action A bit 2 mask. */ +#define TCA_SINGLE_EVACTA2_bp 3 /* Event Action A bit 2 position. */ +#define TCA_SINGLE_CNTBEI_bm 0x10 /* Count on Event Input B bit mask. */ +#define TCA_SINGLE_CNTBEI_bp 4 /* Count on Event Input B bit position. */ +#define TCA_SINGLE_EVACTB_gm 0xE0 /* Event Action B group mask. */ +#define TCA_SINGLE_EVACTB_gp 5 /* Event Action B group position. */ +#define TCA_SINGLE_EVACTB0_bm (1<<5) /* Event Action B bit 0 mask. */ +#define TCA_SINGLE_EVACTB0_bp 5 /* Event Action B bit 0 position. */ +#define TCA_SINGLE_EVACTB1_bm (1<<6) /* Event Action B bit 1 mask. */ +#define TCA_SINGLE_EVACTB1_bp 6 /* Event Action B bit 1 position. */ +#define TCA_SINGLE_EVACTB2_bm (1<<7) /* Event Action B bit 2 mask. */ +#define TCA_SINGLE_EVACTB2_bp 7 /* Event Action B bit 2 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ +#define TCA_SPLIT_RUNSTDBY_bm 0x80 /* Run in Standby bit mask. */ +#define TCA_SPLIT_RUNSTDBY_bp 7 /* Run in Standby bit position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TCA_SPLIT_CMDEN_gp 0 /* Command Enable group position. */ +#define TCA_SPLIT_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TCA_SPLIT_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TCA_SPLIT_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TCA_SPLIT_CMDEN1_bp 1 /* Command Enable bit 1 position. */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x0E /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_CLKSEL2_bm (1<<3) /* Clock Select bit 2 mask. */ +#define TCB_CLKSEL2_bp 3 /* Clock Select bit 2 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_CASCADE_bm 0x20 /* Cascade two timers bit mask. */ +#define TCB_CASCADE_bp 5 /* Cascade two timers bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ +#define TCB_OVF_bm 0x02 /* Overflow bit mask. */ +#define TCB_OVF_bp 1 /* Overflow bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ +/* TCB_OVF is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Synchronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Synchronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Synchronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Synchronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Synchronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Synchronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ +#define TWI_INPUTLVL_bm 0x40 /* Input Voltage Transition Level bit mask. */ +#define TWI_INPUTLVL_bp 6 /* Input Voltage Transition Level bit position. */ + +/* TWI.DUALCTRL bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Dual Control Enable bit mask. */ +#define TWI_ENABLE_bp 0 /* Dual Control Enable bit position. */ +/* TWI_FMPEN is already defined. */ +/* TWI_SDAHOLD is already defined. */ +/* TWI_INPUTLVL is already defined. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.CTRLD bit masks and bit positions */ +#define USART_ABW_gm 0xC0 /* Auto Baud Window group mask. */ +#define USART_ABW_gp 6 /* Auto Baud Window group position. */ +#define USART_ABW0_bm (1<<6) /* Auto Baud Window bit 0 mask. */ +#define USART_ABW0_bp 6 /* Auto Baud Window bit 0 position. */ +#define USART_ABW1_bm (1<<7) /* Auto Baud Window bit 1 mask. */ +#define USART_ABW1_bp 7 /* Auto Baud Window bit 1 position. */ + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.ADC0REF bit masks and bit positions */ +#define VREF_REFSEL_gm 0x07 /* Reference select group mask. */ +#define VREF_REFSEL_gp 0 /* Reference select group position. */ +#define VREF_REFSEL0_bm (1<<0) /* Reference select bit 0 mask. */ +#define VREF_REFSEL0_bp 0 /* Reference select bit 0 position. */ +#define VREF_REFSEL1_bm (1<<1) /* Reference select bit 1 mask. */ +#define VREF_REFSEL1_bp 1 /* Reference select bit 1 position. */ +#define VREF_REFSEL2_bm (1<<2) /* Reference select bit 2 mask. */ +#define VREF_REFSEL2_bp 2 /* Reference select bit 2 position. */ +#define VREF_ALWAYSON_bm 0x80 /* Always on bit mask. */ +#define VREF_ALWAYSON_bp 7 /* Always on bit position. */ + +/* VREF.DAC0REF bit masks and bit positions */ +/* VREF_REFSEL is already defined. */ +/* VREF_ALWAYSON is already defined. */ + +/* VREF.ACREF bit masks and bit positions */ +/* VREF_REFSEL is already defined. */ +/* VREF_ALWAYSON is already defined. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + +/* ZCD - Zero Cross Detect */ +/* ZCD.CTRLA bit masks and bit positions */ +#define ZCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define ZCD_ENABLE_bp 0 /* Enable bit position. */ +#define ZCD_INVERT_bm 0x08 /* Invert signal from pin bit mask. */ +#define ZCD_INVERT_bp 3 /* Invert signal from pin bit position. */ +#define ZCD_OUTEN_bm 0x40 /* Output Pad Enable bit mask. */ +#define ZCD_OUTEN_bp 6 /* Output Pad Enable bit position. */ +#define ZCD_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define ZCD_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* ZCD.INTCTRL bit masks and bit positions */ +#define ZCD_INTMODE_gm 0x03 /* Interrupt Mode group mask. */ +#define ZCD_INTMODE_gp 0 /* Interrupt Mode group position. */ +#define ZCD_INTMODE0_bm (1<<0) /* Interrupt Mode bit 0 mask. */ +#define ZCD_INTMODE0_bp 0 /* Interrupt Mode bit 0 position. */ +#define ZCD_INTMODE1_bm (1<<1) /* Interrupt Mode bit 1 mask. */ +#define ZCD_INTMODE1_bp 1 /* Interrupt Mode bit 1 position. */ + +/* ZCD.STATUS bit masks and bit positions */ +#define ZCD_CROSSIF_bm 0x01 /* ZCD Interrupt Flag bit mask. */ +#define ZCD_CROSSIF_bp 0 /* ZCD Interrupt Flag bit position. */ +#define ZCD_STATE_bm 0x10 /* ZCD State bit mask. */ +#define ZCD_STATE_bp 4 /* ZCD State bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* NMI interrupt vectors */ +#define NMI_vect_num 1 +#define NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 3 +#define RTC_CNT_vect _VECTOR(3) /* */ +#define RTC_PIT_vect_num 4 +#define RTC_PIT_vect _VECTOR(4) /* */ + +/* CCL interrupt vectors */ +#define CCL_CCL_vect_num 5 +#define CCL_CCL_vect _VECTOR(5) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 6 +#define PORTA_PORT_vect _VECTOR(6) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 7 +#define TCA0_LUNF_vect _VECTOR(7) /* */ +#define TCA0_OVF_vect_num 7 +#define TCA0_OVF_vect _VECTOR(7) /* */ +#define TCA0_HUNF_vect_num 8 +#define TCA0_HUNF_vect _VECTOR(8) /* */ +#define TCA0_CMP0_vect_num 9 +#define TCA0_CMP0_vect _VECTOR(9) /* */ +#define TCA0_LCMP0_vect_num 9 +#define TCA0_LCMP0_vect _VECTOR(9) /* */ +#define TCA0_CMP1_vect_num 10 +#define TCA0_CMP1_vect _VECTOR(10) /* */ +#define TCA0_LCMP1_vect_num 10 +#define TCA0_LCMP1_vect _VECTOR(10) /* */ +#define TCA0_CMP2_vect_num 11 +#define TCA0_CMP2_vect _VECTOR(11) /* */ +#define TCA0_LCMP2_vect_num 11 +#define TCA0_LCMP2_vect _VECTOR(11) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 12 +#define TCB0_INT_vect _VECTOR(12) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 13 +#define TCB1_INT_vect _VECTOR(13) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 14 +#define TCD0_OVF_vect _VECTOR(14) /* */ +#define TCD0_TRIG_vect_num 15 +#define TCD0_TRIG_vect _VECTOR(15) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 16 +#define TWI0_TWIS_vect _VECTOR(16) /* */ +#define TWI0_TWIM_vect_num 17 +#define TWI0_TWIM_vect _VECTOR(17) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 18 +#define SPI0_INT_vect _VECTOR(18) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 19 +#define USART0_RXC_vect _VECTOR(19) /* */ +#define USART0_DRE_vect_num 20 +#define USART0_DRE_vect _VECTOR(20) /* */ +#define USART0_TXC_vect_num 21 +#define USART0_TXC_vect _VECTOR(21) /* */ + +/* PORTD interrupt vectors */ +#define PORTD_PORT_vect_num 22 +#define PORTD_PORT_vect _VECTOR(22) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 23 +#define AC0_AC_vect _VECTOR(23) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 24 +#define ADC0_RESRDY_vect _VECTOR(24) /* */ +#define ADC0_WCMP_vect_num 25 +#define ADC0_WCMP_vect _VECTOR(25) /* */ + +/* ZCD0 interrupt vectors */ +#define ZCD0_ZCD_vect_num 26 +#define ZCD0_ZCD_vect _VECTOR(26) /* */ + +/* PTC interrupt vectors */ +#define PTC_PTC_vect_num 27 +#define PTC_PTC_vect _VECTOR(27) /* */ + +/* AC1 interrupt vectors */ +#define AC1_AC_vect_num 28 +#define AC1_AC_vect _VECTOR(28) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 29 +#define PORTC_PORT_vect _VECTOR(29) /* */ + +/* TCB2 interrupt vectors */ +#define TCB2_INT_vect_num 30 +#define TCB2_INT_vect _VECTOR(30) /* */ + +/* USART1 interrupt vectors */ +#define USART1_RXC_vect_num 31 +#define USART1_RXC_vect _VECTOR(31) /* */ +#define USART1_DRE_vect_num 32 +#define USART1_DRE_vect _VECTOR(32) /* */ +#define USART1_TXC_vect_num 33 +#define USART1_TXC_vect _VECTOR(33) /* */ + +/* PORTF interrupt vectors */ +#define PORTF_PORT_vect_num 34 +#define PORTF_PORT_vect _VECTOR(34) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 35 +#define NVMCTRL_EE_vect _VECTOR(35) /* */ + +/* SPI1 interrupt vectors */ +#define SPI1_INT_vect_num 36 +#define SPI1_INT_vect _VECTOR(36) /* */ + +/* USART2 interrupt vectors */ +#define USART2_RXC_vect_num 37 +#define USART2_RXC_vect _VECTOR(37) /* */ +#define USART2_DRE_vect_num 38 +#define USART2_DRE_vect _VECTOR(38) /* */ +#define USART2_TXC_vect_num 39 +#define USART2_TXC_vect _VECTOR(39) /* */ + +/* AC2 interrupt vectors */ +#define AC2_AC_vect_num 40 +#define AC2_AC_vect _VECTOR(40) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 44 +#define PORTB_PORT_vect _VECTOR(44) /* */ + +/* PORTE interrupt vectors */ +#define PORTE_PORT_vect_num 45 +#define PORTE_PORT_vect _VECTOR(45) /* */ + +/* PORTG interrupt vectors */ +#define PORTG_PORT_vect_num 58 +#define PORTG_PORT_vect _VECTOR(58) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (59 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (65536) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (65536U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (512) +# define EEPROM_PAGE_SIZE (1) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (512U) +# define EEPROM_PAGE_SIZE (1U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1050) +# define FUSES_SIZE (16) +# define FUSES_PAGE_SIZE (1) +#else +# define FUSES_START (0x1050U) +# define FUSES_SIZE (16U) +# define FUSES_PAGE_SIZE (1U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x4000) +# define INTERNAL_SRAM_SIZE (16384) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x4000U) +# define INTERNAL_SRAM_SIZE (16384U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4159) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4159U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x1040) +# define LOCKBITS_SIZE (4) +# define LOCKBITS_PAGE_SIZE (1) +#else +# define LOCKBITS_START (0x1040U) +# define LOCKBITS_SIZE (4U) +# define LOCKBITS_PAGE_SIZE (1U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (32768) +# define MAPPED_PROGMEM_PAGE_SIZE (512) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (32768U) +# define MAPPED_PROGMEM_PAGE_SIZE (512U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (125) +# define PROD_SIGNATURES_PAGE_SIZE (128) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (125U) +# define PROD_SIGNATURES_PAGE_SIZE (128U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (128) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (128U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1080) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1080U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (131072) +# define PROGMEM_PAGE_SIZE (512) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (131072U) +# define PROGMEM_PAGE_SIZE (512U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 16 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_CLKSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_CLKSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_CLKSEL2 (unsigned char)_BV(2) /* Frequency Select Bit 2 */ +#define FUSE2_DEFAULT (0x0) +#define FUSE_OSCCFG_DEFAULT (0x0) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSEL (unsigned char)_BV(5) /* CRC Select */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc0) +#define FUSE_SYSCFG0_DEFAULT (0xc0) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x0) +#define FUSE_SYSCFG1_DEFAULT (0x0) + +/* Fuse Byte 7 (CODESIZE) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_CODESIZE_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTSIZE) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTSIZE_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_KEY_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0x5cc5c55c) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x0A + + +#endif /* #ifdef _AVR_AVR128DA28_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/ioavr128da32.h b/hardware/tools/avr/avr/include/avr/ioavr128da32.h new file mode 100644 index 0000000000000000000000000000000000000000..2e1c0747a3243c6f218b8524517ae6404b10066b --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/ioavr128da32.h @@ -0,0 +1,7167 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioavr128da32.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_AVR128DA32_H_INCLUDED +#define _AVR_AVR128DA32_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPZ _SFR_MEM8(0x003B) /* Extended Z-pointer Register */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t MUXCTRL; /* Mux Control A */ + register8_t reserved_1[2]; + register8_t DACREF; /* DAC Voltage Reference */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NONE_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_MEDIUM_gc = (0x02<<1), /* Medium hysteresis */ + AC_HYSMODE_LARGE_gc = (0x03<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* AC Output Initial Value select */ +typedef enum AC_INITVAL_enum +{ + AC_INITVAL_LOW_gc = (0x00<<6), /* Output initialized to 0 */ + AC_INITVAL_HIGH_gc = (0x01<<6), /* Output initialized to 1 */ +} AC_INITVAL_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_ABOVE_gc = (0x00<<4), /* Entering window state above */ + AC_INTMODE_INSIDE_gc = (0x01<<4), /* Entering window state inside */ + AC_INTMODE_BELOW_gc = (0x02<<4), /* Entering window state below */ + AC_INTMODE_OUTSIDE_gc = (0x03<<4), /* Entering window state above or below */ +} AC_INTMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_AINN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_AINN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_AINN2_gc = (0x02<<0), /* Negative Pin 2 */ + AC_MUXNEG_DACREF_gc = (0x03<<0), /* DAC Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_AINP0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_AINP1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_AINP2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_AINP3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* Power profile select */ +typedef enum AC_POWER_enum +{ + AC_POWER_PROFILE0_gc = (0x00<<3), /* Power profile 0, lowest consumption and highest response time. */ + AC_POWER_PROFILE1_gc = (0x01<<3), /* Power profile 1 */ + AC_POWER_PROFILE2_gc = (0x02<<3), /* Power profile 2 */ + AC_POWER_PROFILE3_gc = (0x03<<3), /* Power profile 3 */ +} AC_POWER_t; + +/* Window selection mode select */ +typedef enum AC_WINSEL_enum +{ + AC_WINSEL_DISABLED_gc = (0x00<<0), /* Window function disabled */ + AC_WINSEL_UPSEL1_gc = (0x01<<0), /* Select ACn+1 as upper limit in window compare. */ + AC_WINSEL_UPSEL2_gc = (0x02<<0), /* Select ACn+2 as upper limit in window compare. */ +} AC_WINSEL_t; + +/* Analog Comparator Window State select */ +typedef enum AC_WINSTATE_enum +{ + AC_WINSTATE_ABOVE_gc = (0x00<<6), /* Above window */ + AC_WINSTATE_INSIDE_gc = (0x01<<6), /* Inside window */ + AC_WINSTATE_BELOW_gc = (0x02<<6), /* Below window */ +} AC_WINSTATE_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t reserved_1[2]; + register8_t MUXPOS; /* Positive mux input */ + register8_t MUXNEG; /* Negative mux input */ + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t reserved_2[2]; +} ADC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXNEG_enum +{ + ADC_MUXNEG_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXNEG_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXNEG_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXNEG_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXNEG_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXNEG_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXNEG_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXNEG_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXNEG_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXNEG_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXNEG_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXNEG_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXNEG_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ + ADC_MUXNEG_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ + ADC_MUXNEG_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ + ADC_MUXNEG_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ + ADC_MUXNEG_GND_gc = (0x40<<0), /* Ground */ + ADC_MUXNEG_DAC0_gc = (0x48<<0), /* DAC0 */ +} ADC_MUXNEG_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ + ADC_MUXPOS_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ + ADC_MUXPOS_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ + ADC_MUXPOS_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ + ADC_MUXPOS_AIN16_gc = (0x10<<0), /* ADC input pin 16 */ + ADC_MUXPOS_AIN17_gc = (0x11<<0), /* ADC input pin 17 */ + ADC_MUXPOS_AIN18_gc = (0x12<<0), /* ADC input pin 18 */ + ADC_MUXPOS_AIN19_gc = (0x13<<0), /* ADC input pin 19 */ + ADC_MUXPOS_AIN20_gc = (0x14<<0), /* ADC input pin 20 */ + ADC_MUXPOS_AIN21_gc = (0x15<<0), /* ADC input pin 21 */ + ADC_MUXPOS_GND_gc = (0x40<<0), /* Ground */ + ADC_MUXPOS_TEMPSENSE_gc = (0x42<<0), /* Temperature sensor */ + ADC_MUXPOS_DAC0_gc = (0x48<<0), /* DAC0 */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV12_gc = (0x03<<0), /* CLK_PER divided by 12 */ + ADC_PRESC_DIV16_gc = (0x04<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV20_gc = (0x05<<0), /* CLK_PER divided by 20 */ + ADC_PRESC_DIV24_gc = (0x06<<0), /* CLK_PER divided by 24 */ + ADC_PRESC_DIV28_gc = (0x07<<0), /* CLK_PER divided by 28 */ + ADC_PRESC_DIV32_gc = (0x08<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV48_gc = (0x09<<0), /* CLK_PER divided by 48 */ + ADC_PRESC_DIV64_gc = (0x0A<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV96_gc = (0x0B<<0), /* CLK_PER divided by 96 */ + ADC_PRESC_DIV128_gc = (0x0C<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x0D<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Resolution selection select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_12BIT_gc = (0x00<<2), /* 12-bit mode */ + ADC_RESSEL_10BIT_gc = (0x01<<2), /* 10-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_NONE_gc = (0x00<<0), /* No accumulation */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* 2 results accumulated */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* 4 results accumulated */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* 8 results accumulated */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* 16 results accumulated */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* 32 results accumulated */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* 64 results accumulated */ + ADC_SAMPNUM_ACC128_gc = (0x07<<0), /* 128 results accumulated */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.9 V */ + BOD_LVL_BODLEVEL1_gc = (0x01<<0), /* 2.45 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.7 V */ + BOD_LVL_BODLEVEL3_gc = (0x03<<0), /* 2.85 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_128HZ_gc = (0x00<<4), /* 128Hz sampling frequency */ + BOD_SAMPFREQ_32HZ_gc = (0x01<<4), /* 32Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_FALLING_gc = (0x00<<1), /* VDD falls below VLM threshold */ + BOD_VLMCFG_RISING_gc = (0x01<<1), /* VDD rises above VLM threshold */ + BOD_VLMCFG_BOTH_gc = (0x02<<1), /* VDD crosses VLM threshold */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_OFF_gc = (0x00<<0), /* VLM Disabled */ + BOD_VLMLVL_5ABOVE_gc = (0x01<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x02<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x03<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* Voltage level monitor status select */ +typedef enum BOD_VLMS_enum +{ + BOD_VLMS_ABOVE_gc = (0x00<<0), /* The voltage is above the VLM threshold level */ + BOD_VLMS_BELOW_gc = (0x01<<0), /* The voltage is below the VLM threshold level */ +} BOD_VLMS_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t SEQCTRL1; /* Sequential Control 1 */ + register8_t reserved_1[2]; + register8_t INTCTRL0; /* Interrupt Control 0 */ + register8_t reserved_2[1]; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t LUT2CTRLA; /* LUT Control 2 A */ + register8_t LUT2CTRLB; /* LUT Control 2 B */ + register8_t LUT2CTRLC; /* LUT Control 2 C */ + register8_t TRUTH2; /* Truth 2 */ + register8_t LUT3CTRLA; /* LUT Control 3 A */ + register8_t LUT3CTRLB; /* LUT Control 3 B */ + register8_t LUT3CTRLC; /* LUT Control 3 C */ + register8_t TRUTH3; /* Truth 3 */ + register8_t reserved_3[40]; +} CCL_t; + +/* Clock Source Selection select */ +typedef enum CCL_CLKSRC_enum +{ + CCL_CLKSRC_CLKPER_gc = (0x00<<1), /* CLK_PER is clocking the LUT */ + CCL_CLKSRC_IN2_gc = (0x01<<1), /* IN[2] is clocking the LUT */ + CCL_CLKSRC_OSCHF_gc = (0x04<<1), /* Internal high-frequency oscillator before prescaler is clocking LUT */ + CCL_CLKSRC_OSC32K_gc = (0x05<<1), /* Internal 32.768 kHz oscillator */ + CCL_CLKSRC_OSC1K_gc = (0x06<<1), /* Internal 32.768 kHz oscillator divided by 32 */ +} CCL_CLKSRC_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL0_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL0_IN0_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_ZCD0_gc = (0x07<<0), /* ZCD0 OUT input source */ + CCL_INSEL0_USART0_gc = (0x08<<0), /* USART0 TXD input source */ + CCL_INSEL0_SPI0_gc = (0x09<<0), /* SPI0 MOSI input source */ + CCL_INSEL0_TCA0_gc = (0x0A<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCB0_gc = (0x0C<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCD0_gc = (0x0D<<0), /* TCD0 WOA input source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENTA_gc = (0x03<<4), /* Event input source A */ + CCL_INSEL1_EVENTB_gc = (0x04<<4), /* Event input source B */ + CCL_INSEL1_IN1_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC1_gc = (0x06<<4), /* AC1 OUT input source */ + CCL_INSEL1_ZCD1_gc = (0x07<<4), /* ZCD1 OUT input source */ + CCL_INSEL1_USART1_gc = (0x08<<4), /* USART1 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x09<<4), /* SPI0 MOSI input source */ + CCL_INSEL1_TCA0_gc = (0x0A<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCB1_gc = (0x0C<<4), /* TCB1 WO input source */ + CCL_INSEL1_TCD0_gc = (0x0D<<4), /* TCD0 WOB input soruce */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL2_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL2_IN2_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC2_gc = (0x06<<0), /* AC2 OUT input source */ + CCL_INSEL2_ZCD2_gc = (0x07<<0), /* ZCD2 OUT input source */ + CCL_INSEL2_USART2_gc = (0x08<<0), /* USART2 TXD input source */ + CCL_INSEL2_SPI0_gc = (0x09<<0), /* SPI0 SCK input source */ + CCL_INSEL2_TCA0_gc = (0x0A<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCB2_gc = (0x0C<<0), /* TCB2 WO input source */ + CCL_INSEL2_TCD0_gc = (0x0D<<0), /* TCD0 WOC input source */ +} CCL_INSEL2_t; + +/* Interrupt Mode for LUT0 select */ +typedef enum CCL_INTMODE0_enum +{ + CCL_INTMODE0_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled */ + CCL_INTMODE0_RISING_gc = (0x01<<0), /* Sense rising edge */ + CCL_INTMODE0_FALLING_gc = (0x02<<0), /* Sense falling edge */ + CCL_INTMODE0_BOTH_gc = (0x03<<0), /* Sense both edges */ +} CCL_INTMODE0_t; + +/* Interrupt Mode for LUT1 select */ +typedef enum CCL_INTMODE1_enum +{ + CCL_INTMODE1_INTDISABLE_gc = (0x00<<2), /* Interrupt disabled */ + CCL_INTMODE1_RISING_gc = (0x01<<2), /* Sense rising edge */ + CCL_INTMODE1_FALLING_gc = (0x02<<2), /* Sense falling edge */ + CCL_INTMODE1_BOTH_gc = (0x03<<2), /* Sense both edges */ +} CCL_INTMODE1_t; + +/* Interrupt Mode for LUT2 select */ +typedef enum CCL_INTMODE2_enum +{ + CCL_INTMODE2_INTDISABLE_gc = (0x00<<4), /* Interrupt disabled */ + CCL_INTMODE2_RISING_gc = (0x01<<4), /* Sense rising edge */ + CCL_INTMODE2_FALLING_gc = (0x02<<4), /* Sense falling edge */ + CCL_INTMODE2_BOTH_gc = (0x03<<4), /* Sense both edges */ +} CCL_INTMODE2_t; + +/* Interrupt Mode for LUT3 select */ +typedef enum CCL_INTMODE3_enum +{ + CCL_INTMODE3_INTDISABLE_gc = (0x00<<6), /* Interrupt disabled */ + CCL_INTMODE3_RISING_gc = (0x01<<6), /* Sense rising edge */ + CCL_INTMODE3_FALLING_gc = (0x02<<6), /* Sense falling edge */ + CCL_INTMODE3_BOTH_gc = (0x03<<6), /* Sense both edges */ +} CCL_INTMODE3_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL0_enum +{ + CCL_SEQSEL0_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL0_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL0_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL0_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL0_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL0_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL1_enum +{ + CCL_SEQSEL1_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL1_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL1_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL1_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL1_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL1_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[4]; + register8_t OSCHFCTRLA; /* OSCHF Control A */ + register8_t OSCHFTUNE; /* OSCHF Tune */ + register8_t reserved_2[6]; + register8_t PLLCTRLA; /* PLL Control A */ + register8_t reserved_3[7]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_4[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_5[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSCHF_gc = (0x00<<0), /* Internal high-frequency oxcillator */ + CLKCTRL_CLKSEL_OSC32K_gc = (0x01<<0), /* Internal 32.768 kHz oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768 kHz crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1k cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16k cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32k cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ +} CLKCTRL_CSUT_t; + +/* Frequency select select */ +typedef enum CLKCTRL_FREQSEL_enum +{ + CLKCTRL_FREQSEL_1M_gc = (0x00<<2), /* 1 MHz system clock */ + CLKCTRL_FREQSEL_2M_gc = (0x01<<2), /* 2 MHz system clock */ + CLKCTRL_FREQSEL_3M_gc = (0x02<<2), /* 3 MHz system clock */ + CLKCTRL_FREQSEL_4M_gc = (0x03<<2), /* 4 MHz system clock (default) */ + CLKCTRL_FREQSEL_8M_gc = (0x05<<2), /* 8 MHz system clock */ + CLKCTRL_FREQSEL_12M_gc = (0x06<<2), /* 12 MHz system clock */ + CLKCTRL_FREQSEL_16M_gc = (0x07<<2), /* 16 MHz system clock */ + CLKCTRL_FREQSEL_20M_gc = (0x08<<2), /* 20 MHz system clock */ + CLKCTRL_FREQSEL_24M_gc = (0x09<<2), /* 24 MHz system clock */ +} CLKCTRL_FREQSEL_t; + +/* Multiplication factor select */ +typedef enum CLKCTRL_MULFAC_enum +{ + CLKCTRL_MULFAC_DISABLE_gc = (0x00<<0), /* PLL is disabled */ + CLKCTRL_MULFAC_2x_gc = (0x01<<0), /* 2 x multiplication factor */ + CLKCTRL_MULFAC_3x_gc = (0x02<<0), /* 3 x multiplication factor */ + CLKCTRL_MULFAC_4x_gc = (0x03<<0), /* 4 x multiplication factor */ +} CLKCTRL_MULFAC_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* DATA Register */ +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t SWEVENTA; /* Software Event A */ + register8_t SWEVENTB; /* Software Event B */ + register8_t reserved_1[14]; + register8_t CHANNEL0; /* Multiplexer Channel 0 */ + register8_t CHANNEL1; /* Multiplexer Channel 1 */ + register8_t CHANNEL2; /* Multiplexer Channel 2 */ + register8_t CHANNEL3; /* Multiplexer Channel 3 */ + register8_t CHANNEL4; /* Multiplexer Channel 4 */ + register8_t CHANNEL5; /* Multiplexer Channel 5 */ + register8_t CHANNEL6; /* Multiplexer Channel 6 */ + register8_t CHANNEL7; /* Multiplexer Channel 7 */ + register8_t CHANNEL8; /* Multiplexer Channel 8 */ + register8_t CHANNEL9; /* Multiplexer Channel 9 */ + register8_t reserved_2[6]; + register8_t USERCCLLUT0A; /* User 0 - CCL0 Event A */ + register8_t USERCCLLUT0B; /* User 1 - CCL0 Event B */ + register8_t USERCCLLUT1A; /* User 2 - CCL1 Event A */ + register8_t USERCCLLUT1B; /* User 3 - CCL1 Event B */ + register8_t USERCCLLUT2A; /* User 4 - CCL2 Event A */ + register8_t USERCCLLUT2B; /* User 5 - CCL2 Event B */ + register8_t USERCCLLUT3A; /* User 6 - CCL3 Event A */ + register8_t USERCCLLUT3B; /* User 7 - CCL3 Event B */ + register8_t USERCCLLUT4A; /* User 8 - CCL4 Event A */ + register8_t USERCCLLUT4B; /* User 9 - CCL4 Event B */ + register8_t USERCCLLUT5A; /* User 10 - CCL5 Event A */ + register8_t USERCCLLUT5B; /* User 11 - CCL5 Event B */ + register8_t USERADC0START; /* User 12 - ADC0 */ + register8_t USERPTCSTART; /* User 13 - PTC */ + register8_t USEREVSYSEVOUTA; /* User 14 - EVOUTA */ + register8_t USEREVSYSEVOUTB; /* User 15 - EVOUTB */ + register8_t USEREVSYSEVOUTC; /* User 16 - EVOUTC */ + register8_t USEREVSYSEVOUTD; /* User 17 - EVOUTD */ + register8_t USEREVSYSEVOUTE; /* User 18 - EVOUTE */ + register8_t USEREVSYSEVOUTF; /* User 19 - EVOUTF */ + register8_t USEREVSYSEVOUTG; /* User 20 - EVOUTG */ + register8_t USERUSART0IRDA; /* User 21 - USART0 */ + register8_t USERUSART1IRDA; /* User 22 - USART1 */ + register8_t USERUSART2IRDA; /* User 23 - USART2 */ + register8_t USERUSART3IRDA; /* User 24 - USART3 */ + register8_t USERUSART4IRDA; /* User 25 - USART4 */ + register8_t USERUSART5IRDA; /* User 26 - USART5 */ + register8_t USERTCA0CNTA; /* User 27 - TCA0 Event A */ + register8_t USERTCA0CNTB; /* User 28 - TCA0 Event B */ + register8_t USERTCA1CNTA; /* User 29 - TCA1 Event A */ + register8_t USERTCA1CNTB; /* User 30 - TCA1 Event B */ + register8_t USERTCB0CAPT; /* User 31 - TCB0 Event A */ + register8_t USERTCB0COUNT; /* User 32 - TCB0 Event B */ + register8_t USERTCB1CAPT; /* User 33 - TCB1 Event A */ + register8_t USERTCB1COUNT; /* User 34 - TCB1 Event B */ + register8_t USERTCB2CAPT; /* User 35 - TCB2 Event A */ + register8_t USERTCB2COUNT; /* User 36 - TCB2 Event B */ + register8_t USERTCB3CAPT; /* User 37 - TCB3 Event A */ + register8_t USERTCB3COUNT; /* User 38 - TCB3 Event B */ + register8_t USERTCB4CAPT; /* User 39 - TCB4 Event A */ + register8_t USERTCB4COUNT; /* User 40 - TCB4 Event B */ + register8_t USERTCD0INPUTA; /* User 41 - TCD0 Event A */ + register8_t USERTCD0INPUTB; /* User 42 - TCD0 Event B */ + register8_t USEROSCTEST; /* User 43 - OSCTEST */ +} EVSYS_t; + +/* Channel 0 generator select select */ +typedef enum EVSYS_CHANNEL0_enum +{ + EVSYS_CHANNEL0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL0_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL0_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL0_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL0_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL0_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL0_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL0_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL0_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL0_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL0_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL0_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL0_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL0_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL0_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL0_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL0_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL0_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL0_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL0_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL0_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL0_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL0_PORTA_PIN0_gc = (0x40<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL0_PORTA_PIN1_gc = (0x41<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL0_PORTA_PIN2_gc = (0x42<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL0_PORTA_PIN3_gc = (0x43<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL0_PORTA_PIN4_gc = (0x44<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL0_PORTA_PIN5_gc = (0x45<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL0_PORTA_PIN6_gc = (0x46<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL0_PORTA_PIN7_gc = (0x47<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL0_PORTB_PIN0_gc = (0x48<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL0_PORTB_PIN1_gc = (0x49<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL0_PORTB_PIN2_gc = (0x4A<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL0_PORTB_PIN3_gc = (0x4B<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL0_PORTB_PIN4_gc = (0x4C<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL0_PORTB_PIN5_gc = (0x4D<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL0_PORTB_PIN6_gc = (0x4E<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL0_PORTB_PIN7_gc = (0x4F<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL0_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL0_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL0_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL0_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL0_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL0_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL0_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL0_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL0_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL0_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL0_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL0_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL0_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL0_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL0_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL0_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL0_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL0_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL0_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL0_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL0_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL0_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL0_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL0_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL0_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL0_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL0_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL0_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL0_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL0_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL0_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL0_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL0_t; + +/* Channel 1 generator select select */ +typedef enum EVSYS_CHANNEL1_enum +{ + EVSYS_CHANNEL1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL1_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL1_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL1_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL1_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL1_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL1_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL1_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL1_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL1_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL1_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL1_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL1_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL1_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL1_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL1_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL1_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL1_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL1_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL1_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL1_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL1_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL1_PORTA_PIN0_gc = (0x40<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL1_PORTA_PIN1_gc = (0x41<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL1_PORTA_PIN2_gc = (0x42<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL1_PORTA_PIN3_gc = (0x43<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL1_PORTA_PIN4_gc = (0x44<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL1_PORTA_PIN5_gc = (0x45<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL1_PORTA_PIN6_gc = (0x46<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL1_PORTA_PIN7_gc = (0x47<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL1_PORTB_PIN0_gc = (0x48<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL1_PORTB_PIN1_gc = (0x49<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL1_PORTB_PIN2_gc = (0x4A<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL1_PORTB_PIN3_gc = (0x4B<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL1_PORTB_PIN4_gc = (0x4C<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL1_PORTB_PIN5_gc = (0x4D<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL1_PORTB_PIN6_gc = (0x4E<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL1_PORTB_PIN7_gc = (0x4F<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL1_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL1_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL1_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL1_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL1_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL1_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL1_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL1_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL1_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL1_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL1_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL1_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL1_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL1_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL1_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL1_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL1_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL1_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL1_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL1_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL1_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL1_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL1_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL1_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL1_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL1_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL1_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL1_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL1_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL1_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL1_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL1_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL1_t; + +/* Channel 2 generator select select */ +typedef enum EVSYS_CHANNEL2_enum +{ + EVSYS_CHANNEL2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL2_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL2_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL2_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL2_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL2_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL2_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL2_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL2_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL2_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL2_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL2_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL2_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL2_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL2_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL2_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL2_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL2_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL2_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL2_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL2_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL2_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL2_PORTC_PIN0_gc = (0x40<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL2_PORTC_PIN1_gc = (0x41<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL2_PORTC_PIN2_gc = (0x42<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL2_PORTC_PIN3_gc = (0x43<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL2_PORTC_PIN4_gc = (0x44<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL2_PORTC_PIN5_gc = (0x45<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL2_PORTC_PIN6_gc = (0x46<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL2_PORTC_PIN7_gc = (0x47<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL2_PORTD_PIN0_gc = (0x48<<0), /* Port D Pin 0 */ + EVSYS_CHANNEL2_PORTD_PIN1_gc = (0x49<<0), /* Port D Pin 1 */ + EVSYS_CHANNEL2_PORTD_PIN2_gc = (0x4A<<0), /* Port D Pin 2 */ + EVSYS_CHANNEL2_PORTD_PIN3_gc = (0x4B<<0), /* Port D Pin 3 */ + EVSYS_CHANNEL2_PORTD_PIN4_gc = (0x4C<<0), /* Port D Pin 4 */ + EVSYS_CHANNEL2_PORTD_PIN5_gc = (0x4D<<0), /* Port D Pin 5 */ + EVSYS_CHANNEL2_PORTD_PIN6_gc = (0x4E<<0), /* Port D Pin 6 */ + EVSYS_CHANNEL2_PORTD_PIN7_gc = (0x4F<<0), /* Port D Pin 7 */ + EVSYS_CHANNEL2_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL2_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL2_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL2_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL2_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL2_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL2_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL2_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL2_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL2_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL2_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL2_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL2_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL2_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL2_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL2_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL2_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL2_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL2_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL2_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL2_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL2_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL2_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL2_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL2_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL2_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL2_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL2_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL2_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL2_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL2_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL2_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL2_t; + +/* Channel 3 generator select select */ +typedef enum EVSYS_CHANNEL3_enum +{ + EVSYS_CHANNEL3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL3_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL3_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL3_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL3_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL3_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL3_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL3_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL3_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL3_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL3_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL3_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL3_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL3_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL3_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL3_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL3_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL3_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL3_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL3_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL3_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL3_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL3_PORTC_PIN0_gc = (0x40<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL3_PORTC_PIN1_gc = (0x41<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL3_PORTC_PIN2_gc = (0x42<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL3_PORTC_PIN3_gc = (0x43<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL3_PORTC_PIN4_gc = (0x44<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL3_PORTC_PIN5_gc = (0x45<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL3_PORTC_PIN6_gc = (0x46<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL3_PORTC_PIN7_gc = (0x47<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL3_PORTD_PIN0_gc = (0x48<<0), /* Port D Pin 0 */ + EVSYS_CHANNEL3_PORTD_PIN1_gc = (0x49<<0), /* Port D Pin 1 */ + EVSYS_CHANNEL3_PORTD_PIN2_gc = (0x4A<<0), /* Port D Pin 2 */ + EVSYS_CHANNEL3_PORTD_PIN3_gc = (0x4B<<0), /* Port D Pin 3 */ + EVSYS_CHANNEL3_PORTD_PIN4_gc = (0x4C<<0), /* Port D Pin 4 */ + EVSYS_CHANNEL3_PORTD_PIN5_gc = (0x4D<<0), /* Port D Pin 5 */ + EVSYS_CHANNEL3_PORTD_PIN6_gc = (0x4E<<0), /* Port D Pin 6 */ + EVSYS_CHANNEL3_PORTD_PIN7_gc = (0x4F<<0), /* Port D Pin 7 */ + EVSYS_CHANNEL3_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL3_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL3_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL3_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL3_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL3_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL3_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL3_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL3_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL3_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL3_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL3_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL3_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL3_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL3_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL3_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL3_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL3_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL3_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL3_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL3_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL3_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL3_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL3_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL3_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL3_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL3_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL3_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL3_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL3_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL3_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL3_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL3_t; + +/* Channel 4 generator select select */ +typedef enum EVSYS_CHANNEL4_enum +{ + EVSYS_CHANNEL4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL4_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL4_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL4_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL4_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL4_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL4_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL4_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL4_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL4_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL4_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL4_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL4_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL4_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL4_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL4_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL4_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL4_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL4_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL4_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL4_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL4_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL4_PORTE_PIN0_gc = (0x40<<0), /* Port E Pin 0 */ + EVSYS_CHANNEL4_PORTE_PIN1_gc = (0x41<<0), /* Port E Pin 1 */ + EVSYS_CHANNEL4_PORTE_PIN2_gc = (0x42<<0), /* Port E Pin 2 */ + EVSYS_CHANNEL4_PORTE_PIN3_gc = (0x43<<0), /* Port E Pin 3 */ + EVSYS_CHANNEL4_PORTE_PIN4_gc = (0x44<<0), /* Port E Pin 4 */ + EVSYS_CHANNEL4_PORTE_PIN5_gc = (0x45<<0), /* Port E Pin 5 */ + EVSYS_CHANNEL4_PORTE_PIN6_gc = (0x46<<0), /* Port E Pin 6 */ + EVSYS_CHANNEL4_PORTE_PIN7_gc = (0x47<<0), /* Port E Pin 7 */ + EVSYS_CHANNEL4_PORTF_PIN0_gc = (0x48<<0), /* Port F Pin 0 */ + EVSYS_CHANNEL4_PORTF_PIN1_gc = (0x49<<0), /* Port F Pin 1 */ + EVSYS_CHANNEL4_PORTF_PIN2_gc = (0x4A<<0), /* Port F Pin 2 */ + EVSYS_CHANNEL4_PORTF_PIN3_gc = (0x4B<<0), /* Port F Pin 3 */ + EVSYS_CHANNEL4_PORTF_PIN4_gc = (0x4C<<0), /* Port F Pin 4 */ + EVSYS_CHANNEL4_PORTF_PIN5_gc = (0x4D<<0), /* Port F Pin 5 */ + EVSYS_CHANNEL4_PORTF_PIN6_gc = (0x4E<<0), /* Port F Pin 6 */ + EVSYS_CHANNEL4_PORTF_PIN7_gc = (0x4F<<0), /* Port F Pin 7 */ + EVSYS_CHANNEL4_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL4_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL4_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL4_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL4_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL4_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL4_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL4_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL4_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL4_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL4_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL4_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL4_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL4_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL4_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL4_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL4_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL4_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL4_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL4_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL4_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL4_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL4_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL4_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL4_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL4_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL4_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL4_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL4_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL4_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL4_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL4_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL4_t; + +/* Channel 5 generator select select */ +typedef enum EVSYS_CHANNEL5_enum +{ + EVSYS_CHANNEL5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL5_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL5_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL5_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL5_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL5_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL5_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL5_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL5_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL5_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL5_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL5_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL5_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL5_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL5_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL5_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL5_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL5_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL5_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL5_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL5_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL5_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL5_PORTE_PIN0_gc = (0x40<<0), /* Port E Pin 0 */ + EVSYS_CHANNEL5_PORTE_PIN1_gc = (0x41<<0), /* Port E Pin 1 */ + EVSYS_CHANNEL5_PORTE_PIN2_gc = (0x42<<0), /* Port E Pin 2 */ + EVSYS_CHANNEL5_PORTE_PIN3_gc = (0x43<<0), /* Port E Pin 3 */ + EVSYS_CHANNEL5_PORTE_PIN4_gc = (0x44<<0), /* Port E Pin 4 */ + EVSYS_CHANNEL5_PORTE_PIN5_gc = (0x45<<0), /* Port E Pin 5 */ + EVSYS_CHANNEL5_PORTE_PIN6_gc = (0x46<<0), /* Port E Pin 6 */ + EVSYS_CHANNEL5_PORTA_PIN7_gc = (0x47<<0), /* Port E Pin 7 */ + EVSYS_CHANNEL5_PORTF_PIN0_gc = (0x48<<0), /* Port F Pin 0 */ + EVSYS_CHANNEL5_PORTF_PIN1_gc = (0x49<<0), /* Port F Pin 1 */ + EVSYS_CHANNEL5_PORTF_PIN2_gc = (0x4A<<0), /* Port F Pin 2 */ + EVSYS_CHANNEL5_PORTF_PIN3_gc = (0x4B<<0), /* Port F Pin 3 */ + EVSYS_CHANNEL5_PORTF_PIN4_gc = (0x4C<<0), /* Port F Pin 4 */ + EVSYS_CHANNEL5_PORTF_PIN5_gc = (0x4D<<0), /* Port F Pin 5 */ + EVSYS_CHANNEL5_PORTF_PIN6_gc = (0x4E<<0), /* Port F Pin 6 */ + EVSYS_CHANNEL5_PORTF_PIN7_gc = (0x4F<<0), /* Port F Pin 7 */ + EVSYS_CHANNEL5_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL5_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL5_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL5_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL5_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL5_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL5_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL5_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL5_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL5_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL5_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL5_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL5_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL5_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL5_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL5_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL5_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL5_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL5_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL5_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL5_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL5_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL5_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL5_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL5_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL5_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL5_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL5_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL5_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL5_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL5_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL5_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL5_t; + +/* Channel 6 generator select select */ +typedef enum EVSYS_CHANNEL6_enum +{ + EVSYS_CHANNEL6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL6_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL6_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL6_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL6_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL6_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL6_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL6_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL6_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL6_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL6_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL6_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL6_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL6_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL6_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL6_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL6_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL6_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL6_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL6_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL6_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL6_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL6_PORTG_PIN0_gc = (0x40<<0), /* Port G Pin 0 */ + EVSYS_CHANNEL6_PORTG_PIN1_gc = (0x41<<0), /* Port G Pin 1 */ + EVSYS_CHANNEL6_PORTG_PIN2_gc = (0x42<<0), /* Port G Pin 2 */ + EVSYS_CHANNEL6_PORTG_PIN3_gc = (0x43<<0), /* Port G Pin 3 */ + EVSYS_CHANNEL6_PORTG_PIN4_gc = (0x44<<0), /* Port G Pin 4 */ + EVSYS_CHANNEL6_PORTG_PIN5_gc = (0x45<<0), /* Port G Pin 5 */ + EVSYS_CHANNEL6_PORTG_PIN6_gc = (0x46<<0), /* Port G Pin 6 */ + EVSYS_CHANNEL6_PORTG_PIN7_gc = (0x47<<0), /* Port G Pin 7 */ + EVSYS_CHANNEL6_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL6_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL6_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL6_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL6_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL6_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL6_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL6_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL6_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL6_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL6_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL6_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL6_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL6_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL6_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL6_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL6_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL6_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL6_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL6_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL6_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL6_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL6_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL6_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL6_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL6_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL6_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL6_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL6_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL6_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL6_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL6_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL6_t; + +/* Channel 7 generator select select */ +typedef enum EVSYS_CHANNEL7_enum +{ + EVSYS_CHANNEL7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL7_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL7_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL7_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL7_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL7_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL7_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL7_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL7_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL7_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL7_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL7_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL7_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL7_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL7_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL7_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL7_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL7_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL7_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL7_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL7_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL7_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL7_PORTG_PIN0_gc = (0x40<<0), /* Port G Pin 0 */ + EVSYS_CHANNEL7_PORTG_PIN1_gc = (0x41<<0), /* Port G Pin 1 */ + EVSYS_CHANNEL7_PORTG_PIN2_gc = (0x42<<0), /* Port G Pin 2 */ + EVSYS_CHANNEL7_PORTG_PIN3_gc = (0x43<<0), /* Port G Pin 3 */ + EVSYS_CHANNEL7_PORTG_PIN4_gc = (0x44<<0), /* Port G Pin 4 */ + EVSYS_CHANNEL7_PORTG_PIN5_gc = (0x45<<0), /* Port G Pin 5 */ + EVSYS_CHANNEL7_PORTG_PIN6_gc = (0x46<<0), /* Port G Pin 6 */ + EVSYS_CHANNEL7_PORTG_PIN7_gc = (0x47<<0), /* Port G Pin 7 */ + EVSYS_CHANNEL7_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL7_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL7_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL7_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL7_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL7_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL7_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL7_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL7_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL7_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL7_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL7_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL7_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL7_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL7_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL7_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL7_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL7_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL7_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL7_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL7_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL7_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL7_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL7_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL7_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL7_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL7_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL7_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL7_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL7_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL7_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL7_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL7_t; + +/* Channel 8 generator select select */ +typedef enum EVSYS_CHANNEL8_enum +{ + EVSYS_CHANNEL8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL8_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL8_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL8_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL8_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL8_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL8_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL8_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL8_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL8_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL8_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL8_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL8_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL8_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL8_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL8_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL8_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL8_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL8_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL8_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL8_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL8_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL8_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL8_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL8_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL8_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL8_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL8_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL8_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL8_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL8_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL8_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL8_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL8_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL8_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL8_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL8_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL8_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL8_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL8_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL8_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL8_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL8_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL8_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL8_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL8_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL8_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL8_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL8_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL8_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL8_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL8_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL8_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL8_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL8_t; + +/* Channel 9 generator select select */ +typedef enum EVSYS_CHANNEL9_enum +{ + EVSYS_CHANNEL9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL9_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL9_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL9_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL9_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL9_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL9_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL9_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL9_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL9_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL9_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL9_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL9_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL9_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL9_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL9_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL9_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL9_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL9_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL9_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL9_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL9_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL9_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL9_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL9_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL9_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL9_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL9_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL9_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL9_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL9_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL9_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL9_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL9_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL9_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL9_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL9_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL9_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL9_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL9_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL9_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL9_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL9_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL9_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL9_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL9_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL9_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL9_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL9_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL9_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL9_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL9_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL9_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL9_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL9_t; + +/* Software event on channel select select */ +typedef enum EVSYS_SWEVENTA_enum +{ + EVSYS_SWEVENTA_CH0_gc = (0x01<<0), /* Software event on channel 0 */ + EVSYS_SWEVENTA_CH1_gc = (0x02<<0), /* Software event on channel 1 */ + EVSYS_SWEVENTA_CH2_gc = (0x04<<0), /* Software event on channel 2 */ + EVSYS_SWEVENTA_CH3_gc = (0x08<<0), /* Software event on channel 3 */ + EVSYS_SWEVENTA_CH4_gc = (0x10<<0), /* Software event on channel 4 */ + EVSYS_SWEVENTA_CH5_gc = (0x20<<0), /* Software event on channel 5 */ + EVSYS_SWEVENTA_CH6_gc = (0x40<<0), /* Software event on channel 6 */ + EVSYS_SWEVENTA_CH7_gc = (0x80<<0), /* Software event on channel 7 */ +} EVSYS_SWEVENTA_t; + +/* Software event on channel select select */ +typedef enum EVSYS_SWEVENTB_enum +{ + EVSYS_SWEVENTB_CH8_gc = (0x00<<0), /* Software event on channel 8 */ + EVSYS_SWEVENTB_CH9_gc = (0x01<<0), /* Software event on channel 9 */ +} EVSYS_SWEVENTB_t; + +/* User channel select select */ +typedef enum EVSYS_USER_enum +{ + EVSYS_USER_OFF_gc = (0x00<<0), /* Off */ + EVSYS_USER_CHANNEL0_gc = (0x01<<0), /* Connect user to event channel 0 */ + EVSYS_USER_CHANNEL1_gc = (0x02<<0), /* Connect user to event channel 1 */ + EVSYS_USER_CHANNEL2_gc = (0x03<<0), /* Connect user to event channel 2 */ + EVSYS_USER_CHANNEL3_gc = (0x04<<0), /* Connect user to event channel 3 */ + EVSYS_USER_CHANNEL4_gc = (0x05<<0), /* Connect user to event channel 4 */ + EVSYS_USER_CHANNEL5_gc = (0x06<<0), /* Connect user to event channel 5 */ + EVSYS_USER_CHANNEL6_gc = (0x07<<0), /* Connect user to event channel 6 */ + EVSYS_USER_CHANNEL7_gc = (0x08<<0), /* Connect user to event channel 7 */ + EVSYS_USER_CHANNEL8_gc = (0x09<<0), /* Connect user to event channel 8 */ + EVSYS_USER_CHANNEL9_gc = (0x0A<<0), /* Connect user to event channel 9 */ +} EVSYS_USER_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t CODESIZE; /* Code Section Size */ + register8_t BOOTSIZE; /* Boot Section Size */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DISABLE_gc = (0x00<<2), /* BOD disabled */ + ACTIVE_ENABLE_gc = (0x01<<2), /* BOD enabled in continiuous mode */ + ACTIVE_SAMPLE_gc = (0x02<<2), /* BOD enabled in sampled mode */ + ACTIVE_ENABLEWAIT_gc = (0x03<<2), /* BOD enabled in continiuous mode. Execution is halted at wake-up until BOD is running. */ +} ACTIVE_t; + +/* Frequency Select select */ +typedef enum CLKSEL_enum +{ + CLKSEL_OSCHF_gc = (0x00<<0), /* 1-32MHz internal oscillator */ + CLKSEL_OSC32K_gc = (0x01<<0), /* 32.768kHz internal oscillator */ +} CLKSEL_t; + +/* CRC Select select */ +typedef enum CRCSEL_enum +{ + CRCSEL_CRC16_gc = (0x00<<5), /* Enable CRC16 */ + CRCSEL_CRC32_gc = (0x01<<5), /* Enable CRC32 */ +} CRCSEL_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* CRC of full Flash (boot, application code and application data) */ + CRCSRC_BOOT_gc = (0x01<<6), /* CRC of boot section */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* CRC of application code and boot sections */ + CRCSRC_NOCRC_gc = (0x03<<6), /* No CRC */ +} CRCSRC_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.9V */ + LVL_BODLEVEL1_gc = (0x01<<5), /* 2.45V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.7V */ + LVL_BODLEVEL3_gc = (0x03<<5), /* 2.85V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.0s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.0s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_128Hz_gc = (0x00<<4), /* Sample frequency is 128 Hz */ + SAMPFREQ_32Hz_gc = (0x01<<4), /* Sample frequency is 32 Hz */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DISABLE_gc = (0x00<<0), /* BOD disabled */ + SLEEP_ENABLE_gc = (0x01<<0), /* BOD enabled in continiuous mode */ + SLEEP_SAMPLE_gc = (0x02<<0), /* BOD enabled in sampled mode */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.0s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.0s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +GPR - General Purpose Registers +-------------------------------------------------------------------------- +*/ + +/* General Purpose Registers */ +typedef struct GPR_struct +{ + register8_t GPR0; /* General Purpose Register 0 */ + register8_t GPR1; /* General Purpose Register 1 */ + register8_t GPR2; /* General Purpose Register 2 */ + register8_t GPR3; /* General Purpose Register 3 */ +} GPR_t; + + +/* +-------------------------------------------------------------------------- +LOCK - Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lockbits */ +typedef struct LOCK_struct +{ + _DWORDREGISTER(KEY); /* Lock Key Bits */ +} LOCK_t; + +/* Lock Key select */ +typedef enum LOCK_KEY_enum +{ + LOCK_KEY_NOLOCK_gc = (0x5CC5C55C<<0), /* No locks */ + LOCK_KEY_RWLOCK_gc = (0xA33A3AA3<<0), /* Read and write lock */ +} LOCK_KEY_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _DWORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[4]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_NOOP_gc = (0x01<<0), /* No Operation */ + NVMCTRL_CMD_FLWR_gc = (0x02<<0), /* Flash Write */ + NVMCTRL_CMD_FLPER_gc = (0x08<<0), /* Flash Page Erase */ + NVMCTRL_CMD_FLMPER2_gc = (0x09<<0), /* Flash Multi-Page Erase 2 pages */ + NVMCTRL_CMD_FLMPER4_gc = (0x0A<<0), /* Flash Multi-Page Erase 4 pages */ + NVMCTRL_CMD_FLMPER8_gc = (0x0B<<0), /* Flash Multi-Page Erase 8 pages */ + NVMCTRL_CMD_FLMPER16_gc = (0x0C<<0), /* Flash Multi-Page Erase 16 pages */ + NVMCTRL_CMD_FLMPER32_gc = (0x0D<<0), /* Flash Multi-Page Erase 32 pages */ + NVMCTRL_CMD_EEWR_gc = (0x12<<0), /* EEPROM Write */ + NVMCTRL_CMD_EEERWR_gc = (0x13<<0), /* EEPROM Erase and Write */ + NVMCTRL_CMD_EEBER_gc = (0x18<<0), /* EEPROM Byte Erase */ + NVMCTRL_CMD_EEMBER2_gc = (0x19<<0), /* EEPROM Multi-Byte Erase 2 bytes */ + NVMCTRL_CMD_EEMBER4_gc = (0x1A<<0), /* EEPROM Multi-Byte Erase 4 bytes */ + NVMCTRL_CMD_EEMBER8_gc = (0x1B<<0), /* EEPROM Multi-Byte Erase 8 bytes */ + NVMCTRL_CMD_EEMBER16_gc = (0x1C<<0), /* EEPROM Multi-Byte Erase 16 bytes */ + NVMCTRL_CMD_EEMBER32_gc = (0x1D<<0), /* EEPROM Multi-Byte Erase 32 bytes */ + NVMCTRL_CMD_CHER_gc = (0x20<<0), /* Chip Erase Command */ + NVMCTRL_CMD_EECHER_gc = (0x30<<0), /* EEPROM Erase Command */ +} NVMCTRL_CMD_t; + +/* Write error select */ +typedef enum NVMCTRL_ERROR_enum +{ + NVMCTRL_ERROR_NOERROR_gc = (0x00<<4), /* No Error */ + NVMCTRL_ERROR_ILLEGALCMD_gc = (0x01<<4), /* Write command not selected */ + NVMCTRL_ERROR_ILLEGALSADDR_gc = (0x02<<4), /* Write to section not allowed */ + NVMCTRL_ERROR_DOUBLESELECT_gc = (0x03<<4), /* Selecting new write command while write command already seleted */ + NVMCTRL_ERROR_ONGOINGPROG_gc = (0x04<<4), /* Starting a new programming operation before previous is completed */ +} NVMCTRL_ERROR_t; + +/* Flash Mapping in Data space select */ +typedef enum NVMCTRL_FLMAP_enum +{ + NVMCTRL_FLMAP_SECTION0_gc = (0x00<<4), /* Flash section 0, 0 - 32KB */ + NVMCTRL_FLMAP_SECTION1_gc = (0x01<<4), /* Flash section 1, 32 - 64KB */ + NVMCTRL_FLMAP_SECTION2_gc = (0x02<<4), /* Flash section 2, 64 - 96KB */ + NVMCTRL_FLMAP_SECTION3_gc = (0x03<<4), /* Flash section 3, 96 - 128KB */ +} NVMCTRL_FLMAP_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t PORTCTRL; /* Port Control */ + register8_t PINCONFIG; /* Pin Control Config */ + register8_t PINCTRLUPD; /* Pin Control Update */ + register8_t PINCTRLSET; /* Pin Control Set */ + register8_t PINCTRLCLR; /* Pin Control Clear */ + register8_t reserved_1[1]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t EVSYSROUTEA; /* EVSYS route A */ + register8_t CCLROUTEA; /* CCL route A */ + register8_t USARTROUTEA; /* USART route A */ + register8_t USARTROUTEB; /* USART route B */ + register8_t SPIROUTEA; /* SPI route A */ + register8_t TWIROUTEA; /* TWI route A */ + register8_t TCAROUTEA; /* TCA route A */ + register8_t TCBROUTEA; /* TCB route A */ + register8_t TCDROUTEA; /* TCD route A */ + register8_t ACROUTEA; /* AC route A */ + register8_t ZCDROUTEA; /* ZCD route A */ + register8_t reserved_1[5]; +} PORTMUX_t; + +/* Analog Comparator 0 Output select */ +typedef enum PORTMUX_AC0_enum +{ + PORTMUX_AC0_DEFAULT_gc = (0x00<<0), /* OUT on PA7 */ + PORTMUX_AC0_ALT1_gc = (0x01<<0), /* OUT on PC6 */ +} PORTMUX_AC0_t; + +/* Analog Comparator 1 Output select */ +typedef enum PORTMUX_AC1_enum +{ + PORTMUX_AC1_DEFAULT_gc = (0x00<<1), /* OUT on PA7 */ + PORTMUX_AC1_ALT1_gc = (0x01<<1), /* OUT on PC6 */ +} PORTMUX_AC1_t; + +/* Analog Comparator 2 Output select */ +typedef enum PORTMUX_AC2_enum +{ + PORTMUX_AC2_DEFAULT_gc = (0x00<<2), /* OUT on PA7 */ + PORTMUX_AC2_ALT1_gc = (0x01<<2), /* OUT on PC6 */ +} PORTMUX_AC2_t; + +/* Event Output A select */ +typedef enum PORTMUX_EVOUTA_enum +{ + PORTMUX_EVOUTA_DEFAULT_gc = (0x00<<0), /* EVOUT on PA2 */ + PORTMUX_EVOUTA_ALT1_gc = (0x01<<0), /* EVOUT on PA7 */ +} PORTMUX_EVOUTA_t; + +/* Event Output B select */ +typedef enum PORTMUX_EVOUTB_enum +{ + PORTMUX_EVOUTB_DEFAULT_gc = (0x00<<1), /* EVOUT on PB2 */ + PORTMUX_EVOUTB_ALT1_gc = (0x01<<1), /* EVOUT on PB7 */ +} PORTMUX_EVOUTB_t; + +/* Event Output C select */ +typedef enum PORTMUX_EVOUTC_enum +{ + PORTMUX_EVOUTC_DEFAULT_gc = (0x00<<2), /* EVOUT on PC2 */ + PORTMUX_EVOUTC_ALT1_gc = (0x01<<2), /* EVOUT on PC7 */ +} PORTMUX_EVOUTC_t; + +/* Event Output D select */ +typedef enum PORTMUX_EVOUTD_enum +{ + PORTMUX_EVOUTD_DEFAULT_gc = (0x00<<3), /* EVOUT on PD2 */ + PORTMUX_EVOUTD_ALT1_gc = (0x01<<3), /* EVOUT on PD7 */ +} PORTMUX_EVOUTD_t; + +/* Event Output E select */ +typedef enum PORTMUX_EVOUTE_enum +{ + PORTMUX_EVOUTE_DEFAULT_gc = (0x00<<4), /* EVOUT on PE2 */ + PORTMUX_EVOUTE_ALT1_gc = (0x01<<4), /* EVOUT on PE7 */ +} PORTMUX_EVOUTE_t; + +/* Event Output F select */ +typedef enum PORTMUX_EVOUTF_enum +{ + PORTMUX_EVOUTF_DEFAULT_gc = (0x00<<5), /* EVOUT on PF2 */ +} PORTMUX_EVOUTF_t; + +/* Event Output G select */ +typedef enum PORTMUX_EVOUTG_enum +{ + PORTMUX_EVOUTG_DEFAULT_gc = (0x00<<6), /* EVOUT on PG2 */ + PORTMUX_EVOUTG_ALT1_gc = (0x01<<6), /* EVOUT on PG7 */ +} PORTMUX_EVOUTG_t; + +/* CCL Look-Up Table 0 Signals select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<0), /* Out: PA3 In: PA0, PA1, PA2 */ + PORTMUX_LUT0_ALT1_gc = (0x01<<0), /* Out: PA6 In: PA0, PA1, PA2 */ +} PORTMUX_LUT0_t; + +/* CCL Look-Up Table 1 Signals select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<1), /* Out: PC3 In: PC0, PC1, PC2 */ + PORTMUX_LUT1_ALT1_gc = (0x01<<1), /* Out: PC6 In: PC0, PC1, PC2 */ +} PORTMUX_LUT1_t; + +/* CCL Look-Up Table 2 Signals select */ +typedef enum PORTMUX_LUT2_enum +{ + PORTMUX_LUT2_DEFAULT_gc = (0x00<<2), /* Out: PD3 In: PD0, PD1, PD2 */ + PORTMUX_LUT2_ALT1_gc = (0x01<<2), /* Out: PD6 In: PD0, PD1, PD2 */ +} PORTMUX_LUT2_t; + +/* CCL Look-Up Table 3 Signals select */ +typedef enum PORTMUX_LUT3_enum +{ + PORTMUX_LUT3_DEFAULT_gc = (0x00<<3), /* Out: PF3 In: PF0, PF1, PF2 */ +} PORTMUX_LUT3_t; + +/* CCL Look-Up Table 4 Signals select */ +typedef enum PORTMUX_LUT4_enum +{ + PORTMUX_LUT4_DEFAULT_gc = (0x00<<4), /* Out: PB3 In: PB0, PB1, PB2 */ + PORTMUX_LUT4_ALT1_gc = (0x01<<4), /* Out: PB6 In: PB0, PB1, PB2 */ +} PORTMUX_LUT4_t; + +/* CCL Look-Up Table 5 Signals select */ +typedef enum PORTMUX_LUT5_enum +{ + PORTMUX_LUT5_DEFAULT_gc = (0x00<<5), /* Out: PG3 In: PG0, PG1, PG2 */ + PORTMUX_LUT5_ALT1_gc = (0x01<<5), /* Out: PG6 In: PG0, PG1, PG2 */ +} PORTMUX_LUT5_t; + +/* SPI0 Signals select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<0), /* PA4, PA5, PA6, PA7 */ + PORTMUX_SPI0_ALT1_gc = (0x01<<0), /* PE0, PE1, PE2, PE3 */ + PORTMUX_SPI0_ALT2_gc = (0x02<<0), /* PG4, PG5, PG6, PG7 */ + PORTMUX_SPI0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_SPI0_t; + +/* SPI1 Signals select */ +typedef enum PORTMUX_SPI1_enum +{ + PORTMUX_SPI1_DEFAULT_gc = (0x00<<2), /* PC0, PC1, PC2, PC3 */ + PORTMUX_SPI1_ALT1_gc = (0x01<<2), /* PC4, PC5, PC6, PC7 */ + PORTMUX_SPI1_ALT2_gc = (0x02<<2), /* PB4, PB5, PB6, PB7 */ + PORTMUX_SPI1_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_SPI1_t; + +/* TCA0 Signals select */ +typedef enum PORTMUX_TCA0_enum +{ + PORTMUX_TCA0_PORTA_gc = (0x00<<0), /* PA0, PA1, PA2, PA3, PA4, PA5 */ + PORTMUX_TCA0_PORTB_gc = (0x01<<0), /* PB0, PB1, PB2, PB3, PB4, PB5 */ + PORTMUX_TCA0_PORTC_gc = (0x02<<0), /* PC0, PC1, PC2, PC3, PC4, PC5 */ + PORTMUX_TCA0_PORTD_gc = (0x03<<0), /* PD0, PD1, PD2, PD3, PD4, PD5 */ + PORTMUX_TCA0_PORTE_gc = (0x04<<0), /* PE0, PE1, PE2, PE3, PE4, PE5 */ + PORTMUX_TCA0_PORTF_gc = (0x05<<0), /* PF0, PF1, PF2, PF3, PF4, PF5 */ + PORTMUX_TCA0_PORTG_gc = (0x06<<0), /* PG0, PG1, PG2, PG3, PG4, PG5 */ +} PORTMUX_TCA0_t; + +/* TCB0 Output select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* WO on PA2 */ + PORTMUX_TCB0_ALT1_gc = (0x01<<0), /* WO on PF4 */ +} PORTMUX_TCB0_t; + +/* TCB1 Output select */ +typedef enum PORTMUX_TCB1_enum +{ + PORTMUX_TCB1_DEFAULT_gc = (0x00<<1), /* WO on PA3 */ + PORTMUX_TCB1_ALT1_gc = (0x01<<1), /* WO on PF5 */ +} PORTMUX_TCB1_t; + +/* TCB2 Output select */ +typedef enum PORTMUX_TCB2_enum +{ + PORTMUX_TCB2_DEFAULT_gc = (0x00<<2), /* WO on PC0 */ + PORTMUX_TCB2_ALT1_gc = (0x01<<2), /* WO on PB4 */ +} PORTMUX_TCB2_t; + +/* TCD0 Signals select */ +typedef enum PORTMUX_TCD0_enum +{ + PORTMUX_TCD0_DEFAULT_gc = (0x00<<0), /* PA4, PA5, PA6, PA7 */ + PORTMUX_TCD0_ALT1_gc = (0x01<<0), /* PB4, PB5, PB6, PB7 */ + PORTMUX_TCD0_ALT2_gc = (0x02<<0), /* PF0, PF1, PF2, PF3 */ + PORTMUX_TCD0_ALT3_gc = (0x03<<0), /* PG4, PG5, PG6, PG7 */ +} PORTMUX_TCD0_t; + +/* TWI0 Signals select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<0), /* PA2, PA3, PC2, PC3 */ + PORTMUX_TWI0_ALT1_gc = (0x01<<0), /* PA2, PA3, PC6, PC7 */ + PORTMUX_TWI0_ALT2_gc = (0x02<<0), /* PC2, PC3, PC6, PC7 */ +} PORTMUX_TWI0_t; + +/* TWI1 Signals select */ +typedef enum PORTMUX_TWI1_enum +{ + PORTMUX_TWI1_DEFAULT_gc = (0x00<<2), /* PF2, PF3, PB2, PB3 */ + PORTMUX_TWI1_ALT1_gc = (0x01<<2), /* PF2, PF3, PB6, PB7 */ + PORTMUX_TWI1_ALT2_gc = (0x02<<2), /* PB2, PB3, PB6, PB7 */ +} PORTMUX_TWI1_t; + +/* USART0 Signals select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* PA0, PA1, PA2, PA3 */ + PORTMUX_USART0_ALT1_gc = (0x01<<0), /* PA4, PA5, PA6, PA7 */ + PORTMUX_USART0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_USART0_t; + +/* USART1 Signals select */ +typedef enum PORTMUX_USART1_enum +{ + PORTMUX_USART1_DEFAULT_gc = (0x00<<2), /* PC0, PC1, PC2, PC3 */ + PORTMUX_USART1_ALT1_gc = (0x01<<2), /* PC4, PC5, PC6, PC7 */ + PORTMUX_USART1_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_USART1_t; + +/* USART2 Signals select */ +typedef enum PORTMUX_USART2_enum +{ + PORTMUX_USART2_DEFAULT_gc = (0x00<<4), /* PF0, PF1, PF2, PF3 */ + PORTMUX_USART2_ALT1_gc = (0x01<<4), /* PF4, PF5 */ + PORTMUX_USART2_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_USART2_t; + +/* Zero Cross Detector 0 Output select */ +typedef enum PORTMUX_ZCD0_enum +{ + PORTMUX_ZCD0_DEFAULT_gc = (0x00<<0), /* OUT on PA7 */ + PORTMUX_ZCD0_ALT1_gc = (0x01<<0), /* OUT on PC7 */ +} PORTMUX_ZCD0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t CALIB; /* Calibration */ + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_1[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_2[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_3[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_OSC32K_gc = (0x00<<0), /* Internal 32.768 kHz oscillator */ + RTC_CLKSEL_OSC1K_gc = (0x01<<0), /* Internal 1.024 kHz oscillator */ + RTC_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768 kHz crystal oscillator */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t reserved_1[1]; + _WORDREGISTER(TEMPSENSE0); /* Temperature Calibration 0 */ + _WORDREGISTER(TEMPSENSE1); /* Temperature Calibration 1 */ + register8_t reserved_2[8]; + register8_t SERNUM0; /* LOTNUM0 */ + register8_t SERNUM1; /* LOTNUM1 */ + register8_t SERNUM2; /* LOTNUM2 */ + register8_t SERNUM3; /* LOTNUM3 */ + register8_t SERNUM4; /* LOTNUM4 */ + register8_t SERNUM5; /* LOTNUM5 */ + register8_t SERNUM6; /* RANDOM */ + register8_t SERNUM7; /* SCRIBE */ + register8_t SERNUM8; /* XPOS0 */ + register8_t SERNUM9; /* XPOS1 */ + register8_t SERNUM10; /* YPOS0 */ + register8_t SERNUM11; /* YPOS1 */ + register8_t SERNUM12; /* RES0 */ + register8_t SERNUM13; /* RES1 */ + register8_t SERNUM14; /* RES2 */ + register8_t SERNUM15; /* RES3 */ + register8_t reserved_3[32]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t VREGCTRL; /* Control B */ +} SLPCTRL_t; + +/* Performance Mode select */ +typedef enum SLPCTRL_PMODE_enum +{ + SLPCTRL_PMODE_AUTO_gc = (0x00<<0), /* */ + SLPCTRL_PMODE_FULL_gc = (0x01<<0), /* */ +} SLPCTRL_PMODE_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t reserved_2[22]; + register8_t OCDMCTRL; /* OCD Message Control */ + register8_t OCDMSTATUS; /* OCD Message Status */ + register8_t reserved_3[6]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action A select */ +typedef enum TCA_SINGLE_EVACTA_enum +{ + TCA_SINGLE_EVACTA_CNT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACTA_CNT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACTA_CNT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACTA_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACTA_t; + +/* Event Action B select */ +typedef enum TCA_SINGLE_EVACTB_enum +{ + TCA_SINGLE_EVACTB_UPDOWN_gc = (0x03<<5), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ + TCA_SINGLE_EVACTB_RESTART_POSEDGE_gc = (0x04<<5), /* Restart counter at positive edge event */ + TCA_SINGLE_EVACTB_RESTART_ANYEDGE_gc = (0x05<<5), /* Restart counter on any edge event */ + TCA_SINGLE_EVACTB_RESTART_HIGHLVL_gc = (0x06<<5), /* Restart counter while event line is 1. */ +} TCA_SINGLE_EVACTB_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* Command Enable select */ +typedef enum TCA_SPLIT_CMDEN_enum +{ + TCA_SPLIT_CMDEN_NONE_gc = (0x00<<0), /* None */ + TCA_SPLIT_CMDEN_BOTH_gc = (0x03<<0), /* Both low byte and high byte counter */ +} TCA_SPLIT_CMDEN_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_DIV1_gc = (0x00<<1), /* CLK_PEP */ + TCB_CLKSEL_DIV2_gc = (0x01<<1), /* CLK_PER/2 */ + TCB_CLKSEL_TCA0_gc = (0x02<<1), /* Use CLK_TCA from TCA0 */ + TCB_CLKSEL_EVENT_gc = (0x07<<1), /* Count on event edge */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_OSCHF_gc = (0x00<<5), /* Internal High-Frequency Oscillator */ + TCD_CLKSEL_PLL_gc = (0x01<<5), /* PLL */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External Clock */ + TCD_CLKSEL_CLKPER_gc = (0x03<<5), /* Peripheral Clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Synchronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selected clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selected clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selected clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selected clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t DUALCTRL; /* Dual Control */ + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baud Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_1[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Input Voltage Transition Level select */ +typedef enum TWI_INPUTLVL_enum +{ + TWI_INPUTLVL_I2C_gc = (0x00<<6), /* I2C input voltage transition level */ + TWI_INPUTLVL_SMBUS_gc = (0x01<<6), /* SMBus 3.0 input voltage transition level */ +} TWI_INPUTLVL_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t CTRLD; /* Control D */ + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_1[1]; +} USART_t; + +/* Auto Baud Window select */ +typedef enum USART_ABW_enum +{ + USART_ABW_WDW0_gc = (0x00<<6), /* 18% tolerance */ + USART_ABW_WDW1_gc = (0x01<<6), /* 15% tolerance */ + USART_ABW_WDW2_gc = (0x02<<6), /* 21% tolerance */ + USART_ABW_WDW3_gc = (0x03<<6), /* 25% tolerance */ +} USART_ABW_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t ADC0REF; /* ADC0 Reference */ + register8_t reserved_1[1]; + register8_t DAC0REF; /* DAC0 Reference */ + register8_t reserved_2[1]; + register8_t ACREF; /* AC Reference */ +} VREF_t; + +/* Reference select select */ +typedef enum VREF_REFSEL_enum +{ + VREF_REFSEL_1V024_gc = (0x00<<0), /* Internal 1.024V reference */ + VREF_REFSEL_2V048_gc = (0x01<<0), /* Internal 2.048V reference */ + VREF_REFSEL_4V096_gc = (0x02<<0), /* Internal 4.096V reference */ + VREF_REFSEL_2V500_gc = (0x03<<0), /* Internal 2.500V reference */ + VREF_REFSEL_VDD_gc = (0x05<<0), /* VDD as reference */ + VREF_REFSEL_VREFA_gc = (0x06<<0), /* External referance on VREFA pin */ +} VREF_REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; + +/* +-------------------------------------------------------------------------- +ZCD - Zero Cross Detect +-------------------------------------------------------------------------- +*/ + +/* Zero Cross Detect */ +typedef struct ZCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ + register8_t reserved_2[4]; +} ZCD_t; + +/* Interrupt Mode select */ +typedef enum ZCD_INTMODE_enum +{ + ZCD_INTMODE_NONE_gc = (0x00<<0), /* No interrupt */ + ZCD_INTMODE_RISING_gc = (0x01<<0), /* Interrupt on rising input signal */ + ZCD_INTMODE_FALLING_gc = (0x02<<0), /* Interrupt on falling input signal */ + ZCD_INTMODE_BOTH_gc = (0x03<<0), /* Interrupt on both rising and falling input signal */ +} ZCD_INTMODE_t; + +/* ZCD State select */ +typedef enum ZCD_STATE_enum +{ + ZCD_STATE_LOW_gc = (0x00<<4), /* Output is 0 */ + ZCD_STATE_HIGH_gc = (0x01<<4), /* Output is 1 */ +} ZCD_STATE_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define VPORTD (*(VPORT_t *) 0x000C) /* Virtual Ports */ +#define VPORTE (*(VPORT_t *) 0x0010) /* Virtual Ports */ +#define VPORTF (*(VPORT_t *) 0x0014) /* Virtual Ports */ +#define VPORTG (*(VPORT_t *) 0x0018) /* Virtual Ports */ +#define GPR (*(GPR_t *) 0x001C) /* General Purpose Registers */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define EVSYS (*(EVSYS_t *) 0x0200) /* Event System */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0460) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0480) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x04A0) /* I/O Ports */ +#define PORTG (*(PORT_t *) 0x04C0) /* I/O Ports */ +#define PORTMUX (*(PORTMUX_t *) 0x05E0) /* Port Multiplexer */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define AC1 (*(AC_t *) 0x0688) /* Analog Comparator */ +#define AC2 (*(AC_t *) 0x0690) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x06A0) /* Digital to Analog Converter */ +#define ZCD0 (*(ZCD_t *) 0x06C0) /* Zero Cross Detect */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1 (*(USART_t *) 0x0820) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2 (*(USART_t *) 0x0840) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0900) /* Two-Wire Interface */ +#define TWI1 (*(TWI_t *) 0x0920) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0940) /* Serial Peripheral Interface */ +#define SPI1 (*(SPI_t *) 0x0960) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0B00) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0B10) /* 16-bit Timer Type B */ +#define TCB2 (*(TCB_t *) 0x0B20) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0B80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define LOCK (*(LOCK_t *) 0x1040) /* Lockbits */ +#define FUSE (*(FUSE_t *) 0x1050) /* Fuses */ +#define USERROW (*(USERROW_t *) 0x1080) /* User Row */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* VPORT (VPORTD) - Virtual Ports */ +#define VPORTD_DIR _SFR_MEM8(0x000C) +#define VPORTD_OUT _SFR_MEM8(0x000D) +#define VPORTD_IN _SFR_MEM8(0x000E) +#define VPORTD_INTFLAGS _SFR_MEM8(0x000F) + + +/* VPORT (VPORTE) - Virtual Ports */ +#define VPORTE_DIR _SFR_MEM8(0x0010) +#define VPORTE_OUT _SFR_MEM8(0x0011) +#define VPORTE_IN _SFR_MEM8(0x0012) +#define VPORTE_INTFLAGS _SFR_MEM8(0x0013) + + +/* VPORT (VPORTF) - Virtual Ports */ +#define VPORTF_DIR _SFR_MEM8(0x0014) +#define VPORTF_OUT _SFR_MEM8(0x0015) +#define VPORTF_IN _SFR_MEM8(0x0016) +#define VPORTF_INTFLAGS _SFR_MEM8(0x0017) + + +/* VPORT (VPORTG) - Virtual Ports */ +#define VPORTG_DIR _SFR_MEM8(0x0018) +#define VPORTG_OUT _SFR_MEM8(0x0019) +#define VPORTG_IN _SFR_MEM8(0x001A) +#define VPORTG_INTFLAGS _SFR_MEM8(0x001B) + + +/* GPR - General Purpose Registers */ +#define GPR_GPR0 _SFR_MEM8(0x001C) +#define GPR_GPR1 _SFR_MEM8(0x001D) +#define GPR_GPR2 _SFR_MEM8(0x001E) +#define GPR_GPR3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) +#define SLPCTRL_VREGCTRL _SFR_MEM8(0x0051) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSCHFCTRLA _SFR_MEM8(0x0068) +#define CLKCTRL_OSCHFTUNE _SFR_MEM8(0x0069) +#define CLKCTRL_PLLCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_ADC0REF _SFR_MEM8(0x00A0) +#define VREF_DAC0REF _SFR_MEM8(0x00A2) +#define VREF_ACREF _SFR_MEM8(0x00A4) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CALIB _SFR_MEM8(0x0146) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_SEQCTRL1 _SFR_MEM8(0x01C2) +#define CCL_INTCTRL0 _SFR_MEM8(0x01C5) +#define CCL_INTFLAGS _SFR_MEM8(0x01C7) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C8) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C9) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01CA) +#define CCL_TRUTH0 _SFR_MEM8(0x01CB) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01CC) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CD) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CE) +#define CCL_TRUTH1 _SFR_MEM8(0x01CF) +#define CCL_LUT2CTRLA _SFR_MEM8(0x01D0) +#define CCL_LUT2CTRLB _SFR_MEM8(0x01D1) +#define CCL_LUT2CTRLC _SFR_MEM8(0x01D2) +#define CCL_TRUTH2 _SFR_MEM8(0x01D3) +#define CCL_LUT3CTRLA _SFR_MEM8(0x01D4) +#define CCL_LUT3CTRLB _SFR_MEM8(0x01D5) +#define CCL_LUT3CTRLC _SFR_MEM8(0x01D6) +#define CCL_TRUTH3 _SFR_MEM8(0x01D7) + + +/* EVSYS - Event System */ +#define EVSYS_SWEVENTA _SFR_MEM8(0x0200) +#define EVSYS_SWEVENTB _SFR_MEM8(0x0201) +#define EVSYS_CHANNEL0 _SFR_MEM8(0x0210) +#define EVSYS_CHANNEL1 _SFR_MEM8(0x0211) +#define EVSYS_CHANNEL2 _SFR_MEM8(0x0212) +#define EVSYS_CHANNEL3 _SFR_MEM8(0x0213) +#define EVSYS_CHANNEL4 _SFR_MEM8(0x0214) +#define EVSYS_CHANNEL5 _SFR_MEM8(0x0215) +#define EVSYS_CHANNEL6 _SFR_MEM8(0x0216) +#define EVSYS_CHANNEL7 _SFR_MEM8(0x0217) +#define EVSYS_CHANNEL8 _SFR_MEM8(0x0218) +#define EVSYS_CHANNEL9 _SFR_MEM8(0x0219) +#define EVSYS_USERCCLLUT0A _SFR_MEM8(0x0220) +#define EVSYS_USERCCLLUT0B _SFR_MEM8(0x0221) +#define EVSYS_USERCCLLUT1A _SFR_MEM8(0x0222) +#define EVSYS_USERCCLLUT1B _SFR_MEM8(0x0223) +#define EVSYS_USERCCLLUT2A _SFR_MEM8(0x0224) +#define EVSYS_USERCCLLUT2B _SFR_MEM8(0x0225) +#define EVSYS_USERCCLLUT3A _SFR_MEM8(0x0226) +#define EVSYS_USERCCLLUT3B _SFR_MEM8(0x0227) +#define EVSYS_USERCCLLUT4A _SFR_MEM8(0x0228) +#define EVSYS_USERCCLLUT4B _SFR_MEM8(0x0229) +#define EVSYS_USERCCLLUT5A _SFR_MEM8(0x022A) +#define EVSYS_USERCCLLUT5B _SFR_MEM8(0x022B) +#define EVSYS_USERADC0START _SFR_MEM8(0x022C) +#define EVSYS_USERPTCSTART _SFR_MEM8(0x022D) +#define EVSYS_USEREVSYSEVOUTA _SFR_MEM8(0x022E) +#define EVSYS_USEREVSYSEVOUTB _SFR_MEM8(0x022F) +#define EVSYS_USEREVSYSEVOUTC _SFR_MEM8(0x0230) +#define EVSYS_USEREVSYSEVOUTD _SFR_MEM8(0x0231) +#define EVSYS_USEREVSYSEVOUTE _SFR_MEM8(0x0232) +#define EVSYS_USEREVSYSEVOUTF _SFR_MEM8(0x0233) +#define EVSYS_USEREVSYSEVOUTG _SFR_MEM8(0x0234) +#define EVSYS_USERUSART0IRDA _SFR_MEM8(0x0235) +#define EVSYS_USERUSART1IRDA _SFR_MEM8(0x0236) +#define EVSYS_USERUSART2IRDA _SFR_MEM8(0x0237) +#define EVSYS_USERUSART3IRDA _SFR_MEM8(0x0238) +#define EVSYS_USERUSART4IRDA _SFR_MEM8(0x0239) +#define EVSYS_USERUSART5IRDA _SFR_MEM8(0x023A) +#define EVSYS_USERTCA0CNTA _SFR_MEM8(0x023B) +#define EVSYS_USERTCA0CNTB _SFR_MEM8(0x023C) +#define EVSYS_USERTCA1CNTA _SFR_MEM8(0x023D) +#define EVSYS_USERTCA1CNTB _SFR_MEM8(0x023E) +#define EVSYS_USERTCB0CAPT _SFR_MEM8(0x023F) +#define EVSYS_USERTCB0COUNT _SFR_MEM8(0x0240) +#define EVSYS_USERTCB1CAPT _SFR_MEM8(0x0241) +#define EVSYS_USERTCB1COUNT _SFR_MEM8(0x0242) +#define EVSYS_USERTCB2CAPT _SFR_MEM8(0x0243) +#define EVSYS_USERTCB2COUNT _SFR_MEM8(0x0244) +#define EVSYS_USERTCB3CAPT _SFR_MEM8(0x0245) +#define EVSYS_USERTCB3COUNT _SFR_MEM8(0x0246) +#define EVSYS_USERTCB4CAPT _SFR_MEM8(0x0247) +#define EVSYS_USERTCB4COUNT _SFR_MEM8(0x0248) +#define EVSYS_USERTCD0INPUTA _SFR_MEM8(0x0249) +#define EVSYS_USERTCD0INPUTB _SFR_MEM8(0x024A) +#define EVSYS_USEROSCTEST _SFR_MEM8(0x024B) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PORTCTRL _SFR_MEM8(0x040A) +#define PORTA_PINCONFIG _SFR_MEM8(0x040B) +#define PORTA_PINCTRLUPD _SFR_MEM8(0x040C) +#define PORTA_PINCTRLSET _SFR_MEM8(0x040D) +#define PORTA_PINCTRLCLR _SFR_MEM8(0x040E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PORTCTRL _SFR_MEM8(0x042A) +#define PORTB_PINCONFIG _SFR_MEM8(0x042B) +#define PORTB_PINCTRLUPD _SFR_MEM8(0x042C) +#define PORTB_PINCTRLSET _SFR_MEM8(0x042D) +#define PORTB_PINCTRLCLR _SFR_MEM8(0x042E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PORTCTRL _SFR_MEM8(0x044A) +#define PORTC_PINCONFIG _SFR_MEM8(0x044B) +#define PORTC_PINCTRLUPD _SFR_MEM8(0x044C) +#define PORTC_PINCTRLSET _SFR_MEM8(0x044D) +#define PORTC_PINCTRLCLR _SFR_MEM8(0x044E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* PORT (PORTD) - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0460) +#define PORTD_DIRSET _SFR_MEM8(0x0461) +#define PORTD_DIRCLR _SFR_MEM8(0x0462) +#define PORTD_DIRTGL _SFR_MEM8(0x0463) +#define PORTD_OUT _SFR_MEM8(0x0464) +#define PORTD_OUTSET _SFR_MEM8(0x0465) +#define PORTD_OUTCLR _SFR_MEM8(0x0466) +#define PORTD_OUTTGL _SFR_MEM8(0x0467) +#define PORTD_IN _SFR_MEM8(0x0468) +#define PORTD_INTFLAGS _SFR_MEM8(0x0469) +#define PORTD_PORTCTRL _SFR_MEM8(0x046A) +#define PORTD_PINCONFIG _SFR_MEM8(0x046B) +#define PORTD_PINCTRLUPD _SFR_MEM8(0x046C) +#define PORTD_PINCTRLSET _SFR_MEM8(0x046D) +#define PORTD_PINCTRLCLR _SFR_MEM8(0x046E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0470) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0471) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0472) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0473) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0474) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0475) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0476) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0477) + + +/* PORT (PORTE) - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0480) +#define PORTE_DIRSET _SFR_MEM8(0x0481) +#define PORTE_DIRCLR _SFR_MEM8(0x0482) +#define PORTE_DIRTGL _SFR_MEM8(0x0483) +#define PORTE_OUT _SFR_MEM8(0x0484) +#define PORTE_OUTSET _SFR_MEM8(0x0485) +#define PORTE_OUTCLR _SFR_MEM8(0x0486) +#define PORTE_OUTTGL _SFR_MEM8(0x0487) +#define PORTE_IN _SFR_MEM8(0x0488) +#define PORTE_INTFLAGS _SFR_MEM8(0x0489) +#define PORTE_PORTCTRL _SFR_MEM8(0x048A) +#define PORTE_PINCONFIG _SFR_MEM8(0x048B) +#define PORTE_PINCTRLUPD _SFR_MEM8(0x048C) +#define PORTE_PINCTRLSET _SFR_MEM8(0x048D) +#define PORTE_PINCTRLCLR _SFR_MEM8(0x048E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0490) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0491) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0492) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0493) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0494) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0495) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0496) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0497) + + +/* PORT (PORTF) - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x04A0) +#define PORTF_DIRSET _SFR_MEM8(0x04A1) +#define PORTF_DIRCLR _SFR_MEM8(0x04A2) +#define PORTF_DIRTGL _SFR_MEM8(0x04A3) +#define PORTF_OUT _SFR_MEM8(0x04A4) +#define PORTF_OUTSET _SFR_MEM8(0x04A5) +#define PORTF_OUTCLR _SFR_MEM8(0x04A6) +#define PORTF_OUTTGL _SFR_MEM8(0x04A7) +#define PORTF_IN _SFR_MEM8(0x04A8) +#define PORTF_INTFLAGS _SFR_MEM8(0x04A9) +#define PORTF_PORTCTRL _SFR_MEM8(0x04AA) +#define PORTF_PINCONFIG _SFR_MEM8(0x04AB) +#define PORTF_PINCTRLUPD _SFR_MEM8(0x04AC) +#define PORTF_PINCTRLSET _SFR_MEM8(0x04AD) +#define PORTF_PINCTRLCLR _SFR_MEM8(0x04AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x04B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x04B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x04B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x04B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x04B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x04B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x04B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x04B7) + + +/* PORT (PORTG) - I/O Ports */ +#define PORTG_DIR _SFR_MEM8(0x04C0) +#define PORTG_DIRSET _SFR_MEM8(0x04C1) +#define PORTG_DIRCLR _SFR_MEM8(0x04C2) +#define PORTG_DIRTGL _SFR_MEM8(0x04C3) +#define PORTG_OUT _SFR_MEM8(0x04C4) +#define PORTG_OUTSET _SFR_MEM8(0x04C5) +#define PORTG_OUTCLR _SFR_MEM8(0x04C6) +#define PORTG_OUTTGL _SFR_MEM8(0x04C7) +#define PORTG_IN _SFR_MEM8(0x04C8) +#define PORTG_INTFLAGS _SFR_MEM8(0x04C9) +#define PORTG_PORTCTRL _SFR_MEM8(0x04CA) +#define PORTG_PINCONFIG _SFR_MEM8(0x04CB) +#define PORTG_PINCTRLUPD _SFR_MEM8(0x04CC) +#define PORTG_PINCTRLSET _SFR_MEM8(0x04CD) +#define PORTG_PINCTRLCLR _SFR_MEM8(0x04CE) +#define PORTG_PIN0CTRL _SFR_MEM8(0x04D0) +#define PORTG_PIN1CTRL _SFR_MEM8(0x04D1) +#define PORTG_PIN2CTRL _SFR_MEM8(0x04D2) +#define PORTG_PIN3CTRL _SFR_MEM8(0x04D3) +#define PORTG_PIN4CTRL _SFR_MEM8(0x04D4) +#define PORTG_PIN5CTRL _SFR_MEM8(0x04D5) +#define PORTG_PIN6CTRL _SFR_MEM8(0x04D6) +#define PORTG_PIN7CTRL _SFR_MEM8(0x04D7) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_EVSYSROUTEA _SFR_MEM8(0x05E0) +#define PORTMUX_CCLROUTEA _SFR_MEM8(0x05E1) +#define PORTMUX_USARTROUTEA _SFR_MEM8(0x05E2) +#define PORTMUX_USARTROUTEB _SFR_MEM8(0x05E3) +#define PORTMUX_SPIROUTEA _SFR_MEM8(0x05E4) +#define PORTMUX_TWIROUTEA _SFR_MEM8(0x05E5) +#define PORTMUX_TCAROUTEA _SFR_MEM8(0x05E6) +#define PORTMUX_TCBROUTEA _SFR_MEM8(0x05E7) +#define PORTMUX_TCDROUTEA _SFR_MEM8(0x05E8) +#define PORTMUX_ACROUTEA _SFR_MEM8(0x05E9) +#define PORTMUX_ZCDROUTEA _SFR_MEM8(0x05EA) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0608) +#define ADC0_MUXNEG _SFR_MEM8(0x0609) +#define ADC0_COMMAND _SFR_MEM8(0x060A) +#define ADC0_EVCTRL _SFR_MEM8(0x060B) +#define ADC0_INTCTRL _SFR_MEM8(0x060C) +#define ADC0_INTFLAGS _SFR_MEM8(0x060D) +#define ADC0_DBGCTRL _SFR_MEM8(0x060E) +#define ADC0_TEMP _SFR_MEM8(0x060F) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_CTRLB _SFR_MEM8(0x0681) +#define AC0_MUXCTRL _SFR_MEM8(0x0682) +#define AC0_DACREF _SFR_MEM8(0x0685) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* AC (AC1) - Analog Comparator */ +#define AC1_CTRLA _SFR_MEM8(0x0688) +#define AC1_CTRLB _SFR_MEM8(0x0689) +#define AC1_MUXCTRL _SFR_MEM8(0x068A) +#define AC1_DACREF _SFR_MEM8(0x068D) +#define AC1_INTCTRL _SFR_MEM8(0x068E) +#define AC1_STATUS _SFR_MEM8(0x068F) + + +/* AC (AC2) - Analog Comparator */ +#define AC2_CTRLA _SFR_MEM8(0x0690) +#define AC2_CTRLB _SFR_MEM8(0x0691) +#define AC2_MUXCTRL _SFR_MEM8(0x0692) +#define AC2_DACREF _SFR_MEM8(0x0695) +#define AC2_INTCTRL _SFR_MEM8(0x0696) +#define AC2_STATUS _SFR_MEM8(0x0697) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x06A0) +#define DAC0_DATA _SFR_MEM16(0x06A2) +#define DAC0_DATAL _SFR_MEM8(0x06A2) +#define DAC0_DATAH _SFR_MEM8(0x06A3) + + +/* ZCD (ZCD0) - Zero Cross Detect */ +#define ZCD0_CTRLA _SFR_MEM8(0x06C0) +#define ZCD0_INTCTRL _SFR_MEM8(0x06C2) +#define ZCD0_STATUS _SFR_MEM8(0x06C3) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_CTRLD _SFR_MEM8(0x080A) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* USART (USART1) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1_RXDATAL _SFR_MEM8(0x0820) +#define USART1_RXDATAH _SFR_MEM8(0x0821) +#define USART1_TXDATAL _SFR_MEM8(0x0822) +#define USART1_TXDATAH _SFR_MEM8(0x0823) +#define USART1_STATUS _SFR_MEM8(0x0824) +#define USART1_CTRLA _SFR_MEM8(0x0825) +#define USART1_CTRLB _SFR_MEM8(0x0826) +#define USART1_CTRLC _SFR_MEM8(0x0827) +#define USART1_BAUD _SFR_MEM16(0x0828) +#define USART1_BAUDL _SFR_MEM8(0x0828) +#define USART1_BAUDH _SFR_MEM8(0x0829) +#define USART1_CTRLD _SFR_MEM8(0x082A) +#define USART1_DBGCTRL _SFR_MEM8(0x082B) +#define USART1_EVCTRL _SFR_MEM8(0x082C) +#define USART1_TXPLCTRL _SFR_MEM8(0x082D) +#define USART1_RXPLCTRL _SFR_MEM8(0x082E) + + +/* USART (USART2) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2_RXDATAL _SFR_MEM8(0x0840) +#define USART2_RXDATAH _SFR_MEM8(0x0841) +#define USART2_TXDATAL _SFR_MEM8(0x0842) +#define USART2_TXDATAH _SFR_MEM8(0x0843) +#define USART2_STATUS _SFR_MEM8(0x0844) +#define USART2_CTRLA _SFR_MEM8(0x0845) +#define USART2_CTRLB _SFR_MEM8(0x0846) +#define USART2_CTRLC _SFR_MEM8(0x0847) +#define USART2_BAUD _SFR_MEM16(0x0848) +#define USART2_BAUDL _SFR_MEM8(0x0848) +#define USART2_BAUDH _SFR_MEM8(0x0849) +#define USART2_CTRLD _SFR_MEM8(0x084A) +#define USART2_DBGCTRL _SFR_MEM8(0x084B) +#define USART2_EVCTRL _SFR_MEM8(0x084C) +#define USART2_TXPLCTRL _SFR_MEM8(0x084D) +#define USART2_RXPLCTRL _SFR_MEM8(0x084E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0900) +#define TWI0_DUALCTRL _SFR_MEM8(0x0901) +#define TWI0_DBGCTRL _SFR_MEM8(0x0902) +#define TWI0_MCTRLA _SFR_MEM8(0x0903) +#define TWI0_MCTRLB _SFR_MEM8(0x0904) +#define TWI0_MSTATUS _SFR_MEM8(0x0905) +#define TWI0_MBAUD _SFR_MEM8(0x0906) +#define TWI0_MADDR _SFR_MEM8(0x0907) +#define TWI0_MDATA _SFR_MEM8(0x0908) +#define TWI0_SCTRLA _SFR_MEM8(0x0909) +#define TWI0_SCTRLB _SFR_MEM8(0x090A) +#define TWI0_SSTATUS _SFR_MEM8(0x090B) +#define TWI0_SADDR _SFR_MEM8(0x090C) +#define TWI0_SDATA _SFR_MEM8(0x090D) +#define TWI0_SADDRMASK _SFR_MEM8(0x090E) + + +/* TWI (TWI1) - Two-Wire Interface */ +#define TWI1_CTRLA _SFR_MEM8(0x0920) +#define TWI1_DUALCTRL _SFR_MEM8(0x0921) +#define TWI1_DBGCTRL _SFR_MEM8(0x0922) +#define TWI1_MCTRLA _SFR_MEM8(0x0923) +#define TWI1_MCTRLB _SFR_MEM8(0x0924) +#define TWI1_MSTATUS _SFR_MEM8(0x0925) +#define TWI1_MBAUD _SFR_MEM8(0x0926) +#define TWI1_MADDR _SFR_MEM8(0x0927) +#define TWI1_MDATA _SFR_MEM8(0x0928) +#define TWI1_SCTRLA _SFR_MEM8(0x0929) +#define TWI1_SCTRLB _SFR_MEM8(0x092A) +#define TWI1_SSTATUS _SFR_MEM8(0x092B) +#define TWI1_SADDR _SFR_MEM8(0x092C) +#define TWI1_SDATA _SFR_MEM8(0x092D) +#define TWI1_SADDRMASK _SFR_MEM8(0x092E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0940) +#define SPI0_CTRLB _SFR_MEM8(0x0941) +#define SPI0_INTCTRL _SFR_MEM8(0x0942) +#define SPI0_INTFLAGS _SFR_MEM8(0x0943) +#define SPI0_DATA _SFR_MEM8(0x0944) + + +/* SPI (SPI1) - Serial Peripheral Interface */ +#define SPI1_CTRLA _SFR_MEM8(0x0960) +#define SPI1_CTRLB _SFR_MEM8(0x0961) +#define SPI1_INTCTRL _SFR_MEM8(0x0962) +#define SPI1_INTFLAGS _SFR_MEM8(0x0963) +#define SPI1_DATA _SFR_MEM8(0x0964) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0B00) +#define TCB0_CTRLB _SFR_MEM8(0x0B01) +#define TCB0_EVCTRL _SFR_MEM8(0x0B04) +#define TCB0_INTCTRL _SFR_MEM8(0x0B05) +#define TCB0_INTFLAGS _SFR_MEM8(0x0B06) +#define TCB0_STATUS _SFR_MEM8(0x0B07) +#define TCB0_DBGCTRL _SFR_MEM8(0x0B08) +#define TCB0_TEMP _SFR_MEM8(0x0B09) +#define TCB0_CNT _SFR_MEM16(0x0B0A) +#define TCB0_CNTL _SFR_MEM8(0x0B0A) +#define TCB0_CNTH _SFR_MEM8(0x0B0B) +#define TCB0_CCMP _SFR_MEM16(0x0B0C) +#define TCB0_CCMPL _SFR_MEM8(0x0B0C) +#define TCB0_CCMPH _SFR_MEM8(0x0B0D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0B10) +#define TCB1_CTRLB _SFR_MEM8(0x0B11) +#define TCB1_EVCTRL _SFR_MEM8(0x0B14) +#define TCB1_INTCTRL _SFR_MEM8(0x0B15) +#define TCB1_INTFLAGS _SFR_MEM8(0x0B16) +#define TCB1_STATUS _SFR_MEM8(0x0B17) +#define TCB1_DBGCTRL _SFR_MEM8(0x0B18) +#define TCB1_TEMP _SFR_MEM8(0x0B19) +#define TCB1_CNT _SFR_MEM16(0x0B1A) +#define TCB1_CNTL _SFR_MEM8(0x0B1A) +#define TCB1_CNTH _SFR_MEM8(0x0B1B) +#define TCB1_CCMP _SFR_MEM16(0x0B1C) +#define TCB1_CCMPL _SFR_MEM8(0x0B1C) +#define TCB1_CCMPH _SFR_MEM8(0x0B1D) + + +/* TCB (TCB2) - 16-bit Timer Type B */ +#define TCB2_CTRLA _SFR_MEM8(0x0B20) +#define TCB2_CTRLB _SFR_MEM8(0x0B21) +#define TCB2_EVCTRL _SFR_MEM8(0x0B24) +#define TCB2_INTCTRL _SFR_MEM8(0x0B25) +#define TCB2_INTFLAGS _SFR_MEM8(0x0B26) +#define TCB2_STATUS _SFR_MEM8(0x0B27) +#define TCB2_DBGCTRL _SFR_MEM8(0x0B28) +#define TCB2_TEMP _SFR_MEM8(0x0B29) +#define TCB2_CNT _SFR_MEM16(0x0B2A) +#define TCB2_CNTL _SFR_MEM8(0x0B2A) +#define TCB2_CNTH _SFR_MEM8(0x0B2B) +#define TCB2_CCMP _SFR_MEM16(0x0B2C) +#define TCB2_CCMPL _SFR_MEM8(0x0B2C) +#define TCB2_CCMPH _SFR_MEM8(0x0B2D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0B80) +#define TCD0_CTRLB _SFR_MEM8(0x0B81) +#define TCD0_CTRLC _SFR_MEM8(0x0B82) +#define TCD0_CTRLD _SFR_MEM8(0x0B83) +#define TCD0_CTRLE _SFR_MEM8(0x0B84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0B88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0B89) +#define TCD0_INTCTRL _SFR_MEM8(0x0B8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0B8D) +#define TCD0_STATUS _SFR_MEM8(0x0B8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0B90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0B91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0B92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0B94) +#define TCD0_DLYVAL _SFR_MEM8(0x0B95) +#define TCD0_DITCTRL _SFR_MEM8(0x0B98) +#define TCD0_DITVAL _SFR_MEM8(0x0B99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0B9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0BA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0BA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0BA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0BA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0BA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0BA5) +#define TCD0_CMPASET _SFR_MEM16(0x0BA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0BA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0BA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0BAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0BAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0BAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0BAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0BAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0BAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0BAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0BAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0BAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_OCDMCTRL _SFR_MEM8(0x0F18) +#define SYSCFG_OCDMSTATUS _SFR_MEM8(0x0F19) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM32(0x1008) +#define NVMCTRL_ADDR0 _SFR_MEM8(0x1008) +#define NVMCTRL_ADDR1 _SFR_MEM8(0x1009) +#define NVMCTRL_ADDR2 _SFR_MEM8(0x100A) +#define NVMCTRL_ADDR3 _SFR_MEM8(0x100B) + + +/* LOCK - Lockbits */ +#define LOCK_KEY _SFR_MEM32(0x1040) +#define LOCK_KEY0 _SFR_MEM8(0x1040) +#define LOCK_KEY1 _SFR_MEM8(0x1041) +#define LOCK_KEY2 _SFR_MEM8(0x1042) +#define LOCK_KEY3 _SFR_MEM8(0x1043) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1050) +#define FUSE_BODCFG _SFR_MEM8(0x1051) +#define FUSE_OSCCFG _SFR_MEM8(0x1052) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1055) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1056) +#define FUSE_CODESIZE _SFR_MEM8(0x1057) +#define FUSE_BOOTSIZE _SFR_MEM8(0x1058) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1080) +#define USERROW_USERROW1 _SFR_MEM8(0x1081) +#define USERROW_USERROW2 _SFR_MEM8(0x1082) +#define USERROW_USERROW3 _SFR_MEM8(0x1083) +#define USERROW_USERROW4 _SFR_MEM8(0x1084) +#define USERROW_USERROW5 _SFR_MEM8(0x1085) +#define USERROW_USERROW6 _SFR_MEM8(0x1086) +#define USERROW_USERROW7 _SFR_MEM8(0x1087) +#define USERROW_USERROW8 _SFR_MEM8(0x1088) +#define USERROW_USERROW9 _SFR_MEM8(0x1089) +#define USERROW_USERROW10 _SFR_MEM8(0x108A) +#define USERROW_USERROW11 _SFR_MEM8(0x108B) +#define USERROW_USERROW12 _SFR_MEM8(0x108C) +#define USERROW_USERROW13 _SFR_MEM8(0x108D) +#define USERROW_USERROW14 _SFR_MEM8(0x108E) +#define USERROW_USERROW15 _SFR_MEM8(0x108F) +#define USERROW_USERROW16 _SFR_MEM8(0x1090) +#define USERROW_USERROW17 _SFR_MEM8(0x1091) +#define USERROW_USERROW18 _SFR_MEM8(0x1092) +#define USERROW_USERROW19 _SFR_MEM8(0x1093) +#define USERROW_USERROW20 _SFR_MEM8(0x1094) +#define USERROW_USERROW21 _SFR_MEM8(0x1095) +#define USERROW_USERROW22 _SFR_MEM8(0x1096) +#define USERROW_USERROW23 _SFR_MEM8(0x1097) +#define USERROW_USERROW24 _SFR_MEM8(0x1098) +#define USERROW_USERROW25 _SFR_MEM8(0x1099) +#define USERROW_USERROW26 _SFR_MEM8(0x109A) +#define USERROW_USERROW27 _SFR_MEM8(0x109B) +#define USERROW_USERROW28 _SFR_MEM8(0x109C) +#define USERROW_USERROW29 _SFR_MEM8(0x109D) +#define USERROW_USERROW30 _SFR_MEM8(0x109E) +#define USERROW_USERROW31 _SFR_MEM8(0x109F) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_TEMPSENSE0 _SFR_MEM16(0x1104) +#define SIGROW_TEMPSENSE0L _SFR_MEM8(0x1104) +#define SIGROW_TEMPSENSE0H _SFR_MEM8(0x1105) +#define SIGROW_TEMPSENSE1 _SFR_MEM16(0x1106) +#define SIGROW_TEMPSENSE1L _SFR_MEM8(0x1106) +#define SIGROW_TEMPSENSE1H _SFR_MEM8(0x1107) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1110) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1111) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1112) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1113) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1114) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1115) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1116) +#define SIGROW_SERNUM7 _SFR_MEM8(0x1117) +#define SIGROW_SERNUM8 _SFR_MEM8(0x1118) +#define SIGROW_SERNUM9 _SFR_MEM8(0x1119) +#define SIGROW_SERNUM10 _SFR_MEM8(0x111A) +#define SIGROW_SERNUM11 _SFR_MEM8(0x111B) +#define SIGROW_SERNUM12 _SFR_MEM8(0x111C) +#define SIGROW_SERNUM13 _SFR_MEM8(0x111D) +#define SIGROW_SERNUM14 _SFR_MEM8(0x111E) +#define SIGROW_SERNUM15 _SFR_MEM8(0x111F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_POWER_gm 0x18 /* Power profile group mask. */ +#define AC_POWER_gp 3 /* Power profile group position. */ +#define AC_POWER0_bm (1<<3) /* Power profile bit 0 mask. */ +#define AC_POWER0_bp 3 /* Power profile bit 0 position. */ +#define AC_POWER1_bm (1<<4) /* Power profile bit 1 mask. */ +#define AC_POWER1_bp 4 /* Power profile bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Pad Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Pad Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_WINSEL_gm 0x03 /* Window selection mode group mask. */ +#define AC_WINSEL_gp 0 /* Window selection mode group position. */ +#define AC_WINSEL0_bm (1<<0) /* Window selection mode bit 0 mask. */ +#define AC_WINSEL0_bp 0 /* Window selection mode bit 0 position. */ +#define AC_WINSEL1_bm (1<<1) /* Window selection mode bit 1 mask. */ +#define AC_WINSEL1_bp 1 /* Window selection mode bit 1 position. */ + +/* AC.MUXCTRL bit masks and bit positions */ +#define AC_MUXNEG_gm 0x07 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* Negative Input MUX Selection bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* Negative Input MUX Selection bit 2 position. */ +#define AC_MUXPOS_gm 0x38 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* Positive Input MUX Selection bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* Positive Input MUX Selection bit 2 position. */ +#define AC_INITVAL_bm 0x40 /* AC Output Initial Value bit mask. */ +#define AC_INITVAL_bp 6 /* AC Output Initial Value bit position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.DACREF bit masks and bit positions */ +#define AC_DACREF_gm 0xFF /* DACREF group mask. */ +#define AC_DACREF_gp 0 /* DACREF group position. */ +#define AC_DACREF0_bm (1<<0) /* DACREF bit 0 mask. */ +#define AC_DACREF0_bp 0 /* DACREF bit 0 position. */ +#define AC_DACREF1_bm (1<<1) /* DACREF bit 1 mask. */ +#define AC_DACREF1_bp 1 /* DACREF bit 1 position. */ +#define AC_DACREF2_bm (1<<2) /* DACREF bit 2 mask. */ +#define AC_DACREF2_bp 2 /* DACREF bit 2 position. */ +#define AC_DACREF3_bm (1<<3) /* DACREF bit 3 mask. */ +#define AC_DACREF3_bp 3 /* DACREF bit 3 position. */ +#define AC_DACREF4_bm (1<<4) /* DACREF bit 4 mask. */ +#define AC_DACREF4_bp 4 /* DACREF bit 4 position. */ +#define AC_DACREF5_bm (1<<5) /* DACREF bit 5 mask. */ +#define AC_DACREF5_bp 5 /* DACREF bit 5 position. */ +#define AC_DACREF6_bm (1<<6) /* DACREF bit 6 mask. */ +#define AC_DACREF6_bp 6 /* DACREF bit 6 position. */ +#define AC_DACREF7_bm (1<<7) /* DACREF bit 7 mask. */ +#define AC_DACREF7_bp 7 /* DACREF bit 7 position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_CMPIF_bm 0x01 /* Analog Comparator Interrupt Flag bit mask. */ +#define AC_CMPIF_bp 0 /* Analog Comparator Interrupt Flag bit position. */ +#define AC_CMPSTATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_CMPSTATE_bp 4 /* Analog Comparator State bit position. */ +#define AC_WINSTATE_gm 0xC0 /* Analog Comparator Window State group mask. */ +#define AC_WINSTATE_gp 6 /* Analog Comparator Window State group position. */ +#define AC_WINSTATE0_bm (1<<6) /* Analog Comparator Window State bit 0 mask. */ +#define AC_WINSTATE0_bp 6 /* Analog Comparator Window State bit 0 position. */ +#define AC_WINSTATE1_bm (1<<7) /* Analog Comparator Window State bit 1 mask. */ +#define AC_WINSTATE1_bp 7 /* Analog Comparator Window State bit 1 position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* Free running mode bit mask. */ +#define ADC_FREERUN_bp 1 /* Free running mode bit position. */ +#define ADC_RESSEL_gm 0x0C /* Resolution selection group mask. */ +#define ADC_RESSEL_gp 2 /* Resolution selection group position. */ +#define ADC_RESSEL0_bm (1<<2) /* Resolution selection bit 0 mask. */ +#define ADC_RESSEL0_bp 2 /* Resolution selection bit 0 position. */ +#define ADC_RESSEL1_bm (1<<3) /* Resolution selection bit 1 mask. */ +#define ADC_RESSEL1_bp 3 /* Resolution selection bit 1 position. */ +#define ADC_LEFTADJ_bm 0x10 /* Left adjust result bit mask. */ +#define ADC_LEFTADJ_bp 4 /* Left adjust result bit position. */ +#define ADC_CONVMODE_bm 0x20 /* Conversion mode bit mask. */ +#define ADC_CONVMODE_bp 5 /* Conversion mode bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x0F /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_PRESC3_bm (1<<3) /* Clock Pre-scaler bit 3 mask. */ +#define ADC_PRESC3_bp 3 /* Clock Pre-scaler bit 3 position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0xFF /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ +#define ADC_SAMPLEN5_bm (1<<5) /* Sample lenght bit 5 mask. */ +#define ADC_SAMPLEN5_bp 5 /* Sample lenght bit 5 position. */ +#define ADC_SAMPLEN6_bm (1<<6) /* Sample lenght bit 6 mask. */ +#define ADC_SAMPLEN6_bp 6 /* Sample lenght bit 6 position. */ +#define ADC_SAMPLEN7_bm (1<<7) /* Sample lenght bit 7 mask. */ +#define ADC_SAMPLEN7_bp 7 /* Sample lenght bit 7 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x7F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ +#define ADC_MUXPOS5_bm (1<<5) /* Analog Channel Selection Bits bit 5 mask. */ +#define ADC_MUXPOS5_bp 5 /* Analog Channel Selection Bits bit 5 position. */ +#define ADC_MUXPOS6_bm (1<<6) /* Analog Channel Selection Bits bit 6 mask. */ +#define ADC_MUXPOS6_bp 6 /* Analog Channel Selection Bits bit 6 position. */ + +/* ADC.MUXNEG bit masks and bit positions */ +#define ADC_MUXNEG_gm 0x7F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXNEG_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXNEG0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXNEG0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXNEG1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXNEG1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXNEG2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXNEG2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXNEG3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXNEG3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXNEG4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXNEG4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ +#define ADC_MUXNEG5_bm (1<<5) /* Analog Channel Selection Bits bit 5 mask. */ +#define ADC_MUXNEG5_bp 5 /* Analog Channel Selection Bits bit 5 position. */ +#define ADC_MUXNEG6_bm (1<<6) /* Analog Channel Selection Bits bit 6 mask. */ +#define ADC_MUXNEG6_bp 6 /* Analog Channel Selection Bits bit 6 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion bit position. */ +#define ADC_SPCONV_bm 0x02 /* Stop Conversion bit mask. */ +#define ADC_SPCONV_bp 1 /* Stop Conversion bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL0_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL0_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL00_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL00_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL01_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL01_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL02_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL02_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.SEQCTRL1 bit masks and bit positions */ +#define CCL_SEQSEL1_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL1_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL10_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL10_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL11_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL11_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL12_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL12_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.INTCTRL0 bit masks and bit positions */ +#define CCL_INTMODE0_gm 0x03 /* Interrupt Mode for LUT0 group mask. */ +#define CCL_INTMODE0_gp 0 /* Interrupt Mode for LUT0 group position. */ +#define CCL_INTMODE00_bm (1<<0) /* Interrupt Mode for LUT0 bit 0 mask. */ +#define CCL_INTMODE00_bp 0 /* Interrupt Mode for LUT0 bit 0 position. */ +#define CCL_INTMODE01_bm (1<<1) /* Interrupt Mode for LUT0 bit 1 mask. */ +#define CCL_INTMODE01_bp 1 /* Interrupt Mode for LUT0 bit 1 position. */ +#define CCL_INTMODE1_gm 0x0C /* Interrupt Mode for LUT1 group mask. */ +#define CCL_INTMODE1_gp 2 /* Interrupt Mode for LUT1 group position. */ +#define CCL_INTMODE10_bm (1<<2) /* Interrupt Mode for LUT1 bit 0 mask. */ +#define CCL_INTMODE10_bp 2 /* Interrupt Mode for LUT1 bit 0 position. */ +#define CCL_INTMODE11_bm (1<<3) /* Interrupt Mode for LUT1 bit 1 mask. */ +#define CCL_INTMODE11_bp 3 /* Interrupt Mode for LUT1 bit 1 position. */ +#define CCL_INTMODE2_gm 0x30 /* Interrupt Mode for LUT2 group mask. */ +#define CCL_INTMODE2_gp 4 /* Interrupt Mode for LUT2 group position. */ +#define CCL_INTMODE20_bm (1<<4) /* Interrupt Mode for LUT2 bit 0 mask. */ +#define CCL_INTMODE20_bp 4 /* Interrupt Mode for LUT2 bit 0 position. */ +#define CCL_INTMODE21_bm (1<<5) /* Interrupt Mode for LUT2 bit 1 mask. */ +#define CCL_INTMODE21_bp 5 /* Interrupt Mode for LUT2 bit 1 position. */ +#define CCL_INTMODE3_gm 0xC0 /* Interrupt Mode for LUT3 group mask. */ +#define CCL_INTMODE3_gp 6 /* Interrupt Mode for LUT3 group position. */ +#define CCL_INTMODE30_bm (1<<6) /* Interrupt Mode for LUT3 bit 0 mask. */ +#define CCL_INTMODE30_bp 6 /* Interrupt Mode for LUT3 bit 0 position. */ +#define CCL_INTMODE31_bm (1<<7) /* Interrupt Mode for LUT3 bit 1 mask. */ +#define CCL_INTMODE31_bp 7 /* Interrupt Mode for LUT3 bit 1 position. */ + +/* CCL.INTFLAGS bit masks and bit positions */ +#define CCL_INT_gm 0xFF /* Interrupt Flags group mask. */ +#define CCL_INT_gp 0 /* Interrupt Flags group position. */ +#define CCL_INT0_bm (1<<0) /* Interrupt Flags bit 0 mask. */ +#define CCL_INT0_bp 0 /* Interrupt Flags bit 0 position. */ +#define CCL_INT1_bm (1<<1) /* Interrupt Flags bit 1 mask. */ +#define CCL_INT1_bp 1 /* Interrupt Flags bit 1 position. */ +#define CCL_INT2_bm (1<<2) /* Interrupt Flags bit 2 mask. */ +#define CCL_INT2_bp 2 /* Interrupt Flags bit 2 position. */ +#define CCL_INT3_bm (1<<3) /* Interrupt Flags bit 3 mask. */ +#define CCL_INT3_bp 3 /* Interrupt Flags bit 3 position. */ +#define CCL_INT4_bm (1<<4) /* Interrupt Flags bit 4 mask. */ +#define CCL_INT4_bp 4 /* Interrupt Flags bit 4 position. */ +#define CCL_INT5_bm (1<<5) /* Interrupt Flags bit 5 mask. */ +#define CCL_INT5_bp 5 /* Interrupt Flags bit 5 position. */ +#define CCL_INT6_bm (1<<6) /* Interrupt Flags bit 6 mask. */ +#define CCL_INT6_bp 6 /* Interrupt Flags bit 6 position. */ +#define CCL_INT7_bm (1<<7) /* Interrupt Flags bit 7 mask. */ +#define CCL_INT7_bp 7 /* Interrupt Flags bit 7 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_CLKSRC_gm 0x0E /* Clock Source Selection group mask. */ +#define CCL_CLKSRC_gp 1 /* Clock Source Selection group position. */ +#define CCL_CLKSRC0_bm (1<<1) /* Clock Source Selection bit 0 mask. */ +#define CCL_CLKSRC0_bp 1 /* Clock Source Selection bit 0 position. */ +#define CCL_CLKSRC1_bm (1<<2) /* Clock Source Selection bit 1 mask. */ +#define CCL_CLKSRC1_bp 2 /* Clock Source Selection bit 1 position. */ +#define CCL_CLKSRC2_bm (1<<3) /* Clock Source Selection bit 2 mask. */ +#define CCL_CLKSRC2_bp 3 /* Clock Source Selection bit 2 position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_OUTEN_bm 0x40 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 6 /* Output Enable bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT2CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT2CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT2CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT3CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT3CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT3CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x07 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKSEL2_bm (1<<2) /* clock select bit 2 mask. */ +#define CLKCTRL_CLKSEL2_bp 2 /* clock select bit 2 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSCHFS_bm 0x02 /* High frequency oscillator status bit mask. */ +#define CLKCTRL_OSCHFS_bp 1 /* High frequency oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x04 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 2 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x08 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 3 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x10 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 4 /* External Clock status bit position. */ +#define CLKCTRL_PLLS_bm 0x20 /* PLL oscillator status bit mask. */ +#define CLKCTRL_PLLS_bp 5 /* PLL oscillator status bit position. */ + +/* CLKCTRL.OSCHFCTRLA bit masks and bit positions */ +#define CLKCTRL_AUTOTUNE_bm 0x01 /* Autotune bit mask. */ +#define CLKCTRL_AUTOTUNE_bp 0 /* Autotune bit position. */ +#define CLKCTRL_FREQSEL_gm 0x3C /* Frequency select group mask. */ +#define CLKCTRL_FREQSEL_gp 2 /* Frequency select group position. */ +#define CLKCTRL_FREQSEL0_bm (1<<2) /* Frequency select bit 0 mask. */ +#define CLKCTRL_FREQSEL0_bp 2 /* Frequency select bit 0 position. */ +#define CLKCTRL_FREQSEL1_bm (1<<3) /* Frequency select bit 1 mask. */ +#define CLKCTRL_FREQSEL1_bp 3 /* Frequency select bit 1 position. */ +#define CLKCTRL_FREQSEL2_bm (1<<4) /* Frequency select bit 2 mask. */ +#define CLKCTRL_FREQSEL2_bp 4 /* Frequency select bit 2 position. */ +#define CLKCTRL_FREQSEL3_bm (1<<5) /* Frequency select bit 3 mask. */ +#define CLKCTRL_FREQSEL3_bp 5 /* Frequency select bit 3 position. */ +#define CLKCTRL_RUNSTDBY_bm 0x80 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 7 /* Run standby bit position. */ + +/* CLKCTRL.OSCHFTUNE bit masks and bit positions */ +#define CLKCTRL_TUNE_gm 0xFF /* Tune group mask. */ +#define CLKCTRL_TUNE_gp 0 /* Tune group position. */ +#define CLKCTRL_TUNE0_bm (1<<0) /* Tune bit 0 mask. */ +#define CLKCTRL_TUNE0_bp 0 /* Tune bit 0 position. */ +#define CLKCTRL_TUNE1_bm (1<<1) /* Tune bit 1 mask. */ +#define CLKCTRL_TUNE1_bp 1 /* Tune bit 1 position. */ +#define CLKCTRL_TUNE2_bm (1<<2) /* Tune bit 2 mask. */ +#define CLKCTRL_TUNE2_bp 2 /* Tune bit 2 position. */ +#define CLKCTRL_TUNE3_bm (1<<3) /* Tune bit 3 mask. */ +#define CLKCTRL_TUNE3_bp 3 /* Tune bit 3 position. */ +#define CLKCTRL_TUNE4_bm (1<<4) /* Tune bit 4 mask. */ +#define CLKCTRL_TUNE4_bp 4 /* Tune bit 4 position. */ +#define CLKCTRL_TUNE5_bm (1<<5) /* Tune bit 5 mask. */ +#define CLKCTRL_TUNE5_bp 5 /* Tune bit 5 position. */ +#define CLKCTRL_TUNE6_bm (1<<6) /* Tune bit 6 mask. */ +#define CLKCTRL_TUNE6_bp 6 /* Tune bit 6 position. */ +#define CLKCTRL_TUNE7_bm (1<<7) /* Tune bit 7 mask. */ +#define CLKCTRL_TUNE7_bp 7 /* Tune bit 7 position. */ + +/* CLKCTRL.PLLCTRLA bit masks and bit positions */ +#define CLKCTRL_MULFAC_gm 0x03 /* Multiplication factor group mask. */ +#define CLKCTRL_MULFAC_gp 0 /* Multiplication factor group position. */ +#define CLKCTRL_MULFAC0_bm (1<<0) /* Multiplication factor bit 0 mask. */ +#define CLKCTRL_MULFAC0_bp 0 /* Multiplication factor bit 0 position. */ +#define CLKCTRL_MULFAC1_bm (1<<1) /* Multiplication factor bit 1 mask. */ +#define CLKCTRL_MULFAC1_bp 1 /* Multiplication factor bit 1 position. */ +#define CLKCTRL_SOURCE_bm 0x10 /* Source bit mask. */ +#define CLKCTRL_SOURCE_bp 4 /* Source bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +#define CLKCTRL_LPMODE_bm 0x02 /* Low power mode bit mask. */ +#define CLKCTRL_LPMODE_bp 1 /* Low power mode bit position. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* DAC.DATA bit masks and bit positions */ +#define DAC_DATA_gm 0xFFC0 /* Data group mask. */ +#define DAC_DATA_gp 6 /* Data group position. */ +#define DAC_DATA0_bm (1<<6) /* Data bit 0 mask. */ +#define DAC_DATA0_bp 6 /* Data bit 0 position. */ +#define DAC_DATA1_bm (1<<7) /* Data bit 1 mask. */ +#define DAC_DATA1_bp 7 /* Data bit 1 position. */ +#define DAC_DATA2_bm (1<<8) /* Data bit 2 mask. */ +#define DAC_DATA2_bp 8 /* Data bit 2 position. */ +#define DAC_DATA3_bm (1<<9) /* Data bit 3 mask. */ +#define DAC_DATA3_bp 9 /* Data bit 3 position. */ +#define DAC_DATA4_bm (1<<10) /* Data bit 4 mask. */ +#define DAC_DATA4_bp 10 /* Data bit 4 position. */ +#define DAC_DATA5_bm (1<<11) /* Data bit 5 mask. */ +#define DAC_DATA5_bp 11 /* Data bit 5 position. */ +#define DAC_DATA6_bm (1<<12) /* Data bit 6 mask. */ +#define DAC_DATA6_bp 12 /* Data bit 6 position. */ +#define DAC_DATA7_bm (1<<13) /* Data bit 7 mask. */ +#define DAC_DATA7_bp 13 /* Data bit 7 position. */ +#define DAC_DATA8_bm (1<<14) /* Data bit 8 mask. */ +#define DAC_DATA8_bp 14 /* Data bit 8 position. */ +#define DAC_DATA9_bm (1<<15) /* Data bit 9 mask. */ +#define DAC_DATA9_bp 15 /* Data bit 9 position. */ + +/* EVSYS - Event System */ +/* EVSYS.SWEVENTA bit masks and bit positions */ +#define EVSYS_SWEVENTA_gm 0xFF /* Software event on channel select group mask. */ +#define EVSYS_SWEVENTA_gp 0 /* Software event on channel select group position. */ +#define EVSYS_SWEVENTA0_bm (1<<0) /* Software event on channel select bit 0 mask. */ +#define EVSYS_SWEVENTA0_bp 0 /* Software event on channel select bit 0 position. */ +#define EVSYS_SWEVENTA1_bm (1<<1) /* Software event on channel select bit 1 mask. */ +#define EVSYS_SWEVENTA1_bp 1 /* Software event on channel select bit 1 position. */ +#define EVSYS_SWEVENTA2_bm (1<<2) /* Software event on channel select bit 2 mask. */ +#define EVSYS_SWEVENTA2_bp 2 /* Software event on channel select bit 2 position. */ +#define EVSYS_SWEVENTA3_bm (1<<3) /* Software event on channel select bit 3 mask. */ +#define EVSYS_SWEVENTA3_bp 3 /* Software event on channel select bit 3 position. */ +#define EVSYS_SWEVENTA4_bm (1<<4) /* Software event on channel select bit 4 mask. */ +#define EVSYS_SWEVENTA4_bp 4 /* Software event on channel select bit 4 position. */ +#define EVSYS_SWEVENTA5_bm (1<<5) /* Software event on channel select bit 5 mask. */ +#define EVSYS_SWEVENTA5_bp 5 /* Software event on channel select bit 5 position. */ +#define EVSYS_SWEVENTA6_bm (1<<6) /* Software event on channel select bit 6 mask. */ +#define EVSYS_SWEVENTA6_bp 6 /* Software event on channel select bit 6 position. */ +#define EVSYS_SWEVENTA7_bm (1<<7) /* Software event on channel select bit 7 mask. */ +#define EVSYS_SWEVENTA7_bp 7 /* Software event on channel select bit 7 position. */ + +/* EVSYS.SWEVENTB bit masks and bit positions */ +#define EVSYS_SWEVENTB_gm 0x03 /* Software event on channel select group mask. */ +#define EVSYS_SWEVENTB_gp 0 /* Software event on channel select group position. */ +#define EVSYS_SWEVENTB0_bm (1<<0) /* Software event on channel select bit 0 mask. */ +#define EVSYS_SWEVENTB0_bp 0 /* Software event on channel select bit 0 position. */ +#define EVSYS_SWEVENTB1_bm (1<<1) /* Software event on channel select bit 1 mask. */ +#define EVSYS_SWEVENTB1_bp 1 /* Software event on channel select bit 1 position. */ + +/* EVSYS.CHANNEL0 bit masks and bit positions */ +#define EVSYS_CHANNEL0_gm 0xFF /* Channel 0 generator select group mask. */ +#define EVSYS_CHANNEL0_gp 0 /* Channel 0 generator select group position. */ +#define EVSYS_CHANNEL00_bm (1<<0) /* Channel 0 generator select bit 0 mask. */ +#define EVSYS_CHANNEL00_bp 0 /* Channel 0 generator select bit 0 position. */ +#define EVSYS_CHANNEL01_bm (1<<1) /* Channel 0 generator select bit 1 mask. */ +#define EVSYS_CHANNEL01_bp 1 /* Channel 0 generator select bit 1 position. */ +#define EVSYS_CHANNEL02_bm (1<<2) /* Channel 0 generator select bit 2 mask. */ +#define EVSYS_CHANNEL02_bp 2 /* Channel 0 generator select bit 2 position. */ +#define EVSYS_CHANNEL03_bm (1<<3) /* Channel 0 generator select bit 3 mask. */ +#define EVSYS_CHANNEL03_bp 3 /* Channel 0 generator select bit 3 position. */ +#define EVSYS_CHANNEL04_bm (1<<4) /* Channel 0 generator select bit 4 mask. */ +#define EVSYS_CHANNEL04_bp 4 /* Channel 0 generator select bit 4 position. */ +#define EVSYS_CHANNEL05_bm (1<<5) /* Channel 0 generator select bit 5 mask. */ +#define EVSYS_CHANNEL05_bp 5 /* Channel 0 generator select bit 5 position. */ +#define EVSYS_CHANNEL06_bm (1<<6) /* Channel 0 generator select bit 6 mask. */ +#define EVSYS_CHANNEL06_bp 6 /* Channel 0 generator select bit 6 position. */ +#define EVSYS_CHANNEL07_bm (1<<7) /* Channel 0 generator select bit 7 mask. */ +#define EVSYS_CHANNEL07_bp 7 /* Channel 0 generator select bit 7 position. */ + +/* EVSYS.CHANNEL1 bit masks and bit positions */ +#define EVSYS_CHANNEL1_gm 0xFF /* Channel 1 generator select group mask. */ +#define EVSYS_CHANNEL1_gp 0 /* Channel 1 generator select group position. */ +#define EVSYS_CHANNEL10_bm (1<<0) /* Channel 1 generator select bit 0 mask. */ +#define EVSYS_CHANNEL10_bp 0 /* Channel 1 generator select bit 0 position. */ +#define EVSYS_CHANNEL11_bm (1<<1) /* Channel 1 generator select bit 1 mask. */ +#define EVSYS_CHANNEL11_bp 1 /* Channel 1 generator select bit 1 position. */ +#define EVSYS_CHANNEL12_bm (1<<2) /* Channel 1 generator select bit 2 mask. */ +#define EVSYS_CHANNEL12_bp 2 /* Channel 1 generator select bit 2 position. */ +#define EVSYS_CHANNEL13_bm (1<<3) /* Channel 1 generator select bit 3 mask. */ +#define EVSYS_CHANNEL13_bp 3 /* Channel 1 generator select bit 3 position. */ +#define EVSYS_CHANNEL14_bm (1<<4) /* Channel 1 generator select bit 4 mask. */ +#define EVSYS_CHANNEL14_bp 4 /* Channel 1 generator select bit 4 position. */ +#define EVSYS_CHANNEL15_bm (1<<5) /* Channel 1 generator select bit 5 mask. */ +#define EVSYS_CHANNEL15_bp 5 /* Channel 1 generator select bit 5 position. */ +#define EVSYS_CHANNEL16_bm (1<<6) /* Channel 1 generator select bit 6 mask. */ +#define EVSYS_CHANNEL16_bp 6 /* Channel 1 generator select bit 6 position. */ +#define EVSYS_CHANNEL17_bm (1<<7) /* Channel 1 generator select bit 7 mask. */ +#define EVSYS_CHANNEL17_bp 7 /* Channel 1 generator select bit 7 position. */ + +/* EVSYS.CHANNEL2 bit masks and bit positions */ +#define EVSYS_CHANNEL2_gm 0xFF /* Channel 2 generator select group mask. */ +#define EVSYS_CHANNEL2_gp 0 /* Channel 2 generator select group position. */ +#define EVSYS_CHANNEL20_bm (1<<0) /* Channel 2 generator select bit 0 mask. */ +#define EVSYS_CHANNEL20_bp 0 /* Channel 2 generator select bit 0 position. */ +#define EVSYS_CHANNEL21_bm (1<<1) /* Channel 2 generator select bit 1 mask. */ +#define EVSYS_CHANNEL21_bp 1 /* Channel 2 generator select bit 1 position. */ +#define EVSYS_CHANNEL22_bm (1<<2) /* Channel 2 generator select bit 2 mask. */ +#define EVSYS_CHANNEL22_bp 2 /* Channel 2 generator select bit 2 position. */ +#define EVSYS_CHANNEL23_bm (1<<3) /* Channel 2 generator select bit 3 mask. */ +#define EVSYS_CHANNEL23_bp 3 /* Channel 2 generator select bit 3 position. */ +#define EVSYS_CHANNEL24_bm (1<<4) /* Channel 2 generator select bit 4 mask. */ +#define EVSYS_CHANNEL24_bp 4 /* Channel 2 generator select bit 4 position. */ +#define EVSYS_CHANNEL25_bm (1<<5) /* Channel 2 generator select bit 5 mask. */ +#define EVSYS_CHANNEL25_bp 5 /* Channel 2 generator select bit 5 position. */ +#define EVSYS_CHANNEL26_bm (1<<6) /* Channel 2 generator select bit 6 mask. */ +#define EVSYS_CHANNEL26_bp 6 /* Channel 2 generator select bit 6 position. */ +#define EVSYS_CHANNEL27_bm (1<<7) /* Channel 2 generator select bit 7 mask. */ +#define EVSYS_CHANNEL27_bp 7 /* Channel 2 generator select bit 7 position. */ + +/* EVSYS.CHANNEL3 bit masks and bit positions */ +#define EVSYS_CHANNEL3_gm 0xFF /* Channel 3 generator select group mask. */ +#define EVSYS_CHANNEL3_gp 0 /* Channel 3 generator select group position. */ +#define EVSYS_CHANNEL30_bm (1<<0) /* Channel 3 generator select bit 0 mask. */ +#define EVSYS_CHANNEL30_bp 0 /* Channel 3 generator select bit 0 position. */ +#define EVSYS_CHANNEL31_bm (1<<1) /* Channel 3 generator select bit 1 mask. */ +#define EVSYS_CHANNEL31_bp 1 /* Channel 3 generator select bit 1 position. */ +#define EVSYS_CHANNEL32_bm (1<<2) /* Channel 3 generator select bit 2 mask. */ +#define EVSYS_CHANNEL32_bp 2 /* Channel 3 generator select bit 2 position. */ +#define EVSYS_CHANNEL33_bm (1<<3) /* Channel 3 generator select bit 3 mask. */ +#define EVSYS_CHANNEL33_bp 3 /* Channel 3 generator select bit 3 position. */ +#define EVSYS_CHANNEL34_bm (1<<4) /* Channel 3 generator select bit 4 mask. */ +#define EVSYS_CHANNEL34_bp 4 /* Channel 3 generator select bit 4 position. */ +#define EVSYS_CHANNEL35_bm (1<<5) /* Channel 3 generator select bit 5 mask. */ +#define EVSYS_CHANNEL35_bp 5 /* Channel 3 generator select bit 5 position. */ +#define EVSYS_CHANNEL36_bm (1<<6) /* Channel 3 generator select bit 6 mask. */ +#define EVSYS_CHANNEL36_bp 6 /* Channel 3 generator select bit 6 position. */ +#define EVSYS_CHANNEL37_bm (1<<7) /* Channel 3 generator select bit 7 mask. */ +#define EVSYS_CHANNEL37_bp 7 /* Channel 3 generator select bit 7 position. */ + +/* EVSYS.CHANNEL4 bit masks and bit positions */ +#define EVSYS_CHANNEL4_gm 0xFF /* Channel 4 generator select group mask. */ +#define EVSYS_CHANNEL4_gp 0 /* Channel 4 generator select group position. */ +#define EVSYS_CHANNEL40_bm (1<<0) /* Channel 4 generator select bit 0 mask. */ +#define EVSYS_CHANNEL40_bp 0 /* Channel 4 generator select bit 0 position. */ +#define EVSYS_CHANNEL41_bm (1<<1) /* Channel 4 generator select bit 1 mask. */ +#define EVSYS_CHANNEL41_bp 1 /* Channel 4 generator select bit 1 position. */ +#define EVSYS_CHANNEL42_bm (1<<2) /* Channel 4 generator select bit 2 mask. */ +#define EVSYS_CHANNEL42_bp 2 /* Channel 4 generator select bit 2 position. */ +#define EVSYS_CHANNEL43_bm (1<<3) /* Channel 4 generator select bit 3 mask. */ +#define EVSYS_CHANNEL43_bp 3 /* Channel 4 generator select bit 3 position. */ +#define EVSYS_CHANNEL44_bm (1<<4) /* Channel 4 generator select bit 4 mask. */ +#define EVSYS_CHANNEL44_bp 4 /* Channel 4 generator select bit 4 position. */ +#define EVSYS_CHANNEL45_bm (1<<5) /* Channel 4 generator select bit 5 mask. */ +#define EVSYS_CHANNEL45_bp 5 /* Channel 4 generator select bit 5 position. */ +#define EVSYS_CHANNEL46_bm (1<<6) /* Channel 4 generator select bit 6 mask. */ +#define EVSYS_CHANNEL46_bp 6 /* Channel 4 generator select bit 6 position. */ +#define EVSYS_CHANNEL47_bm (1<<7) /* Channel 4 generator select bit 7 mask. */ +#define EVSYS_CHANNEL47_bp 7 /* Channel 4 generator select bit 7 position. */ + +/* EVSYS.CHANNEL5 bit masks and bit positions */ +#define EVSYS_CHANNEL5_gm 0xFF /* Channel 5 generator select group mask. */ +#define EVSYS_CHANNEL5_gp 0 /* Channel 5 generator select group position. */ +#define EVSYS_CHANNEL50_bm (1<<0) /* Channel 5 generator select bit 0 mask. */ +#define EVSYS_CHANNEL50_bp 0 /* Channel 5 generator select bit 0 position. */ +#define EVSYS_CHANNEL51_bm (1<<1) /* Channel 5 generator select bit 1 mask. */ +#define EVSYS_CHANNEL51_bp 1 /* Channel 5 generator select bit 1 position. */ +#define EVSYS_CHANNEL52_bm (1<<2) /* Channel 5 generator select bit 2 mask. */ +#define EVSYS_CHANNEL52_bp 2 /* Channel 5 generator select bit 2 position. */ +#define EVSYS_CHANNEL53_bm (1<<3) /* Channel 5 generator select bit 3 mask. */ +#define EVSYS_CHANNEL53_bp 3 /* Channel 5 generator select bit 3 position. */ +#define EVSYS_CHANNEL54_bm (1<<4) /* Channel 5 generator select bit 4 mask. */ +#define EVSYS_CHANNEL54_bp 4 /* Channel 5 generator select bit 4 position. */ +#define EVSYS_CHANNEL55_bm (1<<5) /* Channel 5 generator select bit 5 mask. */ +#define EVSYS_CHANNEL55_bp 5 /* Channel 5 generator select bit 5 position. */ +#define EVSYS_CHANNEL56_bm (1<<6) /* Channel 5 generator select bit 6 mask. */ +#define EVSYS_CHANNEL56_bp 6 /* Channel 5 generator select bit 6 position. */ +#define EVSYS_CHANNEL57_bm (1<<7) /* Channel 5 generator select bit 7 mask. */ +#define EVSYS_CHANNEL57_bp 7 /* Channel 5 generator select bit 7 position. */ + +/* EVSYS.CHANNEL6 bit masks and bit positions */ +#define EVSYS_CHANNEL6_gm 0xFF /* Channel 6 generator select group mask. */ +#define EVSYS_CHANNEL6_gp 0 /* Channel 6 generator select group position. */ +#define EVSYS_CHANNEL60_bm (1<<0) /* Channel 6 generator select bit 0 mask. */ +#define EVSYS_CHANNEL60_bp 0 /* Channel 6 generator select bit 0 position. */ +#define EVSYS_CHANNEL61_bm (1<<1) /* Channel 6 generator select bit 1 mask. */ +#define EVSYS_CHANNEL61_bp 1 /* Channel 6 generator select bit 1 position. */ +#define EVSYS_CHANNEL62_bm (1<<2) /* Channel 6 generator select bit 2 mask. */ +#define EVSYS_CHANNEL62_bp 2 /* Channel 6 generator select bit 2 position. */ +#define EVSYS_CHANNEL63_bm (1<<3) /* Channel 6 generator select bit 3 mask. */ +#define EVSYS_CHANNEL63_bp 3 /* Channel 6 generator select bit 3 position. */ +#define EVSYS_CHANNEL64_bm (1<<4) /* Channel 6 generator select bit 4 mask. */ +#define EVSYS_CHANNEL64_bp 4 /* Channel 6 generator select bit 4 position. */ +#define EVSYS_CHANNEL65_bm (1<<5) /* Channel 6 generator select bit 5 mask. */ +#define EVSYS_CHANNEL65_bp 5 /* Channel 6 generator select bit 5 position. */ +#define EVSYS_CHANNEL66_bm (1<<6) /* Channel 6 generator select bit 6 mask. */ +#define EVSYS_CHANNEL66_bp 6 /* Channel 6 generator select bit 6 position. */ +#define EVSYS_CHANNEL67_bm (1<<7) /* Channel 6 generator select bit 7 mask. */ +#define EVSYS_CHANNEL67_bp 7 /* Channel 6 generator select bit 7 position. */ + +/* EVSYS.CHANNEL7 bit masks and bit positions */ +#define EVSYS_CHANNEL7_gm 0xFF /* Channel 7 generator select group mask. */ +#define EVSYS_CHANNEL7_gp 0 /* Channel 7 generator select group position. */ +#define EVSYS_CHANNEL70_bm (1<<0) /* Channel 7 generator select bit 0 mask. */ +#define EVSYS_CHANNEL70_bp 0 /* Channel 7 generator select bit 0 position. */ +#define EVSYS_CHANNEL71_bm (1<<1) /* Channel 7 generator select bit 1 mask. */ +#define EVSYS_CHANNEL71_bp 1 /* Channel 7 generator select bit 1 position. */ +#define EVSYS_CHANNEL72_bm (1<<2) /* Channel 7 generator select bit 2 mask. */ +#define EVSYS_CHANNEL72_bp 2 /* Channel 7 generator select bit 2 position. */ +#define EVSYS_CHANNEL73_bm (1<<3) /* Channel 7 generator select bit 3 mask. */ +#define EVSYS_CHANNEL73_bp 3 /* Channel 7 generator select bit 3 position. */ +#define EVSYS_CHANNEL74_bm (1<<4) /* Channel 7 generator select bit 4 mask. */ +#define EVSYS_CHANNEL74_bp 4 /* Channel 7 generator select bit 4 position. */ +#define EVSYS_CHANNEL75_bm (1<<5) /* Channel 7 generator select bit 5 mask. */ +#define EVSYS_CHANNEL75_bp 5 /* Channel 7 generator select bit 5 position. */ +#define EVSYS_CHANNEL76_bm (1<<6) /* Channel 7 generator select bit 6 mask. */ +#define EVSYS_CHANNEL76_bp 6 /* Channel 7 generator select bit 6 position. */ +#define EVSYS_CHANNEL77_bm (1<<7) /* Channel 7 generator select bit 7 mask. */ +#define EVSYS_CHANNEL77_bp 7 /* Channel 7 generator select bit 7 position. */ + +/* EVSYS.CHANNEL8 bit masks and bit positions */ +#define EVSYS_CHANNEL8_gm 0xFF /* Channel 8 generator select group mask. */ +#define EVSYS_CHANNEL8_gp 0 /* Channel 8 generator select group position. */ +#define EVSYS_CHANNEL80_bm (1<<0) /* Channel 8 generator select bit 0 mask. */ +#define EVSYS_CHANNEL80_bp 0 /* Channel 8 generator select bit 0 position. */ +#define EVSYS_CHANNEL81_bm (1<<1) /* Channel 8 generator select bit 1 mask. */ +#define EVSYS_CHANNEL81_bp 1 /* Channel 8 generator select bit 1 position. */ +#define EVSYS_CHANNEL82_bm (1<<2) /* Channel 8 generator select bit 2 mask. */ +#define EVSYS_CHANNEL82_bp 2 /* Channel 8 generator select bit 2 position. */ +#define EVSYS_CHANNEL83_bm (1<<3) /* Channel 8 generator select bit 3 mask. */ +#define EVSYS_CHANNEL83_bp 3 /* Channel 8 generator select bit 3 position. */ +#define EVSYS_CHANNEL84_bm (1<<4) /* Channel 8 generator select bit 4 mask. */ +#define EVSYS_CHANNEL84_bp 4 /* Channel 8 generator select bit 4 position. */ +#define EVSYS_CHANNEL85_bm (1<<5) /* Channel 8 generator select bit 5 mask. */ +#define EVSYS_CHANNEL85_bp 5 /* Channel 8 generator select bit 5 position. */ +#define EVSYS_CHANNEL86_bm (1<<6) /* Channel 8 generator select bit 6 mask. */ +#define EVSYS_CHANNEL86_bp 6 /* Channel 8 generator select bit 6 position. */ +#define EVSYS_CHANNEL87_bm (1<<7) /* Channel 8 generator select bit 7 mask. */ +#define EVSYS_CHANNEL87_bp 7 /* Channel 8 generator select bit 7 position. */ + +/* EVSYS.CHANNEL9 bit masks and bit positions */ +#define EVSYS_CHANNEL9_gm 0xFF /* Channel 9 generator select group mask. */ +#define EVSYS_CHANNEL9_gp 0 /* Channel 9 generator select group position. */ +#define EVSYS_CHANNEL90_bm (1<<0) /* Channel 9 generator select bit 0 mask. */ +#define EVSYS_CHANNEL90_bp 0 /* Channel 9 generator select bit 0 position. */ +#define EVSYS_CHANNEL91_bm (1<<1) /* Channel 9 generator select bit 1 mask. */ +#define EVSYS_CHANNEL91_bp 1 /* Channel 9 generator select bit 1 position. */ +#define EVSYS_CHANNEL92_bm (1<<2) /* Channel 9 generator select bit 2 mask. */ +#define EVSYS_CHANNEL92_bp 2 /* Channel 9 generator select bit 2 position. */ +#define EVSYS_CHANNEL93_bm (1<<3) /* Channel 9 generator select bit 3 mask. */ +#define EVSYS_CHANNEL93_bp 3 /* Channel 9 generator select bit 3 position. */ +#define EVSYS_CHANNEL94_bm (1<<4) /* Channel 9 generator select bit 4 mask. */ +#define EVSYS_CHANNEL94_bp 4 /* Channel 9 generator select bit 4 position. */ +#define EVSYS_CHANNEL95_bm (1<<5) /* Channel 9 generator select bit 5 mask. */ +#define EVSYS_CHANNEL95_bp 5 /* Channel 9 generator select bit 5 position. */ +#define EVSYS_CHANNEL96_bm (1<<6) /* Channel 9 generator select bit 6 mask. */ +#define EVSYS_CHANNEL96_bp 6 /* Channel 9 generator select bit 6 position. */ +#define EVSYS_CHANNEL97_bm (1<<7) /* Channel 9 generator select bit 7 mask. */ +#define EVSYS_CHANNEL97_bp 7 /* Channel 9 generator select bit 7 position. */ + +/* EVSYS.USERCCLLUT0A bit masks and bit positions */ +#define EVSYS_USER_gm 0xFF /* User channel select group mask. */ +#define EVSYS_USER_gp 0 /* User channel select group position. */ +#define EVSYS_USER0_bm (1<<0) /* User channel select bit 0 mask. */ +#define EVSYS_USER0_bp 0 /* User channel select bit 0 position. */ +#define EVSYS_USER1_bm (1<<1) /* User channel select bit 1 mask. */ +#define EVSYS_USER1_bp 1 /* User channel select bit 1 position. */ +#define EVSYS_USER2_bm (1<<2) /* User channel select bit 2 mask. */ +#define EVSYS_USER2_bp 2 /* User channel select bit 2 position. */ +#define EVSYS_USER3_bm (1<<3) /* User channel select bit 3 mask. */ +#define EVSYS_USER3_bp 3 /* User channel select bit 3 position. */ +#define EVSYS_USER4_bm (1<<4) /* User channel select bit 4 mask. */ +#define EVSYS_USER4_bp 4 /* User channel select bit 4 position. */ +#define EVSYS_USER5_bm (1<<5) /* User channel select bit 5 mask. */ +#define EVSYS_USER5_bp 5 /* User channel select bit 5 position. */ +#define EVSYS_USER6_bm (1<<6) /* User channel select bit 6 mask. */ +#define EVSYS_USER6_bp 6 /* User channel select bit 6 position. */ +#define EVSYS_USER7_bm (1<<7) /* User channel select bit 7 mask. */ +#define EVSYS_USER7_bp 7 /* User channel select bit 7 position. */ + +/* EVSYS.USERCCLLUT0B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT1A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT1B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT2A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT2B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT3A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT3B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT4A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT4B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT5A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT5B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERADC0START bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERPTCSTART bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTC bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTD bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTE bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTF bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTG bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART0IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART1IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART2IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART3IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART4IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART5IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA0CNTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA0CNTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA1CNTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA1CNTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB0CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB0COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB1CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB1COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB2CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB2COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB3CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB3COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB4CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB4COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCD0INPUTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCD0INPUTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEROSCTEST bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_CLKSEL_gm 0x07 /* Frequency Select group mask. */ +#define FUSE_CLKSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_CLKSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_CLKSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_CLKSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_CLKSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_CLKSEL2_bm (1<<2) /* Frequency Select bit 2 mask. */ +#define FUSE_CLKSEL2_bp 2 /* Frequency Select bit 2 position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSEL_bm 0x20 /* CRC Select bit mask. */ +#define FUSE_CRCSEL_bp 5 /* CRC Select bit position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCK - Lockbits */ +/* LOCK.KEY bit masks and bit positions */ +#define LOCK_KEY_gm 0xFFFFFFFF /* Lock Key group mask. */ +#define LOCK_KEY_gp 0 /* Lock Key group position. */ +#define LOCK_KEY0_bm (1<<0) /* Lock Key bit 0 mask. */ +#define LOCK_KEY0_bp 0 /* Lock Key bit 0 position. */ +#define LOCK_KEY1_bm (1<<1) /* Lock Key bit 1 mask. */ +#define LOCK_KEY1_bp 1 /* Lock Key bit 1 position. */ +#define LOCK_KEY2_bm (1<<2) /* Lock Key bit 2 mask. */ +#define LOCK_KEY2_bp 2 /* Lock Key bit 2 position. */ +#define LOCK_KEY3_bm (1<<3) /* Lock Key bit 3 mask. */ +#define LOCK_KEY3_bp 3 /* Lock Key bit 3 position. */ +#define LOCK_KEY4_bm (1<<4) /* Lock Key bit 4 mask. */ +#define LOCK_KEY4_bp 4 /* Lock Key bit 4 position. */ +#define LOCK_KEY5_bm (1<<5) /* Lock Key bit 5 mask. */ +#define LOCK_KEY5_bp 5 /* Lock Key bit 5 position. */ +#define LOCK_KEY6_bm (1<<6) /* Lock Key bit 6 mask. */ +#define LOCK_KEY6_bp 6 /* Lock Key bit 6 position. */ +#define LOCK_KEY7_bm (1<<7) /* Lock Key bit 7 mask. */ +#define LOCK_KEY7_bp 7 /* Lock Key bit 7 position. */ +#define LOCK_KEY8_bm (1<<8) /* Lock Key bit 8 mask. */ +#define LOCK_KEY8_bp 8 /* Lock Key bit 8 position. */ +#define LOCK_KEY9_bm (1<<9) /* Lock Key bit 9 mask. */ +#define LOCK_KEY9_bp 9 /* Lock Key bit 9 position. */ +#define LOCK_KEY10_bm (1<<10) /* Lock Key bit 10 mask. */ +#define LOCK_KEY10_bp 10 /* Lock Key bit 10 position. */ +#define LOCK_KEY11_bm (1<<11) /* Lock Key bit 11 mask. */ +#define LOCK_KEY11_bp 11 /* Lock Key bit 11 position. */ +#define LOCK_KEY12_bm (1<<12) /* Lock Key bit 12 mask. */ +#define LOCK_KEY12_bp 12 /* Lock Key bit 12 position. */ +#define LOCK_KEY13_bm (1<<13) /* Lock Key bit 13 mask. */ +#define LOCK_KEY13_bp 13 /* Lock Key bit 13 position. */ +#define LOCK_KEY14_bm (1<<14) /* Lock Key bit 14 mask. */ +#define LOCK_KEY14_bp 14 /* Lock Key bit 14 position. */ +#define LOCK_KEY15_bm (1<<15) /* Lock Key bit 15 mask. */ +#define LOCK_KEY15_bp 15 /* Lock Key bit 15 position. */ +#define LOCK_KEY16_bm (1<<16) /* Lock Key bit 16 mask. */ +#define LOCK_KEY16_bp 16 /* Lock Key bit 16 position. */ +#define LOCK_KEY17_bm (1<<17) /* Lock Key bit 17 mask. */ +#define LOCK_KEY17_bp 17 /* Lock Key bit 17 position. */ +#define LOCK_KEY18_bm (1<<18) /* Lock Key bit 18 mask. */ +#define LOCK_KEY18_bp 18 /* Lock Key bit 18 position. */ +#define LOCK_KEY19_bm (1<<19) /* Lock Key bit 19 mask. */ +#define LOCK_KEY19_bp 19 /* Lock Key bit 19 position. */ +#define LOCK_KEY20_bm (1<<20) /* Lock Key bit 20 mask. */ +#define LOCK_KEY20_bp 20 /* Lock Key bit 20 position. */ +#define LOCK_KEY21_bm (1<<21) /* Lock Key bit 21 mask. */ +#define LOCK_KEY21_bp 21 /* Lock Key bit 21 position. */ +#define LOCK_KEY22_bm (1<<22) /* Lock Key bit 22 mask. */ +#define LOCK_KEY22_bp 22 /* Lock Key bit 22 position. */ +#define LOCK_KEY23_bm (1<<23) /* Lock Key bit 23 mask. */ +#define LOCK_KEY23_bp 23 /* Lock Key bit 23 position. */ +#define LOCK_KEY24_bm (1<<24) /* Lock Key bit 24 mask. */ +#define LOCK_KEY24_bp 24 /* Lock Key bit 24 position. */ +#define LOCK_KEY25_bm (1<<25) /* Lock Key bit 25 mask. */ +#define LOCK_KEY25_bp 25 /* Lock Key bit 25 position. */ +#define LOCK_KEY26_bm (1<<26) /* Lock Key bit 26 mask. */ +#define LOCK_KEY26_bp 26 /* Lock Key bit 26 position. */ +#define LOCK_KEY27_bm (1<<27) /* Lock Key bit 27 mask. */ +#define LOCK_KEY27_bp 27 /* Lock Key bit 27 position. */ +#define LOCK_KEY28_bm (1<<28) /* Lock Key bit 28 mask. */ +#define LOCK_KEY28_bp 28 /* Lock Key bit 28 position. */ +#define LOCK_KEY29_bm (1<<29) /* Lock Key bit 29 mask. */ +#define LOCK_KEY29_bp 29 /* Lock Key bit 29 position. */ +#define LOCK_KEY30_bm (1<<30) /* Lock Key bit 30 mask. */ +#define LOCK_KEY30_bp 30 /* Lock Key bit 30 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x7F /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ +#define NVMCTRL_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVMCTRL_CMD3_bp 3 /* Command bit 3 position. */ +#define NVMCTRL_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVMCTRL_CMD4_bp 4 /* Command bit 4 position. */ +#define NVMCTRL_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVMCTRL_CMD5_bp 5 /* Command bit 5 position. */ +#define NVMCTRL_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVMCTRL_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APPCODEWP_bm 0x01 /* Application Code Write Protect bit mask. */ +#define NVMCTRL_APPCODEWP_bp 0 /* Application Code Write Protect bit position. */ +#define NVMCTRL_BOOTRP_bm 0x02 /* Boot Read Protect bit mask. */ +#define NVMCTRL_BOOTRP_bp 1 /* Boot Read Protect bit position. */ +#define NVMCTRL_APPDATAWP_bm 0x04 /* Application Data Write Protect bit mask. */ +#define NVMCTRL_APPDATAWP_bp 2 /* Application Data Write Protect bit position. */ +#define NVMCTRL_FLMAP_gm 0x30 /* Flash Mapping in Data space group mask. */ +#define NVMCTRL_FLMAP_gp 4 /* Flash Mapping in Data space group position. */ +#define NVMCTRL_FLMAP0_bm (1<<4) /* Flash Mapping in Data space bit 0 mask. */ +#define NVMCTRL_FLMAP0_bp 4 /* Flash Mapping in Data space bit 0 position. */ +#define NVMCTRL_FLMAP1_bm (1<<5) /* Flash Mapping in Data space bit 1 mask. */ +#define NVMCTRL_FLMAP1_bp 5 /* Flash Mapping in Data space bit 1 position. */ +#define NVMCTRL_FLMAPLOCK_bm 0x80 /* Flash Mapping Lock bit mask. */ +#define NVMCTRL_FLMAPLOCK_bp 7 /* Flash Mapping Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_ERROR_gm 0x70 /* Write error group mask. */ +#define NVMCTRL_ERROR_gp 4 /* Write error group position. */ +#define NVMCTRL_ERROR0_bm (1<<4) /* Write error bit 0 mask. */ +#define NVMCTRL_ERROR0_bp 4 /* Write error bit 0 position. */ +#define NVMCTRL_ERROR1_bm (1<<5) /* Write error bit 1 mask. */ +#define NVMCTRL_ERROR1_bp 5 /* Write error bit 1 position. */ +#define NVMCTRL_ERROR2_bm (1<<6) /* Write error bit 2 mask. */ +#define NVMCTRL_ERROR2_bp 6 /* Write error bit 2 position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PORTCTRL bit masks and bit positions */ +#define PORT_SRL_bm 0x01 /* Slew Rate Limit Enable bit mask. */ +#define PORT_SRL_bp 0 /* Slew Rate Limit Enable bit position. */ + +/* PORT.PINCONFIG bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PINCTRLUPD bit masks and bit positions */ +#define PORT_PINCTRLUPD_gm 0xFF /* Pin control update mask group mask. */ +#define PORT_PINCTRLUPD_gp 0 /* Pin control update mask group position. */ +#define PORT_PINCTRLUPD0_bm (1<<0) /* Pin control update mask bit 0 mask. */ +#define PORT_PINCTRLUPD0_bp 0 /* Pin control update mask bit 0 position. */ +#define PORT_PINCTRLUPD1_bm (1<<1) /* Pin control update mask bit 1 mask. */ +#define PORT_PINCTRLUPD1_bp 1 /* Pin control update mask bit 1 position. */ +#define PORT_PINCTRLUPD2_bm (1<<2) /* Pin control update mask bit 2 mask. */ +#define PORT_PINCTRLUPD2_bp 2 /* Pin control update mask bit 2 position. */ +#define PORT_PINCTRLUPD3_bm (1<<3) /* Pin control update mask bit 3 mask. */ +#define PORT_PINCTRLUPD3_bp 3 /* Pin control update mask bit 3 position. */ +#define PORT_PINCTRLUPD4_bm (1<<4) /* Pin control update mask bit 4 mask. */ +#define PORT_PINCTRLUPD4_bp 4 /* Pin control update mask bit 4 position. */ +#define PORT_PINCTRLUPD5_bm (1<<5) /* Pin control update mask bit 5 mask. */ +#define PORT_PINCTRLUPD5_bp 5 /* Pin control update mask bit 5 position. */ +#define PORT_PINCTRLUPD6_bm (1<<6) /* Pin control update mask bit 6 mask. */ +#define PORT_PINCTRLUPD6_bp 6 /* Pin control update mask bit 6 position. */ +#define PORT_PINCTRLUPD7_bm (1<<7) /* Pin control update mask bit 7 mask. */ +#define PORT_PINCTRLUPD7_bp 7 /* Pin control update mask bit 7 position. */ + +/* PORT.PINCTRLSET bit masks and bit positions */ +#define PORT_PINCTRLSET_gm 0xFF /* Pin control set mask group mask. */ +#define PORT_PINCTRLSET_gp 0 /* Pin control set mask group position. */ +#define PORT_PINCTRLSET0_bm (1<<0) /* Pin control set mask bit 0 mask. */ +#define PORT_PINCTRLSET0_bp 0 /* Pin control set mask bit 0 position. */ +#define PORT_PINCTRLSET1_bm (1<<1) /* Pin control set mask bit 1 mask. */ +#define PORT_PINCTRLSET1_bp 1 /* Pin control set mask bit 1 position. */ +#define PORT_PINCTRLSET2_bm (1<<2) /* Pin control set mask bit 2 mask. */ +#define PORT_PINCTRLSET2_bp 2 /* Pin control set mask bit 2 position. */ +#define PORT_PINCTRLSET3_bm (1<<3) /* Pin control set mask bit 3 mask. */ +#define PORT_PINCTRLSET3_bp 3 /* Pin control set mask bit 3 position. */ +#define PORT_PINCTRLSET4_bm (1<<4) /* Pin control set mask bit 4 mask. */ +#define PORT_PINCTRLSET4_bp 4 /* Pin control set mask bit 4 position. */ +#define PORT_PINCTRLSET5_bm (1<<5) /* Pin control set mask bit 5 mask. */ +#define PORT_PINCTRLSET5_bp 5 /* Pin control set mask bit 5 position. */ +#define PORT_PINCTRLSET6_bm (1<<6) /* Pin control set mask bit 6 mask. */ +#define PORT_PINCTRLSET6_bp 6 /* Pin control set mask bit 6 position. */ +#define PORT_PINCTRLSET7_bm (1<<7) /* Pin control set mask bit 7 mask. */ +#define PORT_PINCTRLSET7_bp 7 /* Pin control set mask bit 7 position. */ + +/* PORT.PINCTRLCLR bit masks and bit positions */ +#define PORT_PINCTRLCLR_gm 0xFF /* Pin control clear mask group mask. */ +#define PORT_PINCTRLCLR_gp 0 /* Pin control clear mask group position. */ +#define PORT_PINCTRLCLR0_bm (1<<0) /* Pin control clear mask bit 0 mask. */ +#define PORT_PINCTRLCLR0_bp 0 /* Pin control clear mask bit 0 position. */ +#define PORT_PINCTRLCLR1_bm (1<<1) /* Pin control clear mask bit 1 mask. */ +#define PORT_PINCTRLCLR1_bp 1 /* Pin control clear mask bit 1 position. */ +#define PORT_PINCTRLCLR2_bm (1<<2) /* Pin control clear mask bit 2 mask. */ +#define PORT_PINCTRLCLR2_bp 2 /* Pin control clear mask bit 2 position. */ +#define PORT_PINCTRLCLR3_bm (1<<3) /* Pin control clear mask bit 3 mask. */ +#define PORT_PINCTRLCLR3_bp 3 /* Pin control clear mask bit 3 position. */ +#define PORT_PINCTRLCLR4_bm (1<<4) /* Pin control clear mask bit 4 mask. */ +#define PORT_PINCTRLCLR4_bp 4 /* Pin control clear mask bit 4 position. */ +#define PORT_PINCTRLCLR5_bm (1<<5) /* Pin control clear mask bit 5 mask. */ +#define PORT_PINCTRLCLR5_bp 5 /* Pin control clear mask bit 5 position. */ +#define PORT_PINCTRLCLR6_bm (1<<6) /* Pin control clear mask bit 6 mask. */ +#define PORT_PINCTRLCLR6_bp 6 /* Pin control clear mask bit 6 position. */ +#define PORT_PINCTRLCLR7_bm (1<<7) /* Pin control clear mask bit 7 mask. */ +#define PORT_PINCTRLCLR7_bp 7 /* Pin control clear mask bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.EVSYSROUTEA bit masks and bit positions */ +#define PORTMUX_EVOUTA_bm 0x01 /* Event Output A bit mask. */ +#define PORTMUX_EVOUTA_bp 0 /* Event Output A bit position. */ +#define PORTMUX_EVOUTB_bm 0x02 /* Event Output B bit mask. */ +#define PORTMUX_EVOUTB_bp 1 /* Event Output B bit position. */ +#define PORTMUX_EVOUTC_bm 0x04 /* Event Output C bit mask. */ +#define PORTMUX_EVOUTC_bp 2 /* Event Output C bit position. */ +#define PORTMUX_EVOUTD_bm 0x08 /* Event Output D bit mask. */ +#define PORTMUX_EVOUTD_bp 3 /* Event Output D bit position. */ +#define PORTMUX_EVOUTE_bm 0x10 /* Event Output E bit mask. */ +#define PORTMUX_EVOUTE_bp 4 /* Event Output E bit position. */ +#define PORTMUX_EVOUTF_bm 0x20 /* Event Output F bit mask. */ +#define PORTMUX_EVOUTF_bp 5 /* Event Output F bit position. */ +#define PORTMUX_EVOUTG_bm 0x40 /* Event Output G bit mask. */ +#define PORTMUX_EVOUTG_bp 6 /* Event Output G bit position. */ + +/* PORTMUX.CCLROUTEA bit masks and bit positions */ +#define PORTMUX_LUT0_bm 0x01 /* CCL Look-Up Table 0 Signals bit mask. */ +#define PORTMUX_LUT0_bp 0 /* CCL Look-Up Table 0 Signals bit position. */ +#define PORTMUX_LUT1_bm 0x02 /* CCL Look-Up Table 1 Signals bit mask. */ +#define PORTMUX_LUT1_bp 1 /* CCL Look-Up Table 1 Signals bit position. */ +#define PORTMUX_LUT2_bm 0x04 /* CCL Look-Up Table 2 Signals bit mask. */ +#define PORTMUX_LUT2_bp 2 /* CCL Look-Up Table 2 Signals bit position. */ +#define PORTMUX_LUT3_bm 0x08 /* CCL Look-Up Table 3 Signals bit mask. */ +#define PORTMUX_LUT3_bp 3 /* CCL Look-Up Table 3 Signals bit position. */ +#define PORTMUX_LUT4_bm 0x10 /* CCL Look-Up Table 4 Signals bit mask. */ +#define PORTMUX_LUT4_bp 4 /* CCL Look-Up Table 4 Signals bit position. */ +#define PORTMUX_LUT5_bm 0x20 /* CCL Look-Up Table 5 Signals bit mask. */ +#define PORTMUX_LUT5_bp 5 /* CCL Look-Up Table 5 Signals bit position. */ + +/* PORTMUX.USARTROUTEA bit masks and bit positions */ +#define PORTMUX_USART0_gm 0x03 /* USART0 Signals group mask. */ +#define PORTMUX_USART0_gp 0 /* USART0 Signals group position. */ +#define PORTMUX_USART00_bm (1<<0) /* USART0 Signals bit 0 mask. */ +#define PORTMUX_USART00_bp 0 /* USART0 Signals bit 0 position. */ +#define PORTMUX_USART01_bm (1<<1) /* USART0 Signals bit 1 mask. */ +#define PORTMUX_USART01_bp 1 /* USART0 Signals bit 1 position. */ +#define PORTMUX_USART1_gm 0x0C /* USART1 Signals group mask. */ +#define PORTMUX_USART1_gp 2 /* USART1 Signals group position. */ +#define PORTMUX_USART10_bm (1<<2) /* USART1 Signals bit 0 mask. */ +#define PORTMUX_USART10_bp 2 /* USART1 Signals bit 0 position. */ +#define PORTMUX_USART11_bm (1<<3) /* USART1 Signals bit 1 mask. */ +#define PORTMUX_USART11_bp 3 /* USART1 Signals bit 1 position. */ +#define PORTMUX_USART2_gm 0x30 /* USART2 Signals group mask. */ +#define PORTMUX_USART2_gp 4 /* USART2 Signals group position. */ +#define PORTMUX_USART20_bm (1<<4) /* USART2 Signals bit 0 mask. */ +#define PORTMUX_USART20_bp 4 /* USART2 Signals bit 0 position. */ +#define PORTMUX_USART21_bm (1<<5) /* USART2 Signals bit 1 mask. */ +#define PORTMUX_USART21_bp 5 /* USART2 Signals bit 1 position. */ + + +/* PORTMUX.SPIROUTEA bit masks and bit positions */ +#define PORTMUX_SPI0_gm 0x03 /* SPI0 Signals group mask. */ +#define PORTMUX_SPI0_gp 0 /* SPI0 Signals group position. */ +#define PORTMUX_SPI00_bm (1<<0) /* SPI0 Signals bit 0 mask. */ +#define PORTMUX_SPI00_bp 0 /* SPI0 Signals bit 0 position. */ +#define PORTMUX_SPI01_bm (1<<1) /* SPI0 Signals bit 1 mask. */ +#define PORTMUX_SPI01_bp 1 /* SPI0 Signals bit 1 position. */ +#define PORTMUX_SPI1_gm 0x0C /* SPI1 Signals group mask. */ +#define PORTMUX_SPI1_gp 2 /* SPI1 Signals group position. */ +#define PORTMUX_SPI10_bm (1<<2) /* SPI1 Signals bit 0 mask. */ +#define PORTMUX_SPI10_bp 2 /* SPI1 Signals bit 0 position. */ +#define PORTMUX_SPI11_bm (1<<3) /* SPI1 Signals bit 1 mask. */ +#define PORTMUX_SPI11_bp 3 /* SPI1 Signals bit 1 position. */ + +/* PORTMUX.TWIROUTEA bit masks and bit positions */ +#define PORTMUX_TWI0_gm 0x03 /* TWI0 Signals group mask. */ +#define PORTMUX_TWI0_gp 0 /* TWI0 Signals group position. */ +#define PORTMUX_TWI00_bm (1<<0) /* TWI0 Signals bit 0 mask. */ +#define PORTMUX_TWI00_bp 0 /* TWI0 Signals bit 0 position. */ +#define PORTMUX_TWI01_bm (1<<1) /* TWI0 Signals bit 1 mask. */ +#define PORTMUX_TWI01_bp 1 /* TWI0 Signals bit 1 position. */ +#define PORTMUX_TWI1_gm 0x0C /* TWI1 Signals group mask. */ +#define PORTMUX_TWI1_gp 2 /* TWI1 Signals group position. */ +#define PORTMUX_TWI10_bm (1<<2) /* TWI1 Signals bit 0 mask. */ +#define PORTMUX_TWI10_bp 2 /* TWI1 Signals bit 0 position. */ +#define PORTMUX_TWI11_bm (1<<3) /* TWI1 Signals bit 1 mask. */ +#define PORTMUX_TWI11_bp 3 /* TWI1 Signals bit 1 position. */ + +/* PORTMUX.TCAROUTEA bit masks and bit positions */ +#define PORTMUX_TCA0_gm 0x07 /* TCA0 Signals group mask. */ +#define PORTMUX_TCA0_gp 0 /* TCA0 Signals group position. */ +#define PORTMUX_TCA00_bm (1<<0) /* TCA0 Signals bit 0 mask. */ +#define PORTMUX_TCA00_bp 0 /* TCA0 Signals bit 0 position. */ +#define PORTMUX_TCA01_bm (1<<1) /* TCA0 Signals bit 1 mask. */ +#define PORTMUX_TCA01_bp 1 /* TCA0 Signals bit 1 position. */ +#define PORTMUX_TCA02_bm (1<<2) /* TCA0 Signals bit 2 mask. */ +#define PORTMUX_TCA02_bp 2 /* TCA0 Signals bit 2 position. */ + +/* PORTMUX.TCBROUTEA bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* TCB0 Output bit mask. */ +#define PORTMUX_TCB0_bp 0 /* TCB0 Output bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* TCB1 Output bit mask. */ +#define PORTMUX_TCB1_bp 1 /* TCB1 Output bit position. */ +#define PORTMUX_TCB2_bm 0x04 /* TCB2 Output bit mask. */ +#define PORTMUX_TCB2_bp 2 /* TCB2 Output bit position. */ + +/* PORTMUX.TCDROUTEA bit masks and bit positions */ +#define PORTMUX_TCD0_gm 0x07 /* TCD0 Signals group mask. */ +#define PORTMUX_TCD0_gp 0 /* TCD0 Signals group position. */ +#define PORTMUX_TCD00_bm (1<<0) /* TCD0 Signals bit 0 mask. */ +#define PORTMUX_TCD00_bp 0 /* TCD0 Signals bit 0 position. */ +#define PORTMUX_TCD01_bm (1<<1) /* TCD0 Signals bit 1 mask. */ +#define PORTMUX_TCD01_bp 1 /* TCD0 Signals bit 1 position. */ +#define PORTMUX_TCD02_bm (1<<2) /* TCD0 Signals bit 2 mask. */ +#define PORTMUX_TCD02_bp 2 /* TCD0 Signals bit 2 position. */ + +/* PORTMUX.ACROUTEA bit masks and bit positions */ +#define PORTMUX_AC0_bm 0x01 /* Analog Comparator 0 Output bit mask. */ +#define PORTMUX_AC0_bp 0 /* Analog Comparator 0 Output bit position. */ +#define PORTMUX_AC1_bm 0x02 /* Analog Comparator 1 Output bit mask. */ +#define PORTMUX_AC1_bp 1 /* Analog Comparator 1 Output bit position. */ +#define PORTMUX_AC2_bm 0x04 /* Analog Comparator 2 Output bit mask. */ +#define PORTMUX_AC2_bp 2 /* Analog Comparator 2 Output bit position. */ + +/* PORTMUX.ZCDROUTEA bit masks and bit positions */ +#define PORTMUX_ZCD0_bm 0x01 /* Zero Cross Detector 0 Output bit mask. */ +#define PORTMUX_ZCD0_bp 0 /* Zero Cross Detector 0 Output bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRST_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRST_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_CORREN_bm 0x04 /* Correction enable bit mask. */ +#define RTC_CORREN_bp 2 /* Correction enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_ERROR_gm 0x7F /* Error Correction Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Correction Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Correction Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Correction Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Correction Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Correction Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Correction Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Correction Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Correction Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Correction Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Correction Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Correction Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Correction Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Correction Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Correction Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Correction Value bit 6 position. */ +#define RTC_SIGN_bm 0x80 /* Error Correction Sign Bit bit mask. */ +#define RTC_SIGN_bp 7 /* Error Correction Sign Bit bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + +/* SIGROW - Signature row */ +/* SIGROW.TEMPSENSE0 bit masks and bit positions */ +#define SIGROW_TEMPSENSE0_gm 0xFFFF /* Temperature Calibration 0 group mask. */ +#define SIGROW_TEMPSENSE0_gp 0 /* Temperature Calibration 0 group position. */ +#define SIGROW_TEMPSENSE00_bm (1<<0) /* Temperature Calibration 0 bit 0 mask. */ +#define SIGROW_TEMPSENSE00_bp 0 /* Temperature Calibration 0 bit 0 position. */ +#define SIGROW_TEMPSENSE01_bm (1<<1) /* Temperature Calibration 0 bit 1 mask. */ +#define SIGROW_TEMPSENSE01_bp 1 /* Temperature Calibration 0 bit 1 position. */ +#define SIGROW_TEMPSENSE02_bm (1<<2) /* Temperature Calibration 0 bit 2 mask. */ +#define SIGROW_TEMPSENSE02_bp 2 /* Temperature Calibration 0 bit 2 position. */ +#define SIGROW_TEMPSENSE03_bm (1<<3) /* Temperature Calibration 0 bit 3 mask. */ +#define SIGROW_TEMPSENSE03_bp 3 /* Temperature Calibration 0 bit 3 position. */ +#define SIGROW_TEMPSENSE04_bm (1<<4) /* Temperature Calibration 0 bit 4 mask. */ +#define SIGROW_TEMPSENSE04_bp 4 /* Temperature Calibration 0 bit 4 position. */ +#define SIGROW_TEMPSENSE05_bm (1<<5) /* Temperature Calibration 0 bit 5 mask. */ +#define SIGROW_TEMPSENSE05_bp 5 /* Temperature Calibration 0 bit 5 position. */ +#define SIGROW_TEMPSENSE06_bm (1<<6) /* Temperature Calibration 0 bit 6 mask. */ +#define SIGROW_TEMPSENSE06_bp 6 /* Temperature Calibration 0 bit 6 position. */ +#define SIGROW_TEMPSENSE07_bm (1<<7) /* Temperature Calibration 0 bit 7 mask. */ +#define SIGROW_TEMPSENSE07_bp 7 /* Temperature Calibration 0 bit 7 position. */ +#define SIGROW_TEMPSENSE08_bm (1<<8) /* Temperature Calibration 0 bit 8 mask. */ +#define SIGROW_TEMPSENSE08_bp 8 /* Temperature Calibration 0 bit 8 position. */ +#define SIGROW_TEMPSENSE09_bm (1<<9) /* Temperature Calibration 0 bit 9 mask. */ +#define SIGROW_TEMPSENSE09_bp 9 /* Temperature Calibration 0 bit 9 position. */ +#define SIGROW_TEMPSENSE010_bm (1<<10) /* Temperature Calibration 0 bit 10 mask. */ +#define SIGROW_TEMPSENSE010_bp 10 /* Temperature Calibration 0 bit 10 position. */ +#define SIGROW_TEMPSENSE011_bm (1<<11) /* Temperature Calibration 0 bit 11 mask. */ +#define SIGROW_TEMPSENSE011_bp 11 /* Temperature Calibration 0 bit 11 position. */ +#define SIGROW_TEMPSENSE012_bm (1<<12) /* Temperature Calibration 0 bit 12 mask. */ +#define SIGROW_TEMPSENSE012_bp 12 /* Temperature Calibration 0 bit 12 position. */ +#define SIGROW_TEMPSENSE013_bm (1<<13) /* Temperature Calibration 0 bit 13 mask. */ +#define SIGROW_TEMPSENSE013_bp 13 /* Temperature Calibration 0 bit 13 position. */ +#define SIGROW_TEMPSENSE014_bm (1<<14) /* Temperature Calibration 0 bit 14 mask. */ +#define SIGROW_TEMPSENSE014_bp 14 /* Temperature Calibration 0 bit 14 position. */ +#define SIGROW_TEMPSENSE015_bm (1<<15) /* Temperature Calibration 0 bit 15 mask. */ +#define SIGROW_TEMPSENSE015_bp 15 /* Temperature Calibration 0 bit 15 position. */ + +/* SIGROW.TEMPSENSE1 bit masks and bit positions */ +#define SIGROW_TEMPSENSE1_gm 0xFFFF /* Temperature Calibration 1 group mask. */ +#define SIGROW_TEMPSENSE1_gp 0 /* Temperature Calibration 1 group position. */ +#define SIGROW_TEMPSENSE10_bm (1<<0) /* Temperature Calibration 1 bit 0 mask. */ +#define SIGROW_TEMPSENSE10_bp 0 /* Temperature Calibration 1 bit 0 position. */ +#define SIGROW_TEMPSENSE11_bm (1<<1) /* Temperature Calibration 1 bit 1 mask. */ +#define SIGROW_TEMPSENSE11_bp 1 /* Temperature Calibration 1 bit 1 position. */ +#define SIGROW_TEMPSENSE12_bm (1<<2) /* Temperature Calibration 1 bit 2 mask. */ +#define SIGROW_TEMPSENSE12_bp 2 /* Temperature Calibration 1 bit 2 position. */ +#define SIGROW_TEMPSENSE13_bm (1<<3) /* Temperature Calibration 1 bit 3 mask. */ +#define SIGROW_TEMPSENSE13_bp 3 /* Temperature Calibration 1 bit 3 position. */ +#define SIGROW_TEMPSENSE14_bm (1<<4) /* Temperature Calibration 1 bit 4 mask. */ +#define SIGROW_TEMPSENSE14_bp 4 /* Temperature Calibration 1 bit 4 position. */ +#define SIGROW_TEMPSENSE15_bm (1<<5) /* Temperature Calibration 1 bit 5 mask. */ +#define SIGROW_TEMPSENSE15_bp 5 /* Temperature Calibration 1 bit 5 position. */ +#define SIGROW_TEMPSENSE16_bm (1<<6) /* Temperature Calibration 1 bit 6 mask. */ +#define SIGROW_TEMPSENSE16_bp 6 /* Temperature Calibration 1 bit 6 position. */ +#define SIGROW_TEMPSENSE17_bm (1<<7) /* Temperature Calibration 1 bit 7 mask. */ +#define SIGROW_TEMPSENSE17_bp 7 /* Temperature Calibration 1 bit 7 position. */ +#define SIGROW_TEMPSENSE18_bm (1<<8) /* Temperature Calibration 1 bit 8 mask. */ +#define SIGROW_TEMPSENSE18_bp 8 /* Temperature Calibration 1 bit 8 position. */ +#define SIGROW_TEMPSENSE19_bm (1<<9) /* Temperature Calibration 1 bit 9 mask. */ +#define SIGROW_TEMPSENSE19_bp 9 /* Temperature Calibration 1 bit 9 position. */ +#define SIGROW_TEMPSENSE110_bm (1<<10) /* Temperature Calibration 1 bit 10 mask. */ +#define SIGROW_TEMPSENSE110_bp 10 /* Temperature Calibration 1 bit 10 position. */ +#define SIGROW_TEMPSENSE111_bm (1<<11) /* Temperature Calibration 1 bit 11 mask. */ +#define SIGROW_TEMPSENSE111_bp 11 /* Temperature Calibration 1 bit 11 position. */ +#define SIGROW_TEMPSENSE112_bm (1<<12) /* Temperature Calibration 1 bit 12 mask. */ +#define SIGROW_TEMPSENSE112_bp 12 /* Temperature Calibration 1 bit 12 position. */ +#define SIGROW_TEMPSENSE113_bm (1<<13) /* Temperature Calibration 1 bit 13 mask. */ +#define SIGROW_TEMPSENSE113_bp 13 /* Temperature Calibration 1 bit 13 position. */ +#define SIGROW_TEMPSENSE114_bm (1<<14) /* Temperature Calibration 1 bit 14 mask. */ +#define SIGROW_TEMPSENSE114_bp 14 /* Temperature Calibration 1 bit 14 position. */ +#define SIGROW_TEMPSENSE115_bm (1<<15) /* Temperature Calibration 1 bit 15 mask. */ +#define SIGROW_TEMPSENSE115_bp 15 /* Temperature Calibration 1 bit 15 position. */ + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SLPCTRL.VREGCTRL bit masks and bit positions */ +#define SLPCTRL_PMODE_gm 0x07 /* Performance Mode group mask. */ +#define SLPCTRL_PMODE_gp 0 /* Performance Mode group position. */ +#define SLPCTRL_PMODE0_bm (1<<0) /* Performance Mode bit 0 mask. */ +#define SLPCTRL_PMODE0_bp 0 /* Performance Mode bit 0 position. */ +#define SLPCTRL_PMODE1_bm (1<<1) /* Performance Mode bit 1 mask. */ +#define SLPCTRL_PMODE1_bp 1 /* Performance Mode bit 1 position. */ +#define SLPCTRL_PMODE2_bm (1<<2) /* Performance Mode bit 2 mask. */ +#define SLPCTRL_PMODE2_bp 2 /* Performance Mode bit 2 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Mode Wait for Receive bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Mode Wait for Receive bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.OCDMSTATUS bit masks and bit positions */ +#define SYSCFG_OCDMR_bm 0x01 /* OCD Message Read bit mask. */ +#define SYSCFG_OCDMR_bp 0 /* OCD Message Read bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ +#define TCA_SINGLE_RUNSTDBY_bm 0x80 /* Run in Standby bit mask. */ +#define TCA_SINGLE_RUNSTDBY_bp 7 /* Run in Standby bit position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTAEI_bm 0x01 /* Count on Event Input A bit mask. */ +#define TCA_SINGLE_CNTAEI_bp 0 /* Count on Event Input A bit position. */ +#define TCA_SINGLE_EVACTA_gm 0x0E /* Event Action A group mask. */ +#define TCA_SINGLE_EVACTA_gp 1 /* Event Action A group position. */ +#define TCA_SINGLE_EVACTA0_bm (1<<1) /* Event Action A bit 0 mask. */ +#define TCA_SINGLE_EVACTA0_bp 1 /* Event Action A bit 0 position. */ +#define TCA_SINGLE_EVACTA1_bm (1<<2) /* Event Action A bit 1 mask. */ +#define TCA_SINGLE_EVACTA1_bp 2 /* Event Action A bit 1 position. */ +#define TCA_SINGLE_EVACTA2_bm (1<<3) /* Event Action A bit 2 mask. */ +#define TCA_SINGLE_EVACTA2_bp 3 /* Event Action A bit 2 position. */ +#define TCA_SINGLE_CNTBEI_bm 0x10 /* Count on Event Input B bit mask. */ +#define TCA_SINGLE_CNTBEI_bp 4 /* Count on Event Input B bit position. */ +#define TCA_SINGLE_EVACTB_gm 0xE0 /* Event Action B group mask. */ +#define TCA_SINGLE_EVACTB_gp 5 /* Event Action B group position. */ +#define TCA_SINGLE_EVACTB0_bm (1<<5) /* Event Action B bit 0 mask. */ +#define TCA_SINGLE_EVACTB0_bp 5 /* Event Action B bit 0 position. */ +#define TCA_SINGLE_EVACTB1_bm (1<<6) /* Event Action B bit 1 mask. */ +#define TCA_SINGLE_EVACTB1_bp 6 /* Event Action B bit 1 position. */ +#define TCA_SINGLE_EVACTB2_bm (1<<7) /* Event Action B bit 2 mask. */ +#define TCA_SINGLE_EVACTB2_bp 7 /* Event Action B bit 2 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ +#define TCA_SPLIT_RUNSTDBY_bm 0x80 /* Run in Standby bit mask. */ +#define TCA_SPLIT_RUNSTDBY_bp 7 /* Run in Standby bit position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TCA_SPLIT_CMDEN_gp 0 /* Command Enable group position. */ +#define TCA_SPLIT_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TCA_SPLIT_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TCA_SPLIT_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TCA_SPLIT_CMDEN1_bp 1 /* Command Enable bit 1 position. */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x0E /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_CLKSEL2_bm (1<<3) /* Clock Select bit 2 mask. */ +#define TCB_CLKSEL2_bp 3 /* Clock Select bit 2 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_CASCADE_bm 0x20 /* Cascade two timers bit mask. */ +#define TCB_CASCADE_bp 5 /* Cascade two timers bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ +#define TCB_OVF_bm 0x02 /* Overflow bit mask. */ +#define TCB_OVF_bp 1 /* Overflow bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ +/* TCB_OVF is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Synchronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Synchronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Synchronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Synchronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Synchronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Synchronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ +#define TWI_INPUTLVL_bm 0x40 /* Input Voltage Transition Level bit mask. */ +#define TWI_INPUTLVL_bp 6 /* Input Voltage Transition Level bit position. */ + +/* TWI.DUALCTRL bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Dual Control Enable bit mask. */ +#define TWI_ENABLE_bp 0 /* Dual Control Enable bit position. */ +/* TWI_FMPEN is already defined. */ +/* TWI_SDAHOLD is already defined. */ +/* TWI_INPUTLVL is already defined. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.CTRLD bit masks and bit positions */ +#define USART_ABW_gm 0xC0 /* Auto Baud Window group mask. */ +#define USART_ABW_gp 6 /* Auto Baud Window group position. */ +#define USART_ABW0_bm (1<<6) /* Auto Baud Window bit 0 mask. */ +#define USART_ABW0_bp 6 /* Auto Baud Window bit 0 position. */ +#define USART_ABW1_bm (1<<7) /* Auto Baud Window bit 1 mask. */ +#define USART_ABW1_bp 7 /* Auto Baud Window bit 1 position. */ + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.ADC0REF bit masks and bit positions */ +#define VREF_REFSEL_gm 0x07 /* Reference select group mask. */ +#define VREF_REFSEL_gp 0 /* Reference select group position. */ +#define VREF_REFSEL0_bm (1<<0) /* Reference select bit 0 mask. */ +#define VREF_REFSEL0_bp 0 /* Reference select bit 0 position. */ +#define VREF_REFSEL1_bm (1<<1) /* Reference select bit 1 mask. */ +#define VREF_REFSEL1_bp 1 /* Reference select bit 1 position. */ +#define VREF_REFSEL2_bm (1<<2) /* Reference select bit 2 mask. */ +#define VREF_REFSEL2_bp 2 /* Reference select bit 2 position. */ +#define VREF_ALWAYSON_bm 0x80 /* Always on bit mask. */ +#define VREF_ALWAYSON_bp 7 /* Always on bit position. */ + +/* VREF.DAC0REF bit masks and bit positions */ +/* VREF_REFSEL is already defined. */ +/* VREF_ALWAYSON is already defined. */ + +/* VREF.ACREF bit masks and bit positions */ +/* VREF_REFSEL is already defined. */ +/* VREF_ALWAYSON is already defined. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + +/* ZCD - Zero Cross Detect */ +/* ZCD.CTRLA bit masks and bit positions */ +#define ZCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define ZCD_ENABLE_bp 0 /* Enable bit position. */ +#define ZCD_INVERT_bm 0x08 /* Invert signal from pin bit mask. */ +#define ZCD_INVERT_bp 3 /* Invert signal from pin bit position. */ +#define ZCD_OUTEN_bm 0x40 /* Output Pad Enable bit mask. */ +#define ZCD_OUTEN_bp 6 /* Output Pad Enable bit position. */ +#define ZCD_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define ZCD_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* ZCD.INTCTRL bit masks and bit positions */ +#define ZCD_INTMODE_gm 0x03 /* Interrupt Mode group mask. */ +#define ZCD_INTMODE_gp 0 /* Interrupt Mode group position. */ +#define ZCD_INTMODE0_bm (1<<0) /* Interrupt Mode bit 0 mask. */ +#define ZCD_INTMODE0_bp 0 /* Interrupt Mode bit 0 position. */ +#define ZCD_INTMODE1_bm (1<<1) /* Interrupt Mode bit 1 mask. */ +#define ZCD_INTMODE1_bp 1 /* Interrupt Mode bit 1 position. */ + +/* ZCD.STATUS bit masks and bit positions */ +#define ZCD_CROSSIF_bm 0x01 /* ZCD Interrupt Flag bit mask. */ +#define ZCD_CROSSIF_bp 0 /* ZCD Interrupt Flag bit position. */ +#define ZCD_STATE_bm 0x10 /* ZCD State bit mask. */ +#define ZCD_STATE_bp 4 /* ZCD State bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* NMI interrupt vectors */ +#define NMI_vect_num 1 +#define NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 3 +#define RTC_CNT_vect _VECTOR(3) /* */ +#define RTC_PIT_vect_num 4 +#define RTC_PIT_vect _VECTOR(4) /* */ + +/* CCL interrupt vectors */ +#define CCL_CCL_vect_num 5 +#define CCL_CCL_vect _VECTOR(5) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 6 +#define PORTA_PORT_vect _VECTOR(6) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 7 +#define TCA0_LUNF_vect _VECTOR(7) /* */ +#define TCA0_OVF_vect_num 7 +#define TCA0_OVF_vect _VECTOR(7) /* */ +#define TCA0_HUNF_vect_num 8 +#define TCA0_HUNF_vect _VECTOR(8) /* */ +#define TCA0_CMP0_vect_num 9 +#define TCA0_CMP0_vect _VECTOR(9) /* */ +#define TCA0_LCMP0_vect_num 9 +#define TCA0_LCMP0_vect _VECTOR(9) /* */ +#define TCA0_CMP1_vect_num 10 +#define TCA0_CMP1_vect _VECTOR(10) /* */ +#define TCA0_LCMP1_vect_num 10 +#define TCA0_LCMP1_vect _VECTOR(10) /* */ +#define TCA0_CMP2_vect_num 11 +#define TCA0_CMP2_vect _VECTOR(11) /* */ +#define TCA0_LCMP2_vect_num 11 +#define TCA0_LCMP2_vect _VECTOR(11) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 12 +#define TCB0_INT_vect _VECTOR(12) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 13 +#define TCB1_INT_vect _VECTOR(13) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 14 +#define TCD0_OVF_vect _VECTOR(14) /* */ +#define TCD0_TRIG_vect_num 15 +#define TCD0_TRIG_vect _VECTOR(15) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 16 +#define TWI0_TWIS_vect _VECTOR(16) /* */ +#define TWI0_TWIM_vect_num 17 +#define TWI0_TWIM_vect _VECTOR(17) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 18 +#define SPI0_INT_vect _VECTOR(18) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 19 +#define USART0_RXC_vect _VECTOR(19) /* */ +#define USART0_DRE_vect_num 20 +#define USART0_DRE_vect _VECTOR(20) /* */ +#define USART0_TXC_vect_num 21 +#define USART0_TXC_vect _VECTOR(21) /* */ + +/* PORTD interrupt vectors */ +#define PORTD_PORT_vect_num 22 +#define PORTD_PORT_vect _VECTOR(22) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 23 +#define AC0_AC_vect _VECTOR(23) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 24 +#define ADC0_RESRDY_vect _VECTOR(24) /* */ +#define ADC0_WCMP_vect_num 25 +#define ADC0_WCMP_vect _VECTOR(25) /* */ + +/* ZCD0 interrupt vectors */ +#define ZCD0_ZCD_vect_num 26 +#define ZCD0_ZCD_vect _VECTOR(26) /* */ + +/* PTC interrupt vectors */ +#define PTC_PTC_vect_num 27 +#define PTC_PTC_vect _VECTOR(27) /* */ + +/* AC1 interrupt vectors */ +#define AC1_AC_vect_num 28 +#define AC1_AC_vect _VECTOR(28) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 29 +#define PORTC_PORT_vect _VECTOR(29) /* */ + +/* TCB2 interrupt vectors */ +#define TCB2_INT_vect_num 30 +#define TCB2_INT_vect _VECTOR(30) /* */ + +/* USART1 interrupt vectors */ +#define USART1_RXC_vect_num 31 +#define USART1_RXC_vect _VECTOR(31) /* */ +#define USART1_DRE_vect_num 32 +#define USART1_DRE_vect _VECTOR(32) /* */ +#define USART1_TXC_vect_num 33 +#define USART1_TXC_vect _VECTOR(33) /* */ + +/* PORTF interrupt vectors */ +#define PORTF_PORT_vect_num 34 +#define PORTF_PORT_vect _VECTOR(34) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 35 +#define NVMCTRL_EE_vect _VECTOR(35) /* */ + +/* SPI1 interrupt vectors */ +#define SPI1_INT_vect_num 36 +#define SPI1_INT_vect _VECTOR(36) /* */ + +/* USART2 interrupt vectors */ +#define USART2_RXC_vect_num 37 +#define USART2_RXC_vect _VECTOR(37) /* */ +#define USART2_DRE_vect_num 38 +#define USART2_DRE_vect _VECTOR(38) /* */ +#define USART2_TXC_vect_num 39 +#define USART2_TXC_vect _VECTOR(39) /* */ + +/* AC2 interrupt vectors */ +#define AC2_AC_vect_num 40 +#define AC2_AC_vect _VECTOR(40) /* */ + +/* TWI1 interrupt vectors */ +#define TWI1_TWIS_vect_num 42 +#define TWI1_TWIS_vect _VECTOR(42) /* */ +#define TWI1_TWIM_vect_num 43 +#define TWI1_TWIM_vect _VECTOR(43) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 44 +#define PORTB_PORT_vect _VECTOR(44) /* */ + +/* PORTE interrupt vectors */ +#define PORTE_PORT_vect_num 45 +#define PORTE_PORT_vect _VECTOR(45) /* */ + +/* PORTG interrupt vectors */ +#define PORTG_PORT_vect_num 58 +#define PORTG_PORT_vect _VECTOR(58) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (59 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (65536) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (65536U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (512) +# define EEPROM_PAGE_SIZE (1) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (512U) +# define EEPROM_PAGE_SIZE (1U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1050) +# define FUSES_SIZE (16) +# define FUSES_PAGE_SIZE (1) +#else +# define FUSES_START (0x1050U) +# define FUSES_SIZE (16U) +# define FUSES_PAGE_SIZE (1U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x4000) +# define INTERNAL_SRAM_SIZE (16384) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x4000U) +# define INTERNAL_SRAM_SIZE (16384U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4159) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4159U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x1040) +# define LOCKBITS_SIZE (4) +# define LOCKBITS_PAGE_SIZE (1) +#else +# define LOCKBITS_START (0x1040U) +# define LOCKBITS_SIZE (4U) +# define LOCKBITS_PAGE_SIZE (1U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (32768) +# define MAPPED_PROGMEM_PAGE_SIZE (512) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (32768U) +# define MAPPED_PROGMEM_PAGE_SIZE (512U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (125) +# define PROD_SIGNATURES_PAGE_SIZE (128) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (125U) +# define PROD_SIGNATURES_PAGE_SIZE (128U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (128) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (128U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1080) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1080U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (131072) +# define PROGMEM_PAGE_SIZE (512) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (131072U) +# define PROGMEM_PAGE_SIZE (512U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 16 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_CLKSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_CLKSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_CLKSEL2 (unsigned char)_BV(2) /* Frequency Select Bit 2 */ +#define FUSE2_DEFAULT (0x0) +#define FUSE_OSCCFG_DEFAULT (0x0) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSEL (unsigned char)_BV(5) /* CRC Select */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc0) +#define FUSE_SYSCFG0_DEFAULT (0xc0) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x0) +#define FUSE_SYSCFG1_DEFAULT (0x0) + +/* Fuse Byte 7 (CODESIZE) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_CODESIZE_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTSIZE) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTSIZE_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_KEY_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0x5cc5c55c) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x09 + + +#endif /* #ifdef _AVR_AVR128DA32_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/ioavr128da48.h b/hardware/tools/avr/avr/include/avr/ioavr128da48.h new file mode 100644 index 0000000000000000000000000000000000000000..0c7ab053682b284435b47379201996980836edb2 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/ioavr128da48.h @@ -0,0 +1,7494 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioavr128da48.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_AVR128DA48_H_INCLUDED +#define _AVR_AVR128DA48_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPZ _SFR_MEM8(0x003B) /* Extended Z-pointer Register */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t MUXCTRL; /* Mux Control A */ + register8_t reserved_1[2]; + register8_t DACREF; /* DAC Voltage Reference */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NONE_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_MEDIUM_gc = (0x02<<1), /* Medium hysteresis */ + AC_HYSMODE_LARGE_gc = (0x03<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* AC Output Initial Value select */ +typedef enum AC_INITVAL_enum +{ + AC_INITVAL_LOW_gc = (0x00<<6), /* Output initialized to 0 */ + AC_INITVAL_HIGH_gc = (0x01<<6), /* Output initialized to 1 */ +} AC_INITVAL_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_ABOVE_gc = (0x00<<4), /* Entering window state above */ + AC_INTMODE_INSIDE_gc = (0x01<<4), /* Entering window state inside */ + AC_INTMODE_BELOW_gc = (0x02<<4), /* Entering window state below */ + AC_INTMODE_OUTSIDE_gc = (0x03<<4), /* Entering window state above or below */ +} AC_INTMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_AINN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_AINN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_AINN2_gc = (0x02<<0), /* Negative Pin 2 */ + AC_MUXNEG_DACREF_gc = (0x03<<0), /* DAC Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_AINP0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_AINP1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_AINP2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_AINP3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* Power profile select */ +typedef enum AC_POWER_enum +{ + AC_POWER_PROFILE0_gc = (0x00<<3), /* Power profile 0, lowest consumption and highest response time. */ + AC_POWER_PROFILE1_gc = (0x01<<3), /* Power profile 1 */ + AC_POWER_PROFILE2_gc = (0x02<<3), /* Power profile 2 */ + AC_POWER_PROFILE3_gc = (0x03<<3), /* Power profile 3 */ +} AC_POWER_t; + +/* Window selection mode select */ +typedef enum AC_WINSEL_enum +{ + AC_WINSEL_DISABLED_gc = (0x00<<0), /* Window function disabled */ + AC_WINSEL_UPSEL1_gc = (0x01<<0), /* Select ACn+1 as upper limit in window compare. */ + AC_WINSEL_UPSEL2_gc = (0x02<<0), /* Select ACn+2 as upper limit in window compare. */ +} AC_WINSEL_t; + +/* Analog Comparator Window State select */ +typedef enum AC_WINSTATE_enum +{ + AC_WINSTATE_ABOVE_gc = (0x00<<6), /* Above window */ + AC_WINSTATE_INSIDE_gc = (0x01<<6), /* Inside window */ + AC_WINSTATE_BELOW_gc = (0x02<<6), /* Below window */ +} AC_WINSTATE_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t reserved_1[2]; + register8_t MUXPOS; /* Positive mux input */ + register8_t MUXNEG; /* Negative mux input */ + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t reserved_2[2]; +} ADC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXNEG_enum +{ + ADC_MUXNEG_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXNEG_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXNEG_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXNEG_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXNEG_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXNEG_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXNEG_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXNEG_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXNEG_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXNEG_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXNEG_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXNEG_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXNEG_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ + ADC_MUXNEG_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ + ADC_MUXNEG_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ + ADC_MUXNEG_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ + ADC_MUXNEG_GND_gc = (0x40<<0), /* Ground */ + ADC_MUXNEG_DAC0_gc = (0x48<<0), /* DAC0 */ +} ADC_MUXNEG_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ + ADC_MUXPOS_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ + ADC_MUXPOS_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ + ADC_MUXPOS_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ + ADC_MUXPOS_AIN16_gc = (0x10<<0), /* ADC input pin 16 */ + ADC_MUXPOS_AIN17_gc = (0x11<<0), /* ADC input pin 17 */ + ADC_MUXPOS_AIN18_gc = (0x12<<0), /* ADC input pin 18 */ + ADC_MUXPOS_AIN19_gc = (0x13<<0), /* ADC input pin 19 */ + ADC_MUXPOS_AIN20_gc = (0x14<<0), /* ADC input pin 20 */ + ADC_MUXPOS_AIN21_gc = (0x15<<0), /* ADC input pin 21 */ + ADC_MUXPOS_GND_gc = (0x40<<0), /* Ground */ + ADC_MUXPOS_TEMPSENSE_gc = (0x42<<0), /* Temperature sensor */ + ADC_MUXPOS_DAC0_gc = (0x48<<0), /* DAC0 */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV12_gc = (0x03<<0), /* CLK_PER divided by 12 */ + ADC_PRESC_DIV16_gc = (0x04<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV20_gc = (0x05<<0), /* CLK_PER divided by 20 */ + ADC_PRESC_DIV24_gc = (0x06<<0), /* CLK_PER divided by 24 */ + ADC_PRESC_DIV28_gc = (0x07<<0), /* CLK_PER divided by 28 */ + ADC_PRESC_DIV32_gc = (0x08<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV48_gc = (0x09<<0), /* CLK_PER divided by 48 */ + ADC_PRESC_DIV64_gc = (0x0A<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV96_gc = (0x0B<<0), /* CLK_PER divided by 96 */ + ADC_PRESC_DIV128_gc = (0x0C<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x0D<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Resolution selection select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_12BIT_gc = (0x00<<2), /* 12-bit mode */ + ADC_RESSEL_10BIT_gc = (0x01<<2), /* 10-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_NONE_gc = (0x00<<0), /* No accumulation */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* 2 results accumulated */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* 4 results accumulated */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* 8 results accumulated */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* 16 results accumulated */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* 32 results accumulated */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* 64 results accumulated */ + ADC_SAMPNUM_ACC128_gc = (0x07<<0), /* 128 results accumulated */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.9 V */ + BOD_LVL_BODLEVEL1_gc = (0x01<<0), /* 2.45 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.7 V */ + BOD_LVL_BODLEVEL3_gc = (0x03<<0), /* 2.85 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_128HZ_gc = (0x00<<4), /* 128Hz sampling frequency */ + BOD_SAMPFREQ_32HZ_gc = (0x01<<4), /* 32Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_FALLING_gc = (0x00<<1), /* VDD falls below VLM threshold */ + BOD_VLMCFG_RISING_gc = (0x01<<1), /* VDD rises above VLM threshold */ + BOD_VLMCFG_BOTH_gc = (0x02<<1), /* VDD crosses VLM threshold */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_OFF_gc = (0x00<<0), /* VLM Disabled */ + BOD_VLMLVL_5ABOVE_gc = (0x01<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x02<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x03<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* Voltage level monitor status select */ +typedef enum BOD_VLMS_enum +{ + BOD_VLMS_ABOVE_gc = (0x00<<0), /* The voltage is above the VLM threshold level */ + BOD_VLMS_BELOW_gc = (0x01<<0), /* The voltage is below the VLM threshold level */ +} BOD_VLMS_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t SEQCTRL1; /* Sequential Control 1 */ + register8_t SEQCTRL2; /* Sequential Control 2 */ + register8_t reserved_1[1]; + register8_t INTCTRL0; /* Interrupt Control 0 */ + register8_t INTCTRL1; /* Interrupt Control 1 */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t LUT2CTRLA; /* LUT Control 2 A */ + register8_t LUT2CTRLB; /* LUT Control 2 B */ + register8_t LUT2CTRLC; /* LUT Control 2 C */ + register8_t TRUTH2; /* Truth 2 */ + register8_t LUT3CTRLA; /* LUT Control 3 A */ + register8_t LUT3CTRLB; /* LUT Control 3 B */ + register8_t LUT3CTRLC; /* LUT Control 3 C */ + register8_t TRUTH3; /* Truth 3 */ + register8_t LUT4CTRLA; /* LUT Control 4 A */ + register8_t LUT4CTRLB; /* LUT Control 4 B */ + register8_t LUT4CTRLC; /* LUT Control 4 C */ + register8_t TRUTH4; /* Truth 4 */ + register8_t LUT5CTRLA; /* LUT Control 5 A */ + register8_t LUT5CTRLB; /* LUT Control 5 B */ + register8_t LUT5CTRLC; /* LUT Control 5 C */ + register8_t TRUTH5; /* Truth 5 */ + register8_t reserved_2[32]; +} CCL_t; + +/* Clock Source Selection select */ +typedef enum CCL_CLKSRC_enum +{ + CCL_CLKSRC_CLKPER_gc = (0x00<<1), /* CLK_PER is clocking the LUT */ + CCL_CLKSRC_IN2_gc = (0x01<<1), /* IN[2] is clocking the LUT */ + CCL_CLKSRC_OSCHF_gc = (0x04<<1), /* Internal high-frequency oscillator before prescaler is clocking LUT */ + CCL_CLKSRC_OSC32K_gc = (0x05<<1), /* Internal 32.768 kHz oscillator */ + CCL_CLKSRC_OSC1K_gc = (0x06<<1), /* Internal 32.768 kHz oscillator divided by 32 */ +} CCL_CLKSRC_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL0_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL0_IN0_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_ZCD0_gc = (0x07<<0), /* ZCD0 OUT input source */ + CCL_INSEL0_USART0_gc = (0x08<<0), /* USART0 TXD input source */ + CCL_INSEL0_SPI0_gc = (0x09<<0), /* SPI0 MOSI input source */ + CCL_INSEL0_TCA0_gc = (0x0A<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCA1_gc = (0x0B<<0), /* TCA1 WO0 input source */ + CCL_INSEL0_TCB0_gc = (0x0C<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCD0_gc = (0x0D<<0), /* TCD0 WOA input source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENTA_gc = (0x03<<4), /* Event input source A */ + CCL_INSEL1_EVENTB_gc = (0x04<<4), /* Event input source B */ + CCL_INSEL1_IN1_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC1_gc = (0x06<<4), /* AC1 OUT input source */ + CCL_INSEL1_ZCD1_gc = (0x07<<4), /* ZCD1 OUT input source */ + CCL_INSEL1_USART1_gc = (0x08<<4), /* USART1 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x09<<4), /* SPI0 MOSI input source */ + CCL_INSEL1_TCA0_gc = (0x0A<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCA1_gc = (0x0B<<4), /* TCA1 WO1 input source */ + CCL_INSEL1_TCB1_gc = (0x0C<<4), /* TCB1 WO input source */ + CCL_INSEL1_TCD0_gc = (0x0D<<4), /* TCD0 WOB input soruce */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL2_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL2_IN2_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC2_gc = (0x06<<0), /* AC2 OUT input source */ + CCL_INSEL2_ZCD2_gc = (0x07<<0), /* ZCD2 OUT input source */ + CCL_INSEL2_USART2_gc = (0x08<<0), /* USART2 TXD input source */ + CCL_INSEL2_SPI0_gc = (0x09<<0), /* SPI0 SCK input source */ + CCL_INSEL2_TCA0_gc = (0x0A<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCA1_gc = (0x0B<<0), /* TCA1 WO2 input source */ + CCL_INSEL2_TCB2_gc = (0x0C<<0), /* TCB2 WO input source */ + CCL_INSEL2_TCD0_gc = (0x0D<<0), /* TCD0 WOC input source */ +} CCL_INSEL2_t; + +/* Interrupt Mode for LUT0 select */ +typedef enum CCL_INTMODE0_enum +{ + CCL_INTMODE0_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled */ + CCL_INTMODE0_RISING_gc = (0x01<<0), /* Sense rising edge */ + CCL_INTMODE0_FALLING_gc = (0x02<<0), /* Sense falling edge */ + CCL_INTMODE0_BOTH_gc = (0x03<<0), /* Sense both edges */ +} CCL_INTMODE0_t; + +/* Interrupt Mode for LUT1 select */ +typedef enum CCL_INTMODE1_enum +{ + CCL_INTMODE1_INTDISABLE_gc = (0x00<<2), /* Interrupt disabled */ + CCL_INTMODE1_RISING_gc = (0x01<<2), /* Sense rising edge */ + CCL_INTMODE1_FALLING_gc = (0x02<<2), /* Sense falling edge */ + CCL_INTMODE1_BOTH_gc = (0x03<<2), /* Sense both edges */ +} CCL_INTMODE1_t; + +/* Interrupt Mode for LUT2 select */ +typedef enum CCL_INTMODE2_enum +{ + CCL_INTMODE2_INTDISABLE_gc = (0x00<<4), /* Interrupt disabled */ + CCL_INTMODE2_RISING_gc = (0x01<<4), /* Sense rising edge */ + CCL_INTMODE2_FALLING_gc = (0x02<<4), /* Sense falling edge */ + CCL_INTMODE2_BOTH_gc = (0x03<<4), /* Sense both edges */ +} CCL_INTMODE2_t; + +/* Interrupt Mode for LUT3 select */ +typedef enum CCL_INTMODE3_enum +{ + CCL_INTMODE3_INTDISABLE_gc = (0x00<<6), /* Interrupt disabled */ + CCL_INTMODE3_RISING_gc = (0x01<<6), /* Sense rising edge */ + CCL_INTMODE3_FALLING_gc = (0x02<<6), /* Sense falling edge */ + CCL_INTMODE3_BOTH_gc = (0x03<<6), /* Sense both edges */ +} CCL_INTMODE3_t; + +/* Interrupt Mode for LUT4 select */ +typedef enum CCL_INTMODE4_enum +{ + CCL_INTMODE4_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled */ + CCL_INTMODE4_RISING_gc = (0x01<<0), /* Sense rising edge */ + CCL_INTMODE4_FALLING_gc = (0x02<<0), /* Sense falling edge */ + CCL_INTMODE4_BOTH_gc = (0x03<<0), /* Sense both edges */ +} CCL_INTMODE4_t; + +/* Interrupt Mode for LUT5 select */ +typedef enum CCL_INTMODE5_enum +{ + CCL_INTMODE5_INTDISABLE_gc = (0x00<<2), /* Interrupt disabled */ + CCL_INTMODE5_RISING_gc = (0x01<<2), /* Sense rising edge */ + CCL_INTMODE5_FALLING_gc = (0x02<<2), /* Sense falling edge */ + CCL_INTMODE5_BOTH_gc = (0x03<<2), /* Sense both edges */ +} CCL_INTMODE5_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL0_enum +{ + CCL_SEQSEL0_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL0_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL0_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL0_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL0_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL0_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL1_enum +{ + CCL_SEQSEL1_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL1_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL1_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL1_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL1_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL1_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL2_enum +{ + CCL_SEQSEL2_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL2_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL2_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL2_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL2_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL2_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[4]; + register8_t OSCHFCTRLA; /* OSCHF Control A */ + register8_t OSCHFTUNE; /* OSCHF Tune */ + register8_t reserved_2[6]; + register8_t PLLCTRLA; /* PLL Control A */ + register8_t reserved_3[7]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_4[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_5[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSCHF_gc = (0x00<<0), /* Internal high-frequency oxcillator */ + CLKCTRL_CLKSEL_OSC32K_gc = (0x01<<0), /* Internal 32.768 kHz oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768 kHz crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1k cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16k cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32k cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ +} CLKCTRL_CSUT_t; + +/* Frequency select select */ +typedef enum CLKCTRL_FREQSEL_enum +{ + CLKCTRL_FREQSEL_1M_gc = (0x00<<2), /* 1 MHz system clock */ + CLKCTRL_FREQSEL_2M_gc = (0x01<<2), /* 2 MHz system clock */ + CLKCTRL_FREQSEL_3M_gc = (0x02<<2), /* 3 MHz system clock */ + CLKCTRL_FREQSEL_4M_gc = (0x03<<2), /* 4 MHz system clock (default) */ + CLKCTRL_FREQSEL_8M_gc = (0x05<<2), /* 8 MHz system clock */ + CLKCTRL_FREQSEL_12M_gc = (0x06<<2), /* 12 MHz system clock */ + CLKCTRL_FREQSEL_16M_gc = (0x07<<2), /* 16 MHz system clock */ + CLKCTRL_FREQSEL_20M_gc = (0x08<<2), /* 20 MHz system clock */ + CLKCTRL_FREQSEL_24M_gc = (0x09<<2), /* 24 MHz system clock */ +} CLKCTRL_FREQSEL_t; + +/* Multiplication factor select */ +typedef enum CLKCTRL_MULFAC_enum +{ + CLKCTRL_MULFAC_DISABLE_gc = (0x00<<0), /* PLL is disabled */ + CLKCTRL_MULFAC_2x_gc = (0x01<<0), /* 2 x multiplication factor */ + CLKCTRL_MULFAC_3x_gc = (0x02<<0), /* 3 x multiplication factor */ + CLKCTRL_MULFAC_4x_gc = (0x03<<0), /* 4 x multiplication factor */ +} CLKCTRL_MULFAC_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* DATA Register */ +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t SWEVENTA; /* Software Event A */ + register8_t SWEVENTB; /* Software Event B */ + register8_t reserved_1[14]; + register8_t CHANNEL0; /* Multiplexer Channel 0 */ + register8_t CHANNEL1; /* Multiplexer Channel 1 */ + register8_t CHANNEL2; /* Multiplexer Channel 2 */ + register8_t CHANNEL3; /* Multiplexer Channel 3 */ + register8_t CHANNEL4; /* Multiplexer Channel 4 */ + register8_t CHANNEL5; /* Multiplexer Channel 5 */ + register8_t CHANNEL6; /* Multiplexer Channel 6 */ + register8_t CHANNEL7; /* Multiplexer Channel 7 */ + register8_t CHANNEL8; /* Multiplexer Channel 8 */ + register8_t CHANNEL9; /* Multiplexer Channel 9 */ + register8_t reserved_2[6]; + register8_t USERCCLLUT0A; /* User 0 - CCL0 Event A */ + register8_t USERCCLLUT0B; /* User 1 - CCL0 Event B */ + register8_t USERCCLLUT1A; /* User 2 - CCL1 Event A */ + register8_t USERCCLLUT1B; /* User 3 - CCL1 Event B */ + register8_t USERCCLLUT2A; /* User 4 - CCL2 Event A */ + register8_t USERCCLLUT2B; /* User 5 - CCL2 Event B */ + register8_t USERCCLLUT3A; /* User 6 - CCL3 Event A */ + register8_t USERCCLLUT3B; /* User 7 - CCL3 Event B */ + register8_t USERCCLLUT4A; /* User 8 - CCL4 Event A */ + register8_t USERCCLLUT4B; /* User 9 - CCL4 Event B */ + register8_t USERCCLLUT5A; /* User 10 - CCL5 Event A */ + register8_t USERCCLLUT5B; /* User 11 - CCL5 Event B */ + register8_t USERADC0START; /* User 12 - ADC0 */ + register8_t USERPTCSTART; /* User 13 - PTC */ + register8_t USEREVSYSEVOUTA; /* User 14 - EVOUTA */ + register8_t USEREVSYSEVOUTB; /* User 15 - EVOUTB */ + register8_t USEREVSYSEVOUTC; /* User 16 - EVOUTC */ + register8_t USEREVSYSEVOUTD; /* User 17 - EVOUTD */ + register8_t USEREVSYSEVOUTE; /* User 18 - EVOUTE */ + register8_t USEREVSYSEVOUTF; /* User 19 - EVOUTF */ + register8_t USEREVSYSEVOUTG; /* User 20 - EVOUTG */ + register8_t USERUSART0IRDA; /* User 21 - USART0 */ + register8_t USERUSART1IRDA; /* User 22 - USART1 */ + register8_t USERUSART2IRDA; /* User 23 - USART2 */ + register8_t USERUSART3IRDA; /* User 24 - USART3 */ + register8_t USERUSART4IRDA; /* User 25 - USART4 */ + register8_t USERUSART5IRDA; /* User 26 - USART5 */ + register8_t USERTCA0CNTA; /* User 27 - TCA0 Event A */ + register8_t USERTCA0CNTB; /* User 28 - TCA0 Event B */ + register8_t USERTCA1CNTA; /* User 29 - TCA1 Event A */ + register8_t USERTCA1CNTB; /* User 30 - TCA1 Event B */ + register8_t USERTCB0CAPT; /* User 31 - TCB0 Event A */ + register8_t USERTCB0COUNT; /* User 32 - TCB0 Event B */ + register8_t USERTCB1CAPT; /* User 33 - TCB1 Event A */ + register8_t USERTCB1COUNT; /* User 34 - TCB1 Event B */ + register8_t USERTCB2CAPT; /* User 35 - TCB2 Event A */ + register8_t USERTCB2COUNT; /* User 36 - TCB2 Event B */ + register8_t USERTCB3CAPT; /* User 37 - TCB3 Event A */ + register8_t USERTCB3COUNT; /* User 38 - TCB3 Event B */ + register8_t USERTCB4CAPT; /* User 39 - TCB4 Event A */ + register8_t USERTCB4COUNT; /* User 40 - TCB4 Event B */ + register8_t USERTCD0INPUTA; /* User 41 - TCD0 Event A */ + register8_t USERTCD0INPUTB; /* User 42 - TCD0 Event B */ + register8_t USEROSCTEST; /* User 43 - OSCTEST */ +} EVSYS_t; + +/* Channel 0 generator select select */ +typedef enum EVSYS_CHANNEL0_enum +{ + EVSYS_CHANNEL0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL0_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL0_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL0_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL0_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL0_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL0_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL0_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL0_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL0_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL0_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL0_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL0_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL0_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL0_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL0_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL0_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL0_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL0_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL0_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL0_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL0_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL0_PORTA_PIN0_gc = (0x40<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL0_PORTA_PIN1_gc = (0x41<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL0_PORTA_PIN2_gc = (0x42<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL0_PORTA_PIN3_gc = (0x43<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL0_PORTA_PIN4_gc = (0x44<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL0_PORTA_PIN5_gc = (0x45<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL0_PORTA_PIN6_gc = (0x46<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL0_PORTA_PIN7_gc = (0x47<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL0_PORTB_PIN0_gc = (0x48<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL0_PORTB_PIN1_gc = (0x49<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL0_PORTB_PIN2_gc = (0x4A<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL0_PORTB_PIN3_gc = (0x4B<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL0_PORTB_PIN4_gc = (0x4C<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL0_PORTB_PIN5_gc = (0x4D<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL0_PORTB_PIN6_gc = (0x4E<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL0_PORTB_PIN7_gc = (0x4F<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL0_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL0_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL0_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL0_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL0_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL0_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL0_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL0_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL0_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL0_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL0_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL0_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL0_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL0_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL0_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL0_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL0_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL0_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL0_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL0_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL0_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL0_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL0_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL0_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL0_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL0_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL0_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL0_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL0_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL0_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL0_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL0_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL0_t; + +/* Channel 1 generator select select */ +typedef enum EVSYS_CHANNEL1_enum +{ + EVSYS_CHANNEL1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL1_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL1_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL1_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL1_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL1_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL1_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL1_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL1_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL1_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL1_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL1_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL1_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL1_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL1_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL1_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL1_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL1_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL1_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL1_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL1_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL1_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL1_PORTA_PIN0_gc = (0x40<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL1_PORTA_PIN1_gc = (0x41<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL1_PORTA_PIN2_gc = (0x42<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL1_PORTA_PIN3_gc = (0x43<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL1_PORTA_PIN4_gc = (0x44<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL1_PORTA_PIN5_gc = (0x45<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL1_PORTA_PIN6_gc = (0x46<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL1_PORTA_PIN7_gc = (0x47<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL1_PORTB_PIN0_gc = (0x48<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL1_PORTB_PIN1_gc = (0x49<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL1_PORTB_PIN2_gc = (0x4A<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL1_PORTB_PIN3_gc = (0x4B<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL1_PORTB_PIN4_gc = (0x4C<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL1_PORTB_PIN5_gc = (0x4D<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL1_PORTB_PIN6_gc = (0x4E<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL1_PORTB_PIN7_gc = (0x4F<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL1_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL1_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL1_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL1_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL1_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL1_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL1_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL1_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL1_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL1_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL1_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL1_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL1_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL1_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL1_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL1_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL1_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL1_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL1_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL1_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL1_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL1_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL1_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL1_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL1_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL1_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL1_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL1_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL1_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL1_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL1_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL1_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL1_t; + +/* Channel 2 generator select select */ +typedef enum EVSYS_CHANNEL2_enum +{ + EVSYS_CHANNEL2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL2_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL2_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL2_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL2_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL2_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL2_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL2_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL2_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL2_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL2_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL2_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL2_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL2_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL2_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL2_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL2_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL2_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL2_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL2_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL2_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL2_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL2_PORTC_PIN0_gc = (0x40<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL2_PORTC_PIN1_gc = (0x41<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL2_PORTC_PIN2_gc = (0x42<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL2_PORTC_PIN3_gc = (0x43<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL2_PORTC_PIN4_gc = (0x44<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL2_PORTC_PIN5_gc = (0x45<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL2_PORTC_PIN6_gc = (0x46<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL2_PORTC_PIN7_gc = (0x47<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL2_PORTD_PIN0_gc = (0x48<<0), /* Port D Pin 0 */ + EVSYS_CHANNEL2_PORTD_PIN1_gc = (0x49<<0), /* Port D Pin 1 */ + EVSYS_CHANNEL2_PORTD_PIN2_gc = (0x4A<<0), /* Port D Pin 2 */ + EVSYS_CHANNEL2_PORTD_PIN3_gc = (0x4B<<0), /* Port D Pin 3 */ + EVSYS_CHANNEL2_PORTD_PIN4_gc = (0x4C<<0), /* Port D Pin 4 */ + EVSYS_CHANNEL2_PORTD_PIN5_gc = (0x4D<<0), /* Port D Pin 5 */ + EVSYS_CHANNEL2_PORTD_PIN6_gc = (0x4E<<0), /* Port D Pin 6 */ + EVSYS_CHANNEL2_PORTD_PIN7_gc = (0x4F<<0), /* Port D Pin 7 */ + EVSYS_CHANNEL2_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL2_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL2_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL2_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL2_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL2_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL2_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL2_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL2_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL2_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL2_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL2_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL2_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL2_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL2_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL2_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL2_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL2_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL2_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL2_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL2_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL2_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL2_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL2_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL2_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL2_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL2_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL2_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL2_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL2_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL2_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL2_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL2_t; + +/* Channel 3 generator select select */ +typedef enum EVSYS_CHANNEL3_enum +{ + EVSYS_CHANNEL3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL3_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL3_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL3_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL3_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL3_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL3_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL3_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL3_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL3_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL3_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL3_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL3_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL3_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL3_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL3_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL3_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL3_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL3_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL3_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL3_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL3_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL3_PORTC_PIN0_gc = (0x40<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL3_PORTC_PIN1_gc = (0x41<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL3_PORTC_PIN2_gc = (0x42<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL3_PORTC_PIN3_gc = (0x43<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL3_PORTC_PIN4_gc = (0x44<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL3_PORTC_PIN5_gc = (0x45<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL3_PORTC_PIN6_gc = (0x46<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL3_PORTC_PIN7_gc = (0x47<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL3_PORTD_PIN0_gc = (0x48<<0), /* Port D Pin 0 */ + EVSYS_CHANNEL3_PORTD_PIN1_gc = (0x49<<0), /* Port D Pin 1 */ + EVSYS_CHANNEL3_PORTD_PIN2_gc = (0x4A<<0), /* Port D Pin 2 */ + EVSYS_CHANNEL3_PORTD_PIN3_gc = (0x4B<<0), /* Port D Pin 3 */ + EVSYS_CHANNEL3_PORTD_PIN4_gc = (0x4C<<0), /* Port D Pin 4 */ + EVSYS_CHANNEL3_PORTD_PIN5_gc = (0x4D<<0), /* Port D Pin 5 */ + EVSYS_CHANNEL3_PORTD_PIN6_gc = (0x4E<<0), /* Port D Pin 6 */ + EVSYS_CHANNEL3_PORTD_PIN7_gc = (0x4F<<0), /* Port D Pin 7 */ + EVSYS_CHANNEL3_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL3_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL3_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL3_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL3_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL3_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL3_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL3_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL3_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL3_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL3_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL3_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL3_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL3_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL3_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL3_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL3_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL3_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL3_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL3_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL3_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL3_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL3_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL3_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL3_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL3_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL3_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL3_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL3_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL3_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL3_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL3_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL3_t; + +/* Channel 4 generator select select */ +typedef enum EVSYS_CHANNEL4_enum +{ + EVSYS_CHANNEL4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL4_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL4_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL4_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL4_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL4_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL4_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL4_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL4_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL4_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL4_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL4_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL4_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL4_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL4_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL4_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL4_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL4_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL4_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL4_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL4_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL4_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL4_PORTE_PIN0_gc = (0x40<<0), /* Port E Pin 0 */ + EVSYS_CHANNEL4_PORTE_PIN1_gc = (0x41<<0), /* Port E Pin 1 */ + EVSYS_CHANNEL4_PORTE_PIN2_gc = (0x42<<0), /* Port E Pin 2 */ + EVSYS_CHANNEL4_PORTE_PIN3_gc = (0x43<<0), /* Port E Pin 3 */ + EVSYS_CHANNEL4_PORTE_PIN4_gc = (0x44<<0), /* Port E Pin 4 */ + EVSYS_CHANNEL4_PORTE_PIN5_gc = (0x45<<0), /* Port E Pin 5 */ + EVSYS_CHANNEL4_PORTE_PIN6_gc = (0x46<<0), /* Port E Pin 6 */ + EVSYS_CHANNEL4_PORTE_PIN7_gc = (0x47<<0), /* Port E Pin 7 */ + EVSYS_CHANNEL4_PORTF_PIN0_gc = (0x48<<0), /* Port F Pin 0 */ + EVSYS_CHANNEL4_PORTF_PIN1_gc = (0x49<<0), /* Port F Pin 1 */ + EVSYS_CHANNEL4_PORTF_PIN2_gc = (0x4A<<0), /* Port F Pin 2 */ + EVSYS_CHANNEL4_PORTF_PIN3_gc = (0x4B<<0), /* Port F Pin 3 */ + EVSYS_CHANNEL4_PORTF_PIN4_gc = (0x4C<<0), /* Port F Pin 4 */ + EVSYS_CHANNEL4_PORTF_PIN5_gc = (0x4D<<0), /* Port F Pin 5 */ + EVSYS_CHANNEL4_PORTF_PIN6_gc = (0x4E<<0), /* Port F Pin 6 */ + EVSYS_CHANNEL4_PORTF_PIN7_gc = (0x4F<<0), /* Port F Pin 7 */ + EVSYS_CHANNEL4_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL4_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL4_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL4_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL4_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL4_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL4_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL4_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL4_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL4_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL4_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL4_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL4_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL4_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL4_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL4_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL4_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL4_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL4_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL4_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL4_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL4_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL4_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL4_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL4_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL4_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL4_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL4_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL4_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL4_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL4_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL4_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL4_t; + +/* Channel 5 generator select select */ +typedef enum EVSYS_CHANNEL5_enum +{ + EVSYS_CHANNEL5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL5_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL5_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL5_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL5_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL5_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL5_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL5_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL5_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL5_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL5_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL5_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL5_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL5_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL5_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL5_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL5_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL5_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL5_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL5_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL5_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL5_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL5_PORTE_PIN0_gc = (0x40<<0), /* Port E Pin 0 */ + EVSYS_CHANNEL5_PORTE_PIN1_gc = (0x41<<0), /* Port E Pin 1 */ + EVSYS_CHANNEL5_PORTE_PIN2_gc = (0x42<<0), /* Port E Pin 2 */ + EVSYS_CHANNEL5_PORTE_PIN3_gc = (0x43<<0), /* Port E Pin 3 */ + EVSYS_CHANNEL5_PORTE_PIN4_gc = (0x44<<0), /* Port E Pin 4 */ + EVSYS_CHANNEL5_PORTE_PIN5_gc = (0x45<<0), /* Port E Pin 5 */ + EVSYS_CHANNEL5_PORTE_PIN6_gc = (0x46<<0), /* Port E Pin 6 */ + EVSYS_CHANNEL5_PORTA_PIN7_gc = (0x47<<0), /* Port E Pin 7 */ + EVSYS_CHANNEL5_PORTF_PIN0_gc = (0x48<<0), /* Port F Pin 0 */ + EVSYS_CHANNEL5_PORTF_PIN1_gc = (0x49<<0), /* Port F Pin 1 */ + EVSYS_CHANNEL5_PORTF_PIN2_gc = (0x4A<<0), /* Port F Pin 2 */ + EVSYS_CHANNEL5_PORTF_PIN3_gc = (0x4B<<0), /* Port F Pin 3 */ + EVSYS_CHANNEL5_PORTF_PIN4_gc = (0x4C<<0), /* Port F Pin 4 */ + EVSYS_CHANNEL5_PORTF_PIN5_gc = (0x4D<<0), /* Port F Pin 5 */ + EVSYS_CHANNEL5_PORTF_PIN6_gc = (0x4E<<0), /* Port F Pin 6 */ + EVSYS_CHANNEL5_PORTF_PIN7_gc = (0x4F<<0), /* Port F Pin 7 */ + EVSYS_CHANNEL5_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL5_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL5_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL5_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL5_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL5_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL5_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL5_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL5_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL5_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL5_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL5_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL5_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL5_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL5_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL5_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL5_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL5_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL5_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL5_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL5_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL5_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL5_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL5_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL5_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL5_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL5_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL5_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL5_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL5_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL5_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL5_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL5_t; + +/* Channel 6 generator select select */ +typedef enum EVSYS_CHANNEL6_enum +{ + EVSYS_CHANNEL6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL6_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL6_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL6_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL6_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL6_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL6_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL6_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL6_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL6_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL6_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL6_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL6_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL6_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL6_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL6_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL6_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL6_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL6_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL6_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL6_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL6_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL6_PORTG_PIN0_gc = (0x40<<0), /* Port G Pin 0 */ + EVSYS_CHANNEL6_PORTG_PIN1_gc = (0x41<<0), /* Port G Pin 1 */ + EVSYS_CHANNEL6_PORTG_PIN2_gc = (0x42<<0), /* Port G Pin 2 */ + EVSYS_CHANNEL6_PORTG_PIN3_gc = (0x43<<0), /* Port G Pin 3 */ + EVSYS_CHANNEL6_PORTG_PIN4_gc = (0x44<<0), /* Port G Pin 4 */ + EVSYS_CHANNEL6_PORTG_PIN5_gc = (0x45<<0), /* Port G Pin 5 */ + EVSYS_CHANNEL6_PORTG_PIN6_gc = (0x46<<0), /* Port G Pin 6 */ + EVSYS_CHANNEL6_PORTG_PIN7_gc = (0x47<<0), /* Port G Pin 7 */ + EVSYS_CHANNEL6_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL6_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL6_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL6_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL6_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL6_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL6_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL6_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL6_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL6_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL6_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL6_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL6_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL6_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL6_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL6_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL6_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL6_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL6_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL6_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL6_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL6_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL6_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL6_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL6_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL6_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL6_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL6_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL6_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL6_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL6_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL6_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL6_t; + +/* Channel 7 generator select select */ +typedef enum EVSYS_CHANNEL7_enum +{ + EVSYS_CHANNEL7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL7_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL7_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL7_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL7_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL7_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL7_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL7_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL7_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL7_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL7_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL7_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL7_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL7_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL7_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL7_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL7_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL7_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL7_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL7_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL7_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL7_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL7_PORTG_PIN0_gc = (0x40<<0), /* Port G Pin 0 */ + EVSYS_CHANNEL7_PORTG_PIN1_gc = (0x41<<0), /* Port G Pin 1 */ + EVSYS_CHANNEL7_PORTG_PIN2_gc = (0x42<<0), /* Port G Pin 2 */ + EVSYS_CHANNEL7_PORTG_PIN3_gc = (0x43<<0), /* Port G Pin 3 */ + EVSYS_CHANNEL7_PORTG_PIN4_gc = (0x44<<0), /* Port G Pin 4 */ + EVSYS_CHANNEL7_PORTG_PIN5_gc = (0x45<<0), /* Port G Pin 5 */ + EVSYS_CHANNEL7_PORTG_PIN6_gc = (0x46<<0), /* Port G Pin 6 */ + EVSYS_CHANNEL7_PORTG_PIN7_gc = (0x47<<0), /* Port G Pin 7 */ + EVSYS_CHANNEL7_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL7_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL7_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL7_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL7_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL7_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL7_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL7_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL7_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL7_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL7_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL7_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL7_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL7_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL7_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL7_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL7_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL7_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL7_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL7_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL7_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL7_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL7_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL7_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL7_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL7_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL7_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL7_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL7_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL7_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL7_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL7_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL7_t; + +/* Channel 8 generator select select */ +typedef enum EVSYS_CHANNEL8_enum +{ + EVSYS_CHANNEL8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL8_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL8_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL8_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL8_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL8_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL8_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL8_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL8_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL8_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL8_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL8_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL8_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL8_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL8_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL8_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL8_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL8_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL8_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL8_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL8_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL8_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL8_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL8_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL8_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL8_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL8_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL8_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL8_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL8_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL8_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL8_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL8_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL8_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL8_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL8_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL8_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL8_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL8_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL8_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL8_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL8_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL8_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL8_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL8_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL8_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL8_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL8_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL8_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL8_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL8_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL8_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL8_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL8_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL8_t; + +/* Channel 9 generator select select */ +typedef enum EVSYS_CHANNEL9_enum +{ + EVSYS_CHANNEL9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL9_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL9_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL9_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL9_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL9_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL9_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL9_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL9_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL9_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL9_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL9_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL9_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL9_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL9_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL9_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL9_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL9_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL9_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL9_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL9_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL9_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL9_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL9_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL9_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL9_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL9_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL9_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL9_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL9_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL9_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL9_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL9_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL9_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL9_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL9_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL9_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL9_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL9_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL9_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL9_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL9_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL9_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL9_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL9_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL9_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL9_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL9_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL9_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL9_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL9_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL9_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL9_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL9_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL9_t; + +/* Software event on channel select select */ +typedef enum EVSYS_SWEVENTA_enum +{ + EVSYS_SWEVENTA_CH0_gc = (0x01<<0), /* Software event on channel 0 */ + EVSYS_SWEVENTA_CH1_gc = (0x02<<0), /* Software event on channel 1 */ + EVSYS_SWEVENTA_CH2_gc = (0x04<<0), /* Software event on channel 2 */ + EVSYS_SWEVENTA_CH3_gc = (0x08<<0), /* Software event on channel 3 */ + EVSYS_SWEVENTA_CH4_gc = (0x10<<0), /* Software event on channel 4 */ + EVSYS_SWEVENTA_CH5_gc = (0x20<<0), /* Software event on channel 5 */ + EVSYS_SWEVENTA_CH6_gc = (0x40<<0), /* Software event on channel 6 */ + EVSYS_SWEVENTA_CH7_gc = (0x80<<0), /* Software event on channel 7 */ +} EVSYS_SWEVENTA_t; + +/* Software event on channel select select */ +typedef enum EVSYS_SWEVENTB_enum +{ + EVSYS_SWEVENTB_CH8_gc = (0x00<<0), /* Software event on channel 8 */ + EVSYS_SWEVENTB_CH9_gc = (0x01<<0), /* Software event on channel 9 */ +} EVSYS_SWEVENTB_t; + +/* User channel select select */ +typedef enum EVSYS_USER_enum +{ + EVSYS_USER_OFF_gc = (0x00<<0), /* Off */ + EVSYS_USER_CHANNEL0_gc = (0x01<<0), /* Connect user to event channel 0 */ + EVSYS_USER_CHANNEL1_gc = (0x02<<0), /* Connect user to event channel 1 */ + EVSYS_USER_CHANNEL2_gc = (0x03<<0), /* Connect user to event channel 2 */ + EVSYS_USER_CHANNEL3_gc = (0x04<<0), /* Connect user to event channel 3 */ + EVSYS_USER_CHANNEL4_gc = (0x05<<0), /* Connect user to event channel 4 */ + EVSYS_USER_CHANNEL5_gc = (0x06<<0), /* Connect user to event channel 5 */ + EVSYS_USER_CHANNEL6_gc = (0x07<<0), /* Connect user to event channel 6 */ + EVSYS_USER_CHANNEL7_gc = (0x08<<0), /* Connect user to event channel 7 */ + EVSYS_USER_CHANNEL8_gc = (0x09<<0), /* Connect user to event channel 8 */ + EVSYS_USER_CHANNEL9_gc = (0x0A<<0), /* Connect user to event channel 9 */ +} EVSYS_USER_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t CODESIZE; /* Code Section Size */ + register8_t BOOTSIZE; /* Boot Section Size */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DISABLE_gc = (0x00<<2), /* BOD disabled */ + ACTIVE_ENABLE_gc = (0x01<<2), /* BOD enabled in continiuous mode */ + ACTIVE_SAMPLE_gc = (0x02<<2), /* BOD enabled in sampled mode */ + ACTIVE_ENABLEWAIT_gc = (0x03<<2), /* BOD enabled in continiuous mode. Execution is halted at wake-up until BOD is running. */ +} ACTIVE_t; + +/* Frequency Select select */ +typedef enum CLKSEL_enum +{ + CLKSEL_OSCHF_gc = (0x00<<0), /* 1-32MHz internal oscillator */ + CLKSEL_OSC32K_gc = (0x01<<0), /* 32.768kHz internal oscillator */ +} CLKSEL_t; + +/* CRC Select select */ +typedef enum CRCSEL_enum +{ + CRCSEL_CRC16_gc = (0x00<<5), /* Enable CRC16 */ + CRCSEL_CRC32_gc = (0x01<<5), /* Enable CRC32 */ +} CRCSEL_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* CRC of full Flash (boot, application code and application data) */ + CRCSRC_BOOT_gc = (0x01<<6), /* CRC of boot section */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* CRC of application code and boot sections */ + CRCSRC_NOCRC_gc = (0x03<<6), /* No CRC */ +} CRCSRC_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.9V */ + LVL_BODLEVEL1_gc = (0x01<<5), /* 2.45V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.7V */ + LVL_BODLEVEL3_gc = (0x03<<5), /* 2.85V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.0s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.0s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_128Hz_gc = (0x00<<4), /* Sample frequency is 128 Hz */ + SAMPFREQ_32Hz_gc = (0x01<<4), /* Sample frequency is 32 Hz */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DISABLE_gc = (0x00<<0), /* BOD disabled */ + SLEEP_ENABLE_gc = (0x01<<0), /* BOD enabled in continiuous mode */ + SLEEP_SAMPLE_gc = (0x02<<0), /* BOD enabled in sampled mode */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.0s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.0s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +GPR - General Purpose Registers +-------------------------------------------------------------------------- +*/ + +/* General Purpose Registers */ +typedef struct GPR_struct +{ + register8_t GPR0; /* General Purpose Register 0 */ + register8_t GPR1; /* General Purpose Register 1 */ + register8_t GPR2; /* General Purpose Register 2 */ + register8_t GPR3; /* General Purpose Register 3 */ +} GPR_t; + + +/* +-------------------------------------------------------------------------- +LOCK - Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lockbits */ +typedef struct LOCK_struct +{ + _DWORDREGISTER(KEY); /* Lock Key Bits */ +} LOCK_t; + +/* Lock Key select */ +typedef enum LOCK_KEY_enum +{ + LOCK_KEY_NOLOCK_gc = (0x5CC5C55C<<0), /* No locks */ + LOCK_KEY_RWLOCK_gc = (0xA33A3AA3<<0), /* Read and write lock */ +} LOCK_KEY_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _DWORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[4]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_NOOP_gc = (0x01<<0), /* No Operation */ + NVMCTRL_CMD_FLWR_gc = (0x02<<0), /* Flash Write */ + NVMCTRL_CMD_FLPER_gc = (0x08<<0), /* Flash Page Erase */ + NVMCTRL_CMD_FLMPER2_gc = (0x09<<0), /* Flash Multi-Page Erase 2 pages */ + NVMCTRL_CMD_FLMPER4_gc = (0x0A<<0), /* Flash Multi-Page Erase 4 pages */ + NVMCTRL_CMD_FLMPER8_gc = (0x0B<<0), /* Flash Multi-Page Erase 8 pages */ + NVMCTRL_CMD_FLMPER16_gc = (0x0C<<0), /* Flash Multi-Page Erase 16 pages */ + NVMCTRL_CMD_FLMPER32_gc = (0x0D<<0), /* Flash Multi-Page Erase 32 pages */ + NVMCTRL_CMD_EEWR_gc = (0x12<<0), /* EEPROM Write */ + NVMCTRL_CMD_EEERWR_gc = (0x13<<0), /* EEPROM Erase and Write */ + NVMCTRL_CMD_EEBER_gc = (0x18<<0), /* EEPROM Byte Erase */ + NVMCTRL_CMD_EEMBER2_gc = (0x19<<0), /* EEPROM Multi-Byte Erase 2 bytes */ + NVMCTRL_CMD_EEMBER4_gc = (0x1A<<0), /* EEPROM Multi-Byte Erase 4 bytes */ + NVMCTRL_CMD_EEMBER8_gc = (0x1B<<0), /* EEPROM Multi-Byte Erase 8 bytes */ + NVMCTRL_CMD_EEMBER16_gc = (0x1C<<0), /* EEPROM Multi-Byte Erase 16 bytes */ + NVMCTRL_CMD_EEMBER32_gc = (0x1D<<0), /* EEPROM Multi-Byte Erase 32 bytes */ + NVMCTRL_CMD_CHER_gc = (0x20<<0), /* Chip Erase Command */ + NVMCTRL_CMD_EECHER_gc = (0x30<<0), /* EEPROM Erase Command */ +} NVMCTRL_CMD_t; + +/* Write error select */ +typedef enum NVMCTRL_ERROR_enum +{ + NVMCTRL_ERROR_NOERROR_gc = (0x00<<4), /* No Error */ + NVMCTRL_ERROR_ILLEGALCMD_gc = (0x01<<4), /* Write command not selected */ + NVMCTRL_ERROR_ILLEGALSADDR_gc = (0x02<<4), /* Write to section not allowed */ + NVMCTRL_ERROR_DOUBLESELECT_gc = (0x03<<4), /* Selecting new write command while write command already seleted */ + NVMCTRL_ERROR_ONGOINGPROG_gc = (0x04<<4), /* Starting a new programming operation before previous is completed */ +} NVMCTRL_ERROR_t; + +/* Flash Mapping in Data space select */ +typedef enum NVMCTRL_FLMAP_enum +{ + NVMCTRL_FLMAP_SECTION0_gc = (0x00<<4), /* Flash section 0, 0 - 32KB */ + NVMCTRL_FLMAP_SECTION1_gc = (0x01<<4), /* Flash section 1, 32 - 64KB */ + NVMCTRL_FLMAP_SECTION2_gc = (0x02<<4), /* Flash section 2, 64 - 96KB */ + NVMCTRL_FLMAP_SECTION3_gc = (0x03<<4), /* Flash section 3, 96 - 128KB */ +} NVMCTRL_FLMAP_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t PORTCTRL; /* Port Control */ + register8_t PINCONFIG; /* Pin Control Config */ + register8_t PINCTRLUPD; /* Pin Control Update */ + register8_t PINCTRLSET; /* Pin Control Set */ + register8_t PINCTRLCLR; /* Pin Control Clear */ + register8_t reserved_1[1]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t EVSYSROUTEA; /* EVSYS route A */ + register8_t CCLROUTEA; /* CCL route A */ + register8_t USARTROUTEA; /* USART route A */ + register8_t USARTROUTEB; /* USART route B */ + register8_t SPIROUTEA; /* SPI route A */ + register8_t TWIROUTEA; /* TWI route A */ + register8_t TCAROUTEA; /* TCA route A */ + register8_t TCBROUTEA; /* TCB route A */ + register8_t TCDROUTEA; /* TCD route A */ + register8_t ACROUTEA; /* AC route A */ + register8_t ZCDROUTEA; /* ZCD route A */ + register8_t reserved_1[5]; +} PORTMUX_t; + +/* Analog Comparator 0 Output select */ +typedef enum PORTMUX_AC0_enum +{ + PORTMUX_AC0_DEFAULT_gc = (0x00<<0), /* OUT on PA7 */ + PORTMUX_AC0_ALT1_gc = (0x01<<0), /* OUT on PC6 */ +} PORTMUX_AC0_t; + +/* Analog Comparator 1 Output select */ +typedef enum PORTMUX_AC1_enum +{ + PORTMUX_AC1_DEFAULT_gc = (0x00<<1), /* OUT on PA7 */ + PORTMUX_AC1_ALT1_gc = (0x01<<1), /* OUT on PC6 */ +} PORTMUX_AC1_t; + +/* Analog Comparator 2 Output select */ +typedef enum PORTMUX_AC2_enum +{ + PORTMUX_AC2_DEFAULT_gc = (0x00<<2), /* OUT on PA7 */ + PORTMUX_AC2_ALT1_gc = (0x01<<2), /* OUT on PC6 */ +} PORTMUX_AC2_t; + +/* Event Output A select */ +typedef enum PORTMUX_EVOUTA_enum +{ + PORTMUX_EVOUTA_DEFAULT_gc = (0x00<<0), /* EVOUT on PA2 */ + PORTMUX_EVOUTA_ALT1_gc = (0x01<<0), /* EVOUT on PA7 */ +} PORTMUX_EVOUTA_t; + +/* Event Output B select */ +typedef enum PORTMUX_EVOUTB_enum +{ + PORTMUX_EVOUTB_DEFAULT_gc = (0x00<<1), /* EVOUT on PB2 */ + PORTMUX_EVOUTB_ALT1_gc = (0x01<<1), /* EVOUT on PB7 */ +} PORTMUX_EVOUTB_t; + +/* Event Output C select */ +typedef enum PORTMUX_EVOUTC_enum +{ + PORTMUX_EVOUTC_DEFAULT_gc = (0x00<<2), /* EVOUT on PC2 */ + PORTMUX_EVOUTC_ALT1_gc = (0x01<<2), /* EVOUT on PC7 */ +} PORTMUX_EVOUTC_t; + +/* Event Output D select */ +typedef enum PORTMUX_EVOUTD_enum +{ + PORTMUX_EVOUTD_DEFAULT_gc = (0x00<<3), /* EVOUT on PD2 */ + PORTMUX_EVOUTD_ALT1_gc = (0x01<<3), /* EVOUT on PD7 */ +} PORTMUX_EVOUTD_t; + +/* Event Output E select */ +typedef enum PORTMUX_EVOUTE_enum +{ + PORTMUX_EVOUTE_DEFAULT_gc = (0x00<<4), /* EVOUT on PE2 */ + PORTMUX_EVOUTE_ALT1_gc = (0x01<<4), /* EVOUT on PE7 */ +} PORTMUX_EVOUTE_t; + +/* Event Output F select */ +typedef enum PORTMUX_EVOUTF_enum +{ + PORTMUX_EVOUTF_DEFAULT_gc = (0x00<<5), /* EVOUT on PF2 */ +} PORTMUX_EVOUTF_t; + +/* Event Output G select */ +typedef enum PORTMUX_EVOUTG_enum +{ + PORTMUX_EVOUTG_DEFAULT_gc = (0x00<<6), /* EVOUT on PG2 */ + PORTMUX_EVOUTG_ALT1_gc = (0x01<<6), /* EVOUT on PG7 */ +} PORTMUX_EVOUTG_t; + +/* CCL Look-Up Table 0 Signals select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<0), /* Out: PA3 In: PA0, PA1, PA2 */ + PORTMUX_LUT0_ALT1_gc = (0x01<<0), /* Out: PA6 In: PA0, PA1, PA2 */ +} PORTMUX_LUT0_t; + +/* CCL Look-Up Table 1 Signals select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<1), /* Out: PC3 In: PC0, PC1, PC2 */ + PORTMUX_LUT1_ALT1_gc = (0x01<<1), /* Out: PC6 In: PC0, PC1, PC2 */ +} PORTMUX_LUT1_t; + +/* CCL Look-Up Table 2 Signals select */ +typedef enum PORTMUX_LUT2_enum +{ + PORTMUX_LUT2_DEFAULT_gc = (0x00<<2), /* Out: PD3 In: PD0, PD1, PD2 */ + PORTMUX_LUT2_ALT1_gc = (0x01<<2), /* Out: PD6 In: PD0, PD1, PD2 */ +} PORTMUX_LUT2_t; + +/* CCL Look-Up Table 3 Signals select */ +typedef enum PORTMUX_LUT3_enum +{ + PORTMUX_LUT3_DEFAULT_gc = (0x00<<3), /* Out: PF3 In: PF0, PF1, PF2 */ +} PORTMUX_LUT3_t; + +/* CCL Look-Up Table 4 Signals select */ +typedef enum PORTMUX_LUT4_enum +{ + PORTMUX_LUT4_DEFAULT_gc = (0x00<<4), /* Out: PB3 In: PB0, PB1, PB2 */ + PORTMUX_LUT4_ALT1_gc = (0x01<<4), /* Out: PB6 In: PB0, PB1, PB2 */ +} PORTMUX_LUT4_t; + +/* CCL Look-Up Table 5 Signals select */ +typedef enum PORTMUX_LUT5_enum +{ + PORTMUX_LUT5_DEFAULT_gc = (0x00<<5), /* Out: PG3 In: PG0, PG1, PG2 */ + PORTMUX_LUT5_ALT1_gc = (0x01<<5), /* Out: PG6 In: PG0, PG1, PG2 */ +} PORTMUX_LUT5_t; + +/* SPI0 Signals select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<0), /* PA4, PA5, PA6, PA7 */ + PORTMUX_SPI0_ALT1_gc = (0x01<<0), /* PE0, PE1, PE2, PE3 */ + PORTMUX_SPI0_ALT2_gc = (0x02<<0), /* PG4, PG5, PG6, PG7 */ + PORTMUX_SPI0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_SPI0_t; + +/* SPI1 Signals select */ +typedef enum PORTMUX_SPI1_enum +{ + PORTMUX_SPI1_DEFAULT_gc = (0x00<<2), /* PC0, PC1, PC2, PC3 */ + PORTMUX_SPI1_ALT1_gc = (0x01<<2), /* PC4, PC5, PC6, PC7 */ + PORTMUX_SPI1_ALT2_gc = (0x02<<2), /* PB4, PB5, PB6, PB7 */ + PORTMUX_SPI1_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_SPI1_t; + +/* TCA0 Signals select */ +typedef enum PORTMUX_TCA0_enum +{ + PORTMUX_TCA0_PORTA_gc = (0x00<<0), /* PA0, PA1, PA2, PA3, PA4, PA5 */ + PORTMUX_TCA0_PORTB_gc = (0x01<<0), /* PB0, PB1, PB2, PB3, PB4, PB5 */ + PORTMUX_TCA0_PORTC_gc = (0x02<<0), /* PC0, PC1, PC2, PC3, PC4, PC5 */ + PORTMUX_TCA0_PORTD_gc = (0x03<<0), /* PD0, PD1, PD2, PD3, PD4, PD5 */ + PORTMUX_TCA0_PORTE_gc = (0x04<<0), /* PE0, PE1, PE2, PE3, PE4, PE5 */ + PORTMUX_TCA0_PORTF_gc = (0x05<<0), /* PF0, PF1, PF2, PF3, PF4, PF5 */ + PORTMUX_TCA0_PORTG_gc = (0x06<<0), /* PG0, PG1, PG2, PG3, PG4, PG5 */ +} PORTMUX_TCA0_t; + +/* TCA1 Signals select */ +typedef enum PORTMUX_TCA1_enum +{ + PORTMUX_TCA1_PORTB_gc = (0x00<<3), /* PB0, PB1, PB2, PB3, PB4, PB5 */ + PORTMUX_TCA1_PORTC_gc = (0x01<<3), /* PC4, PC5, PC6 */ + PORTMUX_TCA1_PORTE_gc = (0x02<<3), /* PE4, PE5, PE6 */ + PORTMUX_TCA1_PORTG_gc = (0x03<<3), /* PG0, PG1, PG2, PG3, PG4, PG5 */ +} PORTMUX_TCA1_t; + +/* TCB0 Output select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* WO on PA2 */ + PORTMUX_TCB0_ALT1_gc = (0x01<<0), /* WO on PF4 */ +} PORTMUX_TCB0_t; + +/* TCB1 Output select */ +typedef enum PORTMUX_TCB1_enum +{ + PORTMUX_TCB1_DEFAULT_gc = (0x00<<1), /* WO on PA3 */ + PORTMUX_TCB1_ALT1_gc = (0x01<<1), /* WO on PF5 */ +} PORTMUX_TCB1_t; + +/* TCB2 Output select */ +typedef enum PORTMUX_TCB2_enum +{ + PORTMUX_TCB2_DEFAULT_gc = (0x00<<2), /* WO on PC0 */ + PORTMUX_TCB2_ALT1_gc = (0x01<<2), /* WO on PB4 */ +} PORTMUX_TCB2_t; + +/* TCB3 Output select */ +typedef enum PORTMUX_TCB3_enum +{ + PORTMUX_TCB3_DEFAULT_gc = (0x00<<3), /* WO on PB5 */ + PORTMUX_TCB3_ALT1_gc = (0x01<<3), /* WO on PC1 */ +} PORTMUX_TCB3_t; + +/* TCD0 Signals select */ +typedef enum PORTMUX_TCD0_enum +{ + PORTMUX_TCD0_DEFAULT_gc = (0x00<<0), /* PA4, PA5, PA6, PA7 */ + PORTMUX_TCD0_ALT1_gc = (0x01<<0), /* PB4, PB5, PB6, PB7 */ + PORTMUX_TCD0_ALT2_gc = (0x02<<0), /* PF0, PF1, PF2, PF3 */ + PORTMUX_TCD0_ALT3_gc = (0x03<<0), /* PG4, PG5, PG6, PG7 */ +} PORTMUX_TCD0_t; + +/* TWI0 Signals select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<0), /* PA2, PA3, PC2, PC3 */ + PORTMUX_TWI0_ALT1_gc = (0x01<<0), /* PA2, PA3, PC6, PC7 */ + PORTMUX_TWI0_ALT2_gc = (0x02<<0), /* PC2, PC3, PC6, PC7 */ +} PORTMUX_TWI0_t; + +/* TWI1 Signals select */ +typedef enum PORTMUX_TWI1_enum +{ + PORTMUX_TWI1_DEFAULT_gc = (0x00<<2), /* PF2, PF3, PB2, PB3 */ + PORTMUX_TWI1_ALT1_gc = (0x01<<2), /* PF2, PF3, PB6, PB7 */ + PORTMUX_TWI1_ALT2_gc = (0x02<<2), /* PB2, PB3, PB6, PB7 */ +} PORTMUX_TWI1_t; + +/* USART0 Signals select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* PA0, PA1, PA2, PA3 */ + PORTMUX_USART0_ALT1_gc = (0x01<<0), /* PA4, PA5, PA6, PA7 */ + PORTMUX_USART0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_USART0_t; + +/* USART1 Signals select */ +typedef enum PORTMUX_USART1_enum +{ + PORTMUX_USART1_DEFAULT_gc = (0x00<<2), /* PC0, PC1, PC2, PC3 */ + PORTMUX_USART1_ALT1_gc = (0x01<<2), /* PC4, PC5, PC6, PC7 */ + PORTMUX_USART1_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_USART1_t; + +/* USART2 Signals select */ +typedef enum PORTMUX_USART2_enum +{ + PORTMUX_USART2_DEFAULT_gc = (0x00<<4), /* PF0, PF1, PF2, PF3 */ + PORTMUX_USART2_ALT1_gc = (0x01<<4), /* PF4, PF5 */ + PORTMUX_USART2_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_USART2_t; + +/* USART3 Signals select */ +typedef enum PORTMUX_USART3_enum +{ + PORTMUX_USART3_DEFAULT_gc = (0x00<<6), /* PB0, PB1, PB2, PB3 */ + PORTMUX_USART3_ALT1_gc = (0x01<<6), /* PB4, PB5, PB6, PB7 */ + PORTMUX_USART3_NONE_gc = (0x03<<6), /* Not connected to any pins */ +} PORTMUX_USART3_t; + +/* USART4 Signals select */ +typedef enum PORTMUX_USART4_enum +{ + PORTMUX_USART4_DEFAULT_gc = (0x00<<0), /* PE0, PE1, PE2, PE3 */ + PORTMUX_USART4_ALT1_gc = (0x01<<0), /* PE4, PE5, PE6, PE7 */ + PORTMUX_USART4_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_USART4_t; + +/* Zero Cross Detector 0 Output select */ +typedef enum PORTMUX_ZCD0_enum +{ + PORTMUX_ZCD0_DEFAULT_gc = (0x00<<0), /* OUT on PA7 */ + PORTMUX_ZCD0_ALT1_gc = (0x01<<0), /* OUT on PC7 */ +} PORTMUX_ZCD0_t; + +/* Zero Cross Detector 1 Output select */ +typedef enum PORTMUX_ZCD1_enum +{ + PORTMUX_ZCD1_DEFAULT_gc = (0x00<<1), /* OUT on PA7 */ + PORTMUX_ZCD1_ALT1_gc = (0x01<<1), /* OUT on PC7 */ +} PORTMUX_ZCD1_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t CALIB; /* Calibration */ + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_1[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_2[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_3[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_OSC32K_gc = (0x00<<0), /* Internal 32.768 kHz oscillator */ + RTC_CLKSEL_OSC1K_gc = (0x01<<0), /* Internal 1.024 kHz oscillator */ + RTC_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768 kHz crystal oscillator */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t reserved_1[1]; + _WORDREGISTER(TEMPSENSE0); /* Temperature Calibration 0 */ + _WORDREGISTER(TEMPSENSE1); /* Temperature Calibration 1 */ + register8_t reserved_2[8]; + register8_t SERNUM0; /* LOTNUM0 */ + register8_t SERNUM1; /* LOTNUM1 */ + register8_t SERNUM2; /* LOTNUM2 */ + register8_t SERNUM3; /* LOTNUM3 */ + register8_t SERNUM4; /* LOTNUM4 */ + register8_t SERNUM5; /* LOTNUM5 */ + register8_t SERNUM6; /* RANDOM */ + register8_t SERNUM7; /* SCRIBE */ + register8_t SERNUM8; /* XPOS0 */ + register8_t SERNUM9; /* XPOS1 */ + register8_t SERNUM10; /* YPOS0 */ + register8_t SERNUM11; /* YPOS1 */ + register8_t SERNUM12; /* RES0 */ + register8_t SERNUM13; /* RES1 */ + register8_t SERNUM14; /* RES2 */ + register8_t SERNUM15; /* RES3 */ + register8_t reserved_3[32]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t VREGCTRL; /* Control B */ +} SLPCTRL_t; + +/* Performance Mode select */ +typedef enum SLPCTRL_PMODE_enum +{ + SLPCTRL_PMODE_AUTO_gc = (0x00<<0), /* */ + SLPCTRL_PMODE_FULL_gc = (0x01<<0), /* */ +} SLPCTRL_PMODE_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t reserved_2[22]; + register8_t OCDMCTRL; /* OCD Message Control */ + register8_t OCDMSTATUS; /* OCD Message Status */ + register8_t reserved_3[6]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action A select */ +typedef enum TCA_SINGLE_EVACTA_enum +{ + TCA_SINGLE_EVACTA_CNT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACTA_CNT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACTA_CNT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACTA_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACTA_t; + +/* Event Action B select */ +typedef enum TCA_SINGLE_EVACTB_enum +{ + TCA_SINGLE_EVACTB_UPDOWN_gc = (0x03<<5), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ + TCA_SINGLE_EVACTB_RESTART_POSEDGE_gc = (0x04<<5), /* Restart counter at positive edge event */ + TCA_SINGLE_EVACTB_RESTART_ANYEDGE_gc = (0x05<<5), /* Restart counter on any edge event */ + TCA_SINGLE_EVACTB_RESTART_HIGHLVL_gc = (0x06<<5), /* Restart counter while event line is 1. */ +} TCA_SINGLE_EVACTB_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* Command Enable select */ +typedef enum TCA_SPLIT_CMDEN_enum +{ + TCA_SPLIT_CMDEN_NONE_gc = (0x00<<0), /* None */ + TCA_SPLIT_CMDEN_BOTH_gc = (0x03<<0), /* Both low byte and high byte counter */ +} TCA_SPLIT_CMDEN_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_DIV1_gc = (0x00<<1), /* CLK_PEP */ + TCB_CLKSEL_DIV2_gc = (0x01<<1), /* CLK_PER/2 */ + TCB_CLKSEL_TCA0_gc = (0x02<<1), /* Use CLK_TCA from TCA0 */ + TCB_CLKSEL_TCA1_gc = (0x03<<1), /* Use CLK_TCA from TCA1 */ + TCB_CLKSEL_EVENT_gc = (0x07<<1), /* Count on event edge */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_OSCHF_gc = (0x00<<5), /* Internal High-Frequency Oscillator */ + TCD_CLKSEL_PLL_gc = (0x01<<5), /* PLL */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External Clock */ + TCD_CLKSEL_CLKPER_gc = (0x03<<5), /* Peripheral Clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Synchronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selected clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selected clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selected clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selected clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t DUALCTRL; /* Dual Control */ + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baud Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_1[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Input Voltage Transition Level select */ +typedef enum TWI_INPUTLVL_enum +{ + TWI_INPUTLVL_I2C_gc = (0x00<<6), /* I2C input voltage transition level */ + TWI_INPUTLVL_SMBUS_gc = (0x01<<6), /* SMBus 3.0 input voltage transition level */ +} TWI_INPUTLVL_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t CTRLD; /* Control D */ + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_1[1]; +} USART_t; + +/* Auto Baud Window select */ +typedef enum USART_ABW_enum +{ + USART_ABW_WDW0_gc = (0x00<<6), /* 18% tolerance */ + USART_ABW_WDW1_gc = (0x01<<6), /* 15% tolerance */ + USART_ABW_WDW2_gc = (0x02<<6), /* 21% tolerance */ + USART_ABW_WDW3_gc = (0x03<<6), /* 25% tolerance */ +} USART_ABW_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t ADC0REF; /* ADC0 Reference */ + register8_t reserved_1[1]; + register8_t DAC0REF; /* DAC0 Reference */ + register8_t reserved_2[1]; + register8_t ACREF; /* AC Reference */ +} VREF_t; + +/* Reference select select */ +typedef enum VREF_REFSEL_enum +{ + VREF_REFSEL_1V024_gc = (0x00<<0), /* Internal 1.024V reference */ + VREF_REFSEL_2V048_gc = (0x01<<0), /* Internal 2.048V reference */ + VREF_REFSEL_4V096_gc = (0x02<<0), /* Internal 4.096V reference */ + VREF_REFSEL_2V500_gc = (0x03<<0), /* Internal 2.500V reference */ + VREF_REFSEL_VDD_gc = (0x05<<0), /* VDD as reference */ + VREF_REFSEL_VREFA_gc = (0x06<<0), /* External referance on VREFA pin */ +} VREF_REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; + +/* +-------------------------------------------------------------------------- +ZCD - Zero Cross Detect +-------------------------------------------------------------------------- +*/ + +/* Zero Cross Detect */ +typedef struct ZCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ + register8_t reserved_2[4]; +} ZCD_t; + +/* Interrupt Mode select */ +typedef enum ZCD_INTMODE_enum +{ + ZCD_INTMODE_NONE_gc = (0x00<<0), /* No interrupt */ + ZCD_INTMODE_RISING_gc = (0x01<<0), /* Interrupt on rising input signal */ + ZCD_INTMODE_FALLING_gc = (0x02<<0), /* Interrupt on falling input signal */ + ZCD_INTMODE_BOTH_gc = (0x03<<0), /* Interrupt on both rising and falling input signal */ +} ZCD_INTMODE_t; + +/* ZCD State select */ +typedef enum ZCD_STATE_enum +{ + ZCD_STATE_LOW_gc = (0x00<<4), /* Output is 0 */ + ZCD_STATE_HIGH_gc = (0x01<<4), /* Output is 1 */ +} ZCD_STATE_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define VPORTD (*(VPORT_t *) 0x000C) /* Virtual Ports */ +#define VPORTE (*(VPORT_t *) 0x0010) /* Virtual Ports */ +#define VPORTF (*(VPORT_t *) 0x0014) /* Virtual Ports */ +#define VPORTG (*(VPORT_t *) 0x0018) /* Virtual Ports */ +#define GPR (*(GPR_t *) 0x001C) /* General Purpose Registers */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define EVSYS (*(EVSYS_t *) 0x0200) /* Event System */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0460) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0480) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x04A0) /* I/O Ports */ +#define PORTG (*(PORT_t *) 0x04C0) /* I/O Ports */ +#define PORTMUX (*(PORTMUX_t *) 0x05E0) /* Port Multiplexer */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define AC1 (*(AC_t *) 0x0688) /* Analog Comparator */ +#define AC2 (*(AC_t *) 0x0690) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x06A0) /* Digital to Analog Converter */ +#define ZCD0 (*(ZCD_t *) 0x06C0) /* Zero Cross Detect */ +#define ZCD1 (*(ZCD_t *) 0x06C8) /* Zero Cross Detect */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1 (*(USART_t *) 0x0820) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2 (*(USART_t *) 0x0840) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART3 (*(USART_t *) 0x0860) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART4 (*(USART_t *) 0x0880) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0900) /* Two-Wire Interface */ +#define TWI1 (*(TWI_t *) 0x0920) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0940) /* Serial Peripheral Interface */ +#define SPI1 (*(SPI_t *) 0x0960) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCA1 (*(TCA_t *) 0x0A40) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0B00) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0B10) /* 16-bit Timer Type B */ +#define TCB2 (*(TCB_t *) 0x0B20) /* 16-bit Timer Type B */ +#define TCB3 (*(TCB_t *) 0x0B30) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0B80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define LOCK (*(LOCK_t *) 0x1040) /* Lockbits */ +#define FUSE (*(FUSE_t *) 0x1050) /* Fuses */ +#define USERROW (*(USERROW_t *) 0x1080) /* User Row */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* VPORT (VPORTD) - Virtual Ports */ +#define VPORTD_DIR _SFR_MEM8(0x000C) +#define VPORTD_OUT _SFR_MEM8(0x000D) +#define VPORTD_IN _SFR_MEM8(0x000E) +#define VPORTD_INTFLAGS _SFR_MEM8(0x000F) + + +/* VPORT (VPORTE) - Virtual Ports */ +#define VPORTE_DIR _SFR_MEM8(0x0010) +#define VPORTE_OUT _SFR_MEM8(0x0011) +#define VPORTE_IN _SFR_MEM8(0x0012) +#define VPORTE_INTFLAGS _SFR_MEM8(0x0013) + + +/* VPORT (VPORTF) - Virtual Ports */ +#define VPORTF_DIR _SFR_MEM8(0x0014) +#define VPORTF_OUT _SFR_MEM8(0x0015) +#define VPORTF_IN _SFR_MEM8(0x0016) +#define VPORTF_INTFLAGS _SFR_MEM8(0x0017) + + +/* VPORT (VPORTG) - Virtual Ports */ +#define VPORTG_DIR _SFR_MEM8(0x0018) +#define VPORTG_OUT _SFR_MEM8(0x0019) +#define VPORTG_IN _SFR_MEM8(0x001A) +#define VPORTG_INTFLAGS _SFR_MEM8(0x001B) + + +/* GPR - General Purpose Registers */ +#define GPR_GPR0 _SFR_MEM8(0x001C) +#define GPR_GPR1 _SFR_MEM8(0x001D) +#define GPR_GPR2 _SFR_MEM8(0x001E) +#define GPR_GPR3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) +#define SLPCTRL_VREGCTRL _SFR_MEM8(0x0051) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSCHFCTRLA _SFR_MEM8(0x0068) +#define CLKCTRL_OSCHFTUNE _SFR_MEM8(0x0069) +#define CLKCTRL_PLLCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_ADC0REF _SFR_MEM8(0x00A0) +#define VREF_DAC0REF _SFR_MEM8(0x00A2) +#define VREF_ACREF _SFR_MEM8(0x00A4) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CALIB _SFR_MEM8(0x0146) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_SEQCTRL1 _SFR_MEM8(0x01C2) +#define CCL_SEQCTRL2 _SFR_MEM8(0x01C3) +#define CCL_INTCTRL0 _SFR_MEM8(0x01C5) +#define CCL_INTCTRL1 _SFR_MEM8(0x01C6) +#define CCL_INTFLAGS _SFR_MEM8(0x01C7) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C8) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C9) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01CA) +#define CCL_TRUTH0 _SFR_MEM8(0x01CB) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01CC) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CD) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CE) +#define CCL_TRUTH1 _SFR_MEM8(0x01CF) +#define CCL_LUT2CTRLA _SFR_MEM8(0x01D0) +#define CCL_LUT2CTRLB _SFR_MEM8(0x01D1) +#define CCL_LUT2CTRLC _SFR_MEM8(0x01D2) +#define CCL_TRUTH2 _SFR_MEM8(0x01D3) +#define CCL_LUT3CTRLA _SFR_MEM8(0x01D4) +#define CCL_LUT3CTRLB _SFR_MEM8(0x01D5) +#define CCL_LUT3CTRLC _SFR_MEM8(0x01D6) +#define CCL_TRUTH3 _SFR_MEM8(0x01D7) +#define CCL_LUT4CTRLA _SFR_MEM8(0x01D8) +#define CCL_LUT4CTRLB _SFR_MEM8(0x01D9) +#define CCL_LUT4CTRLC _SFR_MEM8(0x01DA) +#define CCL_TRUTH4 _SFR_MEM8(0x01DB) +#define CCL_LUT5CTRLA _SFR_MEM8(0x01DC) +#define CCL_LUT5CTRLB _SFR_MEM8(0x01DD) +#define CCL_LUT5CTRLC _SFR_MEM8(0x01DE) +#define CCL_TRUTH5 _SFR_MEM8(0x01DF) + + +/* EVSYS - Event System */ +#define EVSYS_SWEVENTA _SFR_MEM8(0x0200) +#define EVSYS_SWEVENTB _SFR_MEM8(0x0201) +#define EVSYS_CHANNEL0 _SFR_MEM8(0x0210) +#define EVSYS_CHANNEL1 _SFR_MEM8(0x0211) +#define EVSYS_CHANNEL2 _SFR_MEM8(0x0212) +#define EVSYS_CHANNEL3 _SFR_MEM8(0x0213) +#define EVSYS_CHANNEL4 _SFR_MEM8(0x0214) +#define EVSYS_CHANNEL5 _SFR_MEM8(0x0215) +#define EVSYS_CHANNEL6 _SFR_MEM8(0x0216) +#define EVSYS_CHANNEL7 _SFR_MEM8(0x0217) +#define EVSYS_CHANNEL8 _SFR_MEM8(0x0218) +#define EVSYS_CHANNEL9 _SFR_MEM8(0x0219) +#define EVSYS_USERCCLLUT0A _SFR_MEM8(0x0220) +#define EVSYS_USERCCLLUT0B _SFR_MEM8(0x0221) +#define EVSYS_USERCCLLUT1A _SFR_MEM8(0x0222) +#define EVSYS_USERCCLLUT1B _SFR_MEM8(0x0223) +#define EVSYS_USERCCLLUT2A _SFR_MEM8(0x0224) +#define EVSYS_USERCCLLUT2B _SFR_MEM8(0x0225) +#define EVSYS_USERCCLLUT3A _SFR_MEM8(0x0226) +#define EVSYS_USERCCLLUT3B _SFR_MEM8(0x0227) +#define EVSYS_USERCCLLUT4A _SFR_MEM8(0x0228) +#define EVSYS_USERCCLLUT4B _SFR_MEM8(0x0229) +#define EVSYS_USERCCLLUT5A _SFR_MEM8(0x022A) +#define EVSYS_USERCCLLUT5B _SFR_MEM8(0x022B) +#define EVSYS_USERADC0START _SFR_MEM8(0x022C) +#define EVSYS_USERPTCSTART _SFR_MEM8(0x022D) +#define EVSYS_USEREVSYSEVOUTA _SFR_MEM8(0x022E) +#define EVSYS_USEREVSYSEVOUTB _SFR_MEM8(0x022F) +#define EVSYS_USEREVSYSEVOUTC _SFR_MEM8(0x0230) +#define EVSYS_USEREVSYSEVOUTD _SFR_MEM8(0x0231) +#define EVSYS_USEREVSYSEVOUTE _SFR_MEM8(0x0232) +#define EVSYS_USEREVSYSEVOUTF _SFR_MEM8(0x0233) +#define EVSYS_USEREVSYSEVOUTG _SFR_MEM8(0x0234) +#define EVSYS_USERUSART0IRDA _SFR_MEM8(0x0235) +#define EVSYS_USERUSART1IRDA _SFR_MEM8(0x0236) +#define EVSYS_USERUSART2IRDA _SFR_MEM8(0x0237) +#define EVSYS_USERUSART3IRDA _SFR_MEM8(0x0238) +#define EVSYS_USERUSART4IRDA _SFR_MEM8(0x0239) +#define EVSYS_USERUSART5IRDA _SFR_MEM8(0x023A) +#define EVSYS_USERTCA0CNTA _SFR_MEM8(0x023B) +#define EVSYS_USERTCA0CNTB _SFR_MEM8(0x023C) +#define EVSYS_USERTCA1CNTA _SFR_MEM8(0x023D) +#define EVSYS_USERTCA1CNTB _SFR_MEM8(0x023E) +#define EVSYS_USERTCB0CAPT _SFR_MEM8(0x023F) +#define EVSYS_USERTCB0COUNT _SFR_MEM8(0x0240) +#define EVSYS_USERTCB1CAPT _SFR_MEM8(0x0241) +#define EVSYS_USERTCB1COUNT _SFR_MEM8(0x0242) +#define EVSYS_USERTCB2CAPT _SFR_MEM8(0x0243) +#define EVSYS_USERTCB2COUNT _SFR_MEM8(0x0244) +#define EVSYS_USERTCB3CAPT _SFR_MEM8(0x0245) +#define EVSYS_USERTCB3COUNT _SFR_MEM8(0x0246) +#define EVSYS_USERTCB4CAPT _SFR_MEM8(0x0247) +#define EVSYS_USERTCB4COUNT _SFR_MEM8(0x0248) +#define EVSYS_USERTCD0INPUTA _SFR_MEM8(0x0249) +#define EVSYS_USERTCD0INPUTB _SFR_MEM8(0x024A) +#define EVSYS_USEROSCTEST _SFR_MEM8(0x024B) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PORTCTRL _SFR_MEM8(0x040A) +#define PORTA_PINCONFIG _SFR_MEM8(0x040B) +#define PORTA_PINCTRLUPD _SFR_MEM8(0x040C) +#define PORTA_PINCTRLSET _SFR_MEM8(0x040D) +#define PORTA_PINCTRLCLR _SFR_MEM8(0x040E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PORTCTRL _SFR_MEM8(0x042A) +#define PORTB_PINCONFIG _SFR_MEM8(0x042B) +#define PORTB_PINCTRLUPD _SFR_MEM8(0x042C) +#define PORTB_PINCTRLSET _SFR_MEM8(0x042D) +#define PORTB_PINCTRLCLR _SFR_MEM8(0x042E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PORTCTRL _SFR_MEM8(0x044A) +#define PORTC_PINCONFIG _SFR_MEM8(0x044B) +#define PORTC_PINCTRLUPD _SFR_MEM8(0x044C) +#define PORTC_PINCTRLSET _SFR_MEM8(0x044D) +#define PORTC_PINCTRLCLR _SFR_MEM8(0x044E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* PORT (PORTD) - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0460) +#define PORTD_DIRSET _SFR_MEM8(0x0461) +#define PORTD_DIRCLR _SFR_MEM8(0x0462) +#define PORTD_DIRTGL _SFR_MEM8(0x0463) +#define PORTD_OUT _SFR_MEM8(0x0464) +#define PORTD_OUTSET _SFR_MEM8(0x0465) +#define PORTD_OUTCLR _SFR_MEM8(0x0466) +#define PORTD_OUTTGL _SFR_MEM8(0x0467) +#define PORTD_IN _SFR_MEM8(0x0468) +#define PORTD_INTFLAGS _SFR_MEM8(0x0469) +#define PORTD_PORTCTRL _SFR_MEM8(0x046A) +#define PORTD_PINCONFIG _SFR_MEM8(0x046B) +#define PORTD_PINCTRLUPD _SFR_MEM8(0x046C) +#define PORTD_PINCTRLSET _SFR_MEM8(0x046D) +#define PORTD_PINCTRLCLR _SFR_MEM8(0x046E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0470) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0471) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0472) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0473) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0474) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0475) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0476) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0477) + + +/* PORT (PORTE) - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0480) +#define PORTE_DIRSET _SFR_MEM8(0x0481) +#define PORTE_DIRCLR _SFR_MEM8(0x0482) +#define PORTE_DIRTGL _SFR_MEM8(0x0483) +#define PORTE_OUT _SFR_MEM8(0x0484) +#define PORTE_OUTSET _SFR_MEM8(0x0485) +#define PORTE_OUTCLR _SFR_MEM8(0x0486) +#define PORTE_OUTTGL _SFR_MEM8(0x0487) +#define PORTE_IN _SFR_MEM8(0x0488) +#define PORTE_INTFLAGS _SFR_MEM8(0x0489) +#define PORTE_PORTCTRL _SFR_MEM8(0x048A) +#define PORTE_PINCONFIG _SFR_MEM8(0x048B) +#define PORTE_PINCTRLUPD _SFR_MEM8(0x048C) +#define PORTE_PINCTRLSET _SFR_MEM8(0x048D) +#define PORTE_PINCTRLCLR _SFR_MEM8(0x048E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0490) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0491) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0492) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0493) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0494) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0495) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0496) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0497) + + +/* PORT (PORTF) - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x04A0) +#define PORTF_DIRSET _SFR_MEM8(0x04A1) +#define PORTF_DIRCLR _SFR_MEM8(0x04A2) +#define PORTF_DIRTGL _SFR_MEM8(0x04A3) +#define PORTF_OUT _SFR_MEM8(0x04A4) +#define PORTF_OUTSET _SFR_MEM8(0x04A5) +#define PORTF_OUTCLR _SFR_MEM8(0x04A6) +#define PORTF_OUTTGL _SFR_MEM8(0x04A7) +#define PORTF_IN _SFR_MEM8(0x04A8) +#define PORTF_INTFLAGS _SFR_MEM8(0x04A9) +#define PORTF_PORTCTRL _SFR_MEM8(0x04AA) +#define PORTF_PINCONFIG _SFR_MEM8(0x04AB) +#define PORTF_PINCTRLUPD _SFR_MEM8(0x04AC) +#define PORTF_PINCTRLSET _SFR_MEM8(0x04AD) +#define PORTF_PINCTRLCLR _SFR_MEM8(0x04AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x04B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x04B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x04B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x04B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x04B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x04B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x04B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x04B7) + + +/* PORT (PORTG) - I/O Ports */ +#define PORTG_DIR _SFR_MEM8(0x04C0) +#define PORTG_DIRSET _SFR_MEM8(0x04C1) +#define PORTG_DIRCLR _SFR_MEM8(0x04C2) +#define PORTG_DIRTGL _SFR_MEM8(0x04C3) +#define PORTG_OUT _SFR_MEM8(0x04C4) +#define PORTG_OUTSET _SFR_MEM8(0x04C5) +#define PORTG_OUTCLR _SFR_MEM8(0x04C6) +#define PORTG_OUTTGL _SFR_MEM8(0x04C7) +#define PORTG_IN _SFR_MEM8(0x04C8) +#define PORTG_INTFLAGS _SFR_MEM8(0x04C9) +#define PORTG_PORTCTRL _SFR_MEM8(0x04CA) +#define PORTG_PINCONFIG _SFR_MEM8(0x04CB) +#define PORTG_PINCTRLUPD _SFR_MEM8(0x04CC) +#define PORTG_PINCTRLSET _SFR_MEM8(0x04CD) +#define PORTG_PINCTRLCLR _SFR_MEM8(0x04CE) +#define PORTG_PIN0CTRL _SFR_MEM8(0x04D0) +#define PORTG_PIN1CTRL _SFR_MEM8(0x04D1) +#define PORTG_PIN2CTRL _SFR_MEM8(0x04D2) +#define PORTG_PIN3CTRL _SFR_MEM8(0x04D3) +#define PORTG_PIN4CTRL _SFR_MEM8(0x04D4) +#define PORTG_PIN5CTRL _SFR_MEM8(0x04D5) +#define PORTG_PIN6CTRL _SFR_MEM8(0x04D6) +#define PORTG_PIN7CTRL _SFR_MEM8(0x04D7) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_EVSYSROUTEA _SFR_MEM8(0x05E0) +#define PORTMUX_CCLROUTEA _SFR_MEM8(0x05E1) +#define PORTMUX_USARTROUTEA _SFR_MEM8(0x05E2) +#define PORTMUX_USARTROUTEB _SFR_MEM8(0x05E3) +#define PORTMUX_SPIROUTEA _SFR_MEM8(0x05E4) +#define PORTMUX_TWIROUTEA _SFR_MEM8(0x05E5) +#define PORTMUX_TCAROUTEA _SFR_MEM8(0x05E6) +#define PORTMUX_TCBROUTEA _SFR_MEM8(0x05E7) +#define PORTMUX_TCDROUTEA _SFR_MEM8(0x05E8) +#define PORTMUX_ACROUTEA _SFR_MEM8(0x05E9) +#define PORTMUX_ZCDROUTEA _SFR_MEM8(0x05EA) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0608) +#define ADC0_MUXNEG _SFR_MEM8(0x0609) +#define ADC0_COMMAND _SFR_MEM8(0x060A) +#define ADC0_EVCTRL _SFR_MEM8(0x060B) +#define ADC0_INTCTRL _SFR_MEM8(0x060C) +#define ADC0_INTFLAGS _SFR_MEM8(0x060D) +#define ADC0_DBGCTRL _SFR_MEM8(0x060E) +#define ADC0_TEMP _SFR_MEM8(0x060F) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_CTRLB _SFR_MEM8(0x0681) +#define AC0_MUXCTRL _SFR_MEM8(0x0682) +#define AC0_DACREF _SFR_MEM8(0x0685) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* AC (AC1) - Analog Comparator */ +#define AC1_CTRLA _SFR_MEM8(0x0688) +#define AC1_CTRLB _SFR_MEM8(0x0689) +#define AC1_MUXCTRL _SFR_MEM8(0x068A) +#define AC1_DACREF _SFR_MEM8(0x068D) +#define AC1_INTCTRL _SFR_MEM8(0x068E) +#define AC1_STATUS _SFR_MEM8(0x068F) + + +/* AC (AC2) - Analog Comparator */ +#define AC2_CTRLA _SFR_MEM8(0x0690) +#define AC2_CTRLB _SFR_MEM8(0x0691) +#define AC2_MUXCTRL _SFR_MEM8(0x0692) +#define AC2_DACREF _SFR_MEM8(0x0695) +#define AC2_INTCTRL _SFR_MEM8(0x0696) +#define AC2_STATUS _SFR_MEM8(0x0697) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x06A0) +#define DAC0_DATA _SFR_MEM16(0x06A2) +#define DAC0_DATAL _SFR_MEM8(0x06A2) +#define DAC0_DATAH _SFR_MEM8(0x06A3) + + +/* ZCD (ZCD0) - Zero Cross Detect */ +#define ZCD0_CTRLA _SFR_MEM8(0x06C0) +#define ZCD0_INTCTRL _SFR_MEM8(0x06C2) +#define ZCD0_STATUS _SFR_MEM8(0x06C3) + + +/* ZCD (ZCD1) - Zero Cross Detect */ +#define ZCD1_CTRLA _SFR_MEM8(0x06C8) +#define ZCD1_INTCTRL _SFR_MEM8(0x06CA) +#define ZCD1_STATUS _SFR_MEM8(0x06CB) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_CTRLD _SFR_MEM8(0x080A) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* USART (USART1) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1_RXDATAL _SFR_MEM8(0x0820) +#define USART1_RXDATAH _SFR_MEM8(0x0821) +#define USART1_TXDATAL _SFR_MEM8(0x0822) +#define USART1_TXDATAH _SFR_MEM8(0x0823) +#define USART1_STATUS _SFR_MEM8(0x0824) +#define USART1_CTRLA _SFR_MEM8(0x0825) +#define USART1_CTRLB _SFR_MEM8(0x0826) +#define USART1_CTRLC _SFR_MEM8(0x0827) +#define USART1_BAUD _SFR_MEM16(0x0828) +#define USART1_BAUDL _SFR_MEM8(0x0828) +#define USART1_BAUDH _SFR_MEM8(0x0829) +#define USART1_CTRLD _SFR_MEM8(0x082A) +#define USART1_DBGCTRL _SFR_MEM8(0x082B) +#define USART1_EVCTRL _SFR_MEM8(0x082C) +#define USART1_TXPLCTRL _SFR_MEM8(0x082D) +#define USART1_RXPLCTRL _SFR_MEM8(0x082E) + + +/* USART (USART2) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2_RXDATAL _SFR_MEM8(0x0840) +#define USART2_RXDATAH _SFR_MEM8(0x0841) +#define USART2_TXDATAL _SFR_MEM8(0x0842) +#define USART2_TXDATAH _SFR_MEM8(0x0843) +#define USART2_STATUS _SFR_MEM8(0x0844) +#define USART2_CTRLA _SFR_MEM8(0x0845) +#define USART2_CTRLB _SFR_MEM8(0x0846) +#define USART2_CTRLC _SFR_MEM8(0x0847) +#define USART2_BAUD _SFR_MEM16(0x0848) +#define USART2_BAUDL _SFR_MEM8(0x0848) +#define USART2_BAUDH _SFR_MEM8(0x0849) +#define USART2_CTRLD _SFR_MEM8(0x084A) +#define USART2_DBGCTRL _SFR_MEM8(0x084B) +#define USART2_EVCTRL _SFR_MEM8(0x084C) +#define USART2_TXPLCTRL _SFR_MEM8(0x084D) +#define USART2_RXPLCTRL _SFR_MEM8(0x084E) + + +/* USART (USART3) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART3_RXDATAL _SFR_MEM8(0x0860) +#define USART3_RXDATAH _SFR_MEM8(0x0861) +#define USART3_TXDATAL _SFR_MEM8(0x0862) +#define USART3_TXDATAH _SFR_MEM8(0x0863) +#define USART3_STATUS _SFR_MEM8(0x0864) +#define USART3_CTRLA _SFR_MEM8(0x0865) +#define USART3_CTRLB _SFR_MEM8(0x0866) +#define USART3_CTRLC _SFR_MEM8(0x0867) +#define USART3_BAUD _SFR_MEM16(0x0868) +#define USART3_BAUDL _SFR_MEM8(0x0868) +#define USART3_BAUDH _SFR_MEM8(0x0869) +#define USART3_CTRLD _SFR_MEM8(0x086A) +#define USART3_DBGCTRL _SFR_MEM8(0x086B) +#define USART3_EVCTRL _SFR_MEM8(0x086C) +#define USART3_TXPLCTRL _SFR_MEM8(0x086D) +#define USART3_RXPLCTRL _SFR_MEM8(0x086E) + + +/* USART (USART4) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART4_RXDATAL _SFR_MEM8(0x0880) +#define USART4_RXDATAH _SFR_MEM8(0x0881) +#define USART4_TXDATAL _SFR_MEM8(0x0882) +#define USART4_TXDATAH _SFR_MEM8(0x0883) +#define USART4_STATUS _SFR_MEM8(0x0884) +#define USART4_CTRLA _SFR_MEM8(0x0885) +#define USART4_CTRLB _SFR_MEM8(0x0886) +#define USART4_CTRLC _SFR_MEM8(0x0887) +#define USART4_BAUD _SFR_MEM16(0x0888) +#define USART4_BAUDL _SFR_MEM8(0x0888) +#define USART4_BAUDH _SFR_MEM8(0x0889) +#define USART4_CTRLD _SFR_MEM8(0x088A) +#define USART4_DBGCTRL _SFR_MEM8(0x088B) +#define USART4_EVCTRL _SFR_MEM8(0x088C) +#define USART4_TXPLCTRL _SFR_MEM8(0x088D) +#define USART4_RXPLCTRL _SFR_MEM8(0x088E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0900) +#define TWI0_DUALCTRL _SFR_MEM8(0x0901) +#define TWI0_DBGCTRL _SFR_MEM8(0x0902) +#define TWI0_MCTRLA _SFR_MEM8(0x0903) +#define TWI0_MCTRLB _SFR_MEM8(0x0904) +#define TWI0_MSTATUS _SFR_MEM8(0x0905) +#define TWI0_MBAUD _SFR_MEM8(0x0906) +#define TWI0_MADDR _SFR_MEM8(0x0907) +#define TWI0_MDATA _SFR_MEM8(0x0908) +#define TWI0_SCTRLA _SFR_MEM8(0x0909) +#define TWI0_SCTRLB _SFR_MEM8(0x090A) +#define TWI0_SSTATUS _SFR_MEM8(0x090B) +#define TWI0_SADDR _SFR_MEM8(0x090C) +#define TWI0_SDATA _SFR_MEM8(0x090D) +#define TWI0_SADDRMASK _SFR_MEM8(0x090E) + + +/* TWI (TWI1) - Two-Wire Interface */ +#define TWI1_CTRLA _SFR_MEM8(0x0920) +#define TWI1_DUALCTRL _SFR_MEM8(0x0921) +#define TWI1_DBGCTRL _SFR_MEM8(0x0922) +#define TWI1_MCTRLA _SFR_MEM8(0x0923) +#define TWI1_MCTRLB _SFR_MEM8(0x0924) +#define TWI1_MSTATUS _SFR_MEM8(0x0925) +#define TWI1_MBAUD _SFR_MEM8(0x0926) +#define TWI1_MADDR _SFR_MEM8(0x0927) +#define TWI1_MDATA _SFR_MEM8(0x0928) +#define TWI1_SCTRLA _SFR_MEM8(0x0929) +#define TWI1_SCTRLB _SFR_MEM8(0x092A) +#define TWI1_SSTATUS _SFR_MEM8(0x092B) +#define TWI1_SADDR _SFR_MEM8(0x092C) +#define TWI1_SDATA _SFR_MEM8(0x092D) +#define TWI1_SADDRMASK _SFR_MEM8(0x092E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0940) +#define SPI0_CTRLB _SFR_MEM8(0x0941) +#define SPI0_INTCTRL _SFR_MEM8(0x0942) +#define SPI0_INTFLAGS _SFR_MEM8(0x0943) +#define SPI0_DATA _SFR_MEM8(0x0944) + + +/* SPI (SPI1) - Serial Peripheral Interface */ +#define SPI1_CTRLA _SFR_MEM8(0x0960) +#define SPI1_CTRLB _SFR_MEM8(0x0961) +#define SPI1_INTCTRL _SFR_MEM8(0x0962) +#define SPI1_INTFLAGS _SFR_MEM8(0x0963) +#define SPI1_DATA _SFR_MEM8(0x0964) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCA (TCA1) - 16-bit Timer/Counter Type A */ +#define TCA1_SINGLE_CTRLA _SFR_MEM8(0x0A40) +#define TCA1_SINGLE_CTRLB _SFR_MEM8(0x0A41) +#define TCA1_SINGLE_CTRLC _SFR_MEM8(0x0A42) +#define TCA1_SINGLE_CTRLD _SFR_MEM8(0x0A43) +#define TCA1_SINGLE_CTRLECLR _SFR_MEM8(0x0A44) +#define TCA1_SINGLE_CTRLESET _SFR_MEM8(0x0A45) +#define TCA1_SINGLE_CTRLFCLR _SFR_MEM8(0x0A46) +#define TCA1_SINGLE_CTRLFSET _SFR_MEM8(0x0A47) +#define TCA1_SINGLE_EVCTRL _SFR_MEM8(0x0A49) +#define TCA1_SINGLE_INTCTRL _SFR_MEM8(0x0A4A) +#define TCA1_SINGLE_INTFLAGS _SFR_MEM8(0x0A4B) +#define TCA1_SINGLE_DBGCTRL _SFR_MEM8(0x0A4E) +#define TCA1_SINGLE_TEMP _SFR_MEM8(0x0A4F) +#define TCA1_SINGLE_CNT _SFR_MEM16(0x0A60) +#define TCA1_SINGLE_PER _SFR_MEM16(0x0A66) +#define TCA1_SINGLE_CMP0 _SFR_MEM16(0x0A68) +#define TCA1_SINGLE_CMP1 _SFR_MEM16(0x0A6A) +#define TCA1_SINGLE_CMP2 _SFR_MEM16(0x0A6C) +#define TCA1_SINGLE_PERBUF _SFR_MEM16(0x0A76) +#define TCA1_SINGLE_CMP0BUF _SFR_MEM16(0x0A78) +#define TCA1_SINGLE_CMP1BUF _SFR_MEM16(0x0A7A) +#define TCA1_SINGLE_CMP2BUF _SFR_MEM16(0x0A7C) + + +#define TCA1_SPLIT_CTRLA _SFR_MEM8(0x0A40) +#define TCA1_SPLIT_CTRLB _SFR_MEM8(0x0A41) +#define TCA1_SPLIT_CTRLC _SFR_MEM8(0x0A42) +#define TCA1_SPLIT_CTRLD _SFR_MEM8(0x0A43) +#define TCA1_SPLIT_CTRLECLR _SFR_MEM8(0x0A44) +#define TCA1_SPLIT_CTRLESET _SFR_MEM8(0x0A45) +#define TCA1_SPLIT_INTCTRL _SFR_MEM8(0x0A4A) +#define TCA1_SPLIT_INTFLAGS _SFR_MEM8(0x0A4B) +#define TCA1_SPLIT_DBGCTRL _SFR_MEM8(0x0A4E) +#define TCA1_SPLIT_LCNT _SFR_MEM8(0x0A60) +#define TCA1_SPLIT_HCNT _SFR_MEM8(0x0A61) +#define TCA1_SPLIT_LPER _SFR_MEM8(0x0A66) +#define TCA1_SPLIT_HPER _SFR_MEM8(0x0A67) +#define TCA1_SPLIT_LCMP0 _SFR_MEM8(0x0A68) +#define TCA1_SPLIT_HCMP0 _SFR_MEM8(0x0A69) +#define TCA1_SPLIT_LCMP1 _SFR_MEM8(0x0A6A) +#define TCA1_SPLIT_HCMP1 _SFR_MEM8(0x0A6B) +#define TCA1_SPLIT_LCMP2 _SFR_MEM8(0x0A6C) +#define TCA1_SPLIT_HCMP2 _SFR_MEM8(0x0A6D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0B00) +#define TCB0_CTRLB _SFR_MEM8(0x0B01) +#define TCB0_EVCTRL _SFR_MEM8(0x0B04) +#define TCB0_INTCTRL _SFR_MEM8(0x0B05) +#define TCB0_INTFLAGS _SFR_MEM8(0x0B06) +#define TCB0_STATUS _SFR_MEM8(0x0B07) +#define TCB0_DBGCTRL _SFR_MEM8(0x0B08) +#define TCB0_TEMP _SFR_MEM8(0x0B09) +#define TCB0_CNT _SFR_MEM16(0x0B0A) +#define TCB0_CNTL _SFR_MEM8(0x0B0A) +#define TCB0_CNTH _SFR_MEM8(0x0B0B) +#define TCB0_CCMP _SFR_MEM16(0x0B0C) +#define TCB0_CCMPL _SFR_MEM8(0x0B0C) +#define TCB0_CCMPH _SFR_MEM8(0x0B0D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0B10) +#define TCB1_CTRLB _SFR_MEM8(0x0B11) +#define TCB1_EVCTRL _SFR_MEM8(0x0B14) +#define TCB1_INTCTRL _SFR_MEM8(0x0B15) +#define TCB1_INTFLAGS _SFR_MEM8(0x0B16) +#define TCB1_STATUS _SFR_MEM8(0x0B17) +#define TCB1_DBGCTRL _SFR_MEM8(0x0B18) +#define TCB1_TEMP _SFR_MEM8(0x0B19) +#define TCB1_CNT _SFR_MEM16(0x0B1A) +#define TCB1_CNTL _SFR_MEM8(0x0B1A) +#define TCB1_CNTH _SFR_MEM8(0x0B1B) +#define TCB1_CCMP _SFR_MEM16(0x0B1C) +#define TCB1_CCMPL _SFR_MEM8(0x0B1C) +#define TCB1_CCMPH _SFR_MEM8(0x0B1D) + + +/* TCB (TCB2) - 16-bit Timer Type B */ +#define TCB2_CTRLA _SFR_MEM8(0x0B20) +#define TCB2_CTRLB _SFR_MEM8(0x0B21) +#define TCB2_EVCTRL _SFR_MEM8(0x0B24) +#define TCB2_INTCTRL _SFR_MEM8(0x0B25) +#define TCB2_INTFLAGS _SFR_MEM8(0x0B26) +#define TCB2_STATUS _SFR_MEM8(0x0B27) +#define TCB2_DBGCTRL _SFR_MEM8(0x0B28) +#define TCB2_TEMP _SFR_MEM8(0x0B29) +#define TCB2_CNT _SFR_MEM16(0x0B2A) +#define TCB2_CNTL _SFR_MEM8(0x0B2A) +#define TCB2_CNTH _SFR_MEM8(0x0B2B) +#define TCB2_CCMP _SFR_MEM16(0x0B2C) +#define TCB2_CCMPL _SFR_MEM8(0x0B2C) +#define TCB2_CCMPH _SFR_MEM8(0x0B2D) + + +/* TCB (TCB3) - 16-bit Timer Type B */ +#define TCB3_CTRLA _SFR_MEM8(0x0B30) +#define TCB3_CTRLB _SFR_MEM8(0x0B31) +#define TCB3_EVCTRL _SFR_MEM8(0x0B34) +#define TCB3_INTCTRL _SFR_MEM8(0x0B35) +#define TCB3_INTFLAGS _SFR_MEM8(0x0B36) +#define TCB3_STATUS _SFR_MEM8(0x0B37) +#define TCB3_DBGCTRL _SFR_MEM8(0x0B38) +#define TCB3_TEMP _SFR_MEM8(0x0B39) +#define TCB3_CNT _SFR_MEM16(0x0B3A) +#define TCB3_CNTL _SFR_MEM8(0x0B3A) +#define TCB3_CNTH _SFR_MEM8(0x0B3B) +#define TCB3_CCMP _SFR_MEM16(0x0B3C) +#define TCB3_CCMPL _SFR_MEM8(0x0B3C) +#define TCB3_CCMPH _SFR_MEM8(0x0B3D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0B80) +#define TCD0_CTRLB _SFR_MEM8(0x0B81) +#define TCD0_CTRLC _SFR_MEM8(0x0B82) +#define TCD0_CTRLD _SFR_MEM8(0x0B83) +#define TCD0_CTRLE _SFR_MEM8(0x0B84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0B88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0B89) +#define TCD0_INTCTRL _SFR_MEM8(0x0B8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0B8D) +#define TCD0_STATUS _SFR_MEM8(0x0B8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0B90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0B91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0B92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0B94) +#define TCD0_DLYVAL _SFR_MEM8(0x0B95) +#define TCD0_DITCTRL _SFR_MEM8(0x0B98) +#define TCD0_DITVAL _SFR_MEM8(0x0B99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0B9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0BA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0BA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0BA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0BA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0BA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0BA5) +#define TCD0_CMPASET _SFR_MEM16(0x0BA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0BA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0BA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0BAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0BAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0BAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0BAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0BAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0BAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0BAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0BAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0BAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_OCDMCTRL _SFR_MEM8(0x0F18) +#define SYSCFG_OCDMSTATUS _SFR_MEM8(0x0F19) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM32(0x1008) +#define NVMCTRL_ADDR0 _SFR_MEM8(0x1008) +#define NVMCTRL_ADDR1 _SFR_MEM8(0x1009) +#define NVMCTRL_ADDR2 _SFR_MEM8(0x100A) +#define NVMCTRL_ADDR3 _SFR_MEM8(0x100B) + + +/* LOCK - Lockbits */ +#define LOCK_KEY _SFR_MEM32(0x1040) +#define LOCK_KEY0 _SFR_MEM8(0x1040) +#define LOCK_KEY1 _SFR_MEM8(0x1041) +#define LOCK_KEY2 _SFR_MEM8(0x1042) +#define LOCK_KEY3 _SFR_MEM8(0x1043) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1050) +#define FUSE_BODCFG _SFR_MEM8(0x1051) +#define FUSE_OSCCFG _SFR_MEM8(0x1052) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1055) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1056) +#define FUSE_CODESIZE _SFR_MEM8(0x1057) +#define FUSE_BOOTSIZE _SFR_MEM8(0x1058) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1080) +#define USERROW_USERROW1 _SFR_MEM8(0x1081) +#define USERROW_USERROW2 _SFR_MEM8(0x1082) +#define USERROW_USERROW3 _SFR_MEM8(0x1083) +#define USERROW_USERROW4 _SFR_MEM8(0x1084) +#define USERROW_USERROW5 _SFR_MEM8(0x1085) +#define USERROW_USERROW6 _SFR_MEM8(0x1086) +#define USERROW_USERROW7 _SFR_MEM8(0x1087) +#define USERROW_USERROW8 _SFR_MEM8(0x1088) +#define USERROW_USERROW9 _SFR_MEM8(0x1089) +#define USERROW_USERROW10 _SFR_MEM8(0x108A) +#define USERROW_USERROW11 _SFR_MEM8(0x108B) +#define USERROW_USERROW12 _SFR_MEM8(0x108C) +#define USERROW_USERROW13 _SFR_MEM8(0x108D) +#define USERROW_USERROW14 _SFR_MEM8(0x108E) +#define USERROW_USERROW15 _SFR_MEM8(0x108F) +#define USERROW_USERROW16 _SFR_MEM8(0x1090) +#define USERROW_USERROW17 _SFR_MEM8(0x1091) +#define USERROW_USERROW18 _SFR_MEM8(0x1092) +#define USERROW_USERROW19 _SFR_MEM8(0x1093) +#define USERROW_USERROW20 _SFR_MEM8(0x1094) +#define USERROW_USERROW21 _SFR_MEM8(0x1095) +#define USERROW_USERROW22 _SFR_MEM8(0x1096) +#define USERROW_USERROW23 _SFR_MEM8(0x1097) +#define USERROW_USERROW24 _SFR_MEM8(0x1098) +#define USERROW_USERROW25 _SFR_MEM8(0x1099) +#define USERROW_USERROW26 _SFR_MEM8(0x109A) +#define USERROW_USERROW27 _SFR_MEM8(0x109B) +#define USERROW_USERROW28 _SFR_MEM8(0x109C) +#define USERROW_USERROW29 _SFR_MEM8(0x109D) +#define USERROW_USERROW30 _SFR_MEM8(0x109E) +#define USERROW_USERROW31 _SFR_MEM8(0x109F) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_TEMPSENSE0 _SFR_MEM16(0x1104) +#define SIGROW_TEMPSENSE0L _SFR_MEM8(0x1104) +#define SIGROW_TEMPSENSE0H _SFR_MEM8(0x1105) +#define SIGROW_TEMPSENSE1 _SFR_MEM16(0x1106) +#define SIGROW_TEMPSENSE1L _SFR_MEM8(0x1106) +#define SIGROW_TEMPSENSE1H _SFR_MEM8(0x1107) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1110) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1111) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1112) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1113) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1114) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1115) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1116) +#define SIGROW_SERNUM7 _SFR_MEM8(0x1117) +#define SIGROW_SERNUM8 _SFR_MEM8(0x1118) +#define SIGROW_SERNUM9 _SFR_MEM8(0x1119) +#define SIGROW_SERNUM10 _SFR_MEM8(0x111A) +#define SIGROW_SERNUM11 _SFR_MEM8(0x111B) +#define SIGROW_SERNUM12 _SFR_MEM8(0x111C) +#define SIGROW_SERNUM13 _SFR_MEM8(0x111D) +#define SIGROW_SERNUM14 _SFR_MEM8(0x111E) +#define SIGROW_SERNUM15 _SFR_MEM8(0x111F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_POWER_gm 0x18 /* Power profile group mask. */ +#define AC_POWER_gp 3 /* Power profile group position. */ +#define AC_POWER0_bm (1<<3) /* Power profile bit 0 mask. */ +#define AC_POWER0_bp 3 /* Power profile bit 0 position. */ +#define AC_POWER1_bm (1<<4) /* Power profile bit 1 mask. */ +#define AC_POWER1_bp 4 /* Power profile bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Pad Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Pad Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_WINSEL_gm 0x03 /* Window selection mode group mask. */ +#define AC_WINSEL_gp 0 /* Window selection mode group position. */ +#define AC_WINSEL0_bm (1<<0) /* Window selection mode bit 0 mask. */ +#define AC_WINSEL0_bp 0 /* Window selection mode bit 0 position. */ +#define AC_WINSEL1_bm (1<<1) /* Window selection mode bit 1 mask. */ +#define AC_WINSEL1_bp 1 /* Window selection mode bit 1 position. */ + +/* AC.MUXCTRL bit masks and bit positions */ +#define AC_MUXNEG_gm 0x07 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* Negative Input MUX Selection bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* Negative Input MUX Selection bit 2 position. */ +#define AC_MUXPOS_gm 0x38 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* Positive Input MUX Selection bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* Positive Input MUX Selection bit 2 position. */ +#define AC_INITVAL_bm 0x40 /* AC Output Initial Value bit mask. */ +#define AC_INITVAL_bp 6 /* AC Output Initial Value bit position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.DACREF bit masks and bit positions */ +#define AC_DACREF_gm 0xFF /* DACREF group mask. */ +#define AC_DACREF_gp 0 /* DACREF group position. */ +#define AC_DACREF0_bm (1<<0) /* DACREF bit 0 mask. */ +#define AC_DACREF0_bp 0 /* DACREF bit 0 position. */ +#define AC_DACREF1_bm (1<<1) /* DACREF bit 1 mask. */ +#define AC_DACREF1_bp 1 /* DACREF bit 1 position. */ +#define AC_DACREF2_bm (1<<2) /* DACREF bit 2 mask. */ +#define AC_DACREF2_bp 2 /* DACREF bit 2 position. */ +#define AC_DACREF3_bm (1<<3) /* DACREF bit 3 mask. */ +#define AC_DACREF3_bp 3 /* DACREF bit 3 position. */ +#define AC_DACREF4_bm (1<<4) /* DACREF bit 4 mask. */ +#define AC_DACREF4_bp 4 /* DACREF bit 4 position. */ +#define AC_DACREF5_bm (1<<5) /* DACREF bit 5 mask. */ +#define AC_DACREF5_bp 5 /* DACREF bit 5 position. */ +#define AC_DACREF6_bm (1<<6) /* DACREF bit 6 mask. */ +#define AC_DACREF6_bp 6 /* DACREF bit 6 position. */ +#define AC_DACREF7_bm (1<<7) /* DACREF bit 7 mask. */ +#define AC_DACREF7_bp 7 /* DACREF bit 7 position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_CMPIF_bm 0x01 /* Analog Comparator Interrupt Flag bit mask. */ +#define AC_CMPIF_bp 0 /* Analog Comparator Interrupt Flag bit position. */ +#define AC_CMPSTATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_CMPSTATE_bp 4 /* Analog Comparator State bit position. */ +#define AC_WINSTATE_gm 0xC0 /* Analog Comparator Window State group mask. */ +#define AC_WINSTATE_gp 6 /* Analog Comparator Window State group position. */ +#define AC_WINSTATE0_bm (1<<6) /* Analog Comparator Window State bit 0 mask. */ +#define AC_WINSTATE0_bp 6 /* Analog Comparator Window State bit 0 position. */ +#define AC_WINSTATE1_bm (1<<7) /* Analog Comparator Window State bit 1 mask. */ +#define AC_WINSTATE1_bp 7 /* Analog Comparator Window State bit 1 position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* Free running mode bit mask. */ +#define ADC_FREERUN_bp 1 /* Free running mode bit position. */ +#define ADC_RESSEL_gm 0x0C /* Resolution selection group mask. */ +#define ADC_RESSEL_gp 2 /* Resolution selection group position. */ +#define ADC_RESSEL0_bm (1<<2) /* Resolution selection bit 0 mask. */ +#define ADC_RESSEL0_bp 2 /* Resolution selection bit 0 position. */ +#define ADC_RESSEL1_bm (1<<3) /* Resolution selection bit 1 mask. */ +#define ADC_RESSEL1_bp 3 /* Resolution selection bit 1 position. */ +#define ADC_LEFTADJ_bm 0x10 /* Left adjust result bit mask. */ +#define ADC_LEFTADJ_bp 4 /* Left adjust result bit position. */ +#define ADC_CONVMODE_bm 0x20 /* Conversion mode bit mask. */ +#define ADC_CONVMODE_bp 5 /* Conversion mode bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x0F /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_PRESC3_bm (1<<3) /* Clock Pre-scaler bit 3 mask. */ +#define ADC_PRESC3_bp 3 /* Clock Pre-scaler bit 3 position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0xFF /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ +#define ADC_SAMPLEN5_bm (1<<5) /* Sample lenght bit 5 mask. */ +#define ADC_SAMPLEN5_bp 5 /* Sample lenght bit 5 position. */ +#define ADC_SAMPLEN6_bm (1<<6) /* Sample lenght bit 6 mask. */ +#define ADC_SAMPLEN6_bp 6 /* Sample lenght bit 6 position. */ +#define ADC_SAMPLEN7_bm (1<<7) /* Sample lenght bit 7 mask. */ +#define ADC_SAMPLEN7_bp 7 /* Sample lenght bit 7 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x7F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ +#define ADC_MUXPOS5_bm (1<<5) /* Analog Channel Selection Bits bit 5 mask. */ +#define ADC_MUXPOS5_bp 5 /* Analog Channel Selection Bits bit 5 position. */ +#define ADC_MUXPOS6_bm (1<<6) /* Analog Channel Selection Bits bit 6 mask. */ +#define ADC_MUXPOS6_bp 6 /* Analog Channel Selection Bits bit 6 position. */ + +/* ADC.MUXNEG bit masks and bit positions */ +#define ADC_MUXNEG_gm 0x7F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXNEG_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXNEG0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXNEG0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXNEG1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXNEG1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXNEG2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXNEG2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXNEG3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXNEG3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXNEG4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXNEG4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ +#define ADC_MUXNEG5_bm (1<<5) /* Analog Channel Selection Bits bit 5 mask. */ +#define ADC_MUXNEG5_bp 5 /* Analog Channel Selection Bits bit 5 position. */ +#define ADC_MUXNEG6_bm (1<<6) /* Analog Channel Selection Bits bit 6 mask. */ +#define ADC_MUXNEG6_bp 6 /* Analog Channel Selection Bits bit 6 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion bit position. */ +#define ADC_SPCONV_bm 0x02 /* Stop Conversion bit mask. */ +#define ADC_SPCONV_bp 1 /* Stop Conversion bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL0_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL0_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL00_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL00_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL01_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL01_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL02_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL02_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.SEQCTRL1 bit masks and bit positions */ +#define CCL_SEQSEL1_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL1_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL10_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL10_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL11_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL11_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL12_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL12_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.SEQCTRL2 bit masks and bit positions */ +#define CCL_SEQSEL2_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL2_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL20_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL20_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL21_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL21_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL22_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL22_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.INTCTRL0 bit masks and bit positions */ +#define CCL_INTMODE0_gm 0x03 /* Interrupt Mode for LUT0 group mask. */ +#define CCL_INTMODE0_gp 0 /* Interrupt Mode for LUT0 group position. */ +#define CCL_INTMODE00_bm (1<<0) /* Interrupt Mode for LUT0 bit 0 mask. */ +#define CCL_INTMODE00_bp 0 /* Interrupt Mode for LUT0 bit 0 position. */ +#define CCL_INTMODE01_bm (1<<1) /* Interrupt Mode for LUT0 bit 1 mask. */ +#define CCL_INTMODE01_bp 1 /* Interrupt Mode for LUT0 bit 1 position. */ +#define CCL_INTMODE1_gm 0x0C /* Interrupt Mode for LUT1 group mask. */ +#define CCL_INTMODE1_gp 2 /* Interrupt Mode for LUT1 group position. */ +#define CCL_INTMODE10_bm (1<<2) /* Interrupt Mode for LUT1 bit 0 mask. */ +#define CCL_INTMODE10_bp 2 /* Interrupt Mode for LUT1 bit 0 position. */ +#define CCL_INTMODE11_bm (1<<3) /* Interrupt Mode for LUT1 bit 1 mask. */ +#define CCL_INTMODE11_bp 3 /* Interrupt Mode for LUT1 bit 1 position. */ +#define CCL_INTMODE2_gm 0x30 /* Interrupt Mode for LUT2 group mask. */ +#define CCL_INTMODE2_gp 4 /* Interrupt Mode for LUT2 group position. */ +#define CCL_INTMODE20_bm (1<<4) /* Interrupt Mode for LUT2 bit 0 mask. */ +#define CCL_INTMODE20_bp 4 /* Interrupt Mode for LUT2 bit 0 position. */ +#define CCL_INTMODE21_bm (1<<5) /* Interrupt Mode for LUT2 bit 1 mask. */ +#define CCL_INTMODE21_bp 5 /* Interrupt Mode for LUT2 bit 1 position. */ +#define CCL_INTMODE3_gm 0xC0 /* Interrupt Mode for LUT3 group mask. */ +#define CCL_INTMODE3_gp 6 /* Interrupt Mode for LUT3 group position. */ +#define CCL_INTMODE30_bm (1<<6) /* Interrupt Mode for LUT3 bit 0 mask. */ +#define CCL_INTMODE30_bp 6 /* Interrupt Mode for LUT3 bit 0 position. */ +#define CCL_INTMODE31_bm (1<<7) /* Interrupt Mode for LUT3 bit 1 mask. */ +#define CCL_INTMODE31_bp 7 /* Interrupt Mode for LUT3 bit 1 position. */ + +/* CCL.INTCTRL1 bit masks and bit positions */ +#define CCL_INTMODE4_gm 0x03 /* Interrupt Mode for LUT4 group mask. */ +#define CCL_INTMODE4_gp 0 /* Interrupt Mode for LUT4 group position. */ +#define CCL_INTMODE40_bm (1<<0) /* Interrupt Mode for LUT4 bit 0 mask. */ +#define CCL_INTMODE40_bp 0 /* Interrupt Mode for LUT4 bit 0 position. */ +#define CCL_INTMODE41_bm (1<<1) /* Interrupt Mode for LUT4 bit 1 mask. */ +#define CCL_INTMODE41_bp 1 /* Interrupt Mode for LUT4 bit 1 position. */ +#define CCL_INTMODE5_gm 0x0C /* Interrupt Mode for LUT5 group mask. */ +#define CCL_INTMODE5_gp 2 /* Interrupt Mode for LUT5 group position. */ +#define CCL_INTMODE50_bm (1<<2) /* Interrupt Mode for LUT5 bit 0 mask. */ +#define CCL_INTMODE50_bp 2 /* Interrupt Mode for LUT5 bit 0 position. */ +#define CCL_INTMODE51_bm (1<<3) /* Interrupt Mode for LUT5 bit 1 mask. */ +#define CCL_INTMODE51_bp 3 /* Interrupt Mode for LUT5 bit 1 position. */ + +/* CCL.INTFLAGS bit masks and bit positions */ +#define CCL_INT_gm 0xFF /* Interrupt Flags group mask. */ +#define CCL_INT_gp 0 /* Interrupt Flags group position. */ +#define CCL_INT0_bm (1<<0) /* Interrupt Flags bit 0 mask. */ +#define CCL_INT0_bp 0 /* Interrupt Flags bit 0 position. */ +#define CCL_INT1_bm (1<<1) /* Interrupt Flags bit 1 mask. */ +#define CCL_INT1_bp 1 /* Interrupt Flags bit 1 position. */ +#define CCL_INT2_bm (1<<2) /* Interrupt Flags bit 2 mask. */ +#define CCL_INT2_bp 2 /* Interrupt Flags bit 2 position. */ +#define CCL_INT3_bm (1<<3) /* Interrupt Flags bit 3 mask. */ +#define CCL_INT3_bp 3 /* Interrupt Flags bit 3 position. */ +#define CCL_INT4_bm (1<<4) /* Interrupt Flags bit 4 mask. */ +#define CCL_INT4_bp 4 /* Interrupt Flags bit 4 position. */ +#define CCL_INT5_bm (1<<5) /* Interrupt Flags bit 5 mask. */ +#define CCL_INT5_bp 5 /* Interrupt Flags bit 5 position. */ +#define CCL_INT6_bm (1<<6) /* Interrupt Flags bit 6 mask. */ +#define CCL_INT6_bp 6 /* Interrupt Flags bit 6 position. */ +#define CCL_INT7_bm (1<<7) /* Interrupt Flags bit 7 mask. */ +#define CCL_INT7_bp 7 /* Interrupt Flags bit 7 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_CLKSRC_gm 0x0E /* Clock Source Selection group mask. */ +#define CCL_CLKSRC_gp 1 /* Clock Source Selection group position. */ +#define CCL_CLKSRC0_bm (1<<1) /* Clock Source Selection bit 0 mask. */ +#define CCL_CLKSRC0_bp 1 /* Clock Source Selection bit 0 position. */ +#define CCL_CLKSRC1_bm (1<<2) /* Clock Source Selection bit 1 mask. */ +#define CCL_CLKSRC1_bp 2 /* Clock Source Selection bit 1 position. */ +#define CCL_CLKSRC2_bm (1<<3) /* Clock Source Selection bit 2 mask. */ +#define CCL_CLKSRC2_bp 3 /* Clock Source Selection bit 2 position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_OUTEN_bm 0x40 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 6 /* Output Enable bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT2CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT2CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT2CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT3CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT3CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT3CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT4CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT4CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT4CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT5CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT5CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT5CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x07 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKSEL2_bm (1<<2) /* clock select bit 2 mask. */ +#define CLKCTRL_CLKSEL2_bp 2 /* clock select bit 2 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSCHFS_bm 0x02 /* High frequency oscillator status bit mask. */ +#define CLKCTRL_OSCHFS_bp 1 /* High frequency oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x04 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 2 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x08 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 3 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x10 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 4 /* External Clock status bit position. */ +#define CLKCTRL_PLLS_bm 0x20 /* PLL oscillator status bit mask. */ +#define CLKCTRL_PLLS_bp 5 /* PLL oscillator status bit position. */ + +/* CLKCTRL.OSCHFCTRLA bit masks and bit positions */ +#define CLKCTRL_AUTOTUNE_bm 0x01 /* Autotune bit mask. */ +#define CLKCTRL_AUTOTUNE_bp 0 /* Autotune bit position. */ +#define CLKCTRL_FREQSEL_gm 0x3C /* Frequency select group mask. */ +#define CLKCTRL_FREQSEL_gp 2 /* Frequency select group position. */ +#define CLKCTRL_FREQSEL0_bm (1<<2) /* Frequency select bit 0 mask. */ +#define CLKCTRL_FREQSEL0_bp 2 /* Frequency select bit 0 position. */ +#define CLKCTRL_FREQSEL1_bm (1<<3) /* Frequency select bit 1 mask. */ +#define CLKCTRL_FREQSEL1_bp 3 /* Frequency select bit 1 position. */ +#define CLKCTRL_FREQSEL2_bm (1<<4) /* Frequency select bit 2 mask. */ +#define CLKCTRL_FREQSEL2_bp 4 /* Frequency select bit 2 position. */ +#define CLKCTRL_FREQSEL3_bm (1<<5) /* Frequency select bit 3 mask. */ +#define CLKCTRL_FREQSEL3_bp 5 /* Frequency select bit 3 position. */ +#define CLKCTRL_RUNSTDBY_bm 0x80 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 7 /* Run standby bit position. */ + +/* CLKCTRL.OSCHFTUNE bit masks and bit positions */ +#define CLKCTRL_TUNE_gm 0xFF /* Tune group mask. */ +#define CLKCTRL_TUNE_gp 0 /* Tune group position. */ +#define CLKCTRL_TUNE0_bm (1<<0) /* Tune bit 0 mask. */ +#define CLKCTRL_TUNE0_bp 0 /* Tune bit 0 position. */ +#define CLKCTRL_TUNE1_bm (1<<1) /* Tune bit 1 mask. */ +#define CLKCTRL_TUNE1_bp 1 /* Tune bit 1 position. */ +#define CLKCTRL_TUNE2_bm (1<<2) /* Tune bit 2 mask. */ +#define CLKCTRL_TUNE2_bp 2 /* Tune bit 2 position. */ +#define CLKCTRL_TUNE3_bm (1<<3) /* Tune bit 3 mask. */ +#define CLKCTRL_TUNE3_bp 3 /* Tune bit 3 position. */ +#define CLKCTRL_TUNE4_bm (1<<4) /* Tune bit 4 mask. */ +#define CLKCTRL_TUNE4_bp 4 /* Tune bit 4 position. */ +#define CLKCTRL_TUNE5_bm (1<<5) /* Tune bit 5 mask. */ +#define CLKCTRL_TUNE5_bp 5 /* Tune bit 5 position. */ +#define CLKCTRL_TUNE6_bm (1<<6) /* Tune bit 6 mask. */ +#define CLKCTRL_TUNE6_bp 6 /* Tune bit 6 position. */ +#define CLKCTRL_TUNE7_bm (1<<7) /* Tune bit 7 mask. */ +#define CLKCTRL_TUNE7_bp 7 /* Tune bit 7 position. */ + +/* CLKCTRL.PLLCTRLA bit masks and bit positions */ +#define CLKCTRL_MULFAC_gm 0x03 /* Multiplication factor group mask. */ +#define CLKCTRL_MULFAC_gp 0 /* Multiplication factor group position. */ +#define CLKCTRL_MULFAC0_bm (1<<0) /* Multiplication factor bit 0 mask. */ +#define CLKCTRL_MULFAC0_bp 0 /* Multiplication factor bit 0 position. */ +#define CLKCTRL_MULFAC1_bm (1<<1) /* Multiplication factor bit 1 mask. */ +#define CLKCTRL_MULFAC1_bp 1 /* Multiplication factor bit 1 position. */ +#define CLKCTRL_SOURCE_bm 0x10 /* Source bit mask. */ +#define CLKCTRL_SOURCE_bp 4 /* Source bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +#define CLKCTRL_LPMODE_bm 0x02 /* Low power mode bit mask. */ +#define CLKCTRL_LPMODE_bp 1 /* Low power mode bit position. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* DAC.DATA bit masks and bit positions */ +#define DAC_DATA_gm 0xFFC0 /* Data group mask. */ +#define DAC_DATA_gp 6 /* Data group position. */ +#define DAC_DATA0_bm (1<<6) /* Data bit 0 mask. */ +#define DAC_DATA0_bp 6 /* Data bit 0 position. */ +#define DAC_DATA1_bm (1<<7) /* Data bit 1 mask. */ +#define DAC_DATA1_bp 7 /* Data bit 1 position. */ +#define DAC_DATA2_bm (1<<8) /* Data bit 2 mask. */ +#define DAC_DATA2_bp 8 /* Data bit 2 position. */ +#define DAC_DATA3_bm (1<<9) /* Data bit 3 mask. */ +#define DAC_DATA3_bp 9 /* Data bit 3 position. */ +#define DAC_DATA4_bm (1<<10) /* Data bit 4 mask. */ +#define DAC_DATA4_bp 10 /* Data bit 4 position. */ +#define DAC_DATA5_bm (1<<11) /* Data bit 5 mask. */ +#define DAC_DATA5_bp 11 /* Data bit 5 position. */ +#define DAC_DATA6_bm (1<<12) /* Data bit 6 mask. */ +#define DAC_DATA6_bp 12 /* Data bit 6 position. */ +#define DAC_DATA7_bm (1<<13) /* Data bit 7 mask. */ +#define DAC_DATA7_bp 13 /* Data bit 7 position. */ +#define DAC_DATA8_bm (1<<14) /* Data bit 8 mask. */ +#define DAC_DATA8_bp 14 /* Data bit 8 position. */ +#define DAC_DATA9_bm (1<<15) /* Data bit 9 mask. */ +#define DAC_DATA9_bp 15 /* Data bit 9 position. */ + +/* EVSYS - Event System */ +/* EVSYS.SWEVENTA bit masks and bit positions */ +#define EVSYS_SWEVENTA_gm 0xFF /* Software event on channel select group mask. */ +#define EVSYS_SWEVENTA_gp 0 /* Software event on channel select group position. */ +#define EVSYS_SWEVENTA0_bm (1<<0) /* Software event on channel select bit 0 mask. */ +#define EVSYS_SWEVENTA0_bp 0 /* Software event on channel select bit 0 position. */ +#define EVSYS_SWEVENTA1_bm (1<<1) /* Software event on channel select bit 1 mask. */ +#define EVSYS_SWEVENTA1_bp 1 /* Software event on channel select bit 1 position. */ +#define EVSYS_SWEVENTA2_bm (1<<2) /* Software event on channel select bit 2 mask. */ +#define EVSYS_SWEVENTA2_bp 2 /* Software event on channel select bit 2 position. */ +#define EVSYS_SWEVENTA3_bm (1<<3) /* Software event on channel select bit 3 mask. */ +#define EVSYS_SWEVENTA3_bp 3 /* Software event on channel select bit 3 position. */ +#define EVSYS_SWEVENTA4_bm (1<<4) /* Software event on channel select bit 4 mask. */ +#define EVSYS_SWEVENTA4_bp 4 /* Software event on channel select bit 4 position. */ +#define EVSYS_SWEVENTA5_bm (1<<5) /* Software event on channel select bit 5 mask. */ +#define EVSYS_SWEVENTA5_bp 5 /* Software event on channel select bit 5 position. */ +#define EVSYS_SWEVENTA6_bm (1<<6) /* Software event on channel select bit 6 mask. */ +#define EVSYS_SWEVENTA6_bp 6 /* Software event on channel select bit 6 position. */ +#define EVSYS_SWEVENTA7_bm (1<<7) /* Software event on channel select bit 7 mask. */ +#define EVSYS_SWEVENTA7_bp 7 /* Software event on channel select bit 7 position. */ + +/* EVSYS.SWEVENTB bit masks and bit positions */ +#define EVSYS_SWEVENTB_gm 0x03 /* Software event on channel select group mask. */ +#define EVSYS_SWEVENTB_gp 0 /* Software event on channel select group position. */ +#define EVSYS_SWEVENTB0_bm (1<<0) /* Software event on channel select bit 0 mask. */ +#define EVSYS_SWEVENTB0_bp 0 /* Software event on channel select bit 0 position. */ +#define EVSYS_SWEVENTB1_bm (1<<1) /* Software event on channel select bit 1 mask. */ +#define EVSYS_SWEVENTB1_bp 1 /* Software event on channel select bit 1 position. */ + +/* EVSYS.CHANNEL0 bit masks and bit positions */ +#define EVSYS_CHANNEL0_gm 0xFF /* Channel 0 generator select group mask. */ +#define EVSYS_CHANNEL0_gp 0 /* Channel 0 generator select group position. */ +#define EVSYS_CHANNEL00_bm (1<<0) /* Channel 0 generator select bit 0 mask. */ +#define EVSYS_CHANNEL00_bp 0 /* Channel 0 generator select bit 0 position. */ +#define EVSYS_CHANNEL01_bm (1<<1) /* Channel 0 generator select bit 1 mask. */ +#define EVSYS_CHANNEL01_bp 1 /* Channel 0 generator select bit 1 position. */ +#define EVSYS_CHANNEL02_bm (1<<2) /* Channel 0 generator select bit 2 mask. */ +#define EVSYS_CHANNEL02_bp 2 /* Channel 0 generator select bit 2 position. */ +#define EVSYS_CHANNEL03_bm (1<<3) /* Channel 0 generator select bit 3 mask. */ +#define EVSYS_CHANNEL03_bp 3 /* Channel 0 generator select bit 3 position. */ +#define EVSYS_CHANNEL04_bm (1<<4) /* Channel 0 generator select bit 4 mask. */ +#define EVSYS_CHANNEL04_bp 4 /* Channel 0 generator select bit 4 position. */ +#define EVSYS_CHANNEL05_bm (1<<5) /* Channel 0 generator select bit 5 mask. */ +#define EVSYS_CHANNEL05_bp 5 /* Channel 0 generator select bit 5 position. */ +#define EVSYS_CHANNEL06_bm (1<<6) /* Channel 0 generator select bit 6 mask. */ +#define EVSYS_CHANNEL06_bp 6 /* Channel 0 generator select bit 6 position. */ +#define EVSYS_CHANNEL07_bm (1<<7) /* Channel 0 generator select bit 7 mask. */ +#define EVSYS_CHANNEL07_bp 7 /* Channel 0 generator select bit 7 position. */ + +/* EVSYS.CHANNEL1 bit masks and bit positions */ +#define EVSYS_CHANNEL1_gm 0xFF /* Channel 1 generator select group mask. */ +#define EVSYS_CHANNEL1_gp 0 /* Channel 1 generator select group position. */ +#define EVSYS_CHANNEL10_bm (1<<0) /* Channel 1 generator select bit 0 mask. */ +#define EVSYS_CHANNEL10_bp 0 /* Channel 1 generator select bit 0 position. */ +#define EVSYS_CHANNEL11_bm (1<<1) /* Channel 1 generator select bit 1 mask. */ +#define EVSYS_CHANNEL11_bp 1 /* Channel 1 generator select bit 1 position. */ +#define EVSYS_CHANNEL12_bm (1<<2) /* Channel 1 generator select bit 2 mask. */ +#define EVSYS_CHANNEL12_bp 2 /* Channel 1 generator select bit 2 position. */ +#define EVSYS_CHANNEL13_bm (1<<3) /* Channel 1 generator select bit 3 mask. */ +#define EVSYS_CHANNEL13_bp 3 /* Channel 1 generator select bit 3 position. */ +#define EVSYS_CHANNEL14_bm (1<<4) /* Channel 1 generator select bit 4 mask. */ +#define EVSYS_CHANNEL14_bp 4 /* Channel 1 generator select bit 4 position. */ +#define EVSYS_CHANNEL15_bm (1<<5) /* Channel 1 generator select bit 5 mask. */ +#define EVSYS_CHANNEL15_bp 5 /* Channel 1 generator select bit 5 position. */ +#define EVSYS_CHANNEL16_bm (1<<6) /* Channel 1 generator select bit 6 mask. */ +#define EVSYS_CHANNEL16_bp 6 /* Channel 1 generator select bit 6 position. */ +#define EVSYS_CHANNEL17_bm (1<<7) /* Channel 1 generator select bit 7 mask. */ +#define EVSYS_CHANNEL17_bp 7 /* Channel 1 generator select bit 7 position. */ + +/* EVSYS.CHANNEL2 bit masks and bit positions */ +#define EVSYS_CHANNEL2_gm 0xFF /* Channel 2 generator select group mask. */ +#define EVSYS_CHANNEL2_gp 0 /* Channel 2 generator select group position. */ +#define EVSYS_CHANNEL20_bm (1<<0) /* Channel 2 generator select bit 0 mask. */ +#define EVSYS_CHANNEL20_bp 0 /* Channel 2 generator select bit 0 position. */ +#define EVSYS_CHANNEL21_bm (1<<1) /* Channel 2 generator select bit 1 mask. */ +#define EVSYS_CHANNEL21_bp 1 /* Channel 2 generator select bit 1 position. */ +#define EVSYS_CHANNEL22_bm (1<<2) /* Channel 2 generator select bit 2 mask. */ +#define EVSYS_CHANNEL22_bp 2 /* Channel 2 generator select bit 2 position. */ +#define EVSYS_CHANNEL23_bm (1<<3) /* Channel 2 generator select bit 3 mask. */ +#define EVSYS_CHANNEL23_bp 3 /* Channel 2 generator select bit 3 position. */ +#define EVSYS_CHANNEL24_bm (1<<4) /* Channel 2 generator select bit 4 mask. */ +#define EVSYS_CHANNEL24_bp 4 /* Channel 2 generator select bit 4 position. */ +#define EVSYS_CHANNEL25_bm (1<<5) /* Channel 2 generator select bit 5 mask. */ +#define EVSYS_CHANNEL25_bp 5 /* Channel 2 generator select bit 5 position. */ +#define EVSYS_CHANNEL26_bm (1<<6) /* Channel 2 generator select bit 6 mask. */ +#define EVSYS_CHANNEL26_bp 6 /* Channel 2 generator select bit 6 position. */ +#define EVSYS_CHANNEL27_bm (1<<7) /* Channel 2 generator select bit 7 mask. */ +#define EVSYS_CHANNEL27_bp 7 /* Channel 2 generator select bit 7 position. */ + +/* EVSYS.CHANNEL3 bit masks and bit positions */ +#define EVSYS_CHANNEL3_gm 0xFF /* Channel 3 generator select group mask. */ +#define EVSYS_CHANNEL3_gp 0 /* Channel 3 generator select group position. */ +#define EVSYS_CHANNEL30_bm (1<<0) /* Channel 3 generator select bit 0 mask. */ +#define EVSYS_CHANNEL30_bp 0 /* Channel 3 generator select bit 0 position. */ +#define EVSYS_CHANNEL31_bm (1<<1) /* Channel 3 generator select bit 1 mask. */ +#define EVSYS_CHANNEL31_bp 1 /* Channel 3 generator select bit 1 position. */ +#define EVSYS_CHANNEL32_bm (1<<2) /* Channel 3 generator select bit 2 mask. */ +#define EVSYS_CHANNEL32_bp 2 /* Channel 3 generator select bit 2 position. */ +#define EVSYS_CHANNEL33_bm (1<<3) /* Channel 3 generator select bit 3 mask. */ +#define EVSYS_CHANNEL33_bp 3 /* Channel 3 generator select bit 3 position. */ +#define EVSYS_CHANNEL34_bm (1<<4) /* Channel 3 generator select bit 4 mask. */ +#define EVSYS_CHANNEL34_bp 4 /* Channel 3 generator select bit 4 position. */ +#define EVSYS_CHANNEL35_bm (1<<5) /* Channel 3 generator select bit 5 mask. */ +#define EVSYS_CHANNEL35_bp 5 /* Channel 3 generator select bit 5 position. */ +#define EVSYS_CHANNEL36_bm (1<<6) /* Channel 3 generator select bit 6 mask. */ +#define EVSYS_CHANNEL36_bp 6 /* Channel 3 generator select bit 6 position. */ +#define EVSYS_CHANNEL37_bm (1<<7) /* Channel 3 generator select bit 7 mask. */ +#define EVSYS_CHANNEL37_bp 7 /* Channel 3 generator select bit 7 position. */ + +/* EVSYS.CHANNEL4 bit masks and bit positions */ +#define EVSYS_CHANNEL4_gm 0xFF /* Channel 4 generator select group mask. */ +#define EVSYS_CHANNEL4_gp 0 /* Channel 4 generator select group position. */ +#define EVSYS_CHANNEL40_bm (1<<0) /* Channel 4 generator select bit 0 mask. */ +#define EVSYS_CHANNEL40_bp 0 /* Channel 4 generator select bit 0 position. */ +#define EVSYS_CHANNEL41_bm (1<<1) /* Channel 4 generator select bit 1 mask. */ +#define EVSYS_CHANNEL41_bp 1 /* Channel 4 generator select bit 1 position. */ +#define EVSYS_CHANNEL42_bm (1<<2) /* Channel 4 generator select bit 2 mask. */ +#define EVSYS_CHANNEL42_bp 2 /* Channel 4 generator select bit 2 position. */ +#define EVSYS_CHANNEL43_bm (1<<3) /* Channel 4 generator select bit 3 mask. */ +#define EVSYS_CHANNEL43_bp 3 /* Channel 4 generator select bit 3 position. */ +#define EVSYS_CHANNEL44_bm (1<<4) /* Channel 4 generator select bit 4 mask. */ +#define EVSYS_CHANNEL44_bp 4 /* Channel 4 generator select bit 4 position. */ +#define EVSYS_CHANNEL45_bm (1<<5) /* Channel 4 generator select bit 5 mask. */ +#define EVSYS_CHANNEL45_bp 5 /* Channel 4 generator select bit 5 position. */ +#define EVSYS_CHANNEL46_bm (1<<6) /* Channel 4 generator select bit 6 mask. */ +#define EVSYS_CHANNEL46_bp 6 /* Channel 4 generator select bit 6 position. */ +#define EVSYS_CHANNEL47_bm (1<<7) /* Channel 4 generator select bit 7 mask. */ +#define EVSYS_CHANNEL47_bp 7 /* Channel 4 generator select bit 7 position. */ + +/* EVSYS.CHANNEL5 bit masks and bit positions */ +#define EVSYS_CHANNEL5_gm 0xFF /* Channel 5 generator select group mask. */ +#define EVSYS_CHANNEL5_gp 0 /* Channel 5 generator select group position. */ +#define EVSYS_CHANNEL50_bm (1<<0) /* Channel 5 generator select bit 0 mask. */ +#define EVSYS_CHANNEL50_bp 0 /* Channel 5 generator select bit 0 position. */ +#define EVSYS_CHANNEL51_bm (1<<1) /* Channel 5 generator select bit 1 mask. */ +#define EVSYS_CHANNEL51_bp 1 /* Channel 5 generator select bit 1 position. */ +#define EVSYS_CHANNEL52_bm (1<<2) /* Channel 5 generator select bit 2 mask. */ +#define EVSYS_CHANNEL52_bp 2 /* Channel 5 generator select bit 2 position. */ +#define EVSYS_CHANNEL53_bm (1<<3) /* Channel 5 generator select bit 3 mask. */ +#define EVSYS_CHANNEL53_bp 3 /* Channel 5 generator select bit 3 position. */ +#define EVSYS_CHANNEL54_bm (1<<4) /* Channel 5 generator select bit 4 mask. */ +#define EVSYS_CHANNEL54_bp 4 /* Channel 5 generator select bit 4 position. */ +#define EVSYS_CHANNEL55_bm (1<<5) /* Channel 5 generator select bit 5 mask. */ +#define EVSYS_CHANNEL55_bp 5 /* Channel 5 generator select bit 5 position. */ +#define EVSYS_CHANNEL56_bm (1<<6) /* Channel 5 generator select bit 6 mask. */ +#define EVSYS_CHANNEL56_bp 6 /* Channel 5 generator select bit 6 position. */ +#define EVSYS_CHANNEL57_bm (1<<7) /* Channel 5 generator select bit 7 mask. */ +#define EVSYS_CHANNEL57_bp 7 /* Channel 5 generator select bit 7 position. */ + +/* EVSYS.CHANNEL6 bit masks and bit positions */ +#define EVSYS_CHANNEL6_gm 0xFF /* Channel 6 generator select group mask. */ +#define EVSYS_CHANNEL6_gp 0 /* Channel 6 generator select group position. */ +#define EVSYS_CHANNEL60_bm (1<<0) /* Channel 6 generator select bit 0 mask. */ +#define EVSYS_CHANNEL60_bp 0 /* Channel 6 generator select bit 0 position. */ +#define EVSYS_CHANNEL61_bm (1<<1) /* Channel 6 generator select bit 1 mask. */ +#define EVSYS_CHANNEL61_bp 1 /* Channel 6 generator select bit 1 position. */ +#define EVSYS_CHANNEL62_bm (1<<2) /* Channel 6 generator select bit 2 mask. */ +#define EVSYS_CHANNEL62_bp 2 /* Channel 6 generator select bit 2 position. */ +#define EVSYS_CHANNEL63_bm (1<<3) /* Channel 6 generator select bit 3 mask. */ +#define EVSYS_CHANNEL63_bp 3 /* Channel 6 generator select bit 3 position. */ +#define EVSYS_CHANNEL64_bm (1<<4) /* Channel 6 generator select bit 4 mask. */ +#define EVSYS_CHANNEL64_bp 4 /* Channel 6 generator select bit 4 position. */ +#define EVSYS_CHANNEL65_bm (1<<5) /* Channel 6 generator select bit 5 mask. */ +#define EVSYS_CHANNEL65_bp 5 /* Channel 6 generator select bit 5 position. */ +#define EVSYS_CHANNEL66_bm (1<<6) /* Channel 6 generator select bit 6 mask. */ +#define EVSYS_CHANNEL66_bp 6 /* Channel 6 generator select bit 6 position. */ +#define EVSYS_CHANNEL67_bm (1<<7) /* Channel 6 generator select bit 7 mask. */ +#define EVSYS_CHANNEL67_bp 7 /* Channel 6 generator select bit 7 position. */ + +/* EVSYS.CHANNEL7 bit masks and bit positions */ +#define EVSYS_CHANNEL7_gm 0xFF /* Channel 7 generator select group mask. */ +#define EVSYS_CHANNEL7_gp 0 /* Channel 7 generator select group position. */ +#define EVSYS_CHANNEL70_bm (1<<0) /* Channel 7 generator select bit 0 mask. */ +#define EVSYS_CHANNEL70_bp 0 /* Channel 7 generator select bit 0 position. */ +#define EVSYS_CHANNEL71_bm (1<<1) /* Channel 7 generator select bit 1 mask. */ +#define EVSYS_CHANNEL71_bp 1 /* Channel 7 generator select bit 1 position. */ +#define EVSYS_CHANNEL72_bm (1<<2) /* Channel 7 generator select bit 2 mask. */ +#define EVSYS_CHANNEL72_bp 2 /* Channel 7 generator select bit 2 position. */ +#define EVSYS_CHANNEL73_bm (1<<3) /* Channel 7 generator select bit 3 mask. */ +#define EVSYS_CHANNEL73_bp 3 /* Channel 7 generator select bit 3 position. */ +#define EVSYS_CHANNEL74_bm (1<<4) /* Channel 7 generator select bit 4 mask. */ +#define EVSYS_CHANNEL74_bp 4 /* Channel 7 generator select bit 4 position. */ +#define EVSYS_CHANNEL75_bm (1<<5) /* Channel 7 generator select bit 5 mask. */ +#define EVSYS_CHANNEL75_bp 5 /* Channel 7 generator select bit 5 position. */ +#define EVSYS_CHANNEL76_bm (1<<6) /* Channel 7 generator select bit 6 mask. */ +#define EVSYS_CHANNEL76_bp 6 /* Channel 7 generator select bit 6 position. */ +#define EVSYS_CHANNEL77_bm (1<<7) /* Channel 7 generator select bit 7 mask. */ +#define EVSYS_CHANNEL77_bp 7 /* Channel 7 generator select bit 7 position. */ + +/* EVSYS.CHANNEL8 bit masks and bit positions */ +#define EVSYS_CHANNEL8_gm 0xFF /* Channel 8 generator select group mask. */ +#define EVSYS_CHANNEL8_gp 0 /* Channel 8 generator select group position. */ +#define EVSYS_CHANNEL80_bm (1<<0) /* Channel 8 generator select bit 0 mask. */ +#define EVSYS_CHANNEL80_bp 0 /* Channel 8 generator select bit 0 position. */ +#define EVSYS_CHANNEL81_bm (1<<1) /* Channel 8 generator select bit 1 mask. */ +#define EVSYS_CHANNEL81_bp 1 /* Channel 8 generator select bit 1 position. */ +#define EVSYS_CHANNEL82_bm (1<<2) /* Channel 8 generator select bit 2 mask. */ +#define EVSYS_CHANNEL82_bp 2 /* Channel 8 generator select bit 2 position. */ +#define EVSYS_CHANNEL83_bm (1<<3) /* Channel 8 generator select bit 3 mask. */ +#define EVSYS_CHANNEL83_bp 3 /* Channel 8 generator select bit 3 position. */ +#define EVSYS_CHANNEL84_bm (1<<4) /* Channel 8 generator select bit 4 mask. */ +#define EVSYS_CHANNEL84_bp 4 /* Channel 8 generator select bit 4 position. */ +#define EVSYS_CHANNEL85_bm (1<<5) /* Channel 8 generator select bit 5 mask. */ +#define EVSYS_CHANNEL85_bp 5 /* Channel 8 generator select bit 5 position. */ +#define EVSYS_CHANNEL86_bm (1<<6) /* Channel 8 generator select bit 6 mask. */ +#define EVSYS_CHANNEL86_bp 6 /* Channel 8 generator select bit 6 position. */ +#define EVSYS_CHANNEL87_bm (1<<7) /* Channel 8 generator select bit 7 mask. */ +#define EVSYS_CHANNEL87_bp 7 /* Channel 8 generator select bit 7 position. */ + +/* EVSYS.CHANNEL9 bit masks and bit positions */ +#define EVSYS_CHANNEL9_gm 0xFF /* Channel 9 generator select group mask. */ +#define EVSYS_CHANNEL9_gp 0 /* Channel 9 generator select group position. */ +#define EVSYS_CHANNEL90_bm (1<<0) /* Channel 9 generator select bit 0 mask. */ +#define EVSYS_CHANNEL90_bp 0 /* Channel 9 generator select bit 0 position. */ +#define EVSYS_CHANNEL91_bm (1<<1) /* Channel 9 generator select bit 1 mask. */ +#define EVSYS_CHANNEL91_bp 1 /* Channel 9 generator select bit 1 position. */ +#define EVSYS_CHANNEL92_bm (1<<2) /* Channel 9 generator select bit 2 mask. */ +#define EVSYS_CHANNEL92_bp 2 /* Channel 9 generator select bit 2 position. */ +#define EVSYS_CHANNEL93_bm (1<<3) /* Channel 9 generator select bit 3 mask. */ +#define EVSYS_CHANNEL93_bp 3 /* Channel 9 generator select bit 3 position. */ +#define EVSYS_CHANNEL94_bm (1<<4) /* Channel 9 generator select bit 4 mask. */ +#define EVSYS_CHANNEL94_bp 4 /* Channel 9 generator select bit 4 position. */ +#define EVSYS_CHANNEL95_bm (1<<5) /* Channel 9 generator select bit 5 mask. */ +#define EVSYS_CHANNEL95_bp 5 /* Channel 9 generator select bit 5 position. */ +#define EVSYS_CHANNEL96_bm (1<<6) /* Channel 9 generator select bit 6 mask. */ +#define EVSYS_CHANNEL96_bp 6 /* Channel 9 generator select bit 6 position. */ +#define EVSYS_CHANNEL97_bm (1<<7) /* Channel 9 generator select bit 7 mask. */ +#define EVSYS_CHANNEL97_bp 7 /* Channel 9 generator select bit 7 position. */ + +/* EVSYS.USERCCLLUT0A bit masks and bit positions */ +#define EVSYS_USER_gm 0xFF /* User channel select group mask. */ +#define EVSYS_USER_gp 0 /* User channel select group position. */ +#define EVSYS_USER0_bm (1<<0) /* User channel select bit 0 mask. */ +#define EVSYS_USER0_bp 0 /* User channel select bit 0 position. */ +#define EVSYS_USER1_bm (1<<1) /* User channel select bit 1 mask. */ +#define EVSYS_USER1_bp 1 /* User channel select bit 1 position. */ +#define EVSYS_USER2_bm (1<<2) /* User channel select bit 2 mask. */ +#define EVSYS_USER2_bp 2 /* User channel select bit 2 position. */ +#define EVSYS_USER3_bm (1<<3) /* User channel select bit 3 mask. */ +#define EVSYS_USER3_bp 3 /* User channel select bit 3 position. */ +#define EVSYS_USER4_bm (1<<4) /* User channel select bit 4 mask. */ +#define EVSYS_USER4_bp 4 /* User channel select bit 4 position. */ +#define EVSYS_USER5_bm (1<<5) /* User channel select bit 5 mask. */ +#define EVSYS_USER5_bp 5 /* User channel select bit 5 position. */ +#define EVSYS_USER6_bm (1<<6) /* User channel select bit 6 mask. */ +#define EVSYS_USER6_bp 6 /* User channel select bit 6 position. */ +#define EVSYS_USER7_bm (1<<7) /* User channel select bit 7 mask. */ +#define EVSYS_USER7_bp 7 /* User channel select bit 7 position. */ + +/* EVSYS.USERCCLLUT0B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT1A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT1B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT2A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT2B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT3A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT3B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT4A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT4B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT5A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT5B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERADC0START bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERPTCSTART bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTC bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTD bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTE bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTF bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTG bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART0IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART1IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART2IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART3IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART4IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART5IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA0CNTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA0CNTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA1CNTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA1CNTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB0CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB0COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB1CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB1COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB2CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB2COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB3CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB3COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB4CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB4COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCD0INPUTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCD0INPUTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEROSCTEST bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_CLKSEL_gm 0x07 /* Frequency Select group mask. */ +#define FUSE_CLKSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_CLKSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_CLKSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_CLKSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_CLKSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_CLKSEL2_bm (1<<2) /* Frequency Select bit 2 mask. */ +#define FUSE_CLKSEL2_bp 2 /* Frequency Select bit 2 position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSEL_bm 0x20 /* CRC Select bit mask. */ +#define FUSE_CRCSEL_bp 5 /* CRC Select bit position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCK - Lockbits */ +/* LOCK.KEY bit masks and bit positions */ +#define LOCK_KEY_gm 0xFFFFFFFF /* Lock Key group mask. */ +#define LOCK_KEY_gp 0 /* Lock Key group position. */ +#define LOCK_KEY0_bm (1<<0) /* Lock Key bit 0 mask. */ +#define LOCK_KEY0_bp 0 /* Lock Key bit 0 position. */ +#define LOCK_KEY1_bm (1<<1) /* Lock Key bit 1 mask. */ +#define LOCK_KEY1_bp 1 /* Lock Key bit 1 position. */ +#define LOCK_KEY2_bm (1<<2) /* Lock Key bit 2 mask. */ +#define LOCK_KEY2_bp 2 /* Lock Key bit 2 position. */ +#define LOCK_KEY3_bm (1<<3) /* Lock Key bit 3 mask. */ +#define LOCK_KEY3_bp 3 /* Lock Key bit 3 position. */ +#define LOCK_KEY4_bm (1<<4) /* Lock Key bit 4 mask. */ +#define LOCK_KEY4_bp 4 /* Lock Key bit 4 position. */ +#define LOCK_KEY5_bm (1<<5) /* Lock Key bit 5 mask. */ +#define LOCK_KEY5_bp 5 /* Lock Key bit 5 position. */ +#define LOCK_KEY6_bm (1<<6) /* Lock Key bit 6 mask. */ +#define LOCK_KEY6_bp 6 /* Lock Key bit 6 position. */ +#define LOCK_KEY7_bm (1<<7) /* Lock Key bit 7 mask. */ +#define LOCK_KEY7_bp 7 /* Lock Key bit 7 position. */ +#define LOCK_KEY8_bm (1<<8) /* Lock Key bit 8 mask. */ +#define LOCK_KEY8_bp 8 /* Lock Key bit 8 position. */ +#define LOCK_KEY9_bm (1<<9) /* Lock Key bit 9 mask. */ +#define LOCK_KEY9_bp 9 /* Lock Key bit 9 position. */ +#define LOCK_KEY10_bm (1<<10) /* Lock Key bit 10 mask. */ +#define LOCK_KEY10_bp 10 /* Lock Key bit 10 position. */ +#define LOCK_KEY11_bm (1<<11) /* Lock Key bit 11 mask. */ +#define LOCK_KEY11_bp 11 /* Lock Key bit 11 position. */ +#define LOCK_KEY12_bm (1<<12) /* Lock Key bit 12 mask. */ +#define LOCK_KEY12_bp 12 /* Lock Key bit 12 position. */ +#define LOCK_KEY13_bm (1<<13) /* Lock Key bit 13 mask. */ +#define LOCK_KEY13_bp 13 /* Lock Key bit 13 position. */ +#define LOCK_KEY14_bm (1<<14) /* Lock Key bit 14 mask. */ +#define LOCK_KEY14_bp 14 /* Lock Key bit 14 position. */ +#define LOCK_KEY15_bm (1<<15) /* Lock Key bit 15 mask. */ +#define LOCK_KEY15_bp 15 /* Lock Key bit 15 position. */ +#define LOCK_KEY16_bm (1<<16) /* Lock Key bit 16 mask. */ +#define LOCK_KEY16_bp 16 /* Lock Key bit 16 position. */ +#define LOCK_KEY17_bm (1<<17) /* Lock Key bit 17 mask. */ +#define LOCK_KEY17_bp 17 /* Lock Key bit 17 position. */ +#define LOCK_KEY18_bm (1<<18) /* Lock Key bit 18 mask. */ +#define LOCK_KEY18_bp 18 /* Lock Key bit 18 position. */ +#define LOCK_KEY19_bm (1<<19) /* Lock Key bit 19 mask. */ +#define LOCK_KEY19_bp 19 /* Lock Key bit 19 position. */ +#define LOCK_KEY20_bm (1<<20) /* Lock Key bit 20 mask. */ +#define LOCK_KEY20_bp 20 /* Lock Key bit 20 position. */ +#define LOCK_KEY21_bm (1<<21) /* Lock Key bit 21 mask. */ +#define LOCK_KEY21_bp 21 /* Lock Key bit 21 position. */ +#define LOCK_KEY22_bm (1<<22) /* Lock Key bit 22 mask. */ +#define LOCK_KEY22_bp 22 /* Lock Key bit 22 position. */ +#define LOCK_KEY23_bm (1<<23) /* Lock Key bit 23 mask. */ +#define LOCK_KEY23_bp 23 /* Lock Key bit 23 position. */ +#define LOCK_KEY24_bm (1<<24) /* Lock Key bit 24 mask. */ +#define LOCK_KEY24_bp 24 /* Lock Key bit 24 position. */ +#define LOCK_KEY25_bm (1<<25) /* Lock Key bit 25 mask. */ +#define LOCK_KEY25_bp 25 /* Lock Key bit 25 position. */ +#define LOCK_KEY26_bm (1<<26) /* Lock Key bit 26 mask. */ +#define LOCK_KEY26_bp 26 /* Lock Key bit 26 position. */ +#define LOCK_KEY27_bm (1<<27) /* Lock Key bit 27 mask. */ +#define LOCK_KEY27_bp 27 /* Lock Key bit 27 position. */ +#define LOCK_KEY28_bm (1<<28) /* Lock Key bit 28 mask. */ +#define LOCK_KEY28_bp 28 /* Lock Key bit 28 position. */ +#define LOCK_KEY29_bm (1<<29) /* Lock Key bit 29 mask. */ +#define LOCK_KEY29_bp 29 /* Lock Key bit 29 position. */ +#define LOCK_KEY30_bm (1<<30) /* Lock Key bit 30 mask. */ +#define LOCK_KEY30_bp 30 /* Lock Key bit 30 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x7F /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ +#define NVMCTRL_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVMCTRL_CMD3_bp 3 /* Command bit 3 position. */ +#define NVMCTRL_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVMCTRL_CMD4_bp 4 /* Command bit 4 position. */ +#define NVMCTRL_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVMCTRL_CMD5_bp 5 /* Command bit 5 position. */ +#define NVMCTRL_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVMCTRL_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APPCODEWP_bm 0x01 /* Application Code Write Protect bit mask. */ +#define NVMCTRL_APPCODEWP_bp 0 /* Application Code Write Protect bit position. */ +#define NVMCTRL_BOOTRP_bm 0x02 /* Boot Read Protect bit mask. */ +#define NVMCTRL_BOOTRP_bp 1 /* Boot Read Protect bit position. */ +#define NVMCTRL_APPDATAWP_bm 0x04 /* Application Data Write Protect bit mask. */ +#define NVMCTRL_APPDATAWP_bp 2 /* Application Data Write Protect bit position. */ +#define NVMCTRL_FLMAP_gm 0x30 /* Flash Mapping in Data space group mask. */ +#define NVMCTRL_FLMAP_gp 4 /* Flash Mapping in Data space group position. */ +#define NVMCTRL_FLMAP0_bm (1<<4) /* Flash Mapping in Data space bit 0 mask. */ +#define NVMCTRL_FLMAP0_bp 4 /* Flash Mapping in Data space bit 0 position. */ +#define NVMCTRL_FLMAP1_bm (1<<5) /* Flash Mapping in Data space bit 1 mask. */ +#define NVMCTRL_FLMAP1_bp 5 /* Flash Mapping in Data space bit 1 position. */ +#define NVMCTRL_FLMAPLOCK_bm 0x80 /* Flash Mapping Lock bit mask. */ +#define NVMCTRL_FLMAPLOCK_bp 7 /* Flash Mapping Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_ERROR_gm 0x70 /* Write error group mask. */ +#define NVMCTRL_ERROR_gp 4 /* Write error group position. */ +#define NVMCTRL_ERROR0_bm (1<<4) /* Write error bit 0 mask. */ +#define NVMCTRL_ERROR0_bp 4 /* Write error bit 0 position. */ +#define NVMCTRL_ERROR1_bm (1<<5) /* Write error bit 1 mask. */ +#define NVMCTRL_ERROR1_bp 5 /* Write error bit 1 position. */ +#define NVMCTRL_ERROR2_bm (1<<6) /* Write error bit 2 mask. */ +#define NVMCTRL_ERROR2_bp 6 /* Write error bit 2 position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PORTCTRL bit masks and bit positions */ +#define PORT_SRL_bm 0x01 /* Slew Rate Limit Enable bit mask. */ +#define PORT_SRL_bp 0 /* Slew Rate Limit Enable bit position. */ + +/* PORT.PINCONFIG bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PINCTRLUPD bit masks and bit positions */ +#define PORT_PINCTRLUPD_gm 0xFF /* Pin control update mask group mask. */ +#define PORT_PINCTRLUPD_gp 0 /* Pin control update mask group position. */ +#define PORT_PINCTRLUPD0_bm (1<<0) /* Pin control update mask bit 0 mask. */ +#define PORT_PINCTRLUPD0_bp 0 /* Pin control update mask bit 0 position. */ +#define PORT_PINCTRLUPD1_bm (1<<1) /* Pin control update mask bit 1 mask. */ +#define PORT_PINCTRLUPD1_bp 1 /* Pin control update mask bit 1 position. */ +#define PORT_PINCTRLUPD2_bm (1<<2) /* Pin control update mask bit 2 mask. */ +#define PORT_PINCTRLUPD2_bp 2 /* Pin control update mask bit 2 position. */ +#define PORT_PINCTRLUPD3_bm (1<<3) /* Pin control update mask bit 3 mask. */ +#define PORT_PINCTRLUPD3_bp 3 /* Pin control update mask bit 3 position. */ +#define PORT_PINCTRLUPD4_bm (1<<4) /* Pin control update mask bit 4 mask. */ +#define PORT_PINCTRLUPD4_bp 4 /* Pin control update mask bit 4 position. */ +#define PORT_PINCTRLUPD5_bm (1<<5) /* Pin control update mask bit 5 mask. */ +#define PORT_PINCTRLUPD5_bp 5 /* Pin control update mask bit 5 position. */ +#define PORT_PINCTRLUPD6_bm (1<<6) /* Pin control update mask bit 6 mask. */ +#define PORT_PINCTRLUPD6_bp 6 /* Pin control update mask bit 6 position. */ +#define PORT_PINCTRLUPD7_bm (1<<7) /* Pin control update mask bit 7 mask. */ +#define PORT_PINCTRLUPD7_bp 7 /* Pin control update mask bit 7 position. */ + +/* PORT.PINCTRLSET bit masks and bit positions */ +#define PORT_PINCTRLSET_gm 0xFF /* Pin control set mask group mask. */ +#define PORT_PINCTRLSET_gp 0 /* Pin control set mask group position. */ +#define PORT_PINCTRLSET0_bm (1<<0) /* Pin control set mask bit 0 mask. */ +#define PORT_PINCTRLSET0_bp 0 /* Pin control set mask bit 0 position. */ +#define PORT_PINCTRLSET1_bm (1<<1) /* Pin control set mask bit 1 mask. */ +#define PORT_PINCTRLSET1_bp 1 /* Pin control set mask bit 1 position. */ +#define PORT_PINCTRLSET2_bm (1<<2) /* Pin control set mask bit 2 mask. */ +#define PORT_PINCTRLSET2_bp 2 /* Pin control set mask bit 2 position. */ +#define PORT_PINCTRLSET3_bm (1<<3) /* Pin control set mask bit 3 mask. */ +#define PORT_PINCTRLSET3_bp 3 /* Pin control set mask bit 3 position. */ +#define PORT_PINCTRLSET4_bm (1<<4) /* Pin control set mask bit 4 mask. */ +#define PORT_PINCTRLSET4_bp 4 /* Pin control set mask bit 4 position. */ +#define PORT_PINCTRLSET5_bm (1<<5) /* Pin control set mask bit 5 mask. */ +#define PORT_PINCTRLSET5_bp 5 /* Pin control set mask bit 5 position. */ +#define PORT_PINCTRLSET6_bm (1<<6) /* Pin control set mask bit 6 mask. */ +#define PORT_PINCTRLSET6_bp 6 /* Pin control set mask bit 6 position. */ +#define PORT_PINCTRLSET7_bm (1<<7) /* Pin control set mask bit 7 mask. */ +#define PORT_PINCTRLSET7_bp 7 /* Pin control set mask bit 7 position. */ + +/* PORT.PINCTRLCLR bit masks and bit positions */ +#define PORT_PINCTRLCLR_gm 0xFF /* Pin control clear mask group mask. */ +#define PORT_PINCTRLCLR_gp 0 /* Pin control clear mask group position. */ +#define PORT_PINCTRLCLR0_bm (1<<0) /* Pin control clear mask bit 0 mask. */ +#define PORT_PINCTRLCLR0_bp 0 /* Pin control clear mask bit 0 position. */ +#define PORT_PINCTRLCLR1_bm (1<<1) /* Pin control clear mask bit 1 mask. */ +#define PORT_PINCTRLCLR1_bp 1 /* Pin control clear mask bit 1 position. */ +#define PORT_PINCTRLCLR2_bm (1<<2) /* Pin control clear mask bit 2 mask. */ +#define PORT_PINCTRLCLR2_bp 2 /* Pin control clear mask bit 2 position. */ +#define PORT_PINCTRLCLR3_bm (1<<3) /* Pin control clear mask bit 3 mask. */ +#define PORT_PINCTRLCLR3_bp 3 /* Pin control clear mask bit 3 position. */ +#define PORT_PINCTRLCLR4_bm (1<<4) /* Pin control clear mask bit 4 mask. */ +#define PORT_PINCTRLCLR4_bp 4 /* Pin control clear mask bit 4 position. */ +#define PORT_PINCTRLCLR5_bm (1<<5) /* Pin control clear mask bit 5 mask. */ +#define PORT_PINCTRLCLR5_bp 5 /* Pin control clear mask bit 5 position. */ +#define PORT_PINCTRLCLR6_bm (1<<6) /* Pin control clear mask bit 6 mask. */ +#define PORT_PINCTRLCLR6_bp 6 /* Pin control clear mask bit 6 position. */ +#define PORT_PINCTRLCLR7_bm (1<<7) /* Pin control clear mask bit 7 mask. */ +#define PORT_PINCTRLCLR7_bp 7 /* Pin control clear mask bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.EVSYSROUTEA bit masks and bit positions */ +#define PORTMUX_EVOUTA_bm 0x01 /* Event Output A bit mask. */ +#define PORTMUX_EVOUTA_bp 0 /* Event Output A bit position. */ +#define PORTMUX_EVOUTB_bm 0x02 /* Event Output B bit mask. */ +#define PORTMUX_EVOUTB_bp 1 /* Event Output B bit position. */ +#define PORTMUX_EVOUTC_bm 0x04 /* Event Output C bit mask. */ +#define PORTMUX_EVOUTC_bp 2 /* Event Output C bit position. */ +#define PORTMUX_EVOUTD_bm 0x08 /* Event Output D bit mask. */ +#define PORTMUX_EVOUTD_bp 3 /* Event Output D bit position. */ +#define PORTMUX_EVOUTE_bm 0x10 /* Event Output E bit mask. */ +#define PORTMUX_EVOUTE_bp 4 /* Event Output E bit position. */ +#define PORTMUX_EVOUTF_bm 0x20 /* Event Output F bit mask. */ +#define PORTMUX_EVOUTF_bp 5 /* Event Output F bit position. */ +#define PORTMUX_EVOUTG_bm 0x40 /* Event Output G bit mask. */ +#define PORTMUX_EVOUTG_bp 6 /* Event Output G bit position. */ + +/* PORTMUX.CCLROUTEA bit masks and bit positions */ +#define PORTMUX_LUT0_bm 0x01 /* CCL Look-Up Table 0 Signals bit mask. */ +#define PORTMUX_LUT0_bp 0 /* CCL Look-Up Table 0 Signals bit position. */ +#define PORTMUX_LUT1_bm 0x02 /* CCL Look-Up Table 1 Signals bit mask. */ +#define PORTMUX_LUT1_bp 1 /* CCL Look-Up Table 1 Signals bit position. */ +#define PORTMUX_LUT2_bm 0x04 /* CCL Look-Up Table 2 Signals bit mask. */ +#define PORTMUX_LUT2_bp 2 /* CCL Look-Up Table 2 Signals bit position. */ +#define PORTMUX_LUT3_bm 0x08 /* CCL Look-Up Table 3 Signals bit mask. */ +#define PORTMUX_LUT3_bp 3 /* CCL Look-Up Table 3 Signals bit position. */ +#define PORTMUX_LUT4_bm 0x10 /* CCL Look-Up Table 4 Signals bit mask. */ +#define PORTMUX_LUT4_bp 4 /* CCL Look-Up Table 4 Signals bit position. */ +#define PORTMUX_LUT5_bm 0x20 /* CCL Look-Up Table 5 Signals bit mask. */ +#define PORTMUX_LUT5_bp 5 /* CCL Look-Up Table 5 Signals bit position. */ + +/* PORTMUX.USARTROUTEA bit masks and bit positions */ +#define PORTMUX_USART0_gm 0x03 /* USART0 Signals group mask. */ +#define PORTMUX_USART0_gp 0 /* USART0 Signals group position. */ +#define PORTMUX_USART00_bm (1<<0) /* USART0 Signals bit 0 mask. */ +#define PORTMUX_USART00_bp 0 /* USART0 Signals bit 0 position. */ +#define PORTMUX_USART01_bm (1<<1) /* USART0 Signals bit 1 mask. */ +#define PORTMUX_USART01_bp 1 /* USART0 Signals bit 1 position. */ +#define PORTMUX_USART1_gm 0x0C /* USART1 Signals group mask. */ +#define PORTMUX_USART1_gp 2 /* USART1 Signals group position. */ +#define PORTMUX_USART10_bm (1<<2) /* USART1 Signals bit 0 mask. */ +#define PORTMUX_USART10_bp 2 /* USART1 Signals bit 0 position. */ +#define PORTMUX_USART11_bm (1<<3) /* USART1 Signals bit 1 mask. */ +#define PORTMUX_USART11_bp 3 /* USART1 Signals bit 1 position. */ +#define PORTMUX_USART2_gm 0x30 /* USART2 Signals group mask. */ +#define PORTMUX_USART2_gp 4 /* USART2 Signals group position. */ +#define PORTMUX_USART20_bm (1<<4) /* USART2 Signals bit 0 mask. */ +#define PORTMUX_USART20_bp 4 /* USART2 Signals bit 0 position. */ +#define PORTMUX_USART21_bm (1<<5) /* USART2 Signals bit 1 mask. */ +#define PORTMUX_USART21_bp 5 /* USART2 Signals bit 1 position. */ +#define PORTMUX_USART3_gm 0xC0 /* USART3 Signals group mask. */ +#define PORTMUX_USART3_gp 6 /* USART3 Signals group position. */ +#define PORTMUX_USART30_bm (1<<6) /* USART3 Signals bit 0 mask. */ +#define PORTMUX_USART30_bp 6 /* USART3 Signals bit 0 position. */ +#define PORTMUX_USART31_bm (1<<7) /* USART3 Signals bit 1 mask. */ +#define PORTMUX_USART31_bp 7 /* USART3 Signals bit 1 position. */ + +/* PORTMUX.USARTROUTEB bit masks and bit positions */ +#define PORTMUX_USART4_gm 0x03 /* USART4 Signals group mask. */ +#define PORTMUX_USART4_gp 0 /* USART4 Signals group position. */ +#define PORTMUX_USART40_bm (1<<0) /* USART4 Signals bit 0 mask. */ +#define PORTMUX_USART40_bp 0 /* USART4 Signals bit 0 position. */ +#define PORTMUX_USART41_bm (1<<1) /* USART4 Signals bit 1 mask. */ +#define PORTMUX_USART41_bp 1 /* USART4 Signals bit 1 position. */ + +/* PORTMUX.SPIROUTEA bit masks and bit positions */ +#define PORTMUX_SPI0_gm 0x03 /* SPI0 Signals group mask. */ +#define PORTMUX_SPI0_gp 0 /* SPI0 Signals group position. */ +#define PORTMUX_SPI00_bm (1<<0) /* SPI0 Signals bit 0 mask. */ +#define PORTMUX_SPI00_bp 0 /* SPI0 Signals bit 0 position. */ +#define PORTMUX_SPI01_bm (1<<1) /* SPI0 Signals bit 1 mask. */ +#define PORTMUX_SPI01_bp 1 /* SPI0 Signals bit 1 position. */ +#define PORTMUX_SPI1_gm 0x0C /* SPI1 Signals group mask. */ +#define PORTMUX_SPI1_gp 2 /* SPI1 Signals group position. */ +#define PORTMUX_SPI10_bm (1<<2) /* SPI1 Signals bit 0 mask. */ +#define PORTMUX_SPI10_bp 2 /* SPI1 Signals bit 0 position. */ +#define PORTMUX_SPI11_bm (1<<3) /* SPI1 Signals bit 1 mask. */ +#define PORTMUX_SPI11_bp 3 /* SPI1 Signals bit 1 position. */ + +/* PORTMUX.TWIROUTEA bit masks and bit positions */ +#define PORTMUX_TWI0_gm 0x03 /* TWI0 Signals group mask. */ +#define PORTMUX_TWI0_gp 0 /* TWI0 Signals group position. */ +#define PORTMUX_TWI00_bm (1<<0) /* TWI0 Signals bit 0 mask. */ +#define PORTMUX_TWI00_bp 0 /* TWI0 Signals bit 0 position. */ +#define PORTMUX_TWI01_bm (1<<1) /* TWI0 Signals bit 1 mask. */ +#define PORTMUX_TWI01_bp 1 /* TWI0 Signals bit 1 position. */ +#define PORTMUX_TWI1_gm 0x0C /* TWI1 Signals group mask. */ +#define PORTMUX_TWI1_gp 2 /* TWI1 Signals group position. */ +#define PORTMUX_TWI10_bm (1<<2) /* TWI1 Signals bit 0 mask. */ +#define PORTMUX_TWI10_bp 2 /* TWI1 Signals bit 0 position. */ +#define PORTMUX_TWI11_bm (1<<3) /* TWI1 Signals bit 1 mask. */ +#define PORTMUX_TWI11_bp 3 /* TWI1 Signals bit 1 position. */ + +/* PORTMUX.TCAROUTEA bit masks and bit positions */ +#define PORTMUX_TCA0_gm 0x07 /* TCA0 Signals group mask. */ +#define PORTMUX_TCA0_gp 0 /* TCA0 Signals group position. */ +#define PORTMUX_TCA00_bm (1<<0) /* TCA0 Signals bit 0 mask. */ +#define PORTMUX_TCA00_bp 0 /* TCA0 Signals bit 0 position. */ +#define PORTMUX_TCA01_bm (1<<1) /* TCA0 Signals bit 1 mask. */ +#define PORTMUX_TCA01_bp 1 /* TCA0 Signals bit 1 position. */ +#define PORTMUX_TCA02_bm (1<<2) /* TCA0 Signals bit 2 mask. */ +#define PORTMUX_TCA02_bp 2 /* TCA0 Signals bit 2 position. */ +#define PORTMUX_TCA1_gm 0x38 /* TCA1 Signals group mask. */ +#define PORTMUX_TCA1_gp 3 /* TCA1 Signals group position. */ +#define PORTMUX_TCA10_bm (1<<3) /* TCA1 Signals bit 0 mask. */ +#define PORTMUX_TCA10_bp 3 /* TCA1 Signals bit 0 position. */ +#define PORTMUX_TCA11_bm (1<<4) /* TCA1 Signals bit 1 mask. */ +#define PORTMUX_TCA11_bp 4 /* TCA1 Signals bit 1 position. */ +#define PORTMUX_TCA12_bm (1<<5) /* TCA1 Signals bit 2 mask. */ +#define PORTMUX_TCA12_bp 5 /* TCA1 Signals bit 2 position. */ + +/* PORTMUX.TCBROUTEA bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* TCB0 Output bit mask. */ +#define PORTMUX_TCB0_bp 0 /* TCB0 Output bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* TCB1 Output bit mask. */ +#define PORTMUX_TCB1_bp 1 /* TCB1 Output bit position. */ +#define PORTMUX_TCB2_bm 0x04 /* TCB2 Output bit mask. */ +#define PORTMUX_TCB2_bp 2 /* TCB2 Output bit position. */ +#define PORTMUX_TCB3_bm 0x08 /* TCB3 Output bit mask. */ +#define PORTMUX_TCB3_bp 3 /* TCB3 Output bit position. */ + +/* PORTMUX.TCDROUTEA bit masks and bit positions */ +#define PORTMUX_TCD0_gm 0x07 /* TCD0 Signals group mask. */ +#define PORTMUX_TCD0_gp 0 /* TCD0 Signals group position. */ +#define PORTMUX_TCD00_bm (1<<0) /* TCD0 Signals bit 0 mask. */ +#define PORTMUX_TCD00_bp 0 /* TCD0 Signals bit 0 position. */ +#define PORTMUX_TCD01_bm (1<<1) /* TCD0 Signals bit 1 mask. */ +#define PORTMUX_TCD01_bp 1 /* TCD0 Signals bit 1 position. */ +#define PORTMUX_TCD02_bm (1<<2) /* TCD0 Signals bit 2 mask. */ +#define PORTMUX_TCD02_bp 2 /* TCD0 Signals bit 2 position. */ + +/* PORTMUX.ACROUTEA bit masks and bit positions */ +#define PORTMUX_AC0_bm 0x01 /* Analog Comparator 0 Output bit mask. */ +#define PORTMUX_AC0_bp 0 /* Analog Comparator 0 Output bit position. */ +#define PORTMUX_AC1_bm 0x02 /* Analog Comparator 1 Output bit mask. */ +#define PORTMUX_AC1_bp 1 /* Analog Comparator 1 Output bit position. */ +#define PORTMUX_AC2_bm 0x04 /* Analog Comparator 2 Output bit mask. */ +#define PORTMUX_AC2_bp 2 /* Analog Comparator 2 Output bit position. */ + +/* PORTMUX.ZCDROUTEA bit masks and bit positions */ +#define PORTMUX_ZCD0_bm 0x01 /* Zero Cross Detector 0 Output bit mask. */ +#define PORTMUX_ZCD0_bp 0 /* Zero Cross Detector 0 Output bit position. */ +#define PORTMUX_ZCD1_bm 0x02 /* Zero Cross Detector 1 Output bit mask. */ +#define PORTMUX_ZCD1_bp 1 /* Zero Cross Detector 1 Output bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRST_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRST_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_CORREN_bm 0x04 /* Correction enable bit mask. */ +#define RTC_CORREN_bp 2 /* Correction enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_ERROR_gm 0x7F /* Error Correction Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Correction Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Correction Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Correction Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Correction Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Correction Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Correction Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Correction Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Correction Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Correction Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Correction Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Correction Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Correction Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Correction Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Correction Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Correction Value bit 6 position. */ +#define RTC_SIGN_bm 0x80 /* Error Correction Sign Bit bit mask. */ +#define RTC_SIGN_bp 7 /* Error Correction Sign Bit bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + +/* SIGROW - Signature row */ +/* SIGROW.TEMPSENSE0 bit masks and bit positions */ +#define SIGROW_TEMPSENSE0_gm 0xFFFF /* Temperature Calibration 0 group mask. */ +#define SIGROW_TEMPSENSE0_gp 0 /* Temperature Calibration 0 group position. */ +#define SIGROW_TEMPSENSE00_bm (1<<0) /* Temperature Calibration 0 bit 0 mask. */ +#define SIGROW_TEMPSENSE00_bp 0 /* Temperature Calibration 0 bit 0 position. */ +#define SIGROW_TEMPSENSE01_bm (1<<1) /* Temperature Calibration 0 bit 1 mask. */ +#define SIGROW_TEMPSENSE01_bp 1 /* Temperature Calibration 0 bit 1 position. */ +#define SIGROW_TEMPSENSE02_bm (1<<2) /* Temperature Calibration 0 bit 2 mask. */ +#define SIGROW_TEMPSENSE02_bp 2 /* Temperature Calibration 0 bit 2 position. */ +#define SIGROW_TEMPSENSE03_bm (1<<3) /* Temperature Calibration 0 bit 3 mask. */ +#define SIGROW_TEMPSENSE03_bp 3 /* Temperature Calibration 0 bit 3 position. */ +#define SIGROW_TEMPSENSE04_bm (1<<4) /* Temperature Calibration 0 bit 4 mask. */ +#define SIGROW_TEMPSENSE04_bp 4 /* Temperature Calibration 0 bit 4 position. */ +#define SIGROW_TEMPSENSE05_bm (1<<5) /* Temperature Calibration 0 bit 5 mask. */ +#define SIGROW_TEMPSENSE05_bp 5 /* Temperature Calibration 0 bit 5 position. */ +#define SIGROW_TEMPSENSE06_bm (1<<6) /* Temperature Calibration 0 bit 6 mask. */ +#define SIGROW_TEMPSENSE06_bp 6 /* Temperature Calibration 0 bit 6 position. */ +#define SIGROW_TEMPSENSE07_bm (1<<7) /* Temperature Calibration 0 bit 7 mask. */ +#define SIGROW_TEMPSENSE07_bp 7 /* Temperature Calibration 0 bit 7 position. */ +#define SIGROW_TEMPSENSE08_bm (1<<8) /* Temperature Calibration 0 bit 8 mask. */ +#define SIGROW_TEMPSENSE08_bp 8 /* Temperature Calibration 0 bit 8 position. */ +#define SIGROW_TEMPSENSE09_bm (1<<9) /* Temperature Calibration 0 bit 9 mask. */ +#define SIGROW_TEMPSENSE09_bp 9 /* Temperature Calibration 0 bit 9 position. */ +#define SIGROW_TEMPSENSE010_bm (1<<10) /* Temperature Calibration 0 bit 10 mask. */ +#define SIGROW_TEMPSENSE010_bp 10 /* Temperature Calibration 0 bit 10 position. */ +#define SIGROW_TEMPSENSE011_bm (1<<11) /* Temperature Calibration 0 bit 11 mask. */ +#define SIGROW_TEMPSENSE011_bp 11 /* Temperature Calibration 0 bit 11 position. */ +#define SIGROW_TEMPSENSE012_bm (1<<12) /* Temperature Calibration 0 bit 12 mask. */ +#define SIGROW_TEMPSENSE012_bp 12 /* Temperature Calibration 0 bit 12 position. */ +#define SIGROW_TEMPSENSE013_bm (1<<13) /* Temperature Calibration 0 bit 13 mask. */ +#define SIGROW_TEMPSENSE013_bp 13 /* Temperature Calibration 0 bit 13 position. */ +#define SIGROW_TEMPSENSE014_bm (1<<14) /* Temperature Calibration 0 bit 14 mask. */ +#define SIGROW_TEMPSENSE014_bp 14 /* Temperature Calibration 0 bit 14 position. */ +#define SIGROW_TEMPSENSE015_bm (1<<15) /* Temperature Calibration 0 bit 15 mask. */ +#define SIGROW_TEMPSENSE015_bp 15 /* Temperature Calibration 0 bit 15 position. */ + +/* SIGROW.TEMPSENSE1 bit masks and bit positions */ +#define SIGROW_TEMPSENSE1_gm 0xFFFF /* Temperature Calibration 1 group mask. */ +#define SIGROW_TEMPSENSE1_gp 0 /* Temperature Calibration 1 group position. */ +#define SIGROW_TEMPSENSE10_bm (1<<0) /* Temperature Calibration 1 bit 0 mask. */ +#define SIGROW_TEMPSENSE10_bp 0 /* Temperature Calibration 1 bit 0 position. */ +#define SIGROW_TEMPSENSE11_bm (1<<1) /* Temperature Calibration 1 bit 1 mask. */ +#define SIGROW_TEMPSENSE11_bp 1 /* Temperature Calibration 1 bit 1 position. */ +#define SIGROW_TEMPSENSE12_bm (1<<2) /* Temperature Calibration 1 bit 2 mask. */ +#define SIGROW_TEMPSENSE12_bp 2 /* Temperature Calibration 1 bit 2 position. */ +#define SIGROW_TEMPSENSE13_bm (1<<3) /* Temperature Calibration 1 bit 3 mask. */ +#define SIGROW_TEMPSENSE13_bp 3 /* Temperature Calibration 1 bit 3 position. */ +#define SIGROW_TEMPSENSE14_bm (1<<4) /* Temperature Calibration 1 bit 4 mask. */ +#define SIGROW_TEMPSENSE14_bp 4 /* Temperature Calibration 1 bit 4 position. */ +#define SIGROW_TEMPSENSE15_bm (1<<5) /* Temperature Calibration 1 bit 5 mask. */ +#define SIGROW_TEMPSENSE15_bp 5 /* Temperature Calibration 1 bit 5 position. */ +#define SIGROW_TEMPSENSE16_bm (1<<6) /* Temperature Calibration 1 bit 6 mask. */ +#define SIGROW_TEMPSENSE16_bp 6 /* Temperature Calibration 1 bit 6 position. */ +#define SIGROW_TEMPSENSE17_bm (1<<7) /* Temperature Calibration 1 bit 7 mask. */ +#define SIGROW_TEMPSENSE17_bp 7 /* Temperature Calibration 1 bit 7 position. */ +#define SIGROW_TEMPSENSE18_bm (1<<8) /* Temperature Calibration 1 bit 8 mask. */ +#define SIGROW_TEMPSENSE18_bp 8 /* Temperature Calibration 1 bit 8 position. */ +#define SIGROW_TEMPSENSE19_bm (1<<9) /* Temperature Calibration 1 bit 9 mask. */ +#define SIGROW_TEMPSENSE19_bp 9 /* Temperature Calibration 1 bit 9 position. */ +#define SIGROW_TEMPSENSE110_bm (1<<10) /* Temperature Calibration 1 bit 10 mask. */ +#define SIGROW_TEMPSENSE110_bp 10 /* Temperature Calibration 1 bit 10 position. */ +#define SIGROW_TEMPSENSE111_bm (1<<11) /* Temperature Calibration 1 bit 11 mask. */ +#define SIGROW_TEMPSENSE111_bp 11 /* Temperature Calibration 1 bit 11 position. */ +#define SIGROW_TEMPSENSE112_bm (1<<12) /* Temperature Calibration 1 bit 12 mask. */ +#define SIGROW_TEMPSENSE112_bp 12 /* Temperature Calibration 1 bit 12 position. */ +#define SIGROW_TEMPSENSE113_bm (1<<13) /* Temperature Calibration 1 bit 13 mask. */ +#define SIGROW_TEMPSENSE113_bp 13 /* Temperature Calibration 1 bit 13 position. */ +#define SIGROW_TEMPSENSE114_bm (1<<14) /* Temperature Calibration 1 bit 14 mask. */ +#define SIGROW_TEMPSENSE114_bp 14 /* Temperature Calibration 1 bit 14 position. */ +#define SIGROW_TEMPSENSE115_bm (1<<15) /* Temperature Calibration 1 bit 15 mask. */ +#define SIGROW_TEMPSENSE115_bp 15 /* Temperature Calibration 1 bit 15 position. */ + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SLPCTRL.VREGCTRL bit masks and bit positions */ +#define SLPCTRL_PMODE_gm 0x07 /* Performance Mode group mask. */ +#define SLPCTRL_PMODE_gp 0 /* Performance Mode group position. */ +#define SLPCTRL_PMODE0_bm (1<<0) /* Performance Mode bit 0 mask. */ +#define SLPCTRL_PMODE0_bp 0 /* Performance Mode bit 0 position. */ +#define SLPCTRL_PMODE1_bm (1<<1) /* Performance Mode bit 1 mask. */ +#define SLPCTRL_PMODE1_bp 1 /* Performance Mode bit 1 position. */ +#define SLPCTRL_PMODE2_bm (1<<2) /* Performance Mode bit 2 mask. */ +#define SLPCTRL_PMODE2_bp 2 /* Performance Mode bit 2 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Mode Wait for Receive bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Mode Wait for Receive bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.OCDMSTATUS bit masks and bit positions */ +#define SYSCFG_OCDMR_bm 0x01 /* OCD Message Read bit mask. */ +#define SYSCFG_OCDMR_bp 0 /* OCD Message Read bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ +#define TCA_SINGLE_RUNSTDBY_bm 0x80 /* Run in Standby bit mask. */ +#define TCA_SINGLE_RUNSTDBY_bp 7 /* Run in Standby bit position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTAEI_bm 0x01 /* Count on Event Input A bit mask. */ +#define TCA_SINGLE_CNTAEI_bp 0 /* Count on Event Input A bit position. */ +#define TCA_SINGLE_EVACTA_gm 0x0E /* Event Action A group mask. */ +#define TCA_SINGLE_EVACTA_gp 1 /* Event Action A group position. */ +#define TCA_SINGLE_EVACTA0_bm (1<<1) /* Event Action A bit 0 mask. */ +#define TCA_SINGLE_EVACTA0_bp 1 /* Event Action A bit 0 position. */ +#define TCA_SINGLE_EVACTA1_bm (1<<2) /* Event Action A bit 1 mask. */ +#define TCA_SINGLE_EVACTA1_bp 2 /* Event Action A bit 1 position. */ +#define TCA_SINGLE_EVACTA2_bm (1<<3) /* Event Action A bit 2 mask. */ +#define TCA_SINGLE_EVACTA2_bp 3 /* Event Action A bit 2 position. */ +#define TCA_SINGLE_CNTBEI_bm 0x10 /* Count on Event Input B bit mask. */ +#define TCA_SINGLE_CNTBEI_bp 4 /* Count on Event Input B bit position. */ +#define TCA_SINGLE_EVACTB_gm 0xE0 /* Event Action B group mask. */ +#define TCA_SINGLE_EVACTB_gp 5 /* Event Action B group position. */ +#define TCA_SINGLE_EVACTB0_bm (1<<5) /* Event Action B bit 0 mask. */ +#define TCA_SINGLE_EVACTB0_bp 5 /* Event Action B bit 0 position. */ +#define TCA_SINGLE_EVACTB1_bm (1<<6) /* Event Action B bit 1 mask. */ +#define TCA_SINGLE_EVACTB1_bp 6 /* Event Action B bit 1 position. */ +#define TCA_SINGLE_EVACTB2_bm (1<<7) /* Event Action B bit 2 mask. */ +#define TCA_SINGLE_EVACTB2_bp 7 /* Event Action B bit 2 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ +#define TCA_SPLIT_RUNSTDBY_bm 0x80 /* Run in Standby bit mask. */ +#define TCA_SPLIT_RUNSTDBY_bp 7 /* Run in Standby bit position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TCA_SPLIT_CMDEN_gp 0 /* Command Enable group position. */ +#define TCA_SPLIT_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TCA_SPLIT_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TCA_SPLIT_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TCA_SPLIT_CMDEN1_bp 1 /* Command Enable bit 1 position. */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x0E /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_CLKSEL2_bm (1<<3) /* Clock Select bit 2 mask. */ +#define TCB_CLKSEL2_bp 3 /* Clock Select bit 2 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_CASCADE_bm 0x20 /* Cascade two timers bit mask. */ +#define TCB_CASCADE_bp 5 /* Cascade two timers bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ +#define TCB_OVF_bm 0x02 /* Overflow bit mask. */ +#define TCB_OVF_bp 1 /* Overflow bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ +/* TCB_OVF is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Synchronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Synchronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Synchronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Synchronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Synchronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Synchronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ +#define TWI_INPUTLVL_bm 0x40 /* Input Voltage Transition Level bit mask. */ +#define TWI_INPUTLVL_bp 6 /* Input Voltage Transition Level bit position. */ + +/* TWI.DUALCTRL bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Dual Control Enable bit mask. */ +#define TWI_ENABLE_bp 0 /* Dual Control Enable bit position. */ +/* TWI_FMPEN is already defined. */ +/* TWI_SDAHOLD is already defined. */ +/* TWI_INPUTLVL is already defined. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.CTRLD bit masks and bit positions */ +#define USART_ABW_gm 0xC0 /* Auto Baud Window group mask. */ +#define USART_ABW_gp 6 /* Auto Baud Window group position. */ +#define USART_ABW0_bm (1<<6) /* Auto Baud Window bit 0 mask. */ +#define USART_ABW0_bp 6 /* Auto Baud Window bit 0 position. */ +#define USART_ABW1_bm (1<<7) /* Auto Baud Window bit 1 mask. */ +#define USART_ABW1_bp 7 /* Auto Baud Window bit 1 position. */ + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.ADC0REF bit masks and bit positions */ +#define VREF_REFSEL_gm 0x07 /* Reference select group mask. */ +#define VREF_REFSEL_gp 0 /* Reference select group position. */ +#define VREF_REFSEL0_bm (1<<0) /* Reference select bit 0 mask. */ +#define VREF_REFSEL0_bp 0 /* Reference select bit 0 position. */ +#define VREF_REFSEL1_bm (1<<1) /* Reference select bit 1 mask. */ +#define VREF_REFSEL1_bp 1 /* Reference select bit 1 position. */ +#define VREF_REFSEL2_bm (1<<2) /* Reference select bit 2 mask. */ +#define VREF_REFSEL2_bp 2 /* Reference select bit 2 position. */ +#define VREF_ALWAYSON_bm 0x80 /* Always on bit mask. */ +#define VREF_ALWAYSON_bp 7 /* Always on bit position. */ + +/* VREF.DAC0REF bit masks and bit positions */ +/* VREF_REFSEL is already defined. */ +/* VREF_ALWAYSON is already defined. */ + +/* VREF.ACREF bit masks and bit positions */ +/* VREF_REFSEL is already defined. */ +/* VREF_ALWAYSON is already defined. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + +/* ZCD - Zero Cross Detect */ +/* ZCD.CTRLA bit masks and bit positions */ +#define ZCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define ZCD_ENABLE_bp 0 /* Enable bit position. */ +#define ZCD_INVERT_bm 0x08 /* Invert signal from pin bit mask. */ +#define ZCD_INVERT_bp 3 /* Invert signal from pin bit position. */ +#define ZCD_OUTEN_bm 0x40 /* Output Pad Enable bit mask. */ +#define ZCD_OUTEN_bp 6 /* Output Pad Enable bit position. */ +#define ZCD_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define ZCD_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* ZCD.INTCTRL bit masks and bit positions */ +#define ZCD_INTMODE_gm 0x03 /* Interrupt Mode group mask. */ +#define ZCD_INTMODE_gp 0 /* Interrupt Mode group position. */ +#define ZCD_INTMODE0_bm (1<<0) /* Interrupt Mode bit 0 mask. */ +#define ZCD_INTMODE0_bp 0 /* Interrupt Mode bit 0 position. */ +#define ZCD_INTMODE1_bm (1<<1) /* Interrupt Mode bit 1 mask. */ +#define ZCD_INTMODE1_bp 1 /* Interrupt Mode bit 1 position. */ + +/* ZCD.STATUS bit masks and bit positions */ +#define ZCD_CROSSIF_bm 0x01 /* ZCD Interrupt Flag bit mask. */ +#define ZCD_CROSSIF_bp 0 /* ZCD Interrupt Flag bit position. */ +#define ZCD_STATE_bm 0x10 /* ZCD State bit mask. */ +#define ZCD_STATE_bp 4 /* ZCD State bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* NMI interrupt vectors */ +#define NMI_vect_num 1 +#define NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 3 +#define RTC_CNT_vect _VECTOR(3) /* */ +#define RTC_PIT_vect_num 4 +#define RTC_PIT_vect _VECTOR(4) /* */ + +/* CCL interrupt vectors */ +#define CCL_CCL_vect_num 5 +#define CCL_CCL_vect _VECTOR(5) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 6 +#define PORTA_PORT_vect _VECTOR(6) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 7 +#define TCA0_LUNF_vect _VECTOR(7) /* */ +#define TCA0_OVF_vect_num 7 +#define TCA0_OVF_vect _VECTOR(7) /* */ +#define TCA0_HUNF_vect_num 8 +#define TCA0_HUNF_vect _VECTOR(8) /* */ +#define TCA0_CMP0_vect_num 9 +#define TCA0_CMP0_vect _VECTOR(9) /* */ +#define TCA0_LCMP0_vect_num 9 +#define TCA0_LCMP0_vect _VECTOR(9) /* */ +#define TCA0_CMP1_vect_num 10 +#define TCA0_CMP1_vect _VECTOR(10) /* */ +#define TCA0_LCMP1_vect_num 10 +#define TCA0_LCMP1_vect _VECTOR(10) /* */ +#define TCA0_CMP2_vect_num 11 +#define TCA0_CMP2_vect _VECTOR(11) /* */ +#define TCA0_LCMP2_vect_num 11 +#define TCA0_LCMP2_vect _VECTOR(11) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 12 +#define TCB0_INT_vect _VECTOR(12) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 13 +#define TCB1_INT_vect _VECTOR(13) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 14 +#define TCD0_OVF_vect _VECTOR(14) /* */ +#define TCD0_TRIG_vect_num 15 +#define TCD0_TRIG_vect _VECTOR(15) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 16 +#define TWI0_TWIS_vect _VECTOR(16) /* */ +#define TWI0_TWIM_vect_num 17 +#define TWI0_TWIM_vect _VECTOR(17) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 18 +#define SPI0_INT_vect _VECTOR(18) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 19 +#define USART0_RXC_vect _VECTOR(19) /* */ +#define USART0_DRE_vect_num 20 +#define USART0_DRE_vect _VECTOR(20) /* */ +#define USART0_TXC_vect_num 21 +#define USART0_TXC_vect _VECTOR(21) /* */ + +/* PORTD interrupt vectors */ +#define PORTD_PORT_vect_num 22 +#define PORTD_PORT_vect _VECTOR(22) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 23 +#define AC0_AC_vect _VECTOR(23) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 24 +#define ADC0_RESRDY_vect _VECTOR(24) /* */ +#define ADC0_WCMP_vect_num 25 +#define ADC0_WCMP_vect _VECTOR(25) /* */ + +/* ZCD0 interrupt vectors */ +#define ZCD0_ZCD_vect_num 26 +#define ZCD0_ZCD_vect _VECTOR(26) /* */ + +/* PTC interrupt vectors */ +#define PTC_PTC_vect_num 27 +#define PTC_PTC_vect _VECTOR(27) /* */ + +/* AC1 interrupt vectors */ +#define AC1_AC_vect_num 28 +#define AC1_AC_vect _VECTOR(28) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 29 +#define PORTC_PORT_vect _VECTOR(29) /* */ + +/* TCB2 interrupt vectors */ +#define TCB2_INT_vect_num 30 +#define TCB2_INT_vect _VECTOR(30) /* */ + +/* USART1 interrupt vectors */ +#define USART1_RXC_vect_num 31 +#define USART1_RXC_vect _VECTOR(31) /* */ +#define USART1_DRE_vect_num 32 +#define USART1_DRE_vect _VECTOR(32) /* */ +#define USART1_TXC_vect_num 33 +#define USART1_TXC_vect _VECTOR(33) /* */ + +/* PORTF interrupt vectors */ +#define PORTF_PORT_vect_num 34 +#define PORTF_PORT_vect _VECTOR(34) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 35 +#define NVMCTRL_EE_vect _VECTOR(35) /* */ + +/* SPI1 interrupt vectors */ +#define SPI1_INT_vect_num 36 +#define SPI1_INT_vect _VECTOR(36) /* */ + +/* USART2 interrupt vectors */ +#define USART2_RXC_vect_num 37 +#define USART2_RXC_vect _VECTOR(37) /* */ +#define USART2_DRE_vect_num 38 +#define USART2_DRE_vect _VECTOR(38) /* */ +#define USART2_TXC_vect_num 39 +#define USART2_TXC_vect _VECTOR(39) /* */ + +/* AC2 interrupt vectors */ +#define AC2_AC_vect_num 40 +#define AC2_AC_vect _VECTOR(40) /* */ + +/* TCB3 interrupt vectors */ +#define TCB3_INT_vect_num 41 +#define TCB3_INT_vect _VECTOR(41) /* */ + +/* TWI1 interrupt vectors */ +#define TWI1_TWIS_vect_num 42 +#define TWI1_TWIS_vect _VECTOR(42) /* */ +#define TWI1_TWIM_vect_num 43 +#define TWI1_TWIM_vect _VECTOR(43) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 44 +#define PORTB_PORT_vect _VECTOR(44) /* */ + +/* PORTE interrupt vectors */ +#define PORTE_PORT_vect_num 45 +#define PORTE_PORT_vect _VECTOR(45) /* */ + +/* TCA1 interrupt vectors */ +#define TCA1_LUNF_vect_num 46 +#define TCA1_LUNF_vect _VECTOR(46) /* */ +#define TCA1_OVF_vect_num 46 +#define TCA1_OVF_vect _VECTOR(46) /* */ +#define TCA1_HUNF_vect_num 47 +#define TCA1_HUNF_vect _VECTOR(47) /* */ +#define TCA1_CMP0_vect_num 48 +#define TCA1_CMP0_vect _VECTOR(48) /* */ +#define TCA1_LCMP0_vect_num 48 +#define TCA1_LCMP0_vect _VECTOR(48) /* */ +#define TCA1_CMP1_vect_num 49 +#define TCA1_CMP1_vect _VECTOR(49) /* */ +#define TCA1_LCMP1_vect_num 49 +#define TCA1_LCMP1_vect _VECTOR(49) /* */ +#define TCA1_CMP2_vect_num 50 +#define TCA1_CMP2_vect _VECTOR(50) /* */ +#define TCA1_LCMP2_vect_num 50 +#define TCA1_LCMP2_vect _VECTOR(50) /* */ + +/* ZCD1 interrupt vectors */ +#define ZCD1_ZCD_vect_num 51 +#define ZCD1_ZCD_vect _VECTOR(51) /* */ + +/* USART3 interrupt vectors */ +#define USART3_RXC_vect_num 52 +#define USART3_RXC_vect _VECTOR(52) /* */ +#define USART3_DRE_vect_num 53 +#define USART3_DRE_vect _VECTOR(53) /* */ +#define USART3_TXC_vect_num 54 +#define USART3_TXC_vect _VECTOR(54) /* */ + +/* USART4 interrupt vectors */ +#define USART4_RXC_vect_num 55 +#define USART4_RXC_vect _VECTOR(55) /* */ +#define USART4_DRE_vect_num 56 +#define USART4_DRE_vect _VECTOR(56) /* */ +#define USART4_TXC_vect_num 57 +#define USART4_TXC_vect _VECTOR(57) /* */ + +/* PORTG interrupt vectors */ +#define PORTG_PORT_vect_num 58 +#define PORTG_PORT_vect _VECTOR(58) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (59 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (65536) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (65536U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (512) +# define EEPROM_PAGE_SIZE (1) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (512U) +# define EEPROM_PAGE_SIZE (1U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1050) +# define FUSES_SIZE (16) +# define FUSES_PAGE_SIZE (1) +#else +# define FUSES_START (0x1050U) +# define FUSES_SIZE (16U) +# define FUSES_PAGE_SIZE (1U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x4000) +# define INTERNAL_SRAM_SIZE (16384) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x4000U) +# define INTERNAL_SRAM_SIZE (16384U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4159) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4159U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x1040) +# define LOCKBITS_SIZE (4) +# define LOCKBITS_PAGE_SIZE (1) +#else +# define LOCKBITS_START (0x1040U) +# define LOCKBITS_SIZE (4U) +# define LOCKBITS_PAGE_SIZE (1U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (32768) +# define MAPPED_PROGMEM_PAGE_SIZE (512) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (32768U) +# define MAPPED_PROGMEM_PAGE_SIZE (512U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (125) +# define PROD_SIGNATURES_PAGE_SIZE (128) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (125U) +# define PROD_SIGNATURES_PAGE_SIZE (128U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (128) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (128U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1080) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1080U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (131072) +# define PROGMEM_PAGE_SIZE (512) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (131072U) +# define PROGMEM_PAGE_SIZE (512U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 16 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_CLKSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_CLKSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_CLKSEL2 (unsigned char)_BV(2) /* Frequency Select Bit 2 */ +#define FUSE2_DEFAULT (0x0) +#define FUSE_OSCCFG_DEFAULT (0x0) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSEL (unsigned char)_BV(5) /* CRC Select */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc0) +#define FUSE_SYSCFG0_DEFAULT (0xc0) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x0) +#define FUSE_SYSCFG1_DEFAULT (0x0) + +/* Fuse Byte 7 (CODESIZE) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_CODESIZE_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTSIZE) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTSIZE_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_KEY_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0x5cc5c55c) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x08 + + +#endif /* #ifdef _AVR_AVR128DA48_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/ioavr128da64.h b/hardware/tools/avr/avr/include/avr/ioavr128da64.h new file mode 100644 index 0000000000000000000000000000000000000000..1b96f6f0701a59b5a237729d2478bf6f33c663a7 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/ioavr128da64.h @@ -0,0 +1,7587 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioavr128da64.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_AVR128DA64_H_INCLUDED +#define _AVR_AVR128DA64_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPZ _SFR_MEM8(0x003B) /* Extended Z-pointer Register */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t MUXCTRL; /* Mux Control A */ + register8_t reserved_1[2]; + register8_t DACREF; /* DAC Voltage Reference */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NONE_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_MEDIUM_gc = (0x02<<1), /* Medium hysteresis */ + AC_HYSMODE_LARGE_gc = (0x03<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* AC Output Initial Value select */ +typedef enum AC_INITVAL_enum +{ + AC_INITVAL_LOW_gc = (0x00<<6), /* Output initialized to 0 */ + AC_INITVAL_HIGH_gc = (0x01<<6), /* Output initialized to 1 */ +} AC_INITVAL_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_ABOVE_gc = (0x00<<4), /* Entering window state above */ + AC_INTMODE_INSIDE_gc = (0x01<<4), /* Entering window state inside */ + AC_INTMODE_BELOW_gc = (0x02<<4), /* Entering window state below */ + AC_INTMODE_OUTSIDE_gc = (0x03<<4), /* Entering window state above or below */ +} AC_INTMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_AINN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_AINN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_AINN2_gc = (0x02<<0), /* Negative Pin 2 */ + AC_MUXNEG_DACREF_gc = (0x03<<0), /* DAC Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_AINP0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_AINP1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_AINP2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_AINP3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* Power profile select */ +typedef enum AC_POWER_enum +{ + AC_POWER_PROFILE0_gc = (0x00<<3), /* Power profile 0, lowest consumption and highest response time. */ + AC_POWER_PROFILE1_gc = (0x01<<3), /* Power profile 1 */ + AC_POWER_PROFILE2_gc = (0x02<<3), /* Power profile 2 */ + AC_POWER_PROFILE3_gc = (0x03<<3), /* Power profile 3 */ +} AC_POWER_t; + +/* Window selection mode select */ +typedef enum AC_WINSEL_enum +{ + AC_WINSEL_DISABLED_gc = (0x00<<0), /* Window function disabled */ + AC_WINSEL_UPSEL1_gc = (0x01<<0), /* Select ACn+1 as upper limit in window compare. */ + AC_WINSEL_UPSEL2_gc = (0x02<<0), /* Select ACn+2 as upper limit in window compare. */ +} AC_WINSEL_t; + +/* Analog Comparator Window State select */ +typedef enum AC_WINSTATE_enum +{ + AC_WINSTATE_ABOVE_gc = (0x00<<6), /* Above window */ + AC_WINSTATE_INSIDE_gc = (0x01<<6), /* Inside window */ + AC_WINSTATE_BELOW_gc = (0x02<<6), /* Below window */ +} AC_WINSTATE_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t reserved_1[2]; + register8_t MUXPOS; /* Positive mux input */ + register8_t MUXNEG; /* Negative mux input */ + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t reserved_2[2]; +} ADC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXNEG_enum +{ + ADC_MUXNEG_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXNEG_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXNEG_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXNEG_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXNEG_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXNEG_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXNEG_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXNEG_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXNEG_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXNEG_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXNEG_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXNEG_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXNEG_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ + ADC_MUXNEG_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ + ADC_MUXNEG_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ + ADC_MUXNEG_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ + ADC_MUXNEG_GND_gc = (0x40<<0), /* Ground */ + ADC_MUXNEG_DAC0_gc = (0x48<<0), /* DAC0 */ +} ADC_MUXNEG_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ + ADC_MUXPOS_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ + ADC_MUXPOS_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ + ADC_MUXPOS_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ + ADC_MUXPOS_AIN16_gc = (0x10<<0), /* ADC input pin 16 */ + ADC_MUXPOS_AIN17_gc = (0x11<<0), /* ADC input pin 17 */ + ADC_MUXPOS_AIN18_gc = (0x12<<0), /* ADC input pin 18 */ + ADC_MUXPOS_AIN19_gc = (0x13<<0), /* ADC input pin 19 */ + ADC_MUXPOS_AIN20_gc = (0x14<<0), /* ADC input pin 20 */ + ADC_MUXPOS_AIN21_gc = (0x15<<0), /* ADC input pin 21 */ + ADC_MUXPOS_GND_gc = (0x40<<0), /* Ground */ + ADC_MUXPOS_TEMPSENSE_gc = (0x42<<0), /* Temperature sensor */ + ADC_MUXPOS_DAC0_gc = (0x48<<0), /* DAC0 */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV12_gc = (0x03<<0), /* CLK_PER divided by 12 */ + ADC_PRESC_DIV16_gc = (0x04<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV20_gc = (0x05<<0), /* CLK_PER divided by 20 */ + ADC_PRESC_DIV24_gc = (0x06<<0), /* CLK_PER divided by 24 */ + ADC_PRESC_DIV28_gc = (0x07<<0), /* CLK_PER divided by 28 */ + ADC_PRESC_DIV32_gc = (0x08<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV48_gc = (0x09<<0), /* CLK_PER divided by 48 */ + ADC_PRESC_DIV64_gc = (0x0A<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV96_gc = (0x0B<<0), /* CLK_PER divided by 96 */ + ADC_PRESC_DIV128_gc = (0x0C<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x0D<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Resolution selection select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_12BIT_gc = (0x00<<2), /* 12-bit mode */ + ADC_RESSEL_10BIT_gc = (0x01<<2), /* 10-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_NONE_gc = (0x00<<0), /* No accumulation */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* 2 results accumulated */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* 4 results accumulated */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* 8 results accumulated */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* 16 results accumulated */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* 32 results accumulated */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* 64 results accumulated */ + ADC_SAMPNUM_ACC128_gc = (0x07<<0), /* 128 results accumulated */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.9 V */ + BOD_LVL_BODLEVEL1_gc = (0x01<<0), /* 2.45 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.7 V */ + BOD_LVL_BODLEVEL3_gc = (0x03<<0), /* 2.85 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_128HZ_gc = (0x00<<4), /* 128Hz sampling frequency */ + BOD_SAMPFREQ_32HZ_gc = (0x01<<4), /* 32Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_FALLING_gc = (0x00<<1), /* VDD falls below VLM threshold */ + BOD_VLMCFG_RISING_gc = (0x01<<1), /* VDD rises above VLM threshold */ + BOD_VLMCFG_BOTH_gc = (0x02<<1), /* VDD crosses VLM threshold */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_OFF_gc = (0x00<<0), /* VLM Disabled */ + BOD_VLMLVL_5ABOVE_gc = (0x01<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x02<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x03<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* Voltage level monitor status select */ +typedef enum BOD_VLMS_enum +{ + BOD_VLMS_ABOVE_gc = (0x00<<0), /* The voltage is above the VLM threshold level */ + BOD_VLMS_BELOW_gc = (0x01<<0), /* The voltage is below the VLM threshold level */ +} BOD_VLMS_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t SEQCTRL1; /* Sequential Control 1 */ + register8_t SEQCTRL2; /* Sequential Control 2 */ + register8_t reserved_1[1]; + register8_t INTCTRL0; /* Interrupt Control 0 */ + register8_t INTCTRL1; /* Interrupt Control 1 */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t LUT2CTRLA; /* LUT Control 2 A */ + register8_t LUT2CTRLB; /* LUT Control 2 B */ + register8_t LUT2CTRLC; /* LUT Control 2 C */ + register8_t TRUTH2; /* Truth 2 */ + register8_t LUT3CTRLA; /* LUT Control 3 A */ + register8_t LUT3CTRLB; /* LUT Control 3 B */ + register8_t LUT3CTRLC; /* LUT Control 3 C */ + register8_t TRUTH3; /* Truth 3 */ + register8_t LUT4CTRLA; /* LUT Control 4 A */ + register8_t LUT4CTRLB; /* LUT Control 4 B */ + register8_t LUT4CTRLC; /* LUT Control 4 C */ + register8_t TRUTH4; /* Truth 4 */ + register8_t LUT5CTRLA; /* LUT Control 5 A */ + register8_t LUT5CTRLB; /* LUT Control 5 B */ + register8_t LUT5CTRLC; /* LUT Control 5 C */ + register8_t TRUTH5; /* Truth 5 */ + register8_t reserved_2[32]; +} CCL_t; + +/* Clock Source Selection select */ +typedef enum CCL_CLKSRC_enum +{ + CCL_CLKSRC_CLKPER_gc = (0x00<<1), /* CLK_PER is clocking the LUT */ + CCL_CLKSRC_IN2_gc = (0x01<<1), /* IN[2] is clocking the LUT */ + CCL_CLKSRC_OSCHF_gc = (0x04<<1), /* Internal high-frequency oscillator before prescaler is clocking LUT */ + CCL_CLKSRC_OSC32K_gc = (0x05<<1), /* Internal 32.768 kHz oscillator */ + CCL_CLKSRC_OSC1K_gc = (0x06<<1), /* Internal 32.768 kHz oscillator divided by 32 */ +} CCL_CLKSRC_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL0_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL0_IN0_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_ZCD0_gc = (0x07<<0), /* ZCD0 OUT input source */ + CCL_INSEL0_USART0_gc = (0x08<<0), /* USART0 TXD input source */ + CCL_INSEL0_SPI0_gc = (0x09<<0), /* SPI0 MOSI input source */ + CCL_INSEL0_TCA0_gc = (0x0A<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCA1_gc = (0x0B<<0), /* TCA1 WO0 input source */ + CCL_INSEL0_TCB0_gc = (0x0C<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCD0_gc = (0x0D<<0), /* TCD0 WOA input source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENTA_gc = (0x03<<4), /* Event input source A */ + CCL_INSEL1_EVENTB_gc = (0x04<<4), /* Event input source B */ + CCL_INSEL1_IN1_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC1_gc = (0x06<<4), /* AC1 OUT input source */ + CCL_INSEL1_ZCD1_gc = (0x07<<4), /* ZCD1 OUT input source */ + CCL_INSEL1_USART1_gc = (0x08<<4), /* USART1 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x09<<4), /* SPI0 MOSI input source */ + CCL_INSEL1_TCA0_gc = (0x0A<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCA1_gc = (0x0B<<4), /* TCA1 WO1 input source */ + CCL_INSEL1_TCB1_gc = (0x0C<<4), /* TCB1 WO input source */ + CCL_INSEL1_TCD0_gc = (0x0D<<4), /* TCD0 WOB input soruce */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL2_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL2_IN2_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC2_gc = (0x06<<0), /* AC2 OUT input source */ + CCL_INSEL2_ZCD2_gc = (0x07<<0), /* ZCD2 OUT input source */ + CCL_INSEL2_USART2_gc = (0x08<<0), /* USART2 TXD input source */ + CCL_INSEL2_SPI0_gc = (0x09<<0), /* SPI0 SCK input source */ + CCL_INSEL2_TCA0_gc = (0x0A<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCA1_gc = (0x0B<<0), /* TCA1 WO2 input source */ + CCL_INSEL2_TCB2_gc = (0x0C<<0), /* TCB2 WO input source */ + CCL_INSEL2_TCD0_gc = (0x0D<<0), /* TCD0 WOC input source */ +} CCL_INSEL2_t; + +/* Interrupt Mode for LUT0 select */ +typedef enum CCL_INTMODE0_enum +{ + CCL_INTMODE0_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled */ + CCL_INTMODE0_RISING_gc = (0x01<<0), /* Sense rising edge */ + CCL_INTMODE0_FALLING_gc = (0x02<<0), /* Sense falling edge */ + CCL_INTMODE0_BOTH_gc = (0x03<<0), /* Sense both edges */ +} CCL_INTMODE0_t; + +/* Interrupt Mode for LUT1 select */ +typedef enum CCL_INTMODE1_enum +{ + CCL_INTMODE1_INTDISABLE_gc = (0x00<<2), /* Interrupt disabled */ + CCL_INTMODE1_RISING_gc = (0x01<<2), /* Sense rising edge */ + CCL_INTMODE1_FALLING_gc = (0x02<<2), /* Sense falling edge */ + CCL_INTMODE1_BOTH_gc = (0x03<<2), /* Sense both edges */ +} CCL_INTMODE1_t; + +/* Interrupt Mode for LUT2 select */ +typedef enum CCL_INTMODE2_enum +{ + CCL_INTMODE2_INTDISABLE_gc = (0x00<<4), /* Interrupt disabled */ + CCL_INTMODE2_RISING_gc = (0x01<<4), /* Sense rising edge */ + CCL_INTMODE2_FALLING_gc = (0x02<<4), /* Sense falling edge */ + CCL_INTMODE2_BOTH_gc = (0x03<<4), /* Sense both edges */ +} CCL_INTMODE2_t; + +/* Interrupt Mode for LUT3 select */ +typedef enum CCL_INTMODE3_enum +{ + CCL_INTMODE3_INTDISABLE_gc = (0x00<<6), /* Interrupt disabled */ + CCL_INTMODE3_RISING_gc = (0x01<<6), /* Sense rising edge */ + CCL_INTMODE3_FALLING_gc = (0x02<<6), /* Sense falling edge */ + CCL_INTMODE3_BOTH_gc = (0x03<<6), /* Sense both edges */ +} CCL_INTMODE3_t; + +/* Interrupt Mode for LUT4 select */ +typedef enum CCL_INTMODE4_enum +{ + CCL_INTMODE4_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled */ + CCL_INTMODE4_RISING_gc = (0x01<<0), /* Sense rising edge */ + CCL_INTMODE4_FALLING_gc = (0x02<<0), /* Sense falling edge */ + CCL_INTMODE4_BOTH_gc = (0x03<<0), /* Sense both edges */ +} CCL_INTMODE4_t; + +/* Interrupt Mode for LUT5 select */ +typedef enum CCL_INTMODE5_enum +{ + CCL_INTMODE5_INTDISABLE_gc = (0x00<<2), /* Interrupt disabled */ + CCL_INTMODE5_RISING_gc = (0x01<<2), /* Sense rising edge */ + CCL_INTMODE5_FALLING_gc = (0x02<<2), /* Sense falling edge */ + CCL_INTMODE5_BOTH_gc = (0x03<<2), /* Sense both edges */ +} CCL_INTMODE5_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL0_enum +{ + CCL_SEQSEL0_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL0_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL0_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL0_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL0_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL0_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL1_enum +{ + CCL_SEQSEL1_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL1_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL1_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL1_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL1_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL1_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL2_enum +{ + CCL_SEQSEL2_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL2_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL2_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL2_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL2_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL2_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[4]; + register8_t OSCHFCTRLA; /* OSCHF Control A */ + register8_t OSCHFTUNE; /* OSCHF Tune */ + register8_t reserved_2[6]; + register8_t PLLCTRLA; /* PLL Control A */ + register8_t reserved_3[7]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_4[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_5[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSCHF_gc = (0x00<<0), /* Internal high-frequency oxcillator */ + CLKCTRL_CLKSEL_OSC32K_gc = (0x01<<0), /* Internal 32.768 kHz oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768 kHz crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1k cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16k cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32k cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ +} CLKCTRL_CSUT_t; + +/* Frequency select select */ +typedef enum CLKCTRL_FREQSEL_enum +{ + CLKCTRL_FREQSEL_1M_gc = (0x00<<2), /* 1 MHz system clock */ + CLKCTRL_FREQSEL_2M_gc = (0x01<<2), /* 2 MHz system clock */ + CLKCTRL_FREQSEL_3M_gc = (0x02<<2), /* 3 MHz system clock */ + CLKCTRL_FREQSEL_4M_gc = (0x03<<2), /* 4 MHz system clock (default) */ + CLKCTRL_FREQSEL_8M_gc = (0x05<<2), /* 8 MHz system clock */ + CLKCTRL_FREQSEL_12M_gc = (0x06<<2), /* 12 MHz system clock */ + CLKCTRL_FREQSEL_16M_gc = (0x07<<2), /* 16 MHz system clock */ + CLKCTRL_FREQSEL_20M_gc = (0x08<<2), /* 20 MHz system clock */ + CLKCTRL_FREQSEL_24M_gc = (0x09<<2), /* 24 MHz system clock */ +} CLKCTRL_FREQSEL_t; + +/* Multiplication factor select */ +typedef enum CLKCTRL_MULFAC_enum +{ + CLKCTRL_MULFAC_DISABLE_gc = (0x00<<0), /* PLL is disabled */ + CLKCTRL_MULFAC_2x_gc = (0x01<<0), /* 2 x multiplication factor */ + CLKCTRL_MULFAC_3x_gc = (0x02<<0), /* 3 x multiplication factor */ + CLKCTRL_MULFAC_4x_gc = (0x03<<0), /* 4 x multiplication factor */ +} CLKCTRL_MULFAC_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* DATA Register */ +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t SWEVENTA; /* Software Event A */ + register8_t SWEVENTB; /* Software Event B */ + register8_t reserved_1[14]; + register8_t CHANNEL0; /* Multiplexer Channel 0 */ + register8_t CHANNEL1; /* Multiplexer Channel 1 */ + register8_t CHANNEL2; /* Multiplexer Channel 2 */ + register8_t CHANNEL3; /* Multiplexer Channel 3 */ + register8_t CHANNEL4; /* Multiplexer Channel 4 */ + register8_t CHANNEL5; /* Multiplexer Channel 5 */ + register8_t CHANNEL6; /* Multiplexer Channel 6 */ + register8_t CHANNEL7; /* Multiplexer Channel 7 */ + register8_t CHANNEL8; /* Multiplexer Channel 8 */ + register8_t CHANNEL9; /* Multiplexer Channel 9 */ + register8_t reserved_2[6]; + register8_t USERCCLLUT0A; /* User 0 - CCL0 Event A */ + register8_t USERCCLLUT0B; /* User 1 - CCL0 Event B */ + register8_t USERCCLLUT1A; /* User 2 - CCL1 Event A */ + register8_t USERCCLLUT1B; /* User 3 - CCL1 Event B */ + register8_t USERCCLLUT2A; /* User 4 - CCL2 Event A */ + register8_t USERCCLLUT2B; /* User 5 - CCL2 Event B */ + register8_t USERCCLLUT3A; /* User 6 - CCL3 Event A */ + register8_t USERCCLLUT3B; /* User 7 - CCL3 Event B */ + register8_t USERCCLLUT4A; /* User 8 - CCL4 Event A */ + register8_t USERCCLLUT4B; /* User 9 - CCL4 Event B */ + register8_t USERCCLLUT5A; /* User 10 - CCL5 Event A */ + register8_t USERCCLLUT5B; /* User 11 - CCL5 Event B */ + register8_t USERADC0START; /* User 12 - ADC0 */ + register8_t USERPTCSTART; /* User 13 - PTC */ + register8_t USEREVSYSEVOUTA; /* User 14 - EVOUTA */ + register8_t USEREVSYSEVOUTB; /* User 15 - EVOUTB */ + register8_t USEREVSYSEVOUTC; /* User 16 - EVOUTC */ + register8_t USEREVSYSEVOUTD; /* User 17 - EVOUTD */ + register8_t USEREVSYSEVOUTE; /* User 18 - EVOUTE */ + register8_t USEREVSYSEVOUTF; /* User 19 - EVOUTF */ + register8_t USEREVSYSEVOUTG; /* User 20 - EVOUTG */ + register8_t USERUSART0IRDA; /* User 21 - USART0 */ + register8_t USERUSART1IRDA; /* User 22 - USART1 */ + register8_t USERUSART2IRDA; /* User 23 - USART2 */ + register8_t USERUSART3IRDA; /* User 24 - USART3 */ + register8_t USERUSART4IRDA; /* User 25 - USART4 */ + register8_t USERUSART5IRDA; /* User 26 - USART5 */ + register8_t USERTCA0CNTA; /* User 27 - TCA0 Event A */ + register8_t USERTCA0CNTB; /* User 28 - TCA0 Event B */ + register8_t USERTCA1CNTA; /* User 29 - TCA1 Event A */ + register8_t USERTCA1CNTB; /* User 30 - TCA1 Event B */ + register8_t USERTCB0CAPT; /* User 31 - TCB0 Event A */ + register8_t USERTCB0COUNT; /* User 32 - TCB0 Event B */ + register8_t USERTCB1CAPT; /* User 33 - TCB1 Event A */ + register8_t USERTCB1COUNT; /* User 34 - TCB1 Event B */ + register8_t USERTCB2CAPT; /* User 35 - TCB2 Event A */ + register8_t USERTCB2COUNT; /* User 36 - TCB2 Event B */ + register8_t USERTCB3CAPT; /* User 37 - TCB3 Event A */ + register8_t USERTCB3COUNT; /* User 38 - TCB3 Event B */ + register8_t USERTCB4CAPT; /* User 39 - TCB4 Event A */ + register8_t USERTCB4COUNT; /* User 40 - TCB4 Event B */ + register8_t USERTCD0INPUTA; /* User 41 - TCD0 Event A */ + register8_t USERTCD0INPUTB; /* User 42 - TCD0 Event B */ + register8_t USEROSCTEST; /* User 43 - OSCTEST */ +} EVSYS_t; + +/* Channel 0 generator select select */ +typedef enum EVSYS_CHANNEL0_enum +{ + EVSYS_CHANNEL0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL0_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL0_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL0_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL0_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL0_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL0_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL0_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL0_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL0_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL0_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL0_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL0_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL0_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL0_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL0_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL0_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL0_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL0_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL0_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL0_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL0_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL0_PORTA_PIN0_gc = (0x40<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL0_PORTA_PIN1_gc = (0x41<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL0_PORTA_PIN2_gc = (0x42<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL0_PORTA_PIN3_gc = (0x43<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL0_PORTA_PIN4_gc = (0x44<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL0_PORTA_PIN5_gc = (0x45<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL0_PORTA_PIN6_gc = (0x46<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL0_PORTA_PIN7_gc = (0x47<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL0_PORTB_PIN0_gc = (0x48<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL0_PORTB_PIN1_gc = (0x49<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL0_PORTB_PIN2_gc = (0x4A<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL0_PORTB_PIN3_gc = (0x4B<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL0_PORTB_PIN4_gc = (0x4C<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL0_PORTB_PIN5_gc = (0x4D<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL0_PORTB_PIN6_gc = (0x4E<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL0_PORTB_PIN7_gc = (0x4F<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL0_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL0_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL0_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL0_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL0_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL0_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL0_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL0_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL0_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL0_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL0_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL0_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL0_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL0_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL0_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL0_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL0_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL0_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL0_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL0_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL0_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL0_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL0_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL0_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL0_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL0_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL0_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL0_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL0_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL0_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL0_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL0_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL0_t; + +/* Channel 1 generator select select */ +typedef enum EVSYS_CHANNEL1_enum +{ + EVSYS_CHANNEL1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL1_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL1_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL1_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL1_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL1_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL1_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL1_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL1_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL1_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL1_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL1_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL1_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL1_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL1_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL1_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL1_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL1_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL1_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL1_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL1_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL1_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL1_PORTA_PIN0_gc = (0x40<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL1_PORTA_PIN1_gc = (0x41<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL1_PORTA_PIN2_gc = (0x42<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL1_PORTA_PIN3_gc = (0x43<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL1_PORTA_PIN4_gc = (0x44<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL1_PORTA_PIN5_gc = (0x45<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL1_PORTA_PIN6_gc = (0x46<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL1_PORTA_PIN7_gc = (0x47<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL1_PORTB_PIN0_gc = (0x48<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL1_PORTB_PIN1_gc = (0x49<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL1_PORTB_PIN2_gc = (0x4A<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL1_PORTB_PIN3_gc = (0x4B<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL1_PORTB_PIN4_gc = (0x4C<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL1_PORTB_PIN5_gc = (0x4D<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL1_PORTB_PIN6_gc = (0x4E<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL1_PORTB_PIN7_gc = (0x4F<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL1_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL1_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL1_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL1_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL1_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL1_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL1_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL1_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL1_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL1_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL1_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL1_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL1_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL1_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL1_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL1_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL1_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL1_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL1_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL1_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL1_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL1_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL1_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL1_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL1_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL1_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL1_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL1_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL1_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL1_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL1_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL1_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL1_t; + +/* Channel 2 generator select select */ +typedef enum EVSYS_CHANNEL2_enum +{ + EVSYS_CHANNEL2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL2_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL2_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL2_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL2_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL2_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL2_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL2_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL2_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL2_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL2_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL2_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL2_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL2_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL2_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL2_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL2_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL2_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL2_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL2_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL2_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL2_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL2_PORTC_PIN0_gc = (0x40<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL2_PORTC_PIN1_gc = (0x41<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL2_PORTC_PIN2_gc = (0x42<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL2_PORTC_PIN3_gc = (0x43<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL2_PORTC_PIN4_gc = (0x44<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL2_PORTC_PIN5_gc = (0x45<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL2_PORTC_PIN6_gc = (0x46<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL2_PORTC_PIN7_gc = (0x47<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL2_PORTD_PIN0_gc = (0x48<<0), /* Port D Pin 0 */ + EVSYS_CHANNEL2_PORTD_PIN1_gc = (0x49<<0), /* Port D Pin 1 */ + EVSYS_CHANNEL2_PORTD_PIN2_gc = (0x4A<<0), /* Port D Pin 2 */ + EVSYS_CHANNEL2_PORTD_PIN3_gc = (0x4B<<0), /* Port D Pin 3 */ + EVSYS_CHANNEL2_PORTD_PIN4_gc = (0x4C<<0), /* Port D Pin 4 */ + EVSYS_CHANNEL2_PORTD_PIN5_gc = (0x4D<<0), /* Port D Pin 5 */ + EVSYS_CHANNEL2_PORTD_PIN6_gc = (0x4E<<0), /* Port D Pin 6 */ + EVSYS_CHANNEL2_PORTD_PIN7_gc = (0x4F<<0), /* Port D Pin 7 */ + EVSYS_CHANNEL2_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL2_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL2_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL2_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL2_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL2_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL2_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL2_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL2_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL2_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL2_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL2_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL2_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL2_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL2_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL2_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL2_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL2_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL2_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL2_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL2_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL2_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL2_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL2_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL2_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL2_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL2_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL2_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL2_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL2_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL2_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL2_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL2_t; + +/* Channel 3 generator select select */ +typedef enum EVSYS_CHANNEL3_enum +{ + EVSYS_CHANNEL3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL3_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL3_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL3_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL3_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL3_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL3_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL3_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL3_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL3_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL3_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL3_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL3_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL3_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL3_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL3_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL3_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL3_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL3_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL3_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL3_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL3_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL3_PORTC_PIN0_gc = (0x40<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL3_PORTC_PIN1_gc = (0x41<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL3_PORTC_PIN2_gc = (0x42<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL3_PORTC_PIN3_gc = (0x43<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL3_PORTC_PIN4_gc = (0x44<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL3_PORTC_PIN5_gc = (0x45<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL3_PORTC_PIN6_gc = (0x46<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL3_PORTC_PIN7_gc = (0x47<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL3_PORTD_PIN0_gc = (0x48<<0), /* Port D Pin 0 */ + EVSYS_CHANNEL3_PORTD_PIN1_gc = (0x49<<0), /* Port D Pin 1 */ + EVSYS_CHANNEL3_PORTD_PIN2_gc = (0x4A<<0), /* Port D Pin 2 */ + EVSYS_CHANNEL3_PORTD_PIN3_gc = (0x4B<<0), /* Port D Pin 3 */ + EVSYS_CHANNEL3_PORTD_PIN4_gc = (0x4C<<0), /* Port D Pin 4 */ + EVSYS_CHANNEL3_PORTD_PIN5_gc = (0x4D<<0), /* Port D Pin 5 */ + EVSYS_CHANNEL3_PORTD_PIN6_gc = (0x4E<<0), /* Port D Pin 6 */ + EVSYS_CHANNEL3_PORTD_PIN7_gc = (0x4F<<0), /* Port D Pin 7 */ + EVSYS_CHANNEL3_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL3_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL3_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL3_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL3_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL3_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL3_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL3_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL3_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL3_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL3_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL3_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL3_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL3_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL3_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL3_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL3_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL3_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL3_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL3_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL3_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL3_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL3_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL3_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL3_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL3_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL3_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL3_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL3_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL3_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL3_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL3_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL3_t; + +/* Channel 4 generator select select */ +typedef enum EVSYS_CHANNEL4_enum +{ + EVSYS_CHANNEL4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL4_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL4_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL4_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL4_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL4_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL4_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL4_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL4_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL4_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL4_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL4_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL4_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL4_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL4_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL4_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL4_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL4_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL4_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL4_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL4_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL4_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL4_PORTE_PIN0_gc = (0x40<<0), /* Port E Pin 0 */ + EVSYS_CHANNEL4_PORTE_PIN1_gc = (0x41<<0), /* Port E Pin 1 */ + EVSYS_CHANNEL4_PORTE_PIN2_gc = (0x42<<0), /* Port E Pin 2 */ + EVSYS_CHANNEL4_PORTE_PIN3_gc = (0x43<<0), /* Port E Pin 3 */ + EVSYS_CHANNEL4_PORTE_PIN4_gc = (0x44<<0), /* Port E Pin 4 */ + EVSYS_CHANNEL4_PORTE_PIN5_gc = (0x45<<0), /* Port E Pin 5 */ + EVSYS_CHANNEL4_PORTE_PIN6_gc = (0x46<<0), /* Port E Pin 6 */ + EVSYS_CHANNEL4_PORTE_PIN7_gc = (0x47<<0), /* Port E Pin 7 */ + EVSYS_CHANNEL4_PORTF_PIN0_gc = (0x48<<0), /* Port F Pin 0 */ + EVSYS_CHANNEL4_PORTF_PIN1_gc = (0x49<<0), /* Port F Pin 1 */ + EVSYS_CHANNEL4_PORTF_PIN2_gc = (0x4A<<0), /* Port F Pin 2 */ + EVSYS_CHANNEL4_PORTF_PIN3_gc = (0x4B<<0), /* Port F Pin 3 */ + EVSYS_CHANNEL4_PORTF_PIN4_gc = (0x4C<<0), /* Port F Pin 4 */ + EVSYS_CHANNEL4_PORTF_PIN5_gc = (0x4D<<0), /* Port F Pin 5 */ + EVSYS_CHANNEL4_PORTF_PIN6_gc = (0x4E<<0), /* Port F Pin 6 */ + EVSYS_CHANNEL4_PORTF_PIN7_gc = (0x4F<<0), /* Port F Pin 7 */ + EVSYS_CHANNEL4_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL4_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL4_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL4_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL4_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL4_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL4_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL4_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL4_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL4_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL4_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL4_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL4_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL4_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL4_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL4_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL4_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL4_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL4_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL4_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL4_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL4_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL4_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL4_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL4_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL4_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL4_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL4_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL4_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL4_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL4_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL4_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL4_t; + +/* Channel 5 generator select select */ +typedef enum EVSYS_CHANNEL5_enum +{ + EVSYS_CHANNEL5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL5_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL5_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL5_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL5_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL5_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL5_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL5_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL5_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL5_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL5_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL5_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL5_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL5_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL5_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL5_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL5_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL5_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL5_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL5_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL5_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL5_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL5_PORTE_PIN0_gc = (0x40<<0), /* Port E Pin 0 */ + EVSYS_CHANNEL5_PORTE_PIN1_gc = (0x41<<0), /* Port E Pin 1 */ + EVSYS_CHANNEL5_PORTE_PIN2_gc = (0x42<<0), /* Port E Pin 2 */ + EVSYS_CHANNEL5_PORTE_PIN3_gc = (0x43<<0), /* Port E Pin 3 */ + EVSYS_CHANNEL5_PORTE_PIN4_gc = (0x44<<0), /* Port E Pin 4 */ + EVSYS_CHANNEL5_PORTE_PIN5_gc = (0x45<<0), /* Port E Pin 5 */ + EVSYS_CHANNEL5_PORTE_PIN6_gc = (0x46<<0), /* Port E Pin 6 */ + EVSYS_CHANNEL5_PORTA_PIN7_gc = (0x47<<0), /* Port E Pin 7 */ + EVSYS_CHANNEL5_PORTF_PIN0_gc = (0x48<<0), /* Port F Pin 0 */ + EVSYS_CHANNEL5_PORTF_PIN1_gc = (0x49<<0), /* Port F Pin 1 */ + EVSYS_CHANNEL5_PORTF_PIN2_gc = (0x4A<<0), /* Port F Pin 2 */ + EVSYS_CHANNEL5_PORTF_PIN3_gc = (0x4B<<0), /* Port F Pin 3 */ + EVSYS_CHANNEL5_PORTF_PIN4_gc = (0x4C<<0), /* Port F Pin 4 */ + EVSYS_CHANNEL5_PORTF_PIN5_gc = (0x4D<<0), /* Port F Pin 5 */ + EVSYS_CHANNEL5_PORTF_PIN6_gc = (0x4E<<0), /* Port F Pin 6 */ + EVSYS_CHANNEL5_PORTF_PIN7_gc = (0x4F<<0), /* Port F Pin 7 */ + EVSYS_CHANNEL5_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL5_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL5_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL5_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL5_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL5_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL5_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL5_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL5_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL5_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL5_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL5_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL5_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL5_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL5_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL5_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL5_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL5_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL5_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL5_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL5_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL5_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL5_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL5_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL5_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL5_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL5_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL5_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL5_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL5_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL5_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL5_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL5_t; + +/* Channel 6 generator select select */ +typedef enum EVSYS_CHANNEL6_enum +{ + EVSYS_CHANNEL6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL6_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL6_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL6_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL6_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL6_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL6_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL6_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL6_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL6_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL6_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL6_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL6_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL6_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL6_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL6_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL6_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL6_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL6_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL6_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL6_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL6_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL6_PORTG_PIN0_gc = (0x40<<0), /* Port G Pin 0 */ + EVSYS_CHANNEL6_PORTG_PIN1_gc = (0x41<<0), /* Port G Pin 1 */ + EVSYS_CHANNEL6_PORTG_PIN2_gc = (0x42<<0), /* Port G Pin 2 */ + EVSYS_CHANNEL6_PORTG_PIN3_gc = (0x43<<0), /* Port G Pin 3 */ + EVSYS_CHANNEL6_PORTG_PIN4_gc = (0x44<<0), /* Port G Pin 4 */ + EVSYS_CHANNEL6_PORTG_PIN5_gc = (0x45<<0), /* Port G Pin 5 */ + EVSYS_CHANNEL6_PORTG_PIN6_gc = (0x46<<0), /* Port G Pin 6 */ + EVSYS_CHANNEL6_PORTG_PIN7_gc = (0x47<<0), /* Port G Pin 7 */ + EVSYS_CHANNEL6_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL6_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL6_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL6_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL6_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL6_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL6_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL6_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL6_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL6_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL6_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL6_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL6_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL6_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL6_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL6_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL6_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL6_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL6_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL6_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL6_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL6_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL6_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL6_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL6_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL6_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL6_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL6_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL6_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL6_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL6_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL6_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL6_t; + +/* Channel 7 generator select select */ +typedef enum EVSYS_CHANNEL7_enum +{ + EVSYS_CHANNEL7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL7_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL7_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL7_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL7_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL7_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL7_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL7_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL7_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL7_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL7_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL7_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL7_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL7_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL7_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL7_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL7_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL7_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL7_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL7_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL7_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL7_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL7_PORTG_PIN0_gc = (0x40<<0), /* Port G Pin 0 */ + EVSYS_CHANNEL7_PORTG_PIN1_gc = (0x41<<0), /* Port G Pin 1 */ + EVSYS_CHANNEL7_PORTG_PIN2_gc = (0x42<<0), /* Port G Pin 2 */ + EVSYS_CHANNEL7_PORTG_PIN3_gc = (0x43<<0), /* Port G Pin 3 */ + EVSYS_CHANNEL7_PORTG_PIN4_gc = (0x44<<0), /* Port G Pin 4 */ + EVSYS_CHANNEL7_PORTG_PIN5_gc = (0x45<<0), /* Port G Pin 5 */ + EVSYS_CHANNEL7_PORTG_PIN6_gc = (0x46<<0), /* Port G Pin 6 */ + EVSYS_CHANNEL7_PORTG_PIN7_gc = (0x47<<0), /* Port G Pin 7 */ + EVSYS_CHANNEL7_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL7_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL7_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL7_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL7_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL7_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL7_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL7_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL7_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL7_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL7_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL7_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL7_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL7_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL7_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL7_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL7_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL7_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL7_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL7_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL7_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL7_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL7_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL7_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL7_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL7_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL7_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL7_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL7_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL7_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL7_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL7_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL7_t; + +/* Channel 8 generator select select */ +typedef enum EVSYS_CHANNEL8_enum +{ + EVSYS_CHANNEL8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL8_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL8_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL8_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL8_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL8_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL8_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL8_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL8_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL8_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL8_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL8_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL8_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL8_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL8_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL8_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL8_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL8_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL8_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL8_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL8_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL8_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL8_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL8_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL8_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL8_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL8_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL8_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL8_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL8_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL8_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL8_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL8_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL8_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL8_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL8_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL8_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL8_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL8_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL8_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL8_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL8_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL8_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL8_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL8_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL8_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL8_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL8_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL8_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL8_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL8_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL8_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL8_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL8_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL8_t; + +/* Channel 9 generator select select */ +typedef enum EVSYS_CHANNEL9_enum +{ + EVSYS_CHANNEL9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL9_UPDI_SYNCH_gc = (0x01<<0), /* UPDI SYNCH character */ + EVSYS_CHANNEL9_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL9_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL9_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL9_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL9_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL9_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL9_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL9_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL9_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL9_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL9_CCL_LUT4_gc = (0x14<<0), /* Configurable Custom Logic LUT4 */ + EVSYS_CHANNEL9_CCL_LUT5_gc = (0x15<<0), /* Configurable Custom Logic LUT5 */ + EVSYS_CHANNEL9_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL9_AC1_OUT_gc = (0x21<<0), /* Analog Comparator 1 out */ + EVSYS_CHANNEL9_AC2_OUT_gc = (0x22<<0), /* Analog Comparator 2 out */ + EVSYS_CHANNEL9_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready */ + EVSYS_CHANNEL9_PTC_RESRDY_gc = (0x28<<0), /* PTC Result Ready */ + EVSYS_CHANNEL9_ZCD0_gc = (0x30<<0), /* Zero Cross Detect 0 out */ + EVSYS_CHANNEL9_ZCD1_gc = (0x31<<0), /* Zero Cross Detect 1 out */ + EVSYS_CHANNEL9_ZCD2_gc = (0x32<<0), /* Zero Cross Detect 2 out */ + EVSYS_CHANNEL9_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL9_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL9_USART2_XCK_gc = (0x62<<0), /* USART 2 XCK */ + EVSYS_CHANNEL9_USART3_XCK_gc = (0x63<<0), /* USART 3 XCK */ + EVSYS_CHANNEL9_USART4_XCK_gc = (0x64<<0), /* USART 4 XCK */ + EVSYS_CHANNEL9_USART5_XCK_gc = (0x65<<0), /* USART 5 XCK */ + EVSYS_CHANNEL9_SPI0_SCK_gc = (0x68<<0), /* SPI 0 SCK */ + EVSYS_CHANNEL9_SPI1_SCK_gc = (0x69<<0), /* SPI 1 SCK */ + EVSYS_CHANNEL9_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte timer underflow */ + EVSYS_CHANNEL9_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte timer underflow */ + EVSYS_CHANNEL9_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL9_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL9_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL9_TCA1_OVF_LUNF_gc = (0x88<<0), /* Timer/Counter A1 overflow / low byte timer underflow */ + EVSYS_CHANNEL9_TCA1_HUNF_gc = (0x89<<0), /* Timer/Counter A1 high byte timer underflow */ + EVSYS_CHANNEL9_TCA1_CMP0_LCMP0_gc = (0x8C<<0), /* Timer/Counter A1 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL9_TCA1_CMP1_LCMP1_gc = (0x8D<<0), /* Timer/Counter A1 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL9_TCA1_CMP2_LCMP2_gc = (0x8E<<0), /* Timer/Counter A1 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL9_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL9_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL9_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL9_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ + EVSYS_CHANNEL9_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_CHANNEL9_TCB2_OVF_gc = (0xA5<<0), /* Timer/Counter B2 overflow */ + EVSYS_CHANNEL9_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ + EVSYS_CHANNEL9_TCB3_OVF_gc = (0xA7<<0), /* Timer/Counter B3 overflow */ + EVSYS_CHANNEL9_TCB4_CAPT_gc = (0xA8<<0), /* Timer/Counter B4 capture */ + EVSYS_CHANNEL9_TCB4_OVF_gc = (0xA9<<0), /* Timer/Counter B4 overflow */ + EVSYS_CHANNEL9_TCD0_CMPBCLR_gc = (0xB0<<0), /* Timer/Counter D0 event 0 */ + EVSYS_CHANNEL9_TCD0_CMPASET_gc = (0xB1<<0), /* Timer/Counter D0 event 1 */ + EVSYS_CHANNEL9_TCD0_CMPBSET_gc = (0xB2<<0), /* Timer/Counter D0 event 2 */ + EVSYS_CHANNEL9_TCD0_PROGEV_gc = (0xB3<<0), /* Timer/Counter D0 event 3 */ +} EVSYS_CHANNEL9_t; + +/* Software event on channel select select */ +typedef enum EVSYS_SWEVENTA_enum +{ + EVSYS_SWEVENTA_CH0_gc = (0x01<<0), /* Software event on channel 0 */ + EVSYS_SWEVENTA_CH1_gc = (0x02<<0), /* Software event on channel 1 */ + EVSYS_SWEVENTA_CH2_gc = (0x04<<0), /* Software event on channel 2 */ + EVSYS_SWEVENTA_CH3_gc = (0x08<<0), /* Software event on channel 3 */ + EVSYS_SWEVENTA_CH4_gc = (0x10<<0), /* Software event on channel 4 */ + EVSYS_SWEVENTA_CH5_gc = (0x20<<0), /* Software event on channel 5 */ + EVSYS_SWEVENTA_CH6_gc = (0x40<<0), /* Software event on channel 6 */ + EVSYS_SWEVENTA_CH7_gc = (0x80<<0), /* Software event on channel 7 */ +} EVSYS_SWEVENTA_t; + +/* Software event on channel select select */ +typedef enum EVSYS_SWEVENTB_enum +{ + EVSYS_SWEVENTB_CH8_gc = (0x00<<0), /* Software event on channel 8 */ + EVSYS_SWEVENTB_CH9_gc = (0x01<<0), /* Software event on channel 9 */ +} EVSYS_SWEVENTB_t; + +/* User channel select select */ +typedef enum EVSYS_USER_enum +{ + EVSYS_USER_OFF_gc = (0x00<<0), /* Off */ + EVSYS_USER_CHANNEL0_gc = (0x01<<0), /* Connect user to event channel 0 */ + EVSYS_USER_CHANNEL1_gc = (0x02<<0), /* Connect user to event channel 1 */ + EVSYS_USER_CHANNEL2_gc = (0x03<<0), /* Connect user to event channel 2 */ + EVSYS_USER_CHANNEL3_gc = (0x04<<0), /* Connect user to event channel 3 */ + EVSYS_USER_CHANNEL4_gc = (0x05<<0), /* Connect user to event channel 4 */ + EVSYS_USER_CHANNEL5_gc = (0x06<<0), /* Connect user to event channel 5 */ + EVSYS_USER_CHANNEL6_gc = (0x07<<0), /* Connect user to event channel 6 */ + EVSYS_USER_CHANNEL7_gc = (0x08<<0), /* Connect user to event channel 7 */ + EVSYS_USER_CHANNEL8_gc = (0x09<<0), /* Connect user to event channel 8 */ + EVSYS_USER_CHANNEL9_gc = (0x0A<<0), /* Connect user to event channel 9 */ +} EVSYS_USER_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t CODESIZE; /* Code Section Size */ + register8_t BOOTSIZE; /* Boot Section Size */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DISABLE_gc = (0x00<<2), /* BOD disabled */ + ACTIVE_ENABLE_gc = (0x01<<2), /* BOD enabled in continiuous mode */ + ACTIVE_SAMPLE_gc = (0x02<<2), /* BOD enabled in sampled mode */ + ACTIVE_ENABLEWAIT_gc = (0x03<<2), /* BOD enabled in continiuous mode. Execution is halted at wake-up until BOD is running. */ +} ACTIVE_t; + +/* Frequency Select select */ +typedef enum CLKSEL_enum +{ + CLKSEL_OSCHF_gc = (0x00<<0), /* 1-32MHz internal oscillator */ + CLKSEL_OSC32K_gc = (0x01<<0), /* 32.768kHz internal oscillator */ +} CLKSEL_t; + +/* CRC Select select */ +typedef enum CRCSEL_enum +{ + CRCSEL_CRC16_gc = (0x00<<5), /* Enable CRC16 */ + CRCSEL_CRC32_gc = (0x01<<5), /* Enable CRC32 */ +} CRCSEL_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* CRC of full Flash (boot, application code and application data) */ + CRCSRC_BOOT_gc = (0x01<<6), /* CRC of boot section */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* CRC of application code and boot sections */ + CRCSRC_NOCRC_gc = (0x03<<6), /* No CRC */ +} CRCSRC_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.9V */ + LVL_BODLEVEL1_gc = (0x01<<5), /* 2.45V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.7V */ + LVL_BODLEVEL3_gc = (0x03<<5), /* 2.85V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.0s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.0s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_128Hz_gc = (0x00<<4), /* Sample frequency is 128 Hz */ + SAMPFREQ_32Hz_gc = (0x01<<4), /* Sample frequency is 32 Hz */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DISABLE_gc = (0x00<<0), /* BOD disabled */ + SLEEP_ENABLE_gc = (0x01<<0), /* BOD enabled in continiuous mode */ + SLEEP_SAMPLE_gc = (0x02<<0), /* BOD enabled in sampled mode */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.0s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.0s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +GPR - General Purpose Registers +-------------------------------------------------------------------------- +*/ + +/* General Purpose Registers */ +typedef struct GPR_struct +{ + register8_t GPR0; /* General Purpose Register 0 */ + register8_t GPR1; /* General Purpose Register 1 */ + register8_t GPR2; /* General Purpose Register 2 */ + register8_t GPR3; /* General Purpose Register 3 */ +} GPR_t; + + +/* +-------------------------------------------------------------------------- +LOCK - Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lockbits */ +typedef struct LOCK_struct +{ + _DWORDREGISTER(KEY); /* Lock Key Bits */ +} LOCK_t; + +/* Lock Key select */ +typedef enum LOCK_KEY_enum +{ + LOCK_KEY_NOLOCK_gc = (0x5CC5C55C<<0), /* No locks */ + LOCK_KEY_RWLOCK_gc = (0xA33A3AA3<<0), /* Read and write lock */ +} LOCK_KEY_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _DWORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[4]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_NOOP_gc = (0x01<<0), /* No Operation */ + NVMCTRL_CMD_FLWR_gc = (0x02<<0), /* Flash Write */ + NVMCTRL_CMD_FLPER_gc = (0x08<<0), /* Flash Page Erase */ + NVMCTRL_CMD_FLMPER2_gc = (0x09<<0), /* Flash Multi-Page Erase 2 pages */ + NVMCTRL_CMD_FLMPER4_gc = (0x0A<<0), /* Flash Multi-Page Erase 4 pages */ + NVMCTRL_CMD_FLMPER8_gc = (0x0B<<0), /* Flash Multi-Page Erase 8 pages */ + NVMCTRL_CMD_FLMPER16_gc = (0x0C<<0), /* Flash Multi-Page Erase 16 pages */ + NVMCTRL_CMD_FLMPER32_gc = (0x0D<<0), /* Flash Multi-Page Erase 32 pages */ + NVMCTRL_CMD_EEWR_gc = (0x12<<0), /* EEPROM Write */ + NVMCTRL_CMD_EEERWR_gc = (0x13<<0), /* EEPROM Erase and Write */ + NVMCTRL_CMD_EEBER_gc = (0x18<<0), /* EEPROM Byte Erase */ + NVMCTRL_CMD_EEMBER2_gc = (0x19<<0), /* EEPROM Multi-Byte Erase 2 bytes */ + NVMCTRL_CMD_EEMBER4_gc = (0x1A<<0), /* EEPROM Multi-Byte Erase 4 bytes */ + NVMCTRL_CMD_EEMBER8_gc = (0x1B<<0), /* EEPROM Multi-Byte Erase 8 bytes */ + NVMCTRL_CMD_EEMBER16_gc = (0x1C<<0), /* EEPROM Multi-Byte Erase 16 bytes */ + NVMCTRL_CMD_EEMBER32_gc = (0x1D<<0), /* EEPROM Multi-Byte Erase 32 bytes */ + NVMCTRL_CMD_CHER_gc = (0x20<<0), /* Chip Erase Command */ + NVMCTRL_CMD_EECHER_gc = (0x30<<0), /* EEPROM Erase Command */ +} NVMCTRL_CMD_t; + +/* Write error select */ +typedef enum NVMCTRL_ERROR_enum +{ + NVMCTRL_ERROR_NOERROR_gc = (0x00<<4), /* No Error */ + NVMCTRL_ERROR_ILLEGALCMD_gc = (0x01<<4), /* Write command not selected */ + NVMCTRL_ERROR_ILLEGALSADDR_gc = (0x02<<4), /* Write to section not allowed */ + NVMCTRL_ERROR_DOUBLESELECT_gc = (0x03<<4), /* Selecting new write command while write command already seleted */ + NVMCTRL_ERROR_ONGOINGPROG_gc = (0x04<<4), /* Starting a new programming operation before previous is completed */ +} NVMCTRL_ERROR_t; + +/* Flash Mapping in Data space select */ +typedef enum NVMCTRL_FLMAP_enum +{ + NVMCTRL_FLMAP_SECTION0_gc = (0x00<<4), /* Flash section 0, 0 - 32KB */ + NVMCTRL_FLMAP_SECTION1_gc = (0x01<<4), /* Flash section 1, 32 - 64KB */ + NVMCTRL_FLMAP_SECTION2_gc = (0x02<<4), /* Flash section 2, 64 - 96KB */ + NVMCTRL_FLMAP_SECTION3_gc = (0x03<<4), /* Flash section 3, 96 - 128KB */ +} NVMCTRL_FLMAP_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t PORTCTRL; /* Port Control */ + register8_t PINCONFIG; /* Pin Control Config */ + register8_t PINCTRLUPD; /* Pin Control Update */ + register8_t PINCTRLSET; /* Pin Control Set */ + register8_t PINCTRLCLR; /* Pin Control Clear */ + register8_t reserved_1[1]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t EVSYSROUTEA; /* EVSYS route A */ + register8_t CCLROUTEA; /* CCL route A */ + register8_t USARTROUTEA; /* USART route A */ + register8_t USARTROUTEB; /* USART route B */ + register8_t SPIROUTEA; /* SPI route A */ + register8_t TWIROUTEA; /* TWI route A */ + register8_t TCAROUTEA; /* TCA route A */ + register8_t TCBROUTEA; /* TCB route A */ + register8_t TCDROUTEA; /* TCD route A */ + register8_t ACROUTEA; /* AC route A */ + register8_t ZCDROUTEA; /* ZCD route A */ + register8_t reserved_1[5]; +} PORTMUX_t; + +/* Analog Comparator 0 Output select */ +typedef enum PORTMUX_AC0_enum +{ + PORTMUX_AC0_DEFAULT_gc = (0x00<<0), /* OUT on PA7 */ + PORTMUX_AC0_ALT1_gc = (0x01<<0), /* OUT on PC6 */ +} PORTMUX_AC0_t; + +/* Analog Comparator 1 Output select */ +typedef enum PORTMUX_AC1_enum +{ + PORTMUX_AC1_DEFAULT_gc = (0x00<<1), /* OUT on PA7 */ + PORTMUX_AC1_ALT1_gc = (0x01<<1), /* OUT on PC6 */ +} PORTMUX_AC1_t; + +/* Analog Comparator 2 Output select */ +typedef enum PORTMUX_AC2_enum +{ + PORTMUX_AC2_DEFAULT_gc = (0x00<<2), /* OUT on PA7 */ + PORTMUX_AC2_ALT1_gc = (0x01<<2), /* OUT on PC6 */ +} PORTMUX_AC2_t; + +/* Event Output A select */ +typedef enum PORTMUX_EVOUTA_enum +{ + PORTMUX_EVOUTA_DEFAULT_gc = (0x00<<0), /* EVOUT on PA2 */ + PORTMUX_EVOUTA_ALT1_gc = (0x01<<0), /* EVOUT on PA7 */ +} PORTMUX_EVOUTA_t; + +/* Event Output B select */ +typedef enum PORTMUX_EVOUTB_enum +{ + PORTMUX_EVOUTB_DEFAULT_gc = (0x00<<1), /* EVOUT on PB2 */ + PORTMUX_EVOUTB_ALT1_gc = (0x01<<1), /* EVOUT on PB7 */ +} PORTMUX_EVOUTB_t; + +/* Event Output C select */ +typedef enum PORTMUX_EVOUTC_enum +{ + PORTMUX_EVOUTC_DEFAULT_gc = (0x00<<2), /* EVOUT on PC2 */ + PORTMUX_EVOUTC_ALT1_gc = (0x01<<2), /* EVOUT on PC7 */ +} PORTMUX_EVOUTC_t; + +/* Event Output D select */ +typedef enum PORTMUX_EVOUTD_enum +{ + PORTMUX_EVOUTD_DEFAULT_gc = (0x00<<3), /* EVOUT on PD2 */ + PORTMUX_EVOUTD_ALT1_gc = (0x01<<3), /* EVOUT on PD7 */ +} PORTMUX_EVOUTD_t; + +/* Event Output E select */ +typedef enum PORTMUX_EVOUTE_enum +{ + PORTMUX_EVOUTE_DEFAULT_gc = (0x00<<4), /* EVOUT on PE2 */ + PORTMUX_EVOUTE_ALT1_gc = (0x01<<4), /* EVOUT on PE7 */ +} PORTMUX_EVOUTE_t; + +/* Event Output F select */ +typedef enum PORTMUX_EVOUTF_enum +{ + PORTMUX_EVOUTF_DEFAULT_gc = (0x00<<5), /* EVOUT on PF2 */ +} PORTMUX_EVOUTF_t; + +/* Event Output G select */ +typedef enum PORTMUX_EVOUTG_enum +{ + PORTMUX_EVOUTG_DEFAULT_gc = (0x00<<6), /* EVOUT on PG2 */ + PORTMUX_EVOUTG_ALT1_gc = (0x01<<6), /* EVOUT on PG7 */ +} PORTMUX_EVOUTG_t; + +/* CCL Look-Up Table 0 Signals select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<0), /* Out: PA3 In: PA0, PA1, PA2 */ + PORTMUX_LUT0_ALT1_gc = (0x01<<0), /* Out: PA6 In: PA0, PA1, PA2 */ +} PORTMUX_LUT0_t; + +/* CCL Look-Up Table 1 Signals select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<1), /* Out: PC3 In: PC0, PC1, PC2 */ + PORTMUX_LUT1_ALT1_gc = (0x01<<1), /* Out: PC6 In: PC0, PC1, PC2 */ +} PORTMUX_LUT1_t; + +/* CCL Look-Up Table 2 Signals select */ +typedef enum PORTMUX_LUT2_enum +{ + PORTMUX_LUT2_DEFAULT_gc = (0x00<<2), /* Out: PD3 In: PD0, PD1, PD2 */ + PORTMUX_LUT2_ALT1_gc = (0x01<<2), /* Out: PD6 In: PD0, PD1, PD2 */ +} PORTMUX_LUT2_t; + +/* CCL Look-Up Table 3 Signals select */ +typedef enum PORTMUX_LUT3_enum +{ + PORTMUX_LUT3_DEFAULT_gc = (0x00<<3), /* Out: PF3 In: PF0, PF1, PF2 */ +} PORTMUX_LUT3_t; + +/* CCL Look-Up Table 4 Signals select */ +typedef enum PORTMUX_LUT4_enum +{ + PORTMUX_LUT4_DEFAULT_gc = (0x00<<4), /* Out: PB3 In: PB0, PB1, PB2 */ + PORTMUX_LUT4_ALT1_gc = (0x01<<4), /* Out: PB6 In: PB0, PB1, PB2 */ +} PORTMUX_LUT4_t; + +/* CCL Look-Up Table 5 Signals select */ +typedef enum PORTMUX_LUT5_enum +{ + PORTMUX_LUT5_DEFAULT_gc = (0x00<<5), /* Out: PG3 In: PG0, PG1, PG2 */ + PORTMUX_LUT5_ALT1_gc = (0x01<<5), /* Out: PG6 In: PG0, PG1, PG2 */ +} PORTMUX_LUT5_t; + +/* SPI0 Signals select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<0), /* PA4, PA5, PA6, PA7 */ + PORTMUX_SPI0_ALT1_gc = (0x01<<0), /* PE0, PE1, PE2, PE3 */ + PORTMUX_SPI0_ALT2_gc = (0x02<<0), /* PG4, PG5, PG6, PG7 */ + PORTMUX_SPI0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_SPI0_t; + +/* SPI1 Signals select */ +typedef enum PORTMUX_SPI1_enum +{ + PORTMUX_SPI1_DEFAULT_gc = (0x00<<2), /* PC0, PC1, PC2, PC3 */ + PORTMUX_SPI1_ALT1_gc = (0x01<<2), /* PC4, PC5, PC6, PC7 */ + PORTMUX_SPI1_ALT2_gc = (0x02<<2), /* PB4, PB5, PB6, PB7 */ + PORTMUX_SPI1_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_SPI1_t; + +/* TCA0 Signals select */ +typedef enum PORTMUX_TCA0_enum +{ + PORTMUX_TCA0_PORTA_gc = (0x00<<0), /* PA0, PA1, PA2, PA3, PA4, PA5 */ + PORTMUX_TCA0_PORTB_gc = (0x01<<0), /* PB0, PB1, PB2, PB3, PB4, PB5 */ + PORTMUX_TCA0_PORTC_gc = (0x02<<0), /* PC0, PC1, PC2, PC3, PC4, PC5 */ + PORTMUX_TCA0_PORTD_gc = (0x03<<0), /* PD0, PD1, PD2, PD3, PD4, PD5 */ + PORTMUX_TCA0_PORTE_gc = (0x04<<0), /* PE0, PE1, PE2, PE3, PE4, PE5 */ + PORTMUX_TCA0_PORTF_gc = (0x05<<0), /* PF0, PF1, PF2, PF3, PF4, PF5 */ + PORTMUX_TCA0_PORTG_gc = (0x06<<0), /* PG0, PG1, PG2, PG3, PG4, PG5 */ +} PORTMUX_TCA0_t; + +/* TCA1 Signals select */ +typedef enum PORTMUX_TCA1_enum +{ + PORTMUX_TCA1_PORTB_gc = (0x00<<3), /* PB0, PB1, PB2, PB3, PB4, PB5 */ + PORTMUX_TCA1_PORTC_gc = (0x01<<3), /* PC4, PC5, PC6 */ + PORTMUX_TCA1_PORTE_gc = (0x02<<3), /* PE4, PE5, PE6 */ + PORTMUX_TCA1_PORTG_gc = (0x03<<3), /* PG0, PG1, PG2, PG3, PG4, PG5 */ +} PORTMUX_TCA1_t; + +/* TCB0 Output select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* WO on PA2 */ + PORTMUX_TCB0_ALT1_gc = (0x01<<0), /* WO on PF4 */ +} PORTMUX_TCB0_t; + +/* TCB1 Output select */ +typedef enum PORTMUX_TCB1_enum +{ + PORTMUX_TCB1_DEFAULT_gc = (0x00<<1), /* WO on PA3 */ + PORTMUX_TCB1_ALT1_gc = (0x01<<1), /* WO on PF5 */ +} PORTMUX_TCB1_t; + +/* TCB2 Output select */ +typedef enum PORTMUX_TCB2_enum +{ + PORTMUX_TCB2_DEFAULT_gc = (0x00<<2), /* WO on PC0 */ + PORTMUX_TCB2_ALT1_gc = (0x01<<2), /* WO on PB4 */ +} PORTMUX_TCB2_t; + +/* TCB3 Output select */ +typedef enum PORTMUX_TCB3_enum +{ + PORTMUX_TCB3_DEFAULT_gc = (0x00<<3), /* WO on PB5 */ + PORTMUX_TCB3_ALT1_gc = (0x01<<3), /* WO on PC1 */ +} PORTMUX_TCB3_t; + +/* TCB4 Output select */ +typedef enum PORTMUX_TCB4_enum +{ + PORTMUX_TCB4_DEFAULT_gc = (0x00<<4), /* WO on PG3 */ + PORTMUX_TCB4_ALT1_gc = (0x01<<4), /* WO on PC6 */ +} PORTMUX_TCB4_t; + +/* TCD0 Signals select */ +typedef enum PORTMUX_TCD0_enum +{ + PORTMUX_TCD0_DEFAULT_gc = (0x00<<0), /* PA4, PA5, PA6, PA7 */ + PORTMUX_TCD0_ALT1_gc = (0x01<<0), /* PB4, PB5, PB6, PB7 */ + PORTMUX_TCD0_ALT2_gc = (0x02<<0), /* PF0, PF1, PF2, PF3 */ + PORTMUX_TCD0_ALT3_gc = (0x03<<0), /* PG4, PG5, PG6, PG7 */ +} PORTMUX_TCD0_t; + +/* TWI0 Signals select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<0), /* PA2, PA3, PC2, PC3 */ + PORTMUX_TWI0_ALT1_gc = (0x01<<0), /* PA2, PA3, PC6, PC7 */ + PORTMUX_TWI0_ALT2_gc = (0x02<<0), /* PC2, PC3, PC6, PC7 */ +} PORTMUX_TWI0_t; + +/* TWI1 Signals select */ +typedef enum PORTMUX_TWI1_enum +{ + PORTMUX_TWI1_DEFAULT_gc = (0x00<<2), /* PF2, PF3, PB2, PB3 */ + PORTMUX_TWI1_ALT1_gc = (0x01<<2), /* PF2, PF3, PB6, PB7 */ + PORTMUX_TWI1_ALT2_gc = (0x02<<2), /* PB2, PB3, PB6, PB7 */ +} PORTMUX_TWI1_t; + +/* USART0 Signals select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* PA0, PA1, PA2, PA3 */ + PORTMUX_USART0_ALT1_gc = (0x01<<0), /* PA4, PA5, PA6, PA7 */ + PORTMUX_USART0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_USART0_t; + +/* USART1 Signals select */ +typedef enum PORTMUX_USART1_enum +{ + PORTMUX_USART1_DEFAULT_gc = (0x00<<2), /* PC0, PC1, PC2, PC3 */ + PORTMUX_USART1_ALT1_gc = (0x01<<2), /* PC4, PC5, PC6, PC7 */ + PORTMUX_USART1_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_USART1_t; + +/* USART2 Signals select */ +typedef enum PORTMUX_USART2_enum +{ + PORTMUX_USART2_DEFAULT_gc = (0x00<<4), /* PF0, PF1, PF2, PF3 */ + PORTMUX_USART2_ALT1_gc = (0x01<<4), /* PF4, PF5 */ + PORTMUX_USART2_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_USART2_t; + +/* USART3 Signals select */ +typedef enum PORTMUX_USART3_enum +{ + PORTMUX_USART3_DEFAULT_gc = (0x00<<6), /* PB0, PB1, PB2, PB3 */ + PORTMUX_USART3_ALT1_gc = (0x01<<6), /* PB4, PB5, PB6, PB7 */ + PORTMUX_USART3_NONE_gc = (0x03<<6), /* Not connected to any pins */ +} PORTMUX_USART3_t; + +/* USART4 Signals select */ +typedef enum PORTMUX_USART4_enum +{ + PORTMUX_USART4_DEFAULT_gc = (0x00<<0), /* PE0, PE1, PE2, PE3 */ + PORTMUX_USART4_ALT1_gc = (0x01<<0), /* PE4, PE5, PE6, PE7 */ + PORTMUX_USART4_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_USART4_t; + +/* USART5 Signals select */ +typedef enum PORTMUX_USART5_enum +{ + PORTMUX_USART5_DEFAULT_gc = (0x00<<2), /* PG0, PG1, PG2, PG3 */ + PORTMUX_USART5_ALT1_gc = (0x01<<2), /* PG4, PG5, PG6, PG7 */ + PORTMUX_USART5_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_USART5_t; + +/* Zero Cross Detector 0 Output select */ +typedef enum PORTMUX_ZCD0_enum +{ + PORTMUX_ZCD0_DEFAULT_gc = (0x00<<0), /* OUT on PA7 */ + PORTMUX_ZCD0_ALT1_gc = (0x01<<0), /* OUT on PC7 */ +} PORTMUX_ZCD0_t; + +/* Zero Cross Detector 1 Output select */ +typedef enum PORTMUX_ZCD1_enum +{ + PORTMUX_ZCD1_DEFAULT_gc = (0x00<<1), /* OUT on PA7 */ + PORTMUX_ZCD1_ALT1_gc = (0x01<<1), /* OUT on PC7 */ +} PORTMUX_ZCD1_t; + +/* Zero Cross Detector 2 Output select */ +typedef enum PORTMUX_ZCD2_enum +{ + PORTMUX_ZCD2_DEFAULT_gc = (0x00<<2), /* OUT on PA7 */ + PORTMUX_ZCD2_ALT1_gc = (0x01<<2), /* OUT on PC7 */ +} PORTMUX_ZCD2_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t CALIB; /* Calibration */ + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_1[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_2[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_3[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_OSC32K_gc = (0x00<<0), /* Internal 32.768 kHz oscillator */ + RTC_CLKSEL_OSC1K_gc = (0x01<<0), /* Internal 1.024 kHz oscillator */ + RTC_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768 kHz crystal oscillator */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t reserved_1[1]; + _WORDREGISTER(TEMPSENSE0); /* Temperature Calibration 0 */ + _WORDREGISTER(TEMPSENSE1); /* Temperature Calibration 1 */ + register8_t reserved_2[8]; + register8_t SERNUM0; /* LOTNUM0 */ + register8_t SERNUM1; /* LOTNUM1 */ + register8_t SERNUM2; /* LOTNUM2 */ + register8_t SERNUM3; /* LOTNUM3 */ + register8_t SERNUM4; /* LOTNUM4 */ + register8_t SERNUM5; /* LOTNUM5 */ + register8_t SERNUM6; /* RANDOM */ + register8_t SERNUM7; /* SCRIBE */ + register8_t SERNUM8; /* XPOS0 */ + register8_t SERNUM9; /* XPOS1 */ + register8_t SERNUM10; /* YPOS0 */ + register8_t SERNUM11; /* YPOS1 */ + register8_t SERNUM12; /* RES0 */ + register8_t SERNUM13; /* RES1 */ + register8_t SERNUM14; /* RES2 */ + register8_t SERNUM15; /* RES3 */ + register8_t reserved_3[32]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t VREGCTRL; /* Control B */ +} SLPCTRL_t; + +/* Performance Mode select */ +typedef enum SLPCTRL_PMODE_enum +{ + SLPCTRL_PMODE_AUTO_gc = (0x00<<0), /* */ + SLPCTRL_PMODE_FULL_gc = (0x01<<0), /* */ +} SLPCTRL_PMODE_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t reserved_2[22]; + register8_t OCDMCTRL; /* OCD Message Control */ + register8_t OCDMSTATUS; /* OCD Message Status */ + register8_t reserved_3[6]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action A select */ +typedef enum TCA_SINGLE_EVACTA_enum +{ + TCA_SINGLE_EVACTA_CNT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACTA_CNT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACTA_CNT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACTA_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACTA_t; + +/* Event Action B select */ +typedef enum TCA_SINGLE_EVACTB_enum +{ + TCA_SINGLE_EVACTB_UPDOWN_gc = (0x03<<5), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ + TCA_SINGLE_EVACTB_RESTART_POSEDGE_gc = (0x04<<5), /* Restart counter at positive edge event */ + TCA_SINGLE_EVACTB_RESTART_ANYEDGE_gc = (0x05<<5), /* Restart counter on any edge event */ + TCA_SINGLE_EVACTB_RESTART_HIGHLVL_gc = (0x06<<5), /* Restart counter while event line is 1. */ +} TCA_SINGLE_EVACTB_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* Command Enable select */ +typedef enum TCA_SPLIT_CMDEN_enum +{ + TCA_SPLIT_CMDEN_NONE_gc = (0x00<<0), /* None */ + TCA_SPLIT_CMDEN_BOTH_gc = (0x03<<0), /* Both low byte and high byte counter */ +} TCA_SPLIT_CMDEN_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_DIV1_gc = (0x00<<1), /* CLK_PEP */ + TCB_CLKSEL_DIV2_gc = (0x01<<1), /* CLK_PER/2 */ + TCB_CLKSEL_TCA0_gc = (0x02<<1), /* Use CLK_TCA from TCA0 */ + TCB_CLKSEL_TCA1_gc = (0x03<<1), /* Use CLK_TCA from TCA1 */ + TCB_CLKSEL_EVENT_gc = (0x07<<1), /* Count on event edge */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_OSCHF_gc = (0x00<<5), /* Internal High-Frequency Oscillator */ + TCD_CLKSEL_PLL_gc = (0x01<<5), /* PLL */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External Clock */ + TCD_CLKSEL_CLKPER_gc = (0x03<<5), /* Peripheral Clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Synchronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selected clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selected clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selected clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selected clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t DUALCTRL; /* Dual Control */ + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baud Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_1[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Input Voltage Transition Level select */ +typedef enum TWI_INPUTLVL_enum +{ + TWI_INPUTLVL_I2C_gc = (0x00<<6), /* I2C input voltage transition level */ + TWI_INPUTLVL_SMBUS_gc = (0x01<<6), /* SMBus 3.0 input voltage transition level */ +} TWI_INPUTLVL_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t CTRLD; /* Control D */ + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_1[1]; +} USART_t; + +/* Auto Baud Window select */ +typedef enum USART_ABW_enum +{ + USART_ABW_WDW0_gc = (0x00<<6), /* 18% tolerance */ + USART_ABW_WDW1_gc = (0x01<<6), /* 15% tolerance */ + USART_ABW_WDW2_gc = (0x02<<6), /* 21% tolerance */ + USART_ABW_WDW3_gc = (0x03<<6), /* 25% tolerance */ +} USART_ABW_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t ADC0REF; /* ADC0 Reference */ + register8_t reserved_1[1]; + register8_t DAC0REF; /* DAC0 Reference */ + register8_t reserved_2[1]; + register8_t ACREF; /* AC Reference */ +} VREF_t; + +/* Reference select select */ +typedef enum VREF_REFSEL_enum +{ + VREF_REFSEL_1V024_gc = (0x00<<0), /* Internal 1.024V reference */ + VREF_REFSEL_2V048_gc = (0x01<<0), /* Internal 2.048V reference */ + VREF_REFSEL_4V096_gc = (0x02<<0), /* Internal 4.096V reference */ + VREF_REFSEL_2V500_gc = (0x03<<0), /* Internal 2.500V reference */ + VREF_REFSEL_VDD_gc = (0x05<<0), /* VDD as reference */ + VREF_REFSEL_VREFA_gc = (0x06<<0), /* External referance on VREFA pin */ +} VREF_REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; + +/* +-------------------------------------------------------------------------- +ZCD - Zero Cross Detect +-------------------------------------------------------------------------- +*/ + +/* Zero Cross Detect */ +typedef struct ZCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ + register8_t reserved_2[4]; +} ZCD_t; + +/* Interrupt Mode select */ +typedef enum ZCD_INTMODE_enum +{ + ZCD_INTMODE_NONE_gc = (0x00<<0), /* No interrupt */ + ZCD_INTMODE_RISING_gc = (0x01<<0), /* Interrupt on rising input signal */ + ZCD_INTMODE_FALLING_gc = (0x02<<0), /* Interrupt on falling input signal */ + ZCD_INTMODE_BOTH_gc = (0x03<<0), /* Interrupt on both rising and falling input signal */ +} ZCD_INTMODE_t; + +/* ZCD State select */ +typedef enum ZCD_STATE_enum +{ + ZCD_STATE_LOW_gc = (0x00<<4), /* Output is 0 */ + ZCD_STATE_HIGH_gc = (0x01<<4), /* Output is 1 */ +} ZCD_STATE_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define VPORTD (*(VPORT_t *) 0x000C) /* Virtual Ports */ +#define VPORTE (*(VPORT_t *) 0x0010) /* Virtual Ports */ +#define VPORTF (*(VPORT_t *) 0x0014) /* Virtual Ports */ +#define VPORTG (*(VPORT_t *) 0x0018) /* Virtual Ports */ +#define GPR (*(GPR_t *) 0x001C) /* General Purpose Registers */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define EVSYS (*(EVSYS_t *) 0x0200) /* Event System */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0460) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0480) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x04A0) /* I/O Ports */ +#define PORTG (*(PORT_t *) 0x04C0) /* I/O Ports */ +#define PORTMUX (*(PORTMUX_t *) 0x05E0) /* Port Multiplexer */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define AC1 (*(AC_t *) 0x0688) /* Analog Comparator */ +#define AC2 (*(AC_t *) 0x0690) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x06A0) /* Digital to Analog Converter */ +#define ZCD0 (*(ZCD_t *) 0x06C0) /* Zero Cross Detect */ +#define ZCD1 (*(ZCD_t *) 0x06C8) /* Zero Cross Detect */ +#define ZCD2 (*(ZCD_t *) 0x06D0) /* Zero Cross Detect */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1 (*(USART_t *) 0x0820) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2 (*(USART_t *) 0x0840) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART3 (*(USART_t *) 0x0860) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART4 (*(USART_t *) 0x0880) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART5 (*(USART_t *) 0x08A0) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0900) /* Two-Wire Interface */ +#define TWI1 (*(TWI_t *) 0x0920) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0940) /* Serial Peripheral Interface */ +#define SPI1 (*(SPI_t *) 0x0960) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCA1 (*(TCA_t *) 0x0A40) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0B00) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0B10) /* 16-bit Timer Type B */ +#define TCB2 (*(TCB_t *) 0x0B20) /* 16-bit Timer Type B */ +#define TCB3 (*(TCB_t *) 0x0B30) /* 16-bit Timer Type B */ +#define TCB4 (*(TCB_t *) 0x0B40) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0B80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define LOCK (*(LOCK_t *) 0x1040) /* Lockbits */ +#define FUSE (*(FUSE_t *) 0x1050) /* Fuses */ +#define USERROW (*(USERROW_t *) 0x1080) /* User Row */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* VPORT (VPORTD) - Virtual Ports */ +#define VPORTD_DIR _SFR_MEM8(0x000C) +#define VPORTD_OUT _SFR_MEM8(0x000D) +#define VPORTD_IN _SFR_MEM8(0x000E) +#define VPORTD_INTFLAGS _SFR_MEM8(0x000F) + + +/* VPORT (VPORTE) - Virtual Ports */ +#define VPORTE_DIR _SFR_MEM8(0x0010) +#define VPORTE_OUT _SFR_MEM8(0x0011) +#define VPORTE_IN _SFR_MEM8(0x0012) +#define VPORTE_INTFLAGS _SFR_MEM8(0x0013) + + +/* VPORT (VPORTF) - Virtual Ports */ +#define VPORTF_DIR _SFR_MEM8(0x0014) +#define VPORTF_OUT _SFR_MEM8(0x0015) +#define VPORTF_IN _SFR_MEM8(0x0016) +#define VPORTF_INTFLAGS _SFR_MEM8(0x0017) + + +/* VPORT (VPORTG) - Virtual Ports */ +#define VPORTG_DIR _SFR_MEM8(0x0018) +#define VPORTG_OUT _SFR_MEM8(0x0019) +#define VPORTG_IN _SFR_MEM8(0x001A) +#define VPORTG_INTFLAGS _SFR_MEM8(0x001B) + + +/* GPR - General Purpose Registers */ +#define GPR_GPR0 _SFR_MEM8(0x001C) +#define GPR_GPR1 _SFR_MEM8(0x001D) +#define GPR_GPR2 _SFR_MEM8(0x001E) +#define GPR_GPR3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) +#define SLPCTRL_VREGCTRL _SFR_MEM8(0x0051) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSCHFCTRLA _SFR_MEM8(0x0068) +#define CLKCTRL_OSCHFTUNE _SFR_MEM8(0x0069) +#define CLKCTRL_PLLCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_ADC0REF _SFR_MEM8(0x00A0) +#define VREF_DAC0REF _SFR_MEM8(0x00A2) +#define VREF_ACREF _SFR_MEM8(0x00A4) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CALIB _SFR_MEM8(0x0146) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_SEQCTRL1 _SFR_MEM8(0x01C2) +#define CCL_SEQCTRL2 _SFR_MEM8(0x01C3) +#define CCL_INTCTRL0 _SFR_MEM8(0x01C5) +#define CCL_INTCTRL1 _SFR_MEM8(0x01C6) +#define CCL_INTFLAGS _SFR_MEM8(0x01C7) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C8) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C9) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01CA) +#define CCL_TRUTH0 _SFR_MEM8(0x01CB) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01CC) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CD) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CE) +#define CCL_TRUTH1 _SFR_MEM8(0x01CF) +#define CCL_LUT2CTRLA _SFR_MEM8(0x01D0) +#define CCL_LUT2CTRLB _SFR_MEM8(0x01D1) +#define CCL_LUT2CTRLC _SFR_MEM8(0x01D2) +#define CCL_TRUTH2 _SFR_MEM8(0x01D3) +#define CCL_LUT3CTRLA _SFR_MEM8(0x01D4) +#define CCL_LUT3CTRLB _SFR_MEM8(0x01D5) +#define CCL_LUT3CTRLC _SFR_MEM8(0x01D6) +#define CCL_TRUTH3 _SFR_MEM8(0x01D7) +#define CCL_LUT4CTRLA _SFR_MEM8(0x01D8) +#define CCL_LUT4CTRLB _SFR_MEM8(0x01D9) +#define CCL_LUT4CTRLC _SFR_MEM8(0x01DA) +#define CCL_TRUTH4 _SFR_MEM8(0x01DB) +#define CCL_LUT5CTRLA _SFR_MEM8(0x01DC) +#define CCL_LUT5CTRLB _SFR_MEM8(0x01DD) +#define CCL_LUT5CTRLC _SFR_MEM8(0x01DE) +#define CCL_TRUTH5 _SFR_MEM8(0x01DF) + + +/* EVSYS - Event System */ +#define EVSYS_SWEVENTA _SFR_MEM8(0x0200) +#define EVSYS_SWEVENTB _SFR_MEM8(0x0201) +#define EVSYS_CHANNEL0 _SFR_MEM8(0x0210) +#define EVSYS_CHANNEL1 _SFR_MEM8(0x0211) +#define EVSYS_CHANNEL2 _SFR_MEM8(0x0212) +#define EVSYS_CHANNEL3 _SFR_MEM8(0x0213) +#define EVSYS_CHANNEL4 _SFR_MEM8(0x0214) +#define EVSYS_CHANNEL5 _SFR_MEM8(0x0215) +#define EVSYS_CHANNEL6 _SFR_MEM8(0x0216) +#define EVSYS_CHANNEL7 _SFR_MEM8(0x0217) +#define EVSYS_CHANNEL8 _SFR_MEM8(0x0218) +#define EVSYS_CHANNEL9 _SFR_MEM8(0x0219) +#define EVSYS_USERCCLLUT0A _SFR_MEM8(0x0220) +#define EVSYS_USERCCLLUT0B _SFR_MEM8(0x0221) +#define EVSYS_USERCCLLUT1A _SFR_MEM8(0x0222) +#define EVSYS_USERCCLLUT1B _SFR_MEM8(0x0223) +#define EVSYS_USERCCLLUT2A _SFR_MEM8(0x0224) +#define EVSYS_USERCCLLUT2B _SFR_MEM8(0x0225) +#define EVSYS_USERCCLLUT3A _SFR_MEM8(0x0226) +#define EVSYS_USERCCLLUT3B _SFR_MEM8(0x0227) +#define EVSYS_USERCCLLUT4A _SFR_MEM8(0x0228) +#define EVSYS_USERCCLLUT4B _SFR_MEM8(0x0229) +#define EVSYS_USERCCLLUT5A _SFR_MEM8(0x022A) +#define EVSYS_USERCCLLUT5B _SFR_MEM8(0x022B) +#define EVSYS_USERADC0START _SFR_MEM8(0x022C) +#define EVSYS_USERPTCSTART _SFR_MEM8(0x022D) +#define EVSYS_USEREVSYSEVOUTA _SFR_MEM8(0x022E) +#define EVSYS_USEREVSYSEVOUTB _SFR_MEM8(0x022F) +#define EVSYS_USEREVSYSEVOUTC _SFR_MEM8(0x0230) +#define EVSYS_USEREVSYSEVOUTD _SFR_MEM8(0x0231) +#define EVSYS_USEREVSYSEVOUTE _SFR_MEM8(0x0232) +#define EVSYS_USEREVSYSEVOUTF _SFR_MEM8(0x0233) +#define EVSYS_USEREVSYSEVOUTG _SFR_MEM8(0x0234) +#define EVSYS_USERUSART0IRDA _SFR_MEM8(0x0235) +#define EVSYS_USERUSART1IRDA _SFR_MEM8(0x0236) +#define EVSYS_USERUSART2IRDA _SFR_MEM8(0x0237) +#define EVSYS_USERUSART3IRDA _SFR_MEM8(0x0238) +#define EVSYS_USERUSART4IRDA _SFR_MEM8(0x0239) +#define EVSYS_USERUSART5IRDA _SFR_MEM8(0x023A) +#define EVSYS_USERTCA0CNTA _SFR_MEM8(0x023B) +#define EVSYS_USERTCA0CNTB _SFR_MEM8(0x023C) +#define EVSYS_USERTCA1CNTA _SFR_MEM8(0x023D) +#define EVSYS_USERTCA1CNTB _SFR_MEM8(0x023E) +#define EVSYS_USERTCB0CAPT _SFR_MEM8(0x023F) +#define EVSYS_USERTCB0COUNT _SFR_MEM8(0x0240) +#define EVSYS_USERTCB1CAPT _SFR_MEM8(0x0241) +#define EVSYS_USERTCB1COUNT _SFR_MEM8(0x0242) +#define EVSYS_USERTCB2CAPT _SFR_MEM8(0x0243) +#define EVSYS_USERTCB2COUNT _SFR_MEM8(0x0244) +#define EVSYS_USERTCB3CAPT _SFR_MEM8(0x0245) +#define EVSYS_USERTCB3COUNT _SFR_MEM8(0x0246) +#define EVSYS_USERTCB4CAPT _SFR_MEM8(0x0247) +#define EVSYS_USERTCB4COUNT _SFR_MEM8(0x0248) +#define EVSYS_USERTCD0INPUTA _SFR_MEM8(0x0249) +#define EVSYS_USERTCD0INPUTB _SFR_MEM8(0x024A) +#define EVSYS_USEROSCTEST _SFR_MEM8(0x024B) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PORTCTRL _SFR_MEM8(0x040A) +#define PORTA_PINCONFIG _SFR_MEM8(0x040B) +#define PORTA_PINCTRLUPD _SFR_MEM8(0x040C) +#define PORTA_PINCTRLSET _SFR_MEM8(0x040D) +#define PORTA_PINCTRLCLR _SFR_MEM8(0x040E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PORTCTRL _SFR_MEM8(0x042A) +#define PORTB_PINCONFIG _SFR_MEM8(0x042B) +#define PORTB_PINCTRLUPD _SFR_MEM8(0x042C) +#define PORTB_PINCTRLSET _SFR_MEM8(0x042D) +#define PORTB_PINCTRLCLR _SFR_MEM8(0x042E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PORTCTRL _SFR_MEM8(0x044A) +#define PORTC_PINCONFIG _SFR_MEM8(0x044B) +#define PORTC_PINCTRLUPD _SFR_MEM8(0x044C) +#define PORTC_PINCTRLSET _SFR_MEM8(0x044D) +#define PORTC_PINCTRLCLR _SFR_MEM8(0x044E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* PORT (PORTD) - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0460) +#define PORTD_DIRSET _SFR_MEM8(0x0461) +#define PORTD_DIRCLR _SFR_MEM8(0x0462) +#define PORTD_DIRTGL _SFR_MEM8(0x0463) +#define PORTD_OUT _SFR_MEM8(0x0464) +#define PORTD_OUTSET _SFR_MEM8(0x0465) +#define PORTD_OUTCLR _SFR_MEM8(0x0466) +#define PORTD_OUTTGL _SFR_MEM8(0x0467) +#define PORTD_IN _SFR_MEM8(0x0468) +#define PORTD_INTFLAGS _SFR_MEM8(0x0469) +#define PORTD_PORTCTRL _SFR_MEM8(0x046A) +#define PORTD_PINCONFIG _SFR_MEM8(0x046B) +#define PORTD_PINCTRLUPD _SFR_MEM8(0x046C) +#define PORTD_PINCTRLSET _SFR_MEM8(0x046D) +#define PORTD_PINCTRLCLR _SFR_MEM8(0x046E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0470) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0471) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0472) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0473) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0474) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0475) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0476) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0477) + + +/* PORT (PORTE) - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0480) +#define PORTE_DIRSET _SFR_MEM8(0x0481) +#define PORTE_DIRCLR _SFR_MEM8(0x0482) +#define PORTE_DIRTGL _SFR_MEM8(0x0483) +#define PORTE_OUT _SFR_MEM8(0x0484) +#define PORTE_OUTSET _SFR_MEM8(0x0485) +#define PORTE_OUTCLR _SFR_MEM8(0x0486) +#define PORTE_OUTTGL _SFR_MEM8(0x0487) +#define PORTE_IN _SFR_MEM8(0x0488) +#define PORTE_INTFLAGS _SFR_MEM8(0x0489) +#define PORTE_PORTCTRL _SFR_MEM8(0x048A) +#define PORTE_PINCONFIG _SFR_MEM8(0x048B) +#define PORTE_PINCTRLUPD _SFR_MEM8(0x048C) +#define PORTE_PINCTRLSET _SFR_MEM8(0x048D) +#define PORTE_PINCTRLCLR _SFR_MEM8(0x048E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0490) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0491) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0492) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0493) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0494) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0495) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0496) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0497) + + +/* PORT (PORTF) - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x04A0) +#define PORTF_DIRSET _SFR_MEM8(0x04A1) +#define PORTF_DIRCLR _SFR_MEM8(0x04A2) +#define PORTF_DIRTGL _SFR_MEM8(0x04A3) +#define PORTF_OUT _SFR_MEM8(0x04A4) +#define PORTF_OUTSET _SFR_MEM8(0x04A5) +#define PORTF_OUTCLR _SFR_MEM8(0x04A6) +#define PORTF_OUTTGL _SFR_MEM8(0x04A7) +#define PORTF_IN _SFR_MEM8(0x04A8) +#define PORTF_INTFLAGS _SFR_MEM8(0x04A9) +#define PORTF_PORTCTRL _SFR_MEM8(0x04AA) +#define PORTF_PINCONFIG _SFR_MEM8(0x04AB) +#define PORTF_PINCTRLUPD _SFR_MEM8(0x04AC) +#define PORTF_PINCTRLSET _SFR_MEM8(0x04AD) +#define PORTF_PINCTRLCLR _SFR_MEM8(0x04AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x04B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x04B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x04B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x04B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x04B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x04B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x04B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x04B7) + + +/* PORT (PORTG) - I/O Ports */ +#define PORTG_DIR _SFR_MEM8(0x04C0) +#define PORTG_DIRSET _SFR_MEM8(0x04C1) +#define PORTG_DIRCLR _SFR_MEM8(0x04C2) +#define PORTG_DIRTGL _SFR_MEM8(0x04C3) +#define PORTG_OUT _SFR_MEM8(0x04C4) +#define PORTG_OUTSET _SFR_MEM8(0x04C5) +#define PORTG_OUTCLR _SFR_MEM8(0x04C6) +#define PORTG_OUTTGL _SFR_MEM8(0x04C7) +#define PORTG_IN _SFR_MEM8(0x04C8) +#define PORTG_INTFLAGS _SFR_MEM8(0x04C9) +#define PORTG_PORTCTRL _SFR_MEM8(0x04CA) +#define PORTG_PINCONFIG _SFR_MEM8(0x04CB) +#define PORTG_PINCTRLUPD _SFR_MEM8(0x04CC) +#define PORTG_PINCTRLSET _SFR_MEM8(0x04CD) +#define PORTG_PINCTRLCLR _SFR_MEM8(0x04CE) +#define PORTG_PIN0CTRL _SFR_MEM8(0x04D0) +#define PORTG_PIN1CTRL _SFR_MEM8(0x04D1) +#define PORTG_PIN2CTRL _SFR_MEM8(0x04D2) +#define PORTG_PIN3CTRL _SFR_MEM8(0x04D3) +#define PORTG_PIN4CTRL _SFR_MEM8(0x04D4) +#define PORTG_PIN5CTRL _SFR_MEM8(0x04D5) +#define PORTG_PIN6CTRL _SFR_MEM8(0x04D6) +#define PORTG_PIN7CTRL _SFR_MEM8(0x04D7) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_EVSYSROUTEA _SFR_MEM8(0x05E0) +#define PORTMUX_CCLROUTEA _SFR_MEM8(0x05E1) +#define PORTMUX_USARTROUTEA _SFR_MEM8(0x05E2) +#define PORTMUX_USARTROUTEB _SFR_MEM8(0x05E3) +#define PORTMUX_SPIROUTEA _SFR_MEM8(0x05E4) +#define PORTMUX_TWIROUTEA _SFR_MEM8(0x05E5) +#define PORTMUX_TCAROUTEA _SFR_MEM8(0x05E6) +#define PORTMUX_TCBROUTEA _SFR_MEM8(0x05E7) +#define PORTMUX_TCDROUTEA _SFR_MEM8(0x05E8) +#define PORTMUX_ACROUTEA _SFR_MEM8(0x05E9) +#define PORTMUX_ZCDROUTEA _SFR_MEM8(0x05EA) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0608) +#define ADC0_MUXNEG _SFR_MEM8(0x0609) +#define ADC0_COMMAND _SFR_MEM8(0x060A) +#define ADC0_EVCTRL _SFR_MEM8(0x060B) +#define ADC0_INTCTRL _SFR_MEM8(0x060C) +#define ADC0_INTFLAGS _SFR_MEM8(0x060D) +#define ADC0_DBGCTRL _SFR_MEM8(0x060E) +#define ADC0_TEMP _SFR_MEM8(0x060F) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_CTRLB _SFR_MEM8(0x0681) +#define AC0_MUXCTRL _SFR_MEM8(0x0682) +#define AC0_DACREF _SFR_MEM8(0x0685) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* AC (AC1) - Analog Comparator */ +#define AC1_CTRLA _SFR_MEM8(0x0688) +#define AC1_CTRLB _SFR_MEM8(0x0689) +#define AC1_MUXCTRL _SFR_MEM8(0x068A) +#define AC1_DACREF _SFR_MEM8(0x068D) +#define AC1_INTCTRL _SFR_MEM8(0x068E) +#define AC1_STATUS _SFR_MEM8(0x068F) + + +/* AC (AC2) - Analog Comparator */ +#define AC2_CTRLA _SFR_MEM8(0x0690) +#define AC2_CTRLB _SFR_MEM8(0x0691) +#define AC2_MUXCTRL _SFR_MEM8(0x0692) +#define AC2_DACREF _SFR_MEM8(0x0695) +#define AC2_INTCTRL _SFR_MEM8(0x0696) +#define AC2_STATUS _SFR_MEM8(0x0697) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x06A0) +#define DAC0_DATA _SFR_MEM16(0x06A2) +#define DAC0_DATAL _SFR_MEM8(0x06A2) +#define DAC0_DATAH _SFR_MEM8(0x06A3) + + +/* ZCD (ZCD0) - Zero Cross Detect */ +#define ZCD0_CTRLA _SFR_MEM8(0x06C0) +#define ZCD0_INTCTRL _SFR_MEM8(0x06C2) +#define ZCD0_STATUS _SFR_MEM8(0x06C3) + + +/* ZCD (ZCD1) - Zero Cross Detect */ +#define ZCD1_CTRLA _SFR_MEM8(0x06C8) +#define ZCD1_INTCTRL _SFR_MEM8(0x06CA) +#define ZCD1_STATUS _SFR_MEM8(0x06CB) + + +/* ZCD (ZCD2) - Zero Cross Detect */ +#define ZCD2_CTRLA _SFR_MEM8(0x06D0) +#define ZCD2_INTCTRL _SFR_MEM8(0x06D2) +#define ZCD2_STATUS _SFR_MEM8(0x06D3) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_CTRLD _SFR_MEM8(0x080A) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* USART (USART1) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1_RXDATAL _SFR_MEM8(0x0820) +#define USART1_RXDATAH _SFR_MEM8(0x0821) +#define USART1_TXDATAL _SFR_MEM8(0x0822) +#define USART1_TXDATAH _SFR_MEM8(0x0823) +#define USART1_STATUS _SFR_MEM8(0x0824) +#define USART1_CTRLA _SFR_MEM8(0x0825) +#define USART1_CTRLB _SFR_MEM8(0x0826) +#define USART1_CTRLC _SFR_MEM8(0x0827) +#define USART1_BAUD _SFR_MEM16(0x0828) +#define USART1_BAUDL _SFR_MEM8(0x0828) +#define USART1_BAUDH _SFR_MEM8(0x0829) +#define USART1_CTRLD _SFR_MEM8(0x082A) +#define USART1_DBGCTRL _SFR_MEM8(0x082B) +#define USART1_EVCTRL _SFR_MEM8(0x082C) +#define USART1_TXPLCTRL _SFR_MEM8(0x082D) +#define USART1_RXPLCTRL _SFR_MEM8(0x082E) + + +/* USART (USART2) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2_RXDATAL _SFR_MEM8(0x0840) +#define USART2_RXDATAH _SFR_MEM8(0x0841) +#define USART2_TXDATAL _SFR_MEM8(0x0842) +#define USART2_TXDATAH _SFR_MEM8(0x0843) +#define USART2_STATUS _SFR_MEM8(0x0844) +#define USART2_CTRLA _SFR_MEM8(0x0845) +#define USART2_CTRLB _SFR_MEM8(0x0846) +#define USART2_CTRLC _SFR_MEM8(0x0847) +#define USART2_BAUD _SFR_MEM16(0x0848) +#define USART2_BAUDL _SFR_MEM8(0x0848) +#define USART2_BAUDH _SFR_MEM8(0x0849) +#define USART2_CTRLD _SFR_MEM8(0x084A) +#define USART2_DBGCTRL _SFR_MEM8(0x084B) +#define USART2_EVCTRL _SFR_MEM8(0x084C) +#define USART2_TXPLCTRL _SFR_MEM8(0x084D) +#define USART2_RXPLCTRL _SFR_MEM8(0x084E) + + +/* USART (USART3) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART3_RXDATAL _SFR_MEM8(0x0860) +#define USART3_RXDATAH _SFR_MEM8(0x0861) +#define USART3_TXDATAL _SFR_MEM8(0x0862) +#define USART3_TXDATAH _SFR_MEM8(0x0863) +#define USART3_STATUS _SFR_MEM8(0x0864) +#define USART3_CTRLA _SFR_MEM8(0x0865) +#define USART3_CTRLB _SFR_MEM8(0x0866) +#define USART3_CTRLC _SFR_MEM8(0x0867) +#define USART3_BAUD _SFR_MEM16(0x0868) +#define USART3_BAUDL _SFR_MEM8(0x0868) +#define USART3_BAUDH _SFR_MEM8(0x0869) +#define USART3_CTRLD _SFR_MEM8(0x086A) +#define USART3_DBGCTRL _SFR_MEM8(0x086B) +#define USART3_EVCTRL _SFR_MEM8(0x086C) +#define USART3_TXPLCTRL _SFR_MEM8(0x086D) +#define USART3_RXPLCTRL _SFR_MEM8(0x086E) + + +/* USART (USART4) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART4_RXDATAL _SFR_MEM8(0x0880) +#define USART4_RXDATAH _SFR_MEM8(0x0881) +#define USART4_TXDATAL _SFR_MEM8(0x0882) +#define USART4_TXDATAH _SFR_MEM8(0x0883) +#define USART4_STATUS _SFR_MEM8(0x0884) +#define USART4_CTRLA _SFR_MEM8(0x0885) +#define USART4_CTRLB _SFR_MEM8(0x0886) +#define USART4_CTRLC _SFR_MEM8(0x0887) +#define USART4_BAUD _SFR_MEM16(0x0888) +#define USART4_BAUDL _SFR_MEM8(0x0888) +#define USART4_BAUDH _SFR_MEM8(0x0889) +#define USART4_CTRLD _SFR_MEM8(0x088A) +#define USART4_DBGCTRL _SFR_MEM8(0x088B) +#define USART4_EVCTRL _SFR_MEM8(0x088C) +#define USART4_TXPLCTRL _SFR_MEM8(0x088D) +#define USART4_RXPLCTRL _SFR_MEM8(0x088E) + + +/* USART (USART5) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART5_RXDATAL _SFR_MEM8(0x08A0) +#define USART5_RXDATAH _SFR_MEM8(0x08A1) +#define USART5_TXDATAL _SFR_MEM8(0x08A2) +#define USART5_TXDATAH _SFR_MEM8(0x08A3) +#define USART5_STATUS _SFR_MEM8(0x08A4) +#define USART5_CTRLA _SFR_MEM8(0x08A5) +#define USART5_CTRLB _SFR_MEM8(0x08A6) +#define USART5_CTRLC _SFR_MEM8(0x08A7) +#define USART5_BAUD _SFR_MEM16(0x08A8) +#define USART5_BAUDL _SFR_MEM8(0x08A8) +#define USART5_BAUDH _SFR_MEM8(0x08A9) +#define USART5_CTRLD _SFR_MEM8(0x08AA) +#define USART5_DBGCTRL _SFR_MEM8(0x08AB) +#define USART5_EVCTRL _SFR_MEM8(0x08AC) +#define USART5_TXPLCTRL _SFR_MEM8(0x08AD) +#define USART5_RXPLCTRL _SFR_MEM8(0x08AE) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0900) +#define TWI0_DUALCTRL _SFR_MEM8(0x0901) +#define TWI0_DBGCTRL _SFR_MEM8(0x0902) +#define TWI0_MCTRLA _SFR_MEM8(0x0903) +#define TWI0_MCTRLB _SFR_MEM8(0x0904) +#define TWI0_MSTATUS _SFR_MEM8(0x0905) +#define TWI0_MBAUD _SFR_MEM8(0x0906) +#define TWI0_MADDR _SFR_MEM8(0x0907) +#define TWI0_MDATA _SFR_MEM8(0x0908) +#define TWI0_SCTRLA _SFR_MEM8(0x0909) +#define TWI0_SCTRLB _SFR_MEM8(0x090A) +#define TWI0_SSTATUS _SFR_MEM8(0x090B) +#define TWI0_SADDR _SFR_MEM8(0x090C) +#define TWI0_SDATA _SFR_MEM8(0x090D) +#define TWI0_SADDRMASK _SFR_MEM8(0x090E) + + +/* TWI (TWI1) - Two-Wire Interface */ +#define TWI1_CTRLA _SFR_MEM8(0x0920) +#define TWI1_DUALCTRL _SFR_MEM8(0x0921) +#define TWI1_DBGCTRL _SFR_MEM8(0x0922) +#define TWI1_MCTRLA _SFR_MEM8(0x0923) +#define TWI1_MCTRLB _SFR_MEM8(0x0924) +#define TWI1_MSTATUS _SFR_MEM8(0x0925) +#define TWI1_MBAUD _SFR_MEM8(0x0926) +#define TWI1_MADDR _SFR_MEM8(0x0927) +#define TWI1_MDATA _SFR_MEM8(0x0928) +#define TWI1_SCTRLA _SFR_MEM8(0x0929) +#define TWI1_SCTRLB _SFR_MEM8(0x092A) +#define TWI1_SSTATUS _SFR_MEM8(0x092B) +#define TWI1_SADDR _SFR_MEM8(0x092C) +#define TWI1_SDATA _SFR_MEM8(0x092D) +#define TWI1_SADDRMASK _SFR_MEM8(0x092E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0940) +#define SPI0_CTRLB _SFR_MEM8(0x0941) +#define SPI0_INTCTRL _SFR_MEM8(0x0942) +#define SPI0_INTFLAGS _SFR_MEM8(0x0943) +#define SPI0_DATA _SFR_MEM8(0x0944) + + +/* SPI (SPI1) - Serial Peripheral Interface */ +#define SPI1_CTRLA _SFR_MEM8(0x0960) +#define SPI1_CTRLB _SFR_MEM8(0x0961) +#define SPI1_INTCTRL _SFR_MEM8(0x0962) +#define SPI1_INTFLAGS _SFR_MEM8(0x0963) +#define SPI1_DATA _SFR_MEM8(0x0964) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCA (TCA1) - 16-bit Timer/Counter Type A */ +#define TCA1_SINGLE_CTRLA _SFR_MEM8(0x0A40) +#define TCA1_SINGLE_CTRLB _SFR_MEM8(0x0A41) +#define TCA1_SINGLE_CTRLC _SFR_MEM8(0x0A42) +#define TCA1_SINGLE_CTRLD _SFR_MEM8(0x0A43) +#define TCA1_SINGLE_CTRLECLR _SFR_MEM8(0x0A44) +#define TCA1_SINGLE_CTRLESET _SFR_MEM8(0x0A45) +#define TCA1_SINGLE_CTRLFCLR _SFR_MEM8(0x0A46) +#define TCA1_SINGLE_CTRLFSET _SFR_MEM8(0x0A47) +#define TCA1_SINGLE_EVCTRL _SFR_MEM8(0x0A49) +#define TCA1_SINGLE_INTCTRL _SFR_MEM8(0x0A4A) +#define TCA1_SINGLE_INTFLAGS _SFR_MEM8(0x0A4B) +#define TCA1_SINGLE_DBGCTRL _SFR_MEM8(0x0A4E) +#define TCA1_SINGLE_TEMP _SFR_MEM8(0x0A4F) +#define TCA1_SINGLE_CNT _SFR_MEM16(0x0A60) +#define TCA1_SINGLE_PER _SFR_MEM16(0x0A66) +#define TCA1_SINGLE_CMP0 _SFR_MEM16(0x0A68) +#define TCA1_SINGLE_CMP1 _SFR_MEM16(0x0A6A) +#define TCA1_SINGLE_CMP2 _SFR_MEM16(0x0A6C) +#define TCA1_SINGLE_PERBUF _SFR_MEM16(0x0A76) +#define TCA1_SINGLE_CMP0BUF _SFR_MEM16(0x0A78) +#define TCA1_SINGLE_CMP1BUF _SFR_MEM16(0x0A7A) +#define TCA1_SINGLE_CMP2BUF _SFR_MEM16(0x0A7C) + + +#define TCA1_SPLIT_CTRLA _SFR_MEM8(0x0A40) +#define TCA1_SPLIT_CTRLB _SFR_MEM8(0x0A41) +#define TCA1_SPLIT_CTRLC _SFR_MEM8(0x0A42) +#define TCA1_SPLIT_CTRLD _SFR_MEM8(0x0A43) +#define TCA1_SPLIT_CTRLECLR _SFR_MEM8(0x0A44) +#define TCA1_SPLIT_CTRLESET _SFR_MEM8(0x0A45) +#define TCA1_SPLIT_INTCTRL _SFR_MEM8(0x0A4A) +#define TCA1_SPLIT_INTFLAGS _SFR_MEM8(0x0A4B) +#define TCA1_SPLIT_DBGCTRL _SFR_MEM8(0x0A4E) +#define TCA1_SPLIT_LCNT _SFR_MEM8(0x0A60) +#define TCA1_SPLIT_HCNT _SFR_MEM8(0x0A61) +#define TCA1_SPLIT_LPER _SFR_MEM8(0x0A66) +#define TCA1_SPLIT_HPER _SFR_MEM8(0x0A67) +#define TCA1_SPLIT_LCMP0 _SFR_MEM8(0x0A68) +#define TCA1_SPLIT_HCMP0 _SFR_MEM8(0x0A69) +#define TCA1_SPLIT_LCMP1 _SFR_MEM8(0x0A6A) +#define TCA1_SPLIT_HCMP1 _SFR_MEM8(0x0A6B) +#define TCA1_SPLIT_LCMP2 _SFR_MEM8(0x0A6C) +#define TCA1_SPLIT_HCMP2 _SFR_MEM8(0x0A6D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0B00) +#define TCB0_CTRLB _SFR_MEM8(0x0B01) +#define TCB0_EVCTRL _SFR_MEM8(0x0B04) +#define TCB0_INTCTRL _SFR_MEM8(0x0B05) +#define TCB0_INTFLAGS _SFR_MEM8(0x0B06) +#define TCB0_STATUS _SFR_MEM8(0x0B07) +#define TCB0_DBGCTRL _SFR_MEM8(0x0B08) +#define TCB0_TEMP _SFR_MEM8(0x0B09) +#define TCB0_CNT _SFR_MEM16(0x0B0A) +#define TCB0_CNTL _SFR_MEM8(0x0B0A) +#define TCB0_CNTH _SFR_MEM8(0x0B0B) +#define TCB0_CCMP _SFR_MEM16(0x0B0C) +#define TCB0_CCMPL _SFR_MEM8(0x0B0C) +#define TCB0_CCMPH _SFR_MEM8(0x0B0D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0B10) +#define TCB1_CTRLB _SFR_MEM8(0x0B11) +#define TCB1_EVCTRL _SFR_MEM8(0x0B14) +#define TCB1_INTCTRL _SFR_MEM8(0x0B15) +#define TCB1_INTFLAGS _SFR_MEM8(0x0B16) +#define TCB1_STATUS _SFR_MEM8(0x0B17) +#define TCB1_DBGCTRL _SFR_MEM8(0x0B18) +#define TCB1_TEMP _SFR_MEM8(0x0B19) +#define TCB1_CNT _SFR_MEM16(0x0B1A) +#define TCB1_CNTL _SFR_MEM8(0x0B1A) +#define TCB1_CNTH _SFR_MEM8(0x0B1B) +#define TCB1_CCMP _SFR_MEM16(0x0B1C) +#define TCB1_CCMPL _SFR_MEM8(0x0B1C) +#define TCB1_CCMPH _SFR_MEM8(0x0B1D) + + +/* TCB (TCB2) - 16-bit Timer Type B */ +#define TCB2_CTRLA _SFR_MEM8(0x0B20) +#define TCB2_CTRLB _SFR_MEM8(0x0B21) +#define TCB2_EVCTRL _SFR_MEM8(0x0B24) +#define TCB2_INTCTRL _SFR_MEM8(0x0B25) +#define TCB2_INTFLAGS _SFR_MEM8(0x0B26) +#define TCB2_STATUS _SFR_MEM8(0x0B27) +#define TCB2_DBGCTRL _SFR_MEM8(0x0B28) +#define TCB2_TEMP _SFR_MEM8(0x0B29) +#define TCB2_CNT _SFR_MEM16(0x0B2A) +#define TCB2_CNTL _SFR_MEM8(0x0B2A) +#define TCB2_CNTH _SFR_MEM8(0x0B2B) +#define TCB2_CCMP _SFR_MEM16(0x0B2C) +#define TCB2_CCMPL _SFR_MEM8(0x0B2C) +#define TCB2_CCMPH _SFR_MEM8(0x0B2D) + + +/* TCB (TCB3) - 16-bit Timer Type B */ +#define TCB3_CTRLA _SFR_MEM8(0x0B30) +#define TCB3_CTRLB _SFR_MEM8(0x0B31) +#define TCB3_EVCTRL _SFR_MEM8(0x0B34) +#define TCB3_INTCTRL _SFR_MEM8(0x0B35) +#define TCB3_INTFLAGS _SFR_MEM8(0x0B36) +#define TCB3_STATUS _SFR_MEM8(0x0B37) +#define TCB3_DBGCTRL _SFR_MEM8(0x0B38) +#define TCB3_TEMP _SFR_MEM8(0x0B39) +#define TCB3_CNT _SFR_MEM16(0x0B3A) +#define TCB3_CNTL _SFR_MEM8(0x0B3A) +#define TCB3_CNTH _SFR_MEM8(0x0B3B) +#define TCB3_CCMP _SFR_MEM16(0x0B3C) +#define TCB3_CCMPL _SFR_MEM8(0x0B3C) +#define TCB3_CCMPH _SFR_MEM8(0x0B3D) + + +/* TCB (TCB4) - 16-bit Timer Type B */ +#define TCB4_CTRLA _SFR_MEM8(0x0B40) +#define TCB4_CTRLB _SFR_MEM8(0x0B41) +#define TCB4_EVCTRL _SFR_MEM8(0x0B44) +#define TCB4_INTCTRL _SFR_MEM8(0x0B45) +#define TCB4_INTFLAGS _SFR_MEM8(0x0B46) +#define TCB4_STATUS _SFR_MEM8(0x0B47) +#define TCB4_DBGCTRL _SFR_MEM8(0x0B48) +#define TCB4_TEMP _SFR_MEM8(0x0B49) +#define TCB4_CNT _SFR_MEM16(0x0B4A) +#define TCB4_CNTL _SFR_MEM8(0x0B4A) +#define TCB4_CNTH _SFR_MEM8(0x0B4B) +#define TCB4_CCMP _SFR_MEM16(0x0B4C) +#define TCB4_CCMPL _SFR_MEM8(0x0B4C) +#define TCB4_CCMPH _SFR_MEM8(0x0B4D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0B80) +#define TCD0_CTRLB _SFR_MEM8(0x0B81) +#define TCD0_CTRLC _SFR_MEM8(0x0B82) +#define TCD0_CTRLD _SFR_MEM8(0x0B83) +#define TCD0_CTRLE _SFR_MEM8(0x0B84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0B88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0B89) +#define TCD0_INTCTRL _SFR_MEM8(0x0B8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0B8D) +#define TCD0_STATUS _SFR_MEM8(0x0B8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0B90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0B91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0B92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0B94) +#define TCD0_DLYVAL _SFR_MEM8(0x0B95) +#define TCD0_DITCTRL _SFR_MEM8(0x0B98) +#define TCD0_DITVAL _SFR_MEM8(0x0B99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0B9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0BA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0BA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0BA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0BA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0BA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0BA5) +#define TCD0_CMPASET _SFR_MEM16(0x0BA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0BA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0BA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0BAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0BAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0BAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0BAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0BAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0BAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0BAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0BAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0BAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_OCDMCTRL _SFR_MEM8(0x0F18) +#define SYSCFG_OCDMSTATUS _SFR_MEM8(0x0F19) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM32(0x1008) +#define NVMCTRL_ADDR0 _SFR_MEM8(0x1008) +#define NVMCTRL_ADDR1 _SFR_MEM8(0x1009) +#define NVMCTRL_ADDR2 _SFR_MEM8(0x100A) +#define NVMCTRL_ADDR3 _SFR_MEM8(0x100B) + + +/* LOCK - Lockbits */ +#define LOCK_KEY _SFR_MEM32(0x1040) +#define LOCK_KEY0 _SFR_MEM8(0x1040) +#define LOCK_KEY1 _SFR_MEM8(0x1041) +#define LOCK_KEY2 _SFR_MEM8(0x1042) +#define LOCK_KEY3 _SFR_MEM8(0x1043) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1050) +#define FUSE_BODCFG _SFR_MEM8(0x1051) +#define FUSE_OSCCFG _SFR_MEM8(0x1052) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1055) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1056) +#define FUSE_CODESIZE _SFR_MEM8(0x1057) +#define FUSE_BOOTSIZE _SFR_MEM8(0x1058) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1080) +#define USERROW_USERROW1 _SFR_MEM8(0x1081) +#define USERROW_USERROW2 _SFR_MEM8(0x1082) +#define USERROW_USERROW3 _SFR_MEM8(0x1083) +#define USERROW_USERROW4 _SFR_MEM8(0x1084) +#define USERROW_USERROW5 _SFR_MEM8(0x1085) +#define USERROW_USERROW6 _SFR_MEM8(0x1086) +#define USERROW_USERROW7 _SFR_MEM8(0x1087) +#define USERROW_USERROW8 _SFR_MEM8(0x1088) +#define USERROW_USERROW9 _SFR_MEM8(0x1089) +#define USERROW_USERROW10 _SFR_MEM8(0x108A) +#define USERROW_USERROW11 _SFR_MEM8(0x108B) +#define USERROW_USERROW12 _SFR_MEM8(0x108C) +#define USERROW_USERROW13 _SFR_MEM8(0x108D) +#define USERROW_USERROW14 _SFR_MEM8(0x108E) +#define USERROW_USERROW15 _SFR_MEM8(0x108F) +#define USERROW_USERROW16 _SFR_MEM8(0x1090) +#define USERROW_USERROW17 _SFR_MEM8(0x1091) +#define USERROW_USERROW18 _SFR_MEM8(0x1092) +#define USERROW_USERROW19 _SFR_MEM8(0x1093) +#define USERROW_USERROW20 _SFR_MEM8(0x1094) +#define USERROW_USERROW21 _SFR_MEM8(0x1095) +#define USERROW_USERROW22 _SFR_MEM8(0x1096) +#define USERROW_USERROW23 _SFR_MEM8(0x1097) +#define USERROW_USERROW24 _SFR_MEM8(0x1098) +#define USERROW_USERROW25 _SFR_MEM8(0x1099) +#define USERROW_USERROW26 _SFR_MEM8(0x109A) +#define USERROW_USERROW27 _SFR_MEM8(0x109B) +#define USERROW_USERROW28 _SFR_MEM8(0x109C) +#define USERROW_USERROW29 _SFR_MEM8(0x109D) +#define USERROW_USERROW30 _SFR_MEM8(0x109E) +#define USERROW_USERROW31 _SFR_MEM8(0x109F) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_TEMPSENSE0 _SFR_MEM16(0x1104) +#define SIGROW_TEMPSENSE0L _SFR_MEM8(0x1104) +#define SIGROW_TEMPSENSE0H _SFR_MEM8(0x1105) +#define SIGROW_TEMPSENSE1 _SFR_MEM16(0x1106) +#define SIGROW_TEMPSENSE1L _SFR_MEM8(0x1106) +#define SIGROW_TEMPSENSE1H _SFR_MEM8(0x1107) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1110) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1111) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1112) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1113) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1114) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1115) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1116) +#define SIGROW_SERNUM7 _SFR_MEM8(0x1117) +#define SIGROW_SERNUM8 _SFR_MEM8(0x1118) +#define SIGROW_SERNUM9 _SFR_MEM8(0x1119) +#define SIGROW_SERNUM10 _SFR_MEM8(0x111A) +#define SIGROW_SERNUM11 _SFR_MEM8(0x111B) +#define SIGROW_SERNUM12 _SFR_MEM8(0x111C) +#define SIGROW_SERNUM13 _SFR_MEM8(0x111D) +#define SIGROW_SERNUM14 _SFR_MEM8(0x111E) +#define SIGROW_SERNUM15 _SFR_MEM8(0x111F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_POWER_gm 0x18 /* Power profile group mask. */ +#define AC_POWER_gp 3 /* Power profile group position. */ +#define AC_POWER0_bm (1<<3) /* Power profile bit 0 mask. */ +#define AC_POWER0_bp 3 /* Power profile bit 0 position. */ +#define AC_POWER1_bm (1<<4) /* Power profile bit 1 mask. */ +#define AC_POWER1_bp 4 /* Power profile bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Pad Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Pad Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_WINSEL_gm 0x03 /* Window selection mode group mask. */ +#define AC_WINSEL_gp 0 /* Window selection mode group position. */ +#define AC_WINSEL0_bm (1<<0) /* Window selection mode bit 0 mask. */ +#define AC_WINSEL0_bp 0 /* Window selection mode bit 0 position. */ +#define AC_WINSEL1_bm (1<<1) /* Window selection mode bit 1 mask. */ +#define AC_WINSEL1_bp 1 /* Window selection mode bit 1 position. */ + +/* AC.MUXCTRL bit masks and bit positions */ +#define AC_MUXNEG_gm 0x07 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* Negative Input MUX Selection bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* Negative Input MUX Selection bit 2 position. */ +#define AC_MUXPOS_gm 0x38 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* Positive Input MUX Selection bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* Positive Input MUX Selection bit 2 position. */ +#define AC_INITVAL_bm 0x40 /* AC Output Initial Value bit mask. */ +#define AC_INITVAL_bp 6 /* AC Output Initial Value bit position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.DACREF bit masks and bit positions */ +#define AC_DACREF_gm 0xFF /* DACREF group mask. */ +#define AC_DACREF_gp 0 /* DACREF group position. */ +#define AC_DACREF0_bm (1<<0) /* DACREF bit 0 mask. */ +#define AC_DACREF0_bp 0 /* DACREF bit 0 position. */ +#define AC_DACREF1_bm (1<<1) /* DACREF bit 1 mask. */ +#define AC_DACREF1_bp 1 /* DACREF bit 1 position. */ +#define AC_DACREF2_bm (1<<2) /* DACREF bit 2 mask. */ +#define AC_DACREF2_bp 2 /* DACREF bit 2 position. */ +#define AC_DACREF3_bm (1<<3) /* DACREF bit 3 mask. */ +#define AC_DACREF3_bp 3 /* DACREF bit 3 position. */ +#define AC_DACREF4_bm (1<<4) /* DACREF bit 4 mask. */ +#define AC_DACREF4_bp 4 /* DACREF bit 4 position. */ +#define AC_DACREF5_bm (1<<5) /* DACREF bit 5 mask. */ +#define AC_DACREF5_bp 5 /* DACREF bit 5 position. */ +#define AC_DACREF6_bm (1<<6) /* DACREF bit 6 mask. */ +#define AC_DACREF6_bp 6 /* DACREF bit 6 position. */ +#define AC_DACREF7_bm (1<<7) /* DACREF bit 7 mask. */ +#define AC_DACREF7_bp 7 /* DACREF bit 7 position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_CMPIF_bm 0x01 /* Analog Comparator Interrupt Flag bit mask. */ +#define AC_CMPIF_bp 0 /* Analog Comparator Interrupt Flag bit position. */ +#define AC_CMPSTATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_CMPSTATE_bp 4 /* Analog Comparator State bit position. */ +#define AC_WINSTATE_gm 0xC0 /* Analog Comparator Window State group mask. */ +#define AC_WINSTATE_gp 6 /* Analog Comparator Window State group position. */ +#define AC_WINSTATE0_bm (1<<6) /* Analog Comparator Window State bit 0 mask. */ +#define AC_WINSTATE0_bp 6 /* Analog Comparator Window State bit 0 position. */ +#define AC_WINSTATE1_bm (1<<7) /* Analog Comparator Window State bit 1 mask. */ +#define AC_WINSTATE1_bp 7 /* Analog Comparator Window State bit 1 position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* Free running mode bit mask. */ +#define ADC_FREERUN_bp 1 /* Free running mode bit position. */ +#define ADC_RESSEL_gm 0x0C /* Resolution selection group mask. */ +#define ADC_RESSEL_gp 2 /* Resolution selection group position. */ +#define ADC_RESSEL0_bm (1<<2) /* Resolution selection bit 0 mask. */ +#define ADC_RESSEL0_bp 2 /* Resolution selection bit 0 position. */ +#define ADC_RESSEL1_bm (1<<3) /* Resolution selection bit 1 mask. */ +#define ADC_RESSEL1_bp 3 /* Resolution selection bit 1 position. */ +#define ADC_LEFTADJ_bm 0x10 /* Left adjust result bit mask. */ +#define ADC_LEFTADJ_bp 4 /* Left adjust result bit position. */ +#define ADC_CONVMODE_bm 0x20 /* Conversion mode bit mask. */ +#define ADC_CONVMODE_bp 5 /* Conversion mode bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x0F /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_PRESC3_bm (1<<3) /* Clock Pre-scaler bit 3 mask. */ +#define ADC_PRESC3_bp 3 /* Clock Pre-scaler bit 3 position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0xFF /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ +#define ADC_SAMPLEN5_bm (1<<5) /* Sample lenght bit 5 mask. */ +#define ADC_SAMPLEN5_bp 5 /* Sample lenght bit 5 position. */ +#define ADC_SAMPLEN6_bm (1<<6) /* Sample lenght bit 6 mask. */ +#define ADC_SAMPLEN6_bp 6 /* Sample lenght bit 6 position. */ +#define ADC_SAMPLEN7_bm (1<<7) /* Sample lenght bit 7 mask. */ +#define ADC_SAMPLEN7_bp 7 /* Sample lenght bit 7 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x7F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ +#define ADC_MUXPOS5_bm (1<<5) /* Analog Channel Selection Bits bit 5 mask. */ +#define ADC_MUXPOS5_bp 5 /* Analog Channel Selection Bits bit 5 position. */ +#define ADC_MUXPOS6_bm (1<<6) /* Analog Channel Selection Bits bit 6 mask. */ +#define ADC_MUXPOS6_bp 6 /* Analog Channel Selection Bits bit 6 position. */ + +/* ADC.MUXNEG bit masks and bit positions */ +#define ADC_MUXNEG_gm 0x7F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXNEG_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXNEG0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXNEG0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXNEG1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXNEG1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXNEG2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXNEG2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXNEG3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXNEG3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXNEG4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXNEG4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ +#define ADC_MUXNEG5_bm (1<<5) /* Analog Channel Selection Bits bit 5 mask. */ +#define ADC_MUXNEG5_bp 5 /* Analog Channel Selection Bits bit 5 position. */ +#define ADC_MUXNEG6_bm (1<<6) /* Analog Channel Selection Bits bit 6 mask. */ +#define ADC_MUXNEG6_bp 6 /* Analog Channel Selection Bits bit 6 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion bit position. */ +#define ADC_SPCONV_bm 0x02 /* Stop Conversion bit mask. */ +#define ADC_SPCONV_bp 1 /* Stop Conversion bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL0_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL0_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL00_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL00_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL01_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL01_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL02_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL02_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.SEQCTRL1 bit masks and bit positions */ +#define CCL_SEQSEL1_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL1_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL10_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL10_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL11_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL11_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL12_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL12_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.SEQCTRL2 bit masks and bit positions */ +#define CCL_SEQSEL2_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL2_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL20_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL20_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL21_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL21_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL22_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL22_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.INTCTRL0 bit masks and bit positions */ +#define CCL_INTMODE0_gm 0x03 /* Interrupt Mode for LUT0 group mask. */ +#define CCL_INTMODE0_gp 0 /* Interrupt Mode for LUT0 group position. */ +#define CCL_INTMODE00_bm (1<<0) /* Interrupt Mode for LUT0 bit 0 mask. */ +#define CCL_INTMODE00_bp 0 /* Interrupt Mode for LUT0 bit 0 position. */ +#define CCL_INTMODE01_bm (1<<1) /* Interrupt Mode for LUT0 bit 1 mask. */ +#define CCL_INTMODE01_bp 1 /* Interrupt Mode for LUT0 bit 1 position. */ +#define CCL_INTMODE1_gm 0x0C /* Interrupt Mode for LUT1 group mask. */ +#define CCL_INTMODE1_gp 2 /* Interrupt Mode for LUT1 group position. */ +#define CCL_INTMODE10_bm (1<<2) /* Interrupt Mode for LUT1 bit 0 mask. */ +#define CCL_INTMODE10_bp 2 /* Interrupt Mode for LUT1 bit 0 position. */ +#define CCL_INTMODE11_bm (1<<3) /* Interrupt Mode for LUT1 bit 1 mask. */ +#define CCL_INTMODE11_bp 3 /* Interrupt Mode for LUT1 bit 1 position. */ +#define CCL_INTMODE2_gm 0x30 /* Interrupt Mode for LUT2 group mask. */ +#define CCL_INTMODE2_gp 4 /* Interrupt Mode for LUT2 group position. */ +#define CCL_INTMODE20_bm (1<<4) /* Interrupt Mode for LUT2 bit 0 mask. */ +#define CCL_INTMODE20_bp 4 /* Interrupt Mode for LUT2 bit 0 position. */ +#define CCL_INTMODE21_bm (1<<5) /* Interrupt Mode for LUT2 bit 1 mask. */ +#define CCL_INTMODE21_bp 5 /* Interrupt Mode for LUT2 bit 1 position. */ +#define CCL_INTMODE3_gm 0xC0 /* Interrupt Mode for LUT3 group mask. */ +#define CCL_INTMODE3_gp 6 /* Interrupt Mode for LUT3 group position. */ +#define CCL_INTMODE30_bm (1<<6) /* Interrupt Mode for LUT3 bit 0 mask. */ +#define CCL_INTMODE30_bp 6 /* Interrupt Mode for LUT3 bit 0 position. */ +#define CCL_INTMODE31_bm (1<<7) /* Interrupt Mode for LUT3 bit 1 mask. */ +#define CCL_INTMODE31_bp 7 /* Interrupt Mode for LUT3 bit 1 position. */ + +/* CCL.INTCTRL1 bit masks and bit positions */ +#define CCL_INTMODE4_gm 0x03 /* Interrupt Mode for LUT4 group mask. */ +#define CCL_INTMODE4_gp 0 /* Interrupt Mode for LUT4 group position. */ +#define CCL_INTMODE40_bm (1<<0) /* Interrupt Mode for LUT4 bit 0 mask. */ +#define CCL_INTMODE40_bp 0 /* Interrupt Mode for LUT4 bit 0 position. */ +#define CCL_INTMODE41_bm (1<<1) /* Interrupt Mode for LUT4 bit 1 mask. */ +#define CCL_INTMODE41_bp 1 /* Interrupt Mode for LUT4 bit 1 position. */ +#define CCL_INTMODE5_gm 0x0C /* Interrupt Mode for LUT5 group mask. */ +#define CCL_INTMODE5_gp 2 /* Interrupt Mode for LUT5 group position. */ +#define CCL_INTMODE50_bm (1<<2) /* Interrupt Mode for LUT5 bit 0 mask. */ +#define CCL_INTMODE50_bp 2 /* Interrupt Mode for LUT5 bit 0 position. */ +#define CCL_INTMODE51_bm (1<<3) /* Interrupt Mode for LUT5 bit 1 mask. */ +#define CCL_INTMODE51_bp 3 /* Interrupt Mode for LUT5 bit 1 position. */ + +/* CCL.INTFLAGS bit masks and bit positions */ +#define CCL_INT_gm 0xFF /* Interrupt Flags group mask. */ +#define CCL_INT_gp 0 /* Interrupt Flags group position. */ +#define CCL_INT0_bm (1<<0) /* Interrupt Flags bit 0 mask. */ +#define CCL_INT0_bp 0 /* Interrupt Flags bit 0 position. */ +#define CCL_INT1_bm (1<<1) /* Interrupt Flags bit 1 mask. */ +#define CCL_INT1_bp 1 /* Interrupt Flags bit 1 position. */ +#define CCL_INT2_bm (1<<2) /* Interrupt Flags bit 2 mask. */ +#define CCL_INT2_bp 2 /* Interrupt Flags bit 2 position. */ +#define CCL_INT3_bm (1<<3) /* Interrupt Flags bit 3 mask. */ +#define CCL_INT3_bp 3 /* Interrupt Flags bit 3 position. */ +#define CCL_INT4_bm (1<<4) /* Interrupt Flags bit 4 mask. */ +#define CCL_INT4_bp 4 /* Interrupt Flags bit 4 position. */ +#define CCL_INT5_bm (1<<5) /* Interrupt Flags bit 5 mask. */ +#define CCL_INT5_bp 5 /* Interrupt Flags bit 5 position. */ +#define CCL_INT6_bm (1<<6) /* Interrupt Flags bit 6 mask. */ +#define CCL_INT6_bp 6 /* Interrupt Flags bit 6 position. */ +#define CCL_INT7_bm (1<<7) /* Interrupt Flags bit 7 mask. */ +#define CCL_INT7_bp 7 /* Interrupt Flags bit 7 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_CLKSRC_gm 0x0E /* Clock Source Selection group mask. */ +#define CCL_CLKSRC_gp 1 /* Clock Source Selection group position. */ +#define CCL_CLKSRC0_bm (1<<1) /* Clock Source Selection bit 0 mask. */ +#define CCL_CLKSRC0_bp 1 /* Clock Source Selection bit 0 position. */ +#define CCL_CLKSRC1_bm (1<<2) /* Clock Source Selection bit 1 mask. */ +#define CCL_CLKSRC1_bp 2 /* Clock Source Selection bit 1 position. */ +#define CCL_CLKSRC2_bm (1<<3) /* Clock Source Selection bit 2 mask. */ +#define CCL_CLKSRC2_bp 3 /* Clock Source Selection bit 2 position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_OUTEN_bm 0x40 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 6 /* Output Enable bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT2CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT2CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT2CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT3CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT3CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT3CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT4CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT4CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT4CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT5CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT5CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT5CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x07 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKSEL2_bm (1<<2) /* clock select bit 2 mask. */ +#define CLKCTRL_CLKSEL2_bp 2 /* clock select bit 2 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSCHFS_bm 0x02 /* High frequency oscillator status bit mask. */ +#define CLKCTRL_OSCHFS_bp 1 /* High frequency oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x04 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 2 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x08 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 3 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x10 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 4 /* External Clock status bit position. */ +#define CLKCTRL_PLLS_bm 0x20 /* PLL oscillator status bit mask. */ +#define CLKCTRL_PLLS_bp 5 /* PLL oscillator status bit position. */ + +/* CLKCTRL.OSCHFCTRLA bit masks and bit positions */ +#define CLKCTRL_AUTOTUNE_bm 0x01 /* Autotune bit mask. */ +#define CLKCTRL_AUTOTUNE_bp 0 /* Autotune bit position. */ +#define CLKCTRL_FREQSEL_gm 0x3C /* Frequency select group mask. */ +#define CLKCTRL_FREQSEL_gp 2 /* Frequency select group position. */ +#define CLKCTRL_FREQSEL0_bm (1<<2) /* Frequency select bit 0 mask. */ +#define CLKCTRL_FREQSEL0_bp 2 /* Frequency select bit 0 position. */ +#define CLKCTRL_FREQSEL1_bm (1<<3) /* Frequency select bit 1 mask. */ +#define CLKCTRL_FREQSEL1_bp 3 /* Frequency select bit 1 position. */ +#define CLKCTRL_FREQSEL2_bm (1<<4) /* Frequency select bit 2 mask. */ +#define CLKCTRL_FREQSEL2_bp 4 /* Frequency select bit 2 position. */ +#define CLKCTRL_FREQSEL3_bm (1<<5) /* Frequency select bit 3 mask. */ +#define CLKCTRL_FREQSEL3_bp 5 /* Frequency select bit 3 position. */ +#define CLKCTRL_RUNSTDBY_bm 0x80 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 7 /* Run standby bit position. */ + +/* CLKCTRL.OSCHFTUNE bit masks and bit positions */ +#define CLKCTRL_TUNE_gm 0xFF /* Tune group mask. */ +#define CLKCTRL_TUNE_gp 0 /* Tune group position. */ +#define CLKCTRL_TUNE0_bm (1<<0) /* Tune bit 0 mask. */ +#define CLKCTRL_TUNE0_bp 0 /* Tune bit 0 position. */ +#define CLKCTRL_TUNE1_bm (1<<1) /* Tune bit 1 mask. */ +#define CLKCTRL_TUNE1_bp 1 /* Tune bit 1 position. */ +#define CLKCTRL_TUNE2_bm (1<<2) /* Tune bit 2 mask. */ +#define CLKCTRL_TUNE2_bp 2 /* Tune bit 2 position. */ +#define CLKCTRL_TUNE3_bm (1<<3) /* Tune bit 3 mask. */ +#define CLKCTRL_TUNE3_bp 3 /* Tune bit 3 position. */ +#define CLKCTRL_TUNE4_bm (1<<4) /* Tune bit 4 mask. */ +#define CLKCTRL_TUNE4_bp 4 /* Tune bit 4 position. */ +#define CLKCTRL_TUNE5_bm (1<<5) /* Tune bit 5 mask. */ +#define CLKCTRL_TUNE5_bp 5 /* Tune bit 5 position. */ +#define CLKCTRL_TUNE6_bm (1<<6) /* Tune bit 6 mask. */ +#define CLKCTRL_TUNE6_bp 6 /* Tune bit 6 position. */ +#define CLKCTRL_TUNE7_bm (1<<7) /* Tune bit 7 mask. */ +#define CLKCTRL_TUNE7_bp 7 /* Tune bit 7 position. */ + +/* CLKCTRL.PLLCTRLA bit masks and bit positions */ +#define CLKCTRL_MULFAC_gm 0x03 /* Multiplication factor group mask. */ +#define CLKCTRL_MULFAC_gp 0 /* Multiplication factor group position. */ +#define CLKCTRL_MULFAC0_bm (1<<0) /* Multiplication factor bit 0 mask. */ +#define CLKCTRL_MULFAC0_bp 0 /* Multiplication factor bit 0 position. */ +#define CLKCTRL_MULFAC1_bm (1<<1) /* Multiplication factor bit 1 mask. */ +#define CLKCTRL_MULFAC1_bp 1 /* Multiplication factor bit 1 position. */ +#define CLKCTRL_SOURCE_bm 0x10 /* Source bit mask. */ +#define CLKCTRL_SOURCE_bp 4 /* Source bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +#define CLKCTRL_LPMODE_bm 0x02 /* Low power mode bit mask. */ +#define CLKCTRL_LPMODE_bp 1 /* Low power mode bit position. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* DAC.DATA bit masks and bit positions */ +#define DAC_DATA_gm 0xFFC0 /* Data group mask. */ +#define DAC_DATA_gp 6 /* Data group position. */ +#define DAC_DATA0_bm (1<<6) /* Data bit 0 mask. */ +#define DAC_DATA0_bp 6 /* Data bit 0 position. */ +#define DAC_DATA1_bm (1<<7) /* Data bit 1 mask. */ +#define DAC_DATA1_bp 7 /* Data bit 1 position. */ +#define DAC_DATA2_bm (1<<8) /* Data bit 2 mask. */ +#define DAC_DATA2_bp 8 /* Data bit 2 position. */ +#define DAC_DATA3_bm (1<<9) /* Data bit 3 mask. */ +#define DAC_DATA3_bp 9 /* Data bit 3 position. */ +#define DAC_DATA4_bm (1<<10) /* Data bit 4 mask. */ +#define DAC_DATA4_bp 10 /* Data bit 4 position. */ +#define DAC_DATA5_bm (1<<11) /* Data bit 5 mask. */ +#define DAC_DATA5_bp 11 /* Data bit 5 position. */ +#define DAC_DATA6_bm (1<<12) /* Data bit 6 mask. */ +#define DAC_DATA6_bp 12 /* Data bit 6 position. */ +#define DAC_DATA7_bm (1<<13) /* Data bit 7 mask. */ +#define DAC_DATA7_bp 13 /* Data bit 7 position. */ +#define DAC_DATA8_bm (1<<14) /* Data bit 8 mask. */ +#define DAC_DATA8_bp 14 /* Data bit 8 position. */ +#define DAC_DATA9_bm (1<<15) /* Data bit 9 mask. */ +#define DAC_DATA9_bp 15 /* Data bit 9 position. */ + +/* EVSYS - Event System */ +/* EVSYS.SWEVENTA bit masks and bit positions */ +#define EVSYS_SWEVENTA_gm 0xFF /* Software event on channel select group mask. */ +#define EVSYS_SWEVENTA_gp 0 /* Software event on channel select group position. */ +#define EVSYS_SWEVENTA0_bm (1<<0) /* Software event on channel select bit 0 mask. */ +#define EVSYS_SWEVENTA0_bp 0 /* Software event on channel select bit 0 position. */ +#define EVSYS_SWEVENTA1_bm (1<<1) /* Software event on channel select bit 1 mask. */ +#define EVSYS_SWEVENTA1_bp 1 /* Software event on channel select bit 1 position. */ +#define EVSYS_SWEVENTA2_bm (1<<2) /* Software event on channel select bit 2 mask. */ +#define EVSYS_SWEVENTA2_bp 2 /* Software event on channel select bit 2 position. */ +#define EVSYS_SWEVENTA3_bm (1<<3) /* Software event on channel select bit 3 mask. */ +#define EVSYS_SWEVENTA3_bp 3 /* Software event on channel select bit 3 position. */ +#define EVSYS_SWEVENTA4_bm (1<<4) /* Software event on channel select bit 4 mask. */ +#define EVSYS_SWEVENTA4_bp 4 /* Software event on channel select bit 4 position. */ +#define EVSYS_SWEVENTA5_bm (1<<5) /* Software event on channel select bit 5 mask. */ +#define EVSYS_SWEVENTA5_bp 5 /* Software event on channel select bit 5 position. */ +#define EVSYS_SWEVENTA6_bm (1<<6) /* Software event on channel select bit 6 mask. */ +#define EVSYS_SWEVENTA6_bp 6 /* Software event on channel select bit 6 position. */ +#define EVSYS_SWEVENTA7_bm (1<<7) /* Software event on channel select bit 7 mask. */ +#define EVSYS_SWEVENTA7_bp 7 /* Software event on channel select bit 7 position. */ + +/* EVSYS.SWEVENTB bit masks and bit positions */ +#define EVSYS_SWEVENTB_gm 0x03 /* Software event on channel select group mask. */ +#define EVSYS_SWEVENTB_gp 0 /* Software event on channel select group position. */ +#define EVSYS_SWEVENTB0_bm (1<<0) /* Software event on channel select bit 0 mask. */ +#define EVSYS_SWEVENTB0_bp 0 /* Software event on channel select bit 0 position. */ +#define EVSYS_SWEVENTB1_bm (1<<1) /* Software event on channel select bit 1 mask. */ +#define EVSYS_SWEVENTB1_bp 1 /* Software event on channel select bit 1 position. */ + +/* EVSYS.CHANNEL0 bit masks and bit positions */ +#define EVSYS_CHANNEL0_gm 0xFF /* Channel 0 generator select group mask. */ +#define EVSYS_CHANNEL0_gp 0 /* Channel 0 generator select group position. */ +#define EVSYS_CHANNEL00_bm (1<<0) /* Channel 0 generator select bit 0 mask. */ +#define EVSYS_CHANNEL00_bp 0 /* Channel 0 generator select bit 0 position. */ +#define EVSYS_CHANNEL01_bm (1<<1) /* Channel 0 generator select bit 1 mask. */ +#define EVSYS_CHANNEL01_bp 1 /* Channel 0 generator select bit 1 position. */ +#define EVSYS_CHANNEL02_bm (1<<2) /* Channel 0 generator select bit 2 mask. */ +#define EVSYS_CHANNEL02_bp 2 /* Channel 0 generator select bit 2 position. */ +#define EVSYS_CHANNEL03_bm (1<<3) /* Channel 0 generator select bit 3 mask. */ +#define EVSYS_CHANNEL03_bp 3 /* Channel 0 generator select bit 3 position. */ +#define EVSYS_CHANNEL04_bm (1<<4) /* Channel 0 generator select bit 4 mask. */ +#define EVSYS_CHANNEL04_bp 4 /* Channel 0 generator select bit 4 position. */ +#define EVSYS_CHANNEL05_bm (1<<5) /* Channel 0 generator select bit 5 mask. */ +#define EVSYS_CHANNEL05_bp 5 /* Channel 0 generator select bit 5 position. */ +#define EVSYS_CHANNEL06_bm (1<<6) /* Channel 0 generator select bit 6 mask. */ +#define EVSYS_CHANNEL06_bp 6 /* Channel 0 generator select bit 6 position. */ +#define EVSYS_CHANNEL07_bm (1<<7) /* Channel 0 generator select bit 7 mask. */ +#define EVSYS_CHANNEL07_bp 7 /* Channel 0 generator select bit 7 position. */ + +/* EVSYS.CHANNEL1 bit masks and bit positions */ +#define EVSYS_CHANNEL1_gm 0xFF /* Channel 1 generator select group mask. */ +#define EVSYS_CHANNEL1_gp 0 /* Channel 1 generator select group position. */ +#define EVSYS_CHANNEL10_bm (1<<0) /* Channel 1 generator select bit 0 mask. */ +#define EVSYS_CHANNEL10_bp 0 /* Channel 1 generator select bit 0 position. */ +#define EVSYS_CHANNEL11_bm (1<<1) /* Channel 1 generator select bit 1 mask. */ +#define EVSYS_CHANNEL11_bp 1 /* Channel 1 generator select bit 1 position. */ +#define EVSYS_CHANNEL12_bm (1<<2) /* Channel 1 generator select bit 2 mask. */ +#define EVSYS_CHANNEL12_bp 2 /* Channel 1 generator select bit 2 position. */ +#define EVSYS_CHANNEL13_bm (1<<3) /* Channel 1 generator select bit 3 mask. */ +#define EVSYS_CHANNEL13_bp 3 /* Channel 1 generator select bit 3 position. */ +#define EVSYS_CHANNEL14_bm (1<<4) /* Channel 1 generator select bit 4 mask. */ +#define EVSYS_CHANNEL14_bp 4 /* Channel 1 generator select bit 4 position. */ +#define EVSYS_CHANNEL15_bm (1<<5) /* Channel 1 generator select bit 5 mask. */ +#define EVSYS_CHANNEL15_bp 5 /* Channel 1 generator select bit 5 position. */ +#define EVSYS_CHANNEL16_bm (1<<6) /* Channel 1 generator select bit 6 mask. */ +#define EVSYS_CHANNEL16_bp 6 /* Channel 1 generator select bit 6 position. */ +#define EVSYS_CHANNEL17_bm (1<<7) /* Channel 1 generator select bit 7 mask. */ +#define EVSYS_CHANNEL17_bp 7 /* Channel 1 generator select bit 7 position. */ + +/* EVSYS.CHANNEL2 bit masks and bit positions */ +#define EVSYS_CHANNEL2_gm 0xFF /* Channel 2 generator select group mask. */ +#define EVSYS_CHANNEL2_gp 0 /* Channel 2 generator select group position. */ +#define EVSYS_CHANNEL20_bm (1<<0) /* Channel 2 generator select bit 0 mask. */ +#define EVSYS_CHANNEL20_bp 0 /* Channel 2 generator select bit 0 position. */ +#define EVSYS_CHANNEL21_bm (1<<1) /* Channel 2 generator select bit 1 mask. */ +#define EVSYS_CHANNEL21_bp 1 /* Channel 2 generator select bit 1 position. */ +#define EVSYS_CHANNEL22_bm (1<<2) /* Channel 2 generator select bit 2 mask. */ +#define EVSYS_CHANNEL22_bp 2 /* Channel 2 generator select bit 2 position. */ +#define EVSYS_CHANNEL23_bm (1<<3) /* Channel 2 generator select bit 3 mask. */ +#define EVSYS_CHANNEL23_bp 3 /* Channel 2 generator select bit 3 position. */ +#define EVSYS_CHANNEL24_bm (1<<4) /* Channel 2 generator select bit 4 mask. */ +#define EVSYS_CHANNEL24_bp 4 /* Channel 2 generator select bit 4 position. */ +#define EVSYS_CHANNEL25_bm (1<<5) /* Channel 2 generator select bit 5 mask. */ +#define EVSYS_CHANNEL25_bp 5 /* Channel 2 generator select bit 5 position. */ +#define EVSYS_CHANNEL26_bm (1<<6) /* Channel 2 generator select bit 6 mask. */ +#define EVSYS_CHANNEL26_bp 6 /* Channel 2 generator select bit 6 position. */ +#define EVSYS_CHANNEL27_bm (1<<7) /* Channel 2 generator select bit 7 mask. */ +#define EVSYS_CHANNEL27_bp 7 /* Channel 2 generator select bit 7 position. */ + +/* EVSYS.CHANNEL3 bit masks and bit positions */ +#define EVSYS_CHANNEL3_gm 0xFF /* Channel 3 generator select group mask. */ +#define EVSYS_CHANNEL3_gp 0 /* Channel 3 generator select group position. */ +#define EVSYS_CHANNEL30_bm (1<<0) /* Channel 3 generator select bit 0 mask. */ +#define EVSYS_CHANNEL30_bp 0 /* Channel 3 generator select bit 0 position. */ +#define EVSYS_CHANNEL31_bm (1<<1) /* Channel 3 generator select bit 1 mask. */ +#define EVSYS_CHANNEL31_bp 1 /* Channel 3 generator select bit 1 position. */ +#define EVSYS_CHANNEL32_bm (1<<2) /* Channel 3 generator select bit 2 mask. */ +#define EVSYS_CHANNEL32_bp 2 /* Channel 3 generator select bit 2 position. */ +#define EVSYS_CHANNEL33_bm (1<<3) /* Channel 3 generator select bit 3 mask. */ +#define EVSYS_CHANNEL33_bp 3 /* Channel 3 generator select bit 3 position. */ +#define EVSYS_CHANNEL34_bm (1<<4) /* Channel 3 generator select bit 4 mask. */ +#define EVSYS_CHANNEL34_bp 4 /* Channel 3 generator select bit 4 position. */ +#define EVSYS_CHANNEL35_bm (1<<5) /* Channel 3 generator select bit 5 mask. */ +#define EVSYS_CHANNEL35_bp 5 /* Channel 3 generator select bit 5 position. */ +#define EVSYS_CHANNEL36_bm (1<<6) /* Channel 3 generator select bit 6 mask. */ +#define EVSYS_CHANNEL36_bp 6 /* Channel 3 generator select bit 6 position. */ +#define EVSYS_CHANNEL37_bm (1<<7) /* Channel 3 generator select bit 7 mask. */ +#define EVSYS_CHANNEL37_bp 7 /* Channel 3 generator select bit 7 position. */ + +/* EVSYS.CHANNEL4 bit masks and bit positions */ +#define EVSYS_CHANNEL4_gm 0xFF /* Channel 4 generator select group mask. */ +#define EVSYS_CHANNEL4_gp 0 /* Channel 4 generator select group position. */ +#define EVSYS_CHANNEL40_bm (1<<0) /* Channel 4 generator select bit 0 mask. */ +#define EVSYS_CHANNEL40_bp 0 /* Channel 4 generator select bit 0 position. */ +#define EVSYS_CHANNEL41_bm (1<<1) /* Channel 4 generator select bit 1 mask. */ +#define EVSYS_CHANNEL41_bp 1 /* Channel 4 generator select bit 1 position. */ +#define EVSYS_CHANNEL42_bm (1<<2) /* Channel 4 generator select bit 2 mask. */ +#define EVSYS_CHANNEL42_bp 2 /* Channel 4 generator select bit 2 position. */ +#define EVSYS_CHANNEL43_bm (1<<3) /* Channel 4 generator select bit 3 mask. */ +#define EVSYS_CHANNEL43_bp 3 /* Channel 4 generator select bit 3 position. */ +#define EVSYS_CHANNEL44_bm (1<<4) /* Channel 4 generator select bit 4 mask. */ +#define EVSYS_CHANNEL44_bp 4 /* Channel 4 generator select bit 4 position. */ +#define EVSYS_CHANNEL45_bm (1<<5) /* Channel 4 generator select bit 5 mask. */ +#define EVSYS_CHANNEL45_bp 5 /* Channel 4 generator select bit 5 position. */ +#define EVSYS_CHANNEL46_bm (1<<6) /* Channel 4 generator select bit 6 mask. */ +#define EVSYS_CHANNEL46_bp 6 /* Channel 4 generator select bit 6 position. */ +#define EVSYS_CHANNEL47_bm (1<<7) /* Channel 4 generator select bit 7 mask. */ +#define EVSYS_CHANNEL47_bp 7 /* Channel 4 generator select bit 7 position. */ + +/* EVSYS.CHANNEL5 bit masks and bit positions */ +#define EVSYS_CHANNEL5_gm 0xFF /* Channel 5 generator select group mask. */ +#define EVSYS_CHANNEL5_gp 0 /* Channel 5 generator select group position. */ +#define EVSYS_CHANNEL50_bm (1<<0) /* Channel 5 generator select bit 0 mask. */ +#define EVSYS_CHANNEL50_bp 0 /* Channel 5 generator select bit 0 position. */ +#define EVSYS_CHANNEL51_bm (1<<1) /* Channel 5 generator select bit 1 mask. */ +#define EVSYS_CHANNEL51_bp 1 /* Channel 5 generator select bit 1 position. */ +#define EVSYS_CHANNEL52_bm (1<<2) /* Channel 5 generator select bit 2 mask. */ +#define EVSYS_CHANNEL52_bp 2 /* Channel 5 generator select bit 2 position. */ +#define EVSYS_CHANNEL53_bm (1<<3) /* Channel 5 generator select bit 3 mask. */ +#define EVSYS_CHANNEL53_bp 3 /* Channel 5 generator select bit 3 position. */ +#define EVSYS_CHANNEL54_bm (1<<4) /* Channel 5 generator select bit 4 mask. */ +#define EVSYS_CHANNEL54_bp 4 /* Channel 5 generator select bit 4 position. */ +#define EVSYS_CHANNEL55_bm (1<<5) /* Channel 5 generator select bit 5 mask. */ +#define EVSYS_CHANNEL55_bp 5 /* Channel 5 generator select bit 5 position. */ +#define EVSYS_CHANNEL56_bm (1<<6) /* Channel 5 generator select bit 6 mask. */ +#define EVSYS_CHANNEL56_bp 6 /* Channel 5 generator select bit 6 position. */ +#define EVSYS_CHANNEL57_bm (1<<7) /* Channel 5 generator select bit 7 mask. */ +#define EVSYS_CHANNEL57_bp 7 /* Channel 5 generator select bit 7 position. */ + +/* EVSYS.CHANNEL6 bit masks and bit positions */ +#define EVSYS_CHANNEL6_gm 0xFF /* Channel 6 generator select group mask. */ +#define EVSYS_CHANNEL6_gp 0 /* Channel 6 generator select group position. */ +#define EVSYS_CHANNEL60_bm (1<<0) /* Channel 6 generator select bit 0 mask. */ +#define EVSYS_CHANNEL60_bp 0 /* Channel 6 generator select bit 0 position. */ +#define EVSYS_CHANNEL61_bm (1<<1) /* Channel 6 generator select bit 1 mask. */ +#define EVSYS_CHANNEL61_bp 1 /* Channel 6 generator select bit 1 position. */ +#define EVSYS_CHANNEL62_bm (1<<2) /* Channel 6 generator select bit 2 mask. */ +#define EVSYS_CHANNEL62_bp 2 /* Channel 6 generator select bit 2 position. */ +#define EVSYS_CHANNEL63_bm (1<<3) /* Channel 6 generator select bit 3 mask. */ +#define EVSYS_CHANNEL63_bp 3 /* Channel 6 generator select bit 3 position. */ +#define EVSYS_CHANNEL64_bm (1<<4) /* Channel 6 generator select bit 4 mask. */ +#define EVSYS_CHANNEL64_bp 4 /* Channel 6 generator select bit 4 position. */ +#define EVSYS_CHANNEL65_bm (1<<5) /* Channel 6 generator select bit 5 mask. */ +#define EVSYS_CHANNEL65_bp 5 /* Channel 6 generator select bit 5 position. */ +#define EVSYS_CHANNEL66_bm (1<<6) /* Channel 6 generator select bit 6 mask. */ +#define EVSYS_CHANNEL66_bp 6 /* Channel 6 generator select bit 6 position. */ +#define EVSYS_CHANNEL67_bm (1<<7) /* Channel 6 generator select bit 7 mask. */ +#define EVSYS_CHANNEL67_bp 7 /* Channel 6 generator select bit 7 position. */ + +/* EVSYS.CHANNEL7 bit masks and bit positions */ +#define EVSYS_CHANNEL7_gm 0xFF /* Channel 7 generator select group mask. */ +#define EVSYS_CHANNEL7_gp 0 /* Channel 7 generator select group position. */ +#define EVSYS_CHANNEL70_bm (1<<0) /* Channel 7 generator select bit 0 mask. */ +#define EVSYS_CHANNEL70_bp 0 /* Channel 7 generator select bit 0 position. */ +#define EVSYS_CHANNEL71_bm (1<<1) /* Channel 7 generator select bit 1 mask. */ +#define EVSYS_CHANNEL71_bp 1 /* Channel 7 generator select bit 1 position. */ +#define EVSYS_CHANNEL72_bm (1<<2) /* Channel 7 generator select bit 2 mask. */ +#define EVSYS_CHANNEL72_bp 2 /* Channel 7 generator select bit 2 position. */ +#define EVSYS_CHANNEL73_bm (1<<3) /* Channel 7 generator select bit 3 mask. */ +#define EVSYS_CHANNEL73_bp 3 /* Channel 7 generator select bit 3 position. */ +#define EVSYS_CHANNEL74_bm (1<<4) /* Channel 7 generator select bit 4 mask. */ +#define EVSYS_CHANNEL74_bp 4 /* Channel 7 generator select bit 4 position. */ +#define EVSYS_CHANNEL75_bm (1<<5) /* Channel 7 generator select bit 5 mask. */ +#define EVSYS_CHANNEL75_bp 5 /* Channel 7 generator select bit 5 position. */ +#define EVSYS_CHANNEL76_bm (1<<6) /* Channel 7 generator select bit 6 mask. */ +#define EVSYS_CHANNEL76_bp 6 /* Channel 7 generator select bit 6 position. */ +#define EVSYS_CHANNEL77_bm (1<<7) /* Channel 7 generator select bit 7 mask. */ +#define EVSYS_CHANNEL77_bp 7 /* Channel 7 generator select bit 7 position. */ + +/* EVSYS.CHANNEL8 bit masks and bit positions */ +#define EVSYS_CHANNEL8_gm 0xFF /* Channel 8 generator select group mask. */ +#define EVSYS_CHANNEL8_gp 0 /* Channel 8 generator select group position. */ +#define EVSYS_CHANNEL80_bm (1<<0) /* Channel 8 generator select bit 0 mask. */ +#define EVSYS_CHANNEL80_bp 0 /* Channel 8 generator select bit 0 position. */ +#define EVSYS_CHANNEL81_bm (1<<1) /* Channel 8 generator select bit 1 mask. */ +#define EVSYS_CHANNEL81_bp 1 /* Channel 8 generator select bit 1 position. */ +#define EVSYS_CHANNEL82_bm (1<<2) /* Channel 8 generator select bit 2 mask. */ +#define EVSYS_CHANNEL82_bp 2 /* Channel 8 generator select bit 2 position. */ +#define EVSYS_CHANNEL83_bm (1<<3) /* Channel 8 generator select bit 3 mask. */ +#define EVSYS_CHANNEL83_bp 3 /* Channel 8 generator select bit 3 position. */ +#define EVSYS_CHANNEL84_bm (1<<4) /* Channel 8 generator select bit 4 mask. */ +#define EVSYS_CHANNEL84_bp 4 /* Channel 8 generator select bit 4 position. */ +#define EVSYS_CHANNEL85_bm (1<<5) /* Channel 8 generator select bit 5 mask. */ +#define EVSYS_CHANNEL85_bp 5 /* Channel 8 generator select bit 5 position. */ +#define EVSYS_CHANNEL86_bm (1<<6) /* Channel 8 generator select bit 6 mask. */ +#define EVSYS_CHANNEL86_bp 6 /* Channel 8 generator select bit 6 position. */ +#define EVSYS_CHANNEL87_bm (1<<7) /* Channel 8 generator select bit 7 mask. */ +#define EVSYS_CHANNEL87_bp 7 /* Channel 8 generator select bit 7 position. */ + +/* EVSYS.CHANNEL9 bit masks and bit positions */ +#define EVSYS_CHANNEL9_gm 0xFF /* Channel 9 generator select group mask. */ +#define EVSYS_CHANNEL9_gp 0 /* Channel 9 generator select group position. */ +#define EVSYS_CHANNEL90_bm (1<<0) /* Channel 9 generator select bit 0 mask. */ +#define EVSYS_CHANNEL90_bp 0 /* Channel 9 generator select bit 0 position. */ +#define EVSYS_CHANNEL91_bm (1<<1) /* Channel 9 generator select bit 1 mask. */ +#define EVSYS_CHANNEL91_bp 1 /* Channel 9 generator select bit 1 position. */ +#define EVSYS_CHANNEL92_bm (1<<2) /* Channel 9 generator select bit 2 mask. */ +#define EVSYS_CHANNEL92_bp 2 /* Channel 9 generator select bit 2 position. */ +#define EVSYS_CHANNEL93_bm (1<<3) /* Channel 9 generator select bit 3 mask. */ +#define EVSYS_CHANNEL93_bp 3 /* Channel 9 generator select bit 3 position. */ +#define EVSYS_CHANNEL94_bm (1<<4) /* Channel 9 generator select bit 4 mask. */ +#define EVSYS_CHANNEL94_bp 4 /* Channel 9 generator select bit 4 position. */ +#define EVSYS_CHANNEL95_bm (1<<5) /* Channel 9 generator select bit 5 mask. */ +#define EVSYS_CHANNEL95_bp 5 /* Channel 9 generator select bit 5 position. */ +#define EVSYS_CHANNEL96_bm (1<<6) /* Channel 9 generator select bit 6 mask. */ +#define EVSYS_CHANNEL96_bp 6 /* Channel 9 generator select bit 6 position. */ +#define EVSYS_CHANNEL97_bm (1<<7) /* Channel 9 generator select bit 7 mask. */ +#define EVSYS_CHANNEL97_bp 7 /* Channel 9 generator select bit 7 position. */ + +/* EVSYS.USERCCLLUT0A bit masks and bit positions */ +#define EVSYS_USER_gm 0xFF /* User channel select group mask. */ +#define EVSYS_USER_gp 0 /* User channel select group position. */ +#define EVSYS_USER0_bm (1<<0) /* User channel select bit 0 mask. */ +#define EVSYS_USER0_bp 0 /* User channel select bit 0 position. */ +#define EVSYS_USER1_bm (1<<1) /* User channel select bit 1 mask. */ +#define EVSYS_USER1_bp 1 /* User channel select bit 1 position. */ +#define EVSYS_USER2_bm (1<<2) /* User channel select bit 2 mask. */ +#define EVSYS_USER2_bp 2 /* User channel select bit 2 position. */ +#define EVSYS_USER3_bm (1<<3) /* User channel select bit 3 mask. */ +#define EVSYS_USER3_bp 3 /* User channel select bit 3 position. */ +#define EVSYS_USER4_bm (1<<4) /* User channel select bit 4 mask. */ +#define EVSYS_USER4_bp 4 /* User channel select bit 4 position. */ +#define EVSYS_USER5_bm (1<<5) /* User channel select bit 5 mask. */ +#define EVSYS_USER5_bp 5 /* User channel select bit 5 position. */ +#define EVSYS_USER6_bm (1<<6) /* User channel select bit 6 mask. */ +#define EVSYS_USER6_bp 6 /* User channel select bit 6 position. */ +#define EVSYS_USER7_bm (1<<7) /* User channel select bit 7 mask. */ +#define EVSYS_USER7_bp 7 /* User channel select bit 7 position. */ + +/* EVSYS.USERCCLLUT0B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT1A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT1B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT2A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT2B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT3A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT3B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT4A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT4B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT5A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT5B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERADC0START bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERPTCSTART bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTC bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTD bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTE bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTF bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTG bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART0IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART1IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART2IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART3IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART4IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART5IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA0CNTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA0CNTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA1CNTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA1CNTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB0CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB0COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB1CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB1COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB2CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB2COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB3CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB3COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB4CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB4COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCD0INPUTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCD0INPUTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEROSCTEST bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_CLKSEL_gm 0x07 /* Frequency Select group mask. */ +#define FUSE_CLKSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_CLKSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_CLKSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_CLKSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_CLKSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_CLKSEL2_bm (1<<2) /* Frequency Select bit 2 mask. */ +#define FUSE_CLKSEL2_bp 2 /* Frequency Select bit 2 position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSEL_bm 0x20 /* CRC Select bit mask. */ +#define FUSE_CRCSEL_bp 5 /* CRC Select bit position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCK - Lockbits */ +/* LOCK.KEY bit masks and bit positions */ +#define LOCK_KEY_gm 0xFFFFFFFF /* Lock Key group mask. */ +#define LOCK_KEY_gp 0 /* Lock Key group position. */ +#define LOCK_KEY0_bm (1<<0) /* Lock Key bit 0 mask. */ +#define LOCK_KEY0_bp 0 /* Lock Key bit 0 position. */ +#define LOCK_KEY1_bm (1<<1) /* Lock Key bit 1 mask. */ +#define LOCK_KEY1_bp 1 /* Lock Key bit 1 position. */ +#define LOCK_KEY2_bm (1<<2) /* Lock Key bit 2 mask. */ +#define LOCK_KEY2_bp 2 /* Lock Key bit 2 position. */ +#define LOCK_KEY3_bm (1<<3) /* Lock Key bit 3 mask. */ +#define LOCK_KEY3_bp 3 /* Lock Key bit 3 position. */ +#define LOCK_KEY4_bm (1<<4) /* Lock Key bit 4 mask. */ +#define LOCK_KEY4_bp 4 /* Lock Key bit 4 position. */ +#define LOCK_KEY5_bm (1<<5) /* Lock Key bit 5 mask. */ +#define LOCK_KEY5_bp 5 /* Lock Key bit 5 position. */ +#define LOCK_KEY6_bm (1<<6) /* Lock Key bit 6 mask. */ +#define LOCK_KEY6_bp 6 /* Lock Key bit 6 position. */ +#define LOCK_KEY7_bm (1<<7) /* Lock Key bit 7 mask. */ +#define LOCK_KEY7_bp 7 /* Lock Key bit 7 position. */ +#define LOCK_KEY8_bm (1<<8) /* Lock Key bit 8 mask. */ +#define LOCK_KEY8_bp 8 /* Lock Key bit 8 position. */ +#define LOCK_KEY9_bm (1<<9) /* Lock Key bit 9 mask. */ +#define LOCK_KEY9_bp 9 /* Lock Key bit 9 position. */ +#define LOCK_KEY10_bm (1<<10) /* Lock Key bit 10 mask. */ +#define LOCK_KEY10_bp 10 /* Lock Key bit 10 position. */ +#define LOCK_KEY11_bm (1<<11) /* Lock Key bit 11 mask. */ +#define LOCK_KEY11_bp 11 /* Lock Key bit 11 position. */ +#define LOCK_KEY12_bm (1<<12) /* Lock Key bit 12 mask. */ +#define LOCK_KEY12_bp 12 /* Lock Key bit 12 position. */ +#define LOCK_KEY13_bm (1<<13) /* Lock Key bit 13 mask. */ +#define LOCK_KEY13_bp 13 /* Lock Key bit 13 position. */ +#define LOCK_KEY14_bm (1<<14) /* Lock Key bit 14 mask. */ +#define LOCK_KEY14_bp 14 /* Lock Key bit 14 position. */ +#define LOCK_KEY15_bm (1<<15) /* Lock Key bit 15 mask. */ +#define LOCK_KEY15_bp 15 /* Lock Key bit 15 position. */ +#define LOCK_KEY16_bm (1<<16) /* Lock Key bit 16 mask. */ +#define LOCK_KEY16_bp 16 /* Lock Key bit 16 position. */ +#define LOCK_KEY17_bm (1<<17) /* Lock Key bit 17 mask. */ +#define LOCK_KEY17_bp 17 /* Lock Key bit 17 position. */ +#define LOCK_KEY18_bm (1<<18) /* Lock Key bit 18 mask. */ +#define LOCK_KEY18_bp 18 /* Lock Key bit 18 position. */ +#define LOCK_KEY19_bm (1<<19) /* Lock Key bit 19 mask. */ +#define LOCK_KEY19_bp 19 /* Lock Key bit 19 position. */ +#define LOCK_KEY20_bm (1<<20) /* Lock Key bit 20 mask. */ +#define LOCK_KEY20_bp 20 /* Lock Key bit 20 position. */ +#define LOCK_KEY21_bm (1<<21) /* Lock Key bit 21 mask. */ +#define LOCK_KEY21_bp 21 /* Lock Key bit 21 position. */ +#define LOCK_KEY22_bm (1<<22) /* Lock Key bit 22 mask. */ +#define LOCK_KEY22_bp 22 /* Lock Key bit 22 position. */ +#define LOCK_KEY23_bm (1<<23) /* Lock Key bit 23 mask. */ +#define LOCK_KEY23_bp 23 /* Lock Key bit 23 position. */ +#define LOCK_KEY24_bm (1<<24) /* Lock Key bit 24 mask. */ +#define LOCK_KEY24_bp 24 /* Lock Key bit 24 position. */ +#define LOCK_KEY25_bm (1<<25) /* Lock Key bit 25 mask. */ +#define LOCK_KEY25_bp 25 /* Lock Key bit 25 position. */ +#define LOCK_KEY26_bm (1<<26) /* Lock Key bit 26 mask. */ +#define LOCK_KEY26_bp 26 /* Lock Key bit 26 position. */ +#define LOCK_KEY27_bm (1<<27) /* Lock Key bit 27 mask. */ +#define LOCK_KEY27_bp 27 /* Lock Key bit 27 position. */ +#define LOCK_KEY28_bm (1<<28) /* Lock Key bit 28 mask. */ +#define LOCK_KEY28_bp 28 /* Lock Key bit 28 position. */ +#define LOCK_KEY29_bm (1<<29) /* Lock Key bit 29 mask. */ +#define LOCK_KEY29_bp 29 /* Lock Key bit 29 position. */ +#define LOCK_KEY30_bm (1<<30) /* Lock Key bit 30 mask. */ +#define LOCK_KEY30_bp 30 /* Lock Key bit 30 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x7F /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ +#define NVMCTRL_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVMCTRL_CMD3_bp 3 /* Command bit 3 position. */ +#define NVMCTRL_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVMCTRL_CMD4_bp 4 /* Command bit 4 position. */ +#define NVMCTRL_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVMCTRL_CMD5_bp 5 /* Command bit 5 position. */ +#define NVMCTRL_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVMCTRL_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APPCODEWP_bm 0x01 /* Application Code Write Protect bit mask. */ +#define NVMCTRL_APPCODEWP_bp 0 /* Application Code Write Protect bit position. */ +#define NVMCTRL_BOOTRP_bm 0x02 /* Boot Read Protect bit mask. */ +#define NVMCTRL_BOOTRP_bp 1 /* Boot Read Protect bit position. */ +#define NVMCTRL_APPDATAWP_bm 0x04 /* Application Data Write Protect bit mask. */ +#define NVMCTRL_APPDATAWP_bp 2 /* Application Data Write Protect bit position. */ +#define NVMCTRL_FLMAP_gm 0x30 /* Flash Mapping in Data space group mask. */ +#define NVMCTRL_FLMAP_gp 4 /* Flash Mapping in Data space group position. */ +#define NVMCTRL_FLMAP0_bm (1<<4) /* Flash Mapping in Data space bit 0 mask. */ +#define NVMCTRL_FLMAP0_bp 4 /* Flash Mapping in Data space bit 0 position. */ +#define NVMCTRL_FLMAP1_bm (1<<5) /* Flash Mapping in Data space bit 1 mask. */ +#define NVMCTRL_FLMAP1_bp 5 /* Flash Mapping in Data space bit 1 position. */ +#define NVMCTRL_FLMAPLOCK_bm 0x80 /* Flash Mapping Lock bit mask. */ +#define NVMCTRL_FLMAPLOCK_bp 7 /* Flash Mapping Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_ERROR_gm 0x70 /* Write error group mask. */ +#define NVMCTRL_ERROR_gp 4 /* Write error group position. */ +#define NVMCTRL_ERROR0_bm (1<<4) /* Write error bit 0 mask. */ +#define NVMCTRL_ERROR0_bp 4 /* Write error bit 0 position. */ +#define NVMCTRL_ERROR1_bm (1<<5) /* Write error bit 1 mask. */ +#define NVMCTRL_ERROR1_bp 5 /* Write error bit 1 position. */ +#define NVMCTRL_ERROR2_bm (1<<6) /* Write error bit 2 mask. */ +#define NVMCTRL_ERROR2_bp 6 /* Write error bit 2 position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PORTCTRL bit masks and bit positions */ +#define PORT_SRL_bm 0x01 /* Slew Rate Limit Enable bit mask. */ +#define PORT_SRL_bp 0 /* Slew Rate Limit Enable bit position. */ + +/* PORT.PINCONFIG bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PINCTRLUPD bit masks and bit positions */ +#define PORT_PINCTRLUPD_gm 0xFF /* Pin control update mask group mask. */ +#define PORT_PINCTRLUPD_gp 0 /* Pin control update mask group position. */ +#define PORT_PINCTRLUPD0_bm (1<<0) /* Pin control update mask bit 0 mask. */ +#define PORT_PINCTRLUPD0_bp 0 /* Pin control update mask bit 0 position. */ +#define PORT_PINCTRLUPD1_bm (1<<1) /* Pin control update mask bit 1 mask. */ +#define PORT_PINCTRLUPD1_bp 1 /* Pin control update mask bit 1 position. */ +#define PORT_PINCTRLUPD2_bm (1<<2) /* Pin control update mask bit 2 mask. */ +#define PORT_PINCTRLUPD2_bp 2 /* Pin control update mask bit 2 position. */ +#define PORT_PINCTRLUPD3_bm (1<<3) /* Pin control update mask bit 3 mask. */ +#define PORT_PINCTRLUPD3_bp 3 /* Pin control update mask bit 3 position. */ +#define PORT_PINCTRLUPD4_bm (1<<4) /* Pin control update mask bit 4 mask. */ +#define PORT_PINCTRLUPD4_bp 4 /* Pin control update mask bit 4 position. */ +#define PORT_PINCTRLUPD5_bm (1<<5) /* Pin control update mask bit 5 mask. */ +#define PORT_PINCTRLUPD5_bp 5 /* Pin control update mask bit 5 position. */ +#define PORT_PINCTRLUPD6_bm (1<<6) /* Pin control update mask bit 6 mask. */ +#define PORT_PINCTRLUPD6_bp 6 /* Pin control update mask bit 6 position. */ +#define PORT_PINCTRLUPD7_bm (1<<7) /* Pin control update mask bit 7 mask. */ +#define PORT_PINCTRLUPD7_bp 7 /* Pin control update mask bit 7 position. */ + +/* PORT.PINCTRLSET bit masks and bit positions */ +#define PORT_PINCTRLSET_gm 0xFF /* Pin control set mask group mask. */ +#define PORT_PINCTRLSET_gp 0 /* Pin control set mask group position. */ +#define PORT_PINCTRLSET0_bm (1<<0) /* Pin control set mask bit 0 mask. */ +#define PORT_PINCTRLSET0_bp 0 /* Pin control set mask bit 0 position. */ +#define PORT_PINCTRLSET1_bm (1<<1) /* Pin control set mask bit 1 mask. */ +#define PORT_PINCTRLSET1_bp 1 /* Pin control set mask bit 1 position. */ +#define PORT_PINCTRLSET2_bm (1<<2) /* Pin control set mask bit 2 mask. */ +#define PORT_PINCTRLSET2_bp 2 /* Pin control set mask bit 2 position. */ +#define PORT_PINCTRLSET3_bm (1<<3) /* Pin control set mask bit 3 mask. */ +#define PORT_PINCTRLSET3_bp 3 /* Pin control set mask bit 3 position. */ +#define PORT_PINCTRLSET4_bm (1<<4) /* Pin control set mask bit 4 mask. */ +#define PORT_PINCTRLSET4_bp 4 /* Pin control set mask bit 4 position. */ +#define PORT_PINCTRLSET5_bm (1<<5) /* Pin control set mask bit 5 mask. */ +#define PORT_PINCTRLSET5_bp 5 /* Pin control set mask bit 5 position. */ +#define PORT_PINCTRLSET6_bm (1<<6) /* Pin control set mask bit 6 mask. */ +#define PORT_PINCTRLSET6_bp 6 /* Pin control set mask bit 6 position. */ +#define PORT_PINCTRLSET7_bm (1<<7) /* Pin control set mask bit 7 mask. */ +#define PORT_PINCTRLSET7_bp 7 /* Pin control set mask bit 7 position. */ + +/* PORT.PINCTRLCLR bit masks and bit positions */ +#define PORT_PINCTRLCLR_gm 0xFF /* Pin control clear mask group mask. */ +#define PORT_PINCTRLCLR_gp 0 /* Pin control clear mask group position. */ +#define PORT_PINCTRLCLR0_bm (1<<0) /* Pin control clear mask bit 0 mask. */ +#define PORT_PINCTRLCLR0_bp 0 /* Pin control clear mask bit 0 position. */ +#define PORT_PINCTRLCLR1_bm (1<<1) /* Pin control clear mask bit 1 mask. */ +#define PORT_PINCTRLCLR1_bp 1 /* Pin control clear mask bit 1 position. */ +#define PORT_PINCTRLCLR2_bm (1<<2) /* Pin control clear mask bit 2 mask. */ +#define PORT_PINCTRLCLR2_bp 2 /* Pin control clear mask bit 2 position. */ +#define PORT_PINCTRLCLR3_bm (1<<3) /* Pin control clear mask bit 3 mask. */ +#define PORT_PINCTRLCLR3_bp 3 /* Pin control clear mask bit 3 position. */ +#define PORT_PINCTRLCLR4_bm (1<<4) /* Pin control clear mask bit 4 mask. */ +#define PORT_PINCTRLCLR4_bp 4 /* Pin control clear mask bit 4 position. */ +#define PORT_PINCTRLCLR5_bm (1<<5) /* Pin control clear mask bit 5 mask. */ +#define PORT_PINCTRLCLR5_bp 5 /* Pin control clear mask bit 5 position. */ +#define PORT_PINCTRLCLR6_bm (1<<6) /* Pin control clear mask bit 6 mask. */ +#define PORT_PINCTRLCLR6_bp 6 /* Pin control clear mask bit 6 position. */ +#define PORT_PINCTRLCLR7_bm (1<<7) /* Pin control clear mask bit 7 mask. */ +#define PORT_PINCTRLCLR7_bp 7 /* Pin control clear mask bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.EVSYSROUTEA bit masks and bit positions */ +#define PORTMUX_EVOUTA_bm 0x01 /* Event Output A bit mask. */ +#define PORTMUX_EVOUTA_bp 0 /* Event Output A bit position. */ +#define PORTMUX_EVOUTB_bm 0x02 /* Event Output B bit mask. */ +#define PORTMUX_EVOUTB_bp 1 /* Event Output B bit position. */ +#define PORTMUX_EVOUTC_bm 0x04 /* Event Output C bit mask. */ +#define PORTMUX_EVOUTC_bp 2 /* Event Output C bit position. */ +#define PORTMUX_EVOUTD_bm 0x08 /* Event Output D bit mask. */ +#define PORTMUX_EVOUTD_bp 3 /* Event Output D bit position. */ +#define PORTMUX_EVOUTE_bm 0x10 /* Event Output E bit mask. */ +#define PORTMUX_EVOUTE_bp 4 /* Event Output E bit position. */ +#define PORTMUX_EVOUTF_bm 0x20 /* Event Output F bit mask. */ +#define PORTMUX_EVOUTF_bp 5 /* Event Output F bit position. */ +#define PORTMUX_EVOUTG_bm 0x40 /* Event Output G bit mask. */ +#define PORTMUX_EVOUTG_bp 6 /* Event Output G bit position. */ + +/* PORTMUX.CCLROUTEA bit masks and bit positions */ +#define PORTMUX_LUT0_bm 0x01 /* CCL Look-Up Table 0 Signals bit mask. */ +#define PORTMUX_LUT0_bp 0 /* CCL Look-Up Table 0 Signals bit position. */ +#define PORTMUX_LUT1_bm 0x02 /* CCL Look-Up Table 1 Signals bit mask. */ +#define PORTMUX_LUT1_bp 1 /* CCL Look-Up Table 1 Signals bit position. */ +#define PORTMUX_LUT2_bm 0x04 /* CCL Look-Up Table 2 Signals bit mask. */ +#define PORTMUX_LUT2_bp 2 /* CCL Look-Up Table 2 Signals bit position. */ +#define PORTMUX_LUT3_bm 0x08 /* CCL Look-Up Table 3 Signals bit mask. */ +#define PORTMUX_LUT3_bp 3 /* CCL Look-Up Table 3 Signals bit position. */ +#define PORTMUX_LUT4_bm 0x10 /* CCL Look-Up Table 4 Signals bit mask. */ +#define PORTMUX_LUT4_bp 4 /* CCL Look-Up Table 4 Signals bit position. */ +#define PORTMUX_LUT5_bm 0x20 /* CCL Look-Up Table 5 Signals bit mask. */ +#define PORTMUX_LUT5_bp 5 /* CCL Look-Up Table 5 Signals bit position. */ + +/* PORTMUX.USARTROUTEA bit masks and bit positions */ +#define PORTMUX_USART0_gm 0x03 /* USART0 Signals group mask. */ +#define PORTMUX_USART0_gp 0 /* USART0 Signals group position. */ +#define PORTMUX_USART00_bm (1<<0) /* USART0 Signals bit 0 mask. */ +#define PORTMUX_USART00_bp 0 /* USART0 Signals bit 0 position. */ +#define PORTMUX_USART01_bm (1<<1) /* USART0 Signals bit 1 mask. */ +#define PORTMUX_USART01_bp 1 /* USART0 Signals bit 1 position. */ +#define PORTMUX_USART1_gm 0x0C /* USART1 Signals group mask. */ +#define PORTMUX_USART1_gp 2 /* USART1 Signals group position. */ +#define PORTMUX_USART10_bm (1<<2) /* USART1 Signals bit 0 mask. */ +#define PORTMUX_USART10_bp 2 /* USART1 Signals bit 0 position. */ +#define PORTMUX_USART11_bm (1<<3) /* USART1 Signals bit 1 mask. */ +#define PORTMUX_USART11_bp 3 /* USART1 Signals bit 1 position. */ +#define PORTMUX_USART2_gm 0x30 /* USART2 Signals group mask. */ +#define PORTMUX_USART2_gp 4 /* USART2 Signals group position. */ +#define PORTMUX_USART20_bm (1<<4) /* USART2 Signals bit 0 mask. */ +#define PORTMUX_USART20_bp 4 /* USART2 Signals bit 0 position. */ +#define PORTMUX_USART21_bm (1<<5) /* USART2 Signals bit 1 mask. */ +#define PORTMUX_USART21_bp 5 /* USART2 Signals bit 1 position. */ +#define PORTMUX_USART3_gm 0xC0 /* USART3 Signals group mask. */ +#define PORTMUX_USART3_gp 6 /* USART3 Signals group position. */ +#define PORTMUX_USART30_bm (1<<6) /* USART3 Signals bit 0 mask. */ +#define PORTMUX_USART30_bp 6 /* USART3 Signals bit 0 position. */ +#define PORTMUX_USART31_bm (1<<7) /* USART3 Signals bit 1 mask. */ +#define PORTMUX_USART31_bp 7 /* USART3 Signals bit 1 position. */ + +/* PORTMUX.USARTROUTEB bit masks and bit positions */ +#define PORTMUX_USART4_gm 0x03 /* USART4 Signals group mask. */ +#define PORTMUX_USART4_gp 0 /* USART4 Signals group position. */ +#define PORTMUX_USART40_bm (1<<0) /* USART4 Signals bit 0 mask. */ +#define PORTMUX_USART40_bp 0 /* USART4 Signals bit 0 position. */ +#define PORTMUX_USART41_bm (1<<1) /* USART4 Signals bit 1 mask. */ +#define PORTMUX_USART41_bp 1 /* USART4 Signals bit 1 position. */ +#define PORTMUX_USART5_gm 0x0C /* USART5 Signals group mask. */ +#define PORTMUX_USART5_gp 2 /* USART5 Signals group position. */ +#define PORTMUX_USART50_bm (1<<2) /* USART5 Signals bit 0 mask. */ +#define PORTMUX_USART50_bp 2 /* USART5 Signals bit 0 position. */ +#define PORTMUX_USART51_bm (1<<3) /* USART5 Signals bit 1 mask. */ +#define PORTMUX_USART51_bp 3 /* USART5 Signals bit 1 position. */ + +/* PORTMUX.SPIROUTEA bit masks and bit positions */ +#define PORTMUX_SPI0_gm 0x03 /* SPI0 Signals group mask. */ +#define PORTMUX_SPI0_gp 0 /* SPI0 Signals group position. */ +#define PORTMUX_SPI00_bm (1<<0) /* SPI0 Signals bit 0 mask. */ +#define PORTMUX_SPI00_bp 0 /* SPI0 Signals bit 0 position. */ +#define PORTMUX_SPI01_bm (1<<1) /* SPI0 Signals bit 1 mask. */ +#define PORTMUX_SPI01_bp 1 /* SPI0 Signals bit 1 position. */ +#define PORTMUX_SPI1_gm 0x0C /* SPI1 Signals group mask. */ +#define PORTMUX_SPI1_gp 2 /* SPI1 Signals group position. */ +#define PORTMUX_SPI10_bm (1<<2) /* SPI1 Signals bit 0 mask. */ +#define PORTMUX_SPI10_bp 2 /* SPI1 Signals bit 0 position. */ +#define PORTMUX_SPI11_bm (1<<3) /* SPI1 Signals bit 1 mask. */ +#define PORTMUX_SPI11_bp 3 /* SPI1 Signals bit 1 position. */ + +/* PORTMUX.TWIROUTEA bit masks and bit positions */ +#define PORTMUX_TWI0_gm 0x03 /* TWI0 Signals group mask. */ +#define PORTMUX_TWI0_gp 0 /* TWI0 Signals group position. */ +#define PORTMUX_TWI00_bm (1<<0) /* TWI0 Signals bit 0 mask. */ +#define PORTMUX_TWI00_bp 0 /* TWI0 Signals bit 0 position. */ +#define PORTMUX_TWI01_bm (1<<1) /* TWI0 Signals bit 1 mask. */ +#define PORTMUX_TWI01_bp 1 /* TWI0 Signals bit 1 position. */ +#define PORTMUX_TWI1_gm 0x0C /* TWI1 Signals group mask. */ +#define PORTMUX_TWI1_gp 2 /* TWI1 Signals group position. */ +#define PORTMUX_TWI10_bm (1<<2) /* TWI1 Signals bit 0 mask. */ +#define PORTMUX_TWI10_bp 2 /* TWI1 Signals bit 0 position. */ +#define PORTMUX_TWI11_bm (1<<3) /* TWI1 Signals bit 1 mask. */ +#define PORTMUX_TWI11_bp 3 /* TWI1 Signals bit 1 position. */ + +/* PORTMUX.TCAROUTEA bit masks and bit positions */ +#define PORTMUX_TCA0_gm 0x07 /* TCA0 Signals group mask. */ +#define PORTMUX_TCA0_gp 0 /* TCA0 Signals group position. */ +#define PORTMUX_TCA00_bm (1<<0) /* TCA0 Signals bit 0 mask. */ +#define PORTMUX_TCA00_bp 0 /* TCA0 Signals bit 0 position. */ +#define PORTMUX_TCA01_bm (1<<1) /* TCA0 Signals bit 1 mask. */ +#define PORTMUX_TCA01_bp 1 /* TCA0 Signals bit 1 position. */ +#define PORTMUX_TCA02_bm (1<<2) /* TCA0 Signals bit 2 mask. */ +#define PORTMUX_TCA02_bp 2 /* TCA0 Signals bit 2 position. */ +#define PORTMUX_TCA1_gm 0x38 /* TCA1 Signals group mask. */ +#define PORTMUX_TCA1_gp 3 /* TCA1 Signals group position. */ +#define PORTMUX_TCA10_bm (1<<3) /* TCA1 Signals bit 0 mask. */ +#define PORTMUX_TCA10_bp 3 /* TCA1 Signals bit 0 position. */ +#define PORTMUX_TCA11_bm (1<<4) /* TCA1 Signals bit 1 mask. */ +#define PORTMUX_TCA11_bp 4 /* TCA1 Signals bit 1 position. */ +#define PORTMUX_TCA12_bm (1<<5) /* TCA1 Signals bit 2 mask. */ +#define PORTMUX_TCA12_bp 5 /* TCA1 Signals bit 2 position. */ + +/* PORTMUX.TCBROUTEA bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* TCB0 Output bit mask. */ +#define PORTMUX_TCB0_bp 0 /* TCB0 Output bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* TCB1 Output bit mask. */ +#define PORTMUX_TCB1_bp 1 /* TCB1 Output bit position. */ +#define PORTMUX_TCB2_bm 0x04 /* TCB2 Output bit mask. */ +#define PORTMUX_TCB2_bp 2 /* TCB2 Output bit position. */ +#define PORTMUX_TCB3_bm 0x08 /* TCB3 Output bit mask. */ +#define PORTMUX_TCB3_bp 3 /* TCB3 Output bit position. */ +#define PORTMUX_TCB4_bm 0x10 /* TCB4 Output bit mask. */ +#define PORTMUX_TCB4_bp 4 /* TCB4 Output bit position. */ + +/* PORTMUX.TCDROUTEA bit masks and bit positions */ +#define PORTMUX_TCD0_gm 0x07 /* TCD0 Signals group mask. */ +#define PORTMUX_TCD0_gp 0 /* TCD0 Signals group position. */ +#define PORTMUX_TCD00_bm (1<<0) /* TCD0 Signals bit 0 mask. */ +#define PORTMUX_TCD00_bp 0 /* TCD0 Signals bit 0 position. */ +#define PORTMUX_TCD01_bm (1<<1) /* TCD0 Signals bit 1 mask. */ +#define PORTMUX_TCD01_bp 1 /* TCD0 Signals bit 1 position. */ +#define PORTMUX_TCD02_bm (1<<2) /* TCD0 Signals bit 2 mask. */ +#define PORTMUX_TCD02_bp 2 /* TCD0 Signals bit 2 position. */ + +/* PORTMUX.ACROUTEA bit masks and bit positions */ +#define PORTMUX_AC0_bm 0x01 /* Analog Comparator 0 Output bit mask. */ +#define PORTMUX_AC0_bp 0 /* Analog Comparator 0 Output bit position. */ +#define PORTMUX_AC1_bm 0x02 /* Analog Comparator 1 Output bit mask. */ +#define PORTMUX_AC1_bp 1 /* Analog Comparator 1 Output bit position. */ +#define PORTMUX_AC2_bm 0x04 /* Analog Comparator 2 Output bit mask. */ +#define PORTMUX_AC2_bp 2 /* Analog Comparator 2 Output bit position. */ + +/* PORTMUX.ZCDROUTEA bit masks and bit positions */ +#define PORTMUX_ZCD0_bm 0x01 /* Zero Cross Detector 0 Output bit mask. */ +#define PORTMUX_ZCD0_bp 0 /* Zero Cross Detector 0 Output bit position. */ +#define PORTMUX_ZCD1_bm 0x02 /* Zero Cross Detector 1 Output bit mask. */ +#define PORTMUX_ZCD1_bp 1 /* Zero Cross Detector 1 Output bit position. */ +#define PORTMUX_ZCD2_bm 0x04 /* Zero Cross Detector 2 Output bit mask. */ +#define PORTMUX_ZCD2_bp 2 /* Zero Cross Detector 2 Output bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRST_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRST_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_CORREN_bm 0x04 /* Correction enable bit mask. */ +#define RTC_CORREN_bp 2 /* Correction enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_ERROR_gm 0x7F /* Error Correction Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Correction Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Correction Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Correction Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Correction Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Correction Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Correction Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Correction Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Correction Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Correction Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Correction Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Correction Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Correction Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Correction Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Correction Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Correction Value bit 6 position. */ +#define RTC_SIGN_bm 0x80 /* Error Correction Sign Bit bit mask. */ +#define RTC_SIGN_bp 7 /* Error Correction Sign Bit bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + +/* SIGROW - Signature row */ +/* SIGROW.TEMPSENSE0 bit masks and bit positions */ +#define SIGROW_TEMPSENSE0_gm 0xFFFF /* Temperature Calibration 0 group mask. */ +#define SIGROW_TEMPSENSE0_gp 0 /* Temperature Calibration 0 group position. */ +#define SIGROW_TEMPSENSE00_bm (1<<0) /* Temperature Calibration 0 bit 0 mask. */ +#define SIGROW_TEMPSENSE00_bp 0 /* Temperature Calibration 0 bit 0 position. */ +#define SIGROW_TEMPSENSE01_bm (1<<1) /* Temperature Calibration 0 bit 1 mask. */ +#define SIGROW_TEMPSENSE01_bp 1 /* Temperature Calibration 0 bit 1 position. */ +#define SIGROW_TEMPSENSE02_bm (1<<2) /* Temperature Calibration 0 bit 2 mask. */ +#define SIGROW_TEMPSENSE02_bp 2 /* Temperature Calibration 0 bit 2 position. */ +#define SIGROW_TEMPSENSE03_bm (1<<3) /* Temperature Calibration 0 bit 3 mask. */ +#define SIGROW_TEMPSENSE03_bp 3 /* Temperature Calibration 0 bit 3 position. */ +#define SIGROW_TEMPSENSE04_bm (1<<4) /* Temperature Calibration 0 bit 4 mask. */ +#define SIGROW_TEMPSENSE04_bp 4 /* Temperature Calibration 0 bit 4 position. */ +#define SIGROW_TEMPSENSE05_bm (1<<5) /* Temperature Calibration 0 bit 5 mask. */ +#define SIGROW_TEMPSENSE05_bp 5 /* Temperature Calibration 0 bit 5 position. */ +#define SIGROW_TEMPSENSE06_bm (1<<6) /* Temperature Calibration 0 bit 6 mask. */ +#define SIGROW_TEMPSENSE06_bp 6 /* Temperature Calibration 0 bit 6 position. */ +#define SIGROW_TEMPSENSE07_bm (1<<7) /* Temperature Calibration 0 bit 7 mask. */ +#define SIGROW_TEMPSENSE07_bp 7 /* Temperature Calibration 0 bit 7 position. */ +#define SIGROW_TEMPSENSE08_bm (1<<8) /* Temperature Calibration 0 bit 8 mask. */ +#define SIGROW_TEMPSENSE08_bp 8 /* Temperature Calibration 0 bit 8 position. */ +#define SIGROW_TEMPSENSE09_bm (1<<9) /* Temperature Calibration 0 bit 9 mask. */ +#define SIGROW_TEMPSENSE09_bp 9 /* Temperature Calibration 0 bit 9 position. */ +#define SIGROW_TEMPSENSE010_bm (1<<10) /* Temperature Calibration 0 bit 10 mask. */ +#define SIGROW_TEMPSENSE010_bp 10 /* Temperature Calibration 0 bit 10 position. */ +#define SIGROW_TEMPSENSE011_bm (1<<11) /* Temperature Calibration 0 bit 11 mask. */ +#define SIGROW_TEMPSENSE011_bp 11 /* Temperature Calibration 0 bit 11 position. */ +#define SIGROW_TEMPSENSE012_bm (1<<12) /* Temperature Calibration 0 bit 12 mask. */ +#define SIGROW_TEMPSENSE012_bp 12 /* Temperature Calibration 0 bit 12 position. */ +#define SIGROW_TEMPSENSE013_bm (1<<13) /* Temperature Calibration 0 bit 13 mask. */ +#define SIGROW_TEMPSENSE013_bp 13 /* Temperature Calibration 0 bit 13 position. */ +#define SIGROW_TEMPSENSE014_bm (1<<14) /* Temperature Calibration 0 bit 14 mask. */ +#define SIGROW_TEMPSENSE014_bp 14 /* Temperature Calibration 0 bit 14 position. */ +#define SIGROW_TEMPSENSE015_bm (1<<15) /* Temperature Calibration 0 bit 15 mask. */ +#define SIGROW_TEMPSENSE015_bp 15 /* Temperature Calibration 0 bit 15 position. */ + +/* SIGROW.TEMPSENSE1 bit masks and bit positions */ +#define SIGROW_TEMPSENSE1_gm 0xFFFF /* Temperature Calibration 1 group mask. */ +#define SIGROW_TEMPSENSE1_gp 0 /* Temperature Calibration 1 group position. */ +#define SIGROW_TEMPSENSE10_bm (1<<0) /* Temperature Calibration 1 bit 0 mask. */ +#define SIGROW_TEMPSENSE10_bp 0 /* Temperature Calibration 1 bit 0 position. */ +#define SIGROW_TEMPSENSE11_bm (1<<1) /* Temperature Calibration 1 bit 1 mask. */ +#define SIGROW_TEMPSENSE11_bp 1 /* Temperature Calibration 1 bit 1 position. */ +#define SIGROW_TEMPSENSE12_bm (1<<2) /* Temperature Calibration 1 bit 2 mask. */ +#define SIGROW_TEMPSENSE12_bp 2 /* Temperature Calibration 1 bit 2 position. */ +#define SIGROW_TEMPSENSE13_bm (1<<3) /* Temperature Calibration 1 bit 3 mask. */ +#define SIGROW_TEMPSENSE13_bp 3 /* Temperature Calibration 1 bit 3 position. */ +#define SIGROW_TEMPSENSE14_bm (1<<4) /* Temperature Calibration 1 bit 4 mask. */ +#define SIGROW_TEMPSENSE14_bp 4 /* Temperature Calibration 1 bit 4 position. */ +#define SIGROW_TEMPSENSE15_bm (1<<5) /* Temperature Calibration 1 bit 5 mask. */ +#define SIGROW_TEMPSENSE15_bp 5 /* Temperature Calibration 1 bit 5 position. */ +#define SIGROW_TEMPSENSE16_bm (1<<6) /* Temperature Calibration 1 bit 6 mask. */ +#define SIGROW_TEMPSENSE16_bp 6 /* Temperature Calibration 1 bit 6 position. */ +#define SIGROW_TEMPSENSE17_bm (1<<7) /* Temperature Calibration 1 bit 7 mask. */ +#define SIGROW_TEMPSENSE17_bp 7 /* Temperature Calibration 1 bit 7 position. */ +#define SIGROW_TEMPSENSE18_bm (1<<8) /* Temperature Calibration 1 bit 8 mask. */ +#define SIGROW_TEMPSENSE18_bp 8 /* Temperature Calibration 1 bit 8 position. */ +#define SIGROW_TEMPSENSE19_bm (1<<9) /* Temperature Calibration 1 bit 9 mask. */ +#define SIGROW_TEMPSENSE19_bp 9 /* Temperature Calibration 1 bit 9 position. */ +#define SIGROW_TEMPSENSE110_bm (1<<10) /* Temperature Calibration 1 bit 10 mask. */ +#define SIGROW_TEMPSENSE110_bp 10 /* Temperature Calibration 1 bit 10 position. */ +#define SIGROW_TEMPSENSE111_bm (1<<11) /* Temperature Calibration 1 bit 11 mask. */ +#define SIGROW_TEMPSENSE111_bp 11 /* Temperature Calibration 1 bit 11 position. */ +#define SIGROW_TEMPSENSE112_bm (1<<12) /* Temperature Calibration 1 bit 12 mask. */ +#define SIGROW_TEMPSENSE112_bp 12 /* Temperature Calibration 1 bit 12 position. */ +#define SIGROW_TEMPSENSE113_bm (1<<13) /* Temperature Calibration 1 bit 13 mask. */ +#define SIGROW_TEMPSENSE113_bp 13 /* Temperature Calibration 1 bit 13 position. */ +#define SIGROW_TEMPSENSE114_bm (1<<14) /* Temperature Calibration 1 bit 14 mask. */ +#define SIGROW_TEMPSENSE114_bp 14 /* Temperature Calibration 1 bit 14 position. */ +#define SIGROW_TEMPSENSE115_bm (1<<15) /* Temperature Calibration 1 bit 15 mask. */ +#define SIGROW_TEMPSENSE115_bp 15 /* Temperature Calibration 1 bit 15 position. */ + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SLPCTRL.VREGCTRL bit masks and bit positions */ +#define SLPCTRL_PMODE_gm 0x07 /* Performance Mode group mask. */ +#define SLPCTRL_PMODE_gp 0 /* Performance Mode group position. */ +#define SLPCTRL_PMODE0_bm (1<<0) /* Performance Mode bit 0 mask. */ +#define SLPCTRL_PMODE0_bp 0 /* Performance Mode bit 0 position. */ +#define SLPCTRL_PMODE1_bm (1<<1) /* Performance Mode bit 1 mask. */ +#define SLPCTRL_PMODE1_bp 1 /* Performance Mode bit 1 position. */ +#define SLPCTRL_PMODE2_bm (1<<2) /* Performance Mode bit 2 mask. */ +#define SLPCTRL_PMODE2_bp 2 /* Performance Mode bit 2 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Mode Wait for Receive bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Mode Wait for Receive bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.OCDMSTATUS bit masks and bit positions */ +#define SYSCFG_OCDMR_bm 0x01 /* OCD Message Read bit mask. */ +#define SYSCFG_OCDMR_bp 0 /* OCD Message Read bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ +#define TCA_SINGLE_RUNSTDBY_bm 0x80 /* Run in Standby bit mask. */ +#define TCA_SINGLE_RUNSTDBY_bp 7 /* Run in Standby bit position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTAEI_bm 0x01 /* Count on Event Input A bit mask. */ +#define TCA_SINGLE_CNTAEI_bp 0 /* Count on Event Input A bit position. */ +#define TCA_SINGLE_EVACTA_gm 0x0E /* Event Action A group mask. */ +#define TCA_SINGLE_EVACTA_gp 1 /* Event Action A group position. */ +#define TCA_SINGLE_EVACTA0_bm (1<<1) /* Event Action A bit 0 mask. */ +#define TCA_SINGLE_EVACTA0_bp 1 /* Event Action A bit 0 position. */ +#define TCA_SINGLE_EVACTA1_bm (1<<2) /* Event Action A bit 1 mask. */ +#define TCA_SINGLE_EVACTA1_bp 2 /* Event Action A bit 1 position. */ +#define TCA_SINGLE_EVACTA2_bm (1<<3) /* Event Action A bit 2 mask. */ +#define TCA_SINGLE_EVACTA2_bp 3 /* Event Action A bit 2 position. */ +#define TCA_SINGLE_CNTBEI_bm 0x10 /* Count on Event Input B bit mask. */ +#define TCA_SINGLE_CNTBEI_bp 4 /* Count on Event Input B bit position. */ +#define TCA_SINGLE_EVACTB_gm 0xE0 /* Event Action B group mask. */ +#define TCA_SINGLE_EVACTB_gp 5 /* Event Action B group position. */ +#define TCA_SINGLE_EVACTB0_bm (1<<5) /* Event Action B bit 0 mask. */ +#define TCA_SINGLE_EVACTB0_bp 5 /* Event Action B bit 0 position. */ +#define TCA_SINGLE_EVACTB1_bm (1<<6) /* Event Action B bit 1 mask. */ +#define TCA_SINGLE_EVACTB1_bp 6 /* Event Action B bit 1 position. */ +#define TCA_SINGLE_EVACTB2_bm (1<<7) /* Event Action B bit 2 mask. */ +#define TCA_SINGLE_EVACTB2_bp 7 /* Event Action B bit 2 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ +#define TCA_SPLIT_RUNSTDBY_bm 0x80 /* Run in Standby bit mask. */ +#define TCA_SPLIT_RUNSTDBY_bp 7 /* Run in Standby bit position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TCA_SPLIT_CMDEN_gp 0 /* Command Enable group position. */ +#define TCA_SPLIT_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TCA_SPLIT_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TCA_SPLIT_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TCA_SPLIT_CMDEN1_bp 1 /* Command Enable bit 1 position. */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x0E /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_CLKSEL2_bm (1<<3) /* Clock Select bit 2 mask. */ +#define TCB_CLKSEL2_bp 3 /* Clock Select bit 2 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_CASCADE_bm 0x20 /* Cascade two timers bit mask. */ +#define TCB_CASCADE_bp 5 /* Cascade two timers bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ +#define TCB_OVF_bm 0x02 /* Overflow bit mask. */ +#define TCB_OVF_bp 1 /* Overflow bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ +/* TCB_OVF is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Synchronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Synchronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Synchronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Synchronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Synchronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Synchronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ +#define TWI_INPUTLVL_bm 0x40 /* Input Voltage Transition Level bit mask. */ +#define TWI_INPUTLVL_bp 6 /* Input Voltage Transition Level bit position. */ + +/* TWI.DUALCTRL bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Dual Control Enable bit mask. */ +#define TWI_ENABLE_bp 0 /* Dual Control Enable bit position. */ +/* TWI_FMPEN is already defined. */ +/* TWI_SDAHOLD is already defined. */ +/* TWI_INPUTLVL is already defined. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.CTRLD bit masks and bit positions */ +#define USART_ABW_gm 0xC0 /* Auto Baud Window group mask. */ +#define USART_ABW_gp 6 /* Auto Baud Window group position. */ +#define USART_ABW0_bm (1<<6) /* Auto Baud Window bit 0 mask. */ +#define USART_ABW0_bp 6 /* Auto Baud Window bit 0 position. */ +#define USART_ABW1_bm (1<<7) /* Auto Baud Window bit 1 mask. */ +#define USART_ABW1_bp 7 /* Auto Baud Window bit 1 position. */ + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.ADC0REF bit masks and bit positions */ +#define VREF_REFSEL_gm 0x07 /* Reference select group mask. */ +#define VREF_REFSEL_gp 0 /* Reference select group position. */ +#define VREF_REFSEL0_bm (1<<0) /* Reference select bit 0 mask. */ +#define VREF_REFSEL0_bp 0 /* Reference select bit 0 position. */ +#define VREF_REFSEL1_bm (1<<1) /* Reference select bit 1 mask. */ +#define VREF_REFSEL1_bp 1 /* Reference select bit 1 position. */ +#define VREF_REFSEL2_bm (1<<2) /* Reference select bit 2 mask. */ +#define VREF_REFSEL2_bp 2 /* Reference select bit 2 position. */ +#define VREF_ALWAYSON_bm 0x80 /* Always on bit mask. */ +#define VREF_ALWAYSON_bp 7 /* Always on bit position. */ + +/* VREF.DAC0REF bit masks and bit positions */ +/* VREF_REFSEL is already defined. */ +/* VREF_ALWAYSON is already defined. */ + +/* VREF.ACREF bit masks and bit positions */ +/* VREF_REFSEL is already defined. */ +/* VREF_ALWAYSON is already defined. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + +/* ZCD - Zero Cross Detect */ +/* ZCD.CTRLA bit masks and bit positions */ +#define ZCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define ZCD_ENABLE_bp 0 /* Enable bit position. */ +#define ZCD_INVERT_bm 0x08 /* Invert signal from pin bit mask. */ +#define ZCD_INVERT_bp 3 /* Invert signal from pin bit position. */ +#define ZCD_OUTEN_bm 0x40 /* Output Pad Enable bit mask. */ +#define ZCD_OUTEN_bp 6 /* Output Pad Enable bit position. */ +#define ZCD_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define ZCD_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* ZCD.INTCTRL bit masks and bit positions */ +#define ZCD_INTMODE_gm 0x03 /* Interrupt Mode group mask. */ +#define ZCD_INTMODE_gp 0 /* Interrupt Mode group position. */ +#define ZCD_INTMODE0_bm (1<<0) /* Interrupt Mode bit 0 mask. */ +#define ZCD_INTMODE0_bp 0 /* Interrupt Mode bit 0 position. */ +#define ZCD_INTMODE1_bm (1<<1) /* Interrupt Mode bit 1 mask. */ +#define ZCD_INTMODE1_bp 1 /* Interrupt Mode bit 1 position. */ + +/* ZCD.STATUS bit masks and bit positions */ +#define ZCD_CROSSIF_bm 0x01 /* ZCD Interrupt Flag bit mask. */ +#define ZCD_CROSSIF_bp 0 /* ZCD Interrupt Flag bit position. */ +#define ZCD_STATE_bm 0x10 /* ZCD State bit mask. */ +#define ZCD_STATE_bp 4 /* ZCD State bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* NMI interrupt vectors */ +#define NMI_vect_num 1 +#define NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 3 +#define RTC_CNT_vect _VECTOR(3) /* */ +#define RTC_PIT_vect_num 4 +#define RTC_PIT_vect _VECTOR(4) /* */ + +/* CCL interrupt vectors */ +#define CCL_CCL_vect_num 5 +#define CCL_CCL_vect _VECTOR(5) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 6 +#define PORTA_PORT_vect _VECTOR(6) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 7 +#define TCA0_LUNF_vect _VECTOR(7) /* */ +#define TCA0_OVF_vect_num 7 +#define TCA0_OVF_vect _VECTOR(7) /* */ +#define TCA0_HUNF_vect_num 8 +#define TCA0_HUNF_vect _VECTOR(8) /* */ +#define TCA0_CMP0_vect_num 9 +#define TCA0_CMP0_vect _VECTOR(9) /* */ +#define TCA0_LCMP0_vect_num 9 +#define TCA0_LCMP0_vect _VECTOR(9) /* */ +#define TCA0_CMP1_vect_num 10 +#define TCA0_CMP1_vect _VECTOR(10) /* */ +#define TCA0_LCMP1_vect_num 10 +#define TCA0_LCMP1_vect _VECTOR(10) /* */ +#define TCA0_CMP2_vect_num 11 +#define TCA0_CMP2_vect _VECTOR(11) /* */ +#define TCA0_LCMP2_vect_num 11 +#define TCA0_LCMP2_vect _VECTOR(11) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 12 +#define TCB0_INT_vect _VECTOR(12) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 13 +#define TCB1_INT_vect _VECTOR(13) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 14 +#define TCD0_OVF_vect _VECTOR(14) /* */ +#define TCD0_TRIG_vect_num 15 +#define TCD0_TRIG_vect _VECTOR(15) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 16 +#define TWI0_TWIS_vect _VECTOR(16) /* */ +#define TWI0_TWIM_vect_num 17 +#define TWI0_TWIM_vect _VECTOR(17) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 18 +#define SPI0_INT_vect _VECTOR(18) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 19 +#define USART0_RXC_vect _VECTOR(19) /* */ +#define USART0_DRE_vect_num 20 +#define USART0_DRE_vect _VECTOR(20) /* */ +#define USART0_TXC_vect_num 21 +#define USART0_TXC_vect _VECTOR(21) /* */ + +/* PORTD interrupt vectors */ +#define PORTD_PORT_vect_num 22 +#define PORTD_PORT_vect _VECTOR(22) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 23 +#define AC0_AC_vect _VECTOR(23) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 24 +#define ADC0_RESRDY_vect _VECTOR(24) /* */ +#define ADC0_WCMP_vect_num 25 +#define ADC0_WCMP_vect _VECTOR(25) /* */ + +/* ZCD0 interrupt vectors */ +#define ZCD0_ZCD_vect_num 26 +#define ZCD0_ZCD_vect _VECTOR(26) /* */ + +/* PTC interrupt vectors */ +#define PTC_PTC_vect_num 27 +#define PTC_PTC_vect _VECTOR(27) /* */ + +/* AC1 interrupt vectors */ +#define AC1_AC_vect_num 28 +#define AC1_AC_vect _VECTOR(28) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 29 +#define PORTC_PORT_vect _VECTOR(29) /* */ + +/* TCB2 interrupt vectors */ +#define TCB2_INT_vect_num 30 +#define TCB2_INT_vect _VECTOR(30) /* */ + +/* USART1 interrupt vectors */ +#define USART1_RXC_vect_num 31 +#define USART1_RXC_vect _VECTOR(31) /* */ +#define USART1_DRE_vect_num 32 +#define USART1_DRE_vect _VECTOR(32) /* */ +#define USART1_TXC_vect_num 33 +#define USART1_TXC_vect _VECTOR(33) /* */ + +/* PORTF interrupt vectors */ +#define PORTF_PORT_vect_num 34 +#define PORTF_PORT_vect _VECTOR(34) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 35 +#define NVMCTRL_EE_vect _VECTOR(35) /* */ + +/* SPI1 interrupt vectors */ +#define SPI1_INT_vect_num 36 +#define SPI1_INT_vect _VECTOR(36) /* */ + +/* USART2 interrupt vectors */ +#define USART2_RXC_vect_num 37 +#define USART2_RXC_vect _VECTOR(37) /* */ +#define USART2_DRE_vect_num 38 +#define USART2_DRE_vect _VECTOR(38) /* */ +#define USART2_TXC_vect_num 39 +#define USART2_TXC_vect _VECTOR(39) /* */ + +/* AC2 interrupt vectors */ +#define AC2_AC_vect_num 40 +#define AC2_AC_vect _VECTOR(40) /* */ + +/* TCB3 interrupt vectors */ +#define TCB3_INT_vect_num 41 +#define TCB3_INT_vect _VECTOR(41) /* */ + +/* TWI1 interrupt vectors */ +#define TWI1_TWIS_vect_num 42 +#define TWI1_TWIS_vect _VECTOR(42) /* */ +#define TWI1_TWIM_vect_num 43 +#define TWI1_TWIM_vect _VECTOR(43) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 44 +#define PORTB_PORT_vect _VECTOR(44) /* */ + +/* PORTE interrupt vectors */ +#define PORTE_PORT_vect_num 45 +#define PORTE_PORT_vect _VECTOR(45) /* */ + +/* TCA1 interrupt vectors */ +#define TCA1_LUNF_vect_num 46 +#define TCA1_LUNF_vect _VECTOR(46) /* */ +#define TCA1_OVF_vect_num 46 +#define TCA1_OVF_vect _VECTOR(46) /* */ +#define TCA1_HUNF_vect_num 47 +#define TCA1_HUNF_vect _VECTOR(47) /* */ +#define TCA1_CMP0_vect_num 48 +#define TCA1_CMP0_vect _VECTOR(48) /* */ +#define TCA1_LCMP0_vect_num 48 +#define TCA1_LCMP0_vect _VECTOR(48) /* */ +#define TCA1_CMP1_vect_num 49 +#define TCA1_CMP1_vect _VECTOR(49) /* */ +#define TCA1_LCMP1_vect_num 49 +#define TCA1_LCMP1_vect _VECTOR(49) /* */ +#define TCA1_CMP2_vect_num 50 +#define TCA1_CMP2_vect _VECTOR(50) /* */ +#define TCA1_LCMP2_vect_num 50 +#define TCA1_LCMP2_vect _VECTOR(50) /* */ + +/* ZCD1 interrupt vectors */ +#define ZCD1_ZCD_vect_num 51 +#define ZCD1_ZCD_vect _VECTOR(51) /* */ + +/* USART3 interrupt vectors */ +#define USART3_RXC_vect_num 52 +#define USART3_RXC_vect _VECTOR(52) /* */ +#define USART3_DRE_vect_num 53 +#define USART3_DRE_vect _VECTOR(53) /* */ +#define USART3_TXC_vect_num 54 +#define USART3_TXC_vect _VECTOR(54) /* */ + +/* USART4 interrupt vectors */ +#define USART4_RXC_vect_num 55 +#define USART4_RXC_vect _VECTOR(55) /* */ +#define USART4_DRE_vect_num 56 +#define USART4_DRE_vect _VECTOR(56) /* */ +#define USART4_TXC_vect_num 57 +#define USART4_TXC_vect _VECTOR(57) /* */ + +/* PORTG interrupt vectors */ +#define PORTG_PORT_vect_num 58 +#define PORTG_PORT_vect _VECTOR(58) /* */ + +/* ZCD2 interrupt vectors */ +#define ZCD2_ZCD_vect_num 59 +#define ZCD2_ZCD_vect _VECTOR(59) /* */ + +/* TCB4 interrupt vectors */ +#define TCB4_INT_vect_num 60 +#define TCB4_INT_vect _VECTOR(60) /* */ + +/* USART5 interrupt vectors */ +#define USART5_RXC_vect_num 61 +#define USART5_RXC_vect _VECTOR(61) /* */ +#define USART5_DRE_vect_num 62 +#define USART5_DRE_vect _VECTOR(62) /* */ +#define USART5_TXC_vect_num 63 +#define USART5_TXC_vect _VECTOR(63) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (64 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (65536) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (65536U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (512) +# define EEPROM_PAGE_SIZE (1) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (512U) +# define EEPROM_PAGE_SIZE (1U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1050) +# define FUSES_SIZE (16) +# define FUSES_PAGE_SIZE (1) +#else +# define FUSES_START (0x1050U) +# define FUSES_SIZE (16U) +# define FUSES_PAGE_SIZE (1U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x4000) +# define INTERNAL_SRAM_SIZE (16384) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x4000U) +# define INTERNAL_SRAM_SIZE (16384U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4159) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4159U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x1040) +# define LOCKBITS_SIZE (4) +# define LOCKBITS_PAGE_SIZE (1) +#else +# define LOCKBITS_START (0x1040U) +# define LOCKBITS_SIZE (4U) +# define LOCKBITS_PAGE_SIZE (1U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (32768) +# define MAPPED_PROGMEM_PAGE_SIZE (512) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (32768U) +# define MAPPED_PROGMEM_PAGE_SIZE (512U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (125) +# define PROD_SIGNATURES_PAGE_SIZE (128) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (125U) +# define PROD_SIGNATURES_PAGE_SIZE (128U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (128) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (128U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1080) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1080U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (131072) +# define PROGMEM_PAGE_SIZE (512) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (131072U) +# define PROGMEM_PAGE_SIZE (512U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 16 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_CLKSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_CLKSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_CLKSEL2 (unsigned char)_BV(2) /* Frequency Select Bit 2 */ +#define FUSE2_DEFAULT (0x0) +#define FUSE_OSCCFG_DEFAULT (0x0) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSEL (unsigned char)_BV(5) /* CRC Select */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc0) +#define FUSE_SYSCFG0_DEFAULT (0xc0) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x0) +#define FUSE_SYSCFG1_DEFAULT (0x0) + +/* Fuse Byte 7 (CODESIZE) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_CODESIZE_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTSIZE) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTSIZE_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_KEY_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0x5cc5c55c) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x07 + + +#endif /* #ifdef _AVR_AVR128DA64_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iocan128.h b/hardware/tools/avr/avr/include/avr/iocan128.h new file mode 100644 index 0000000000000000000000000000000000000000..bdbfb9f08aafbd0a75fa520e279ba8c6e218d7b9 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iocan128.h @@ -0,0 +1,100 @@ +/* Copyright (c) 2004,2005, Colin O'Flynn + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iocan128.h 1767 2008-10-17 23:27:53Z arcanum $ */ + +/* iocan128.h - definitions for CAN128 */ + +#ifndef _AVR_IOCAN128_H_ +#define _AVR_IOCAN128_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 256 +#define RAMSTART 0x100 +#define RAMEND 0x10FF /* Last On-Chip SRAM Location */ +#define XRAMEND 0xFFFF +#define E2END 0x0FFF +#define E2PAGESIZE 8 +#define FLASHEND 0x1FFFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + +/* Extended Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x81 + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) + +#endif /* _AVR_IOCAN128_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iocan32.h b/hardware/tools/avr/avr/include/avr/iocan32.h new file mode 100644 index 0000000000000000000000000000000000000000..f7c148f1dae9cf058eb8bc6e2eae950b53e1b000 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iocan32.h @@ -0,0 +1,100 @@ +/* Copyright (c) 2004,2005, Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iocan32.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ + +/* iocan32.h - definitions for CAN32 */ + +#ifndef _AVR_IOCAN32_H_ +#define _AVR_IOCAN32_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 256 +#define RAMSTART 0x100 +#define RAMEND 0x08FF /* Last On-Chip SRAM Location */ +#define XRAMEND 0xFFFF +#define E2END 0x03FF +#define E2PAGESIZE 8 +#define FLASHEND 0x7FFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + +/* Extended Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x81 + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) + +#endif /* _AVR_IOCAN32_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iocan64.h b/hardware/tools/avr/avr/include/avr/iocan64.h new file mode 100644 index 0000000000000000000000000000000000000000..d07929e4e73eaba24b76d6d3d5c704764ae19722 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iocan64.h @@ -0,0 +1,100 @@ +/* Copyright (c) 2004,2005, Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iocan64.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ + +/* iocan64.h - definitions for CAN64 */ + +#ifndef _AVR_IOCAN64_H_ +#define _AVR_IOCAN64_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 256 +#define RAMSTART 0x100 +#define RAMEND 0x10FF /* Last On-Chip SRAM Location */ +#define XRAMEND 0xFFFF +#define E2END 0x07FF +#define E2PAGESIZE 8 +#define FLASHEND 0xFFFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + +/* Extended Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x81 + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) + +#endif /* _AVR_IOCAN64_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iocanxx.h b/hardware/tools/avr/avr/include/avr/iocanxx.h new file mode 100644 index 0000000000000000000000000000000000000000..cb58e1b59dc6dc86f77964f6cc323c768e07cb0a --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iocanxx.h @@ -0,0 +1,2020 @@ +/* Copyright (c) 2004,2005,2006 Colin O'Flynn + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iocanxx.h 2225 2011-03-02 16:27:26Z arcanum $ */ + +/* This file is based largely on: + - iom128.h by Peter Jansen (bit defines) + - iom169.h by Juergen Schilling + (register addresses) + - AT90CAN128 Datasheet (bit defines and register addresses) + - Appnote on Mega128 --> AT90Can128 Conversion (for what registers I need + to change) */ + +/* iocanxx.h - definitions for AT90CAN32, AT90CAN64 and AT90CAN128 */ + +#ifndef _AVR_IOCANXX_H_ +#define _AVR_IOCANXX_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iocanxx.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers and bit definitions. */ + +/* RegDef: Port A */ +#define PINA _SFR_IO8(0x00) +#define DDRA _SFR_IO8(0x01) +#define PORTA _SFR_IO8(0x02) + +/* RegDef: Port B */ +#define PINB _SFR_IO8(0x03) +#define DDRB _SFR_IO8(0x04) +#define PORTB _SFR_IO8(0x05) + +/* RegDef: Port C */ +#define PINC _SFR_IO8(0x06) +#define DDRC _SFR_IO8(0x07) +#define PORTC _SFR_IO8(0x08) + +/* RegDef: Port D */ +#define PIND _SFR_IO8(0x09) +#define DDRD _SFR_IO8(0x0A) +#define PORTD _SFR_IO8(0x0B) + +/* RegDef: Port E */ +#define PINE _SFR_IO8(0x0C) +#define DDRE _SFR_IO8(0x0D) +#define PORTE _SFR_IO8(0x0E) + +/* RegDef: Port F */ +#define PINF _SFR_IO8(0x0F) +#define DDRF _SFR_IO8(0x10) +#define PORTF _SFR_IO8(0x11) + +/* RegDef: Port G */ +#define PING _SFR_IO8(0x12) +#define DDRG _SFR_IO8(0x13) +#define PORTG _SFR_IO8(0x14) + +/* RegDef: Timer/Counter 0 interrupt Flag Register */ +#define TIFR0 _SFR_IO8(0x15) + +/* RegDef: Timer/Counter 1 interrupt Flag Register */ +#define TIFR1 _SFR_IO8(0x16) + +/* RegDef: Timer/Counter 2 interrupt Flag Register */ +#define TIFR2 _SFR_IO8(0x17) + +/* RegDef: Timer/Counter 3 interrupt Flag Register */ +#define TIFR3 _SFR_IO8(0x18) + +/* RegDef: External Interrupt Flag Register */ +#define EIFR _SFR_IO8(0x1C) + +/* RegDef: External Interrupt Mask Register */ +#define EIMSK _SFR_IO8(0x1D) + +/* RegDef: General Purpose I/O Register 0 */ +#define GPIOR0 _SFR_IO8(0x1E) + +/* RegDef: EEPROM Control Register */ +#define EECR _SFR_IO8(0x1F) + +/* RegDef: EEPROM Data Register */ +#define EEDR _SFR_IO8(0x20) + +/* RegDef: EEPROM Address Register */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +/* RegDef: General Timer/Counter Control Register */ +#define GTCCR _SFR_IO8(0x23) + +/* RegDef: Timer/Counter Control Register A */ +#define TCCR0A _SFR_IO8(0x24) + +/* RegDef: Timer/Counter Register */ +#define TCNT0 _SFR_IO8(0x26) + +/* RegDef: Output Compare Register A */ +#define OCR0A _SFR_IO8(0x27) + +/* RegDef: General Purpose I/O Register 1 */ +#define GPIOR1 _SFR_IO8(0x2A) + +/* RegDef: General Purpose I/O Register 2 */ +#define GPIOR2 _SFR_IO8(0x2B) + +/* RegDef: SPI Control Register */ +#define SPCR _SFR_IO8(0x2C) + +/* RegDef: SPI Status Register */ +#define SPSR _SFR_IO8(0x2D) + +/* RegDef: SPI Data Register */ +#define SPDR _SFR_IO8(0x2E) + +/* RegDef: Analog Comperator Control and Status Register */ +#define ACSR _SFR_IO8(0x30) + +/* RegDef: On-chip Debug Register */ +#define OCDR _SFR_IO8(0x31) + +/* RegDef: Sleep Mode Control Register */ +#define SMCR _SFR_IO8(0x33) + +/* RegDef: MCU Status Register */ +#define MCUSR _SFR_IO8(0x34) + +/* RegDef: MCU Control Rgeister */ +#define MCUCR _SFR_IO8(0x35) + +/* RegDef: Store Program Memory Control and Status Register */ +#define SPMCSR _SFR_IO8(0x37) + +/* RegDef: RAMPZ register. */ +#define RAMPZ _SFR_IO8(0x3B) + +/* RegDef: Watchdog Timer Control Register */ +#define WDTCR _SFR_MEM8(0x60) + +/* RegDef: Clock Prescale Register */ +#define CLKPR _SFR_MEM8(0x61) + +/* RegDef: Oscillator Calibration Register */ +#define OSCCAL _SFR_MEM8(0x66) + +/* RegDef: External Interrupt Control Register A */ +#define EICRA _SFR_MEM8(0x69) + +/* RegDef: External Interrupt Control Register B */ +#define EICRB _SFR_MEM8(0x6A) + +/* RegDef: Timer/Counter 0 Interrupt Mask Register */ +#define TIMSK0 _SFR_MEM8(0x6E) + +/* RegDef: Timer/Counter 1 Interrupt Mask Register */ +#define TIMSK1 _SFR_MEM8(0x6F) + +/* RegDef: Timer/Counter 2 Interrupt Mask Register */ +#define TIMSK2 _SFR_MEM8(0x70) + +/* RegDef: Timer/Counter 3 Interrupt Mask Register */ +#define TIMSK3 _SFR_MEM8(0x71) + +/* RegDef: External Memory Control Register A */ +#define XMCRA _SFR_MEM8(0x74) + +/* RegDef: External Memory Control Register A */ +#define XMCRB _SFR_MEM8(0x75) + +/* RegDef: ADC Data Register */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_MEM16(0x78) +#endif +#define ADCW _SFR_MEM16(0x78) +#define ADCL _SFR_MEM8(0x78) +#define ADCH _SFR_MEM8(0x79) + +/* RegDef: ADC Control and Status Register A */ +#define ADCSRA _SFR_MEM8(0x7A) + +/* RegDef: ADC Control and Status Register B */ +#define ADCSRB _SFR_MEM8(0x7B) + +/* RegDef: ADC Multiplex Selection Register */ +#define ADMUX _SFR_MEM8(0x7C) + +/* RegDef: Digital Input Disable Register 0 */ +#define DIDR0 _SFR_MEM8(0x7E) + +/* RegDef: Digital Input Disable Register 1 */ +#define DIDR1 _SFR_MEM8(0x7F) + +/* RegDef: Timer/Counter1 Control Register A */ +#define TCCR1A _SFR_MEM8(0x80) + +/* RegDef: Timer/Counter1 Control Register B */ +#define TCCR1B _SFR_MEM8(0x81) + +/* RegDef: Timer/Counter1 Control Register C */ +#define TCCR1C _SFR_MEM8(0x82) + +/* RegDef: Timer/Counter1 Register */ +#define TCNT1 _SFR_MEM16(0x84) +#define TCNT1L _SFR_MEM8(0x84) +#define TCNT1H _SFR_MEM8(0x85) + +/* RegDef: Timer/Counter1 Input Capture Register */ +#define ICR1 _SFR_MEM16(0x86) +#define ICR1L _SFR_MEM8(0x86) +#define ICR1H _SFR_MEM8(0x87) + +/* RegDef: Timer/Counter1 Output Compare Register A */ +#define OCR1A _SFR_MEM16(0x88) +#define OCR1AL _SFR_MEM8(0x88) +#define OCR1AH _SFR_MEM8(0x89) + +/* RegDef: Timer/Counter1 Output Compare Register B */ +#define OCR1B _SFR_MEM16(0x8A) +#define OCR1BL _SFR_MEM8(0x8A) +#define OCR1BH _SFR_MEM8(0x8B) + +/* RegDef: Timer/Counter1 Output Compare Register C */ +#define OCR1C _SFR_MEM16(0x8C) +#define OCR1CL _SFR_MEM8(0x8C) +#define OCR1CH _SFR_MEM8(0x8D) + +/* RegDef: Timer/Counter3 Control Register A */ +#define TCCR3A _SFR_MEM8(0x90) + +/* RegDef: Timer/Counter3 Control Register B */ +#define TCCR3B _SFR_MEM8(0x91) + +/* RegDef: Timer/Counter3 Control Register C */ +#define TCCR3C _SFR_MEM8(0x92) + +/* RegDef: Timer/Counter3 Register */ +#define TCNT3 _SFR_MEM16(0x94) +#define TCNT3L _SFR_MEM8(0x94) +#define TCNT3H _SFR_MEM8(0x95) + +/* RegDef: Timer/Counter3 Input Capture Register */ +#define ICR3 _SFR_MEM16(0x96) +#define ICR3L _SFR_MEM8(0x96) +#define ICR3H _SFR_MEM8(0x97) + +/* RegDef: Timer/Counter3 Output Compare Register A */ +#define OCR3A _SFR_MEM16(0x98) +#define OCR3AL _SFR_MEM8(0x98) +#define OCR3AH _SFR_MEM8(0x99) + +/* RegDef: Timer/Counter3 Output Compare Register B */ +#define OCR3B _SFR_MEM16(0x9A) +#define OCR3BL _SFR_MEM8(0x9A) +#define OCR3BH _SFR_MEM8(0x9B) + +/* RegDef: Timer/Counter3 Output Compare Register C */ +#define OCR3C _SFR_MEM16(0x9C) +#define OCR3CL _SFR_MEM8(0x9C) +#define OCR3CH _SFR_MEM8(0x9D) + +/* RegDef: Timer/Counter2 Control Register A */ +#define TCCR2A _SFR_MEM8(0xB0) + +/* RegDef: Timer/Counter2 Register */ +#define TCNT2 _SFR_MEM8(0xB2) + +/* RegDef: Timer/Counter2 Output Compare Register */ +#define OCR2A _SFR_MEM8(0xB3) + +/* RegDef: Asynchronous Status Register */ +#define ASSR _SFR_MEM8(0xB6) + +/* RegDef: TWI Bit Rate Register */ +#define TWBR _SFR_MEM8(0xB8) + +/* RegDef: TWI Status Register */ +#define TWSR _SFR_MEM8(0xB9) + +/* RegDef: TWI (Slave) Address Register */ +#define TWAR _SFR_MEM8(0xBA) + +/* RegDef: TWI Data Register */ +#define TWDR _SFR_MEM8(0xBB) + +/* RegDef: TWI Control Register */ +#define TWCR _SFR_MEM8(0xBC) + +/* RegDef: USART0 Control and Status Register A */ +#define UCSR0A _SFR_MEM8(0xC0) + +/* RegDef: USART0 Control and Status Register B */ +#define UCSR0B _SFR_MEM8(0xC1) + +/* RegDef: USART0 Control and Status Register C */ +#define UCSR0C _SFR_MEM8(0xC2) + +/* RegDef: USART0 Baud Rate Register */ +#define UBRR0 _SFR_MEM16(0xC4) +#define UBRR0L _SFR_MEM8(0xC4) +#define UBRR0H _SFR_MEM8(0xC5) + +/* RegDef: USART0 I/O Data Register */ +#define UDR0 _SFR_MEM8(0xC6) + +/* RegDef: USART1 Control and Status Register A */ +#define UCSR1A _SFR_MEM8(0xC8) + +/* RegDef: USART1 Control and Status Register B */ +#define UCSR1B _SFR_MEM8(0xC9) + +/* RegDef: USART1 Control and Status Register C */ +#define UCSR1C _SFR_MEM8(0xCA) + +/* RegDef: USART1 Baud Rate Register */ +#define UBRR1 _SFR_MEM16(0xCC) +#define UBRR1L _SFR_MEM8(0xCC) +#define UBRR1H _SFR_MEM8(0xCD) + +/* RegDef: USART1 I/O Data Register */ +#define UDR1 _SFR_MEM8(0xCE) + +/* RegDef: CAN General Control Register*/ +#define CANGCON _SFR_MEM8(0xD8) + +/* RegDef: CAN General Status Register*/ +#define CANGSTA _SFR_MEM8(0xD9) + +/* RegDef: CAN General Interrupt Register*/ +#define CANGIT _SFR_MEM8(0xDA) + +/* RegDef: CAN General Interrupt Enable Register*/ +#define CANGIE _SFR_MEM8(0xDB) + +/* Word Definition: CAN Enable MOb Register*/ +#define CANEN _SFR_MEM16(0xDC) + +/* RegDef: CAN Enable MOb Register*/ +#define CANEN2 _SFR_MEM8(0xDC) + +/* RegDef: CAN Enable MOb Register*/ +#define CANEN1 _SFR_MEM8(0xDD) + +/* Word Definition: CAN Enable Interrupt MOb Register*/ +#define CANIE _SFR_MEM16(0xDE) + +/* RegDef: CAN Enable Interrupt MOb Register*/ +#define CANIE2 _SFR_MEM8(0xDE) + +/* RegDef: CAN Enable Interrupt MOb Register*/ +#define CANIE1 _SFR_MEM8(0xDF) + +/* RegDef: CAN Status Interrupt MOb Register*/ +/* + * WARNING: Do not apply the SIT8...SIT14 constants to bits in the CANSIT + * register. + */ +#define CANSIT _SFR_MEM16(0xE0) +#define CANSIT2 _SFR_MEM8(0xE0) +#define CANSIT1 _SFR_MEM8(0xE1) + +/* RegDef: CAN Bit Timing Register 1*/ +#define CANBT1 _SFR_MEM8(0xE2) + +/* RegDef: CAN Bit Timing Register 2*/ +#define CANBT2 _SFR_MEM8(0xE3) + +/* RegDef: CAN Bit Timing Register 3*/ +#define CANBT3 _SFR_MEM8(0xE4) + +/* RegDef: CAN Timer Control Register*/ +#define CANTCON _SFR_MEM8(0xE5) + +/* RegDef: CAN Timer Register*/ +#define CANTIM _SFR_MEM16(0xE6) +#define CANTIML _SFR_MEM8(0xE6) +#define CANTIMH _SFR_MEM8(0xE7) + +/* RegDef: CAN TTC Timer Register*/ +#define CANTTC _SFR_MEM16(0xE8) +#define CANTTCL _SFR_MEM8(0xE8) +#define CANTTCH _SFR_MEM8(0xE9) + +/* RegDef: CAN Transmitt Error Counter Register*/ +#define CANTEC _SFR_MEM8(0xEA) + +/* RegDef: CAN Receive Error Counter Register*/ +#define CANREC _SFR_MEM8(0xEB) + +/* RegDef: CAN Highest Priority MOb Register*/ +#define CANHPMOB _SFR_MEM8(0xEC) + +/* RegDef: CAN Page MOb Register*/ +#define CANPAGE _SFR_MEM8(0xED) + +/* RegDef: CAN MOb Status Register*/ +#define CANSTMOB _SFR_MEM8(0xEE) + +/* RegDef: CAN MOb Control and DLC Register*/ +#define CANCDMOB _SFR_MEM8(0xEF) + +/* RegDef: CAN Identifier Tag Registers*/ +#define CANIDT _SFR_MEM32(0xF0) + +#define CANIDT4 _SFR_MEM8(0xF0) +#define CANIDT3 _SFR_MEM8(0xF1) +#define CANIDT2 _SFR_MEM8(0xF2) +#define CANIDT1 _SFR_MEM8(0xF3) + +/* RegDef: CAN Identifier Mask Registers */ +#define CANIDM _SFR_MEM32(0xF4) + +#define CANIDM4 _SFR_MEM8(0xF4) +#define CANIDM3 _SFR_MEM8(0xF5) +#define CANIDM2 _SFR_MEM8(0xF6) +#define CANIDM1 _SFR_MEM8(0xF7) + +/* RegDef: CAN TTC Timer Register*/ +#define CANSTM _SFR_MEM16(0xF8) +#define CANSTML _SFR_MEM8(0xF8) +#define CANSTMH _SFR_MEM8(0xF9) + +/* RegDef: CAN Message Register*/ +#define CANMSG _SFR_MEM8(0xFA) + +/* Interrupt vectors */ + +/* External Interrupt Request 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt Request 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* External Interrupt Request 2 */ +#define INT2_vect_num 3 +#define INT2_vect _VECTOR(3) +#define SIG_INTERRUPT2 _VECTOR(3) + +/* External Interrupt Request 3 */ +#define INT3_vect_num 4 +#define INT3_vect _VECTOR(4) +#define SIG_INTERRUPT3 _VECTOR(4) + +/* External Interrupt Request 4 */ +#define INT4_vect_num 5 +#define INT4_vect _VECTOR(5) +#define SIG_INTERRUPT4 _VECTOR(5) + +/* External Interrupt Request 5 */ +#define INT5_vect_num 6 +#define INT5_vect _VECTOR(6) +#define SIG_INTERRUPT5 _VECTOR(6) + +/* External Interrupt Request 6 */ +#define INT6_vect_num 7 +#define INT6_vect _VECTOR(7) +#define SIG_INTERRUPT6 _VECTOR(7) + +/* External Interrupt Request 7 */ +#define INT7_vect_num 8 +#define INT7_vect _VECTOR(8) +#define SIG_INTERRUPT7 _VECTOR(8) + +/* Timer/Counter2 Compare Match */ +#define TIMER2_COMP_vect_num 9 +#define TIMER2_COMP_vect _VECTOR(9) +#define SIG_OUTPUT_COMPARE2 _VECTOR(9) + +/* Timer/Counter2 Overflow */ +#define TIMER2_OVF_vect_num 10 +#define TIMER2_OVF_vect _VECTOR(10) +#define SIG_OVERFLOW2 _VECTOR(10) + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect_num 11 +#define TIMER1_CAPT_vect _VECTOR(11) +#define SIG_INPUT_CAPTURE1 _VECTOR(11) + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect_num 12 +#define TIMER1_COMPA_vect _VECTOR(12) +#define SIG_OUTPUT_COMPARE1A _VECTOR(12) + +/* Timer/Counter Compare Match B */ +#define TIMER1_COMPB_vect_num 13 +#define TIMER1_COMPB_vect _VECTOR(13) +#define SIG_OUTPUT_COMPARE1B _VECTOR(13) + +/* Timer/Counter1 Compare Match C */ +#define TIMER1_COMPC_vect_num 14 +#define TIMER1_COMPC_vect _VECTOR(14) +#define SIG_OUTPUT_COMPARE1C _VECTOR(14) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 15 +#define TIMER1_OVF_vect _VECTOR(15) +#define SIG_OVERFLOW1 _VECTOR(15) + +/* Timer/Counter0 Compare Match */ +#define TIMER0_COMP_vect_num 16 +#define TIMER0_COMP_vect _VECTOR(16) +#define SIG_OUTPUT_COMPARE0 _VECTOR(16) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 17 +#define TIMER0_OVF_vect _VECTOR(17) +#define SIG_OVERFLOW0 _VECTOR(17) + +/* CAN Transfer Complete or Error */ +#define CANIT_vect_num 18 +#define CANIT_vect _VECTOR(18) +#define SIG_CAN_INTERRUPT1 _VECTOR(18) + +/* CAN Timer Overrun */ +#define OVRIT_vect_num 19 +#define OVRIT_vect _VECTOR(19) +#define SIG_CAN_OVERFLOW1 _VECTOR(19) + +/* SPI Serial Transfer Complete */ +#define SPI_STC_vect_num 20 +#define SPI_STC_vect _VECTOR(20) +#define SIG_SPI _VECTOR(20) + +/* USART0, Rx Complete */ +#define USART0_RX_vect_num 21 +#define USART0_RX_vect _VECTOR(21) +#define SIG_UART0_RECV _VECTOR(21) +#define SIG_USART0_RECV _VECTOR(21) + +/* USART0 Data Register Empty */ +#define USART0_UDRE_vect_num 22 +#define USART0_UDRE_vect _VECTOR(22) +#define SIG_UART0_DATA _VECTOR(22) +#define SIG_USART0_DATA _VECTOR(22) + +/* USART0, Tx Complete */ +#define USART0_TX_vect_num 23 +#define USART0_TX_vect _VECTOR(23) +#define SIG_UART0_TRANS _VECTOR(23) +#define SIG_USART0_TRANS _VECTOR(23) + +/* Analog Comparator */ +#define ANALOG_COMP_vect_num 24 +#define ANALOG_COMP_vect _VECTOR(24) +#define SIG_COMPARATOR _VECTOR(24) + +/* ADC Conversion Complete */ +#define ADC_vect_num 25 +#define ADC_vect _VECTOR(25) +#define SIG_ADC _VECTOR(25) + +/* EEPROM Ready */ +#define EE_READY_vect_num 26 +#define EE_READY_vect _VECTOR(26) +#define SIG_EEPROM_READY _VECTOR(26) + +/* Timer/Counter3 Capture Event */ +#define TIMER3_CAPT_vect_num 27 +#define TIMER3_CAPT_vect _VECTOR(27) +#define SIG_INPUT_CAPTURE3 _VECTOR(27) + +/* Timer/Counter3 Compare Match A */ +#define TIMER3_COMPA_vect_num 28 +#define TIMER3_COMPA_vect _VECTOR(28) +#define SIG_OUTPUT_COMPARE3A _VECTOR(28) + +/* Timer/Counter3 Compare Match B */ +#define TIMER3_COMPB_vect_num 29 +#define TIMER3_COMPB_vect _VECTOR(29) +#define SIG_OUTPUT_COMPARE3B _VECTOR(29) + +/* Timer/Counter3 Compare Match C */ +#define TIMER3_COMPC_vect_num 30 +#define TIMER3_COMPC_vect _VECTOR(30) +#define SIG_OUTPUT_COMPARE3C _VECTOR(30) + +/* Timer/Counter3 Overflow */ +#define TIMER3_OVF_vect_num 31 +#define TIMER3_OVF_vect _VECTOR(31) +#define SIG_OVERFLOW3 _VECTOR(31) + +/* USART1, Rx Complete */ +#define USART1_RX_vect_num 32 +#define USART1_RX_vect _VECTOR(32) +#define SIG_UART1_RECV _VECTOR(32) +#define SIG_USART1_RECV _VECTOR(32) + +/* USART1, Data Register Empty */ +#define USART1_UDRE_vect_num 33 +#define USART1_UDRE_vect _VECTOR(33) +#define SIG_UART1_DATA _VECTOR(33) +#define SIG_USART1_DATA _VECTOR(33) + +/* USART1, Tx Complete */ +#define USART1_TX_vect_num 34 +#define USART1_TX_vect _VECTOR(34) +#define SIG_UART1_TRANS _VECTOR(34) +#define SIG_USART1_TRANS _VECTOR(34) + +/* 2-wire Serial Interface */ +#define TWI_vect_num 35 +#define TWI_vect _VECTOR(35) +#define SIG_2WIRE_SERIAL _VECTOR(35) + +/* Store Program Memory Read */ +#define SPM_READY_vect_num 36 +#define SPM_READY_vect _VECTOR(36) +#define SIG_SPM_READY _VECTOR(36) + +#define _VECTORS_SIZE 148 + +/* The Register Bit names are represented by their bit number (0-7). */ + +/* Register Bits [ASSR] */ +/* Asynchronous Status Register */ +#define EXCLK 4 +#define AS2 3 +#define TCN2UB 2 +#define OCR2UB 1 +#define TCR2UB 0 +/* End Register Bits */ + +/* Register Bits [TWCR] */ +/* 2-wire Control Register - TWCR */ +#define TWINT 7 +#define TWEA 6 +#define TWSTA 5 +#define TWSTO 4 +#define TWWC 3 +#define TWEN 2 +#define TWIE 0 +/* End Register Bits */ + +/* Register Bits [TWAR] */ +/* 2-wire Address Register - TWAR */ +#define TWA6 7 +#define TWA5 6 +#define TWA4 5 +#define TWA3 4 +#define TWA2 3 +#define TWA1 2 +#define TWA0 1 +#define TWGCE 0 +/* End Register Bits */ + +/* Register Bits [TWSR] */ +/* 2-wire Status Register - TWSR */ +#define TWS7 7 +#define TWS6 6 +#define TWS5 5 +#define TWS4 4 +#define TWS3 3 +#define TWPS1 1 +#define TWPS0 0 +/* End Register Bits */ + +/* Register Bits [XMCRB] */ +/* External Memory Control Register B - XMCRB */ +#define XMBK 7 +#define XMM2 2 +#define XMM1 1 +#define XMM0 0 +/* End Register Bits */ + +/* Register Bits [XMCRA] */ +/* External Memory Control Register A - XMCRA */ +#define SRE 7 +#define SRL2 6 +#define SRL1 5 +#define SRL0 4 +#define SRW11 3 +#define SRW10 2 +#define SRW01 1 +#define SRW00 0 +/* End Register Bits */ + +/* Register Bits [RAMPZ] */ +/* RAM Page Z select register - RAMPZ */ +#define RAMPZ0 0 +/* End Register Bits */ + +/* Register Bits [EICRA] */ +/* External Interrupt Control Register A - EICRA */ +#define ISC31 7 +#define ISC30 6 +#define ISC21 5 +#define ISC20 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 +/* End Register Bits */ + +/* Register Bits [EICRB] */ +/* External Interrupt Control Register B - EICRB */ +#define ISC71 7 +#define ISC70 6 +#define ISC61 5 +#define ISC60 4 +#define ISC51 3 +#define ISC50 2 +#define ISC41 1 +#define ISC40 0 +/* End Register Bits */ + +/* Register Bits [SPMCSR] */ +/* Store Program Memory Control Register - SPMCSR, SPMCR */ +#define SPMIE 7 +#define RWWSB 6 +#define RWWSRE 4 +#define BLBSET 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 +/* End Register Bits */ + +/* Register Bits [EIMSK] */ +/* External Interrupt MaSK register - EIMSK */ +#define INT7 7 +#define INT6 6 +#define INT5 5 +#define INT4 4 +#define INT3 3 +#define INT2 2 +#define INT1 1 +#define INT0 0 +/* End Register Bits */ + +/* Register Bits [EIFR] */ +/* External Interrupt Flag Register - EIFR */ +#define INTF7 7 +#define INTF6 6 +#define INTF5 5 +#define INTF4 4 +#define INTF3 3 +#define INTF2 2 +#define INTF1 1 +#define INTF0 0 +/* End Register Bits */ + +/* Register Bits [TCCR2] */ +/* Timer/Counter 2 Control Register - TCCR2 */ +#define FOC2A 7 +#define WGM20 6 +#define COM2A1 5 +#define COM2A0 4 +#define WGM21 3 +#define CS22 2 +#define CS21 1 +#define CS20 0 +/* End Register Bits */ + +/* Register Bits [TCCR1A] */ +/* Timer/Counter 1 Control and Status Register A - TCCR1A */ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define COM1C1 3 +#define COM1C0 2 +#define WGM11 1 +#define WGM10 0 +/* End Register Bits */ + +/* Register Bits [TCCR3A] */ +/* Timer/Counter 3 Control and Status Register A - TCCR3A */ +#define COM3A1 7 +#define COM3A0 6 +#define COM3B1 5 +#define COM3B0 4 +#define COM3C1 3 +#define COM3C0 2 +#define WGM31 1 +#define WGM30 0 +/* End Register Bits */ + +/* Register Bits [TCCR1B] */ +/* Timer/Counter 1 Control and Status Register B - TCCR1B */ +#define ICNC1 7 +#define ICES1 6 +#define WGM13 4 +#define WGM12 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 +/* End Register Bits */ + +/* Register Bits [TCCR3B] */ +/* Timer/Counter 3 Control and Status Register B - TCCR3B */ +#define ICNC3 7 +#define ICES3 6 +#define WGM33 4 +#define WGM32 3 +#define CS32 2 +#define CS31 1 +#define CS30 0 +/* End Register Bits */ + +/* Register Bits [TCCR3C] */ +/* Timer/Counter 3 Control Register C - TCCR3C */ +#define FOC3A 7 +#define FOC3B 6 +#define FOC3C 5 +/* End Register Bits */ + +/* Register Bits [TCCR1C] */ +/* Timer/Counter 1 Control Register C - TCCR1C */ +#define FOC1A 7 +#define FOC1B 6 +#define FOC1C 5 +/* End Register Bits */ + +/* Register Bits [OCDR] */ +/* On-chip Debug Register - OCDR */ +#define IDRD 7 +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 +/* End Register Bits */ + +/* Register Bits [WDTCR] */ +/* Watchdog Timer Control Register - WDTCR */ +#define WDCE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 +/* End Register Bits */ + +/* Register Bits [SPSR] */ +/* SPI Status Register - SPSR */ +#define SPIF 7 +#define WCOL 6 +#define SPI2X 0 +/* End Register Bits */ + +/* Register Bits [SPCR] */ +/* SPI Control Register - SPCR */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 +/* End Register Bits */ + +/* Register Bits [UCSR1C] */ +/* USART1 Register C - UCSR1C */ +#define UMSEL1 6 +#define UPM11 5 +#define UPM10 4 +#define USBS1 3 +#define UCSZ11 2 +#define UCSZ10 1 +#define UCPOL1 0 +/* End Register Bits */ + +/* Register Bits [UCSR0C] */ +/* USART0 Register C - UCSR0C */ +#define UMSEL0 6 +#define UPM01 5 +#define UPM00 4 +#define USBS0 3 +#define UCSZ01 2 +#define UCSZ00 1 +#define UCPOL0 0 +/* End Register Bits */ + +/* Register Bits [UCSR1A] */ +/* USART1 Status Register A - UCSR1A */ +#define RXC1 7 +#define TXC1 6 +#define UDRE1 5 +#define FE1 4 +#define DOR1 3 +#define UPE1 2 +#define U2X1 1 +#define MPCM1 0 +/* End Register Bits */ + +/* Register Bits [UCSR0A] */ +/* USART0 Status Register A - UCSR0A */ +#define RXC0 7 +#define TXC0 6 +#define UDRE0 5 +#define FE0 4 +#define DOR0 3 +#define UPE0 2 +#define U2X0 1 +#define MPCM0 0 +/* End Register Bits */ + +/* Register Bits [UCSR1B] */ +/* USART1 Control Register B - UCSR1B */ +#define RXCIE1 7 +#define TXCIE1 6 +#define UDRIE1 5 +#define RXEN1 4 +#define TXEN1 3 +#define UCSZ12 2 +#define RXB81 1 +#define TXB81 0 +/* End Register Bits */ + +/* Register Bits [UCSR0B] */ +/* USART0 Control Register B - UCSR0B */ +#define RXCIE0 7 +#define TXCIE0 6 +#define UDRIE0 5 +#define RXEN0 4 +#define TXEN0 3 +#define UCSZ02 2 +#define RXB80 1 +#define TXB80 0 +/* End Register Bits */ + +/* Register Bits [ACSR] */ +/* Analog Comparator Control and Status Register - ACSR */ +#define ACD 7 +#define ACBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 +/* End Register Bits */ + +/* Register Bits [ADCSRA] */ +/* ADC Control and status register - ADCSRA */ +#define ADEN 7 +#define ADSC 6 +#define ADATE 5 +#define ADIF 4 +#define ADIE 3 +#define ADPS2 2 +#define ADPS1 1 +#define ADPS0 0 +/* End Register Bits */ + +/* + The ADHSM bit has been removed from all documentation, + as being not needed at all since the comparator has proven + to be fast enough even without feeding it more power. +*/ + +/* Register Bits [ADCSRB] */ +/* ADC Control and status register - ADCSRB */ +#define ACME 6 +#define ADTS2 2 +#define ADTS1 1 +#define ADTS0 0 +/* End Register Bits */ + +/* Register Bits [ADMUX] */ +/* ADC Multiplexer select - ADMUX */ +#define REFS1 7 +#define REFS0 6 +#define ADLAR 5 +#define MUX4 4 +#define MUX3 3 +#define MUX2 2 +#define MUX1 1 +#define MUX0 0 +/* End Register Bits */ + +/* Register Bits [DIDR0] */ +/* Digital Input Disable Register 0 */ +#define ADC7D 7 +#define ADC6D 6 +#define ADC5D 5 +#define ADC4D 4 +#define ADC3D 3 +#define ADC2D 2 +#define ADC1D 1 +#define ADC0D 0 +/* End Register Bits */ + +/* Register Bits [DIDR1] */ +/* Digital Input Disable Register 1 */ +#define AIN1D 1 +#define AIN0D 0 +/* End Register Bits */ + +/* Register Bits [PORTA] */ +/* Port A Data Register - PORTA */ +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 +/* End Register Bits */ + +/* Register Bits [DDRA] */ +/* Port A Data Direction Register - DDRA */ +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 +/* End Register Bits */ + +/* Register Bits [PINA] */ +/* Port A Input Pins - PINA */ +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 +/* End Register Bits */ + +/* Register Bits [PORTB] */ +/* Port B Data Register - PORTB */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 +/* End Register Bits */ + +/* Register Bits [DDRB] */ +/* Port B Data Direction Register - DDRB */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 +/* End Register Bits */ + +/* Register Bits [PINB] */ +/* Port B Input Pins - PINB */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 +/* End Register Bits */ + +/* Register Bits [PORTC] */ +/* Port C Data Register - PORTC */ +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 +/* End Register Bits */ + +/* Register Bits [DDRC] */ +/* Port C Data Direction Register - DDRC */ +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 +/* End Register Bits */ + +/* Register Bits [PINC] */ +/* Port C Input Pins - PINC */ +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 +/* End Register Bits */ + +/* Register Bits [PORTD] */ +/* Port D Data Register - PORTD */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 +/* End Register Bits */ + +/* Register Bits [DDRD] */ +/* Port D Data Direction Register - DDRD */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 +/* End Register Bits */ + +/* Register Bits [PIND] */ +/* Port D Input Pins - PIND */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 +/* End Register Bits */ + +/* Register Bits [PORTE] */ +/* Port E Data Register - PORTE */ +#define PE7 7 +#define PE6 6 +#define PE5 5 +#define PE4 4 +#define PE3 3 +#define PE2 2 +#define PE1 1 +#define PE0 0 +/* End Register Bits */ + +/* Register Bits [DDRE] */ +/* Port E Data Direction Register - DDRE */ +#define DDE7 7 +#define DDE6 6 +#define DDE5 5 +#define DDE4 4 +#define DDE3 3 +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 +/* End Register Bits */ + +/* Register Bits [PINE] */ +/* Port E Input Pins - PINE */ +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 +/* End Register Bits */ + +/* Register Bits [PORTF] */ +/* Port F Data Register - PORTF */ +#define PF7 7 +#define PF6 6 +#define PF5 5 +#define PF4 4 +#define PF3 3 +#define PF2 2 +#define PF1 1 +#define PF0 0 +/* End Register Bits */ + +/* Register Bits [DDRF] */ +/* Port F Data Direction Register - DDRF */ +#define DDF7 7 +#define DDF6 6 +#define DDF5 5 +#define DDF4 4 +#define DDF3 3 +#define DDF2 2 +#define DDF1 1 +#define DDF0 0 +/* End Register Bits */ + +/* Register Bits [PINF] */ +/* Port F Input Pins - PINF */ +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 +/* End Register Bits */ + +/* Register Bits [PORTG] */ +/* Port G Data Register - PORTG */ +#define PG4 4 +#define PG3 3 +#define PG2 2 +#define PG1 1 +#define PG0 0 +/* End Register Bits */ + +/* Register Bits [DDRG] */ +/* Port G Data Direction Register - DDRG */ +#define DDG4 4 +#define DDG3 3 +#define DDG2 2 +#define DDG1 1 +#define DDG0 0 +/* End Register Bits */ + +/* Register Bits [PING] */ +/* Port G Input Pins - PING */ +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 +/* End Register Bits */ + + +/* Register Bits [TIFR0] */ +/* Timer/Counter 0 interrupt Flag Register */ +#define OCF0A 1 +#define TOV0 0 +/* End Register Bits */ + +/* Register Bits [TIFR1] */ +/* Timer/Counter 1 interrupt Flag Register */ +#define ICF1 5 +#define OCF1C 3 +#define OCF1B 2 +#define OCF1A 1 +#define TOV1 0 +/* End Register Bits */ + +/* Register Bits [TIFR2] */ +/* Timer/Counter 2 interrupt Flag Register */ +#define OCF2A 1 +#define TOV2 0 +/* End Register Bits */ + +/* Register Bits [TIFR3] */ +/* Timer/Counter 3 interrupt Flag Register */ +#define ICF3 5 +#define OCF3C 3 +#define OCF3B 2 +#define OCF3A 1 +#define TOV3 0 +/* End Register Bits */ + +/* Register Bits [GPIOR0] */ +/* General Purpose I/O Register 0 */ +#define GPIOR07 7 +#define GPIOR06 6 +#define GPIOR05 5 +#define GPIOR04 4 +#define GPIOR03 3 +#define GPIOR02 2 +#define GPIOR01 1 +#define GPIOR00 0 +/* End Register Bits */ + +/* Register Bits [GPIOR1] */ +/* General Purpose I/O Register 1 */ +#define GPIOR17 7 +#define GPIOR16 6 +#define GPIOR15 5 +#define GPIOR14 4 +#define GPIOR13 3 +#define GPIOR12 2 +#define GPIOR11 1 +#define GPIOR10 0 +/* End Register Bits */ + +/* Register Bits [GPIOR2] */ +/* General Purpose I/O Register 2 */ +#define GPIOR27 7 +#define GPIOR26 6 +#define GPIOR25 5 +#define GPIOR24 4 +#define GPIOR23 3 +#define GPIOR22 2 +#define GPIOR21 1 +#define GPIOR20 0 +/* End Register Bits */ + +/* Register Bits [EECR] */ +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 +/* End Register Bits */ + +/* Register Bits [EEDR] */ +/* EEPROM Data Register */ +#define EEDR7 7 +#define EEDR6 6 +#define EEDR5 5 +#define EEDR4 4 +#define EEDR3 3 +#define EEDR2 2 +#define EEDR1 1 +#define EEDR0 0 +/* End Register Bits */ + +/* Register Bits [EEARL] */ +/* EEPROM Address Register */ +#define EEAR7 7 +#define EEAR6 6 +#define EEAR5 5 +#define EEAR4 4 +#define EEAR3 3 +#define EEAR2 2 +#define EEAR1 1 +#define EEAR0 0 +/* End Register Bits */ + +/* Register Bits [EEARH] */ +/* EEPROM Address Register */ +#define EEAR11 3 +#define EEAR10 2 +#define EEAR9 1 +#define EEAR8 0 +/* End Register Bits */ + +/* Register Bits [GTCCR] */ +/* General Timer/Counter Control Register */ +#define TSM 7 +#define PSR2 1 +#define PSR310 0 +/* End Register Bits */ + +/* Register Bits [TCCR0A] */ +/* Timer/Counter Control Register A */ +/* ALSO COVERED IN GENERIC SECTION */ +#define FOC0A 7 +#define WGM00 6 +#define COM0A1 5 +#define COM0A0 4 +#define WGM01 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 +/* End Register Bits */ + +/* Register Bits [OCR0A] */ +/* Output Compare Register A */ +#define OCR0A7 7 +#define OCR0A6 6 +#define OCR0A5 5 +#define OCR0A4 4 +#define OCR0A3 3 +#define OCR0A2 2 +#define OCR0A1 1 +#define OCR0A0 0 +/* End Register Bits */ + + +/* Register Bits [SPIDR] */ +/* SPI Data Register */ +#define SPD7 7 +#define SPD6 6 +#define SPD5 5 +#define SPD4 4 +#define SPD3 3 +#define SPD2 2 +#define SPD1 1 +#define SPD0 0 +/* End Register Bits */ + +/* Register Bits [SMCR] */ +/* Sleep Mode Control Register */ +#define SM2 3 +#define SM1 2 +#define SM0 1 +#define SE 0 +/* End Register Bits */ + +/* Register Bits [MCUSR] */ +/* MCU Status Register */ +#define JTRF 4 +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 +/* End Register Bits */ + +/* Register Bits [MCUCR] */ +/* MCU Control Register */ +#define JTD 7 +#define PUD 4 +#define IVSEL 1 +#define IVCE 0 +/* End Register Bits */ + +/* Register Bits [CLKPR] */ +/* Clock Prescale Register */ +#define CLKPCE 7 +#define CLKPS3 3 +#define CLKPS2 2 +#define CLKPS1 1 +#define CLKPS0 0 +/* End Register Bits */ + +/* Register Bits [OSCCAL] */ +/* Oscillator Calibration Register */ +#define CAL6 6 +#define CAL5 5 +#define CAL4 4 +#define CAL3 3 +#define CAL2 2 +#define CAL1 1 +#define CAL0 0 +/* End Register Bits */ + +/* Register Bits [TIMSK0] */ +/* Timer/Counter 0 interrupt mask Register */ +#define OCIE0A 1 +#define TOIE0 0 +/* End Register Bits */ + +/* Register Bits [TIMSK1] */ +/* Timer/Counter 1 interrupt mask Register */ +#define ICIE1 5 +#define OCIE1C 3 +#define OCIE1B 2 +#define OCIE1A 1 +#define TOIE1 0 +/* End Register Bits */ + +/* Register Bits [TIMSK2] */ +/* Timer/Counter 2 interrupt mask Register */ +#define OCIE2A 1 +#define TOIE2 0 +/* End Register Bits */ + +/* Register Bits [TIMSK3] */ +/* Timer/Counter 3 interrupt mask Register */ +#define ICIE3 5 +#define OCIE3C 3 +#define OCIE3B 2 +#define OCIE3A 1 +#define TOIE3 0 +/* End Register Bits */ + +//Begin CAN specific parts + +/* Register Bits [CANGCON] */ +/* CAN General Control Register */ +#define ABRQ 7 +#define OVRQ 6 +#define TTC 5 +#define SYNTTC 4 +#define LISTEN 3 +#define TEST 2 +#define ENASTB 1 +#define SWRES 0 +/* End Register Bits */ + +/* Register Bits [CANGSTA] */ +/* CAN General Status Register */ +#define OVFG 6 +#define OVRG 6 +#define TXBSY 4 +#define RXBSY 3 +#define ENFG 2 +#define BOFF 1 +#define ERRP 0 +/* End Register Bits */ + +/* Register Bits [CANGIT] */ +/* CAN General Interrupt Register */ +#define CANIT 7 +#define BOFFIT 6 +#define OVRTIM 5 +#define BXOK 4 +#define SERG 3 +#define CERG 2 +#define FERG 1 +#define AERG 0 +/* End Register Bits */ + +/* Register Bits [CANGIE] */ +/* CAN General Interrupt Enable */ +#define ENIT 7 +#define ENBOFF 6 +#define ENRX 5 +#define ENTX 4 +#define ENERR 3 +#define ENBX 2 +#define ENERG 1 +#define ENOVRT 0 +/* End Register Bits */ + +/* Register Bits [CANEN2] */ +/* CAN Enable MOb Register */ +#define ENMOB7 7 +#define ENMOB6 6 +#define ENMOB5 5 +#define ENMOB4 4 +#define ENMOB3 3 +#define ENMOB2 2 +#define ENMOB1 1 +#define ENMOB0 0 +/* End Register Bits */ + +/* Register Bits [CANEN1] */ +/* CAN Enable MOb Register */ +#define ENMOB14 6 +#define ENMOB13 5 +#define ENMOB12 4 +#define ENMOB11 3 +#define ENMOB10 2 +#define ENMOB9 1 +#define ENMOB8 0 +/* End Register Bits */ + +/* Register Bits [CANIE2] */ +/* CAN Interrupt Enable MOb Register */ +#define IEMOB7 7 +#define IEMOB6 6 +#define IEMOB5 5 +#define IEMOB4 4 +#define IEMOB3 3 +#define IEMOB2 2 +#define IEMOB1 1 +#define IEMOB0 0 +/* End Register Bits */ + +/* Register Bits [CANIE1] */ +/* CAN Interrupt Enable MOb Register */ +#define IEMOB14 6 +#define IEMOB13 5 +#define IEMOB12 4 +#define IEMOB11 3 +#define IEMOB10 2 +#define IEMOB9 1 +#define IEMOB8 0 +/* End Register Bits */ + +/* Register Bits [CANSIT2] */ +/* CAN Status Interrupt MOb Register */ +#define SIT7 7 +#define SIT6 6 +#define SIT5 5 +#define SIT4 4 +#define SIT3 3 +#define SIT2 2 +#define SIT1 1 +#define SIT0 0 +/* End Register Bits */ + +/* Register Bits [CANSIT1] */ +/* CAN Status Interrupt MOb Register */ +#define SIT14 6 +#define SIT13 5 +#define SIT12 4 +#define SIT11 3 +#define SIT10 2 +#define SIT9 1 +#define SIT8 0 +/* End Register Bits */ + +/* Register Bits [CANBT1] */ +/* Bit Timing Register 1 */ +#define BRP5 6 +#define BRP4 5 +#define BRP3 4 +#define BRP2 3 +#define BRP1 2 +#define BRP0 1 +/* End Register Bits */ + +/* Register Bits [CANBT2] */ +/* Bit Timing Register 2 */ +#define SJW1 6 +#define SJW0 5 +#define PRS2 3 +#define PRS1 2 +#define PRS0 1 +/* End Register Bits */ + +/* Register Bits [CANBT3] */ +/* Bit Timing Register 3 */ +#define PHS22 6 +#define PHS21 5 +#define PHS20 4 +#define PHS12 3 +#define PHS11 2 +#define PHS10 1 +#define SMP 0 +/* End Register Bits */ + +/* Register Bits [CANTCON] */ +/* CAN Timer Control Register */ +#define TPRSC7 7 +#define TPRSC6 6 +#define TPRSC5 5 +#define TPRSC4 4 +#define TPRSC3 3 +#define TPRSC2 2 +#define TPRSC1 1 +#define TPRSC0 0 +/* End Register Bits */ + +/* Register Bits [CANTIML] */ +/* CAN Timer Register Low */ +#define CANTIM7 7 +#define CANTIM6 6 +#define CANTIM5 5 +#define CANTIM4 4 +#define CANTIM3 3 +#define CANTIM2 2 +#define CANTIM1 1 +#define CANTIM0 0 +/* End Register Bits */ + +/* Register Bits [CANTIMH] */ +/* CAN Timer Register High */ +#define CANTIM15 7 +#define CANTIM14 6 +#define CANTIM13 5 +#define CANTIM12 4 +#define CANTIM11 3 +#define CANTIM10 2 +#define CANTIM9 1 +#define CANTIM8 0 +/* End Register Bits */ + +/* Register Bits [CANTTCL] */ +/* CAN TTC Timer Register Low */ +#define TIMTTC7 7 +#define TIMTTC6 6 +#define TIMTTC5 5 +#define TIMTTC4 4 +#define TIMTTC3 3 +#define TIMTTC2 2 +#define TIMTTC1 1 +#define TIMTTC0 0 +/* End Register Bits */ + +/* Register Bits [CANTTCH] */ +/* CAN TTC Timer Register High */ +#define TIMTTC15 7 +#define TIMTTC14 6 +#define TIMTTC13 5 +#define TIMTTC12 4 +#define TIMTTC11 3 +#define TIMTTC10 2 +#define TIMTTC9 1 +#define TIMTTC8 0 +/* End Register Bits */ + +/* Register Bits [CANTEC] */ +/* CAN Transmitt Error Counter */ +#define TEC7 7 +#define TEC6 6 +#define TEC5 5 +#define TEC4 4 +#define TEC3 3 +#define TEC2 2 +#define TEC1 1 +#define TEC0 0 +/* End Register Bits */ + +/* Register Bits [CANREC] */ +/* CAN Receive Error Counter */ +#define REC7 7 +#define REC6 6 +#define REC5 5 +#define REC4 4 +#define REC3 3 +#define REC2 2 +#define REC1 1 +#define REC0 0 +/* End Register Bits */ + +/* Register Bits [CANHPMOB] */ +/* Highest Priority MOb */ +#define HPMOB3 7 +#define HPMOB2 6 +#define HPMOB1 5 +#define HPMOB0 4 +#define CGP3 3 +#define CGP2 2 +#define CGP1 1 +#define CGP0 0 +/* End Register Bits */ + +/* Register Bits [CANPAGE] */ +/* CAN Page MOb Register */ +#define MOBNB3 7 +#define MOBNB2 6 +#define MOBNB1 5 +#define MOBNB0 4 +#define AINC 3 +#define INDX2 2 +#define INDX1 1 +#define INDX0 0 +/* End Register Bits */ + +/* Register Bits [CANSTMOB] */ +/* CAN MOb Status Register */ +#define DLCW 7 +#define TXOK 6 +#define RXOK 5 +#define BERR 4 +#define SERR 3 +#define CERR 2 +#define FERR 1 +#define AERR 0 +/* End Register Bits */ + +/* Register Bits [CANCDMOB] */ +/* CAN MOb Control and DLC Register */ +#define CONMOB1 7 +#define CONMOB0 6 +#define RPLV 5 +#define IDE 4 +#define DLC3 3 +#define DLC2 2 +#define DLC1 1 +#define DLC0 0 +/* End Register Bits */ + +/* Register Bits [CANIDT4] */ +/* CAN Identifier Tag Register 4 */ +#define IDT4 7 +#define IDT3 6 +#define IDT2 5 +#define IDT1 4 +#define IDT0 3 +#define RTRTAG 2 +#define RB1TAG 1 +#define RB0TAG 0 +/* End Register Bits */ + +/* Register Bits [CANIDT3] */ +/* CAN Identifier Tag Register 3 */ +#define IDT12 7 +#define IDT11 6 +#define IDT10 5 +#define IDT9 4 +#define IDT8 3 +#define IDT7 2 +#define IDT6 1 +#define IDT5 0 +/* End Register Bits */ + +/* Register Bits [CANIDT2] */ +/* CAN Identifier Tag Register 2 */ +#define IDT20 7 +#define IDT19 6 +#define IDT18 5 +#define IDT17 4 +#define IDT16 3 +#define IDT15 2 +#define IDT14 1 +#define IDT13 0 +/* End Register Bits */ + +/* Register Bits [CANIDT1] */ +/* CAN Identifier Tag Register 1 */ +#define IDT28 7 +#define IDT27 6 +#define IDT26 5 +#define IDT25 4 +#define IDT24 3 +#define IDT23 2 +#define IDT22 1 +#define IDT21 0 +/* End Register Bits */ + +/* Register Bits [CANIDM4] */ +/* CAN Identifier Mask Register 4 */ +#define IDMSK4 7 +#define IDMSK3 6 +#define IDMSK2 5 +#define IDMSK1 4 +#define IDMSK0 3 +#define RTRMSK 2 +#define IDEMSK 0 +/* End Register Bits */ + +/* Register Bits [CANIDM3] */ +/* CAN Identifier Mask Register 3 */ +#define IDMSK12 7 +#define IDMSK11 6 +#define IDMSK10 5 +#define IDMSK9 4 +#define IDMSK8 3 +#define IDMSK7 2 +#define IDMSK6 1 +#define IDMSK5 0 +/* End Register Bits */ + +/* Register Bits [CANIDM2] */ +/* CAN Identifier Mask Register 2 */ +#define IDMSK20 7 +#define IDMSK19 6 +#define IDMSK18 5 +#define IDMSK17 4 +#define IDMSK16 3 +#define IDMSK15 2 +#define IDMSK14 1 +#define IDMSK13 0 +/* End Register Bits */ + +/* Register Bits [CANIDM1] */ +/* CAN Identifier Mask Register 1 */ +#define IDMSK28 7 +#define IDMSK27 6 +#define IDMSK26 5 +#define IDMSK25 4 +#define IDMSK24 3 +#define IDMSK23 2 +#define IDMSK22 1 +#define IDMSK21 0 +/* End Register Bits */ + +/* Register Bits [CANSTML] */ +/* CAN Timer Register of some sort, low*/ +#define TIMSTM7 7 +#define TIMSTM6 6 +#define TIMSTM5 5 +#define TIMSTM4 4 +#define TIMSTM3 3 +#define TIMSTM2 2 +#define TIMSTM1 1 +#define TIMSTM0 0 +/* End Register Bits */ + +/* Register Bits [CANSTMH] */ +/* CAN Timer Register of some sort, high */ +#define TIMSTM15 7 +#define TIMSTM14 6 +#define TIMSTM13 5 +#define TIMSTM12 4 +#define TIMSTM11 3 +#define TIMSTM10 2 +#define TIMSTM9 1 +#define TIMSTM8 0 +/* End Register Bits */ + +/* Register Bits [CANMSG] */ +/* CAN Message Register */ +#define MSG7 7 +#define MSG6 6 +#define MSG5 5 +#define MSG4 4 +#define MSG3 3 +#define MSG2 2 +#define MSG1 1 +#define MSG0 0 +/* End Register Bits */ + +/* Begin Verbatim */ + +/* Timer/Counter Control Register (generic) */ +#define FOC 7 +#define WGM0 6 +#define COM1 5 +#define COM0 4 +#define WGM1 3 +#define CS2 2 +#define CS1 1 +#define CS0 0 + +/* Timer/Counter Control Register A (generic) */ +#define COMA1 7 +#define COMA0 6 +#define COMB1 5 +#define COMB0 4 +#define COMC1 3 +#define COMC0 2 +#define WGMA1 1 +#define WGMA0 0 + +/* Timer/Counter Control and Status Register B (generic) */ +#define ICNC 7 +#define ICES 6 +#define WGMB3 4 +#define WGMB2 3 +#define CSB2 2 +#define CSB1 1 +#define CSB0 0 + +/* Timer/Counter Control Register C (generic) */ +#define FOCA 7 +#define FOCB 6 +#define FOCC 5 + +/* Port Data Register (generic) */ +#define PORT7 7 +#define PORT6 6 +#define PORT5 5 +#define PORT4 4 +#define PORT3 3 +#define PORT2 2 +#define PORT1 1 +#define PORT0 0 + +/* Port Data Direction Register (generic) */ +#define DD7 7 +#define DD6 6 +#define DD5 5 +#define DD4 4 +#define DD3 3 +#define DD2 2 +#define DD1 1 +#define DD0 0 + +/* Port Input Pins (generic) */ +#define PIN7 7 +#define PIN6 6 +#define PIN5 5 +#define PIN4 4 +#define PIN3 3 +#define PIN2 2 +#define PIN1 1 +#define PIN0 0 + +/* USART Status Register A (generic) */ +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 +#define UPE 2 +#define U2X 1 +#define MPCM 0 + +/* USART Control Register B (generic) */ +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define UCSZ 2 +#define UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ +#define RXB8 1 +#define TXB8 0 + +/* USART Register C (generic) */ +#define UMSEL 6 +#define UPM1 5 +#define UPM0 4 +#define USBS 3 +#define UCSZ1 2 +#define UCSZ0 1 +#define UCPOL 0 + +/* End Verbatim */ + +#endif /* _AVR_IOCANXX_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom103.h b/hardware/tools/avr/avr/include/avr/iom103.h new file mode 100644 index 0000000000000000000000000000000000000000..c31a16b35137be1b40f5dd2be80222eae23d2180 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom103.h @@ -0,0 +1,735 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom103.h 2227 2011-03-04 19:35:10Z arcanum $ */ + +/* avr/iom103.h - definitions for ATmega103 */ + +#ifndef _AVR_IOM103_H_ +#define _AVR_IOM103_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom103.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* Input Pins, Port F */ +#define PINF _SFR_IO8(0x00) + +/* Input Pins, Port E */ +#define PINE _SFR_IO8(0x01) + +/* Data Direction Register, Port E */ +#define DDRE _SFR_IO8(0x02) + +/* Data Register, Port E */ +#define PORTE _SFR_IO8(0x03) + +/* ADC Data Register */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) + +/* ADC Control and status register */ +#define ADCSR _SFR_IO8(0x06) + +/* ADC Multiplexer select */ +#define ADMUX _SFR_IO8(0x07) + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) + +/* UART Baud Rate Register */ +#define UBRR _SFR_IO8(0x09) + +/* UART Control Register */ +#define UCR _SFR_IO8(0x0A) + +/* UART Status Register */ +#define USR _SFR_IO8(0x0B) + +/* UART I/O Data Register */ +#define UDR _SFR_IO8(0x0C) + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x0D) + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x0E) + +/* SPI I/O Data Register */ +#define SPDR _SFR_IO8(0x0F) + +/* Input Pins, Port D */ +#define PIND _SFR_IO8(0x10) + +/* Data Direction Register, Port D */ +#define DDRD _SFR_IO8(0x11) + +/* Data Register, Port D */ +#define PORTD _SFR_IO8(0x12) + +/* Data Register, Port C */ +#define PORTC _SFR_IO8(0x15) + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* Input Pins, Port A */ +#define PINA _SFR_IO8(0x19) + +/* Data Direction Register, Port A */ +#define DDRA _SFR_IO8(0x1A) + +/* Data Register, Port A */ +#define PORTA _SFR_IO8(0x1B) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO16(0x1E) +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* Timer2 Output Compare Register */ +#define OCR2 _SFR_IO8(0x23) + +/* Timer/Counter 2 */ +#define TCNT2 _SFR_IO8(0x24) + +/* Timer/Counter 2 Control register */ +#define TCCR2 _SFR_IO8(0x25) + +/* T/C 1 Input Capture Register */ +#define ICR1 _SFR_IO16(0x26) +#define ICR1L _SFR_IO8(0x26) +#define ICR1H _SFR_IO8(0x27) + +/* Timer/Counter1 Output Compare Register B */ +#define OCR1B _SFR_IO16(0x28) +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Timer/Counter1 Output Compare Register A */ +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Timer/Counter 1 */ +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +/* Timer/Counter 1 Control and Status Register */ +#define TCCR1B _SFR_IO8(0x2E) + +/* Timer/Counter 1 Control Register */ +#define TCCR1A _SFR_IO8(0x2F) + +/* Timer/Counter 0 Asynchronous Control & Status Register */ +#define ASSR _SFR_IO8(0x30) + +/* Output Compare Register 0 */ +#define OCR0 _SFR_IO8(0x31) + +/* Timer/Counter 0 */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter 0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU Status Register */ +#define MCUSR _SFR_IO8(0x34) + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* Timer/Counter Interrupt Flag Register */ +#define TIFR _SFR_IO8(0x36) + +/* Timer/Counter Interrupt MaSK register */ +#define TIMSK _SFR_IO8(0x37) + +/* �xternal Interrupt Flag Register */ +#define EIFR _SFR_IO8(0x38) + +/* External Interrupt MaSK register */ +#define EIMSK _SFR_IO8(0x39) + +/* External Interrupt Control Register */ +#define EICR _SFR_IO8(0x3A) + +/* RAM Page Z select register */ +#define RAMPZ _SFR_IO8(0x3B) + +/* XDIV Divide control register */ +#define XDIV _SFR_IO8(0x3C) + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* External Interrupt 2 */ +#define INT2_vect_num 3 +#define INT2_vect _VECTOR(3) +#define SIG_INTERRUPT2 _VECTOR(3) + +/* External Interrupt 3 */ +#define INT3_vect_num 4 +#define INT3_vect _VECTOR(4) +#define SIG_INTERRUPT3 _VECTOR(4) + +/* External Interrupt 4 */ +#define INT4_vect_num 5 +#define INT4_vect _VECTOR(5) +#define SIG_INTERRUPT4 _VECTOR(5) + +/* External Interrupt 5 */ +#define INT5_vect_num 6 +#define INT5_vect _VECTOR(6) +#define SIG_INTERRUPT5 _VECTOR(6) + +/* External Interrupt 6 */ +#define INT6_vect_num 7 +#define INT6_vect _VECTOR(7) +#define SIG_INTERRUPT6 _VECTOR(7) + +/* External Interrupt 7 */ +#define INT7_vect_num 8 +#define INT7_vect _VECTOR(8) +#define SIG_INTERRUPT7 _VECTOR(8) + +/* Timer/Counter2 Compare Match */ +#define TIMER2_COMP_vect_num 9 +#define TIMER2_COMP_vect _VECTOR(9) +#define SIG_OUTPUT_COMPARE2 _VECTOR(9) + +/* Timer/Counter2 Overflow */ +#define TIMER2_OVF_vect_num 10 +#define TIMER2_OVF_vect _VECTOR(10) +#define SIG_OVERFLOW2 _VECTOR(10) + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect_num 11 +#define TIMER1_CAPT_vect _VECTOR(11) +#define SIG_INPUT_CAPTURE1 _VECTOR(11) + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect_num 12 +#define TIMER1_COMPA_vect _VECTOR(12) +#define SIG_OUTPUT_COMPARE1A _VECTOR(12) + +/* Timer/Counter1 Compare Match B */ +#define TIMER1_COMPB_vect_num 13 +#define TIMER1_COMPB_vect _VECTOR(13) +#define SIG_OUTPUT_COMPARE1B _VECTOR(13) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 14 +#define TIMER1_OVF_vect _VECTOR(14) +#define SIG_OVERFLOW1 _VECTOR(14) + +/* Timer/Counter0 Compare Match */ +#define TIMER0_COMP_vect_num 15 +#define TIMER0_COMP_vect _VECTOR(15) +#define SIG_OUTPUT_COMPARE0 _VECTOR(15) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 16 +#define TIMER0_OVF_vect _VECTOR(16) +#define SIG_OVERFLOW0 _VECTOR(16) + +/* SPI Serial Transfer Complete */ +#define SPI_STC_vect_num 17 +#define SPI_STC_vect _VECTOR(17) +#define SIG_SPI _VECTOR(17) + +/* UART, Rx Complete */ +#define UART_RX_vect_num 18 +#define UART_RX_vect _VECTOR(18) +#define SIG_UART_RECV _VECTOR(18) + +/* UART Data Register Empty */ +#define UART_UDRE_vect_num 19 +#define UART_UDRE_vect _VECTOR(19) +#define SIG_UART_DATA _VECTOR(19) + +/* UART, Tx Complete */ +#define UART_TX_vect_num 20 +#define UART_TX_vect _VECTOR(20) +#define SIG_UART_TRANS _VECTOR(20) + +/* ADC Conversion Complete */ +#define ADC_vect_num 21 +#define ADC_vect _VECTOR(21) +#define SIG_ADC _VECTOR(21) + +/* EEPROM Ready */ +#define EE_READY_vect_num 22 +#define EE_READY_vect _VECTOR(22) +#define SIG_EEPROM_READY _VECTOR(22) + +/* Analog Comparator */ +#define ANALOG_COMP_vect_num 23 +#define ANALOG_COMP_vect _VECTOR(23) +#define SIG_COMPARATOR _VECTOR(23) + +#define _VECTORS_SIZE 96 + +/* + The Register Bit names are represented by their bit number (0-7). +*/ + +/* XDIV Divide control register*/ +#define XDIVEN 7 +#define XDIV6 6 +#define XDIV5 5 +#define XDIV4 4 +#define XDIV3 3 +#define XDIV2 2 +#define XDIV1 1 +#define XDIV0 0 + +/* RAM Page Z select register */ +#define RAMPZ0 0 + +/* External Interrupt Control Register */ +#define ISC71 7 +#define ISC70 6 +#define ISC61 5 +#define ISC60 4 +#define ISC51 3 +#define ISC50 2 +#define ISC41 1 +#define ISC40 0 + +/* External Interrupt MaSK register */ +#define INT7 7 +#define INT6 6 +#define INT5 5 +#define INT4 4 +#define INT3 3 +#define INT2 2 +#define INT1 1 +#define INT0 0 + +/* �xternal Interrupt Flag Register */ +#define INTF7 7 +#define INTF6 6 +#define INTF5 5 +#define INTF4 4 + +/* Timer/Counter Interrupt MaSK register */ +#define OCIE2 7 +#define TOIE2 6 +#define TICIE1 5 +#define OCIE1A 4 +#define OCIE1B 3 +#define TOIE1 2 +#define OCIE0 1 +#define TOIE0 0 + +/* Timer/Counter Interrupt Flag Register */ +#define OCF2 7 +#define TOV2 6 +#define ICF1 5 +#define OCF1A 4 +#define OCF1B 3 +#define TOV1 2 +#define OCF0 1 +#define TOV0 0 + +/* MCU general Control Register */ +#define SRE 7 +#define SRW 6 +#define SE 5 +#define SM1 4 +#define SM0 3 + +/* MCU Status Register */ +#define EXTRF 1 +#define PORF 0 + +/* Timer/Counter 0 Control Register */ +#define PWM0 6 +#define COM01 5 +#define COM00 4 +#define CTC0 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* Timer/Counter 0 Asynchronous Control & Status Register */ +#define AS0 3 +#define TCN0UB 2 +#define OCR0UB 1 +#define TCR0UB 0 + +/* Timer/Counter 1 Control Register */ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define PWM11 1 +#define PWM10 0 + +/* Timer/Counter 1 Control and Status Register */ +#define ICNC1 7 +#define ICES1 6 +#define CTC1 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* Timer/Counter 2 Control register */ +#define PWM2 6 +#define COM21 5 +#define COM20 4 +#define CTC2 3 +#define CS22 2 +#define CS21 1 +#define CS20 0 + +/* Watchdog Timer Control Register */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* Data Register, Port A */ +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* Data Direction Register, Port A */ +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +/* Input Pins, Port A */ +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +/* Data Register, Port B */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Data Direction Register, Port B */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Input Pins, Port B */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* Data Register, Port C */ +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* Data Register, Port D */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* Data Direction Register, Port D */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* Input Pins, Port D */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* Data Register, Port E */ +#define PE7 7 +#define PE6 6 +#define PE5 5 +#define PE4 4 +#define PE3 3 +#define PE2 2 +#define PE1 1 +#define PE0 0 + +/* Data Direction Register, Port E */ +#define DDE7 7 +#define DDE6 6 +#define DDE5 5 +#define DDE4 4 +#define DDE3 3 +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +/* Input Pins, Port E */ +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +/* Input Pins, Port F */ +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +/* SPI Status Register */ +#define SPIF 7 +#define WCOL 6 + +/* SPI Control Register */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* UART Status Register */ +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 + +/* UART Control Register */ +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define CHR9 2 +#define RXB8 1 +#define TXB8 0 + +/* Analog Comparator Control and Status Register */ +#define ACD 7 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +/* ADC Control and status register */ +#define ADEN 7 +#define ADSC 6 +#define ADFR 5 +#define ADIF 4 +#define ADIE 3 +#define ADPS2 2 +#define ADPS1 1 +#define ADPS0 0 + +/* ADC Multiplexer select */ +#define MUX2 2 +#define MUX1 1 +#define MUX0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define RAMSTART 0x60 +#define RAMEND 0x0FFF /*Last On-Chip SRAM Location*/ +#define XRAMEND 0xFFFF +#define E2END 0x0FFF +#define E2PAGESIZE 0 +#define FLASHEND 0x1FFFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 1 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +#define FUSE_BODEN (unsigned char)~_BV(6) /* Brown out detector enable */ +#define FUSE_BODLEVEL (unsigned char)~_BV(7) /* Brown out detector trigger level */ +#define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x01 + +#define SLEEP_MODE_IDLE 0 +#define SLEEP_MODE_ADC _BV(SM0) +#define SLEEP_MODE_PWR_DOWN _BV(SM1) +#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_INTERRUPT1 +#pragma GCC poison SIG_INTERRUPT2 +#pragma GCC poison SIG_INTERRUPT3 +#pragma GCC poison SIG_INTERRUPT4 +#pragma GCC poison SIG_INTERRUPT5 +#pragma GCC poison SIG_INTERRUPT6 +#pragma GCC poison SIG_INTERRUPT7 +#pragma GCC poison SIG_OUTPUT_COMPARE2 +#pragma GCC poison SIG_OVERFLOW2 +#pragma GCC poison SIG_INPUT_CAPTURE1 +#pragma GCC poison SIG_OUTPUT_COMPARE1A +#pragma GCC poison SIG_OUTPUT_COMPARE1B +#pragma GCC poison SIG_OVERFLOW1 +#pragma GCC poison SIG_OUTPUT_COMPARE0 +#pragma GCC poison SIG_OVERFLOW0 +#pragma GCC poison SIG_SPI +#pragma GCC poison SIG_UART_RECV +#pragma GCC poison SIG_UART_DATA +#pragma GCC poison SIG_UART_TRANS +#pragma GCC poison SIG_ADC +#pragma GCC poison SIG_EEPROM_READY +#pragma GCC poison SIG_COMPARATOR + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + + +#endif /* _AVR_IOM103_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom128.h b/hardware/tools/avr/avr/include/avr/iom128.h new file mode 100644 index 0000000000000000000000000000000000000000..1b19839736f4f1a92b93d461e1c8fc9e0f5beeaa --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom128.h @@ -0,0 +1,1299 @@ +/* Copyright (c) 2002, Peter Jansen + Copyright (c) 2007, Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom128.h 2226 2011-03-04 17:47:16Z arcanum $ */ + +/* avr/iom128.h - defines for ATmega128 + + As of 2002-08-27: + - This should be up to date with data sheet 2467E-AVR-05/02 */ + +#ifndef _AVR_IOM128_H_ +#define _AVR_IOM128_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom128.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* Input Pins, Port F */ +#define PINF _SFR_IO8(0x00) + +/* Input Pins, Port E */ +#define PINE _SFR_IO8(0x01) + +/* Data Direction Register, Port E */ +#define DDRE _SFR_IO8(0x02) + +/* Data Register, Port E */ +#define PORTE _SFR_IO8(0x03) + +/* ADC Data Register */ +#define ADCW _SFR_IO16(0x04) +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) + +/* ADC Control and status register */ +#define ADCSR _SFR_IO8(0x06) +#define ADCSRA _SFR_IO8(0x06) /* new name in datasheet (2467E-AVR-05/02) */ + +/* ADC Multiplexer select */ +#define ADMUX _SFR_IO8(0x07) + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) + +/* USART0 Baud Rate Register Low */ +#define UBRR0L _SFR_IO8(0x09) + +/* USART0 Control and Status Register B */ +#define UCSR0B _SFR_IO8(0x0A) + +/* USART0 Control and Status Register A */ +#define UCSR0A _SFR_IO8(0x0B) + +/* USART0 I/O Data Register */ +#define UDR0 _SFR_IO8(0x0C) + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x0D) + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x0E) + +/* SPI I/O Data Register */ +#define SPDR _SFR_IO8(0x0F) + +/* Input Pins, Port D */ +#define PIND _SFR_IO8(0x10) + +/* Data Direction Register, Port D */ +#define DDRD _SFR_IO8(0x11) + +/* Data Register, Port D */ +#define PORTD _SFR_IO8(0x12) + +/* Input Pins, Port C */ +#define PINC _SFR_IO8(0x13) + +/* Data Direction Register, Port C */ +#define DDRC _SFR_IO8(0x14) + +/* Data Register, Port C */ +#define PORTC _SFR_IO8(0x15) + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* Input Pins, Port A */ +#define PINA _SFR_IO8(0x19) + +/* Data Direction Register, Port A */ +#define DDRA _SFR_IO8(0x1A) + +/* Data Register, Port A */ +#define PORTA _SFR_IO8(0x1B) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO16(0x1E) +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +/* Special Function I/O Register */ +#define SFIOR _SFR_IO8(0x20) + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* On-chip Debug Register */ +#define OCDR _SFR_IO8(0x22) + +/* Timer2 Output Compare Register */ +#define OCR2 _SFR_IO8(0x23) + +/* Timer/Counter 2 */ +#define TCNT2 _SFR_IO8(0x24) + +/* Timer/Counter 2 Control register */ +#define TCCR2 _SFR_IO8(0x25) + +/* T/C 1 Input Capture Register */ +#define ICR1 _SFR_IO16(0x26) +#define ICR1L _SFR_IO8(0x26) +#define ICR1H _SFR_IO8(0x27) + +/* Timer/Counter1 Output Compare Register B */ +#define OCR1B _SFR_IO16(0x28) +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Timer/Counter1 Output Compare Register A */ +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Timer/Counter 1 */ +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +/* Timer/Counter 1 Control and Status Register */ +#define TCCR1B _SFR_IO8(0x2E) + +/* Timer/Counter 1 Control Register */ +#define TCCR1A _SFR_IO8(0x2F) + +/* Timer/Counter 0 Asynchronous Control & Status Register */ +#define ASSR _SFR_IO8(0x30) + +/* Output Compare Register 0 */ +#define OCR0 _SFR_IO8(0x31) + +/* Timer/Counter 0 */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter 0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU Status Register */ +#define MCUSR _SFR_IO8(0x34) +#define MCUCSR _SFR_IO8(0x34) /* new name in datasheet (2467E-AVR-05/02) */ + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* Timer/Counter Interrupt Flag Register */ +#define TIFR _SFR_IO8(0x36) + +/* Timer/Counter Interrupt MaSK register */ +#define TIMSK _SFR_IO8(0x37) + +/* External Interrupt Flag Register */ +#define EIFR _SFR_IO8(0x38) + +/* External Interrupt MaSK register */ +#define EIMSK _SFR_IO8(0x39) + +/* External Interrupt Control Register B */ +#define EICRB _SFR_IO8(0x3A) + +/* RAM Page Z select register */ +#define RAMPZ _SFR_IO8(0x3B) + +/* XDIV Divide control register */ +#define XDIV _SFR_IO8(0x3C) + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Extended I/O registers */ + +/* Data Direction Register, Port F */ +#define DDRF _SFR_MEM8(0x61) + +/* Data Register, Port F */ +#define PORTF _SFR_MEM8(0x62) + +/* Input Pins, Port G */ +#define PING _SFR_MEM8(0x63) + +/* Data Direction Register, Port G */ +#define DDRG _SFR_MEM8(0x64) + +/* Data Register, Port G */ +#define PORTG _SFR_MEM8(0x65) + +/* Store Program Memory Control and Status Register */ +#define SPMCR _SFR_MEM8(0x68) +#define SPMCSR _SFR_MEM8(0x68) /* new name in datasheet (2467E-AVR-05/02) */ + +/* External Interrupt Control Register A */ +#define EICRA _SFR_MEM8(0x6A) + +/* External Memory Control Register B */ +#define XMCRB _SFR_MEM8(0x6C) + +/* External Memory Control Register A */ +#define XMCRA _SFR_MEM8(0x6D) + +/* Oscillator Calibration Register */ +#define OSCCAL _SFR_MEM8(0x6F) + +/* 2-wire Serial Interface Bit Rate Register */ +#define TWBR _SFR_MEM8(0x70) + +/* 2-wire Serial Interface Status Register */ +#define TWSR _SFR_MEM8(0x71) + +/* 2-wire Serial Interface Address Register */ +#define TWAR _SFR_MEM8(0x72) + +/* 2-wire Serial Interface Data Register */ +#define TWDR _SFR_MEM8(0x73) + +/* 2-wire Serial Interface Control Register */ +#define TWCR _SFR_MEM8(0x74) + +/* Time Counter 1 Output Compare Register C */ +#define OCR1C _SFR_MEM16(0x78) +#define OCR1CL _SFR_MEM8(0x78) +#define OCR1CH _SFR_MEM8(0x79) + +/* Timer/Counter 1 Control Register C */ +#define TCCR1C _SFR_MEM8(0x7A) + +/* Extended Timer Interrupt Flag Register */ +#define ETIFR _SFR_MEM8(0x7C) + +/* Extended Timer Interrupt Mask Register */ +#define ETIMSK _SFR_MEM8(0x7D) + +/* Timer/Counter 3 Input Capture Register */ +#define ICR3 _SFR_MEM16(0x80) +#define ICR3L _SFR_MEM8(0x80) +#define ICR3H _SFR_MEM8(0x81) + +/* Timer/Counter 3 Output Compare Register C */ +#define OCR3C _SFR_MEM16(0x82) +#define OCR3CL _SFR_MEM8(0x82) +#define OCR3CH _SFR_MEM8(0x83) + +/* Timer/Counter 3 Output Compare Register B */ +#define OCR3B _SFR_MEM16(0x84) +#define OCR3BL _SFR_MEM8(0x84) +#define OCR3BH _SFR_MEM8(0x85) + +/* Timer/Counter 3 Output Compare Register A */ +#define OCR3A _SFR_MEM16(0x86) +#define OCR3AL _SFR_MEM8(0x86) +#define OCR3AH _SFR_MEM8(0x87) + +/* Timer/Counter 3 Counter Register */ +#define TCNT3 _SFR_MEM16(0x88) +#define TCNT3L _SFR_MEM8(0x88) +#define TCNT3H _SFR_MEM8(0x89) + +/* Timer/Counter 3 Control Register B */ +#define TCCR3B _SFR_MEM8(0x8A) + +/* Timer/Counter 3 Control Register A */ +#define TCCR3A _SFR_MEM8(0x8B) + +/* Timer/Counter 3 Control Register C */ +#define TCCR3C _SFR_MEM8(0x8C) + +/* USART0 Baud Rate Register High */ +#define UBRR0H _SFR_MEM8(0x90) + +/* USART0 Control and Status Register C */ +#define UCSR0C _SFR_MEM8(0x95) + +/* USART1 Baud Rate Register High */ +#define UBRR1H _SFR_MEM8(0x98) + +/* USART1 Baud Rate Register Low*/ +#define UBRR1L _SFR_MEM8(0x99) + +/* USART1 Control and Status Register B */ +#define UCSR1B _SFR_MEM8(0x9A) + +/* USART1 Control and Status Register A */ +#define UCSR1A _SFR_MEM8(0x9B) + +/* USART1 I/O Data Register */ +#define UDR1 _SFR_MEM8(0x9C) + +/* USART1 Control and Status Register C */ +#define UCSR1C _SFR_MEM8(0x9D) + +/* Interrupt vectors */ + +/* External Interrupt Request 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt Request 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* External Interrupt Request 2 */ +#define INT2_vect_num 3 +#define INT2_vect _VECTOR(3) +#define SIG_INTERRUPT2 _VECTOR(3) + +/* External Interrupt Request 3 */ +#define INT3_vect_num 4 +#define INT3_vect _VECTOR(4) +#define SIG_INTERRUPT3 _VECTOR(4) + +/* External Interrupt Request 4 */ +#define INT4_vect_num 5 +#define INT4_vect _VECTOR(5) +#define SIG_INTERRUPT4 _VECTOR(5) + +/* External Interrupt Request 5 */ +#define INT5_vect_num 6 +#define INT5_vect _VECTOR(6) +#define SIG_INTERRUPT5 _VECTOR(6) + +/* External Interrupt Request 6 */ +#define INT6_vect_num 7 +#define INT6_vect _VECTOR(7) +#define SIG_INTERRUPT6 _VECTOR(7) + +/* External Interrupt Request 7 */ +#define INT7_vect_num 8 +#define INT7_vect _VECTOR(8) +#define SIG_INTERRUPT7 _VECTOR(8) + +/* Timer/Counter2 Compare Match */ +#define TIMER2_COMP_vect_num 9 +#define TIMER2_COMP_vect _VECTOR(9) +#define SIG_OUTPUT_COMPARE2 _VECTOR(9) + +/* Timer/Counter2 Overflow */ +#define TIMER2_OVF_vect_num 10 +#define TIMER2_OVF_vect _VECTOR(10) +#define SIG_OVERFLOW2 _VECTOR(10) + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect_num 11 +#define TIMER1_CAPT_vect _VECTOR(11) +#define SIG_INPUT_CAPTURE1 _VECTOR(11) + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect_num 12 +#define TIMER1_COMPA_vect _VECTOR(12) +#define SIG_OUTPUT_COMPARE1A _VECTOR(12) + +/* Timer/Counter Compare Match B */ +#define TIMER1_COMPB_vect_num 13 +#define TIMER1_COMPB_vect _VECTOR(13) +#define SIG_OUTPUT_COMPARE1B _VECTOR(13) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 14 +#define TIMER1_OVF_vect _VECTOR(14) +#define SIG_OVERFLOW1 _VECTOR(14) + +/* Timer/Counter0 Compare Match */ +#define TIMER0_COMP_vect_num 15 +#define TIMER0_COMP_vect _VECTOR(15) +#define SIG_OUTPUT_COMPARE0 _VECTOR(15) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 16 +#define TIMER0_OVF_vect _VECTOR(16) +#define SIG_OVERFLOW0 _VECTOR(16) + +/* SPI Serial Transfer Complete */ +#define SPI_STC_vect_num 17 +#define SPI_STC_vect _VECTOR(17) +#define SIG_SPI _VECTOR(17) + +/* USART0, Rx Complete */ +#define USART0_RX_vect_num 18 +#define USART0_RX_vect _VECTOR(18) +#define SIG_USART0_RECV _VECTOR(18) +#define SIG_UART0_RECV _VECTOR(18) + +/* USART0 Data Register Empty */ +#define USART0_UDRE_vect_num 19 +#define USART0_UDRE_vect _VECTOR(19) +#define SIG_USART0_DATA _VECTOR(19) +#define SIG_UART0_DATA _VECTOR(19) + +/* USART0, Tx Complete */ +#define USART0_TX_vect_num 20 +#define USART0_TX_vect _VECTOR(20) +#define SIG_USART0_TRANS _VECTOR(20) +#define SIG_UART0_TRANS _VECTOR(20) + +/* ADC Conversion Complete */ +#define ADC_vect_num 21 +#define ADC_vect _VECTOR(21) +#define SIG_ADC _VECTOR(21) + +/* EEPROM Ready */ +#define EE_READY_vect _VECTOR(22) +#define EE_READY_vect _VECTOR(22) +#define SIG_EEPROM_READY _VECTOR(22) + +/* Analog Comparator */ +#define ANALOG_COMP_vect_num 23 +#define ANALOG_COMP_vect _VECTOR(23) +#define SIG_COMPARATOR _VECTOR(23) + +/* Timer/Counter1 Compare Match C */ +#define TIMER1_COMPC_vect_num 24 +#define TIMER1_COMPC_vect _VECTOR(24) +#define SIG_OUTPUT_COMPARE1C _VECTOR(24) + +/* Timer/Counter3 Capture Event */ +#define TIMER3_CAPT_vect_num 25 +#define TIMER3_CAPT_vect _VECTOR(25) +#define SIG_INPUT_CAPTURE3 _VECTOR(25) + +/* Timer/Counter3 Compare Match A */ +#define TIMER3_COMPA_vect_num 26 +#define TIMER3_COMPA_vect _VECTOR(26) +#define SIG_OUTPUT_COMPARE3A _VECTOR(26) + +/* Timer/Counter3 Compare Match B */ +#define TIMER3_COMPB_vect_num 27 +#define TIMER3_COMPB_vect _VECTOR(27) +#define SIG_OUTPUT_COMPARE3B _VECTOR(27) + +/* Timer/Counter3 Compare Match C */ +#define TIMER3_COMPC_vect_num 28 +#define TIMER3_COMPC_vect _VECTOR(28) +#define SIG_OUTPUT_COMPARE3C _VECTOR(28) + +/* Timer/Counter3 Overflow */ +#define TIMER3_OVF_vect_num 29 +#define TIMER3_OVF_vect _VECTOR(29) +#define SIG_OVERFLOW3 _VECTOR(29) + +/* USART1, Rx Complete */ +#define USART1_RX_vect_num 30 +#define USART1_RX_vect _VECTOR(30) +#define SIG_USART1_RECV _VECTOR(30) +#define SIG_UART1_RECV _VECTOR(30) + +/* USART1, Data Register Empty */ +#define USART1_UDRE_vect_num 31 +#define USART1_UDRE_vect _VECTOR(31) +#define SIG_USART1_DATA _VECTOR(31) +#define SIG_UART1_DATA _VECTOR(31) + +/* USART1, Tx Complete */ +#define USART1_TX_vect_num 32 +#define USART1_TX_vect _VECTOR(32) +#define SIG_USART1_TRANS _VECTOR(32) +#define SIG_UART1_TRANS _VECTOR(32) + +/* 2-wire Serial Interface */ +#define TWI_vect_num 33 +#define TWI_vect _VECTOR(33) +#define SIG_2WIRE_SERIAL _VECTOR(33) + +/* Store Program Memory Read */ +#define SPM_READY_vect_num 34 +#define SPM_READY_vect _VECTOR(34) +#define SPM_READY_vect _VECTOR(34) +#define SIG_SPM_READY _VECTOR(34) + +#define _VECTORS_SIZE 140 + +/* + The Register Bit names are represented by their bit number (0-7). +*/ + +/* 2-wire Control Register - TWCR */ +#define TWINT 7 +#define TWEA 6 +#define TWSTA 5 +#define TWSTO 4 +#define TWWC 3 +#define TWEN 2 +#define TWIE 0 + +/* 2-wire Address Register - TWAR */ +#define TWA6 7 +#define TWA5 6 +#define TWA4 5 +#define TWA3 4 +#define TWA2 3 +#define TWA1 2 +#define TWA0 1 +#define TWGCE 0 + +/* 2-wire Status Register - TWSR */ +#define TWS7 7 +#define TWS6 6 +#define TWS5 5 +#define TWS4 4 +#define TWS3 3 +#define TWPS1 1 +#define TWPS0 0 + +/* External Memory Control Register A - XMCRA */ +#define SRL2 6 +#define SRL1 5 +#define SRL0 4 +#define SRW01 3 +#define SRW00 2 +#define SRW11 1 + +/* External Memory Control Register B - XMCRA */ +#define XMBK 7 +#define XMM2 2 +#define XMM1 1 +#define XMM0 0 + +/* XDIV Divide control register - XDIV */ +#define XDIVEN 7 +#define XDIV6 6 +#define XDIV5 5 +#define XDIV4 4 +#define XDIV3 3 +#define XDIV2 2 +#define XDIV1 1 +#define XDIV0 0 + +/* RAM Page Z select register - RAMPZ */ +#define RAMPZ0 0 + +/* External Interrupt Control Register A - EICRA */ +#define ISC31 7 +#define ISC30 6 +#define ISC21 5 +#define ISC20 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/* External Interrupt Control Register B - EICRB */ +#define ISC71 7 +#define ISC70 6 +#define ISC61 5 +#define ISC60 4 +#define ISC51 3 +#define ISC50 2 +#define ISC41 1 +#define ISC40 0 + +/* Store Program Memory Control Register - SPMCSR, SPMCR */ +#define SPMIE 7 +#define RWWSB 6 +#define RWWSRE 4 +#define BLBSET 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 + +/* External Interrupt MaSK register - EIMSK */ +#define INT7 7 +#define INT6 6 +#define INT5 5 +#define INT4 4 +#define INT3 3 +#define INT2 2 +#define INT1 1 +#define INT0 0 + +/* External Interrupt Flag Register - EIFR */ +#define INTF7 7 +#define INTF6 6 +#define INTF5 5 +#define INTF4 4 +#define INTF3 3 +#define INTF2 2 +#define INTF1 1 +#define INTF0 0 + +/* Timer/Counter Interrupt MaSK register - TIMSK */ +#define OCIE2 7 +#define TOIE2 6 +#define TICIE1 5 +#define OCIE1A 4 +#define OCIE1B 3 +#define TOIE1 2 +#define OCIE0 1 +#define TOIE0 0 + +/* Timer/Counter Interrupt Flag Register - TIFR */ +#define OCF2 7 +#define TOV2 6 +#define ICF1 5 +#define OCF1A 4 +#define OCF1B 3 +#define TOV1 2 +#define OCF0 1 +#define TOV0 0 + +/* Extended Timer Interrupt MaSK register - ETIMSK */ +#define TICIE3 5 +#define OCIE3A 4 +#define OCIE3B 3 +#define TOIE3 2 +#define OCIE3C 1 +#define OCIE1C 0 + +/* Extended Timer Interrupt Flag Register - ETIFR */ +#define ICF3 5 +#define OCF3A 4 +#define OCF3B 3 +#define TOV3 2 +#define OCF3C 1 +#define OCF1C 0 + +/* MCU general Control Register - MCUCR */ +#define SRE 7 +#define SRW 6 +#define SRW10 6 /* new name in datasheet (2467E-AVR-05/02) */ +#define SE 5 +#define SM1 4 +#define SM0 3 +#define SM2 2 +#define IVSEL 1 +#define IVCE 0 + +/* MCU Status Register - MCUSR, MCUCSR */ +#define JTD 7 +#define JTRF 4 +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +/* Timer/Counter Control Register (generic) */ +#define FOC 7 +#define WGM0 6 +#define COM1 5 +#define COM0 4 +#define WGM1 3 +#define CS2 2 +#define CS1 1 +#define CS0 0 + +/* Timer/Counter 0 Control Register - TCCR0 */ +#define FOC0 7 +#define WGM00 6 +#define COM01 5 +#define COM00 4 +#define WGM01 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* Timer/Counter 2 Control Register - TCCR2 */ +#define FOC2 7 +#define WGM20 6 +#define COM21 5 +#define COM20 4 +#define WGM21 3 +#define CS22 2 +#define CS21 1 +#define CS20 0 + +/* Timer/Counter 0 Asynchronous Control & Status Register - ASSR */ +#define AS0 3 +#define TCN0UB 2 +#define OCR0UB 1 +#define TCR0UB 0 + +/* Timer/Counter Control Register A (generic) */ +#define COMA1 7 +#define COMA0 6 +#define COMB1 5 +#define COMB0 4 +#define COMC1 3 +#define COMC0 2 +#define WGMA1 1 +#define WGMA0 0 + +/* Timer/Counter 1 Control and Status Register A - TCCR1A */ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define COM1C1 3 +#define COM1C0 2 +#define WGM11 1 +#define WGM10 0 + +/* Timer/Counter 3 Control and Status Register A - TCCR3A */ +#define COM3A1 7 +#define COM3A0 6 +#define COM3B1 5 +#define COM3B0 4 +#define COM3C1 3 +#define COM3C0 2 +#define WGM31 1 +#define WGM30 0 + +/* Timer/Counter Control and Status Register B (generic) */ +#define ICNC 7 +#define ICES 6 +#define WGMB3 4 +#define WGMB2 3 +#define CSB2 2 +#define CSB1 1 +#define CSB0 0 + +/* Timer/Counter 1 Control and Status Register B - TCCR1B */ +#define ICNC1 7 +#define ICES1 6 +#define WGM13 4 +#define WGM12 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* Timer/Counter 3 Control and Status Register B - TCCR3B */ +#define ICNC3 7 +#define ICES3 6 +#define WGM33 4 +#define WGM32 3 +#define CS32 2 +#define CS31 1 +#define CS30 0 + +/* Timer/Counter Control Register C (generic) */ +#define FOCA 7 +#define FOCB 6 +#define FOCC 5 + +/* Timer/Counter 3 Control Register C - TCCR3C */ +#define FOC3A 7 +#define FOC3B 6 +#define FOC3C 5 + +/* Timer/Counter 1 Control Register C - TCCR1C */ +#define FOC1A 7 +#define FOC1B 6 +#define FOC1C 5 + +/* On-chip Debug Register - OCDR */ +#define IDRD 7 +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Watchdog Timer Control Register - WDTCR */ +#define WDCE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* + The ADHSM bit has been removed from all documentation, + as being not needed at all since the comparator has proven + to be fast enough even without feeding it more power. +*/ + +/* Special Function I/O Register - SFIOR */ +#define TSM 7 +#define ACME 3 +#define PUD 2 +#define PSR0 1 +#define PSR321 0 + +/* SPI Status Register - SPSR */ +#define SPIF 7 +#define WCOL 6 +#define SPI2X 0 + +/* SPI Control Register - SPCR */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* USART Register C (generic) */ +#define UMSEL 6 +#define UPM1 5 +#define UPM0 4 +#define USBS 3 +#define UCSZ1 2 +#define UCSZ0 1 +#define UCPOL 0 + +/* USART1 Register C - UCSR1C */ +#define UMSEL1 6 +#define UPM11 5 +#define UPM10 4 +#define USBS1 3 +#define UCSZ11 2 +#define UCSZ10 1 +#define UCPOL1 0 + +/* USART0 Register C - UCSR0C */ +#define UMSEL0 6 +#define UPM01 5 +#define UPM00 4 +#define USBS0 3 +#define UCSZ01 2 +#define UCSZ00 1 +#define UCPOL0 0 + +/* USART Status Register A (generic) */ +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 +#define UPE 2 +#define U2X 1 +#define MPCM 0 + +/* USART1 Status Register A - UCSR1A */ +#define RXC1 7 +#define TXC1 6 +#define UDRE1 5 +#define FE1 4 +#define DOR1 3 +#define UPE1 2 +#define U2X1 1 +#define MPCM1 0 + +/* USART0 Status Register A - UCSR0A */ +#define RXC0 7 +#define TXC0 6 +#define UDRE0 5 +#define FE0 4 +#define DOR0 3 +#define UPE0 2 +#define U2X0 1 +#define MPCM0 0 + +/* USART Control Register B (generic) */ +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define UCSZ 2 +#define UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ +#define RXB8 1 +#define TXB8 0 + +/* USART1 Control Register B - UCSR1B */ +#define RXCIE1 7 +#define TXCIE1 6 +#define UDRIE1 5 +#define RXEN1 4 +#define TXEN1 3 +#define UCSZ12 2 +#define RXB81 1 +#define TXB81 0 + +/* USART0 Control Register B - UCSR0B */ +#define RXCIE0 7 +#define TXCIE0 6 +#define UDRIE0 5 +#define RXEN0 4 +#define TXEN0 3 +#define UCSZ02 2 +#define RXB80 1 +#define TXB80 0 + +/* Analog Comparator Control and Status Register - ACSR */ +#define ACD 7 +#define ACBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +/* ADC Control and status register - ADCSRA */ +#define ADEN 7 +#define ADSC 6 +#define ADFR 5 +#define ADIF 4 +#define ADIE 3 +#define ADPS2 2 +#define ADPS1 1 +#define ADPS0 0 + +/* ADC Multiplexer select - ADMUX */ +#define REFS1 7 +#define REFS0 6 +#define ADLAR 5 +#define MUX4 4 +#define MUX3 3 +#define MUX2 2 +#define MUX1 1 +#define MUX0 0 + +/* Port A Data Register - PORTA */ +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* Port A Data Direction Register - DDRA */ +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +/* Port A Input Pins - PINA */ +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +/* Port B Data Register - PORTB */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Port B Data Direction Register - DDRB */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Port B Input Pins - PINB */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* Port C Data Register - PORTC */ +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* Port C Data Direction Register - DDRC */ +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +/* Port C Input Pins - PINC */ +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +/* Port D Data Register - PORTD */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* Port D Data Direction Register - DDRD */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* Port D Input Pins - PIND */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* Port E Data Register - PORTE */ +#define PE7 7 +#define PE6 6 +#define PE5 5 +#define PE4 4 +#define PE3 3 +#define PE2 2 +#define PE1 1 +#define PE0 0 + +/* Port E Data Direction Register - DDRE */ +#define DDE7 7 +#define DDE6 6 +#define DDE5 5 +#define DDE4 4 +#define DDE3 3 +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +/* Port E Input Pins - PINE */ +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +/* Port F Data Register - PORTF */ +#define PF7 7 +#define PF6 6 +#define PF5 5 +#define PF4 4 +#define PF3 3 +#define PF2 2 +#define PF1 1 +#define PF0 0 + +/* Port F Data Direction Register - DDRF */ +#define DDF7 7 +#define DDF6 6 +#define DDF5 5 +#define DDF4 4 +#define DDF3 3 +#define DDF2 2 +#define DDF1 1 +#define DDF0 0 + +/* Port F Input Pins - PINF */ +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +/* Port G Data Register - PORTG */ +#define PG4 4 +#define PG3 3 +#define PG2 2 +#define PG1 1 +#define PG0 0 + +/* Port G Data Direction Register - DDRG */ +#define DDG4 4 +#define DDG3 3 +#define DDG2 2 +#define DDG1 1 +#define DDG0 0 + +/* Port G Input Pins - PING */ +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define SPM_PAGESIZE 256 +#define RAMSTART 0x100 +#define RAMEND 0x10FF /* Last On-Chip SRAM Location */ +#define XRAMEND 0xFFFF +#define E2END 0x0FFF +#define E2PAGESIZE 8 +#define FLASHEND 0x1FFFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_BODEN (unsigned char)~_BV(6) +#define FUSE_BODLEVEL (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_CKOPT (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + +/* Extended Fuse Byte */ +#define FUSE_WDTON (unsigned char)~_BV(0) +#define FUSE_M103C (unsigned char)~_BV(1) +#define EFUSE_DEFAULT (FUSE_M103C) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x02 + + + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison MCUSR +#pragma GCC poison SPMCR + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_INTERRUPT1 +#pragma GCC poison SIG_INTERRUPT2 +#pragma GCC poison SIG_INTERRUPT3 +#pragma GCC poison SIG_INTERRUPT4 +#pragma GCC poison SIG_INTERRUPT5 +#pragma GCC poison SIG_INTERRUPT6 +#pragma GCC poison SIG_INTERRUPT7 +#pragma GCC poison SIG_OUTPUT_COMPARE2 +#pragma GCC poison SIG_OVERFLOW2 +#pragma GCC poison SIG_INPUT_CAPTURE1 +#pragma GCC poison SIG_OUTPUT_COMPARE1A +#pragma GCC poison SIG_OUTPUT_COMPARE1B +#pragma GCC poison SIG_OVERFLOW1 +#pragma GCC poison SIG_OUTPUT_COMPARE0 +#pragma GCC poison SIG_OVERFLOW0 +#pragma GCC poison SIG_SPI +#pragma GCC poison SIG_USART0_RECV +#pragma GCC poison SIG_UART0_RECV +#pragma GCC poison SIG_USART0_DATA +#pragma GCC poison SIG_UART0_DATA +#pragma GCC poison SIG_USART0_TRANS +#pragma GCC poison SIG_UART0_TRANS +#pragma GCC poison SIG_ADC +#pragma GCC poison SIG_EEPROM_READY +#pragma GCC poison SIG_COMPARATOR +#pragma GCC poison SIG_OUTPUT_COMPARE1C +#pragma GCC poison SIG_INPUT_CAPTURE3 +#pragma GCC poison SIG_OUTPUT_COMPARE3A +#pragma GCC poison SIG_OUTPUT_COMPARE3B +#pragma GCC poison SIG_OUTPUT_COMPARE3C +#pragma GCC poison SIG_OVERFLOW3 +#pragma GCC poison SIG_USART1_RECV +#pragma GCC poison SIG_UART1_RECV +#pragma GCC poison SIG_USART1_DATA +#pragma GCC poison SIG_UART1_DATA +#pragma GCC poison SIG_USART1_TRANS +#pragma GCC poison SIG_UART1_TRANS +#pragma GCC poison SIG_2WIRE_SERIAL +#pragma GCC poison SIG_SPM_READY + + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + +#define SLEEP_MODE_IDLE (0x00<<2) +#define SLEEP_MODE_ADC (0x02<<2) +#define SLEEP_MODE_PWR_DOWN (0x04<<2) +#define SLEEP_MODE_PWR_SAVE (0x06<<2) +#define SLEEP_MODE_STANDBY (0x05<<2) +#define SLEEP_MODE_EXT_STANDBY (0x07<<2) + +#endif /* _AVR_IOM128_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom1280.h b/hardware/tools/avr/avr/include/avr/iom1280.h new file mode 100644 index 0000000000000000000000000000000000000000..54f477f4c6f91329eedfbad788b23f288160e92d --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom1280.h @@ -0,0 +1,101 @@ +/* Copyright (c) 2005 Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom1280.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ + +/* avr/iom1280.h - definitions for ATmega1280 */ + +#ifndef _AVR_IOM1280_H_ +#define _AVR_IOM1280_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 256 +#define RAMSTART 0x200 +#define RAMEND 0x21FF +#define XRAMEND 0xFFFF +#define E2END 0xFFF +#define E2PAGESIZE 8 +#define FLASHEND 0x1FFFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + +/* Extended Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x03 + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +#endif /* _AVR_IOM1280_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom1281.h b/hardware/tools/avr/avr/include/avr/iom1281.h new file mode 100644 index 0000000000000000000000000000000000000000..07df33eea4c0fa618504ae954c65875d1a5c2c7f --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom1281.h @@ -0,0 +1,101 @@ +/* Copyright (c) 2005 Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom1281.h 2115 2010-04-05 23:19:53Z arcanum $ */ + +/* avr/iom1281.h - definitions for ATmega1281 */ + +#ifndef _AVR_IOM1281_H_ +#define _AVR_IOM1281_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 256 +#define RAMSTART (0x200) +#define RAMEND 0x21FF +#define XRAMEND 0xFFFF +#define E2END 0xFFF +#define E2PAGESIZE 8 +#define FLASHEND 0x1FFFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + +/* Extended Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x04 + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +#endif /* _AVR_IOM1281_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom1284.h b/hardware/tools/avr/avr/include/avr/iom1284.h new file mode 100644 index 0000000000000000000000000000000000000000..b2015c040906066b6cfad77ad7ffc80c8c830a8a --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom1284.h @@ -0,0 +1,1099 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_ATMEGA1284_H_INCLUDED +#define _AVR_ATMEGA1284_H_INCLUDED + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom1284.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define ICF3 5 + +/* Reserved [0x19..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3A] */ + +#define RAMPZ _SFR_IO8(0x3B) + +/* Reserved [0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR0 _SFR_MEM8(0x64) +#define PRADC 0 +#define PRSPI 2 +#define PRTIM1 3 +#define PRUSART0 1 +#define PRUSART1 4 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom1284p.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_IOM1284P_H_ +#define _AVR_IOM1284P_H_ 1 + + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 +#define PINA4 4 +#define PINA5 5 +#define PINA6 6 +#define PINA7 7 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 +#define PORTA4 4 +#define PORTA5 5 +#define PORTA6 6 +#define PORTA7 7 + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define ICF3 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 +#define EEAR10 2 +#define EEAR11 3 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 +#define JTD 7 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define RAMPZ _SFR_IO8(0x3B) +#define RAMPZ0 0 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR0 _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRUSART1 4 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom1284rfr2.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_IO8(0x12) +#define PING7 7 +#define PING6 6 +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDRG7 7 +// Inserted "DDG7" from "DDRG7" due to compatibility +#define DDG7 7 +#define DDRG6 6 +// Inserted "DDG6" from "DDRG6" due to compatibility +#define DDG6 6 +#define DDRG5 5 +// Inserted "DDG5" from "DDRG5" due to compatibility +#define DDG5 5 +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PORTG7 7 +#define PORTG6 6 +#define PORTG5 5 +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define Res0 3 +#define Res1 4 +#define Res2 5 +#define Res3 6 +#define Res4 7 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define OCF1C 3 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define OCF3C 3 +#define ICF3 5 + +#define TIFR4 _SFR_IO8(0x19) +#define TOV4 0 +#define OCF4A 1 +#define OCF4B 2 +#define OCF4C 3 +#define ICF4 5 + +#define TIFR5 _SFR_IO8(0x1A) +#define TOV5 0 +#define OCF5A 1 +#define OCF5B 2 +#define OCF5C 3 +#define ICF5 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3A] */ + +#define RAMPZ _SFR_IO8(0x3B) +#define RAMPZ0 0 +#define Res5 6 +#define Res6 7 + +/* Reserved [0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62] */ + +#define PRR2 _SFR_MEM8(0x63) +#define PRRAM0 0 +#define PRRAM1 1 +#define PRRAM2 2 +#define PRRAM3 3 + +#define __AVR_HAVE_PRR2 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom128a.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINF _SFR_IO8(0x00) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define PINE _SFR_IO8(0x01) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x02) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x03) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +/* Combine ADCL and ADCH */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) + +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) + +#define ADCSRA _SFR_IO8(0x06) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADFR 5 +#define ADSC 6 +#define ADEN 7 + +#define ADMUX _SFR_IO8(0x07) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define MUX4 4 +#define ADLAR 5 +#define REFS0 6 +#define REFS1 7 + +#define ACSR _SFR_IO8(0x08) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define UBRR0L _SFR_IO8(0x09) + +#define UCSR0B _SFR_IO8(0x0A) +#define TXB80 0 +#define RXB80 1 +#define UCSZ02 2 +#define TXEN0 3 +#define RXEN0 4 +#define UDRIE0 5 +#define TXCIE0 6 +#define RXCIE0 7 + +#define UCSR0A _SFR_IO8(0x0B) +#define MPCM0 0 +#define U2X0 1 +#define UPE0 2 +#define DOR0 3 +#define FE0 4 +#define UDRE0 5 +#define TXC0 6 +#define RXC0 7 + +#define UDR0 _SFR_IO8(0x0C) + +#define SPCR _SFR_IO8(0x0D) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x0E) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x0F) + +#define PIND _SFR_IO8(0x10) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x11) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x12) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINC _SFR_IO8(0x13) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x14) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x15) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PINB _SFR_IO8(0x16) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x17) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x18) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINA _SFR_IO8(0x19) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x1A) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x1B) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0x1D) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x1E) + +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +#define SFIOR _SFR_IO8(0x20) +#define ACME 3 +#define PSR321 0 +#define PSR0 1 +#define PUD 2 +#define TSM 7 + +#define WDTCR _SFR_IO8(0x21) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define OCDR _SFR_IO8(0x22) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +#define OCR2 _SFR_IO8(0x23) + +#define TCNT2 _SFR_IO8(0x24) + +#define TCCR2 _SFR_IO8(0x25) +#define CS20 0 +#define CS21 1 +#define CS22 2 +#define WGM21 3 +#define COM20 4 +#define COM21 5 +#define WGM20 6 +#define FOC2 7 + +/* Combine ICR1L and ICR1H */ +#define ICR1 _SFR_IO16(0x26) + +#define ICR1L _SFR_IO8(0x26) +#define ICR1H _SFR_IO8(0x27) + +/* Combine OCR1BL and OCR1BH */ +#define OCR1B _SFR_IO16(0x28) + +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Combine OCR1AL and OCR1AH */ +#define OCR1A _SFR_IO16(0x2A) + +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Combine TCNT1L and TCNT1H */ +#define TCNT1 _SFR_IO16(0x2C) + +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +#define TCCR1B _SFR_IO8(0x2E) +#define CS10 0 +#define CS11 1 +#define CS12 2 +#define WGM12 3 +#define WGM13 4 +#define ICES1 6 +#define ICNC1 7 + +#define TCCR1A _SFR_IO8(0x2F) +#define WGM10 0 +#define WGM11 1 +#define COM1C0 2 +#define COM1C1 3 +#define COM1B0 4 +#define COM1B1 5 +#define COM1A0 6 +#define COM1A1 7 + +#define ASSR _SFR_IO8(0x30) +#define TCR0UB 0 +#define OCR0UB 1 +#define TCN0UB 2 +#define AS0 3 + +#define OCR0 _SFR_IO8(0x31) + +#define TCNT0 _SFR_IO8(0x32) + +#define TCCR0 _SFR_IO8(0x33) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM00 4 +#define COM01 5 +#define WGM00 6 +#define FOC0 7 + +#define MCUCSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 +#define JTD 7 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define SM2 2 +#define SM0 3 +#define SM1 4 +#define SE 5 +#define SRW10 6 +#define SRE 7 + +#define TIFR _SFR_IO8(0x36) +#define TOV0 0 +#define OCF0 1 +#define TOV1 2 +#define OCF1B 3 +#define OCF1A 4 +#define ICF1 5 +#define TOV2 6 +#define OCF2 7 + +#define TIMSK _SFR_IO8(0x37) +#define TOIE0 0 +#define OCIE0 1 +#define TOIE1 2 +#define OCIE1B 3 +#define OCIE1A 4 +#define TICIE1 5 +#define TOIE2 6 +#define OCIE2 7 + +#define EIFR _SFR_IO8(0x38) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x39) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define EICRB _SFR_IO8(0x3A) +#define ISC40 0 +#define ISC41 1 +#define ISC50 2 +#define ISC51 3 +#define ISC60 4 +#define ISC61 5 +#define ISC70 6 +#define ISC71 7 + +#define RAMPZ _SFR_IO8(0x3B) +#define RAMPZ0 0 + +#define XDIV _SFR_IO8(0x3C) + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +/* Reserved [0x40..0x60] */ + +#define DDRF _SFR_MEM8(0x61) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_MEM8(0x62) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_MEM8(0x63) +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_MEM8(0x64) +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_MEM8(0x65) +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +/* Reserved [0x66..0x67] */ + +#define SPMCSR _SFR_MEM8(0x68) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x69] */ + +#define EICRA _SFR_MEM8(0x6A) +#define ISC00 0 +#define ISC01 1 +#define ISC10 2 +#define ISC11 3 +#define ISC20 4 +#define ISC21 5 +#define ISC30 6 +#define ISC31 7 + +/* Reserved [0x6B] */ + +#define XMCRB _SFR_MEM8(0x6C) +#define XMM0 0 +#define XMM1 1 +#define XMM2 2 +#define XMBK 7 + +#define XMCRA _SFR_MEM8(0x6D) +#define SRW11 1 +#define SRW00 2 +#define SRW01 3 +#define SRL0 4 +#define SRL1 5 +#define SRL2 6 + +/* Reserved [0x6E] */ + +#define OSCCAL _SFR_MEM8(0x6F) +#define OSCCAL0 0 +#define OSCCAL1 1 +#define OSCCAL2 2 +#define OSCCAL3 3 +#define OSCCAL4 4 +#define OSCCAL5 5 +#define OSCCAL6 6 +#define OSCCAL7 7 + +#define TWBR _SFR_MEM8(0x70) + +#define TWSR _SFR_MEM8(0x71) +#define TWPS0 0 +#define TWPS1 1 +#define TWS3 3 +#define TWS4 4 +#define TWS5 5 +#define TWS6 6 +#define TWS7 7 + +#define TWAR _SFR_MEM8(0x72) +#define TWGCE 0 +#define TWA0 1 +#define TWA1 2 +#define TWA2 3 +#define TWA3 4 +#define TWA4 5 +#define TWA5 6 +#define TWA6 7 + +#define TWDR _SFR_MEM8(0x73) + +#define TWCR _SFR_MEM8(0x74) +#define TWIE 0 +#define TWEN 2 +#define TWWC 3 +#define TWSTO 4 +#define TWSTA 5 +#define TWEA 6 +#define TWINT 7 + +/* Reserved [0x75..0x77] */ + +/* Combine OCR1CL and OCR1CH */ +#define OCR1C _SFR_MEM16(0x78) + +#define OCR1CL _SFR_MEM8(0x78) +#define OCR1CH _SFR_MEM8(0x79) + +#define TCCR1C _SFR_MEM8(0x7A) +#define FOC1C 5 +#define FOC1B 6 +#define FOC1A 7 + +/* Reserved [0x7B] */ + +#define ETIFR _SFR_MEM8(0x7C) +#define OCF1C 0 +#define OCF3C 1 +#define TOV3 2 +#define OCF3B 3 +#define OCF3A 4 +#define ICF3 5 + +#define ETIMSK _SFR_MEM8(0x7D) +#define OCIE1C 0 +#define OCIE3C 1 +#define TOIE3 2 +#define OCIE3B 3 +#define OCIE3A 4 +#define TICIE3 5 + +/* Reserved [0x7E..0x7F] */ + +/* Combine ICR3L and ICR3H */ +#define ICR3 _SFR_MEM16(0x80) + +#define ICR3L _SFR_MEM8(0x80) +#define ICR3H _SFR_MEM8(0x81) + +/* Combine OCR3CL and OCR3CH */ +#define OCR3C _SFR_MEM16(0x82) + +#define OCR3CL _SFR_MEM8(0x82) +#define OCR3CH _SFR_MEM8(0x83) + +/* Combine OCR3BL and OCR3BH */ +#define OCR3B _SFR_MEM16(0x84) + +#define OCR3BL _SFR_MEM8(0x84) +#define OCR3BH _SFR_MEM8(0x85) + +/* Combine OCR3AL and OCR3AH */ +#define OCR3A _SFR_MEM16(0x86) + +#define OCR3AL _SFR_MEM8(0x86) +#define OCR3AH _SFR_MEM8(0x87) + +/* Combine TCNT3L and TCNT3H */ +#define TCNT3 _SFR_MEM16(0x88) + +#define TCNT3L _SFR_MEM8(0x88) +#define TCNT3H _SFR_MEM8(0x89) + +#define TCCR3B _SFR_MEM8(0x8A) +#define CS30 0 +#define CS31 1 +#define CS32 2 +#define WGM32 3 +#define WGM33 4 +#define ICES3 6 +#define ICNC3 7 + +#define TCCR3A _SFR_MEM8(0x8B) +#define WGM30 0 +#define WGM31 1 +#define COM3C0 2 +#define COM3C1 3 +#define COM3B0 4 +#define COM3B1 5 +#define COM3A0 6 +#define COM3A1 7 + +#define TCCR3C _SFR_MEM8(0x8C) +#define FOC3C 5 +#define FOC3B 6 +#define FOC3A 7 + +/* Reserved [0x8D..0x8F] */ + +#define UBRR0H _SFR_MEM8(0x90) + +/* Reserved [0x91..0x94] */ + +#define UCSR0C _SFR_MEM8(0x95) +#define UCPOL0 0 +#define UCSZ00 1 +#define UCSZ01 2 +#define USBS0 3 +#define UPM00 4 +#define UPM01 5 +#define UMSEL0 6 + +/* Reserved [0x96..0x97] */ + +#define UBRR1H _SFR_MEM8(0x98) + +#define UBRR1L _SFR_MEM8(0x99) + +#define UCSR1B _SFR_MEM8(0x9A) +#define TXB81 0 +#define RXB81 1 +#define UCSZ12 2 +#define TXEN1 3 +#define RXEN1 4 +#define UDRIE1 5 +#define TXCIE1 6 +#define RXCIE1 7 + +#define UCSR1A _SFR_MEM8(0x9B) +#define MPCM1 0 +#define U2X1 1 +#define UPE1 2 +#define DOR1 3 +#define FE1 4 +#define UDRE1 5 +#define TXC1 6 +#define RXC1 7 + +#define UDR1 _SFR_MEM8(0x9C) + +#define UCSR1C _SFR_MEM8(0x9D) +#define UCPOL1 0 +#define UCSZ10 1 +#define UCSZ11 2 +#define USBS1 3 +#define UPM10 4 +#define UPM11 5 +#define UMSEL1 6 + + + +/* Values and associated defines */ + + +#define SLEEP_MODE_IDLE (0x00<<2) +#define SLEEP_MODE_ADC (0x02<<2) +#define SLEEP_MODE_PWR_DOWN (0x04<<2) +#define SLEEP_MODE_PWR_SAVE (0x06<<2) +#define SLEEP_MODE_STANDBY (0x05<<2) +#define SLEEP_MODE_EXT_STANDBY (0x07<<2) + +/* Interrupt vectors */ +/* Vector 0 is the reset vector */ +/* External Interrupt Request 0 */ +#define INT0_vect _VECTOR(1) +#define INT0_vect_num 1 + +/* External Interrupt Request 1 */ +#define INT1_vect _VECTOR(2) +#define INT1_vect_num 2 + +/* External Interrupt Request 2 */ +#define INT2_vect _VECTOR(3) +#define INT2_vect_num 3 + +/* External Interrupt Request 3 */ +#define INT3_vect _VECTOR(4) +#define INT3_vect_num 4 + +/* External Interrupt Request 4 */ +#define INT4_vect _VECTOR(5) +#define INT4_vect_num 5 + +/* External Interrupt Request 5 */ +#define INT5_vect _VECTOR(6) +#define INT5_vect_num 6 + +/* External Interrupt Request 6 */ +#define INT6_vect _VECTOR(7) +#define INT6_vect_num 7 + +/* External Interrupt Request 7 */ +#define INT7_vect _VECTOR(8) +#define INT7_vect_num 8 + +/* Timer/Counter2 Compare Match */ +#define TIMER2_COMP_vect _VECTOR(9) +#define TIMER2_COMP_vect_num 9 + +/* Timer/Counter2 Overflow */ +#define TIMER2_OVF_vect _VECTOR(10) +#define TIMER2_OVF_vect_num 10 + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect _VECTOR(11) +#define TIMER1_CAPT_vect_num 11 + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect _VECTOR(12) +#define TIMER1_COMPA_vect_num 12 + +/* Timer/Counter Compare Match B */ +#define TIMER1_COMPB_vect _VECTOR(13) +#define TIMER1_COMPB_vect_num 13 + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect _VECTOR(14) +#define TIMER1_OVF_vect_num 14 + +/* Timer/Counter0 Compare Match */ +#define TIMER0_COMP_vect _VECTOR(15) +#define TIMER0_COMP_vect_num 15 + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect _VECTOR(16) +#define TIMER0_OVF_vect_num 16 + +/* SPI Serial Transfer Complete */ +#define SPI_STC_vect _VECTOR(17) +#define SPI_STC_vect_num 17 + +/* USART0, Rx Complete */ +#define USART0_RX_vect _VECTOR(18) +#define USART0_RX_vect_num 18 + +/* USART0 Data Register Empty */ +#define USART0_UDRE_vect _VECTOR(19) +#define USART0_UDRE_vect_num 19 + +/* USART0, Tx Complete */ +#define USART0_TX_vect _VECTOR(20) +#define USART0_TX_vect_num 20 + +/* ADC Conversion Complete */ +#define ADC_vect _VECTOR(21) +#define ADC_vect_num 21 + +/* EEPROM Ready */ +#define EE_READY_vect _VECTOR(22) +#define EE_READY_vect_num 22 + +/* Analog Comparator */ +#define ANALOG_COMP_vect _VECTOR(23) +#define ANALOG_COMP_vect_num 23 + +/* Timer/Counter1 Compare Match C */ +#define TIMER1_COMPC_vect _VECTOR(24) +#define TIMER1_COMPC_vect_num 24 + +/* Timer/Counter3 Capture Event */ +#define TIMER3_CAPT_vect _VECTOR(25) +#define TIMER3_CAPT_vect_num 25 + +/* Timer/Counter3 Compare Match A */ +#define TIMER3_COMPA_vect _VECTOR(26) +#define TIMER3_COMPA_vect_num 26 + +/* Timer/Counter3 Compare Match B */ +#define TIMER3_COMPB_vect _VECTOR(27) +#define TIMER3_COMPB_vect_num 27 + +/* Timer/Counter3 Compare Match C */ +#define TIMER3_COMPC_vect _VECTOR(28) +#define TIMER3_COMPC_vect_num 28 + +/* Timer/Counter3 Overflow */ +#define TIMER3_OVF_vect _VECTOR(29) +#define TIMER3_OVF_vect_num 29 + +/* USART1, Rx Complete */ +#define USART1_RX_vect _VECTOR(30) +#define USART1_RX_vect_num 30 + +/* USART1, Data Register Empty */ +#define USART1_UDRE_vect _VECTOR(31) +#define USART1_UDRE_vect_num 31 + +/* USART1, Tx Complete */ +#define USART1_TX_vect _VECTOR(32) +#define USART1_TX_vect_num 32 + +/* 2-wire Serial Interface */ +#define TWI_vect _VECTOR(33) +#define TWI_vect_num 33 + +/* Store Program Memory Read */ +#define SPM_READY_vect _VECTOR(34) +#define SPM_READY_vect_num 34 + +#define _VECTORS_SIZE 140 + + +/* Constants */ + +#define SPM_PAGESIZE 256 +#define FLASHSTART 0x0000 +#define FLASHEND 0x1FFFF +#define RAMSTART 0x0100 +#define RAMSIZE 4096 +#define RAMEND 0x10FF +#define E2START 0 +#define E2SIZE 4096 +#define E2PAGESIZE 8 +#define E2END 0x0FFF +#define XRAMEND RAMEND + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) +#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) +#define FUSE_BODEN (unsigned char)~_BV(6) +#define FUSE_BODLEVEL (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_SUT_CKSEL1 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4) + + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_CKOPT (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + + +/* Extended Fuse Byte */ +#define FUSE_WDTON (unsigned char)~_BV(0) +#define FUSE_M103C (unsigned char)~_BV(1) +#define EFUSE_DEFAULT (FUSE_M103C) + + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x02 + + +#endif /* #ifdef _AVR_ATMEGA128A_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iom128rfa1.h b/hardware/tools/avr/avr/include/avr/iom128rfa1.h new file mode 100644 index 0000000000000000000000000000000000000000..77b814be04e5ba2367a27064091de42418450358 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom128rfa1.h @@ -0,0 +1,5385 @@ +/* Copyright (c) 2009 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom128rfa1.h 2009 2009-07-01 14:57:41Z joerg_wunsch $ */ + +/* avr/iom128rfa1.h - definitions for ATmega128RFA1 */ + +#ifndef _AVR_IOM128RFA1_H_ +#define _AVR_IOM128RFA1_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom128rfa1.h" +#else +# error "Attempt to include more than one file." +#endif + +#include + +#ifndef __ASSEMBLER__ +# define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr)) +# define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type) +# define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type) +#endif /* __ASSEMBLER__ */ + +/* + * USAGE: + * + * simple register assignment: + * TIFR1 = 0x17 + * subregister assignment: + * TIFR1_struct.ocf1a = 1 + * (subregister names are converted to small letters) + */ + + +/* Port A Input Pins Address */ +#define PINA _SFR_IO8(0x00) + + /* PINA */ + +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 +#define PINA4 4 +#define PINA5 5 +#define PINA6 6 +#define PINA7 7 + +/* Port A Data Direction Register */ +#define DDRA _SFR_IO8(0x01) + + /* DDRA */ + +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +/* Port A Data Register */ +#define PORTA _SFR_IO8(0x02) + + /* PORTA */ + +#define PORTA0 0 +#define PA0 0 +#define PORTA1 1 +#define PA1 1 +#define PORTA2 2 +#define PA2 2 +#define PORTA3 3 +#define PA3 3 +#define PORTA4 4 +#define PA4 4 +#define PORTA5 5 +#define PA5 5 +#define PORTA6 6 +#define PA6 6 +#define PORTA7 7 +#define PA7 7 + +/* Port B Input Pins Address */ +#define PINB _SFR_IO8(0x03) + + /* PINB */ + +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +/* Port B Data Direction Register */ +#define DDRB _SFR_IO8(0x04) + + /* DDRB */ + +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +/* Port B Data Register */ +#define PORTB _SFR_IO8(0x05) + + /* PORTB */ + +#define PORTB0 0 +#define PB0 0 +#define PORTB1 1 +#define PB1 1 +#define PORTB2 2 +#define PB2 2 +#define PORTB3 3 +#define PB3 3 +#define PORTB4 4 +#define PB4 4 +#define PORTB5 5 +#define PB5 5 +#define PORTB6 6 +#define PB6 6 +#define PORTB7 7 +#define PB7 7 + +/* Port C Input Pins Address */ +#define PINC _SFR_IO8(0x06) + + /* PINC */ + +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +/* Port C Data Direction Register */ +#define DDRC _SFR_IO8(0x07) + + /* DDRC */ + +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +/* Port C Data Register */ +#define PORTC _SFR_IO8(0x08) + + /* PORTC */ + +#define PORTC0 0 +#define PC0 0 +#define PORTC1 1 +#define PC1 1 +#define PORTC2 2 +#define PC2 2 +#define PORTC3 3 +#define PC3 3 +#define PORTC4 4 +#define PC4 4 +#define PORTC5 5 +#define PC5 5 +#define PORTC6 6 +#define PC6 6 +#define PORTC7 7 +#define PC7 7 + +/* Port D Input Pins Address */ +#define PIND _SFR_IO8(0x09) + + /* PIND */ + +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +/* Port D Data Direction Register */ +#define DDRD _SFR_IO8(0x0A) + + /* DDRD */ + +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +/* Port D Data Register */ +#define PORTD _SFR_IO8(0x0B) + + /* PORTD */ + +#define PORTD0 0 +#define PD0 0 +#define PORTD1 1 +#define PD1 1 +#define PORTD2 2 +#define PD2 2 +#define PORTD3 3 +#define PD3 3 +#define PORTD4 4 +#define PD4 4 +#define PORTD5 5 +#define PD5 5 +#define PORTD6 6 +#define PD6 6 +#define PORTD7 7 +#define PD7 7 + +/* Port E Input Pins Address */ +#define PINE _SFR_IO8(0x0C) + + /* PINE */ + +#define PINE0 0 +#define PINE1 1 +#define PINE2 2 +#define PINE3 3 +#define PINE4 4 +#define PINE5 5 +#define PINE6 6 +#define PINE7 7 + +/* Port E Data Direction Register */ +#define DDRE _SFR_IO8(0x0D) + + /* DDRE */ + +#define DDE0 0 +#define DDE1 1 +#define DDE2 2 +#define DDE3 3 +#define DDE4 4 +#define DDE5 5 +#define DDE6 6 +#define DDE7 7 + +/* Port E Data Register */ +#define PORTE _SFR_IO8(0x0E) + + /* PORTE */ + +#define PORTE0 0 +#define PE0 0 +#define PORTE1 1 +#define PE1 1 +#define PORTE2 2 +#define PE2 2 +#define PORTE3 3 +#define PE3 3 +#define PORTE4 4 +#define PE4 4 +#define PORTE5 5 +#define PE5 5 +#define PORTE6 6 +#define PE6 6 +#define PORTE7 7 +#define PE7 7 + +/* Port F Input Pins Address */ +#define PINF _SFR_IO8(0x0F) + + /* PINF */ + +#define PINF0 0 +#define PINF1 1 +#define PINF2 2 +#define PINF3 3 +#define PINF4 4 +#define PINF5 5 +#define PINF6 6 +#define PINF7 7 + +/* Port F Data Direction Register */ +#define DDRF _SFR_IO8(0x10) + + /* DDRF */ + +#define DDF0 0 +#define DDF1 1 +#define DDF2 2 +#define DDF3 3 +#define DDF4 4 +#define DDF5 5 +#define DDF6 6 +#define DDF7 7 + +/* Port F Data Register */ +#define PORTF _SFR_IO8(0x11) + + /* PORTF */ + +#define PORTF0 0 +#define PF0 0 +#define PORTF1 1 +#define PF1 1 +#define PORTF2 2 +#define PF2 2 +#define PORTF3 3 +#define PF3 3 +#define PORTF4 4 +#define PF4 4 +#define PORTF5 5 +#define PF5 5 +#define PORTF6 6 +#define PF6 6 +#define PORTF7 7 +#define PF7 7 + +/* Port G Input Pins Address */ +#define PING _SFR_IO8(0x12) + + /* PING */ + +#define PING0 0 +#define PING1 1 +#define PING2 2 +#define PING3 3 +#define PING4 4 +#define PING5 5 + +/* Port G Data Direction Register */ +#define DDRG _SFR_IO8(0x13) + + /* DDRG */ + +#define DDG0 0 +#define DDG1 1 +#define DDG2 2 +#define DDG3 3 +#define DDG4 4 +#define DDG5 5 + +/* Port G Data Register */ +#define PORTG _SFR_IO8(0x14) + + /* PORTG */ + +#define PORTG0 0 +#define PG0 0 +#define PORTG1 1 +#define PG1 1 +#define PORTG2 2 +#define PG2 2 +#define PORTG3 3 +#define PG3 3 +#define PORTG4 4 +#define PG4 4 +#define PORTG5 5 +#define PG5 5 + +/* Timer/Counter0 Interrupt Flag Register */ +#define TIFR0 _SFR_IO8(0x15) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_TIFR0 { + unsigned int tov0 : 1; /* Timer/Counter0 Overflow Flag */ + unsigned int ocf0a : 1; /* Timer/Counter0 Output Compare A Match Flag */ + unsigned int ocf0b : 1; /* Timer/Counter0 Output Compare B Match Flag */ + unsigned int : 5; +}; + +#define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0) + +#endif /* __ASSEMBLER__ */ + + /* TIFR0 */ + +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +/* Timer/Counter1 Interrupt Flag Register */ +#define TIFR1 _SFR_IO8(0x16) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_TIFR1 { + unsigned int tov1 : 1; /* Timer/Counter1 Overflow Flag */ + unsigned int ocf1a : 1; /* Timer/Counter1 Output Compare A Match Flag */ + unsigned int ocf1b : 1; /* Timer/Counter1 Output Compare B Match Flag */ + unsigned int ocf1c : 1; /* Timer/Counter1 Output Compare C Match Flag */ + unsigned int : 1; + unsigned int icf1 : 1; /* Timer/Counter1 Input Capture Flag */ + unsigned int : 2; +}; + +#define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1) + +#endif /* __ASSEMBLER__ */ + + /* TIFR1 */ + +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define OCF1C 3 +#define ICF1 5 + +/* Timer/Counter Interrupt Flag Register */ +#define TIFR2 _SFR_IO8(0x17) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_TIFR2 { + unsigned int tov2 : 1; /* Timer/Counter2 Overflow Flag */ + unsigned int ocf2a : 1; /* Output Compare Flag 2 A */ + unsigned int ocf2b : 1; /* Output Compare Flag 2 B */ + unsigned int : 5; +}; + +#define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2) + +#endif /* __ASSEMBLER__ */ + + /* TIFR2 */ + +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Timer/Counter3 Interrupt Flag Register */ +#define TIFR3 _SFR_IO8(0x18) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_TIFR3 { + unsigned int tov3 : 1; /* Timer/Counter3 Overflow Flag */ + unsigned int ocf3a : 1; /* Timer/Counter3 Output Compare A Match Flag */ + unsigned int ocf3b : 1; /* Timer/Counter3 Output Compare B Match Flag */ + unsigned int ocf3c : 1; /* Timer/Counter3 Output Compare C Match Flag */ + unsigned int : 1; + unsigned int icf3 : 1; /* Timer/Counter3 Input Capture Flag */ + unsigned int : 2; +}; + +#define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3) + +#endif /* __ASSEMBLER__ */ + + /* TIFR3 */ + +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define OCF3C 3 +#define ICF3 5 + +/* Timer/Counter4 Interrupt Flag Register */ +#define TIFR4 _SFR_IO8(0x19) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_TIFR4 { + unsigned int tov4 : 1; /* Timer/Counter4 Overflow Flag */ + unsigned int ocf4a : 1; /* Timer/Counter4 Output Compare A Match Flag */ + unsigned int ocf4b : 1; /* Timer/Counter4 Output Compare B Match Flag */ + unsigned int ocf4c : 1; /* Timer/Counter4 Output Compare C Match Flag */ + unsigned int : 1; + unsigned int icf4 : 1; /* Timer/Counter4 Input Capture Flag */ + unsigned int : 2; +}; + +#define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4) + +#endif /* __ASSEMBLER__ */ + + /* TIFR4 */ + +#define TOV4 0 +#define OCF4A 1 +#define OCF4B 2 +#define OCF4C 3 +#define ICF4 5 + +/* Timer/Counter5 Interrupt Flag Register */ +#define TIFR5 _SFR_IO8(0x1A) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_TIFR5 { + unsigned int tov5 : 1; /* Timer/Counter5 Overflow Flag */ + unsigned int ocf5a : 1; /* Timer/Counter5 Output Compare A Match Flag */ + unsigned int ocf5b : 1; /* Timer/Counter5 Output Compare B Match Flag */ + unsigned int ocf5c : 1; /* Timer/Counter5 Output Compare C Match Flag */ + unsigned int : 1; + unsigned int icf5 : 1; /* Timer/Counter5 Input Capture Flag */ + unsigned int : 2; +}; + +#define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5) + +#endif /* __ASSEMBLER__ */ + + /* TIFR5 */ + +#define TOV5 0 +#define OCF5A 1 +#define OCF5B 2 +#define OCF5C 3 +#define ICF5 5 + +/* Pin Change Interrupt Flag Register */ +#define PCIFR _SFR_IO8(0x1B) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_PCIFR { + unsigned int pcif : 3; /* Pin Change Interrupt Flag 2 */ + unsigned int : 5; +}; + +#define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR) + +#endif /* __ASSEMBLER__ */ + + /* PCIFR */ + +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +/* External Interrupt Flag Register */ +#define EIFR _SFR_IO8(0x1C) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_EIFR { + unsigned int intf : 8; /* External Interrupt Flag */ +}; + +#define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR) + +#endif /* __ASSEMBLER__ */ + + /* EIFR */ + +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +/* External Interrupt Mask Register */ +#define EIMSK _SFR_IO8(0x1D) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_EIMSK { + unsigned int intm : 8; /* External Interrupt Request Enable */ +}; + +#define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK) + +#endif /* __ASSEMBLER__ */ + + /* EIMSK */ + +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +/* General Purpose IO Register 0 */ +#define GPIOR0 _SFR_IO8(0x1E) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_GPIOR0 { + unsigned int gpior0 : 8; /* General Purpose I/O Register 0 Value */ +}; + +#define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0) + +#endif /* __ASSEMBLER__ */ + + /* GPIOR0 */ + +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ + +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1F) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_EECR { + unsigned int eere : 1; /* EEPROM Read Enable */ + unsigned int eepe : 1; /* EEPROM Programming Enable */ + unsigned int eempe : 1; /* EEPROM Master Write Enable */ + unsigned int eerie : 1; /* EEPROM Ready Interrupt Enable */ + unsigned int eepm : 2; /* EEPROM Programming Mode */ + unsigned int : 2; +}; + +#define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR) + +#endif /* __ASSEMBLER__ */ + + /* EECR */ + +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x20) + + /* EEDR */ + +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +/* EEPROM Address Register Bytes */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +/* General Timer/Counter Control Register */ +#define GTCCR _SFR_IO8(0x23) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_GTCCR { + unsigned int psrsync : 1; /* Prescaler Reset for Synchronous Timer/Counters */ + unsigned int psrasy : 1; /* Prescaler Reset Timer/Counter2 */ + unsigned int : 5; + unsigned int tsm : 1; /* Timer/Counter Synchronization Mode */ +}; + +#define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR) + +#endif /* __ASSEMBLER__ */ + + /* GTCCR */ + +#define PSRSYNC 0 +#define PSR10 0 +#define PSRASY 1 +#define PSR2 1 +#define TSM 7 + +/* Timer/Counter0 Control Register A */ +#define TCCR0A _SFR_IO8(0x24) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_TCCR0A { + unsigned int wgm0 : 2; /* Waveform Generation Mode */ + unsigned int : 2; + unsigned int com0b : 2; /* Compare Match Output B Mode */ + unsigned int com0a : 2; /* Compare Match Output A Mode */ +}; + +#define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A) + +#endif /* __ASSEMBLER__ */ + + /* TCCR0A */ + +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +/* Timer/Counter0 Control Register B */ +#define TCCR0B _SFR_IO8(0x25) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_TCCR0B { + unsigned int cs0 : 3; /* Clock Select */ + unsigned int wgm02 : 1; /* */ + unsigned int : 2; + unsigned int foc0b : 1; /* Force Output Compare B */ + unsigned int foc0a : 1; /* Force Output Compare A */ +}; + +#define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B) + +#endif /* __ASSEMBLER__ */ + + /* TCCR0B */ + +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +/* Timer/Counter0 Register */ +#define TCNT0 _SFR_IO8(0x26) + + /* TCNT0 */ + +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +/* Timer/Counter0 Output Compare Register */ +#define OCR0A _SFR_IO8(0x27) + + /* OCR0A */ + +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +/* Timer/Counter0 Output Compare Register B */ +#define OCR0B _SFR_IO8(0x28) + + /* OCR0B */ + +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +/* General Purpose IO Register 1 */ +#define GPIOR1 _SFR_IO8(0x2A) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_GPIOR1 { + unsigned int gpior1 : 8; /* General Purpose I/O Register 1 Value */ +}; + +#define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1) + +#endif /* __ASSEMBLER__ */ + + /* GPIOR1 */ + +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +/* General Purpose I/O Register 2 */ +#define GPIOR2 _SFR_IO8(0x2B) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_GPIOR2 { + unsigned int gpior2 : 8; /* General Purpose I/O Register 2 Value */ +}; + +#define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2) + +#endif /* __ASSEMBLER__ */ + + /* GPIOR2 */ + +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x2C) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_SPCR { + unsigned int spr : 2; /* SPI Clock Rate Select 1 and 0 */ + unsigned int cpha : 1; /* Clock Phase */ + unsigned int cpol : 1; /* Clock polarity */ + unsigned int mstr : 1; /* Master/Slave Select */ + unsigned int dord : 1; /* Data Order */ + unsigned int spe : 1; /* SPI Enable */ + unsigned int spie : 1; /* SPI Interrupt Enable */ +}; + +#define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR) + +#endif /* __ASSEMBLER__ */ + + /* SPCR */ + +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x2D) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_SPSR { + unsigned int spi2x : 1; /* Double SPI Speed Bit */ + unsigned int : 5; + unsigned int wcol : 1; /* Write Collision Flag */ + unsigned int spif : 1; /* SPI Interrupt Flag */ +}; + +#define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR) + +#endif /* __ASSEMBLER__ */ + + /* SPSR */ + +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +/* SPI Data Register */ +#define SPDR _SFR_IO8(0x2E) + + /* SPDR */ + +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +/* Analog Comparator Control And Status Register */ +#define ACSR _SFR_IO8(0x30) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_ACSR { + unsigned int acis : 2; /* Analog Comparator Interrupt Mode Select */ + unsigned int acic : 1; /* Analog Comparator Input Capture Enable */ + unsigned int acie : 1; /* Analog Comparator Interrupt Enable */ + unsigned int aci : 1; /* Analog Comparator Interrupt Flag */ + unsigned int aco : 1; /* Analog Compare Output */ + unsigned int acbg : 1; /* Analog Comparator Bandgap Select */ + unsigned int acd : 1; /* Analog Comparator Disable */ +}; + +#define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR) + +#endif /* __ASSEMBLER__ */ + + /* ACSR */ + +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* On-Chip Debug Register */ +#define OCDR _SFR_IO8(0x31) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_OCDR { + unsigned int ocdr : 8; /* On-Chip Debug Register Data */ +}; + +#define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR) + +#endif /* __ASSEMBLER__ */ + + /* OCDR */ + +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 +#define IDRD 7 + +/* Sleep Mode Control Register */ +#define SMCR _SFR_IO8(0x33) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_SMCR { + unsigned int se : 1; /* Sleep Enable */ + unsigned int sm : 3; /* Sleep Mode Select bits */ + unsigned int : 4; +}; + +#define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR) + +#endif /* __ASSEMBLER__ */ + + /* SMCR */ + +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +/* MCU Status Register */ +#define MCUSR _SFR_IO8(0x34) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_MCUSR { + unsigned int porf : 1; /* Power-on Reset Flag */ + unsigned int extrf : 1; /* External Reset Flag */ + unsigned int borf : 1; /* Brown-out Reset Flag */ + unsigned int wdrf : 1; /* Watchdog Reset Flag */ + unsigned int jtrf : 1; /* JTAG Reset Flag */ + unsigned int : 3; +}; + +#define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR) + +#endif /* __ASSEMBLER__ */ + + /* MCUSR */ + +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +/* MCU Control Register */ +#define MCUCR _SFR_IO8(0x35) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_MCUCR { + unsigned int ivce : 1; /* Interrupt Vector Change Enable */ + unsigned int ivsel : 1; /* Interrupt Vector Select */ + unsigned int : 2; + unsigned int pud : 1; /* Pull-up Disable */ + unsigned int : 2; + unsigned int jtd : 1; /* JTAG Interface Disable */ +}; + +#define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR) + +#endif /* __ASSEMBLER__ */ + + /* MCUCR */ + +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define JTD 7 + +/* Store Program Memory Control Register */ +#define SPMCSR _SFR_IO8(0x37) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_SPMCSR { + unsigned int spmen : 1; /* Store Program Memory Enable */ + unsigned int pgers : 1; /* Page Erase */ + unsigned int pgwrt : 1; /* Page Write */ + unsigned int blbset : 1; /* Boot Lock Bit Set */ + unsigned int rwwsre : 1; /* Read While Write Section Read Enable */ + unsigned int sigrd : 1; /* Signature Row Read */ + unsigned int rwwsb : 1; /* Read While Write Section Busy */ + unsigned int spmie : 1; /* SPM Interrupt Enable */ +}; + +#define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR) + +#endif /* __ASSEMBLER__ */ + + /* SPMCSR */ + +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Extended Z-pointer Register for ELPM/SPM */ +#define RAMPZ _SFR_IO8(0x3B) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_RAMPZ { + unsigned int rampz : 2; /* Extended Z-Pointer Value */ + unsigned int : 6; +}; + +#define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ) + +#endif /* __ASSEMBLER__ */ + + /* RAMPZ */ + +#define RAMPZ0 0 +#define RAMPZ1 1 + +/* Stack Pointer */ +#define SP _SFR_IO16(0x3D) +#define SPL _SFR_IO8(0x3D) +#define SPH _SFR_IO8(0x3E) + +/* Status Register */ +#define SREG _SFR_IO8(0x3F) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_SREG { + unsigned int c : 1; /* Carry Flag */ + unsigned int z : 1; /* Zero Flag */ + unsigned int n : 1; /* Negative Flag */ + unsigned int v : 1; /* Two's Complement Overflow Flag */ + unsigned int s : 1; /* Sign Bit */ + unsigned int h : 1; /* Half Carry Flag */ + unsigned int t : 1; /* Bit Copy Storage */ + unsigned int i : 1; /* Global Interrupt Enable */ +}; + +#define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG) + +#endif /* __ASSEMBLER__ */ + + /* SREG */ + +#define SREG_C 0 +#define SREG_Z 1 +#define SREG_N 2 +#define SREG_V 3 +#define SREG_S 4 +#define SREG_H 5 +#define SREG_T 6 +#define SREG_I 7 + +/* Watchdog Timer Control Register */ +#define WDTCSR _SFR_MEM8(0x60) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_WDTCSR { + unsigned int wdp : 3; /* Watchdog Timer Prescaler bits */ + unsigned int wde : 1; /* Watch Dog Enable */ + unsigned int wdce : 1; /* Watchdog Change Enable */ + unsigned int : 1; + unsigned int wdie : 1; /* Watchdog Timeout Interrupt Enable */ + unsigned int wdif : 1; /* Watchdog Timeout Interrupt Flag */ +}; + +#define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR) + +#endif /* __ASSEMBLER__ */ + + /* WDTCSR */ + +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +/* Clock Prescale Register */ +#define CLKPR _SFR_MEM8(0x61) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_CLKPR { + unsigned int clkps : 4; /* Clock Prescaler Select Bits */ + unsigned int : 3; + unsigned int clkpce : 1; /* Clock Prescaler Change Enable */ +}; + +#define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR) + +#endif /* __ASSEMBLER__ */ + + /* CLKPR */ + +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Power Reduction Register 2 */ +#define PRR2 _SFR_MEM8(0x63) + +#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) + +struct __reg_PRR2 { + unsigned int prram : 4; /* Power Reduction SRAM 3 */ + unsigned int : 4; +}; + +#define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2) + +#endif /* __ASSEMBLER__ */ + + /* PRR2 */ + +#define PRRAM0 0 +#define PRRAM1 1 +#define PRRAM2 2 +#define PRRAM3 3 + +#define __AVR_HAVE_PRR2 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom128rfr2.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_IO8(0x12) +#define PING7 7 +#define PING6 6 +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDRG7 7 +// Inserted "DDG7" from "DDRG7" due to compatibility +#define DDG7 7 +#define DDRG6 6 +// Inserted "DDG6" from "DDRG6" due to compatibility +#define DDG6 6 +#define DDRG5 5 +// Inserted "DDG5" from "DDRG5" due to compatibility +#define DDG5 5 +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PORTG7 7 +#define PORTG6 6 +#define PORTG5 5 +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define Res0 3 +#define Res1 4 +#define Res2 5 +#define Res3 6 +#define Res4 7 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define OCF1C 3 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define OCF3C 3 +#define ICF3 5 + +#define TIFR4 _SFR_IO8(0x19) +#define TOV4 0 +#define OCF4A 1 +#define OCF4B 2 +#define OCF4C 3 +#define ICF4 5 + +#define TIFR5 _SFR_IO8(0x1A) +#define TOV5 0 +#define OCF5A 1 +#define OCF5B 2 +#define OCF5C 3 +#define ICF5 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3A] */ + +#define RAMPZ _SFR_IO8(0x3B) +#define RAMPZ0 0 +#define Res5 6 +#define Res6 7 + +/* Reserved [0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62] */ + +#define PRR2 _SFR_MEM8(0x63) +#define PRRAM0 0 +#define PRRAM1 1 +#define PRRAM2 2 +#define PRRAM3 3 + +#define __AVR_HAVE_PRR2 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom16.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define TWBR _SFR_IO8(0x00) + +#define TWSR _SFR_IO8(0x01) +#define TWPS0 0 +#define TWPS1 1 +#define TWS3 3 +#define TWS4 4 +#define TWS5 5 +#define TWS6 6 +#define TWS7 7 + +#define TWAR _SFR_IO8(0x02) +#define TWGCE 0 +#define TWA0 1 +#define TWA1 2 +#define TWA2 3 +#define TWA3 4 +#define TWA4 5 +#define TWA5 6 +#define TWA6 7 + +#define TWDR _SFR_IO8(0x03) + +/* Combine ADCL and ADCH */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) + +#define ADCSRA _SFR_IO8(0x06) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +#define ADMUX _SFR_IO8(0x07) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define MUX4 4 +#define ADLAR 5 +#define REFS0 6 +#define REFS1 7 + +#define ACSR _SFR_IO8(0x08) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define UBRRL _SFR_IO8(0x09) + +#define UCSRB _SFR_IO8(0x0A) +#define TXB8 0 +#define RXB8 1 +#define UCSZ2 2 +#define TXEN 3 +#define RXEN 4 +#define UDRIE 5 +#define TXCIE 6 +#define RXCIE 7 + +#define UCSRA _SFR_IO8(0x0B) +#define MPCM 0 +#define U2X 1 +#define PE 2 +#define DOR 3 +#define FE 4 +#define UDRE 5 +#define TXC 6 +#define RXC 7 + +#define UDR _SFR_IO8(0x0C) + +#define SPCR _SFR_IO8(0x0D) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x0E) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x0F) + +#define PIND _SFR_IO8(0x10) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x11) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x12) +#define PD0 0 +#define PD1 1 +#define PD2 2 +#define PD3 3 +#define PD4 4 +#define PD5 5 +#define PD6 6 +#define PD7 7 + +#define PINC _SFR_IO8(0x13) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x14) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x15) +#define PC0 0 +#define PC1 1 +#define PC2 2 +#define PC3 3 +#define PC4 4 +#define PC5 5 +#define PC6 6 +#define PC7 7 + +#define PINB _SFR_IO8(0x16) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x17) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x18) +#define PB0 0 +#define PB1 1 +#define PB2 2 +#define PB3 3 +#define PB4 4 +#define PB5 5 +#define PB6 6 +#define PB7 7 + +#define PINA _SFR_IO8(0x19) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 +#define PINA4 4 +#define PINA5 5 +#define PINA6 6 +#define PINA7 7 + +#define DDRA _SFR_IO8(0x1A) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x1B) +#define PA0 0 +#define PA1 1 +#define PA2 2 +#define PA3 3 +#define PA4 4 +#define PA5 5 +#define PA6 6 +#define PA7 7 + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO16(0x1E) +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +#define UCSRC _SFR_IO8(0x20) +#define UCPOL 0 +#define UCSZ0 1 +#define UCSZ1 2 +#define USBS 3 +#define UPM0 4 +#define UPM1 5 +#define UMSEL 6 +#define URSEL 7 + +#define UBRRH _SFR_IO8(0x20) +#define URSEL 7 + +#define WDTCR _SFR_IO8(0x21) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDTOE 4 + +#define ASSR _SFR_IO8(0x22) +#define TCR2UB 0 +#define OCR2UB 1 +#define TCN2UB 2 +#define AS2 3 + +#define OCR2 _SFR_IO8(0x23) + +#define TCNT2 _SFR_IO8(0x24) + +#define TCCR2 _SFR_IO8(0x25) +#define CS20 0 +#define CS21 1 +#define CS22 2 +#define WGM21 3 +#define COM20 4 +#define COM21 5 +#define WGM20 6 +#define FOC2 7 + +/* Combine ICR1L and ICR1H */ +#define ICR1 _SFR_IO16(0x26) + +#define ICR1L _SFR_IO8(0x26) +#define ICR1H _SFR_IO8(0x27) + +/* Combine OCR1BL and OCR1BH */ +#define OCR1B _SFR_IO16(0x28) + +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Combine OCR1AL and OCR1AH */ +#define OCR1A _SFR_IO16(0x2A) + +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Combine TCNT1L and TCNT1H */ +#define TCNT1 _SFR_IO16(0x2C) + +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +#define TCCR1B _SFR_IO8(0x2E) +#define CS10 0 +#define CS11 1 +#define CS12 2 +#define WGM12 3 +#define WGM13 4 +#define ICES1 6 +#define ICNC1 7 + +#define TCCR1A _SFR_IO8(0x2F) +#define WGM10 0 +#define WGM11 1 +#define FOC1B 2 +#define FOC1A 3 +#define COM1B0 4 +#define COM1B1 5 +#define COM1A0 6 +#define COM1A1 7 + +/* + The ADHSM bit has been removed from all documentation, + as being not needed at all since the comparator has proven + to be fast enough even without feeding it more power. +*/ + +#define SFIOR _SFR_IO8(0x30) +#define PSR10 0 +#define PSR2 1 +#define PUD 2 +#define ACME 3 +#define ADTS0 5 +#define ADTS1 6 +#define ADTS2 7 + +#define OSCCAL _SFR_IO8(0x31) + +#define OCDR _SFR_IO8(0x31) + +#define TCNT0 _SFR_IO8(0x32) + +#define TCCR0 _SFR_IO8(0x33) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM00 4 +#define COM01 5 +#define WGM00 6 +#define FOC0 7 + +#define MCUCSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 +#define ISC2 6 +#define JTD 7 + +#define MCUCR _SFR_IO8(0x35) +#define ISC00 0 +#define ISC01 1 +#define ISC10 2 +#define ISC11 3 +#define SM0 4 +#define SM1 5 +#define SE 6 +#define SM2 7 + +#define TWCR _SFR_IO8(0x36) +#define TWIE 0 +#define TWEN 2 +#define TWWC 3 +#define TWSTO 4 +#define TWSTA 5 +#define TWEA 6 +#define TWINT 7 + +#define SPMCR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +#define TIFR _SFR_IO8(0x38) +#define TOV0 0 +#define OCF0 1 +#define TOV1 2 +#define OCF1B 3 +#define OCF1A 4 +#define ICF1 5 +#define TOV2 6 +#define OCF2 7 + +#define TIMSK _SFR_IO8(0x39) +#define TOIE0 0 +#define OCIE0 1 +#define TOIE1 2 +#define OCIE1B 3 +#define OCIE1A 4 +#define TICIE1 5 +#define TOIE2 6 +#define OCIE2 7 + +#define GIFR _SFR_IO8(0x3A) +#define INTF2 5 +#define INTF0 6 +#define INTF1 7 + +#define GICR _SFR_IO8(0x3B) +#define IVCE 0 +#define IVSEL 1 +#define INT2 5 +#define INT0 6 +#define INT1 7 + +#define OCR0 _SFR_IO8(0x3C) + +/* SP [0x3D..0x3E] */ +/* SREG [0x3F] */ + + +/* Interrupt vectors */ +/* Vector 0 is the reset vector. */ +/* External Interrupt Request 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt Request 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* Timer/Counter2 Compare Match */ +#define TIMER2_COMP_vect_num 3 +#define TIMER2_COMP_vect _VECTOR(3) +#define SIG_OUTPUT_COMPARE2 _VECTOR(3) + +/* Timer/Counter2 Overflow */ +#define TIMER2_OVF_vect_num 4 +#define TIMER2_OVF_vect _VECTOR(4) +#define SIG_OVERFLOW2 _VECTOR(4) + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect_num 5 +#define TIMER1_CAPT_vect _VECTOR(5) +#define SIG_INPUT_CAPTURE1 _VECTOR(5) + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect_num 6 +#define TIMER1_COMPA_vect _VECTOR(6) +#define SIG_OUTPUT_COMPARE1A _VECTOR(6) + +/* Timer/Counter1 Compare Match B */ +#define TIMER1_COMPB_vect_num 7 +#define TIMER1_COMPB_vect _VECTOR(7) +#define SIG_OUTPUT_COMPARE1B _VECTOR(7) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 8 +#define TIMER1_OVF_vect _VECTOR(8) +#define SIG_OVERFLOW1 _VECTOR(8) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 9 +#define TIMER0_OVF_vect _VECTOR(9) +#define SIG_OVERFLOW0 _VECTOR(9) + +/* Serial Transfer Complete */ +#define SPI_STC_vect_num 10 +#define SPI_STC_vect _VECTOR(10) +#define SIG_SPI _VECTOR(10) + +/* USART, Rx Complete */ +#define USART_RXC_vect_num 11 +#define USART_RXC_vect _VECTOR(11) +#define SIG_USART_RECV _VECTOR(11) +#define SIG_UART_RECV _VECTOR(11) + +/* USART Data Register Empty */ +#define USART_UDRE_vect_num 12 +#define USART_UDRE_vect _VECTOR(12) +#define SIG_USART_DATA _VECTOR(12) +#define SIG_UART_DATA _VECTOR(12) + +/* USART, Tx Complete */ +#define USART_TXC_vect_num 13 +#define USART_TXC_vect _VECTOR(13) +#define SIG_USART_TRANS _VECTOR(13) +#define SIG_UART_TRANS _VECTOR(13) + +/* ADC Conversion Complete */ +#define ADC_vect_num 14 +#define ADC_vect _VECTOR(14) +#define SIG_ADC _VECTOR(14) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 15 +#define EE_RDY_vect _VECTOR(15) +#define SIG_EEPROM_READY _VECTOR(15) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 16 +#define ANA_COMP_vect _VECTOR(16) +#define SIG_COMPARATOR _VECTOR(16) + +/* 2-wire Serial Interface */ +#define TWI_vect_num 17 +#define TWI_vect _VECTOR(17) +#define SIG_2WIRE_SERIAL _VECTOR(17) + +/* External Interrupt Request 2 */ +#define INT2_vect_num 18 +#define INT2_vect _VECTOR(18) +#define SIG_INTERRUPT2 _VECTOR(18) + +/* Timer/Counter0 Compare Match */ +#define TIMER0_COMP_vect_num 19 +#define TIMER0_COMP_vect _VECTOR(19) +#define SIG_OUTPUT_COMPARE0 _VECTOR(19) + +/* Store Program Memory Ready */ +#define SPM_RDY_vect_num 20 +#define SPM_RDY_vect _VECTOR(20) +#define SIG_SPM_READY _VECTOR(20) + +#define _VECTORS_SIZE 84 + + +/* Constants */ +#define SPM_PAGESIZE 128 +#define RAMSTART (0x60) +#define RAMEND 0x45F +#define XRAMEND RAMEND +#define E2END 0x1FF +#define E2PAGESIZE 4 +#define FLASHEND 0x3FFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 2 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_BODEN (unsigned char)~_BV(6) +#define FUSE_BODLEVEL (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_CKOPT (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x03 + + + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_INTERRUPT1 +#pragma GCC poison SIG_OUTPUT_COMPARE2 +#pragma GCC poison SIG_OVERFLOW2 +#pragma GCC poison SIG_INPUT_CAPTURE1 +#pragma GCC poison SIG_OUTPUT_COMPARE1A +#pragma GCC poison SIG_OUTPUT_COMPARE1B +#pragma GCC poison SIG_OVERFLOW1 +#pragma GCC poison SIG_OVERFLOW0 +#pragma GCC poison SIG_SPI +#pragma GCC poison SIG_USART_RECV +#pragma GCC poison SIG_UART_RECV +#pragma GCC poison SIG_USART_DATA +#pragma GCC poison SIG_UART_DATA +#pragma GCC poison SIG_USART_TRANS +#pragma GCC poison SIG_UART_TRANS +#pragma GCC poison SIG_ADC +#pragma GCC poison SIG_EEPROM_READY +#pragma GCC poison SIG_COMPARATOR +#pragma GCC poison SIG_2WIRE_SERIAL +#pragma GCC poison SIG_INTERRUPT2 +#pragma GCC poison SIG_OUTPUT_COMPARE0 +#pragma GCC poison SIG_SPM_READY + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + +#define SLEEP_MODE_IDLE (0x00<<4) +#define SLEEP_MODE_ADC (0x01<<4) +#define SLEEP_MODE_PWR_DOWN (0x02<<4) +#define SLEEP_MODE_PWR_SAVE (0x03<<4) +#define SLEEP_MODE_STANDBY (0x0A<<4) +#define SLEEP_MODE_EXT_STANDBY (0x0B<<4) + +#endif /* _AVR_IOM16_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom1608.h b/hardware/tools/avr/avr/include/avr/iom1608.h new file mode 100644 index 0000000000000000000000000000000000000000..6da3565048980fb51645d3e7eb907bf4f4e112cb --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom1608.h @@ -0,0 +1,4955 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom1608.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATMEGA1608_H_INCLUDED +#define _AVR_ATMEGA1608_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[1]; + register8_t DACREF; /* Referance scale control */ + register8_t reserved_3[1]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_PIN2_gc = (0x02<<0), /* Negative Pin 2 */ + AC_MUXNEG_DACREF_gc = (0x03<<0), /* DAC Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ + ADC_MUXPOS_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ + ADC_MUXPOS_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ + ADC_MUXPOS_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ + ADC_MUXPOS_DACREF_gc = (0x1C<<0), /* AC DAC Reference */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temperature sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* 0V (GND) */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t SEQCTRL1; /* Sequential Control 1 */ + register8_t reserved_1[2]; + register8_t INTCTRL0; /* Interrupt Control 0 */ + register8_t reserved_2[1]; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t LUT2CTRLA; /* LUT Control 2 A */ + register8_t LUT2CTRLB; /* LUT Control 2 B */ + register8_t LUT2CTRLC; /* LUT Control 2 C */ + register8_t TRUTH2; /* Truth 2 */ + register8_t LUT3CTRLA; /* LUT Control 3 A */ + register8_t LUT3CTRLB; /* LUT Control 3 B */ + register8_t LUT3CTRLC; /* LUT Control 3 C */ + register8_t TRUTH3; /* Truth 3 */ + register8_t reserved_3[40]; +} CCL_t; + +/* Clock Source Selection select */ +typedef enum CCL_CLKSRC_enum +{ + CCL_CLKSRC_CLKPER_gc = (0x00<<1), /* CLK_PER is clocking the LUT */ + CCL_CLKSRC_IN2_gc = (0x01<<1), /* IN[2] is clocking the LUT */ + CCL_CLKSRC_OSC20M_gc = (0x04<<1), /* 20MHz oscillator before prescaler is clocking the LUT */ + CCL_CLKSRC_OSCULP32K_gc = (0x05<<1), /* 32kHz oscillator is clocking the LUT */ + CCL_CLKSRC_OSCULP1K_gc = (0x06<<1), /* 32kHz oscillator after DIV32 is clocking the LUT */ +} CCL_CLKSRC_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL0_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_USART0_gc = (0x08<<0), /* USART0 TXD input source */ + CCL_INSEL0_SPI0_gc = (0x09<<0), /* SPI0 MOSI input source */ + CCL_INSEL0_TCA0_gc = (0x0A<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCB0_gc = (0x0C<<0), /* TCB0 WO input source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENTA_gc = (0x03<<4), /* Event input source A */ + CCL_INSEL1_EVENTB_gc = (0x04<<4), /* Event input source B */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_USART1_gc = (0x08<<4), /* USART1 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x09<<4), /* SPI0 MOSI input source */ + CCL_INSEL1_TCA0_gc = (0x0A<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCB1_gc = (0x0C<<4), /* TCB1 WO input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL2_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_USART2_gc = (0x08<<0), /* USART2 TXD input source */ + CCL_INSEL2_SPI0_gc = (0x09<<0), /* SPI0 SCK input source */ + CCL_INSEL2_TCA0_gc = (0x0A<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCB2_gc = (0x0C<<0), /* TCB2 WO input source */ +} CCL_INSEL2_t; + +/* Interrupt Mode for LUT0 select */ +typedef enum CCL_INTMODE0_enum +{ + CCL_INTMODE0_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled */ + CCL_INTMODE0_RISING_gc = (0x01<<0), /* Sense rising edge */ + CCL_INTMODE0_FALLING_gc = (0x02<<0), /* Sense falling edge */ + CCL_INTMODE0_BOTH_gc = (0x03<<0), /* Sense both edges */ +} CCL_INTMODE0_t; + +/* Interrupt Mode for LUT1 select */ +typedef enum CCL_INTMODE1_enum +{ + CCL_INTMODE1_INTDISABLE_gc = (0x00<<2), /* Interrupt disabled */ + CCL_INTMODE1_RISING_gc = (0x01<<2), /* Sense rising edge */ + CCL_INTMODE1_FALLING_gc = (0x02<<2), /* Sense falling edge */ + CCL_INTMODE1_BOTH_gc = (0x03<<2), /* Sense both edges */ +} CCL_INTMODE1_t; + +/* Interrupt Mode for LUT2 select */ +typedef enum CCL_INTMODE2_enum +{ + CCL_INTMODE2_INTDISABLE_gc = (0x00<<4), /* Interrupt disabled */ + CCL_INTMODE2_RISING_gc = (0x01<<4), /* Sense rising edge */ + CCL_INTMODE2_FALLING_gc = (0x02<<4), /* Sense falling edge */ + CCL_INTMODE2_BOTH_gc = (0x03<<4), /* Sense both edges */ +} CCL_INTMODE2_t; + +/* Interrupt Mode for LUT3 select */ +typedef enum CCL_INTMODE3_enum +{ + CCL_INTMODE3_INTDISABLE_gc = (0x00<<6), /* Interrupt disabled */ + CCL_INTMODE3_RISING_gc = (0x01<<6), /* Sense rising edge */ + CCL_INTMODE3_FALLING_gc = (0x02<<6), /* Sense falling edge */ + CCL_INTMODE3_BOTH_gc = (0x03<<6), /* Sense both edges */ +} CCL_INTMODE3_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL0_enum +{ + CCL_SEQSEL0_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL0_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL0_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL0_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL0_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL0_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL1_enum +{ + CCL_SEQSEL1_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL1_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL1_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL1_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL1_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL1_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1k cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16k cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32k cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t STROBE; /* Channel Strobe */ + register8_t reserved_1[15]; + register8_t CHANNEL0; /* Multiplexer Channel 0 */ + register8_t CHANNEL1; /* Multiplexer Channel 1 */ + register8_t CHANNEL2; /* Multiplexer Channel 2 */ + register8_t CHANNEL3; /* Multiplexer Channel 3 */ + register8_t CHANNEL4; /* Multiplexer Channel 4 */ + register8_t CHANNEL5; /* Multiplexer Channel 5 */ + register8_t reserved_2[10]; + register8_t USERCCLLUT0A; /* User CCL LUT0 Event A */ + register8_t USERCCLLUT0B; /* User CCL LUT0 Event B */ + register8_t USERCCLLUT1A; /* User CCL LUT1 Event A */ + register8_t USERCCLLUT1B; /* User CCL LUT1 Event B */ + register8_t USERCCLLUT2A; /* User CCL LUT2 Event A */ + register8_t USERCCLLUT2B; /* User CCL LUT2 Event B */ + register8_t USERCCLLUT3A; /* User CCL LUT3 Event A */ + register8_t USERCCLLUT3B; /* User CCL LUT3 Event B */ + register8_t USERADC0; /* User ADC0 */ + register8_t USEREVOUTA; /* User EVOUT Port A */ + register8_t USEREVOUTB; /* User EVOUT Port B */ + register8_t USEREVOUTC; /* User EVOUT Port C */ + register8_t USEREVOUTD; /* User EVOUT Port D */ + register8_t USEREVOUTE; /* User EVOUT Port E */ + register8_t USEREVOUTF; /* User EVOUT Port F */ + register8_t USERUSART0; /* User USART0 */ + register8_t USERUSART1; /* User USART1 */ + register8_t USERUSART2; /* User USART2 */ + register8_t USERUSART3; /* User USART3 */ + register8_t USERTCA0; /* User TCA0 */ + register8_t USERTCB0; /* User TCB0 */ + register8_t USERTCB1; /* User TCB1 */ + register8_t USERTCB2; /* User TCB2 */ + register8_t USERTCB3; /* User TCB3 */ + register8_t reserved_3[8]; +} EVSYS_t; + +/* Channel selector select */ +typedef enum EVSYS_CHANNEL_enum +{ + EVSYS_CHANNEL_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL_CHANNEL0_gc = (0x01<<0), /* Connect user to event channel 0 */ + EVSYS_CHANNEL_CHANNEL1_gc = (0x02<<0), /* Connect user to event channel 1 */ + EVSYS_CHANNEL_CHANNEL2_gc = (0x03<<0), /* Connect user to event channel 2 */ + EVSYS_CHANNEL_CHANNEL3_gc = (0x04<<0), /* Connect user to event channel 3 */ + EVSYS_CHANNEL_CHANNEL4_gc = (0x05<<0), /* Connect user to event channel 4 */ + EVSYS_CHANNEL_CHANNEL5_gc = (0x06<<0), /* Connect user to event channel 5 */ +} EVSYS_CHANNEL_t; + +/* Generator selector select */ +typedef enum EVSYS_GENERATOR_enum +{ + EVSYS_GENERATOR_OFF_gc = (0x00<<0), /* Off */ + EVSYS_GENERATOR_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_GENERATOR_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_GENERATOR_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_GENERATOR_RTC_PIT0_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_GENERATOR_RTC_PIT1_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_GENERATOR_RTC_PIT2_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_GENERATOR_RTC_PIT3_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_GENERATOR_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_GENERATOR_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_GENERATOR_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_GENERATOR_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_GENERATOR_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_GENERATOR_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready Event */ + EVSYS_GENERATOR_PORT0_PIN0_gc = (0x40<<0), /* Port 0 Pin 0 */ + EVSYS_GENERATOR_PORT0_PIN1_gc = (0x41<<0), /* Port 0 Pin 1 */ + EVSYS_GENERATOR_PORT0_PIN2_gc = (0x42<<0), /* Port 0 Pin 2 */ + EVSYS_GENERATOR_PORT0_PIN3_gc = (0x43<<0), /* Port 0 Pin 3 */ + EVSYS_GENERATOR_PORT0_PIN4_gc = (0x44<<0), /* Port 0 Pin 4 */ + EVSYS_GENERATOR_PORT0_PIN5_gc = (0x45<<0), /* Port 0 Pin 5 */ + EVSYS_GENERATOR_PORT0_PIN6_gc = (0x46<<0), /* Port 0 Pin 6 */ + EVSYS_GENERATOR_PORT0_PIN7_gc = (0x47<<0), /* Port 0 Pin 7 */ + EVSYS_GENERATOR_PORT1_PIN0_gc = (0x48<<0), /* Port 1 Pin 0 */ + EVSYS_GENERATOR_PORT1_PIN1_gc = (0x49<<0), /* Port 1 Pin 1 */ + EVSYS_GENERATOR_PORT1_PIN2_gc = (0x4A<<0), /* Port 1 Pin 2 */ + EVSYS_GENERATOR_PORT1_PIN3_gc = (0x4B<<0), /* Port 1 Pin 3 */ + EVSYS_GENERATOR_PORT1_PIN4_gc = (0x4C<<0), /* Port 1 Pin 4 */ + EVSYS_GENERATOR_PORT1_PIN5_gc = (0x4D<<0), /* Port 1 Pin 5 */ + EVSYS_GENERATOR_PORT1_PIN6_gc = (0x4E<<0), /* Port 1 Pin 6 */ + EVSYS_GENERATOR_PORT1_PIN7_gc = (0x4F<<0), /* Port 1 Pin 7 */ + EVSYS_GENERATOR_USART0_XCK_gc = (0x60<<0), /* USART 0 Xclock */ + EVSYS_GENERATOR_USART1_XCK_gc = (0x61<<0), /* USART 1 Xclock */ + EVSYS_GENERATOR_USART2_XCK_gc = (0x62<<0), /* USART 2 Xclock */ + EVSYS_GENERATOR_USART3_XCK_gc = (0x63<<0), /* USART 3 Xclock */ + EVSYS_GENERATOR_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_GENERATOR_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_GENERATOR_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow (split mode) */ + EVSYS_GENERATOR_TCA0_CMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_GENERATOR_TCA0_CMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_GENERATOR_TCA0_CMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_GENERATOR_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_GENERATOR_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_GENERATOR_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_GENERATOR_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ +} EVSYS_GENERATOR_t; + +/* Software event on channels select */ +typedef enum EVSYS_STROBE0_enum +{ + EVSYS_STROBE0_EV_STROBE_CH0_gc = (0x01<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH1_gc = (0x02<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH2_gc = (0x04<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH3_gc = (0x08<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH4_gc = (0x10<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH5_gc = (0x20<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH6_gc = (0x40<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH7_gc = (0x80<<0), /* */ +} EVSYS_STROBE0_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<3), /* GPIO mode */ + RSTPINCFG_RST_gc = (0x01<<3), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock Bits */ + register8_t reserved_1[1]; +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t PORTCTRL; /* Port Control */ + register8_t reserved_1[5]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t EVSYSROUTEA; /* Port Multiplexer EVSYS */ + register8_t CCLROUTEA; /* Port Multiplexer CCL */ + register8_t USARTROUTEA; /* Port Multiplexer USART register A */ + register8_t TWISPIROUTEA; /* Port Multiplexer TWI and SPI */ + register8_t TCAROUTEA; /* Port Multiplexer TCA */ + register8_t TCBROUTEA; /* Port Multiplexer TCB */ + register8_t reserved_1[10]; +} PORTMUX_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<0), /* SPI0 on PA[7:4] */ + PORTMUX_SPI0_ALT1_gc = (0x01<<0), /* SPI0 on PC[3:0] */ + PORTMUX_SPI0_ALT2_gc = (0x02<<0), /* SPI0 on PE[3:0] */ + PORTMUX_SPI0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 select */ +typedef enum PORTMUX_TCA0_enum +{ + PORTMUX_TCA0_PORTA_gc = (0x00<<0), /* TCA0 pins on PA[5:0] */ + PORTMUX_TCA0_PORTB_gc = (0x01<<0), /* TCA0 pins on PB[5:0] */ + PORTMUX_TCA0_PORTC_gc = (0x02<<0), /* TCA0 pins on PC[5:0] */ + PORTMUX_TCA0_PORTD_gc = (0x03<<0), /* TCA0 pins on PD[5:0] */ + PORTMUX_TCA0_PORTE_gc = (0x04<<0), /* TCA0 pins on PE[5:0] */ + PORTMUX_TCA0_PORTF_gc = (0x05<<0), /* TCA0 pins on PF[5:0] */ +} PORTMUX_TCA0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* SCL/SDA on PA[3:2], Slave mode on PC[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT1_gc = (0x01<<4), /* SCL/SDA on PA[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT2_gc = (0x02<<4), /* SCL/SDA on PC[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* USART0 on PA[3:0] */ + PORTMUX_USART0_ALT1_gc = (0x01<<0), /* USART0 on PA[7:4] */ + PORTMUX_USART0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_USART0_t; + +/* Port Multiplexer USART1 select */ +typedef enum PORTMUX_USART1_enum +{ + PORTMUX_USART1_DEFAULT_gc = (0x00<<2), /* USART1 on PC[3:0] */ + PORTMUX_USART1_ALT1_gc = (0x01<<2), /* USART1 on PC[7:4] */ + PORTMUX_USART1_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_USART1_t; + +/* Port Multiplexer USART2 select */ +typedef enum PORTMUX_USART2_enum +{ + PORTMUX_USART2_DEFAULT_gc = (0x00<<4), /* USART2 on PF[3:0] */ + PORTMUX_USART2_ALT1_gc = (0x01<<4), /* USART2 on PF[6:4] */ + PORTMUX_USART2_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_USART2_t; + +/* Port Multiplexer USART3 select */ +typedef enum PORTMUX_USART3_enum +{ + PORTMUX_USART3_DEFAULT_gc = (0x00<<6), /* USART3 on PB[3:0] */ + PORTMUX_USART3_ALT1_gc = (0x01<<6), /* USART3 on PB[5:4] */ + PORTMUX_USART3_NONE_gc = (0x03<<6), /* Not connected to any pins */ +} PORTMUX_USART3_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t CALIB; /* Calibration */ + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_1[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_2[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_3[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[7]; + register8_t OSCCAL32K; /* Oscillator Calibration for 32kHz ULP */ + register8_t reserved_2[3]; + register8_t OSCCAL16M0; /* Oscillator Calibration 16 MHz Byte 0 */ + register8_t OSCCAL16M1; /* Oscillator Calibration 16 MHz Byte 1 */ + register8_t OSCCAL20M0; /* Oscillator Calibration 20 MHz Byte 0 */ + register8_t OSCCAL20M1; /* Oscillator Calibration 20 MHz Byte 1 */ + register8_t reserved_3[4]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_4[9]; + register8_t CHECKSUM1; /* CRC Checksum Byte 1 */ + register8_t reserved_5[16]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[21]; + register8_t OCDM; /* OCD Message Register */ + register8_t OCDMS; /* OCD Message Status */ + register8_t reserved_3[6]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t DUALCTRL; /* Dual Control */ + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_1[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t CTRLD; /* Control D */ + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_1[1]; +} USART_t; + +/* Auto Baud Window select */ +typedef enum USART_ABW_enum +{ + USART_ABW_WDW0_gc = (0x00<<6), /* 18% tolerance */ + USART_ABW_WDW1_gc = (0x01<<6), /* 15% tolerance */ + USART_ABW_WDW2_gc = (0x02<<6), /* 21% tolerance */ + USART_ABW_WDW3_gc = (0x03<<6), /* 25% tolerance */ +} USART_ABW_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ + register8_t USERROW32; /* User Row Byte 32 */ + register8_t USERROW33; /* User Row Byte 33 */ + register8_t USERROW34; /* User Row Byte 34 */ + register8_t USERROW35; /* User Row Byte 35 */ + register8_t USERROW36; /* User Row Byte 36 */ + register8_t USERROW37; /* User Row Byte 37 */ + register8_t USERROW38; /* User Row Byte 38 */ + register8_t USERROW39; /* User Row Byte 39 */ + register8_t USERROW40; /* User Row Byte 40 */ + register8_t USERROW41; /* User Row Byte 41 */ + register8_t USERROW42; /* User Row Byte 42 */ + register8_t USERROW43; /* User Row Byte 43 */ + register8_t USERROW44; /* User Row Byte 44 */ + register8_t USERROW45; /* User Row Byte 45 */ + register8_t USERROW46; /* User Row Byte 46 */ + register8_t USERROW47; /* User Row Byte 47 */ + register8_t USERROW48; /* User Row Byte 48 */ + register8_t USERROW49; /* User Row Byte 49 */ + register8_t USERROW50; /* User Row Byte 50 */ + register8_t USERROW51; /* User Row Byte 51 */ + register8_t USERROW52; /* User Row Byte 52 */ + register8_t USERROW53; /* User Row Byte 53 */ + register8_t USERROW54; /* User Row Byte 54 */ + register8_t USERROW55; /* User Row Byte 55 */ + register8_t USERROW56; /* User Row Byte 56 */ + register8_t USERROW57; /* User Row Byte 57 */ + register8_t USERROW58; /* User Row Byte 58 */ + register8_t USERROW59; /* User Row Byte 59 */ + register8_t USERROW60; /* User Row Byte 60 */ + register8_t USERROW61; /* User Row Byte 61 */ + register8_t USERROW62; /* User Row Byte 62 */ + register8_t USERROW63; /* User Row Byte 63 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* AC0 reference select select */ +typedef enum VREF_AC0REFSEL_enum +{ + VREF_AC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_AC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_AC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_AC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_AC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ + VREF_AC0REFSEL_AVDD_gc = (0x07<<0), /* AVDD as Voltage reference */ +} VREF_AC0REFSEL_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define VPORTD (*(VPORT_t *) 0x000C) /* Virtual Ports */ +#define VPORTE (*(VPORT_t *) 0x0010) /* Virtual Ports */ +#define VPORTF (*(VPORT_t *) 0x0014) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0460) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0480) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x04A0) /* I/O Ports */ +#define PORTMUX (*(PORTMUX_t *) 0x05E0) /* Port Multiplexer */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1 (*(USART_t *) 0x0820) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2 (*(USART_t *) 0x0840) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x08A0) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A80) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0A90) /* 16-bit Timer Type B */ +#define TCB2 (*(TCB_t *) 0x0AA0) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* VPORT (VPORTD) - Virtual Ports */ +#define VPORTD_DIR _SFR_MEM8(0x000C) +#define VPORTD_OUT _SFR_MEM8(0x000D) +#define VPORTD_IN _SFR_MEM8(0x000E) +#define VPORTD_INTFLAGS _SFR_MEM8(0x000F) + + +/* VPORT (VPORTE) - Virtual Ports */ +#define VPORTE_DIR _SFR_MEM8(0x0010) +#define VPORTE_OUT _SFR_MEM8(0x0011) +#define VPORTE_IN _SFR_MEM8(0x0012) +#define VPORTE_INTFLAGS _SFR_MEM8(0x0013) + + +/* VPORT (VPORTF) - Virtual Ports */ +#define VPORTF_DIR _SFR_MEM8(0x0014) +#define VPORTF_OUT _SFR_MEM8(0x0015) +#define VPORTF_IN _SFR_MEM8(0x0016) +#define VPORTF_INTFLAGS _SFR_MEM8(0x0017) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CALIB _SFR_MEM8(0x0146) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_STROBE _SFR_MEM8(0x0180) +#define EVSYS_CHANNEL0 _SFR_MEM8(0x0190) +#define EVSYS_CHANNEL1 _SFR_MEM8(0x0191) +#define EVSYS_CHANNEL2 _SFR_MEM8(0x0192) +#define EVSYS_CHANNEL3 _SFR_MEM8(0x0193) +#define EVSYS_CHANNEL4 _SFR_MEM8(0x0194) +#define EVSYS_CHANNEL5 _SFR_MEM8(0x0195) +#define EVSYS_USERCCLLUT0A _SFR_MEM8(0x01A0) +#define EVSYS_USERCCLLUT0B _SFR_MEM8(0x01A1) +#define EVSYS_USERCCLLUT1A _SFR_MEM8(0x01A2) +#define EVSYS_USERCCLLUT1B _SFR_MEM8(0x01A3) +#define EVSYS_USERCCLLUT2A _SFR_MEM8(0x01A4) +#define EVSYS_USERCCLLUT2B _SFR_MEM8(0x01A5) +#define EVSYS_USERCCLLUT3A _SFR_MEM8(0x01A6) +#define EVSYS_USERCCLLUT3B _SFR_MEM8(0x01A7) +#define EVSYS_USERADC0 _SFR_MEM8(0x01A8) +#define EVSYS_USEREVOUTA _SFR_MEM8(0x01A9) +#define EVSYS_USEREVOUTB _SFR_MEM8(0x01AA) +#define EVSYS_USEREVOUTC _SFR_MEM8(0x01AB) +#define EVSYS_USEREVOUTD _SFR_MEM8(0x01AC) +#define EVSYS_USEREVOUTE _SFR_MEM8(0x01AD) +#define EVSYS_USEREVOUTF _SFR_MEM8(0x01AE) +#define EVSYS_USERUSART0 _SFR_MEM8(0x01AF) +#define EVSYS_USERUSART1 _SFR_MEM8(0x01B0) +#define EVSYS_USERUSART2 _SFR_MEM8(0x01B1) +#define EVSYS_USERUSART3 _SFR_MEM8(0x01B2) +#define EVSYS_USERTCA0 _SFR_MEM8(0x01B3) +#define EVSYS_USERTCB0 _SFR_MEM8(0x01B4) +#define EVSYS_USERTCB1 _SFR_MEM8(0x01B5) +#define EVSYS_USERTCB2 _SFR_MEM8(0x01B6) +#define EVSYS_USERTCB3 _SFR_MEM8(0x01B7) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_SEQCTRL1 _SFR_MEM8(0x01C2) +#define CCL_INTCTRL0 _SFR_MEM8(0x01C5) +#define CCL_INTFLAGS _SFR_MEM8(0x01C7) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C8) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C9) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01CA) +#define CCL_TRUTH0 _SFR_MEM8(0x01CB) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01CC) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CD) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CE) +#define CCL_TRUTH1 _SFR_MEM8(0x01CF) +#define CCL_LUT2CTRLA _SFR_MEM8(0x01D0) +#define CCL_LUT2CTRLB _SFR_MEM8(0x01D1) +#define CCL_LUT2CTRLC _SFR_MEM8(0x01D2) +#define CCL_TRUTH2 _SFR_MEM8(0x01D3) +#define CCL_LUT3CTRLA _SFR_MEM8(0x01D4) +#define CCL_LUT3CTRLB _SFR_MEM8(0x01D5) +#define CCL_LUT3CTRLC _SFR_MEM8(0x01D6) +#define CCL_TRUTH3 _SFR_MEM8(0x01D7) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PORTCTRL _SFR_MEM8(0x040A) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PORTCTRL _SFR_MEM8(0x042A) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PORTCTRL _SFR_MEM8(0x044A) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* PORT (PORTD) - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0460) +#define PORTD_DIRSET _SFR_MEM8(0x0461) +#define PORTD_DIRCLR _SFR_MEM8(0x0462) +#define PORTD_DIRTGL _SFR_MEM8(0x0463) +#define PORTD_OUT _SFR_MEM8(0x0464) +#define PORTD_OUTSET _SFR_MEM8(0x0465) +#define PORTD_OUTCLR _SFR_MEM8(0x0466) +#define PORTD_OUTTGL _SFR_MEM8(0x0467) +#define PORTD_IN _SFR_MEM8(0x0468) +#define PORTD_INTFLAGS _SFR_MEM8(0x0469) +#define PORTD_PORTCTRL _SFR_MEM8(0x046A) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0470) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0471) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0472) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0473) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0474) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0475) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0476) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0477) + + +/* PORT (PORTE) - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0480) +#define PORTE_DIRSET _SFR_MEM8(0x0481) +#define PORTE_DIRCLR _SFR_MEM8(0x0482) +#define PORTE_DIRTGL _SFR_MEM8(0x0483) +#define PORTE_OUT _SFR_MEM8(0x0484) +#define PORTE_OUTSET _SFR_MEM8(0x0485) +#define PORTE_OUTCLR _SFR_MEM8(0x0486) +#define PORTE_OUTTGL _SFR_MEM8(0x0487) +#define PORTE_IN _SFR_MEM8(0x0488) +#define PORTE_INTFLAGS _SFR_MEM8(0x0489) +#define PORTE_PORTCTRL _SFR_MEM8(0x048A) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0490) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0491) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0492) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0493) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0494) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0495) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0496) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0497) + + +/* PORT (PORTF) - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x04A0) +#define PORTF_DIRSET _SFR_MEM8(0x04A1) +#define PORTF_DIRCLR _SFR_MEM8(0x04A2) +#define PORTF_DIRTGL _SFR_MEM8(0x04A3) +#define PORTF_OUT _SFR_MEM8(0x04A4) +#define PORTF_OUTSET _SFR_MEM8(0x04A5) +#define PORTF_OUTCLR _SFR_MEM8(0x04A6) +#define PORTF_OUTTGL _SFR_MEM8(0x04A7) +#define PORTF_IN _SFR_MEM8(0x04A8) +#define PORTF_INTFLAGS _SFR_MEM8(0x04A9) +#define PORTF_PORTCTRL _SFR_MEM8(0x04AA) +#define PORTF_PIN0CTRL _SFR_MEM8(0x04B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x04B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x04B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x04B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x04B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x04B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x04B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x04B7) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_EVSYSROUTEA _SFR_MEM8(0x05E0) +#define PORTMUX_CCLROUTEA _SFR_MEM8(0x05E1) +#define PORTMUX_USARTROUTEA _SFR_MEM8(0x05E2) +#define PORTMUX_TWISPIROUTEA _SFR_MEM8(0x05E3) +#define PORTMUX_TCAROUTEA _SFR_MEM8(0x05E4) +#define PORTMUX_TCBROUTEA _SFR_MEM8(0x05E5) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_DACREF _SFR_MEM8(0x0684) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_CTRLD _SFR_MEM8(0x080A) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* USART (USART1) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1_RXDATAL _SFR_MEM8(0x0820) +#define USART1_RXDATAH _SFR_MEM8(0x0821) +#define USART1_TXDATAL _SFR_MEM8(0x0822) +#define USART1_TXDATAH _SFR_MEM8(0x0823) +#define USART1_STATUS _SFR_MEM8(0x0824) +#define USART1_CTRLA _SFR_MEM8(0x0825) +#define USART1_CTRLB _SFR_MEM8(0x0826) +#define USART1_CTRLC _SFR_MEM8(0x0827) +#define USART1_BAUD _SFR_MEM16(0x0828) +#define USART1_BAUDL _SFR_MEM8(0x0828) +#define USART1_BAUDH _SFR_MEM8(0x0829) +#define USART1_CTRLD _SFR_MEM8(0x082A) +#define USART1_DBGCTRL _SFR_MEM8(0x082B) +#define USART1_EVCTRL _SFR_MEM8(0x082C) +#define USART1_TXPLCTRL _SFR_MEM8(0x082D) +#define USART1_RXPLCTRL _SFR_MEM8(0x082E) + + +/* USART (USART2) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2_RXDATAL _SFR_MEM8(0x0840) +#define USART2_RXDATAH _SFR_MEM8(0x0841) +#define USART2_TXDATAL _SFR_MEM8(0x0842) +#define USART2_TXDATAH _SFR_MEM8(0x0843) +#define USART2_STATUS _SFR_MEM8(0x0844) +#define USART2_CTRLA _SFR_MEM8(0x0845) +#define USART2_CTRLB _SFR_MEM8(0x0846) +#define USART2_CTRLC _SFR_MEM8(0x0847) +#define USART2_BAUD _SFR_MEM16(0x0848) +#define USART2_BAUDL _SFR_MEM8(0x0848) +#define USART2_BAUDH _SFR_MEM8(0x0849) +#define USART2_CTRLD _SFR_MEM8(0x084A) +#define USART2_DBGCTRL _SFR_MEM8(0x084B) +#define USART2_EVCTRL _SFR_MEM8(0x084C) +#define USART2_TXPLCTRL _SFR_MEM8(0x084D) +#define USART2_RXPLCTRL _SFR_MEM8(0x084E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x08A0) +#define TWI0_DUALCTRL _SFR_MEM8(0x08A1) +#define TWI0_DBGCTRL _SFR_MEM8(0x08A2) +#define TWI0_MCTRLA _SFR_MEM8(0x08A3) +#define TWI0_MCTRLB _SFR_MEM8(0x08A4) +#define TWI0_MSTATUS _SFR_MEM8(0x08A5) +#define TWI0_MBAUD _SFR_MEM8(0x08A6) +#define TWI0_MADDR _SFR_MEM8(0x08A7) +#define TWI0_MDATA _SFR_MEM8(0x08A8) +#define TWI0_SCTRLA _SFR_MEM8(0x08A9) +#define TWI0_SCTRLB _SFR_MEM8(0x08AA) +#define TWI0_SSTATUS _SFR_MEM8(0x08AB) +#define TWI0_SADDR _SFR_MEM8(0x08AC) +#define TWI0_SDATA _SFR_MEM8(0x08AD) +#define TWI0_SADDRMASK _SFR_MEM8(0x08AE) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x08C0) +#define SPI0_CTRLB _SFR_MEM8(0x08C1) +#define SPI0_INTCTRL _SFR_MEM8(0x08C2) +#define SPI0_INTFLAGS _SFR_MEM8(0x08C3) +#define SPI0_DATA _SFR_MEM8(0x08C4) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A80) +#define TCB0_CTRLB _SFR_MEM8(0x0A81) +#define TCB0_EVCTRL _SFR_MEM8(0x0A84) +#define TCB0_INTCTRL _SFR_MEM8(0x0A85) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A86) +#define TCB0_STATUS _SFR_MEM8(0x0A87) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A88) +#define TCB0_TEMP _SFR_MEM8(0x0A89) +#define TCB0_CNT _SFR_MEM16(0x0A8A) +#define TCB0_CNTL _SFR_MEM8(0x0A8A) +#define TCB0_CNTH _SFR_MEM8(0x0A8B) +#define TCB0_CCMP _SFR_MEM16(0x0A8C) +#define TCB0_CCMPL _SFR_MEM8(0x0A8C) +#define TCB0_CCMPH _SFR_MEM8(0x0A8D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0A90) +#define TCB1_CTRLB _SFR_MEM8(0x0A91) +#define TCB1_EVCTRL _SFR_MEM8(0x0A94) +#define TCB1_INTCTRL _SFR_MEM8(0x0A95) +#define TCB1_INTFLAGS _SFR_MEM8(0x0A96) +#define TCB1_STATUS _SFR_MEM8(0x0A97) +#define TCB1_DBGCTRL _SFR_MEM8(0x0A98) +#define TCB1_TEMP _SFR_MEM8(0x0A99) +#define TCB1_CNT _SFR_MEM16(0x0A9A) +#define TCB1_CNTL _SFR_MEM8(0x0A9A) +#define TCB1_CNTH _SFR_MEM8(0x0A9B) +#define TCB1_CCMP _SFR_MEM16(0x0A9C) +#define TCB1_CCMPL _SFR_MEM8(0x0A9C) +#define TCB1_CCMPH _SFR_MEM8(0x0A9D) + + +/* TCB (TCB2) - 16-bit Timer Type B */ +#define TCB2_CTRLA _SFR_MEM8(0x0AA0) +#define TCB2_CTRLB _SFR_MEM8(0x0AA1) +#define TCB2_EVCTRL _SFR_MEM8(0x0AA4) +#define TCB2_INTCTRL _SFR_MEM8(0x0AA5) +#define TCB2_INTFLAGS _SFR_MEM8(0x0AA6) +#define TCB2_STATUS _SFR_MEM8(0x0AA7) +#define TCB2_DBGCTRL _SFR_MEM8(0x0AA8) +#define TCB2_TEMP _SFR_MEM8(0x0AA9) +#define TCB2_CNT _SFR_MEM16(0x0AAA) +#define TCB2_CNTL _SFR_MEM8(0x0AAA) +#define TCB2_CNTH _SFR_MEM8(0x0AAB) +#define TCB2_CCMP _SFR_MEM16(0x0AAC) +#define TCB2_CCMPL _SFR_MEM8(0x0AAC) +#define TCB2_CCMPH _SFR_MEM8(0x0AAD) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) +#define SYSCFG_OCDM _SFR_MEM8(0x0F18) +#define SYSCFG_OCDMS _SFR_MEM8(0x0F19) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_OSCCAL32K _SFR_MEM8(0x1114) +#define SIGROW_OSCCAL16M0 _SFR_MEM8(0x1118) +#define SIGROW_OSCCAL16M1 _SFR_MEM8(0x1119) +#define SIGROW_OSCCAL20M0 _SFR_MEM8(0x111A) +#define SIGROW_OSCCAL20M1 _SFR_MEM8(0x111B) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) +#define SIGROW_CHECKSUM1 _SFR_MEM8(0x112F) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) +#define USERROW_USERROW32 _SFR_MEM8(0x1320) +#define USERROW_USERROW33 _SFR_MEM8(0x1321) +#define USERROW_USERROW34 _SFR_MEM8(0x1322) +#define USERROW_USERROW35 _SFR_MEM8(0x1323) +#define USERROW_USERROW36 _SFR_MEM8(0x1324) +#define USERROW_USERROW37 _SFR_MEM8(0x1325) +#define USERROW_USERROW38 _SFR_MEM8(0x1326) +#define USERROW_USERROW39 _SFR_MEM8(0x1327) +#define USERROW_USERROW40 _SFR_MEM8(0x1328) +#define USERROW_USERROW41 _SFR_MEM8(0x1329) +#define USERROW_USERROW42 _SFR_MEM8(0x132A) +#define USERROW_USERROW43 _SFR_MEM8(0x132B) +#define USERROW_USERROW44 _SFR_MEM8(0x132C) +#define USERROW_USERROW45 _SFR_MEM8(0x132D) +#define USERROW_USERROW46 _SFR_MEM8(0x132E) +#define USERROW_USERROW47 _SFR_MEM8(0x132F) +#define USERROW_USERROW48 _SFR_MEM8(0x1330) +#define USERROW_USERROW49 _SFR_MEM8(0x1331) +#define USERROW_USERROW50 _SFR_MEM8(0x1332) +#define USERROW_USERROW51 _SFR_MEM8(0x1333) +#define USERROW_USERROW52 _SFR_MEM8(0x1334) +#define USERROW_USERROW53 _SFR_MEM8(0x1335) +#define USERROW_USERROW54 _SFR_MEM8(0x1336) +#define USERROW_USERROW55 _SFR_MEM8(0x1337) +#define USERROW_USERROW56 _SFR_MEM8(0x1338) +#define USERROW_USERROW57 _SFR_MEM8(0x1339) +#define USERROW_USERROW58 _SFR_MEM8(0x133A) +#define USERROW_USERROW59 _SFR_MEM8(0x133B) +#define USERROW_USERROW60 _SFR_MEM8(0x133C) +#define USERROW_USERROW61 _SFR_MEM8(0x133D) +#define USERROW_USERROW62 _SFR_MEM8(0x133E) +#define USERROW_USERROW63 _SFR_MEM8(0x133F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.DACREF bit masks and bit positions */ +#define AC_DATA_gm 0xFF /* DAC voltage reference group mask. */ +#define AC_DATA_gp 0 /* DAC voltage reference group position. */ +#define AC_DATA0_bm (1<<0) /* DAC voltage reference bit 0 mask. */ +#define AC_DATA0_bp 0 /* DAC voltage reference bit 0 position. */ +#define AC_DATA1_bm (1<<1) /* DAC voltage reference bit 1 mask. */ +#define AC_DATA1_bp 1 /* DAC voltage reference bit 1 position. */ +#define AC_DATA2_bm (1<<2) /* DAC voltage reference bit 2 mask. */ +#define AC_DATA2_bp 2 /* DAC voltage reference bit 2 position. */ +#define AC_DATA3_bm (1<<3) /* DAC voltage reference bit 3 mask. */ +#define AC_DATA3_bp 3 /* DAC voltage reference bit 3 position. */ +#define AC_DATA4_bm (1<<4) /* DAC voltage reference bit 4 mask. */ +#define AC_DATA4_bp 4 /* DAC voltage reference bit 4 position. */ +#define AC_DATA5_bm (1<<5) /* DAC voltage reference bit 5 mask. */ +#define AC_DATA5_bp 5 /* DAC voltage reference bit 5 position. */ +#define AC_DATA6_bm (1<<6) /* DAC voltage reference bit 6 mask. */ +#define AC_DATA6_bp 6 /* DAC voltage reference bit 6 position. */ +#define AC_DATA7_bm (1<<7) /* DAC voltage reference bit 7 mask. */ +#define AC_DATA7_bp 7 /* DAC voltage reference bit 7 position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL0_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL0_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL00_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL00_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL01_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL01_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL02_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL02_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.SEQCTRL1 bit masks and bit positions */ +#define CCL_SEQSEL1_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL1_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL10_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL10_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL11_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL11_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL12_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL12_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.INTCTRL0 bit masks and bit positions */ +#define CCL_INTMODE0_gm 0x03 /* Interrupt Mode for LUT0 group mask. */ +#define CCL_INTMODE0_gp 0 /* Interrupt Mode for LUT0 group position. */ +#define CCL_INTMODE00_bm (1<<0) /* Interrupt Mode for LUT0 bit 0 mask. */ +#define CCL_INTMODE00_bp 0 /* Interrupt Mode for LUT0 bit 0 position. */ +#define CCL_INTMODE01_bm (1<<1) /* Interrupt Mode for LUT0 bit 1 mask. */ +#define CCL_INTMODE01_bp 1 /* Interrupt Mode for LUT0 bit 1 position. */ +#define CCL_INTMODE1_gm 0x0C /* Interrupt Mode for LUT1 group mask. */ +#define CCL_INTMODE1_gp 2 /* Interrupt Mode for LUT1 group position. */ +#define CCL_INTMODE10_bm (1<<2) /* Interrupt Mode for LUT1 bit 0 mask. */ +#define CCL_INTMODE10_bp 2 /* Interrupt Mode for LUT1 bit 0 position. */ +#define CCL_INTMODE11_bm (1<<3) /* Interrupt Mode for LUT1 bit 1 mask. */ +#define CCL_INTMODE11_bp 3 /* Interrupt Mode for LUT1 bit 1 position. */ +#define CCL_INTMODE2_gm 0x30 /* Interrupt Mode for LUT2 group mask. */ +#define CCL_INTMODE2_gp 4 /* Interrupt Mode for LUT2 group position. */ +#define CCL_INTMODE20_bm (1<<4) /* Interrupt Mode for LUT2 bit 0 mask. */ +#define CCL_INTMODE20_bp 4 /* Interrupt Mode for LUT2 bit 0 position. */ +#define CCL_INTMODE21_bm (1<<5) /* Interrupt Mode for LUT2 bit 1 mask. */ +#define CCL_INTMODE21_bp 5 /* Interrupt Mode for LUT2 bit 1 position. */ +#define CCL_INTMODE3_gm 0xC0 /* Interrupt Mode for LUT3 group mask. */ +#define CCL_INTMODE3_gp 6 /* Interrupt Mode for LUT3 group position. */ +#define CCL_INTMODE30_bm (1<<6) /* Interrupt Mode for LUT3 bit 0 mask. */ +#define CCL_INTMODE30_bp 6 /* Interrupt Mode for LUT3 bit 0 position. */ +#define CCL_INTMODE31_bm (1<<7) /* Interrupt Mode for LUT3 bit 1 mask. */ +#define CCL_INTMODE31_bp 7 /* Interrupt Mode for LUT3 bit 1 position. */ + +/* CCL.INTFLAGS bit masks and bit positions */ +#define CCL_INT_gm 0x0F /* Interrupt Flags group mask. */ +#define CCL_INT_gp 0 /* Interrupt Flags group position. */ +#define CCL_INT0_bm (1<<0) /* Interrupt Flags bit 0 mask. */ +#define CCL_INT0_bp 0 /* Interrupt Flags bit 0 position. */ +#define CCL_INT1_bm (1<<1) /* Interrupt Flags bit 1 mask. */ +#define CCL_INT1_bp 1 /* Interrupt Flags bit 1 position. */ +#define CCL_INT2_bm (1<<2) /* Interrupt Flags bit 2 mask. */ +#define CCL_INT2_bp 2 /* Interrupt Flags bit 2 position. */ +#define CCL_INT3_bm (1<<3) /* Interrupt Flags bit 3 mask. */ +#define CCL_INT3_bp 3 /* Interrupt Flags bit 3 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_CLKSRC_gm 0x0E /* Clock Source Selection group mask. */ +#define CCL_CLKSRC_gp 1 /* Clock Source Selection group position. */ +#define CCL_CLKSRC0_bm (1<<1) /* Clock Source Selection bit 0 mask. */ +#define CCL_CLKSRC0_bp 1 /* Clock Source Selection bit 0 position. */ +#define CCL_CLKSRC1_bm (1<<2) /* Clock Source Selection bit 1 mask. */ +#define CCL_CLKSRC1_bp 2 /* Clock Source Selection bit 1 position. */ +#define CCL_CLKSRC2_bm (1<<3) /* Clock Source Selection bit 2 mask. */ +#define CCL_CLKSRC2_bp 3 /* Clock Source Selection bit 2 position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_OUTEN_bm 0x40 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 6 /* Output Enable bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT2CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT2CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT2CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT3CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT3CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT3CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x7F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ +#define CLKCTRL_CAL20M6_bm (1<<6) /* Calibration bit 6 mask. */ +#define CLKCTRL_CAL20M6_bp 6 /* Calibration bit 6 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.STROBE bit masks and bit positions */ +#define EVSYS_STROBE0_gm 0xFF /* Software event on channels group mask. */ +#define EVSYS_STROBE0_gp 0 /* Software event on channels group position. */ +#define EVSYS_STROBE00_bm (1<<0) /* Software event on channels bit 0 mask. */ +#define EVSYS_STROBE00_bp 0 /* Software event on channels bit 0 position. */ +#define EVSYS_STROBE01_bm (1<<1) /* Software event on channels bit 1 mask. */ +#define EVSYS_STROBE01_bp 1 /* Software event on channels bit 1 position. */ +#define EVSYS_STROBE02_bm (1<<2) /* Software event on channels bit 2 mask. */ +#define EVSYS_STROBE02_bp 2 /* Software event on channels bit 2 position. */ +#define EVSYS_STROBE03_bm (1<<3) /* Software event on channels bit 3 mask. */ +#define EVSYS_STROBE03_bp 3 /* Software event on channels bit 3 position. */ +#define EVSYS_STROBE04_bm (1<<4) /* Software event on channels bit 4 mask. */ +#define EVSYS_STROBE04_bp 4 /* Software event on channels bit 4 position. */ +#define EVSYS_STROBE05_bm (1<<5) /* Software event on channels bit 5 mask. */ +#define EVSYS_STROBE05_bp 5 /* Software event on channels bit 5 position. */ +#define EVSYS_STROBE06_bm (1<<6) /* Software event on channels bit 6 mask. */ +#define EVSYS_STROBE06_bp 6 /* Software event on channels bit 6 position. */ +#define EVSYS_STROBE07_bm (1<<7) /* Software event on channels bit 7 mask. */ +#define EVSYS_STROBE07_bp 7 /* Software event on channels bit 7 position. */ + +/* EVSYS.CHANNEL0 bit masks and bit positions */ +#define EVSYS_GENERATOR_gm 0xFF /* Generator selector group mask. */ +#define EVSYS_GENERATOR_gp 0 /* Generator selector group position. */ +#define EVSYS_GENERATOR0_bm (1<<0) /* Generator selector bit 0 mask. */ +#define EVSYS_GENERATOR0_bp 0 /* Generator selector bit 0 position. */ +#define EVSYS_GENERATOR1_bm (1<<1) /* Generator selector bit 1 mask. */ +#define EVSYS_GENERATOR1_bp 1 /* Generator selector bit 1 position. */ +#define EVSYS_GENERATOR2_bm (1<<2) /* Generator selector bit 2 mask. */ +#define EVSYS_GENERATOR2_bp 2 /* Generator selector bit 2 position. */ +#define EVSYS_GENERATOR3_bm (1<<3) /* Generator selector bit 3 mask. */ +#define EVSYS_GENERATOR3_bp 3 /* Generator selector bit 3 position. */ +#define EVSYS_GENERATOR4_bm (1<<4) /* Generator selector bit 4 mask. */ +#define EVSYS_GENERATOR4_bp 4 /* Generator selector bit 4 position. */ +#define EVSYS_GENERATOR5_bm (1<<5) /* Generator selector bit 5 mask. */ +#define EVSYS_GENERATOR5_bp 5 /* Generator selector bit 5 position. */ +#define EVSYS_GENERATOR6_bm (1<<6) /* Generator selector bit 6 mask. */ +#define EVSYS_GENERATOR6_bp 6 /* Generator selector bit 6 position. */ +#define EVSYS_GENERATOR7_bm (1<<7) /* Generator selector bit 7 mask. */ +#define EVSYS_GENERATOR7_bp 7 /* Generator selector bit 7 position. */ + +/* EVSYS.CHANNEL1 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL2 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL3 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL4 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL5 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.USERCCLLUT0A bit masks and bit positions */ +#define EVSYS_CHANNEL_gm 0xFF /* Channel selector group mask. */ +#define EVSYS_CHANNEL_gp 0 /* Channel selector group position. */ +#define EVSYS_CHANNEL0_bm (1<<0) /* Channel selector bit 0 mask. */ +#define EVSYS_CHANNEL0_bp 0 /* Channel selector bit 0 position. */ +#define EVSYS_CHANNEL1_bm (1<<1) /* Channel selector bit 1 mask. */ +#define EVSYS_CHANNEL1_bp 1 /* Channel selector bit 1 position. */ +#define EVSYS_CHANNEL2_bm (1<<2) /* Channel selector bit 2 mask. */ +#define EVSYS_CHANNEL2_bp 2 /* Channel selector bit 2 position. */ +#define EVSYS_CHANNEL3_bm (1<<3) /* Channel selector bit 3 mask. */ +#define EVSYS_CHANNEL3_bp 3 /* Channel selector bit 3 position. */ +#define EVSYS_CHANNEL4_bm (1<<4) /* Channel selector bit 4 mask. */ +#define EVSYS_CHANNEL4_bp 4 /* Channel selector bit 4 position. */ +#define EVSYS_CHANNEL5_bm (1<<5) /* Channel selector bit 5 mask. */ +#define EVSYS_CHANNEL5_bp 5 /* Channel selector bit 5 position. */ +#define EVSYS_CHANNEL6_bm (1<<6) /* Channel selector bit 6 mask. */ +#define EVSYS_CHANNEL6_bp 6 /* Channel selector bit 6 position. */ +#define EVSYS_CHANNEL7_bm (1<<7) /* Channel selector bit 7 mask. */ +#define EVSYS_CHANNEL7_bp 7 /* Channel selector bit 7 position. */ + +/* EVSYS.USERCCLLUT0B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT1A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT1B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT2A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT2B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT3A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT3B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERADC0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTA bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTB bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTC bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTD bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTE bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTF bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART1 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART2 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART3 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCA0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB1 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB2 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB3 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_bm 0x08 /* Reset Pin Configuration bit mask. */ +#define FUSE_RSTPINCFG_bp 3 /* Reset Pin Configuration bit position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PORTCTRL bit masks and bit positions */ +#define PORT_SRL_bm 0x01 /* Slew Rate Limit Enable bit mask. */ +#define PORT_SRL_bp 0 /* Slew Rate Limit Enable bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.EVSYSROUTEA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_EVOUT3_bm 0x08 /* Event Output 3 bit mask. */ +#define PORTMUX_EVOUT3_bp 3 /* Event Output 3 bit position. */ +#define PORTMUX_EVOUT4_bm 0x10 /* Event Output 4 bit mask. */ +#define PORTMUX_EVOUT4_bp 4 /* Event Output 4 bit position. */ +#define PORTMUX_EVOUT5_bm 0x20 /* Event Output 5 bit mask. */ +#define PORTMUX_EVOUT5_bp 5 /* Event Output 5 bit position. */ + +/* PORTMUX.CCLROUTEA bit masks and bit positions */ +#define PORTMUX_LUT0_bm 0x01 /* CCL LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 0 /* CCL LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x02 /* CCL LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 1 /* CCL LUT1 bit position. */ +#define PORTMUX_LUT2_bm 0x04 /* CCL LUT2 bit mask. */ +#define PORTMUX_LUT2_bp 2 /* CCL LUT2 bit position. */ +#define PORTMUX_LUT3_bm 0x08 /* CCL LUT3 bit mask. */ +#define PORTMUX_LUT3_bp 3 /* CCL LUT3 bit position. */ + +/* PORTMUX.USARTROUTEA bit masks and bit positions */ +#define PORTMUX_USART0_gm 0x03 /* Port Multiplexer USART0 group mask. */ +#define PORTMUX_USART0_gp 0 /* Port Multiplexer USART0 group position. */ +#define PORTMUX_USART00_bm (1<<0) /* Port Multiplexer USART0 bit 0 mask. */ +#define PORTMUX_USART00_bp 0 /* Port Multiplexer USART0 bit 0 position. */ +#define PORTMUX_USART01_bm (1<<1) /* Port Multiplexer USART0 bit 1 mask. */ +#define PORTMUX_USART01_bp 1 /* Port Multiplexer USART0 bit 1 position. */ +#define PORTMUX_USART1_gm 0x0C /* Port Multiplexer USART1 group mask. */ +#define PORTMUX_USART1_gp 2 /* Port Multiplexer USART1 group position. */ +#define PORTMUX_USART10_bm (1<<2) /* Port Multiplexer USART1 bit 0 mask. */ +#define PORTMUX_USART10_bp 2 /* Port Multiplexer USART1 bit 0 position. */ +#define PORTMUX_USART11_bm (1<<3) /* Port Multiplexer USART1 bit 1 mask. */ +#define PORTMUX_USART11_bp 3 /* Port Multiplexer USART1 bit 1 position. */ +#define PORTMUX_USART2_gm 0x30 /* Port Multiplexer USART2 group mask. */ +#define PORTMUX_USART2_gp 4 /* Port Multiplexer USART2 group position. */ +#define PORTMUX_USART20_bm (1<<4) /* Port Multiplexer USART2 bit 0 mask. */ +#define PORTMUX_USART20_bp 4 /* Port Multiplexer USART2 bit 0 position. */ +#define PORTMUX_USART21_bm (1<<5) /* Port Multiplexer USART2 bit 1 mask. */ +#define PORTMUX_USART21_bp 5 /* Port Multiplexer USART2 bit 1 position. */ +#define PORTMUX_USART3_gm 0xC0 /* Port Multiplexer USART3 group mask. */ +#define PORTMUX_USART3_gp 6 /* Port Multiplexer USART3 group position. */ +#define PORTMUX_USART30_bm (1<<6) /* Port Multiplexer USART3 bit 0 mask. */ +#define PORTMUX_USART30_bp 6 /* Port Multiplexer USART3 bit 0 position. */ +#define PORTMUX_USART31_bm (1<<7) /* Port Multiplexer USART3 bit 1 mask. */ +#define PORTMUX_USART31_bp 7 /* Port Multiplexer USART3 bit 1 position. */ + +/* PORTMUX.TWISPIROUTEA bit masks and bit positions */ +#define PORTMUX_SPI0_gm 0x03 /* Port Multiplexer SPI0 group mask. */ +#define PORTMUX_SPI0_gp 0 /* Port Multiplexer SPI0 group position. */ +#define PORTMUX_SPI00_bm (1<<0) /* Port Multiplexer SPI0 bit 0 mask. */ +#define PORTMUX_SPI00_bp 0 /* Port Multiplexer SPI0 bit 0 position. */ +#define PORTMUX_SPI01_bm (1<<1) /* Port Multiplexer SPI0 bit 1 mask. */ +#define PORTMUX_SPI01_bp 1 /* Port Multiplexer SPI0 bit 1 position. */ +#define PORTMUX_TWI0_gm 0x30 /* Port Multiplexer TWI0 group mask. */ +#define PORTMUX_TWI0_gp 4 /* Port Multiplexer TWI0 group position. */ +#define PORTMUX_TWI00_bm (1<<4) /* Port Multiplexer TWI0 bit 0 mask. */ +#define PORTMUX_TWI00_bp 4 /* Port Multiplexer TWI0 bit 0 position. */ +#define PORTMUX_TWI01_bm (1<<5) /* Port Multiplexer TWI0 bit 1 mask. */ +#define PORTMUX_TWI01_bp 5 /* Port Multiplexer TWI0 bit 1 position. */ + +/* PORTMUX.TCAROUTEA bit masks and bit positions */ +#define PORTMUX_TCA0_gm 0x07 /* Port Multiplexer TCA0 group mask. */ +#define PORTMUX_TCA0_gp 0 /* Port Multiplexer TCA0 group position. */ +#define PORTMUX_TCA00_bm (1<<0) /* Port Multiplexer TCA0 bit 0 mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 bit 0 position. */ +#define PORTMUX_TCA01_bm (1<<1) /* Port Multiplexer TCA0 bit 1 mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 bit 1 position. */ +#define PORTMUX_TCA02_bm (1<<2) /* Port Multiplexer TCA0 bit 2 mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 bit 2 position. */ + +/* PORTMUX.TCBROUTEA bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ +#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ +#define PORTMUX_TCB2_bm 0x04 /* Port Multiplexer TCB2 bit mask. */ +#define PORTMUX_TCB2_bp 2 /* Port Multiplexer TCB2 bit position. */ +#define PORTMUX_TCB3_bm 0x08 /* Port Multiplexer TCB3 bit mask. */ +#define PORTMUX_TCB3_bp 3 /* Port Multiplexer TCB3 bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_CORREN_bm 0x04 /* Correction enable bit mask. */ +#define RTC_CORREN_bp 2 /* Correction enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_ERROR_gm 0x7F /* Error Correction Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Correction Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Correction Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Correction Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Correction Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Correction Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Correction Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Correction Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Correction Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Correction Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Correction Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Correction Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Correction Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Correction Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Correction Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Correction Value bit 6 position. */ +#define RTC_SIGN_bm 0x80 /* Error Correction Sign Bit bit mask. */ +#define RTC_SIGN_bp 7 /* Error Correction Sign Bit bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + + +/* SYSCFG.OCDMS bit masks and bit positions */ +#define SYSCFG_OCDMR_bm 0x01 /* OCD Message Read bit mask. */ +#define SYSCFG_OCDMR_bp 0 /* OCD Message Read bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DUALCTRL bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Dual Control Enable bit mask. */ +#define TWI_ENABLE_bp 0 /* Dual Control Enable bit position. */ +/* TWI_FMPEN is already defined. */ +/* TWI_SDAHOLD is already defined. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.CTRLD bit masks and bit positions */ +#define USART_ABW_gm 0xC0 /* Auto Baud Window group mask. */ +#define USART_ABW_gp 6 /* Auto Baud Window group position. */ +#define USART_ABW0_bm (1<<6) /* Auto Baud Window bit 0 mask. */ +#define USART_ABW0_bp 6 /* Auto Baud Window bit 0 position. */ +#define USART_ABW1_bm (1<<7) /* Auto Baud Window bit 1 mask. */ +#define USART_ABW1_bp 7 /* Auto Baud Window bit 1 position. */ + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_AC0REFSEL_gm 0x07 /* AC0 reference select group mask. */ +#define VREF_AC0REFSEL_gp 0 /* AC0 reference select group position. */ +#define VREF_AC0REFSEL0_bm (1<<0) /* AC0 reference select bit 0 mask. */ +#define VREF_AC0REFSEL0_bp 0 /* AC0 reference select bit 0 position. */ +#define VREF_AC0REFSEL1_bm (1<<1) /* AC0 reference select bit 1 mask. */ +#define VREF_AC0REFSEL1_bp 1 /* AC0 reference select bit 1 position. */ +#define VREF_AC0REFSEL2_bm (1<<2) /* AC0 reference select bit 2 mask. */ +#define VREF_AC0REFSEL2_bp 2 /* AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_AC0REFEN_bm 0x01 /* AC0 DACREF reference enable bit mask. */ +#define VREF_AC0REFEN_bp 0 /* AC0 DACREF reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 3 +#define RTC_CNT_vect _VECTOR(3) /* */ +#define RTC_PIT_vect_num 4 +#define RTC_PIT_vect _VECTOR(4) /* */ + +/* CCL interrupt vectors */ +#define CCL_CCL_vect_num 5 +#define CCL_CCL_vect _VECTOR(5) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 6 +#define PORTA_PORT_vect _VECTOR(6) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 7 +#define TCA0_LUNF_vect _VECTOR(7) /* */ +#define TCA0_OVF_vect_num 7 +#define TCA0_OVF_vect _VECTOR(7) /* */ +#define TCA0_HUNF_vect_num 8 +#define TCA0_HUNF_vect _VECTOR(8) /* */ +#define TCA0_CMP0_vect_num 9 +#define TCA0_CMP0_vect _VECTOR(9) /* */ +#define TCA0_LCMP0_vect_num 9 +#define TCA0_LCMP0_vect _VECTOR(9) /* */ +#define TCA0_CMP1_vect_num 10 +#define TCA0_CMP1_vect _VECTOR(10) /* */ +#define TCA0_LCMP1_vect_num 10 +#define TCA0_LCMP1_vect _VECTOR(10) /* */ +#define TCA0_CMP2_vect_num 11 +#define TCA0_CMP2_vect _VECTOR(11) /* */ +#define TCA0_LCMP2_vect_num 11 +#define TCA0_LCMP2_vect _VECTOR(11) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 12 +#define TCB0_INT_vect _VECTOR(12) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 13 +#define TCB1_INT_vect _VECTOR(13) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 14 +#define TWI0_TWIS_vect _VECTOR(14) /* */ +#define TWI0_TWIM_vect_num 15 +#define TWI0_TWIM_vect _VECTOR(15) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 16 +#define SPI0_INT_vect _VECTOR(16) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 17 +#define USART0_RXC_vect _VECTOR(17) /* */ +#define USART0_DRE_vect_num 18 +#define USART0_DRE_vect _VECTOR(18) /* */ +#define USART0_TXC_vect_num 19 +#define USART0_TXC_vect _VECTOR(19) /* */ + +/* PORTD interrupt vectors */ +#define PORTD_PORT_vect_num 20 +#define PORTD_PORT_vect _VECTOR(20) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 21 +#define AC0_AC_vect _VECTOR(21) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 22 +#define ADC0_RESRDY_vect _VECTOR(22) /* */ +#define ADC0_WCOMP_vect_num 23 +#define ADC0_WCOMP_vect _VECTOR(23) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 24 +#define PORTC_PORT_vect _VECTOR(24) /* */ + +/* TCB2 interrupt vectors */ +#define TCB2_INT_vect_num 25 +#define TCB2_INT_vect _VECTOR(25) /* */ + +/* USART1 interrupt vectors */ +#define USART1_RXC_vect_num 26 +#define USART1_RXC_vect _VECTOR(26) /* */ +#define USART1_DRE_vect_num 27 +#define USART1_DRE_vect _VECTOR(27) /* */ +#define USART1_TXC_vect_num 28 +#define USART1_TXC_vect _VECTOR(28) /* */ + +/* PORTF interrupt vectors */ +#define PORTF_PORT_vect_num 29 +#define PORTF_PORT_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +/* USART2 interrupt vectors */ +#define USART2_RXC_vect_num 31 +#define USART2_RXC_vect _VECTOR(31) /* */ +#define USART2_DRE_vect_num 32 +#define USART2_DRE_vect _VECTOR(32) /* */ +#define USART2_TXC_vect_num 33 +#define USART2_TXC_vect _VECTOR(33) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 34 +#define PORTB_PORT_vect _VECTOR(34) /* */ + +/* PORTE interrupt vectors */ +#define PORTE_PORT_vect_num 35 +#define PORTE_PORT_vect _VECTOR(35) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (36 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (16384) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (16384U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3800) +# define INTERNAL_SRAM_SIZE (2048) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3800U) +# define INTERNAL_SRAM_SIZE (2048U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x4000) +# define MAPPED_PROGMEM_SIZE (16384) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x4000U) +# define MAPPED_PROGMEM_SIZE (16384U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (16384) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (16384U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG (unsigned char)_BV(3) /* Reset Pin Configuration */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x27 + + +#endif /* #ifdef _AVR_ATMEGA1608_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iom1609.h b/hardware/tools/avr/avr/include/avr/iom1609.h new file mode 100644 index 0000000000000000000000000000000000000000..400d90d5d805b8f345d966110bb0c7e75e84f911 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom1609.h @@ -0,0 +1,5017 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom1609.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATMEGA1609_H_INCLUDED +#define _AVR_ATMEGA1609_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[1]; + register8_t DACREF; /* Referance scale control */ + register8_t reserved_3[1]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_PIN2_gc = (0x02<<0), /* Negative Pin 2 */ + AC_MUXNEG_DACREF_gc = (0x03<<0), /* DAC Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ + ADC_MUXPOS_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ + ADC_MUXPOS_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ + ADC_MUXPOS_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ + ADC_MUXPOS_DACREF_gc = (0x1C<<0), /* AC DAC Reference */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temperature sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* 0V (GND) */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t SEQCTRL1; /* Sequential Control 1 */ + register8_t reserved_1[2]; + register8_t INTCTRL0; /* Interrupt Control 0 */ + register8_t reserved_2[1]; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t LUT2CTRLA; /* LUT Control 2 A */ + register8_t LUT2CTRLB; /* LUT Control 2 B */ + register8_t LUT2CTRLC; /* LUT Control 2 C */ + register8_t TRUTH2; /* Truth 2 */ + register8_t LUT3CTRLA; /* LUT Control 3 A */ + register8_t LUT3CTRLB; /* LUT Control 3 B */ + register8_t LUT3CTRLC; /* LUT Control 3 C */ + register8_t TRUTH3; /* Truth 3 */ + register8_t reserved_3[40]; +} CCL_t; + +/* Clock Source Selection select */ +typedef enum CCL_CLKSRC_enum +{ + CCL_CLKSRC_CLKPER_gc = (0x00<<1), /* CLK_PER is clocking the LUT */ + CCL_CLKSRC_IN2_gc = (0x01<<1), /* IN[2] is clocking the LUT */ + CCL_CLKSRC_OSC20M_gc = (0x04<<1), /* 20MHz oscillator before prescaler is clocking the LUT */ + CCL_CLKSRC_OSCULP32K_gc = (0x05<<1), /* 32kHz oscillator is clocking the LUT */ + CCL_CLKSRC_OSCULP1K_gc = (0x06<<1), /* 32kHz oscillator after DIV32 is clocking the LUT */ +} CCL_CLKSRC_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL0_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_USART0_gc = (0x08<<0), /* USART0 TXD input source */ + CCL_INSEL0_SPI0_gc = (0x09<<0), /* SPI0 MOSI input source */ + CCL_INSEL0_TCA0_gc = (0x0A<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCB0_gc = (0x0C<<0), /* TCB0 WO input source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENTA_gc = (0x03<<4), /* Event input source A */ + CCL_INSEL1_EVENTB_gc = (0x04<<4), /* Event input source B */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_USART1_gc = (0x08<<4), /* USART1 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x09<<4), /* SPI0 MOSI input source */ + CCL_INSEL1_TCA0_gc = (0x0A<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCB1_gc = (0x0C<<4), /* TCB1 WO input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL2_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_USART2_gc = (0x08<<0), /* USART2 TXD input source */ + CCL_INSEL2_SPI0_gc = (0x09<<0), /* SPI0 SCK input source */ + CCL_INSEL2_TCA0_gc = (0x0A<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCB2_gc = (0x0C<<0), /* TCB2 WO input source */ +} CCL_INSEL2_t; + +/* Interrupt Mode for LUT0 select */ +typedef enum CCL_INTMODE0_enum +{ + CCL_INTMODE0_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled */ + CCL_INTMODE0_RISING_gc = (0x01<<0), /* Sense rising edge */ + CCL_INTMODE0_FALLING_gc = (0x02<<0), /* Sense falling edge */ + CCL_INTMODE0_BOTH_gc = (0x03<<0), /* Sense both edges */ +} CCL_INTMODE0_t; + +/* Interrupt Mode for LUT1 select */ +typedef enum CCL_INTMODE1_enum +{ + CCL_INTMODE1_INTDISABLE_gc = (0x00<<2), /* Interrupt disabled */ + CCL_INTMODE1_RISING_gc = (0x01<<2), /* Sense rising edge */ + CCL_INTMODE1_FALLING_gc = (0x02<<2), /* Sense falling edge */ + CCL_INTMODE1_BOTH_gc = (0x03<<2), /* Sense both edges */ +} CCL_INTMODE1_t; + +/* Interrupt Mode for LUT2 select */ +typedef enum CCL_INTMODE2_enum +{ + CCL_INTMODE2_INTDISABLE_gc = (0x00<<4), /* Interrupt disabled */ + CCL_INTMODE2_RISING_gc = (0x01<<4), /* Sense rising edge */ + CCL_INTMODE2_FALLING_gc = (0x02<<4), /* Sense falling edge */ + CCL_INTMODE2_BOTH_gc = (0x03<<4), /* Sense both edges */ +} CCL_INTMODE2_t; + +/* Interrupt Mode for LUT3 select */ +typedef enum CCL_INTMODE3_enum +{ + CCL_INTMODE3_INTDISABLE_gc = (0x00<<6), /* Interrupt disabled */ + CCL_INTMODE3_RISING_gc = (0x01<<6), /* Sense rising edge */ + CCL_INTMODE3_FALLING_gc = (0x02<<6), /* Sense falling edge */ + CCL_INTMODE3_BOTH_gc = (0x03<<6), /* Sense both edges */ +} CCL_INTMODE3_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL0_enum +{ + CCL_SEQSEL0_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL0_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL0_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL0_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL0_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL0_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL1_enum +{ + CCL_SEQSEL1_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL1_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL1_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL1_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL1_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL1_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1k cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16k cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32k cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t STROBE; /* Channel Strobe */ + register8_t reserved_1[15]; + register8_t CHANNEL0; /* Multiplexer Channel 0 */ + register8_t CHANNEL1; /* Multiplexer Channel 1 */ + register8_t CHANNEL2; /* Multiplexer Channel 2 */ + register8_t CHANNEL3; /* Multiplexer Channel 3 */ + register8_t CHANNEL4; /* Multiplexer Channel 4 */ + register8_t CHANNEL5; /* Multiplexer Channel 5 */ + register8_t CHANNEL6; /* Multiplexer Channel 6 */ + register8_t CHANNEL7; /* Multiplexer Channel 7 */ + register8_t reserved_2[8]; + register8_t USERCCLLUT0A; /* User CCL LUT0 Event A */ + register8_t USERCCLLUT0B; /* User CCL LUT0 Event B */ + register8_t USERCCLLUT1A; /* User CCL LUT1 Event A */ + register8_t USERCCLLUT1B; /* User CCL LUT1 Event B */ + register8_t USERCCLLUT2A; /* User CCL LUT2 Event A */ + register8_t USERCCLLUT2B; /* User CCL LUT2 Event B */ + register8_t USERCCLLUT3A; /* User CCL LUT3 Event A */ + register8_t USERCCLLUT3B; /* User CCL LUT3 Event B */ + register8_t USERADC0; /* User ADC0 */ + register8_t USEREVOUTA; /* User EVOUT Port A */ + register8_t USEREVOUTB; /* User EVOUT Port B */ + register8_t USEREVOUTC; /* User EVOUT Port C */ + register8_t USEREVOUTD; /* User EVOUT Port D */ + register8_t USEREVOUTE; /* User EVOUT Port E */ + register8_t USEREVOUTF; /* User EVOUT Port F */ + register8_t USERUSART0; /* User USART0 */ + register8_t USERUSART1; /* User USART1 */ + register8_t USERUSART2; /* User USART2 */ + register8_t USERUSART3; /* User USART3 */ + register8_t USERTCA0; /* User TCA0 */ + register8_t USERTCB0; /* User TCB0 */ + register8_t USERTCB1; /* User TCB1 */ + register8_t USERTCB2; /* User TCB2 */ + register8_t USERTCB3; /* User TCB3 */ + register8_t reserved_3[8]; +} EVSYS_t; + +/* Channel selector select */ +typedef enum EVSYS_CHANNEL_enum +{ + EVSYS_CHANNEL_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL_CHANNEL0_gc = (0x01<<0), /* Connect user to event channel 0 */ + EVSYS_CHANNEL_CHANNEL1_gc = (0x02<<0), /* Connect user to event channel 1 */ + EVSYS_CHANNEL_CHANNEL2_gc = (0x03<<0), /* Connect user to event channel 2 */ + EVSYS_CHANNEL_CHANNEL3_gc = (0x04<<0), /* Connect user to event channel 3 */ + EVSYS_CHANNEL_CHANNEL4_gc = (0x05<<0), /* Connect user to event channel 4 */ + EVSYS_CHANNEL_CHANNEL5_gc = (0x06<<0), /* Connect user to event channel 5 */ + EVSYS_CHANNEL_CHANNEL6_gc = (0x07<<0), /* Connect user to event channel 6 */ + EVSYS_CHANNEL_CHANNEL7_gc = (0x08<<0), /* Connect user to event channel 7 */ +} EVSYS_CHANNEL_t; + +/* Generator selector select */ +typedef enum EVSYS_GENERATOR_enum +{ + EVSYS_GENERATOR_OFF_gc = (0x00<<0), /* Off */ + EVSYS_GENERATOR_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_GENERATOR_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_GENERATOR_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_GENERATOR_RTC_PIT0_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_GENERATOR_RTC_PIT1_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_GENERATOR_RTC_PIT2_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_GENERATOR_RTC_PIT3_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_GENERATOR_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_GENERATOR_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_GENERATOR_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_GENERATOR_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_GENERATOR_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_GENERATOR_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready Event */ + EVSYS_GENERATOR_PORT0_PIN0_gc = (0x40<<0), /* Port 0 Pin 0 */ + EVSYS_GENERATOR_PORT0_PIN1_gc = (0x41<<0), /* Port 0 Pin 1 */ + EVSYS_GENERATOR_PORT0_PIN2_gc = (0x42<<0), /* Port 0 Pin 2 */ + EVSYS_GENERATOR_PORT0_PIN3_gc = (0x43<<0), /* Port 0 Pin 3 */ + EVSYS_GENERATOR_PORT0_PIN4_gc = (0x44<<0), /* Port 0 Pin 4 */ + EVSYS_GENERATOR_PORT0_PIN5_gc = (0x45<<0), /* Port 0 Pin 5 */ + EVSYS_GENERATOR_PORT0_PIN6_gc = (0x46<<0), /* Port 0 Pin 6 */ + EVSYS_GENERATOR_PORT0_PIN7_gc = (0x47<<0), /* Port 0 Pin 7 */ + EVSYS_GENERATOR_PORT1_PIN0_gc = (0x48<<0), /* Port 1 Pin 0 */ + EVSYS_GENERATOR_PORT1_PIN1_gc = (0x49<<0), /* Port 1 Pin 1 */ + EVSYS_GENERATOR_PORT1_PIN2_gc = (0x4A<<0), /* Port 1 Pin 2 */ + EVSYS_GENERATOR_PORT1_PIN3_gc = (0x4B<<0), /* Port 1 Pin 3 */ + EVSYS_GENERATOR_PORT1_PIN4_gc = (0x4C<<0), /* Port 1 Pin 4 */ + EVSYS_GENERATOR_PORT1_PIN5_gc = (0x4D<<0), /* Port 1 Pin 5 */ + EVSYS_GENERATOR_PORT1_PIN6_gc = (0x4E<<0), /* Port 1 Pin 6 */ + EVSYS_GENERATOR_PORT1_PIN7_gc = (0x4F<<0), /* Port 1 Pin 7 */ + EVSYS_GENERATOR_USART0_XCK_gc = (0x60<<0), /* USART 0 Xclock */ + EVSYS_GENERATOR_USART1_XCK_gc = (0x61<<0), /* USART 1 Xclock */ + EVSYS_GENERATOR_USART2_XCK_gc = (0x62<<0), /* USART 2 Xclock */ + EVSYS_GENERATOR_USART3_XCK_gc = (0x63<<0), /* USART 3 Xclock */ + EVSYS_GENERATOR_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_GENERATOR_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_GENERATOR_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow (split mode) */ + EVSYS_GENERATOR_TCA0_CMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_GENERATOR_TCA0_CMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_GENERATOR_TCA0_CMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_GENERATOR_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_GENERATOR_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_GENERATOR_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_GENERATOR_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ +} EVSYS_GENERATOR_t; + +/* Software event on channels select */ +typedef enum EVSYS_STROBE0_enum +{ + EVSYS_STROBE0_EV_STROBE_CH0_gc = (0x01<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH1_gc = (0x02<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH2_gc = (0x04<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH3_gc = (0x08<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH4_gc = (0x10<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH5_gc = (0x20<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH6_gc = (0x40<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH7_gc = (0x80<<0), /* */ +} EVSYS_STROBE0_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<3), /* GPIO mode */ + RSTPINCFG_RST_gc = (0x01<<3), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock Bits */ + register8_t reserved_1[1]; +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t PORTCTRL; /* Port Control */ + register8_t reserved_1[5]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t EVSYSROUTEA; /* Port Multiplexer EVSYS */ + register8_t CCLROUTEA; /* Port Multiplexer CCL */ + register8_t USARTROUTEA; /* Port Multiplexer USART register A */ + register8_t TWISPIROUTEA; /* Port Multiplexer TWI and SPI */ + register8_t TCAROUTEA; /* Port Multiplexer TCA */ + register8_t TCBROUTEA; /* Port Multiplexer TCB */ + register8_t reserved_1[10]; +} PORTMUX_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<0), /* SPI0 on PA[7:4] */ + PORTMUX_SPI0_ALT1_gc = (0x01<<0), /* SPI0 on PC[3:0] */ + PORTMUX_SPI0_ALT2_gc = (0x02<<0), /* SPI0 on PE[3:0] */ + PORTMUX_SPI0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 select */ +typedef enum PORTMUX_TCA0_enum +{ + PORTMUX_TCA0_PORTA_gc = (0x00<<0), /* TCA0 pins on PA[5:0] */ + PORTMUX_TCA0_PORTB_gc = (0x01<<0), /* TCA0 pins on PB[5:0] */ + PORTMUX_TCA0_PORTC_gc = (0x02<<0), /* TCA0 pins on PC[5:0] */ + PORTMUX_TCA0_PORTD_gc = (0x03<<0), /* TCA0 pins on PD[5:0] */ + PORTMUX_TCA0_PORTE_gc = (0x04<<0), /* TCA0 pins on PE[5:0] */ + PORTMUX_TCA0_PORTF_gc = (0x05<<0), /* TCA0 pins on PF[5:0] */ +} PORTMUX_TCA0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* SCL/SDA on PA[3:2], Slave mode on PC[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT1_gc = (0x01<<4), /* SCL/SDA on PA[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT2_gc = (0x02<<4), /* SCL/SDA on PC[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* USART0 on PA[3:0] */ + PORTMUX_USART0_ALT1_gc = (0x01<<0), /* USART0 on PA[7:4] */ + PORTMUX_USART0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_USART0_t; + +/* Port Multiplexer USART1 select */ +typedef enum PORTMUX_USART1_enum +{ + PORTMUX_USART1_DEFAULT_gc = (0x00<<2), /* USART1 on PC[3:0] */ + PORTMUX_USART1_ALT1_gc = (0x01<<2), /* USART1 on PC[7:4] */ + PORTMUX_USART1_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_USART1_t; + +/* Port Multiplexer USART2 select */ +typedef enum PORTMUX_USART2_enum +{ + PORTMUX_USART2_DEFAULT_gc = (0x00<<4), /* USART2 on PF[3:0] */ + PORTMUX_USART2_ALT1_gc = (0x01<<4), /* USART2 on PF[6:4] */ + PORTMUX_USART2_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_USART2_t; + +/* Port Multiplexer USART3 select */ +typedef enum PORTMUX_USART3_enum +{ + PORTMUX_USART3_DEFAULT_gc = (0x00<<6), /* USART3 on PB[3:0] */ + PORTMUX_USART3_ALT1_gc = (0x01<<6), /* USART3 on PB[5:4] */ + PORTMUX_USART3_NONE_gc = (0x03<<6), /* Not connected to any pins */ +} PORTMUX_USART3_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t CALIB; /* Calibration */ + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_1[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_2[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_3[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[7]; + register8_t OSCCAL32K; /* Oscillator Calibration for 32kHz ULP */ + register8_t reserved_2[3]; + register8_t OSCCAL16M0; /* Oscillator Calibration 16 MHz Byte 0 */ + register8_t OSCCAL16M1; /* Oscillator Calibration 16 MHz Byte 1 */ + register8_t OSCCAL20M0; /* Oscillator Calibration 20 MHz Byte 0 */ + register8_t OSCCAL20M1; /* Oscillator Calibration 20 MHz Byte 1 */ + register8_t reserved_3[4]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_4[9]; + register8_t CHECKSUM1; /* CRC Checksum Byte 1 */ + register8_t reserved_5[16]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[21]; + register8_t OCDM; /* OCD Message Register */ + register8_t OCDMS; /* OCD Message Status */ + register8_t reserved_3[6]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t DUALCTRL; /* Dual Control */ + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_1[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t CTRLD; /* Control D */ + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_1[1]; +} USART_t; + +/* Auto Baud Window select */ +typedef enum USART_ABW_enum +{ + USART_ABW_WDW0_gc = (0x00<<6), /* 18% tolerance */ + USART_ABW_WDW1_gc = (0x01<<6), /* 15% tolerance */ + USART_ABW_WDW2_gc = (0x02<<6), /* 21% tolerance */ + USART_ABW_WDW3_gc = (0x03<<6), /* 25% tolerance */ +} USART_ABW_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ + register8_t USERROW32; /* User Row Byte 32 */ + register8_t USERROW33; /* User Row Byte 33 */ + register8_t USERROW34; /* User Row Byte 34 */ + register8_t USERROW35; /* User Row Byte 35 */ + register8_t USERROW36; /* User Row Byte 36 */ + register8_t USERROW37; /* User Row Byte 37 */ + register8_t USERROW38; /* User Row Byte 38 */ + register8_t USERROW39; /* User Row Byte 39 */ + register8_t USERROW40; /* User Row Byte 40 */ + register8_t USERROW41; /* User Row Byte 41 */ + register8_t USERROW42; /* User Row Byte 42 */ + register8_t USERROW43; /* User Row Byte 43 */ + register8_t USERROW44; /* User Row Byte 44 */ + register8_t USERROW45; /* User Row Byte 45 */ + register8_t USERROW46; /* User Row Byte 46 */ + register8_t USERROW47; /* User Row Byte 47 */ + register8_t USERROW48; /* User Row Byte 48 */ + register8_t USERROW49; /* User Row Byte 49 */ + register8_t USERROW50; /* User Row Byte 50 */ + register8_t USERROW51; /* User Row Byte 51 */ + register8_t USERROW52; /* User Row Byte 52 */ + register8_t USERROW53; /* User Row Byte 53 */ + register8_t USERROW54; /* User Row Byte 54 */ + register8_t USERROW55; /* User Row Byte 55 */ + register8_t USERROW56; /* User Row Byte 56 */ + register8_t USERROW57; /* User Row Byte 57 */ + register8_t USERROW58; /* User Row Byte 58 */ + register8_t USERROW59; /* User Row Byte 59 */ + register8_t USERROW60; /* User Row Byte 60 */ + register8_t USERROW61; /* User Row Byte 61 */ + register8_t USERROW62; /* User Row Byte 62 */ + register8_t USERROW63; /* User Row Byte 63 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* AC0 reference select select */ +typedef enum VREF_AC0REFSEL_enum +{ + VREF_AC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_AC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_AC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_AC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_AC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ + VREF_AC0REFSEL_AVDD_gc = (0x07<<0), /* AVDD as Voltage reference */ +} VREF_AC0REFSEL_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define VPORTD (*(VPORT_t *) 0x000C) /* Virtual Ports */ +#define VPORTE (*(VPORT_t *) 0x0010) /* Virtual Ports */ +#define VPORTF (*(VPORT_t *) 0x0014) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0460) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0480) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x04A0) /* I/O Ports */ +#define PORTMUX (*(PORTMUX_t *) 0x05E0) /* Port Multiplexer */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1 (*(USART_t *) 0x0820) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2 (*(USART_t *) 0x0840) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART3 (*(USART_t *) 0x0860) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x08A0) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A80) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0A90) /* 16-bit Timer Type B */ +#define TCB2 (*(TCB_t *) 0x0AA0) /* 16-bit Timer Type B */ +#define TCB3 (*(TCB_t *) 0x0AB0) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* VPORT (VPORTD) - Virtual Ports */ +#define VPORTD_DIR _SFR_MEM8(0x000C) +#define VPORTD_OUT _SFR_MEM8(0x000D) +#define VPORTD_IN _SFR_MEM8(0x000E) +#define VPORTD_INTFLAGS _SFR_MEM8(0x000F) + + +/* VPORT (VPORTE) - Virtual Ports */ +#define VPORTE_DIR _SFR_MEM8(0x0010) +#define VPORTE_OUT _SFR_MEM8(0x0011) +#define VPORTE_IN _SFR_MEM8(0x0012) +#define VPORTE_INTFLAGS _SFR_MEM8(0x0013) + + +/* VPORT (VPORTF) - Virtual Ports */ +#define VPORTF_DIR _SFR_MEM8(0x0014) +#define VPORTF_OUT _SFR_MEM8(0x0015) +#define VPORTF_IN _SFR_MEM8(0x0016) +#define VPORTF_INTFLAGS _SFR_MEM8(0x0017) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CALIB _SFR_MEM8(0x0146) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_STROBE _SFR_MEM8(0x0180) +#define EVSYS_CHANNEL0 _SFR_MEM8(0x0190) +#define EVSYS_CHANNEL1 _SFR_MEM8(0x0191) +#define EVSYS_CHANNEL2 _SFR_MEM8(0x0192) +#define EVSYS_CHANNEL3 _SFR_MEM8(0x0193) +#define EVSYS_CHANNEL4 _SFR_MEM8(0x0194) +#define EVSYS_CHANNEL5 _SFR_MEM8(0x0195) +#define EVSYS_CHANNEL6 _SFR_MEM8(0x0196) +#define EVSYS_CHANNEL7 _SFR_MEM8(0x0197) +#define EVSYS_USERCCLLUT0A _SFR_MEM8(0x01A0) +#define EVSYS_USERCCLLUT0B _SFR_MEM8(0x01A1) +#define EVSYS_USERCCLLUT1A _SFR_MEM8(0x01A2) +#define EVSYS_USERCCLLUT1B _SFR_MEM8(0x01A3) +#define EVSYS_USERCCLLUT2A _SFR_MEM8(0x01A4) +#define EVSYS_USERCCLLUT2B _SFR_MEM8(0x01A5) +#define EVSYS_USERCCLLUT3A _SFR_MEM8(0x01A6) +#define EVSYS_USERCCLLUT3B _SFR_MEM8(0x01A7) +#define EVSYS_USERADC0 _SFR_MEM8(0x01A8) +#define EVSYS_USEREVOUTA _SFR_MEM8(0x01A9) +#define EVSYS_USEREVOUTB _SFR_MEM8(0x01AA) +#define EVSYS_USEREVOUTC _SFR_MEM8(0x01AB) +#define EVSYS_USEREVOUTD _SFR_MEM8(0x01AC) +#define EVSYS_USEREVOUTE _SFR_MEM8(0x01AD) +#define EVSYS_USEREVOUTF _SFR_MEM8(0x01AE) +#define EVSYS_USERUSART0 _SFR_MEM8(0x01AF) +#define EVSYS_USERUSART1 _SFR_MEM8(0x01B0) +#define EVSYS_USERUSART2 _SFR_MEM8(0x01B1) +#define EVSYS_USERUSART3 _SFR_MEM8(0x01B2) +#define EVSYS_USERTCA0 _SFR_MEM8(0x01B3) +#define EVSYS_USERTCB0 _SFR_MEM8(0x01B4) +#define EVSYS_USERTCB1 _SFR_MEM8(0x01B5) +#define EVSYS_USERTCB2 _SFR_MEM8(0x01B6) +#define EVSYS_USERTCB3 _SFR_MEM8(0x01B7) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_SEQCTRL1 _SFR_MEM8(0x01C2) +#define CCL_INTCTRL0 _SFR_MEM8(0x01C5) +#define CCL_INTFLAGS _SFR_MEM8(0x01C7) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C8) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C9) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01CA) +#define CCL_TRUTH0 _SFR_MEM8(0x01CB) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01CC) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CD) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CE) +#define CCL_TRUTH1 _SFR_MEM8(0x01CF) +#define CCL_LUT2CTRLA _SFR_MEM8(0x01D0) +#define CCL_LUT2CTRLB _SFR_MEM8(0x01D1) +#define CCL_LUT2CTRLC _SFR_MEM8(0x01D2) +#define CCL_TRUTH2 _SFR_MEM8(0x01D3) +#define CCL_LUT3CTRLA _SFR_MEM8(0x01D4) +#define CCL_LUT3CTRLB _SFR_MEM8(0x01D5) +#define CCL_LUT3CTRLC _SFR_MEM8(0x01D6) +#define CCL_TRUTH3 _SFR_MEM8(0x01D7) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PORTCTRL _SFR_MEM8(0x040A) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PORTCTRL _SFR_MEM8(0x042A) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PORTCTRL _SFR_MEM8(0x044A) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* PORT (PORTD) - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0460) +#define PORTD_DIRSET _SFR_MEM8(0x0461) +#define PORTD_DIRCLR _SFR_MEM8(0x0462) +#define PORTD_DIRTGL _SFR_MEM8(0x0463) +#define PORTD_OUT _SFR_MEM8(0x0464) +#define PORTD_OUTSET _SFR_MEM8(0x0465) +#define PORTD_OUTCLR _SFR_MEM8(0x0466) +#define PORTD_OUTTGL _SFR_MEM8(0x0467) +#define PORTD_IN _SFR_MEM8(0x0468) +#define PORTD_INTFLAGS _SFR_MEM8(0x0469) +#define PORTD_PORTCTRL _SFR_MEM8(0x046A) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0470) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0471) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0472) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0473) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0474) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0475) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0476) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0477) + + +/* PORT (PORTE) - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0480) +#define PORTE_DIRSET _SFR_MEM8(0x0481) +#define PORTE_DIRCLR _SFR_MEM8(0x0482) +#define PORTE_DIRTGL _SFR_MEM8(0x0483) +#define PORTE_OUT _SFR_MEM8(0x0484) +#define PORTE_OUTSET _SFR_MEM8(0x0485) +#define PORTE_OUTCLR _SFR_MEM8(0x0486) +#define PORTE_OUTTGL _SFR_MEM8(0x0487) +#define PORTE_IN _SFR_MEM8(0x0488) +#define PORTE_INTFLAGS _SFR_MEM8(0x0489) +#define PORTE_PORTCTRL _SFR_MEM8(0x048A) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0490) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0491) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0492) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0493) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0494) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0495) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0496) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0497) + + +/* PORT (PORTF) - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x04A0) +#define PORTF_DIRSET _SFR_MEM8(0x04A1) +#define PORTF_DIRCLR _SFR_MEM8(0x04A2) +#define PORTF_DIRTGL _SFR_MEM8(0x04A3) +#define PORTF_OUT _SFR_MEM8(0x04A4) +#define PORTF_OUTSET _SFR_MEM8(0x04A5) +#define PORTF_OUTCLR _SFR_MEM8(0x04A6) +#define PORTF_OUTTGL _SFR_MEM8(0x04A7) +#define PORTF_IN _SFR_MEM8(0x04A8) +#define PORTF_INTFLAGS _SFR_MEM8(0x04A9) +#define PORTF_PORTCTRL _SFR_MEM8(0x04AA) +#define PORTF_PIN0CTRL _SFR_MEM8(0x04B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x04B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x04B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x04B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x04B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x04B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x04B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x04B7) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_EVSYSROUTEA _SFR_MEM8(0x05E0) +#define PORTMUX_CCLROUTEA _SFR_MEM8(0x05E1) +#define PORTMUX_USARTROUTEA _SFR_MEM8(0x05E2) +#define PORTMUX_TWISPIROUTEA _SFR_MEM8(0x05E3) +#define PORTMUX_TCAROUTEA _SFR_MEM8(0x05E4) +#define PORTMUX_TCBROUTEA _SFR_MEM8(0x05E5) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_DACREF _SFR_MEM8(0x0684) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_CTRLD _SFR_MEM8(0x080A) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* USART (USART1) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1_RXDATAL _SFR_MEM8(0x0820) +#define USART1_RXDATAH _SFR_MEM8(0x0821) +#define USART1_TXDATAL _SFR_MEM8(0x0822) +#define USART1_TXDATAH _SFR_MEM8(0x0823) +#define USART1_STATUS _SFR_MEM8(0x0824) +#define USART1_CTRLA _SFR_MEM8(0x0825) +#define USART1_CTRLB _SFR_MEM8(0x0826) +#define USART1_CTRLC _SFR_MEM8(0x0827) +#define USART1_BAUD _SFR_MEM16(0x0828) +#define USART1_BAUDL _SFR_MEM8(0x0828) +#define USART1_BAUDH _SFR_MEM8(0x0829) +#define USART1_CTRLD _SFR_MEM8(0x082A) +#define USART1_DBGCTRL _SFR_MEM8(0x082B) +#define USART1_EVCTRL _SFR_MEM8(0x082C) +#define USART1_TXPLCTRL _SFR_MEM8(0x082D) +#define USART1_RXPLCTRL _SFR_MEM8(0x082E) + + +/* USART (USART2) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2_RXDATAL _SFR_MEM8(0x0840) +#define USART2_RXDATAH _SFR_MEM8(0x0841) +#define USART2_TXDATAL _SFR_MEM8(0x0842) +#define USART2_TXDATAH _SFR_MEM8(0x0843) +#define USART2_STATUS _SFR_MEM8(0x0844) +#define USART2_CTRLA _SFR_MEM8(0x0845) +#define USART2_CTRLB _SFR_MEM8(0x0846) +#define USART2_CTRLC _SFR_MEM8(0x0847) +#define USART2_BAUD _SFR_MEM16(0x0848) +#define USART2_BAUDL _SFR_MEM8(0x0848) +#define USART2_BAUDH _SFR_MEM8(0x0849) +#define USART2_CTRLD _SFR_MEM8(0x084A) +#define USART2_DBGCTRL _SFR_MEM8(0x084B) +#define USART2_EVCTRL _SFR_MEM8(0x084C) +#define USART2_TXPLCTRL _SFR_MEM8(0x084D) +#define USART2_RXPLCTRL _SFR_MEM8(0x084E) + + +/* USART (USART3) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART3_RXDATAL _SFR_MEM8(0x0860) +#define USART3_RXDATAH _SFR_MEM8(0x0861) +#define USART3_TXDATAL _SFR_MEM8(0x0862) +#define USART3_TXDATAH _SFR_MEM8(0x0863) +#define USART3_STATUS _SFR_MEM8(0x0864) +#define USART3_CTRLA _SFR_MEM8(0x0865) +#define USART3_CTRLB _SFR_MEM8(0x0866) +#define USART3_CTRLC _SFR_MEM8(0x0867) +#define USART3_BAUD _SFR_MEM16(0x0868) +#define USART3_BAUDL _SFR_MEM8(0x0868) +#define USART3_BAUDH _SFR_MEM8(0x0869) +#define USART3_CTRLD _SFR_MEM8(0x086A) +#define USART3_DBGCTRL _SFR_MEM8(0x086B) +#define USART3_EVCTRL _SFR_MEM8(0x086C) +#define USART3_TXPLCTRL _SFR_MEM8(0x086D) +#define USART3_RXPLCTRL _SFR_MEM8(0x086E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x08A0) +#define TWI0_DUALCTRL _SFR_MEM8(0x08A1) +#define TWI0_DBGCTRL _SFR_MEM8(0x08A2) +#define TWI0_MCTRLA _SFR_MEM8(0x08A3) +#define TWI0_MCTRLB _SFR_MEM8(0x08A4) +#define TWI0_MSTATUS _SFR_MEM8(0x08A5) +#define TWI0_MBAUD _SFR_MEM8(0x08A6) +#define TWI0_MADDR _SFR_MEM8(0x08A7) +#define TWI0_MDATA _SFR_MEM8(0x08A8) +#define TWI0_SCTRLA _SFR_MEM8(0x08A9) +#define TWI0_SCTRLB _SFR_MEM8(0x08AA) +#define TWI0_SSTATUS _SFR_MEM8(0x08AB) +#define TWI0_SADDR _SFR_MEM8(0x08AC) +#define TWI0_SDATA _SFR_MEM8(0x08AD) +#define TWI0_SADDRMASK _SFR_MEM8(0x08AE) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x08C0) +#define SPI0_CTRLB _SFR_MEM8(0x08C1) +#define SPI0_INTCTRL _SFR_MEM8(0x08C2) +#define SPI0_INTFLAGS _SFR_MEM8(0x08C3) +#define SPI0_DATA _SFR_MEM8(0x08C4) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A80) +#define TCB0_CTRLB _SFR_MEM8(0x0A81) +#define TCB0_EVCTRL _SFR_MEM8(0x0A84) +#define TCB0_INTCTRL _SFR_MEM8(0x0A85) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A86) +#define TCB0_STATUS _SFR_MEM8(0x0A87) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A88) +#define TCB0_TEMP _SFR_MEM8(0x0A89) +#define TCB0_CNT _SFR_MEM16(0x0A8A) +#define TCB0_CNTL _SFR_MEM8(0x0A8A) +#define TCB0_CNTH _SFR_MEM8(0x0A8B) +#define TCB0_CCMP _SFR_MEM16(0x0A8C) +#define TCB0_CCMPL _SFR_MEM8(0x0A8C) +#define TCB0_CCMPH _SFR_MEM8(0x0A8D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0A90) +#define TCB1_CTRLB _SFR_MEM8(0x0A91) +#define TCB1_EVCTRL _SFR_MEM8(0x0A94) +#define TCB1_INTCTRL _SFR_MEM8(0x0A95) +#define TCB1_INTFLAGS _SFR_MEM8(0x0A96) +#define TCB1_STATUS _SFR_MEM8(0x0A97) +#define TCB1_DBGCTRL _SFR_MEM8(0x0A98) +#define TCB1_TEMP _SFR_MEM8(0x0A99) +#define TCB1_CNT _SFR_MEM16(0x0A9A) +#define TCB1_CNTL _SFR_MEM8(0x0A9A) +#define TCB1_CNTH _SFR_MEM8(0x0A9B) +#define TCB1_CCMP _SFR_MEM16(0x0A9C) +#define TCB1_CCMPL _SFR_MEM8(0x0A9C) +#define TCB1_CCMPH _SFR_MEM8(0x0A9D) + + +/* TCB (TCB2) - 16-bit Timer Type B */ +#define TCB2_CTRLA _SFR_MEM8(0x0AA0) +#define TCB2_CTRLB _SFR_MEM8(0x0AA1) +#define TCB2_EVCTRL _SFR_MEM8(0x0AA4) +#define TCB2_INTCTRL _SFR_MEM8(0x0AA5) +#define TCB2_INTFLAGS _SFR_MEM8(0x0AA6) +#define TCB2_STATUS _SFR_MEM8(0x0AA7) +#define TCB2_DBGCTRL _SFR_MEM8(0x0AA8) +#define TCB2_TEMP _SFR_MEM8(0x0AA9) +#define TCB2_CNT _SFR_MEM16(0x0AAA) +#define TCB2_CNTL _SFR_MEM8(0x0AAA) +#define TCB2_CNTH _SFR_MEM8(0x0AAB) +#define TCB2_CCMP _SFR_MEM16(0x0AAC) +#define TCB2_CCMPL _SFR_MEM8(0x0AAC) +#define TCB2_CCMPH _SFR_MEM8(0x0AAD) + + +/* TCB (TCB3) - 16-bit Timer Type B */ +#define TCB3_CTRLA _SFR_MEM8(0x0AB0) +#define TCB3_CTRLB _SFR_MEM8(0x0AB1) +#define TCB3_EVCTRL _SFR_MEM8(0x0AB4) +#define TCB3_INTCTRL _SFR_MEM8(0x0AB5) +#define TCB3_INTFLAGS _SFR_MEM8(0x0AB6) +#define TCB3_STATUS _SFR_MEM8(0x0AB7) +#define TCB3_DBGCTRL _SFR_MEM8(0x0AB8) +#define TCB3_TEMP _SFR_MEM8(0x0AB9) +#define TCB3_CNT _SFR_MEM16(0x0ABA) +#define TCB3_CNTL _SFR_MEM8(0x0ABA) +#define TCB3_CNTH _SFR_MEM8(0x0ABB) +#define TCB3_CCMP _SFR_MEM16(0x0ABC) +#define TCB3_CCMPL _SFR_MEM8(0x0ABC) +#define TCB3_CCMPH _SFR_MEM8(0x0ABD) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) +#define SYSCFG_OCDM _SFR_MEM8(0x0F18) +#define SYSCFG_OCDMS _SFR_MEM8(0x0F19) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_OSCCAL32K _SFR_MEM8(0x1114) +#define SIGROW_OSCCAL16M0 _SFR_MEM8(0x1118) +#define SIGROW_OSCCAL16M1 _SFR_MEM8(0x1119) +#define SIGROW_OSCCAL20M0 _SFR_MEM8(0x111A) +#define SIGROW_OSCCAL20M1 _SFR_MEM8(0x111B) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) +#define SIGROW_CHECKSUM1 _SFR_MEM8(0x112F) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) +#define USERROW_USERROW32 _SFR_MEM8(0x1320) +#define USERROW_USERROW33 _SFR_MEM8(0x1321) +#define USERROW_USERROW34 _SFR_MEM8(0x1322) +#define USERROW_USERROW35 _SFR_MEM8(0x1323) +#define USERROW_USERROW36 _SFR_MEM8(0x1324) +#define USERROW_USERROW37 _SFR_MEM8(0x1325) +#define USERROW_USERROW38 _SFR_MEM8(0x1326) +#define USERROW_USERROW39 _SFR_MEM8(0x1327) +#define USERROW_USERROW40 _SFR_MEM8(0x1328) +#define USERROW_USERROW41 _SFR_MEM8(0x1329) +#define USERROW_USERROW42 _SFR_MEM8(0x132A) +#define USERROW_USERROW43 _SFR_MEM8(0x132B) +#define USERROW_USERROW44 _SFR_MEM8(0x132C) +#define USERROW_USERROW45 _SFR_MEM8(0x132D) +#define USERROW_USERROW46 _SFR_MEM8(0x132E) +#define USERROW_USERROW47 _SFR_MEM8(0x132F) +#define USERROW_USERROW48 _SFR_MEM8(0x1330) +#define USERROW_USERROW49 _SFR_MEM8(0x1331) +#define USERROW_USERROW50 _SFR_MEM8(0x1332) +#define USERROW_USERROW51 _SFR_MEM8(0x1333) +#define USERROW_USERROW52 _SFR_MEM8(0x1334) +#define USERROW_USERROW53 _SFR_MEM8(0x1335) +#define USERROW_USERROW54 _SFR_MEM8(0x1336) +#define USERROW_USERROW55 _SFR_MEM8(0x1337) +#define USERROW_USERROW56 _SFR_MEM8(0x1338) +#define USERROW_USERROW57 _SFR_MEM8(0x1339) +#define USERROW_USERROW58 _SFR_MEM8(0x133A) +#define USERROW_USERROW59 _SFR_MEM8(0x133B) +#define USERROW_USERROW60 _SFR_MEM8(0x133C) +#define USERROW_USERROW61 _SFR_MEM8(0x133D) +#define USERROW_USERROW62 _SFR_MEM8(0x133E) +#define USERROW_USERROW63 _SFR_MEM8(0x133F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.DACREF bit masks and bit positions */ +#define AC_DATA_gm 0xFF /* DAC voltage reference group mask. */ +#define AC_DATA_gp 0 /* DAC voltage reference group position. */ +#define AC_DATA0_bm (1<<0) /* DAC voltage reference bit 0 mask. */ +#define AC_DATA0_bp 0 /* DAC voltage reference bit 0 position. */ +#define AC_DATA1_bm (1<<1) /* DAC voltage reference bit 1 mask. */ +#define AC_DATA1_bp 1 /* DAC voltage reference bit 1 position. */ +#define AC_DATA2_bm (1<<2) /* DAC voltage reference bit 2 mask. */ +#define AC_DATA2_bp 2 /* DAC voltage reference bit 2 position. */ +#define AC_DATA3_bm (1<<3) /* DAC voltage reference bit 3 mask. */ +#define AC_DATA3_bp 3 /* DAC voltage reference bit 3 position. */ +#define AC_DATA4_bm (1<<4) /* DAC voltage reference bit 4 mask. */ +#define AC_DATA4_bp 4 /* DAC voltage reference bit 4 position. */ +#define AC_DATA5_bm (1<<5) /* DAC voltage reference bit 5 mask. */ +#define AC_DATA5_bp 5 /* DAC voltage reference bit 5 position. */ +#define AC_DATA6_bm (1<<6) /* DAC voltage reference bit 6 mask. */ +#define AC_DATA6_bp 6 /* DAC voltage reference bit 6 position. */ +#define AC_DATA7_bm (1<<7) /* DAC voltage reference bit 7 mask. */ +#define AC_DATA7_bp 7 /* DAC voltage reference bit 7 position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL0_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL0_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL00_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL00_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL01_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL01_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL02_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL02_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.SEQCTRL1 bit masks and bit positions */ +#define CCL_SEQSEL1_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL1_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL10_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL10_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL11_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL11_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL12_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL12_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.INTCTRL0 bit masks and bit positions */ +#define CCL_INTMODE0_gm 0x03 /* Interrupt Mode for LUT0 group mask. */ +#define CCL_INTMODE0_gp 0 /* Interrupt Mode for LUT0 group position. */ +#define CCL_INTMODE00_bm (1<<0) /* Interrupt Mode for LUT0 bit 0 mask. */ +#define CCL_INTMODE00_bp 0 /* Interrupt Mode for LUT0 bit 0 position. */ +#define CCL_INTMODE01_bm (1<<1) /* Interrupt Mode for LUT0 bit 1 mask. */ +#define CCL_INTMODE01_bp 1 /* Interrupt Mode for LUT0 bit 1 position. */ +#define CCL_INTMODE1_gm 0x0C /* Interrupt Mode for LUT1 group mask. */ +#define CCL_INTMODE1_gp 2 /* Interrupt Mode for LUT1 group position. */ +#define CCL_INTMODE10_bm (1<<2) /* Interrupt Mode for LUT1 bit 0 mask. */ +#define CCL_INTMODE10_bp 2 /* Interrupt Mode for LUT1 bit 0 position. */ +#define CCL_INTMODE11_bm (1<<3) /* Interrupt Mode for LUT1 bit 1 mask. */ +#define CCL_INTMODE11_bp 3 /* Interrupt Mode for LUT1 bit 1 position. */ +#define CCL_INTMODE2_gm 0x30 /* Interrupt Mode for LUT2 group mask. */ +#define CCL_INTMODE2_gp 4 /* Interrupt Mode for LUT2 group position. */ +#define CCL_INTMODE20_bm (1<<4) /* Interrupt Mode for LUT2 bit 0 mask. */ +#define CCL_INTMODE20_bp 4 /* Interrupt Mode for LUT2 bit 0 position. */ +#define CCL_INTMODE21_bm (1<<5) /* Interrupt Mode for LUT2 bit 1 mask. */ +#define CCL_INTMODE21_bp 5 /* Interrupt Mode for LUT2 bit 1 position. */ +#define CCL_INTMODE3_gm 0xC0 /* Interrupt Mode for LUT3 group mask. */ +#define CCL_INTMODE3_gp 6 /* Interrupt Mode for LUT3 group position. */ +#define CCL_INTMODE30_bm (1<<6) /* Interrupt Mode for LUT3 bit 0 mask. */ +#define CCL_INTMODE30_bp 6 /* Interrupt Mode for LUT3 bit 0 position. */ +#define CCL_INTMODE31_bm (1<<7) /* Interrupt Mode for LUT3 bit 1 mask. */ +#define CCL_INTMODE31_bp 7 /* Interrupt Mode for LUT3 bit 1 position. */ + +/* CCL.INTFLAGS bit masks and bit positions */ +#define CCL_INT_gm 0x0F /* Interrupt Flags group mask. */ +#define CCL_INT_gp 0 /* Interrupt Flags group position. */ +#define CCL_INT0_bm (1<<0) /* Interrupt Flags bit 0 mask. */ +#define CCL_INT0_bp 0 /* Interrupt Flags bit 0 position. */ +#define CCL_INT1_bm (1<<1) /* Interrupt Flags bit 1 mask. */ +#define CCL_INT1_bp 1 /* Interrupt Flags bit 1 position. */ +#define CCL_INT2_bm (1<<2) /* Interrupt Flags bit 2 mask. */ +#define CCL_INT2_bp 2 /* Interrupt Flags bit 2 position. */ +#define CCL_INT3_bm (1<<3) /* Interrupt Flags bit 3 mask. */ +#define CCL_INT3_bp 3 /* Interrupt Flags bit 3 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_CLKSRC_gm 0x0E /* Clock Source Selection group mask. */ +#define CCL_CLKSRC_gp 1 /* Clock Source Selection group position. */ +#define CCL_CLKSRC0_bm (1<<1) /* Clock Source Selection bit 0 mask. */ +#define CCL_CLKSRC0_bp 1 /* Clock Source Selection bit 0 position. */ +#define CCL_CLKSRC1_bm (1<<2) /* Clock Source Selection bit 1 mask. */ +#define CCL_CLKSRC1_bp 2 /* Clock Source Selection bit 1 position. */ +#define CCL_CLKSRC2_bm (1<<3) /* Clock Source Selection bit 2 mask. */ +#define CCL_CLKSRC2_bp 3 /* Clock Source Selection bit 2 position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_OUTEN_bm 0x40 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 6 /* Output Enable bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT2CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT2CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT2CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT3CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT3CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT3CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x7F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ +#define CLKCTRL_CAL20M6_bm (1<<6) /* Calibration bit 6 mask. */ +#define CLKCTRL_CAL20M6_bp 6 /* Calibration bit 6 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.STROBE bit masks and bit positions */ +#define EVSYS_STROBE0_gm 0xFF /* Software event on channels group mask. */ +#define EVSYS_STROBE0_gp 0 /* Software event on channels group position. */ +#define EVSYS_STROBE00_bm (1<<0) /* Software event on channels bit 0 mask. */ +#define EVSYS_STROBE00_bp 0 /* Software event on channels bit 0 position. */ +#define EVSYS_STROBE01_bm (1<<1) /* Software event on channels bit 1 mask. */ +#define EVSYS_STROBE01_bp 1 /* Software event on channels bit 1 position. */ +#define EVSYS_STROBE02_bm (1<<2) /* Software event on channels bit 2 mask. */ +#define EVSYS_STROBE02_bp 2 /* Software event on channels bit 2 position. */ +#define EVSYS_STROBE03_bm (1<<3) /* Software event on channels bit 3 mask. */ +#define EVSYS_STROBE03_bp 3 /* Software event on channels bit 3 position. */ +#define EVSYS_STROBE04_bm (1<<4) /* Software event on channels bit 4 mask. */ +#define EVSYS_STROBE04_bp 4 /* Software event on channels bit 4 position. */ +#define EVSYS_STROBE05_bm (1<<5) /* Software event on channels bit 5 mask. */ +#define EVSYS_STROBE05_bp 5 /* Software event on channels bit 5 position. */ +#define EVSYS_STROBE06_bm (1<<6) /* Software event on channels bit 6 mask. */ +#define EVSYS_STROBE06_bp 6 /* Software event on channels bit 6 position. */ +#define EVSYS_STROBE07_bm (1<<7) /* Software event on channels bit 7 mask. */ +#define EVSYS_STROBE07_bp 7 /* Software event on channels bit 7 position. */ + +/* EVSYS.CHANNEL0 bit masks and bit positions */ +#define EVSYS_GENERATOR_gm 0xFF /* Generator selector group mask. */ +#define EVSYS_GENERATOR_gp 0 /* Generator selector group position. */ +#define EVSYS_GENERATOR0_bm (1<<0) /* Generator selector bit 0 mask. */ +#define EVSYS_GENERATOR0_bp 0 /* Generator selector bit 0 position. */ +#define EVSYS_GENERATOR1_bm (1<<1) /* Generator selector bit 1 mask. */ +#define EVSYS_GENERATOR1_bp 1 /* Generator selector bit 1 position. */ +#define EVSYS_GENERATOR2_bm (1<<2) /* Generator selector bit 2 mask. */ +#define EVSYS_GENERATOR2_bp 2 /* Generator selector bit 2 position. */ +#define EVSYS_GENERATOR3_bm (1<<3) /* Generator selector bit 3 mask. */ +#define EVSYS_GENERATOR3_bp 3 /* Generator selector bit 3 position. */ +#define EVSYS_GENERATOR4_bm (1<<4) /* Generator selector bit 4 mask. */ +#define EVSYS_GENERATOR4_bp 4 /* Generator selector bit 4 position. */ +#define EVSYS_GENERATOR5_bm (1<<5) /* Generator selector bit 5 mask. */ +#define EVSYS_GENERATOR5_bp 5 /* Generator selector bit 5 position. */ +#define EVSYS_GENERATOR6_bm (1<<6) /* Generator selector bit 6 mask. */ +#define EVSYS_GENERATOR6_bp 6 /* Generator selector bit 6 position. */ +#define EVSYS_GENERATOR7_bm (1<<7) /* Generator selector bit 7 mask. */ +#define EVSYS_GENERATOR7_bp 7 /* Generator selector bit 7 position. */ + +/* EVSYS.CHANNEL1 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL2 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL3 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL4 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL5 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL6 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL7 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.USERCCLLUT0A bit masks and bit positions */ +#define EVSYS_CHANNEL_gm 0xFF /* Channel selector group mask. */ +#define EVSYS_CHANNEL_gp 0 /* Channel selector group position. */ +#define EVSYS_CHANNEL0_bm (1<<0) /* Channel selector bit 0 mask. */ +#define EVSYS_CHANNEL0_bp 0 /* Channel selector bit 0 position. */ +#define EVSYS_CHANNEL1_bm (1<<1) /* Channel selector bit 1 mask. */ +#define EVSYS_CHANNEL1_bp 1 /* Channel selector bit 1 position. */ +#define EVSYS_CHANNEL2_bm (1<<2) /* Channel selector bit 2 mask. */ +#define EVSYS_CHANNEL2_bp 2 /* Channel selector bit 2 position. */ +#define EVSYS_CHANNEL3_bm (1<<3) /* Channel selector bit 3 mask. */ +#define EVSYS_CHANNEL3_bp 3 /* Channel selector bit 3 position. */ +#define EVSYS_CHANNEL4_bm (1<<4) /* Channel selector bit 4 mask. */ +#define EVSYS_CHANNEL4_bp 4 /* Channel selector bit 4 position. */ +#define EVSYS_CHANNEL5_bm (1<<5) /* Channel selector bit 5 mask. */ +#define EVSYS_CHANNEL5_bp 5 /* Channel selector bit 5 position. */ +#define EVSYS_CHANNEL6_bm (1<<6) /* Channel selector bit 6 mask. */ +#define EVSYS_CHANNEL6_bp 6 /* Channel selector bit 6 position. */ +#define EVSYS_CHANNEL7_bm (1<<7) /* Channel selector bit 7 mask. */ +#define EVSYS_CHANNEL7_bp 7 /* Channel selector bit 7 position. */ + +/* EVSYS.USERCCLLUT0B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT1A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT1B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT2A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT2B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT3A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT3B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERADC0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTA bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTB bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTC bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTD bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTE bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTF bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART1 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART2 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART3 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCA0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB1 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB2 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB3 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_bm 0x08 /* Reset Pin Configuration bit mask. */ +#define FUSE_RSTPINCFG_bp 3 /* Reset Pin Configuration bit position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PORTCTRL bit masks and bit positions */ +#define PORT_SRL_bm 0x01 /* Slew Rate Limit Enable bit mask. */ +#define PORT_SRL_bp 0 /* Slew Rate Limit Enable bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.EVSYSROUTEA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_EVOUT3_bm 0x08 /* Event Output 3 bit mask. */ +#define PORTMUX_EVOUT3_bp 3 /* Event Output 3 bit position. */ +#define PORTMUX_EVOUT4_bm 0x10 /* Event Output 4 bit mask. */ +#define PORTMUX_EVOUT4_bp 4 /* Event Output 4 bit position. */ +#define PORTMUX_EVOUT5_bm 0x20 /* Event Output 5 bit mask. */ +#define PORTMUX_EVOUT5_bp 5 /* Event Output 5 bit position. */ + +/* PORTMUX.CCLROUTEA bit masks and bit positions */ +#define PORTMUX_LUT0_bm 0x01 /* CCL LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 0 /* CCL LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x02 /* CCL LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 1 /* CCL LUT1 bit position. */ +#define PORTMUX_LUT2_bm 0x04 /* CCL LUT2 bit mask. */ +#define PORTMUX_LUT2_bp 2 /* CCL LUT2 bit position. */ +#define PORTMUX_LUT3_bm 0x08 /* CCL LUT3 bit mask. */ +#define PORTMUX_LUT3_bp 3 /* CCL LUT3 bit position. */ + +/* PORTMUX.USARTROUTEA bit masks and bit positions */ +#define PORTMUX_USART0_gm 0x03 /* Port Multiplexer USART0 group mask. */ +#define PORTMUX_USART0_gp 0 /* Port Multiplexer USART0 group position. */ +#define PORTMUX_USART00_bm (1<<0) /* Port Multiplexer USART0 bit 0 mask. */ +#define PORTMUX_USART00_bp 0 /* Port Multiplexer USART0 bit 0 position. */ +#define PORTMUX_USART01_bm (1<<1) /* Port Multiplexer USART0 bit 1 mask. */ +#define PORTMUX_USART01_bp 1 /* Port Multiplexer USART0 bit 1 position. */ +#define PORTMUX_USART1_gm 0x0C /* Port Multiplexer USART1 group mask. */ +#define PORTMUX_USART1_gp 2 /* Port Multiplexer USART1 group position. */ +#define PORTMUX_USART10_bm (1<<2) /* Port Multiplexer USART1 bit 0 mask. */ +#define PORTMUX_USART10_bp 2 /* Port Multiplexer USART1 bit 0 position. */ +#define PORTMUX_USART11_bm (1<<3) /* Port Multiplexer USART1 bit 1 mask. */ +#define PORTMUX_USART11_bp 3 /* Port Multiplexer USART1 bit 1 position. */ +#define PORTMUX_USART2_gm 0x30 /* Port Multiplexer USART2 group mask. */ +#define PORTMUX_USART2_gp 4 /* Port Multiplexer USART2 group position. */ +#define PORTMUX_USART20_bm (1<<4) /* Port Multiplexer USART2 bit 0 mask. */ +#define PORTMUX_USART20_bp 4 /* Port Multiplexer USART2 bit 0 position. */ +#define PORTMUX_USART21_bm (1<<5) /* Port Multiplexer USART2 bit 1 mask. */ +#define PORTMUX_USART21_bp 5 /* Port Multiplexer USART2 bit 1 position. */ +#define PORTMUX_USART3_gm 0xC0 /* Port Multiplexer USART3 group mask. */ +#define PORTMUX_USART3_gp 6 /* Port Multiplexer USART3 group position. */ +#define PORTMUX_USART30_bm (1<<6) /* Port Multiplexer USART3 bit 0 mask. */ +#define PORTMUX_USART30_bp 6 /* Port Multiplexer USART3 bit 0 position. */ +#define PORTMUX_USART31_bm (1<<7) /* Port Multiplexer USART3 bit 1 mask. */ +#define PORTMUX_USART31_bp 7 /* Port Multiplexer USART3 bit 1 position. */ + +/* PORTMUX.TWISPIROUTEA bit masks and bit positions */ +#define PORTMUX_SPI0_gm 0x03 /* Port Multiplexer SPI0 group mask. */ +#define PORTMUX_SPI0_gp 0 /* Port Multiplexer SPI0 group position. */ +#define PORTMUX_SPI00_bm (1<<0) /* Port Multiplexer SPI0 bit 0 mask. */ +#define PORTMUX_SPI00_bp 0 /* Port Multiplexer SPI0 bit 0 position. */ +#define PORTMUX_SPI01_bm (1<<1) /* Port Multiplexer SPI0 bit 1 mask. */ +#define PORTMUX_SPI01_bp 1 /* Port Multiplexer SPI0 bit 1 position. */ +#define PORTMUX_TWI0_gm 0x30 /* Port Multiplexer TWI0 group mask. */ +#define PORTMUX_TWI0_gp 4 /* Port Multiplexer TWI0 group position. */ +#define PORTMUX_TWI00_bm (1<<4) /* Port Multiplexer TWI0 bit 0 mask. */ +#define PORTMUX_TWI00_bp 4 /* Port Multiplexer TWI0 bit 0 position. */ +#define PORTMUX_TWI01_bm (1<<5) /* Port Multiplexer TWI0 bit 1 mask. */ +#define PORTMUX_TWI01_bp 5 /* Port Multiplexer TWI0 bit 1 position. */ + +/* PORTMUX.TCAROUTEA bit masks and bit positions */ +#define PORTMUX_TCA0_gm 0x07 /* Port Multiplexer TCA0 group mask. */ +#define PORTMUX_TCA0_gp 0 /* Port Multiplexer TCA0 group position. */ +#define PORTMUX_TCA00_bm (1<<0) /* Port Multiplexer TCA0 bit 0 mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 bit 0 position. */ +#define PORTMUX_TCA01_bm (1<<1) /* Port Multiplexer TCA0 bit 1 mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 bit 1 position. */ +#define PORTMUX_TCA02_bm (1<<2) /* Port Multiplexer TCA0 bit 2 mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 bit 2 position. */ + +/* PORTMUX.TCBROUTEA bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ +#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ +#define PORTMUX_TCB2_bm 0x04 /* Port Multiplexer TCB2 bit mask. */ +#define PORTMUX_TCB2_bp 2 /* Port Multiplexer TCB2 bit position. */ +#define PORTMUX_TCB3_bm 0x08 /* Port Multiplexer TCB3 bit mask. */ +#define PORTMUX_TCB3_bp 3 /* Port Multiplexer TCB3 bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_CORREN_bm 0x04 /* Correction enable bit mask. */ +#define RTC_CORREN_bp 2 /* Correction enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_ERROR_gm 0x7F /* Error Correction Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Correction Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Correction Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Correction Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Correction Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Correction Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Correction Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Correction Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Correction Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Correction Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Correction Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Correction Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Correction Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Correction Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Correction Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Correction Value bit 6 position. */ +#define RTC_SIGN_bm 0x80 /* Error Correction Sign Bit bit mask. */ +#define RTC_SIGN_bp 7 /* Error Correction Sign Bit bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + + +/* SYSCFG.OCDMS bit masks and bit positions */ +#define SYSCFG_OCDMR_bm 0x01 /* OCD Message Read bit mask. */ +#define SYSCFG_OCDMR_bp 0 /* OCD Message Read bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DUALCTRL bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Dual Control Enable bit mask. */ +#define TWI_ENABLE_bp 0 /* Dual Control Enable bit position. */ +/* TWI_FMPEN is already defined. */ +/* TWI_SDAHOLD is already defined. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.CTRLD bit masks and bit positions */ +#define USART_ABW_gm 0xC0 /* Auto Baud Window group mask. */ +#define USART_ABW_gp 6 /* Auto Baud Window group position. */ +#define USART_ABW0_bm (1<<6) /* Auto Baud Window bit 0 mask. */ +#define USART_ABW0_bp 6 /* Auto Baud Window bit 0 position. */ +#define USART_ABW1_bm (1<<7) /* Auto Baud Window bit 1 mask. */ +#define USART_ABW1_bp 7 /* Auto Baud Window bit 1 position. */ + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_AC0REFSEL_gm 0x07 /* AC0 reference select group mask. */ +#define VREF_AC0REFSEL_gp 0 /* AC0 reference select group position. */ +#define VREF_AC0REFSEL0_bm (1<<0) /* AC0 reference select bit 0 mask. */ +#define VREF_AC0REFSEL0_bp 0 /* AC0 reference select bit 0 position. */ +#define VREF_AC0REFSEL1_bm (1<<1) /* AC0 reference select bit 1 mask. */ +#define VREF_AC0REFSEL1_bp 1 /* AC0 reference select bit 1 position. */ +#define VREF_AC0REFSEL2_bm (1<<2) /* AC0 reference select bit 2 mask. */ +#define VREF_AC0REFSEL2_bp 2 /* AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_AC0REFEN_bm 0x01 /* AC0 DACREF reference enable bit mask. */ +#define VREF_AC0REFEN_bp 0 /* AC0 DACREF reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 3 +#define RTC_CNT_vect _VECTOR(3) /* */ +#define RTC_PIT_vect_num 4 +#define RTC_PIT_vect _VECTOR(4) /* */ + +/* CCL interrupt vectors */ +#define CCL_CCL_vect_num 5 +#define CCL_CCL_vect _VECTOR(5) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 6 +#define PORTA_PORT_vect _VECTOR(6) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 7 +#define TCA0_LUNF_vect _VECTOR(7) /* */ +#define TCA0_OVF_vect_num 7 +#define TCA0_OVF_vect _VECTOR(7) /* */ +#define TCA0_HUNF_vect_num 8 +#define TCA0_HUNF_vect _VECTOR(8) /* */ +#define TCA0_CMP0_vect_num 9 +#define TCA0_CMP0_vect _VECTOR(9) /* */ +#define TCA0_LCMP0_vect_num 9 +#define TCA0_LCMP0_vect _VECTOR(9) /* */ +#define TCA0_CMP1_vect_num 10 +#define TCA0_CMP1_vect _VECTOR(10) /* */ +#define TCA0_LCMP1_vect_num 10 +#define TCA0_LCMP1_vect _VECTOR(10) /* */ +#define TCA0_CMP2_vect_num 11 +#define TCA0_CMP2_vect _VECTOR(11) /* */ +#define TCA0_LCMP2_vect_num 11 +#define TCA0_LCMP2_vect _VECTOR(11) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 12 +#define TCB0_INT_vect _VECTOR(12) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 13 +#define TCB1_INT_vect _VECTOR(13) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 14 +#define TWI0_TWIS_vect _VECTOR(14) /* */ +#define TWI0_TWIM_vect_num 15 +#define TWI0_TWIM_vect _VECTOR(15) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 16 +#define SPI0_INT_vect _VECTOR(16) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 17 +#define USART0_RXC_vect _VECTOR(17) /* */ +#define USART0_DRE_vect_num 18 +#define USART0_DRE_vect _VECTOR(18) /* */ +#define USART0_TXC_vect_num 19 +#define USART0_TXC_vect _VECTOR(19) /* */ + +/* PORTD interrupt vectors */ +#define PORTD_PORT_vect_num 20 +#define PORTD_PORT_vect _VECTOR(20) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 21 +#define AC0_AC_vect _VECTOR(21) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 22 +#define ADC0_RESRDY_vect _VECTOR(22) /* */ +#define ADC0_WCOMP_vect_num 23 +#define ADC0_WCOMP_vect _VECTOR(23) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 24 +#define PORTC_PORT_vect _VECTOR(24) /* */ + +/* TCB2 interrupt vectors */ +#define TCB2_INT_vect_num 25 +#define TCB2_INT_vect _VECTOR(25) /* */ + +/* USART1 interrupt vectors */ +#define USART1_RXC_vect_num 26 +#define USART1_RXC_vect _VECTOR(26) /* */ +#define USART1_DRE_vect_num 27 +#define USART1_DRE_vect _VECTOR(27) /* */ +#define USART1_TXC_vect_num 28 +#define USART1_TXC_vect _VECTOR(28) /* */ + +/* PORTF interrupt vectors */ +#define PORTF_PORT_vect_num 29 +#define PORTF_PORT_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +/* USART2 interrupt vectors */ +#define USART2_RXC_vect_num 31 +#define USART2_RXC_vect _VECTOR(31) /* */ +#define USART2_DRE_vect_num 32 +#define USART2_DRE_vect _VECTOR(32) /* */ +#define USART2_TXC_vect_num 33 +#define USART2_TXC_vect _VECTOR(33) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 34 +#define PORTB_PORT_vect _VECTOR(34) /* */ + +/* PORTE interrupt vectors */ +#define PORTE_PORT_vect_num 35 +#define PORTE_PORT_vect _VECTOR(35) /* */ + +/* TCB3 interrupt vectors */ +#define TCB3_INT_vect_num 36 +#define TCB3_INT_vect _VECTOR(36) /* */ + +/* USART3 interrupt vectors */ +#define USART3_RXC_vect_num 37 +#define USART3_RXC_vect _VECTOR(37) /* */ +#define USART3_DRE_vect_num 38 +#define USART3_DRE_vect _VECTOR(38) /* */ +#define USART3_TXC_vect_num 39 +#define USART3_TXC_vect _VECTOR(39) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (40 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (16384) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (16384U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3800) +# define INTERNAL_SRAM_SIZE (2048) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3800U) +# define INTERNAL_SRAM_SIZE (2048U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x4000) +# define MAPPED_PROGMEM_SIZE (16384) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x4000U) +# define MAPPED_PROGMEM_SIZE (16384U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (16384) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (16384U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG (unsigned char)_BV(3) /* Reset Pin Configuration */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x26 + + +#endif /* #ifdef _AVR_ATMEGA1609_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iom161.h b/hardware/tools/avr/avr/include/avr/iom161.h new file mode 100644 index 0000000000000000000000000000000000000000..a5f6f9edf015f1093613eb16b6e7fbe1f767c490 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom161.h @@ -0,0 +1,726 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom161.h 2229 2011-03-05 17:00:18Z arcanum $ */ + +/* avr/iom161.h - definitions for ATmega161 */ + +#ifndef _AVR_IOM161_H_ +#define _AVR_IOM161_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom161.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* UART1 Baud Rate Register */ +#define UBRR1 _SFR_IO8(0x00) + +/* UART1 Control and Status Registers */ +#define UCSR1B _SFR_IO8(0x01) +#define UCSR1A _SFR_IO8(0x02) + +/* UART1 I/O Data Register */ +#define UDR1 _SFR_IO8(0x03) + +/* 0x04 reserved */ + +/* Input Pins, Port E */ +#define PINE _SFR_IO8(0x05) + +/* Data Direction Register, Port E */ +#define DDRE _SFR_IO8(0x06) + +/* Data Register, Port E */ +#define PORTE _SFR_IO8(0x07) + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) + +/* UART0 Baud Rate Register */ +#define UBRR0 _SFR_IO8(0x09) + +/* UART0 Control and Status Registers */ +#define UCSR0B _SFR_IO8(0x0A) +#define UCSR0A _SFR_IO8(0x0B) + +/* UART0 I/O Data Register */ +#define UDR0 _SFR_IO8(0x0C) + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x0D) + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x0E) + +/* SPI I/O Data Register */ +#define SPDR _SFR_IO8(0x0F) + +/* Input Pins, Port D */ +#define PIND _SFR_IO8(0x10) + +/* Data Direction Register, Port D */ +#define DDRD _SFR_IO8(0x11) + +/* Data Register, Port D */ +#define PORTD _SFR_IO8(0x12) + +/* Input Pins, Port C */ +#define PINC _SFR_IO8(0x13) + +/* Data Direction Register, Port C */ +#define DDRC _SFR_IO8(0x14) + +/* Data Register, Port C */ +#define PORTC _SFR_IO8(0x15) + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* Input Pins, Port A */ +#define PINA _SFR_IO8(0x19) + +/* Data Direction Register, Port A */ +#define DDRA _SFR_IO8(0x1A) + +/* Data Register, Port A */ +#define PORTA _SFR_IO8(0x1B) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO16(0x1E) +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +/* UART Baud Register HIgh */ +#define UBRRH _SFR_IO8(0x20) + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* Timer/Counter2 Output Compare Register */ +#define OCR2 _SFR_IO8(0x22) + +/* Timer/Counter2 (8-bit) */ +#define TCNT2 _SFR_IO8(0x23) + +/* Timer/Counter1 Input Capture Register */ +#define ICR1 _SFR_IO16(0x24) +#define ICR1L _SFR_IO8(0x24) +#define ICR1H _SFR_IO8(0x25) + +/* ASynchronous mode Status Register */ +#define ASSR _SFR_IO8(0x26) + +/* Timer/Counter2 Control Register */ +#define TCCR2 _SFR_IO8(0x27) + +/* Timer/Counter1 Output Compare RegisterB */ +#define OCR1B _SFR_IO16(0x28) +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Timer/Counter1 Output Compare RegisterA */ +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Timer/Counter1 */ +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +/* Timer/Counter1 Control Register B */ +#define TCCR1B _SFR_IO8(0x2E) + +/* Timer/Counter1 Control Register A */ +#define TCCR1A _SFR_IO8(0x2F) + +/* Special Function IO Register */ +#define SFIOR _SFR_IO8(0x30) + +/* Timer/Counter0 Output Compare Register */ +#define OCR0 _SFR_IO8(0x31) + +/* Timer/Counter0 (8-bit) */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU general Status Register */ +#define MCUSR _SFR_IO8(0x34) + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* Extended MCU general Control Register */ +#define EMCUCR _SFR_IO8(0x36) + +/* Store Program Memory Control Register */ +#define SPMCR _SFR_IO8(0x37) + +/* Timer/Counter Interrupt Flag Register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK Register */ +#define TIMSK _SFR_IO8(0x39) + +/* General Interrupt Flag Register */ +#define GIFR _SFR_IO8(0x3A) + +/* General Interrupt MaSK register */ +#define GIMSK _SFR_IO8(0x3B) + +/* 0x3C reserved */ + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* External Interrupt 2 */ +#define INT2_vect_num 3 +#define INT2_vect _VECTOR(3) +#define SIG_INTERRUPT2 _VECTOR(3) + +/* Timer/Counter2 Compare Match */ +#define TIMER2_COMP_vect_num 4 +#define TIMER2_COMP_vect _VECTOR(4) +#define SIG_OUTPUT_COMPARE2 _VECTOR(4) + +/* Timer/Counter2 Overflow */ +#define TIMER2_OVF_vect_num 5 +#define TIMER2_OVF_vect _VECTOR(5) +#define SIG_OVERFLOW2 _VECTOR(5) + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect_num 6 +#define TIMER1_CAPT_vect _VECTOR(6) +#define SIG_INPUT_CAPTURE1 _VECTOR(6) + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect_num 7 +#define TIMER1_COMPA_vect _VECTOR(7) +#define SIG_OUTPUT_COMPARE1A _VECTOR(7) + +/* Timer/Counter1 Compare Match B */ +#define TIMER1_COMPB_vect_num 8 +#define TIMER1_COMPB_vect _VECTOR(8) +#define SIG_OUTPUT_COMPARE1B _VECTOR(8) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 9 +#define TIMER1_OVF_vect _VECTOR(9) +#define SIG_OVERFLOW1 _VECTOR(9) + +/* Timer/Counter0 Compare Match */ +#define TIMER0_COMP_vect_num 10 +#define TIMER0_COMP_vect _VECTOR(10) +#define SIG_OUTPUT_COMPARE0 _VECTOR(10) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 11 +#define TIMER0_OVF_vect _VECTOR(11) +#define SIG_OVERFLOW0 _VECTOR(11) + +/* Serial Transfer Complete */ +#define SPI_STC_vect_num 12 +#define SPI_STC_vect _VECTOR(12) +#define SIG_SPI _VECTOR(12) + +/* UART0, Rx Complete */ +#define UART0_RX_vect_num 13 +#define UART0_RX_vect _VECTOR(13) +#define SIG_UART0_RECV _VECTOR(13) + +/* UART1, Rx Complete */ +#define UART1_RX_vect_num 14 +#define UART1_RX_vect _VECTOR(14) +#define SIG_UART1_RECV _VECTOR(14) + +/* UART0 Data Register Empty */ +#define UART0_UDRE_vect_num 15 +#define UART0_UDRE_vect _VECTOR(15) +#define SIG_UART0_DATA _VECTOR(15) + +/* UART1 Data Register Empty */ +#define UART1_UDRE_vect_num 16 +#define UART1_UDRE_vect _VECTOR(16) +#define SIG_UART1_DATA _VECTOR(16) + +/* UART0, Tx Complete */ +#define UART0_TX_vect_num 17 +#define UART0_TX_vect _VECTOR(17) +#define SIG_UART0_TRANS _VECTOR(17) + +/* UART1, Tx Complete */ +#define UART1_TX_vect_num 18 +#define UART1_TX_vect _VECTOR(18) +#define SIG_UART1_TRANS _VECTOR(18) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 19 +#define EE_RDY_vect _VECTOR(19) +#define SIG_EEPROM_READY _VECTOR(19) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 20 +#define ANA_COMP_vect _VECTOR(20) +#define SIG_COMPARATOR _VECTOR(20) + +#define _VECTORS_SIZE 84 + +/* Bit numbers */ + +/* GIMSK */ +#define INT1 7 +#define INT0 6 +#define INT2 5 + +/* GIFR */ +#define INTF1 7 +#define INTF0 6 +#define INTF2 5 + +/* TIMSK */ +#define TOIE1 7 +#define OCIE1A 6 +#define OCIE1B 5 +#define TOIE2 4 +#define TICIE1 3 +#define OCIE2 2 +#define TOIE0 1 +#define OCIE0 0 + +/* TIFR */ +#define TOV1 7 +#define OCF1A 6 +#define OCF1B 5 +#define TOV2 4 +#define ICF1 3 +#define OCF2 2 +#define TOV0 1 +#define OCF0 0 + +/* MCUCR */ +#define SRE 7 +#define SRW10 6 +#define SE 5 +#define SM1 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/* EMCUCR */ +#define SM0 7 +#define SRL2 6 +#define SRL1 5 +#define SRL0 4 +#define SRW01 3 +#define SRW00 2 +#define SRW11 1 +#define ISC2 0 + +/* SPMCR */ +#define BLBSET 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 + +/* SFIOR */ +#define PSR2 1 +#define PSR10 0 + +/* TCCR0 */ +#define FOC0 7 +#define PWM0 6 +#define COM01 5 +#define COM00 4 +#define CTC0 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* TCCR2 */ +#define FOC2 7 +#define PWM2 6 +#define COM21 5 +#define COM20 4 +#define CTC2 3 +#define CS22 2 +#define CS21 1 +#define CS20 0 + +/* ASSR */ +#define AS2 3 +#define TCN2UB 2 +#define OCR2UB 1 +#define TCR2UB 0 + +/* TCCR1A */ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define FOC1A 3 +#define FOC1B 2 +#define PWM11 1 +#define PWM10 0 + +/* TCCR1B */ +#define ICNC1 7 +#define ICES1 6 +#define CTC1 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* WDTCR */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* PORTA */ +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* DDRA */ +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +/* PINA */ +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +/* + PB7 = SCK + PB6 = MISO + PB5 = MOSI + PB4 = SS# + PB3 = TXD1 / AIN1 + PB2 = RXD1 / AIN0 + PB1 = OC2 / T1 + PB0 = OC0 / T0 + */ + +/* PORTB */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* DDRB */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* PINB */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* PORTC */ +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* DDRC */ +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +/* PINC */ +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +/* + PD7 = RD# + PD6 = WR# + PD5 = TOSC2 / OC1A + PD4 = TOSC1 + PD3 = INT1 + PD2 = INT0 + PD1 = TXD0 + PD0 = RXD0 + */ + +/* PORTD */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* DDRD */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* PIND */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* + PE2 = ALE + PE1 = OC1B + PE0 = ICP / INT2 + */ + +/* PORTE */ +#define PE2 2 +#define PE1 1 +#define PE0 0 + +/* DDRE */ +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +/* PINE */ +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +/* SPSR */ +#define SPIF 7 +#define WCOL 6 +#define SPI2X 0 + +/* SPCR */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* UCSR0A, UCSR1A */ +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 +#define U2X 1 +#define MPCM 0 + +/* UCSR0B, UCSR1B */ +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define CHR9 2 +#define RXB8 1 +#define TXB8 0 + +/* ACSR */ +#define ACD 7 +#define AINBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define SPM_PAGESIZE 128 +#define RAMSTART 0x60 +#define RAMEND 0x45F +#define XRAMEND 0xFFFF +#define E2END 0x1FF +#define E2PAGESIZE 0 +#define FLASHEND 0x3FFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 1 + +/* Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_SUT (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_BOOTRST (unsigned char)~_BV(6) +#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SPIEN) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x01 + +#define SLEEP_MODE_IDLE 0 +#define SLEEP_MODE_PWR_DOWN 1 +#define SLEEP_MODE_PWR_SAVE 2 + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_INTERRUPT1 +#pragma GCC poison SIG_INTERRUPT2 +#pragma GCC poison SIG_OUTPUT_COMPARE2 +#pragma GCC poison SIG_OVERFLOW2 +#pragma GCC poison SIG_INPUT_CAPTURE1 +#pragma GCC poison SIG_OUTPUT_COMPARE1A +#pragma GCC poison SIG_OUTPUT_COMPARE1B +#pragma GCC poison SIG_OVERFLOW1 +#pragma GCC poison SIG_OUTPUT_COMPARE0 +#pragma GCC poison SIG_OVERFLOW0 +#pragma GCC poison SIG_SPI +#pragma GCC poison SIG_UART0_RECV +#pragma GCC poison SIG_UART1_RECV +#pragma GCC poison SIG_UART0_DATA +#pragma GCC poison SIG_UART1_DATA +#pragma GCC poison SIG_UART0_TRANS +#pragma GCC poison SIG_UART1_TRANS +#pragma GCC poison SIG_EEPROM_READY +#pragma GCC poison SIG_COMPARATOR + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + + +#endif /* _AVR_IOM161_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom162.h b/hardware/tools/avr/avr/include/avr/iom162.h new file mode 100644 index 0000000000000000000000000000000000000000..08533c9a588846414eb3b3f75a7aecc634cb0d61 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom162.h @@ -0,0 +1,1022 @@ +/* Copyright (c) 2002, Nils Kristian Strom + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom162.h 2230 2011-03-06 02:42:04Z arcanum $ */ + +/* iom162.h - definitions for ATmega162 */ + +#ifndef _AVR_IOM162_H_ +#define _AVR_IOM162_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom162.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Memory mapped I/O registers */ + +/* Timer/Counter3 Control Register A */ +#define TCCR3A _SFR_MEM8(0x8B) + +/* Timer/Counter3 Control Register B */ +#define TCCR3B _SFR_MEM8(0x8A) + +/* Timer/Counter3 - Counter Register */ +#define TCNT3H _SFR_MEM8(0x89) +#define TCNT3L _SFR_MEM8(0x88) +#define TCNT3 _SFR_MEM16(0x88) + +/* Timer/Counter3 - Output Compare Register A */ +#define OCR3AH _SFR_MEM8(0x87) +#define OCR3AL _SFR_MEM8(0x86) +#define OCR3A _SFR_MEM16(0x86) + +/* Timer/Counter3 - Output Compare Register B */ +#define OCR3BH _SFR_MEM8(0x85) +#define OCR3BL _SFR_MEM8(0x84) +#define OCR3B _SFR_MEM16(0x84) + +/* Timer/Counter3 - Input Capture Register */ +#define ICR3H _SFR_MEM8(0x81) +#define ICR3L _SFR_MEM8(0x80) +#define ICR3 _SFR_MEM16(0x80) + +/* Extended Timer/Counter Interrupt Mask */ +#define ETIMSK _SFR_MEM8(0x7D) + +/* Extended Timer/Counter Interrupt Flag Register */ +#define ETIFR _SFR_MEM8(0x7C) + +/* Pin Change Mask Register 1 */ +#define PCMSK1 _SFR_MEM8(0x6C) + +/* Pin Change Mask Register 0 */ +#define PCMSK0 _SFR_MEM8(0x6B) + +/* Clock PRescale */ +#define CLKPR _SFR_MEM8(0x61) + + +/* Standard I/O registers */ + +/* 0x3F SREG */ +/* 0x3D..0x3E SP */ +#define UBRR1H _SFR_IO8(0x3C) /* USART 1 Baud Rate Register High Byte, Shared with UCSR1C */ +#define UCSR1C _SFR_IO8(0x3C) /* USART 1 Control and Status Register, Shared with UBRR1H */ +#define GICR _SFR_IO8(0x3B) /* General Interrupt Control Register */ +#define GIFR _SFR_IO8(0x3A) /* General Interrupt Flag Register */ +#define TIMSK _SFR_IO8(0x39) /* Timer Interrupt Mask */ +#define TIFR _SFR_IO8(0x38) /* Timer Interrupt Flag Register */ +#define SPMCR _SFR_IO8(0x37) /* Store Program Memory Control Register */ +#define EMCUCR _SFR_IO8(0x36) /* Extended MCU Control Register */ +#define MCUCR _SFR_IO8(0x35) /* MCU Control Register */ +#define MCUCSR _SFR_IO8(0x34) /* MCU Control and Status Register */ +#define TCCR0 _SFR_IO8(0x33) /* Timer/Counter 0 Control Register */ +#define TCNT0 _SFR_IO8(0x32) /* TImer/Counter 0 */ +#define OCR0 _SFR_IO8(0x31) /* Output Compare Register 0 */ +#define SFIOR _SFR_IO8(0x30) /* Special Function I/O Register */ +#define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 1 Control Register A */ +#define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register A */ +#define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 High Byte */ +#define TCNT1L _SFR_IO8(0x2C) /* Timer/Counter 1 Low Byte */ +#define TCNT1 _SFR_IO16(0x2C) /* Timer/Counter 1 */ +#define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 Output Compare Register A High Byte */ +#define OCR1AL _SFR_IO8(0x2A) /* Timer/Counter 1 Output Compare Register A Low Byte */ +#define OCR1A _SFR_IO16(0x2A) /* Timer/Counter 1 Output Compare Register A */ +#define OCR1BH _SFR_IO8(0x29) /* Timer/Counter 1 Output Compare Register B High Byte */ +#define OCR1BL _SFR_IO8(0x28) /* Timer/Counter 1 Output Compare Register B Low Byte */ +#define OCR1B _SFR_IO16(0x28) /* Timer/Counter 1 Output Compare Register B */ +#define TCCR2 _SFR_IO8(0x27) /* Timer/Counter 2 Control Register */ +#define ASSR _SFR_IO8(0x26) /* Asynchronous Status Register */ +#define ICR1H _SFR_IO8(0x25) /* Input Capture Register 1 High Byte */ +#define ICR1L _SFR_IO8(0x24) /* Input Capture Register 1 Low Byte */ +#define ICR1 _SFR_IO16(0x24) /* Input Capture Register 1 */ +#define TCNT2 _SFR_IO8(0x23) /* Timer/Counter 2 */ +#define OCR2 _SFR_IO8(0x22) /* Timer/Counter 2 Output Compare Register */ +#define WDTCR _SFR_IO8(0x21) /* Watchdow Timer Control Register */ +#define UBRR0H _SFR_IO8(0x20) /* USART 0 Baud-Rate Register High Byte, Shared with UCSR0C */ +#define UCSR0C _SFR_IO8(0x20) /* USART 0 Control and Status Register C, Shared with UBRR0H */ +#define EEARH _SFR_IO8(0x1F) /* EEPROM Address Register High Byte */ +#define EEARL _SFR_IO8(0x1E) /* EEPROM Address Register Low Byte */ +#define EEAR _SFR_IO16(0x1E) /* EEPROM Address Register */ +#define EEDR _SFR_IO8(0x1D) /* EEPROM Data Register */ +#define EECR _SFR_IO8(0x1C) /* EEPROM Control Register */ +#define PORTA _SFR_IO8(0x1B) /* Port A */ +#define DDRA _SFR_IO8(0x1A) /* Port A Data Direction Register */ +#define PINA _SFR_IO8(0x19) /* Port A Pin Register */ +#define PORTB _SFR_IO8(0x18) /* Port B */ +#define DDRB _SFR_IO8(0x17) /* Port B Data Direction Register */ +#define PINB _SFR_IO8(0x16) /* Port B Pin Register */ +#define PORTC _SFR_IO8(0x15) /* Port C */ +#define DDRC _SFR_IO8(0x14) /* Port C Data Direction Register */ +#define PINC _SFR_IO8(0x13) /* Port C Pin Register */ +#define PORTD _SFR_IO8(0x12) /* Port D */ +#define DDRD _SFR_IO8(0x11) /* Port D Data Direction Register */ +#define PIND _SFR_IO8(0x10) /* Port D Pin Register */ +#define SPDR _SFR_IO8(0x0F) /* SPI Data Register */ +#define SPSR _SFR_IO8(0x0E) /* SPI Status Register */ +#define SPCR _SFR_IO8(0x0D) /* SPI Control Register */ +#define UDR0 _SFR_IO8(0x0C) /* USART 0 Data Register */ +#define UCSR0A _SFR_IO8(0x0B) /* USART 0 Control and Status Register A */ +#define UCSR0B _SFR_IO8(0x0A) /* USART 0 Control and Status Register B */ +#define UBRR0L _SFR_IO8(0x09) /* USART 0 Baud-Rate Register Low Byte */ +#define ACSR _SFR_IO8(0x08) /* Analog Comparator Status Register */ +#define PORTE _SFR_IO8(0x07) /* Port E */ +#define DDRE _SFR_IO8(0x06) /* Port E Data Direction Register */ +#define PINE _SFR_IO8(0x05) /* Port E Pin Register */ +#define OSCCAL _SFR_IO8(0x04) /* Oscillator Calibration, Shared with OCDR */ +#define OCDR _SFR_IO8(0x04) /* On-Chip Debug Register, Shared with OSCCAL */ +#define UDR1 _SFR_IO8(0x03) /* USART 1 Data Register */ +#define UCSR1A _SFR_IO8(0x02) /* USART 1 Control and Status Register A */ +#define UCSR1B _SFR_IO8(0x01) /* USART 1 Control and Status Register B */ +#define UBRR1L _SFR_IO8(0x00) /* USART 0 Baud Rate Register High Byte */ + + +/* Interrupt vectors (byte addresses) */ + +/* External Interrupt Request 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt Request 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* External Interrupt Request 2 */ +#define INT2_vect_num 3 +#define INT2_vect _VECTOR(3) +#define SIG_INTERRUPT2 _VECTOR(3) + +/* Pin Change Interrupt Request 0 */ +#define PCINT0_vect_num 4 +#define PCINT0_vect _VECTOR(4) +#define SIG_PIN_CHANGE0 _VECTOR(4) + +/* Pin Change Interrupt Request 1 */ +#define PCINT1_vect_num 5 +#define PCINT1_vect _VECTOR(5) +#define SIG_PIN_CHANGE1 _VECTOR(5) + +/* Timer/Counter3 Capture Event */ +#define TIMER3_CAPT_vect_num 6 +#define TIMER3_CAPT_vect _VECTOR(6) +#define SIG_INPUT_CAPTURE3 _VECTOR(6) + +/* Timer/Counter3 Compare Match A */ +#define TIMER3_COMPA_vect_num 7 +#define TIMER3_COMPA_vect _VECTOR(7) +#define SIG_OUTPUT_COMPARE3A _VECTOR(7) + +/* Timer/Counter3 Compare Match B */ +#define TIMER3_COMPB_vect_num 8 +#define TIMER3_COMPB_vect _VECTOR(8) +#define SIG_OUTPUT_COMPARE3B _VECTOR(8) + +/* Timer/Counter3 Overflow */ +#define TIMER3_OVF_vect_num 9 +#define TIMER3_OVF_vect _VECTOR(9) +#define SIG_OVERFLOW3 _VECTOR(9) + +/* Timer/Counter2 Compare Match */ +#define TIMER2_COMP_vect_num 10 +#define TIMER2_COMP_vect _VECTOR(10) +#define SIG_OUTPUT_COMPARE2 _VECTOR(10) + +/* Timer/Counter2 Overflow */ +#define TIMER2_OVF_vect_num 11 +#define TIMER2_OVF_vect _VECTOR(11) +#define SIG_OVERFLOW2 _VECTOR(11) + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect_num 12 +#define TIMER1_CAPT_vect _VECTOR(12) +#define SIG_INPUT_CAPTURE1 _VECTOR(12) + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect_num 13 +#define TIMER1_COMPA_vect _VECTOR(13) +#define SIG_OUTPUT_COMPARE1A _VECTOR(13) + +/* Timer/Counter Compare Match B */ +#define TIMER1_COMPB_vect_num 14 +#define TIMER1_COMPB_vect _VECTOR(14) +#define SIG_OUTPUT_COMPARE1B _VECTOR(14) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 15 +#define TIMER1_OVF_vect _VECTOR(15) +#define SIG_OVERFLOW1 _VECTOR(15) + +/* Timer/Counter0 Compare Match */ +#define TIMER0_COMP_vect_num 16 +#define TIMER0_COMP_vect _VECTOR(16) +#define SIG_OUTPUT_COMPARE0 _VECTOR(16) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 17 +#define TIMER0_OVF_vect _VECTOR(17) +#define SIG_OVERFLOW0 _VECTOR(17) + +/* SPI Serial Transfer Complete */ +#define SPI_STC_vect_num 18 +#define SPI_STC_vect _VECTOR(18) +#define SIG_SPI _VECTOR(18) + +/* USART0, Rx Complete */ +#define USART0_RXC_vect_num 19 +#define USART0_RXC_vect _VECTOR(19) +#define SIG_USART0_RECV _VECTOR(19) + +/* USART1, Rx Complete */ +#define USART1_RXC_vect_num 20 +#define USART1_RXC_vect _VECTOR(20) +#define SIG_USART1_RECV _VECTOR(20) + +/* USART0 Data register Empty */ +#define USART0_UDRE_vect_num 21 +#define USART0_UDRE_vect _VECTOR(21) +#define SIG_USART0_DATA _VECTOR(21) + +/* USART1, Data register Empty */ +#define USART1_UDRE_vect_num 22 +#define USART1_UDRE_vect _VECTOR(22) +#define SIG_USART1_DATA _VECTOR(22) + +/* USART0, Tx Complete */ +#define USART0_TXC_vect_num 23 +#define USART0_TXC_vect _VECTOR(23) +#define SIG_USART0_TRANS _VECTOR(23) + +/* USART1, Tx Complete */ +#define USART1_TXC_vect_num 24 +#define USART1_TXC_vect _VECTOR(24) +#define SIG_USART1_TRANS _VECTOR(24) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 25 +#define EE_RDY_vect _VECTOR(25) +#define SIG_EEPROM_READY _VECTOR(25) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 26 +#define ANA_COMP_vect _VECTOR(26) +#define SIG_COMPARATOR _VECTOR(26) + +/* Store Program Memory Read */ +#define SPM_RDY_vect_num 27 +#define SPM_RDY_vect _VECTOR(27) +#define SIG_SPM_READY _VECTOR(27) + +#define _VECTORS_SIZE 112 /* = (num vec+1) * 4 */ + + + + + +/* TCCR3B bit definitions, memory mapped I/O */ + +#define ICNC3 7 +#define ICES3 6 +#define WGM33 4 +#define WGM32 3 +#define CS32 2 +#define CS31 1 +#define CS30 0 + + + +/* TCCR3A bit definitions, memory mapped I/O */ + +#define COM3A1 7 +#define COM3A0 6 +#define COM3B1 5 +#define COM3B0 4 +#define FOC3A 3 +#define FOC3B 2 +#define WGM31 1 +#define WGM30 0 + + + +/* ETIMSK bit definitions, memory mapped I/O */ + +#define TICIE3 5 +#define OCIE3A 4 +#define OCIE3B 3 +#define TOIE3 2 + + + +/* ETIFR bit definitions, memory mapped I/O */ + +#define ICF3 5 +#define OCF3A 4 +#define OCF3B 3 +#define TOV3 2 + + + +/* PCMSK1 bit definitions, memory mapped I/O */ +#define PCINT15 7 +#define PCINT14 6 +#define PCINT13 5 +#define PCINT12 4 +#define PCINT11 3 +#define PCINT10 2 +#define PCINT9 1 +#define PCINT8 0 + + + +/* PCMSK0 bit definitions, memory mapped I/O */ + +#define PCINT7 7 +#define PCINT6 6 +#define PCINT5 5 +#define PCINT4 4 +#define PCINT3 3 +#define PCINT2 2 +#define PCINT1 1 +#define PCINT0 0 + + + +/* CLKPR bit definitions, memory mapped I/O */ + +#define CLKPCE 7 +#define CLKPS3 3 +#define CLKPS2 2 +#define CLKPS1 1 +#define CLKPS0 0 + + + +/* SPH bit definitions */ + +#define SP15 15 +#define SP14 14 +#define SP13 13 +#define SP12 12 +#define SP11 11 +#define SP10 10 +#define SP9 9 +#define SP8 8 + + + +/* SPL bit definitions */ + +#define SP7 7 +#define SP6 6 +#define SP5 5 +#define SP4 4 +#define SP3 3 +#define SP2 2 +#define SP1 1 +#define SP0 0 + + + +/* UBRR1H bit definitions */ + +#define URSEL1 7 +#define UBRR111 3 +#define UBRR110 2 +#define UBRR19 1 +#define UBRR18 0 + + + +/* UCSR1C bit definitions */ + +#define URSEL1 7 +#define UMSEL1 6 +#define UPM11 5 +#define UPM10 4 +#define USBS1 3 +#define UCSZ11 2 +#define UCSZ10 1 +#define UCPOL1 0 + + + +/* GICR bit definitions */ + +#define INT1 7 +#define INT0 6 +#define INT2 5 +#define PCIE1 4 +#define PCIE0 3 +#define IVSEL 1 +#define IVCE 0 + + + +/* GIFR bit definitions */ + +#define INTF1 7 +#define INTF0 6 +#define INTF2 5 +#define PCIF1 4 +#define PCIF0 3 + + + +/* TIMSK bit definitions */ + +#define TOIE1 7 +#define OCIE1A 6 +#define OCIE1B 5 +#define OCIE2 4 +#define TICIE1 3 +#define TOIE2 2 +#define TOIE0 1 +#define OCIE0 0 + + + +/* TIFR bit definitions */ + +#define TOV1 7 +#define OCF1A 6 +#define OCF1B 5 +#define OCF2 4 +#define ICF1 3 +#define TOV2 2 +#define TOV0 1 +#define OCF0 0 + + + +/* SPMCR bit definitions */ + +#define SPMIE 7 +#define RWWSB 6 +#define RWWSRE 4 +#define BLBSET 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 + + + +/* EMCUCR bit definitions */ + +#define SM0 7 +#define SRL2 6 +#define SRL1 5 +#define SRL0 4 +#define SRW01 3 +#define SRW00 2 +#define SRW11 1 +#define ISC2 0 + + + +/* MCUCR bit definitions */ + +#define SRE 7 +#define SRW10 6 +#define SE 5 +#define SM1 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + + + +/* MCUCSR bit definitions */ + +#define JTD 7 +#define SM2 5 +#define JTRF 4 +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + + + +/* TCCR0 bit definitions */ + +#define FOC0 7 +#define WGM00 6 +#define COM01 5 +#define COM00 4 +#define WGM01 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + + + +/* SFIOR bit definitions */ + +#define TSM 7 +#define XMBK 6 +#define XMM2 5 +#define XMM1 4 +#define XMM0 3 +#define PUD 2 +#define PSR2 1 +#define PSR310 0 + + + +/* TCCR1A bit definitions */ + +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define FOC1A 3 +#define FOC1B 2 +#define WGM11 1 +#define WGM10 0 + + + + +/* TCCR1B bit definitions */ + +#define ICNC1 7 /* Input Capture Noise Canceler */ +#define ICES1 6 /* Input Capture Edge Select */ +#define WGM13 4 /* Waveform Generation Mode 3 */ +#define WGM12 3 /* Waveform Generation Mode 2 */ +#define CS12 2 /* Clock Select 2 */ +#define CS11 1 /* Clock Select 1 */ +#define CS10 0 /* Clock Select 0 */ + + + +/* TCCR2 bit definitions */ + +#define FOC2 7 +#define WGM20 6 +#define COM21 5 +#define COM20 4 +#define WGM21 3 +#define CS22 2 +#define CS21 1 +#define CS20 0 + + + +/* ASSR bit definitions */ + +#define AS2 3 +#define TCN2UB 2 +#define TCON2UB 2 /* Kept for backwards compatibility. */ +#define OCR2UB 1 +#define TCR2UB 0 + + + +/* WDTCR bit definitions */ + +#define WDCE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + + + +/* UBRR0H bif definitions */ + +#define URSEL0 7 +#define UBRR011 3 +#define UBRR010 2 +#define UBRR09 1 +#define UBRR08 0 + + + +/* UCSR0C bit definitions */ + +#define URSEL0 7 +#define UMSEL0 6 +#define UPM01 5 +#define UPM00 4 +#define USBS0 3 +#define UCSZ01 2 +#define UCSZ00 1 +#define UCPOL0 0 + + + +/* EEARH bit definitions */ + +#define EEAR8 0 + + + +/* EECR bit definitions */ + +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + + + +/* PORTA bit definitions */ + +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + + + +/* DDRA bit definitions */ + +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + + + +/* PINA bit definitions */ + +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + + +/* PORTB bit definitions */ + +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + + + +/* DDRB bit definitions */ + +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + + + +/* PINB bit definitions */ + +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + + + +/* PORTC bit definitions */ + +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + + + +/* DDRC bit definitions */ + +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + + + +/* PINC bit definitions */ + +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + + + +/* PORTD bit definitions */ + +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + + + +/* DDRD bit definitions */ + +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + + + +/* PIND bit definitions */ + +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + + + +/* SPSR bit definitions */ + +#define SPIF 7 +#define WCOL 6 +#define SPI2X 0 + + + +/* SPCR bit definitions */ + +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + + + +/* UCSR0A bit definitions */ + +#define RXC0 7 +#define TXC0 6 +#define UDRE0 5 +#define FE0 4 +#define DOR0 3 +#define UPE0 2 +#define U2X0 1 +#define MPCM0 0 + + + +/* UCSR0B bit definitions */ + +#define RXCIE0 7 +#define TXCIE0 6 +#define UDRIE0 5 +#define RXEN0 4 +#define TXEN0 3 +#define UCSZ02 2 +#define RXB80 1 +#define TXB80 0 + + + +/* ACSR bit definitions */ + +#define ACD 7 +#define ACBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + + + +/* PORTE bit definitions */ + +#define PE2 2 +#define PE1 1 +#define PE0 0 + + + +/* DDRE bit definitions */ + +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + + + +/* PINE bit definitions */ + +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + + + +/* UCSR1A bit definitions */ + +#define RXC1 7 +#define TXC1 6 +#define UDRE1 5 +#define FE1 4 +#define DOR1 3 +#define UPE1 2 +#define U2X1 1 +#define MPCM1 0 + + + +/* UCSR1B bit definitions */ + +#define RXCIE1 7 +#define TXCIE1 6 +#define UDRIE1 5 +#define RXEN1 4 +#define TXEN1 3 +#define UCSZ12 2 +#define RXB81 1 +#define TXB81 0 + + +/* Constants */ +#define SPM_PAGESIZE 128 +#define RAMSTART 0x100 +#define RAMEND 0x4FF +#define XRAMEND 0xFFFF +#define E2END 0x1FF +#define E2PAGESIZE 4 +#define FLASHEND 0x3FFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + +/* Extended Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) +#define FUSE_M161C (unsigned char)~_BV(4) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x04 + +#define SLEEP_MODE_IDLE 0 +#define SLEEP_MODE_PWR_DOWN 1 +#define SLEEP_MODE_PWR_SAVE 2 +#define SLEEP_MODE_ADC 3 +#define SLEEP_MODE_STANDBY 4 +#define SLEEP_MODE_EXT_STANDBY 5 + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_INTERRUPT1 +#pragma GCC poison SIG_INTERRUPT2 +#pragma GCC poison SIG_PIN_CHANGE0 +#pragma GCC poison SIG_PIN_CHANGE1 +#pragma GCC poison SIG_INPUT_CAPTURE3 +#pragma GCC poison SIG_OUTPUT_COMPARE3A +#pragma GCC poison SIG_OUTPUT_COMPARE3B +#pragma GCC poison SIG_OVERFLOW3 +#pragma GCC poison SIG_OUTPUT_COMPARE2 +#pragma GCC poison SIG_OVERFLOW2 +#pragma GCC poison SIG_INPUT_CAPTURE1 +#pragma GCC poison SIG_OUTPUT_COMPARE1A +#pragma GCC poison SIG_OUTPUT_COMPARE1B +#pragma GCC poison SIG_OVERFLOW1 +#pragma GCC poison SIG_OUTPUT_COMPARE0 +#pragma GCC poison SIG_OVERFLOW0 +#pragma GCC poison SIG_SPI +#pragma GCC poison SIG_USART0_RECV +#pragma GCC poison SIG_USART1_RECV +#pragma GCC poison SIG_USART0_DATA +#pragma GCC poison SIG_USART1_DATA +#pragma GCC poison SIG_USART0_TRANS +#pragma GCC poison SIG_USART1_TRANS +#pragma GCC poison SIG_EEPROM_READY +#pragma GCC poison SIG_COMPARATOR +#pragma GCC poison SIG_SPM_READY + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + + +#endif /* _AVR_IOM162_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom163.h b/hardware/tools/avr/avr/include/avr/iom163.h new file mode 100644 index 0000000000000000000000000000000000000000..160abf36d9bc99549971b75f7a76cafac5c7386f --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom163.h @@ -0,0 +1,686 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom163.h 2231 2011-03-07 05:06:55Z arcanum $ */ + +/* avr/iom163.h - definitions for ATmega163 */ + +#ifndef _AVR_IOM163_H_ +#define _AVR_IOM163_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom163.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +#define TWBR _SFR_IO8(0x00) +#define TWSR _SFR_IO8(0x01) +#define TWAR _SFR_IO8(0x02) +#define TWDR _SFR_IO8(0x03) + +/* ADC */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) +#define ADCSR _SFR_IO8(0x06) +#define ADMUX _SFR_IO8(0x07) + +/* analog comparator */ +#define ACSR _SFR_IO8(0x08) + +/* UART */ +#define UBRR _SFR_IO8(0x09) +#define UCSRB _SFR_IO8(0x0A) +#define UCSRA _SFR_IO8(0x0B) +#define UDR _SFR_IO8(0x0C) + +/* SPI */ +#define SPCR _SFR_IO8(0x0D) +#define SPSR _SFR_IO8(0x0E) +#define SPDR _SFR_IO8(0x0F) + +/* Port D */ +#define PIND _SFR_IO8(0x10) +#define DDRD _SFR_IO8(0x11) +#define PORTD _SFR_IO8(0x12) + +/* Port C */ +#define PINC _SFR_IO8(0x13) +#define DDRC _SFR_IO8(0x14) +#define PORTC _SFR_IO8(0x15) + +/* Port B */ +#define PINB _SFR_IO8(0x16) +#define DDRB _SFR_IO8(0x17) +#define PORTB _SFR_IO8(0x18) + +/* Port A */ +#define PINA _SFR_IO8(0x19) +#define DDRA _SFR_IO8(0x1A) +#define PORTA _SFR_IO8(0x1B) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO16(0x1E) +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +#define UBRRHI _SFR_IO8(0x20) + +#define WDTCR _SFR_IO8(0x21) + +#define ASSR _SFR_IO8(0x22) + +/* Timer 2 */ +#define OCR2 _SFR_IO8(0x23) +#define TCNT2 _SFR_IO8(0x24) +#define TCCR2 _SFR_IO8(0x25) + +/* Timer 1 */ +#define ICR1 _SFR_IO16(0x26) +#define ICR1L _SFR_IO8(0x26) +#define ICR1H _SFR_IO8(0x27) +#define OCR1B _SFR_IO16(0x28) +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) +#define TCCR1B _SFR_IO8(0x2E) +#define TCCR1A _SFR_IO8(0x2F) + +#define SFIOR _SFR_IO8(0x30) + +#define OSCCAL _SFR_IO8(0x31) + +/* Timer 0 */ +#define TCNT0 _SFR_IO8(0x32) +#define TCCR0 _SFR_IO8(0x33) + +#define MCUSR _SFR_IO8(0x34) +#define MCUCR _SFR_IO8(0x35) + +#define TWCR _SFR_IO8(0x36) + +#define SPMCR _SFR_IO8(0x37) + +#define TIFR _SFR_IO8(0x38) +#define TIMSK _SFR_IO8(0x39) + +#define GIFR _SFR_IO8(0x3A) +#define GIMSK _SFR_IO8(0x3B) + +/* 0x3C reserved */ + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* Timer/Counter2 Compare Match */ +#define TIMER2_COMP_vect_num 3 +#define TIMER2_COMP_vect _VECTOR(3) +#define SIG_OUTPUT_COMPARE2 _VECTOR(3) + +/* Timer/Counter2 Overflow */ +#define TIMER2_OVF_vect_num 4 +#define TIMER2_OVF_vect _VECTOR(4) +#define SIG_OVERFLOW2 _VECTOR(4) + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect_num 5 +#define TIMER1_CAPT_vect _VECTOR(5) +#define SIG_INPUT_CAPTURE1 _VECTOR(5) + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect_num 6 +#define TIMER1_COMPA_vect _VECTOR(6) +#define SIG_OUTPUT_COMPARE1A _VECTOR(6) + +/* Timer/Counter1 Compare Match B */ +#define TIMER1_COMPB_vect_num 7 +#define TIMER1_COMPB_vect _VECTOR(7) +#define SIG_OUTPUT_COMPARE1B _VECTOR(7) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 8 +#define TIMER1_OVF_vect _VECTOR(8) +#define SIG_OVERFLOW1 _VECTOR(8) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 9 +#define TIMER0_OVF_vect _VECTOR(9) +#define SIG_OVERFLOW0 _VECTOR(9) + +/* SPI Serial Transfer Complete */ +#define SPI_STC_vect_num 10 +#define SPI_STC_vect _VECTOR(10) +#define SIG_SPI _VECTOR(10) + +/* UART, RX Complete */ +#define UART_RX_vect_num 11 +#define UART_RX_vect _VECTOR(11) +#define SIG_UART_RECV _VECTOR(11) + +/* UART Data Register Empty */ +#define UART_UDRE_vect_num 12 +#define UART_UDRE_vect _VECTOR(12) +#define SIG_UART_DATA _VECTOR(12) + +/* UART, TX Complete */ +#define UART_TX_vect_num 13 +#define UART_TX_vect _VECTOR(13) +#define SIG_UART_TRANS _VECTOR(13) + +/* ADC Conversion Complete */ +#define ADC_vect_num 14 +#define ADC_vect _VECTOR(14) +#define SIG_ADC _VECTOR(14) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 15 +#define EE_RDY_vect _VECTOR(15) +#define SIG_EEPROM_READY _VECTOR(15) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 16 +#define ANA_COMP_vect _VECTOR(16) +#define SIG_COMPARATOR _VECTOR(16) + +/* 2-Wire Serial Interface */ +#define TWI_vect_num 17 +#define TWI_vect _VECTOR(17) +#define SIG_2WIRE_SERIAL _VECTOR(17) + +#define _VECTORS_SIZE 72 + +/* Bit numbers */ + +/* GIMSK */ +#define INT1 7 +#define INT0 6 +/* bit 5 reserved, undefined */ +/* bits 4-0 reserved */ + +/* GIFR */ +#define INTF1 7 +#define INTF0 6 +/* bits 5-0 reserved */ + +/* TIMSK */ +#define OCIE2 7 +#define TOIE2 6 +#define TICIE1 5 +#define OCIE1A 4 +#define OCIE1B 3 +#define TOIE1 2 +/* bit 1 reserved */ +#define TOIE0 0 + +/* TIFR */ +#define OCF2 7 +#define TOV2 6 +#define ICF1 5 +#define OCF1A 4 +#define OCF1B 3 +#define TOV1 2 +/* bit 1 reserved, undefined */ +#define TOV0 0 + +/* SPMCR */ +/* bit 7 reserved */ +#define ASB 6 +/* bit 5 reserved */ +#define ASRE 4 +#define BLBSET 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 + +/* TWCR */ +#define TWINT 7 +#define TWEA 6 +#define TWSTA 5 +#define TWSTO 4 +#define TWWC 3 +#define TWEN 2 +/* bit 1 reserved */ +#define TWIE 0 + +/* TWAR */ +#define TWGCE 0 + +/* TWSR */ +#define TWS7 7 +#define TWS6 6 +#define TWS5 5 +#define TWS4 4 +#define TWS3 3 +/* bits 2-0 reserved */ + +/* MCUCR */ +/* bit 7 reserved */ +#define SE 6 +#define SM1 5 +#define SM0 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/* MCUSR */ +/* bits 7-4 reserved */ +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +/* SFIOR */ +/* bits 7-4 reserved */ +#define ACME 3 +#define PUD 2 +#define PSR2 1 +#define PSR10 0 + +/* TCCR0 */ +/* bits 7-3 reserved */ +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* TCCR2 */ +#define FOC2 7 +#define PWM2 6 +#define COM21 5 +#define COM20 4 +#define CTC2 3 +#define CS22 2 +#define CS21 1 +#define CS20 0 + +/* ASSR */ +/* bits 7-4 reserved */ +#define AS2 3 +#define TCN2UB 2 +#define OCR2UB 1 +#define TCR2UB 0 + +/* TCCR1A */ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define FOC1A 3 +#define FOC1B 2 +#define PWM11 1 +#define PWM10 0 + +/* TCCR1B */ +#define ICNC1 7 +#define ICES1 6 +/* bits 5-4 reserved */ +#define CTC1 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* WDTCR */ +/* bits 7-5 reserved */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* PA7-PA0 = ADC7-ADC0 */ +/* PORTA */ +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* DDRA */ +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +/* PINA */ +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +/* + PB7 = SCK + PB6 = MISO + PB5 = MOSI + PB4 = SS# + PB3 = AIN1 + PB2 = AIN0 + PB1 = T1 + PB0 = T0 + */ + +/* PORTB */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* DDRB */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* PINB */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* + PC7 = TOSC2 + PC6 = TOSC1 + PC1 = SDA + PC0 = SCL + */ +/* PORTC */ +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* DDRC */ +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +/* PINC */ +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +/* + PD7 = OC2 + PD6 = ICP + PD5 = OC1A + PD4 = OC1B + PD3 = INT1 + PD2 = INT0 + PD1 = TXD + PD0 = RXD + */ + +/* PORTD */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* DDRD */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* PIND */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* SPSR */ +#define SPIF 7 +#define WCOL 6 +/* bits 5-1 reserved */ +#define SPI2X 0 + +/* SPCR */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* UCSRA */ +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 +/* bit 2 reserved */ +#define U2X 1 +#define MPCM 0 + +/* UCSRB */ +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define CHR9 2 +#define RXB8 1 +#define TXB8 0 + +/* ACSR */ +#define ACD 7 +#define AINBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +/* ADCSR */ +#define ADEN 7 +#define ADSC 6 +#define ADFR 5 +#define ADIF 4 +#define ADIE 3 +#define ADPS2 2 +#define ADPS1 1 +#define ADPS0 0 + +/* ADMUX */ +#define REFS1 7 +#define REFS0 6 +#define ADLAR 5 +#define MUX4 4 +#define MUX3 3 +#define MUX2 2 +#define MUX1 1 +#define MUX0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define SPM_PAGESIZE 128 +#define RAMSTART 0x60 +#define RAMEND 0x45F +#define XRAMEND RAMEND +#define E2END 0x1FF +#define E2PAGESIZE 0 +#define FLASHEND 0x3FFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 2 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_BODEN (unsigned char)~_BV(6) +#define FUSE_BODLEVEL (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SPIEN) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define HFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x02 + +#define SLEEP_MODE_IDLE 0 +#define SLEEP_MODE_ADC _BV(SM0) +#define SLEEP_MODE_PWR_DOWN _BV(SM1) +#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_INTERRUPT1 +#pragma GCC poison SIG_OUTPUT_COMPARE2 +#pragma GCC poison SIG_OVERFLOW2 +#pragma GCC poison SIG_INPUT_CAPTURE1 +#pragma GCC poison SIG_OUTPUT_COMPARE1A +#pragma GCC poison SIG_OUTPUT_COMPARE1B +#pragma GCC poison SIG_OVERFLOW1 +#pragma GCC poison SIG_OVERFLOW0 +#pragma GCC poison SIG_SPI +#pragma GCC poison SIG_UART_RECV +#pragma GCC poison SIG_UART_DATA +#pragma GCC poison SIG_UART_TRANS +#pragma GCC poison SIG_ADC +#pragma GCC poison SIG_EEPROM_READY +#pragma GCC poison SIG_COMPARATOR +#pragma GCC poison SIG_2WIRE_SERIAL + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + +#endif /* _AVR_IOM163_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom164.h b/hardware/tools/avr/avr/include/avr/iom164.h new file mode 100644 index 0000000000000000000000000000000000000000..0b12b8b75e6703a13fcdad33a0e738e33c104278 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom164.h @@ -0,0 +1,101 @@ +/* Copyright (c) 2005, 2006 Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* avr/iom164.h - definitions for ATmega164 */ + +/* $Id: iom164.h 2115 2010-04-05 23:19:53Z arcanum $ */ + +#ifndef _AVR_IOM164_H_ +#define _AVR_IOM164_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 128 +#define RAMSTART (0x100) +#define RAMEND 0x04FF +#define XRAMEND RAMEND +#define E2END 0x1FF +#define E2PAGESIZE 4 +#define FLASHEND 0x3FFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + +/* Extended Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature (ATmega164P) */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x0A + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +#endif /* _AVR_IOM164_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom164a.h b/hardware/tools/avr/avr/include/avr/iom164a.h new file mode 100644 index 0000000000000000000000000000000000000000..4b9d790ed8bc43ccb1796bc2e523df90705a1abe --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom164a.h @@ -0,0 +1,34 @@ +/***************************************************************************** + * + * Copyright (C) 2011 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + +#include "iom164.h" diff --git a/hardware/tools/avr/avr/include/avr/iom164pa.h b/hardware/tools/avr/avr/include/avr/iom164pa.h new file mode 100644 index 0000000000000000000000000000000000000000..3ecedebbbbd826c9bf3f5c01c96c5cfa64a49d1a --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom164pa.h @@ -0,0 +1,1016 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_ATMEGA164PA_H_INCLUDED +#define _AVR_ATMEGA164PA_H_INCLUDED + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom164pa.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR0 _SFR_IO8(0x2C) +#define SPR00 0 +#define SPR10 1 +#define CPHA0 2 +#define CPOL0 3 +#define MSTR0 4 +#define DORD0 5 +#define SPE0 6 +#define SPIE0 7 + +#define SPSR0 _SFR_IO8(0x2D) +#define SPI2X0 0 +#define WCOL0 6 +#define SPIF0 7 + +#define SPDR0 _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR0 _SFR_MEM8(0x64) +#define PRADC 0 +#define PRSPI 2 +#define PRTIM1 3 +#define PRUSART0 1 +#define PRUSART1 4 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom165.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDE7 7 +#define DDE6 6 +#define DDE5 5 +#define DDE4 4 +#define DDE3 3 +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PE7 7 +#define PE6 6 +#define PE5 5 +#define PE4 4 +#define PE3 3 +#define PE2 2 +#define PE1 1 +#define PE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDF7 7 +#define DDF6 6 +#define DDF5 5 +#define DDF4 4 +#define DDF3 3 +#define DDF2 2 +#define DDF1 1 +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PF7 7 +#define PF6 6 +#define PF5 5 +#define PF4 4 +#define PF3 3 +#define PF2 2 +#define PF1 1 +#define PF0 0 + +#define PING _SFR_IO8(0x12) +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDG4 4 +#define DDG3 3 +#define DDG2 2 +#define DDG1 1 +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PG4 4 +#define PG3 3 +#define PG2 2 +#define PG1 1 +#define PG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 + +/* Reserved [0x18..0x1B] */ + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define PCIF0 6 +#define PCIF1 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define PCIE0 6 +#define PCIE1 7 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0X20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0X22) + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 +#define PSR2 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM0A0 4 +#define COM0A1 5 +#define WGM00 6 +#define FOC0A 7 + +/* Reserved [0x25] */ + +#define TCNT0 _SFR_IO8(0X26) + +#define OCR0A _SFR_IO8(0X27) + +/* Reserved [0x28..0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0X2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCD 7 // The datasheet defines this but IMO it should be OCDR7. +#define OCDR7 7 +#define IDRD 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +#define MCUCR _SFR_IO8(0X35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define JTD 7 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom165a.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +#define DDRA6 6 +#define DDRA5 5 +#define DDRA4 4 +#define DDRA3 3 +#define DDRA2 2 +#define DDRA1 1 +#define DDRA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +#define DDRB6 6 +#define DDRB5 5 +#define DDRB4 4 +#define DDRB3 3 +#define DDRB2 2 +#define DDRB1 1 +#define DDRB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +#define DDRC6 6 +#define DDRC5 5 +#define DDRC4 4 +#define DDRC3 3 +#define DDRC2 2 +#define DDRC1 1 +#define DDRC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +#define DDRD6 6 +#define DDRD5 5 +#define DDRD4 4 +#define DDRD3 3 +#define DDRD2 2 +#define DDRD1 1 +#define DDRD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE7 7 +#define DDRE6 6 +#define DDRE5 5 +#define DDRE4 4 +#define DDRE3 3 +#define DDRE2 2 +#define DDRE1 1 +#define DDRE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDRF7 7 +#define DDRF6 6 +#define DDRF5 5 +#define DDRF4 4 +#define DDRF3 3 +#define DDRF2 2 +#define DDRF1 1 +#define DDRF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_IO8(0x12) +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDRG4 4 +#define DDRG3 3 +#define DDRG2 2 +#define DDRG1 1 +#define DDRG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 + +/* Reserved [0x18..0x1B] */ + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define PCIF0 4 +#define PCIF1 5 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define PCIE0 4 +#define PCIE1 5 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSR310 0 +#define TSM 7 +#define PSR2 1 + +#define TCCR0A _SFR_IO8(0x24) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM0A0 4 +#define COM0A1 5 +#define WGM00 6 +#define FOC0A 7 + +/* Reserved [0x25] */ + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +/* Reserved [0x28..0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 + +#define __AVR_HAVE_PRR ((1< + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom165p.h 2231 2011-03-07 05:06:55Z arcanum $ */ + +/* avr/iom165p.h - definitions for ATmega165P */ + +#ifndef _AVR_IOM165P_H_ +#define _AVR_IOM165P_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom165p.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDE7 7 +#define DDE6 6 +#define DDE5 5 +#define DDE4 4 +#define DDE3 3 +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PE7 7 +#define PE6 6 +#define PE5 5 +#define PE4 4 +#define PE3 3 +#define PE2 2 +#define PE1 1 +#define PE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDF7 7 +#define DDF6 6 +#define DDF5 5 +#define DDF4 4 +#define DDF3 3 +#define DDF2 2 +#define DDF1 1 +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PF7 7 +#define PF6 6 +#define PF5 5 +#define PF4 4 +#define PF3 3 +#define PF2 2 +#define PF1 1 +#define PF0 0 + +#define PING _SFR_IO8(0x12) +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDG4 4 +#define DDG3 3 +#define DDG2 2 +#define DDG1 1 +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PG4 4 +#define PG3 3 +#define PG2 2 +#define PG1 1 +#define PG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 + +/* Reserved [0x18..0x1B] */ + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define PCIF0 6 +#define PCIF1 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define PCIE0 6 +#define PCIE1 7 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0X20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0X22) + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 +#define PSR2 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM0A0 4 +#define COM0A1 5 +#define WGM00 6 +#define FOC0A 7 + +/* Reserved [0x25] */ + +#define TCNT0 _SFR_IO8(0X26) + +#define OCR0A _SFR_IO8(0X27) + +/* Reserved [0x28..0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0X2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCD 7 // The datasheet defines this but IMO it should be OCDR7. +#define OCDR7 7 +#define IDRD 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +#define MCUCR _SFR_IO8(0X35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define JTD 7 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom165pa.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_IO8(0x12) +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 + +/* Reserved [0x18..0x1B] */ + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define PCIF0 4 +#define PCIF1 5 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define PCIE0 4 +#define PCIE1 5 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSR310 0 +#define TSM 7 +#define PSR2 1 + +#define TCCR0A _SFR_IO8(0x24) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM0A0 4 +#define COM0A1 5 +#define WGM00 6 +#define FOC0A 7 + +/* Reserved [0x25] */ + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +/* Reserved [0x28..0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 + +#define __AVR_HAVE_PRR ((1< + +/* Constants */ +#define SPM_PAGESIZE 128 +#define RAMSTART (0x100) +#define RAMEND 0x4FF +#define XRAMEND RAMEND +#define E2END 0x1FF +#define E2PAGESIZE 4 +#define FLASHEND 0x3FFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ +#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ +#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ +#define HFUSE_DEFAULT (FUSE_SPIEN) + +/* Extended Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x06 + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) + +#endif /* _AVR_IOM168_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom168a.h b/hardware/tools/avr/avr/include/avr/iom168a.h new file mode 100644 index 0000000000000000000000000000000000000000..34384348e788e1faa2288f02b71db4e9b5039573 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom168a.h @@ -0,0 +1,35 @@ +/***************************************************************************** + * + * Copyright (C) 2011 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + +#include "iom168.h" +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) diff --git a/hardware/tools/avr/avr/include/avr/iom168p.h b/hardware/tools/avr/avr/include/avr/iom168p.h new file mode 100644 index 0000000000000000000000000000000000000000..78a8e3aa447a24a00ef00f70346c41be0d9f417e --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom168p.h @@ -0,0 +1,942 @@ +/* Copyright (c) 2007 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +/* $Id: iom168p.h 2225 2011-03-02 16:27:26Z arcanum $ */ + +/* avr/iom168p.h - definitions for ATmega168P. */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom168p.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_IOM168P_H_ +#define _AVR_IOM168P_H_ 1 + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 + +#define EEPROM_REG_LOCATIONS 1F2021 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom168pa.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom168pb.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define ACSRB _SFR_IO8(0x0F) +#define ACOE 0 + +/* Reserved [0x10..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< + Eric B. Weddington + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom169.h 2231 2011-03-07 05:06:55Z arcanum $ */ + +/* iom169.h - definitions for ATmega169 */ + +/* This should be up to date with data sheet version 2514J-AVR-12/03. */ + +#ifndef _AVR_IOM169_H_ +#define _AVR_IOM169_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom169.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* Port A */ +#define PINA _SFR_IO8(0x00) +#define DDRA _SFR_IO8(0x01) +#define PORTA _SFR_IO8(0x02) + +/* Port B */ +#define PINB _SFR_IO8(0x03) +#define DDRB _SFR_IO8(0x04) +#define PORTB _SFR_IO8(0x05) + +/* Port C */ +#define PINC _SFR_IO8(0x06) +#define DDRC _SFR_IO8(0x07) +#define PORTC _SFR_IO8(0x08) + +/* Port D */ +#define PIND _SFR_IO8(0x09) +#define DDRD _SFR_IO8(0x0A) +#define PORTD _SFR_IO8(0x0B) + +/* Port E */ +#define PINE _SFR_IO8(0x0C) +#define DDRE _SFR_IO8(0x0D) +#define PORTE _SFR_IO8(0x0E) + +/* Port F */ +#define PINF _SFR_IO8(0x0F) +#define DDRF _SFR_IO8(0x10) +#define PORTF _SFR_IO8(0x11) + +/* Port G */ +#define PING _SFR_IO8(0x12) +#define DDRG _SFR_IO8(0x13) +#define PORTG _SFR_IO8(0x14) + +/* Timer/Counter 0 interrupt Flag Register */ +#define TIFR0 _SFR_IO8(0x15) + +/* Timer/Counter 1 interrupt Flag Register */ +#define TIFR1 _SFR_IO8(0x16) + +/* Timer/Counter 2 interrupt Flag Register */ +#define TIFR2 _SFR_IO8(0x17) + +/* External Interrupt Flag Register */ +#define EIFR _SFR_IO8(0x1C) + +/* External Interrupt Mask Register */ +#define EIMSK _SFR_IO8(0x1D) + +/* General Purpose I/O Register 0 */ +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) + +#define EEDR _SFR_IO8(0X20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0X22) + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +/* General Timer/Counter Control Register */ +#define GTCCR _SFR_IO8(0x23) + +/* Timer/Counter Control Register A */ +#define TCCR0A _SFR_IO8(0x24) + +/* Timer/Counter Register */ +#define TCNT0 _SFR_IO8(0x26) + +/* Output Compare Register A */ +#define OCR0A _SFR_IO8(0x27) + +/* General Purpose I/O Register 1 */ +#define GPIOR1 _SFR_IO8(0x2A) + +/* General Purpose I/O Register 2 */ +#define GPIOR2 _SFR_IO8(0x2B) + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x2C) + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x2D) + +/* SPI Data Register */ +#define SPDR _SFR_IO8(0x2E) + +/* Analog Comperator Control and Status Register */ +#define ACSR _SFR_IO8(0x30) + +/* On-chip Debug Register */ +#define OCDR _SFR_IO8(0x31) + +/* Sleep Mode Control Register */ +#define SMCR _SFR_IO8(0x33) + +/* MCU Status Register */ +#define MCUSR _SFR_IO8(0x34) + +/* MCU Control Rgeister */ +#define MCUCR _SFR_IO8(0x35) + +/* Store Program Memory Control and Status Register */ +#define SPMCSR _SFR_IO8(0x37) + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_MEM8(0x60) + +/* Clock Prescale Register */ +#define CLKPR _SFR_MEM8(0x61) + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRLCD 4 + +#define __AVR_HAVE_PRR ((1< + Eric B. Weddington + Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom169p.h 2231 2011-03-07 05:06:55Z arcanum $ */ + +/* iom169p.h - definitions for ATmega169P */ + +#ifndef _AVR_IOM169P_H_ +#define _AVR_IOM169P_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom169p.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* Port A */ +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* Port B */ +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Port C */ +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* Port D */ +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* Port E */ +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDE7 7 +#define DDE6 6 +#define DDE5 5 +#define DDE4 4 +#define DDE3 3 +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PE7 7 +#define PE6 6 +#define PE5 5 +#define PE4 4 +#define PE3 3 +#define PE2 2 +#define PE1 1 +#define PE0 0 + +/* Port F */ +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDF7 7 +#define DDF6 6 +#define DDF5 5 +#define DDF4 4 +#define DDF3 3 +#define DDF2 2 +#define DDF1 1 +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PF7 7 +#define PF6 6 +#define PF5 5 +#define PF4 4 +#define PF3 3 +#define PF2 2 +#define PF1 1 +#define PF0 0 + +/* Port G */ +#define PING _SFR_IO8(0x12) +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDG4 4 +#define DDG3 3 +#define DDG2 2 +#define DDG1 1 +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PG4 4 +#define PG3 3 +#define PG2 2 +#define PG1 1 +#define PG0 0 + +/* Timer/Counter 0 interrupt Flag Register */ +#define TIFR0 _SFR_IO8(0x15) +#define OCF0A 1 +#define TOV0 0 + +/* Timer/Counter 1 interrupt Flag Register */ +#define TIFR1 _SFR_IO8(0x16) +#define ICF1 5 +#define OCF1B 2 +#define OCF1A 1 +#define TOV1 0 + +/* Timer/Counter 2 interrupt Flag Register */ +#define TIFR2 _SFR_IO8(0x17) +#define OCF2A 1 +#define TOV2 0 + +/* External Interrupt Flag Register */ +#define EIFR _SFR_IO8(0x1C) +#define PCIF1 7 +#define PCIF0 6 +#define INTF0 0 + +/* External Interrupt Mask Register */ +#define EIMSK _SFR_IO8(0x1D) +#define PCIE1 7 +#define PCIE0 6 +#define INT0 0 + +/* General Purpose I/O Register 0 */ +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +#define EEDR _SFR_IO8(0X20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0X22) + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +/* General Timer/Counter Control Register */ +#define GTCCR _SFR_IO8(0x23) +#define TSM 7 +#define PSR2 1 +#define PSR10 0 + +/* Timer/Counter Control Register A */ +#define TCCR0A _SFR_IO8(0x24) +#define FOC0A 7 +#define WGM00 6 +#define COM0A1 5 +#define COM0A0 4 +#define WGM01 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* Timer/Counter Register */ +#define TCNT0 _SFR_IO8(0x26) + +/* Output Compare Register A */ +#define OCR0A _SFR_IO8(0x27) + +/* General Purpose I/O Register 1 */ +#define GPIOR1 _SFR_IO8(0x2A) + +/* General Purpose I/O Register 2 */ +#define GPIOR2 _SFR_IO8(0x2B) + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x2C) +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x2D) +#define SPIF 7 +#define WCOL 6 +#define SPI2X 0 + +/* SPI Data Register */ +#define SPDR _SFR_IO8(0x2E) + +/* Analog Comperator Control and Status Register */ +#define ACSR _SFR_IO8(0x30) +#define ACD 7 +#define ACBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +/* On-chip Debug Register */ +#define OCDR _SFR_IO8(0x31) +#define IDRD 7 +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Sleep Mode Control Register */ +#define SMCR _SFR_IO8(0x33) +#define SM2 3 +#define SM1 2 +#define SM0 1 +#define SE 0 + +/* MCU Status Register */ +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +/* MCU Control Rgeister */ +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define PUD 4 +#define IVSEL 1 +#define IVCE 0 + +/* Store Program Memory Control and Status Register */ +#define SPMCSR _SFR_IO8(0x37) +#define SPMIE 7 +#define RWWSB 6 +#define RWWSRE 4 +#define BLBSET 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_MEM8(0x60) +#define WDCE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* Clock Prescale Register */ +#define CLKPR _SFR_MEM8(0x61) +#define CLKPCE 7 +#define CLKPS3 3 +#define CLKPS2 2 +#define CLKPS1 1 +#define CLKPS0 0 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRLCD 4 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom169pa.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega169PA_H_ +#define _AVR_ATmega169PA_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINA _SFR_IO8(0x00) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 +#define PINA4 4 +#define PINA5 5 +#define PINA6 6 +#define PINA7 7 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 +#define PORTA4 4 +#define PORTA5 5 +#define PORTA6 6 +#define PORTA7 7 + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define PINE _SFR_IO8(0x0C) +#define PINE0 0 +#define PINE1 1 +#define PINE2 2 +#define PINE3 3 +#define PINE4 4 +#define PINE5 5 +#define PINE6 6 +#define PINE7 7 + +#define DDRE _SFR_IO8(0x0D) +#define DDE0 0 +#define DDE1 1 +#define DDE2 2 +#define DDE3 3 +#define DDE4 4 +#define DDE5 5 +#define DDE6 6 +#define DDE7 7 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE0 0 +#define PORTE1 1 +#define PORTE2 2 +#define PORTE3 3 +#define PORTE4 4 +#define PORTE5 5 +#define PORTE6 6 +#define PORTE7 7 + +#define PINF _SFR_IO8(0x0F) +#define PINF0 0 +#define PINF1 1 +#define PINF2 2 +#define PINF3 3 +#define PINF4 4 +#define PINF5 5 +#define PINF6 6 +#define PINF7 7 + +#define DDRF _SFR_IO8(0x10) +#define DDF0 0 +#define DDF1 1 +#define DDF2 2 +#define DDF3 3 +#define DDF4 4 +#define DDF5 5 +#define DDF6 6 +#define DDF7 7 + +#define PORTF _SFR_IO8(0x11) +#define PORTF0 0 +#define PORTF1 1 +#define PORTF2 2 +#define PORTF3 3 +#define PORTF4 4 +#define PORTF5 5 +#define PORTF6 6 +#define PORTF7 7 + +#define PING _SFR_IO8(0x12) +#define PING0 0 +#define PING1 1 +#define PING2 2 +#define PING3 3 +#define PING4 4 +#define PING5 5 + +#define DDRG _SFR_IO8(0x13) +#define DDG0 0 +#define DDG1 1 +#define DDG2 2 +#define DDG3 3 +#define DDG4 4 +#define DDG5 5 + +#define PORTG _SFR_IO8(0x14) +#define PORTG0 0 +#define PORTG1 1 +#define PORTG2 2 +#define PORTG3 3 +#define PORTG4 4 +#define PORTG5 5 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define PCIF0 4 +#define PCIF1 5 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define PCIE0 4 +#define PCIE1 5 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 + +#define GTCCR _SFR_IO8(0x23) +#define PSR310 0 +#define PSR2 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM0A0 4 +#define COM0A1 5 +#define WGM00 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A0 0 +#define OCR0A1 1 +#define OCR0A2 2 +#define OCR0A3 3 +#define OCR0A4 4 +#define OCR0A5 5 +#define OCR0A6 6 +#define OCR0A7 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 +#define JTD 7 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRLCD 4 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom16a.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega16A_H_ +#define _AVR_ATmega16A_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define TWBR _SFR_IO8(0x00) +#define TWBR0 0 +#define TWBR1 1 +#define TWBR2 2 +#define TWBR3 3 +#define TWBR4 4 +#define TWBR5 5 +#define TWBR6 6 +#define TWBR7 7 + +#define TWSR _SFR_IO8(0x01) +#define TWPS0 0 +#define TWPS1 1 +#define TWS3 3 +#define TWS4 4 +#define TWS5 5 +#define TWS6 6 +#define TWS7 7 + +#define TWAR _SFR_IO8(0x02) +#define TWGCE 0 +#define TWA0 1 +#define TWA1 2 +#define TWA2 3 +#define TWA3 4 +#define TWA4 5 +#define TWA5 6 +#define TWA6 7 + +#define TWDR _SFR_IO8(0x03) +#define TWD0 0 +#define TWD1 1 +#define TWD2 2 +#define TWD3 3 +#define TWD4 4 +#define TWD5 5 +#define TWD6 6 +#define TWD7 7 + +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) + +#define ADCL _SFR_IO8(0x04) +#define ADCL0 0 +#define ADCL1 1 +#define ADCL2 2 +#define ADCL3 3 +#define ADCL4 4 +#define ADCL5 5 +#define ADCL6 6 +#define ADCL7 7 + +#define ADCH _SFR_IO8(0x05) +#define ADCH0 0 +#define ADCH1 1 +#define ADCH2 2 +#define ADCH3 3 +#define ADCH4 4 +#define ADCH5 5 +#define ADCH6 6 +#define ADCH7 7 + +#define ADCSRA _SFR_IO8(0x06) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +#define ADMUX _SFR_IO8(0x07) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define MUX4 4 +#define ADLAR 5 +#define REFS0 6 +#define REFS1 7 + +#define ACSR _SFR_IO8(0x08) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define UBRRL _SFR_IO8(0x09) +#define UBRR0 0 +#define UBRR1 1 +#define UBRR2 2 +#define UBRR3 3 +#define UBRR4 4 +#define UBRR5 5 +#define UBRR6 6 +#define UBRR7 7 + +#define UCSRB _SFR_IO8(0x0A) +#define TXB8 0 +#define RXB8 1 +#define UCSZ2 2 +#define TXEN 3 +#define RXEN 4 +#define UDRIE 5 +#define TXCIE 6 +#define RXCIE 7 + +#define UCSRA _SFR_IO8(0x0B) +#define MPCM 0 +#define U2X 1 +#define UPE 2 +#define DOR 3 +#define FE 4 +#define UDRE 5 +#define TXC 6 +#define RXC 7 + +#define UDR _SFR_IO8(0x0C) +#define UDR0 0 +#define UDR1 1 +#define UDR2 2 +#define UDR3 3 +#define UDR4 4 +#define UDR5 5 +#define UDR6 6 +#define UDR7 7 + +#define SPCR _SFR_IO8(0x0D) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x0E) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x0F) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define PIND _SFR_IO8(0x10) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x11) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x12) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define PINC _SFR_IO8(0x13) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x14) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x15) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PINB _SFR_IO8(0x16) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x17) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x18) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINA _SFR_IO8(0x19) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 +#define PINA4 4 +#define PINA5 5 +#define PINA6 6 +#define PINA7 7 + +#define DDRA _SFR_IO8(0x1A) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x1B) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 +#define PORTA4 4 +#define PORTA5 5 +#define PORTA6 6 +#define PORTA7 7 + +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0x1D) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x1E) + +#define EEARL _SFR_IO8(0x1E) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x1F) +#define EEAR8 0 + +#define UBRRH _SFR_IO8(0x20) +#define UBRR8 0 +#define UBRR9 1 +#define UBRR10 2 +#define UBRR11 3 + +#define UCSRC _SFR_IO8(0x20) +#define UCPOL 0 +#define UCSZ0 1 +#define UCSZ1 2 +#define USBS 3 +#define UPM0 4 +#define UPM1 5 +#define UMSEL 6 +#define URSEL 7 + +#define WDTCR _SFR_IO8(0x21) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDTOE 4 + +#define ASSR _SFR_IO8(0x22) +#define TCR2UB 0 +#define OCR2UB 1 +#define TCN2UB 2 +#define AS2 3 + +#define OCR2 _SFR_IO8(0x23) +#define OCR2_0 0 +#define OCR2_1 1 +#define OCR2_2 2 +#define OCR2_3 3 +#define OCR2_4 4 +#define OCR2_5 5 +#define OCR2_6 6 +#define OCR2_7 7 + +#define TCNT2 _SFR_IO8(0x24) +#define TCNT2_0 0 +#define TCNT2_1 1 +#define TCNT2_2 2 +#define TCNT2_3 3 +#define TCNT2_4 4 +#define TCNT2_5 5 +#define TCNT2_6 6 +#define TCNT2_7 7 + +#define TCCR2 _SFR_IO8(0x25) +#define CS20 0 +#define CS21 1 +#define CS22 2 +#define WGM21 3 +#define COM20 4 +#define COM21 5 +#define WGM20 6 +#define FOC2 7 + +#define ICR1 _SFR_IO16(0x26) + +#define ICR1L _SFR_IO8(0x26) +#define ICR1L0 0 +#define ICR1L1 1 +#define ICR1L2 2 +#define ICR1L3 3 +#define ICR1L4 4 +#define ICR1L5 5 +#define ICR1L6 6 +#define ICR1L7 7 + +#define ICR1H _SFR_IO8(0x27) +#define ICR1H0 0 +#define ICR1H1 1 +#define ICR1H2 2 +#define ICR1H3 3 +#define ICR1H4 4 +#define ICR1H5 5 +#define ICR1H6 6 +#define ICR1H7 7 + +#define OCR1B _SFR_IO16(0x28) + +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BL0 0 +#define OCR1BL1 1 +#define OCR1BL2 2 +#define OCR1BL3 3 +#define OCR1BL4 4 +#define OCR1BL5 5 +#define OCR1BL6 6 +#define OCR1BL7 7 + +#define OCR1BH _SFR_IO8(0x29) +#define OCR1BH0 0 +#define OCR1BH1 1 +#define OCR1BH2 2 +#define OCR1BH3 3 +#define OCR1BH4 4 +#define OCR1BH5 5 +#define OCR1BH6 6 +#define OCR1BH7 7 + +#define OCR1A _SFR_IO16(0x2A) + +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AL0 0 +#define OCR1AL1 1 +#define OCR1AL2 2 +#define OCR1AL3 3 +#define OCR1AL4 4 +#define OCR1AL5 5 +#define OCR1AL6 6 +#define OCR1AL7 7 + +#define OCR1AH _SFR_IO8(0x2B) +#define OCR1AH0 0 +#define OCR1AH1 1 +#define OCR1AH2 2 +#define OCR1AH3 3 +#define OCR1AH4 4 +#define OCR1AH5 5 +#define OCR1AH6 6 +#define OCR1AH7 7 + +#define TCNT1 _SFR_IO16(0x2C) + +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1L0 0 +#define TCNT1L1 1 +#define TCNT1L2 2 +#define TCNT1L3 3 +#define TCNT1L4 4 +#define TCNT1L5 5 +#define TCNT1L6 6 +#define TCNT1L7 7 + +#define TCNT1H _SFR_IO8(0x2D) +#define TCNT1H0 0 +#define TCNT1H1 1 +#define TCNT1H2 2 +#define TCNT1H3 3 +#define TCNT1H4 4 +#define TCNT1H5 5 +#define TCNT1H6 6 +#define TCNT1H7 7 + +#define TCCR1B _SFR_IO8(0x2E) +#define CS10 0 +#define CS11 1 +#define CS12 2 +#define WGM12 3 +#define WGM13 4 +#define ICES1 6 +#define ICNC1 7 + +#define TCCR1A _SFR_IO8(0x2F) +#define WGM10 0 +#define WGM11 1 +#define FOC1B 2 +#define FOC1A 3 +#define COM1B0 4 +#define COM1B1 5 +#define COM1A0 6 +#define COM1A1 7 + +#define SFIOR _SFR_IO8(0x30) +#define PSR10 0 +#define PSR2 1 +#define PUD 2 +#define ACME 3 +#define ADTS0 5 +#define ADTS1 6 +#define ADTS2 7 + +#define OSCCAL _SFR_IO8(0x31) +#define CAL0 0 +#define CAL1 1 +#define CAL2 2 +#define CAL3 3 +#define CAL4 4 +#define CAL5 5 +#define CAL6 6 +#define CAL7 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +#define TCNT0 _SFR_IO8(0x32) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define TCCR0 _SFR_IO8(0x33) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM00 4 +#define COM01 5 +#define WGM00 6 +#define FOC0 7 + +#define MCUCSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 +#define ISC2 6 +#define JTD 7 + +#define MCUCR _SFR_IO8(0x35) +#define ISC00 0 +#define ISC01 1 +#define ISC10 2 +#define ISC11 3 +#define SM0 4 +#define SM1 5 +#define SE 6 +#define SM2 7 + +#define TWCR _SFR_IO8(0x36) +#define TWIE 0 +#define TWEN 2 +#define TWWC 3 +#define TWSTO 4 +#define TWSTA 5 +#define TWEA 6 +#define TWINT 7 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +#define TIFR _SFR_IO8(0x38) +#define TOV0 0 +#define OCF0 1 +#define TOV1 2 +#define OCF1B 3 +#define OCF1A 4 +#define ICF1 5 +#define TOV2 6 +#define OCF2 7 + +#define TIMSK _SFR_IO8(0x39) +#define TOIE0 0 +#define OCIE0 1 +#define TOIE1 2 +#define OCIE1B 3 +#define OCIE1A 4 +#define TICIE1 5 +#define TOIE2 6 +#define OCIE2 7 + +#define GIFR _SFR_IO8(0x3A) +#define INTF2 5 +#define INTF0 6 +#define INTF1 7 + +#define GICR _SFR_IO8(0x3B) +#define IVCE 0 +#define IVSEL 1 +#define INT2 5 +#define INT0 6 +#define INT1 7 + +#define OCR0 _SFR_IO8(0x3C) +#define OCR0_0 0 +#define OCR0_1 1 +#define OCR0_2 2 +#define OCR0_3 3 +#define OCR0_4 4 +#define OCR0_5 5 +#define OCR0_6 6 +#define OCR0_7 7 + + +/* Interrupt vectors */ +/* Vector 0 is the reset vector */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +#define TIMER2_COMP_vect_num 3 +#define TIMER2_COMP_vect _VECTOR(3) /* Timer/Counter2 Compare Match */ +#define TIMER2_OVF_vect_num 4 +#define TIMER2_OVF_vect _VECTOR(4) /* Timer/Counter2 Overflow */ +#define TIMER1_CAPT_vect_num 5 +#define TIMER1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */ +#define TIMER1_COMPA_vect_num 6 +#define TIMER1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPB_vect_num 7 +#define TIMER1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */ +#define TIMER1_OVF_vect_num 8 +#define TIMER1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */ +#define TIMER0_OVF_vect_num 9 +#define TIMER0_OVF_vect _VECTOR(9) /* Timer/Counter0 Overflow */ +#define SPI_STC_vect_num 10 +#define SPI_STC_vect _VECTOR(10) /* Serial Transfer Complete */ + +/* The following vectors use an inconsistent (to the ATmega16 etc.) + naming scheme. The inconsistent names are preserved here for softwares + that already use them: */ +#define USARTRXC_vect_num 11 +#define USARTRXC_vect _VECTOR(11) /* USART, Rx Complete */ +#define USARTUDRE_vect_num 12 +#define USARTUDRE_vect _VECTOR(12) /* USART Data Register Empty */ +#define USARTTXC_vect_num 13 +#define USARTTXC_vect _VECTOR(13) /* USART, Tx Complete */ +/* The "classic" designators: */ +#define USART_RXC_vect_num 11 +#define USART_RXC_vect _VECTOR(11) /* USART, Rx Complete */ +#define USART_UDRE_vect_num 12 +#define USART_UDRE_vect _VECTOR(12) /* USART Data Register Empty */ +#define USART_TXC_vect_num 13 +#define USART_TXC_vect _VECTOR(13) /* USART, Tx Complete */ + +#define ADC_vect_num 14 +#define ADC_vect _VECTOR(14) /* ADC Conversion Complete */ +#define EE_RDY_vect_num 15 +#define EE_RDY_vect _VECTOR(15) /* EEPROM Ready */ +#define ANA_COMP_vect_num 16 +#define ANA_COMP_vect _VECTOR(16) /* Analog Comparator */ +#define TWI_vect_num 17 +#define TWI_vect _VECTOR(17) /* 2-wire Serial Interface */ +#define INT2_vect_num 18 +#define INT2_vect _VECTOR(18) /* External Interrupt Request 2 */ +#define TIMER0_COMP_vect_num 19 +#define TIMER0_COMP_vect _VECTOR(19) /* Timer/Counter0 Compare Match */ +#define SPM_RDY_vect_num 20 +#define SPM_RDY_vect _VECTOR(20) /* Store Program Memory Ready */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (21 * _VECTOR_SIZE) + + +/* Constants */ +#define SPM_PAGESIZE (128) +#define RAMSTART (0x60) +#define RAMSIZE (1024) +#define RAMEND (RAMSTART + RAMSIZE - 1) +#define XRAMSTART (NA) +#define XRAMSIZE (0) +#define XRAMEND (RAMEND) +#define E2END (0x1FF) +#define E2PAGESIZE (4) +#define FLASHEND (0x3FFF) + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 2 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +#define FUSE_BODEN (unsigned char)~_BV(6) /* Brown out detector enable */ +#define FUSE_BODLEVEL (unsigned char)~_BV(7) /* Brown out detector trigger level */ +#define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +#define FUSE_CKOPT (unsigned char)~_BV(4) /* Oscillator Options */ +#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ +#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ +#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x03 + + +/* Device Pin Definitions */ +#define MOSI_DDR DDRB +#define MOSI_PORT PORTB +#define MOSI_PIN PINB +#define MOSI_BIT 5 + +#define MISO_DDR DDRB +#define MISO_PORT PORTB +#define MISO_PIN PINB +#define MISO_BIT 6 + +#define PB7_SCK_DDR DDRB7_SCK +#define PB7_SCK_PORT PORTB7_SCK +#define PB7_SCK_PIN PINB7_SCK +#define PB7_SCK_BIT 7_SCK + +#define RXD_DDR DDRD +#define RXD_PORT PORTD +#define RXD_PIN PIND +#define RXD_BIT 0 + +#define TXD_DDR DDRD +#define TXD_PORT PORTD +#define TXD_PIN PIND +#define TXD_BIT 1 + +#define INT0_DDR DDRD +#define INT0_PORT PORTD +#define INT0_PIN PIND +#define INT0_BIT 2 + +#define INT1_DDR DDRD +#define INT1_PORT PORTD +#define INT1_PIN PIND +#define INT1_BIT 3 + +#define OC1B_DDR DDRD +#define OC1B_PORT PORTD +#define OC1B_PIN PIND +#define OC1B_BIT 4 + +#define OC1A_DDR DDRD +#define OC1A_PORT PORTD +#define OC1A_PIN PIND +#define OC1A_BIT 5 + +#define ICP_DDR DDRD +#define ICP_PORT PORTD +#define ICP_PIN PIND +#define ICP_BIT 6 + +#define OC2_DDR DDRD +#define OC2_PORT PORTD +#define OC2_PIN PIND +#define OC2_BIT 7 + +#define SCL_DDR DDRC +#define SCL_PORT PORTC +#define SCL_PIN PINC +#define SCL_BIT 0 + +#define SDA_DDR DDRC +#define SDA_PORT PORTC +#define SDA_PIN PINC +#define SDA_BIT 1 + +#define PC3_DDR DDRC +#define PC3_PORT PORTC +#define PC3_PIN PINC +#define PC3_BIT 3 + +#define PC4_DDR DDRC +#define PC4_PORT PORTC +#define PC4_PIN PINC +#define PC4_BIT 4 + +#define PC5_DDR DDRC +#define PC5_PORT PORTC +#define PC5_PIN PINC +#define PC5_BIT 5 + +#define ADC7_DDR DDRA +#define ADC7_PORT PORTA +#define ADC7_PIN PINA +#define ADC7_BIT 7 + +#define ADC6_DDR DDRA +#define ADC6_PORT PORTA +#define ADC6_PIN PINA +#define ADC6_BIT 6 + +#define ADc5_DDR DDRA +#define ADc5_PORT PORTA +#define ADc5_PIN PINA +#define ADc5_BIT 5 + +#define ADC4_DDR DDRA +#define ADC4_PORT PORTA +#define ADC4_PIN PINA +#define ADC4_BIT 4 + +#define ADC3_DDR DDRA +#define ADC3_PORT PORTA +#define ADC3_PIN PINA +#define ADC3_BIT 3 + +#define ADC2_DDR DDRA +#define ADC2_PORT PORTA +#define ADC2_PIN PINA +#define ADC2_BIT 2 + +#define ADC1_DDR DDRA +#define ADC1_PORT PORTA +#define ADC1_PIN PINA +#define ADC1_BIT 1 + +#define ADC0_DDR DDRA +#define ADC0_PORT PORTA +#define ADC0_PIN PINA +#define ADC0_BIT 0 + +#define T0_DDR DDRB +#define T0_PORT PORTB +#define T0_PIN PINB +#define T0_BIT 0 + +#define T1_DDR DDRB +#define T1_PORT PORTB +#define T1_PIN PINB +#define T1_BIT 1 + +#define AIN0_DDR DDRB +#define AIN0_PORT PORTB +#define AIN0_PIN PINB +#define AIN0_BIT 2 + +#define AIN1_DDR DDRB +#define AIN1_PORT PORTB +#define AIN1_PIN PINB +#define AIN1_BIT 3 + +#define SS_DDR DDRB +#define SS_PORT PORTB +#define SS_PIN PINB +#define SS_BIT 4 + +#define SLEEP_MODE_IDLE (0x00<<4) +#define SLEEP_MODE_ADC (0x01<<4) +#define SLEEP_MODE_PWR_DOWN (0x02<<4) +#define SLEEP_MODE_PWR_SAVE (0x03<<4) +#define SLEEP_MODE_STANDBY (0x0A<<4) +#define SLEEP_MODE_EXT_STANDBY (0x0B<<4) + +#endif /* _AVR_ATmega16A_H_ */ + diff --git a/hardware/tools/avr/avr/include/avr/iom16hva.h b/hardware/tools/avr/avr/include/avr/iom16hva.h new file mode 100644 index 0000000000000000000000000000000000000000..ba1caaf4cff0363727489634b00fad890a9ca1cf --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom16hva.h @@ -0,0 +1,80 @@ +/* Copyright (c) 2007, Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom16hva.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ + +/* iom16hva.h - definitions for ATmega16HVA. */ + +#ifndef _AVR_IOM16HVA_H_ +#define _AVR_IOM16HVA_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 128 +#define RAMSTART 0x100 +#define RAMEND 0x2FF +#define XRAMEND RAMEND +#define E2END 0xFF +#define E2PAGESIZE 4 +#define FLASHEND 0x3FFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 1 + +/* Low Fuse Byte */ +#define FUSE_SUT0 (unsigned char)~_BV(0) +#define FUSE_SUT1 (unsigned char)~_BV(1) +#define FUSE_SUT2 (unsigned char)~_BV(2) +#define FUSE_SELFPRGEN (unsigned char)~_BV(3) +#define FUSE_DWEN (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_EESAVE (unsigned char)~_BV(6) +#define FUSE_WDTON (unsigned char)~_BV(7) +#define FUSE_DEFAULT (FUSE_SPIEN) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x0C + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_PWR_OFF (0x04<<1) + +#endif /* _AVR_IOM16HVA_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom16hva2.h b/hardware/tools/avr/avr/include/avr/iom16hva2.h new file mode 100644 index 0000000000000000000000000000000000000000..2ca27e5afa61b2c3668a27f0b656f8a18557b6bd --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom16hva2.h @@ -0,0 +1,883 @@ +/* Copyright (c) 2009 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom16hva2.h 2192 2010-11-08 13:53:24Z arcanum $ */ + +/* avr/iom16hva2.h - definitions for ATmega16HVA2 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom16hva2.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega16HVA2_H_ +#define _AVR_ATmega16HVA2_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINA _SFR_IO8(0x00) +#define PINA0 0 +#define PINA1 1 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 + +#define PORTA _SFR_IO8(0x02) +#define PORTA0 0 +#define PORTA1 1 + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define ICF0 3 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 3 + +#define OSICSR _SFR_IO8(0x17) +#define OSIEN 0 +#define OSIST 1 +#define OSISEL0 4 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define ICS0 3 +#define ICES0 4 +#define ICNC0 5 +#define ICEN0 6 +#define TCW0 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 + +#define TCNT0 _SFR_IO16(0x26) + +#define TCNT0L _SFR_IO8(0x26) +#define TCNT0L0 0 +#define TCNT0L1 1 +#define TCNT0L2 2 +#define TCNT0L3 3 +#define TCNT0L4 4 +#define TCNT0L5 5 +#define TCNT0L6 6 +#define TCNT0L7 7 + +#define TCNT0H _SFR_IO8(0x27) +#define TCNT0H0 0 +#define TCNT0H1 1 +#define TCNT0H2 2 +#define TCNT0H3 3 +#define TCNT0H4 4 +#define TCNT0H5 5 +#define TCNT0H6 6 +#define TCNT0H7 7 + +#define OCR0A _SFR_IO8(0x28) +#define OCR0A0 0 +#define OCR0A1 1 +#define OCR0A2 2 +#define OCR0A3 3 +#define OCR0A4 4 +#define OCR0A5 5 +#define OCR0A6 6 +#define OCR0A7 7 + +#define OCR0B _SFR_IO8(0x29) +#define OCR0B0 0 +#define OCR0B1 1 +#define OCR0B2 2 +#define OCR0B3 3 +#define OCR0B4 4 +#define OCR0B5 5 +#define OCR0B6 6 +#define OCR0B7 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define DWDR _SFR_IO8(0x31) + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BODRF 2 +#define WDRF 3 +#define OCDRF 4 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define CKOE 5 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define SIGRD 5 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPCE 7 + +#define PRR0 _SFR_MEM8(0x64) +#define PRVADC 0 +#define PRTIM0 1 +#define PRTIM1 2 +#define PRSPI 3 +#define PRVRM 5 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom16hvb.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega16HVB_H_ +#define _AVR_ATmega16HVB_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINA _SFR_IO8(0x00) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 + +#define PORTA _SFR_IO8(0x02) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define ICF0 3 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 3 + +#define OSICSR _SFR_IO8(0x17) +#define OSIEN 0 +#define OSIST 1 +#define OSISEL0 4 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define ICS0 3 +#define ICES0 4 +#define ICNC0 5 +#define ICEN0 6 +#define TCW0 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 + +#define TCNT0 _SFR_IO16(0x26) + +#define TCNT0L _SFR_IO8(0x26) +#define TCNT0L0 0 +#define TCNT0L1 1 +#define TCNT0L2 2 +#define TCNT0L3 3 +#define TCNT0L4 4 +#define TCNT0L5 5 +#define TCNT0L6 6 +#define TCNT0L7 7 + +#define TCNT0H _SFR_IO8(0x27) +#define TCNT0H0 0 +#define TCNT0H1 1 +#define TCNT0H2 2 +#define TCNT0H3 3 +#define TCNT0H4 4 +#define TCNT0H5 5 +#define TCNT0H6 6 +#define TCNT0H7 7 + +#define OCR0A _SFR_IO8(0x28) +#define OCR0A0 0 +#define OCR0A1 1 +#define OCR0A2 2 +#define OCR0A3 3 +#define OCR0A4 4 +#define OCR0A5 5 +#define OCR0A6 6 +#define OCR0A7 7 + +#define OCR0B _SFR_IO8(0x29) +#define OCR0B0 0 +#define OCR0B1 1 +#define OCR0B2 2 +#define OCR0B3 3 +#define OCR0B4 4 +#define OCR0B5 5 +#define OCR0B6 6 +#define OCR0B7 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define DWDR _SFR_IO8(0x31) + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BODRF 2 +#define WDRF 3 +#define OCDRF 4 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define CKOE 5 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define LBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPCE 7 + +#define PRR0 _SFR_MEM8(0x64) +#define PRVADC 0 +#define PRTIM0 1 +#define PRTIM1 2 +#define PRSPI 3 +#define PRVRM 5 +#define PRTWI 6 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom16hvbrevb.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega16HVBREVB_H_ +#define _AVR_ATmega16HVBREVB_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINA _SFR_IO8(0x00) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 + +#define PORTA _SFR_IO8(0x02) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define ICF0 3 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 3 + +#define OSICSR _SFR_IO8(0x17) +#define OSIEN 0 +#define OSIST 1 +#define OSISEL0 4 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define ICS0 3 +#define ICES0 4 +#define ICNC0 5 +#define ICEN0 6 +#define TCW0 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 + +#define TCNT0 _SFR_IO16(0x26) + +#define TCNT0L _SFR_IO8(0x26) +#define TCNT0L0 0 +#define TCNT0L1 1 +#define TCNT0L2 2 +#define TCNT0L3 3 +#define TCNT0L4 4 +#define TCNT0L5 5 +#define TCNT0L6 6 +#define TCNT0L7 7 + +#define TCNT0H _SFR_IO8(0x27) +#define TCNT0H0 0 +#define TCNT0H1 1 +#define TCNT0H2 2 +#define TCNT0H3 3 +#define TCNT0H4 4 +#define TCNT0H5 5 +#define TCNT0H6 6 +#define TCNT0H7 7 + +#define OCR0A _SFR_IO8(0x28) +#define OCR0A0 0 +#define OCR0A1 1 +#define OCR0A2 2 +#define OCR0A3 3 +#define OCR0A4 4 +#define OCR0A5 5 +#define OCR0A6 6 +#define OCR0A7 7 + +#define OCR0B _SFR_IO8(0x29) +#define OCR0B0 0 +#define OCR0B1 1 +#define OCR0B2 2 +#define OCR0B3 3 +#define OCR0B4 4 +#define OCR0B5 5 +#define OCR0B6 6 +#define OCR0B7 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define DWDR _SFR_IO8(0x31) + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BODRF 2 +#define WDRF 3 +#define OCDRF 4 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define CKOE 5 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define LBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPCE 7 + +#define PRR0 _SFR_MEM8(0x64) +#define PRVADC 0 +#define PRTIM0 1 +#define PRTIM1 2 +#define PRSPI 3 +#define PRVRM 5 +#define PRTWI 6 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom16m1.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega16M1_H_ +#define _AVR_ATmega16M1_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define PINE _SFR_IO8(0x0C) +#define PINE0 0 +#define PINE1 1 +#define PINE2 2 + +#define DDRE _SFR_IO8(0x0D) +#define DDE0 0 +#define DDE1 1 +#define DDE2 2 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE0 0 +#define PORTE1 1 +#define PORTE2 2 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define GPIOR1 _SFR_IO8(0x19) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x1A) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 + +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 +#define PSRSYNC 0 +#define ICPSEL1 6 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 +#define PLLE 1 +#define PLLF 2 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define AC0O 0 +#define AC1O 1 +#define AC2O 2 +#define AC3O 3 +#define AC0IF 4 +#define AC1IF 5 +#define AC2IF 6 +#define AC3IF 7 + +#define DWDR _SFR_IO8(0x31) + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define SPIPS 7 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRLIN 1 +#define PRSPI 2 +#define PRTIM0 3 +#define PRTIM1 4 +#define PRPSC 5 +#define PRCAN 6 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom16u2.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega16U2_H_ +#define _AVR_ATmega16U2_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define OCF1C 3 +#define ICF1 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 +#define EEAR10 2 +#define EEAR11 3 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 +#define PLLE 1 +#define PLLP0 2 +#define PLLP1 3 +#define PLLP2 4 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define DWDR _SFR_IO8(0x31) +#define DWDR0 0 +#define DWDR1 1 +#define DWDR2 2 +#define DWDR3 3 +#define DWDR4 4 +#define DWDR5 5 +#define DWDR6 6 +#define DWDR7 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define USBRF 5 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define EIND _SFR_IO8(0x3C) +#define EIND0 0 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define WDTCKD _SFR_MEM8(0x62) +#define WCLKD0 0 +#define WCLKD1 1 +#define WDEWIE 2 +#define WDEWIF 3 + +#define REGCR _SFR_MEM8(0x63) +#define REGDIS 0 + +#define PRR0 _SFR_MEM8(0x64) +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom16u4.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega16U4_H_ +#define _AVR_ATmega16U4_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define PINE _SFR_IO8(0x0C) +#define PINE2 2 +#define PINE6 6 + +#define DDRE _SFR_IO8(0x0D) +#define DDE2 2 +#define DDE6 6 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE2 2 +#define PORTE6 6 + +#define PINF _SFR_IO8(0x0F) +#define PINF0 0 +#define PINF1 1 +#define PINF4 4 +#define PINF5 5 +#define PINF6 6 +#define PINF7 7 + +#define DDRF _SFR_IO8(0x10) +#define DDF0 0 +#define DDF1 1 +#define DDF4 4 +#define DDF5 5 +#define DDF6 6 +#define DDF7 7 + +#define PORTF _SFR_IO8(0x11) +#define PORTF0 0 +#define PORTF1 1 +#define PORTF4 4 +#define PORTF5 5 +#define PORTF6 6 +#define PORTF7 7 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define OCF1C 3 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define OCF3C 3 +#define ICF3 5 + +#define TIFR4 _SFR_IO8(0x19) +#define TOV4 2 +#define OCF4B 5 +#define OCF4A 6 +#define OCF4D 7 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 +#define EEAR10 2 +#define EEAR11 3 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCROA_0 0 +#define OCROA_1 1 +#define OCROA_2 2 +#define OCROA_3 3 +#define OCROA_4 4 +#define OCROA_5 5 +#define OCROA_6 6 +#define OCROA_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 +#define PLLE 1 +#define PINDIV 4 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +#define PLLFRQ _SFR_IO8(0x32) +#define PDIV0 0 +#define PDIV1 1 +#define PDIV2 2 +#define PDIV3 3 +#define PLLTM0 4 +#define PLLTM1 5 +#define PLLUSB 6 +#define PINMUX 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define JTD 7 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define RAMPZ _SFR_IO8(0x3B) +#define RAMPZ0 0 + +#define EIND _SFR_IO8(0x3C) +#define EIND0 0 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR0 _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR0 ((1< + +/* Constants */ +#define SPM_PAGESIZE 256 +#define RAMSTART 0x200 +#define RAMEND 0x21FF +#define XRAMEND 0xFFFF +#define E2END 0xFFF +#define E2PAGESIZE 8 +#define FLASHEND 0x3FFFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + +/* Extended Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x98 +#define SIGNATURE_2 0x01 + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +#endif /* _AVR_IOM2560_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom2561.h b/hardware/tools/avr/avr/include/avr/iom2561.h new file mode 100644 index 0000000000000000000000000000000000000000..cd065c590a904e2c1d7d3bef8e03f619e0ba1553 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom2561.h @@ -0,0 +1,101 @@ +/* Copyright (c) 2005 Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id */ + +/* avr/iom2561.h - definitions for ATmega2561 */ + +#ifndef _AVR_IOM2561_H_ +#define _AVR_IOM2561_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 256 +#define RAMSTART 0x200 +#define RAMEND 0x21FF +#define XRAMEND 0xFFFF +#define E2END 0xFFF +#define E2PAGESIZE 8 +#define FLASHEND 0x3FFFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + +/* Extended Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x98 +#define SIGNATURE_2 0x02 + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +#endif /* _AVR_IOM2561_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom2564rfr2.h b/hardware/tools/avr/avr/include/avr/iom2564rfr2.h new file mode 100644 index 0000000000000000000000000000000000000000..3870f8a870f809c0edaeac424010cbe7a22968c1 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom2564rfr2.h @@ -0,0 +1,2691 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_ATMEGA2564RFR2_H_INCLUDED +#define _AVR_ATMEGA2564RFR2_H_INCLUDED + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom2564rfr2.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_IO8(0x12) +#define PING7 7 +#define PING6 6 +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDRG7 7 +// Inserted "DDG7" from "DDRG7" due to compatibility +#define DDG7 7 +#define DDRG6 6 +// Inserted "DDG6" from "DDRG6" due to compatibility +#define DDG6 6 +#define DDRG5 5 +// Inserted "DDG5" from "DDRG5" due to compatibility +#define DDG5 5 +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PORTG7 7 +#define PORTG6 6 +#define PORTG5 5 +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define Res0 3 +#define Res1 4 +#define Res2 5 +#define Res3 6 +#define Res4 7 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define OCF1C 3 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define OCF3C 3 +#define ICF3 5 + +#define TIFR4 _SFR_IO8(0x19) +#define TOV4 0 +#define OCF4A 1 +#define OCF4B 2 +#define OCF4C 3 +#define ICF4 5 + +#define TIFR5 _SFR_IO8(0x1A) +#define TOV5 0 +#define OCF5A 1 +#define OCF5B 2 +#define OCF5C 3 +#define ICF5 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3A] */ + +#define RAMPZ _SFR_IO8(0x3B) +#define RAMPZ0 0 +#define RAMPZ1 1 +#define Res5 7 + +#define EIND _SFR_IO8(0x3C) + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62] */ + +#define PRR2 _SFR_MEM8(0x63) +#define PRRAM0 0 +#define PRRAM1 1 +#define PRRAM2 2 +#define PRRAM3 3 + +#define __AVR_HAVE_PRR2 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom256rfr2.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_IO8(0x12) +#define PING7 7 +#define PING6 6 +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDRG7 7 +// Inserted "DDG7" from "DDRG7" due to compatibility +#define DDG7 7 +#define DDRG6 6 +// Inserted "DDG6" from "DDRG6" due to compatibility +#define DDG6 6 +#define DDRG5 5 +// Inserted "DDG5" from "DDRG5" due to compatibility +#define DDG5 5 +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PORTG7 7 +#define PORTG6 6 +#define PORTG5 5 +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define Res0 3 +#define Res1 4 +#define Res2 5 +#define Res3 6 +#define Res4 7 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define OCF1C 3 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define OCF3C 3 +#define ICF3 5 + +#define TIFR4 _SFR_IO8(0x19) +#define TOV4 0 +#define OCF4A 1 +#define OCF4B 2 +#define OCF4C 3 +#define ICF4 5 + +#define TIFR5 _SFR_IO8(0x1A) +#define TOV5 0 +#define OCF5A 1 +#define OCF5B 2 +#define OCF5C 3 +#define ICF5 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3A] */ + +#define RAMPZ _SFR_IO8(0x3B) +#define RAMPZ0 0 +#define RAMPZ1 1 +#define Res5 7 + +#define EIND _SFR_IO8(0x3C) + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62] */ + +#define PRR2 _SFR_MEM8(0x63) +#define PRRAM0 0 +#define PRRAM1 1 +#define PRRAM2 2 +#define PRRAM3 3 + +#define __AVR_HAVE_PRR2 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom3000.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_IOM3000_H_ +#define _AVR_IOM3000_H_ 1 + +/* Registers and associated bit numbers */ + +#define IPD _SFR_IO16(0x00) +#define IPDL _SFR_IO8(0x00) +#define IPDH _SFR_IO8(0x01) +#define IPA _SFR_IO16(0x02) +#define IPAL _SFR_IO8(0x02) +#define IPAH _SFR_IO8(0x03) +#define IPCR _SFR_IO8(0x04) +#define ADRSLT _SFR_IO16(0x05) +#define ADRSLTL _SFR_IO8(0x05) /* Alias. */ +#define ADRSLTH _SFR_IO8(0x06) /* Alias. */ +#define ADRSLTLO _SFR_IO8(0x05) /* Name according to datasheet. */ +#define ADRSLTHI _SFR_IO8(0x06) /* Name according to datasheet. */ +#define ADCSR _SFR_IO8(0x07) +#define AMUXCTL _SFR_IO8(0x0B) +#define MSPCR _SFR_IO8(0x0C) +#define USPCR _SFR_IO8(0x0C) +#define MSPSR _SFR_IO8(0x0D) +#define USPSR _SFR_IO8(0x0D) +#define MSPDR _SFR_IO8(0x0E) +#define USPDR _SFR_IO8(0x0E) +#define WDTCR _SFR_IO8(0x0F) +#define USR _SFR_IO8(0x11) +#define UCRA _SFR_IO8(0x12) +#define UCRB _SFR_IO8(0x13) +#define UBRR _SFR_IO8(0x14) +#define UBRRL _SFR_IO8(0x14) /* Alias. */ +#define UBRRH _SFR_IO8(0x15) /* Alias. */ +#define UBRRLO _SFR_IO8(0x14) /* Name according to datasheet. */ +#define UBRRHI _SFR_IO8(0x15) /* Name according to datasheet. */ +#define GIFR _SFR_IO8(0x16) +#define GIMSK _SFR_IO8(0x17) +#define DACVAL _SFR_IO16(0x18) +#define DACVALL _SFR_IO8(0x18) /* Alias. */ +#define DACVALH _SFR_IO8(0x19) /* Alias. */ +#define DACVALLO _SFR_IO8(0x18) /* Name according to datasheet. */ +#define DACVALHI _SFR_IO8(0x19) /* Name according to datasheet. */ +#define BGPPIN _SFR_IO8(0x1A) +#define BGPDDR _SFR_IO8(0x1B) +#define BGPPORT _SFR_IO8(0x1C) +#define AGPPIN _SFR_IO8(0x1D) +#define AGPDDR _SFR_IO8(0x1E) +#define AGPPORT _SFR_IO8(0x1F) +#define EXTCCR1A _SFR_IO8(0x20) +#define EXTCCR1B _SFR_IO8(0x21) +#define EXTCNT1 _SFR_IO16(0x22) +#define EXTCNT1L _SFR_IO8(0x22) +#define EXTCNT1H _SFR_IO8(0x23) +#define EXOCR1A _SFR_IO16(0x24) +#define EXOCR1AL _SFR_IO8(0x24) +#define EXOCR1AH _SFR_IO8(0x25) +#define EXOCR1B _SFR_IO16(0x26) +#define EXOCR1BL _SFR_IO8(0x26) +#define EXOCR1BH _SFR_IO8(0x27) +#define EXTIFR _SFR_IO8(0x2A) +#define EXTIMSK _SFR_IO8(0x2B) +#define EXTCNT _SFR_IO8(0x2C) +#define EXTCCR0 _SFR_IO8(0x2D) +#define CGPPIN _SFR_IO8(0x30) +#define CGPDDR _SFR_IO8(0x31) +#define CGPPORT _SFR_IO8(0x32) +#define MCSR _SFR_IO8(0x33) + + +#define CDIVCAN _SFR_MEM8(0x100) +#define CBTR1 _SFR_MEM8(0x101) +#define CBTR2 _SFR_MEM8(0x102) +#define CBTR3 _SFR_MEM8(0x103) +#define CMCR _SFR_MEM8(0x104) +#define CRAFEN _SFR_MEM8(0x105) +#define CTARR _SFR_MEM8(0x106) +#define CIER _SFR_MEM8(0x107) +#define CCFLG _SFR_MEM8(0x108) +#define CCISR _SFR_MEM8(0x109) +#define CIDAH0 _SFR_MEM8(0x10A) +#define CIDAH1 _SFR_MEM8(0x10B) +#define CEFR _SFR_MEM8(0x10C) +#define CRXERR _SFR_MEM8(0x10D) +#define CTXERR _SFR_MEM8(0x10E) +#define CVER _SFR_MEM8(0x10F) +#define CIDAC0R _SFR_MEM32(0x110) +#define CIDM0R _SFR_MEM32(0x114) +#define CIDAC1R _SFR_MEM32(0x118) +#define CIDM1R _SFR_MEM32(0x11C) +#define CIDAC2R _SFR_MEM32(0x120) +#define CIDM2R _SFR_MEM32(0x124) +#define CIDAC3R _SFR_MEM32(0x128) +#define CIDM3R _SFR_MEM32(0x12C) +#define CIDAC4R _SFR_MEM32(0x130) +#define CIDM4R _SFR_MEM32(0x134) +#define CIDAC5R _SFR_MEM32(0x138) +#define CIDM5R _SFR_MEM32(0x13C) +#define CIDAC6R _SFR_MEM32(0x140) +#define CIDM6R _SFR_MEM32(0x144) +#define CTXB0 ((volatile uint8_t [16])(0x150)) +#define CTXB1 ((volatile uint8_t [16])(0x160)) +#define CTXB2 ((volatile uint8_t [16])(0x170)) +#define CRXB0 ((volatile uint8_t [16])(0x180)) +#define CRXB1 ((volatile uint8_t [16])(0x190)) +#define PWMMSK _SFR_MEM8(0x200) +#define PWMPER _SFR_MEM8(0x201) +#define PWMSFRQ _SFR_MEM8(0x202) +#define PWMCTL _SFR_MEM8(0x203) +#define CURIRUN _SFR_MEM8(0x204) +#define CURIRED _SFR_MEM8(0x205) +#define CURRDLY _SFR_MEM16(0x206) +#define VELLOW1 _SFR_MEM8(0x208) +#define VELLOW2 _SFR_MEM8(0x209) +#define VELLOW3 _SFR_MEM8(0x20A) +#define VELHI1 _SFR_MEM8(0x20B) +#define VELHI2 _SFR_MEM8(0x20C) +#define VELHI3 _SFR_MEM8(0x20D) +#define VELDEC1 _SFR_MEM8(0x20E) +#define VELDEC2 _SFR_MEM8(0x20F) +#define VELDEC3 _SFR_MEM8(0x210) +#define VELACC1 _SFR_MEM8(0x211) +#define VELACC2 _SFR_MEM8(0x212) +#define VELACC3 _SFR_MEM8(0x213) +#define VELCVEL _SFR_MEM8(0x214) +/* +#define VELCVEL _SFR_MEM8(0x215) +#define VELCVEL _SFR_MEM8(0x216) +*/ +#define VELTVEL _SFR_MEM8(0x217) +/* +#define VELTVEL _SFR_MEM8(0x218) +#define VELTVEL _SFR_MEM8(0x219) +*/ +#define VELVGCTL _SFR_MEM8(0x21A) +#define VELSTB _SFR_MEM8(0x21B) +#define VELIFLG _SFR_MEM8(0x21C) +#define VELIMSK _SFR_MEM8(0x21D) +#define IDXTRT _SFR_MEM32(0x21E) +#define IDXENT _SFR_MEM32(0x222) +#define IDXMSDT _SFR_MEM16(0x226) +#define IDXPOT _SFR_MEM32(0x228) +#define IDXPOS _SFR_MEM32(0x22C) +#define IDXENC _SFR_MEM32(0x230) +#define IDXCTRL _SFR_MEM8(0x234) +#define IDXSTRB _SFR_MEM8(0x235) +#define IDXCPTP _SFR_MEM32(0x236) +#define IDXIFLG _SFR_MEM8(0x23A) +#define IDXIMSK _SFR_MEM8(0x23B) +#define SCIO _SFR_MEM8(0x23C) +#define SCSW _SFR_MEM8(0x23D) +#define SCRF _SFR_MEM32(0x23E) +#define IOF _SFR_MEM8(0x242) +#define MSELR _SFR_MEM8(0x243) +#define STAT _SFR_MEM8(0x244) +#define SPWMCTL _SFR_MEM8(0x245) +#define SINDAC _SFR_MEM16(0x280) +#define SINDACL _SFR_MEM8(0x280) +#define SINDACH _SFR_MEM8(0x281) +#define COSDAC _SFR_MEM8(0x282) +#define COSDACL _SFR_MEM8(0x282) +#define COSDACH _SFR_MEM8(0x283) +#define GAINDAC _SFR_MEM8(0x284) +#define DACCTRL _SFR_MEM8(0x285) +#define INTCCR1A _SFR_MEM8(0x800) +#define INTCCR1B _SFR_MEM8(0x801) +#define INTCNT1 _SFR_MEM16(0x802) +#define INTCNT1L _SFR_MEM8(0x802) +#define INTCNT1H _SFR_MEM8(0x803) +#define INOCR1A _SFR_MEM16(0x804) +#define INOCR1AL _SFR_MEM8(0x804) +#define INOCR1AH _SFR_MEM8(0x805) +#define INOCR1B _SFR_MEM16(0x806) /* Data sheet says 0x807-0x808, but I believe this is wrong due to conflict with INTCNT. */ +#define INOCR1BL _SFR_MEM8(0x806) +#define INOCR1BH _SFR_MEM8(0x807) +#define INTCNT _SFR_MEM8(0x808) +#define INTCCR0 _SFR_MEM8(0x809) +#define INTIFR _SFR_MEM8(0x80A) +#define INTIMSK _SFR_MEM8(0x80B) + + +/* Constants */ +#define RAMSTART 0x1000 +#define RAMEND 0x1FFF /* Last On-Chip SRAM Location */ +#define E2END 0x0 +#define E2PAGESIZE 0 +#define FLASHEND 0xFFFF +#define _VECTORS_SIZE 0 + + +#endif /* _AVR_IOM3000_H_ */ + diff --git a/hardware/tools/avr/avr/include/avr/iom32.h b/hardware/tools/avr/avr/include/avr/iom32.h new file mode 100644 index 0000000000000000000000000000000000000000..11b9d4e365d7c306c53356776ba7f3db2cf300e2 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom32.h @@ -0,0 +1,755 @@ +/* Copyright (c) 2002, Steinar Haugen + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom32.h 2233 2011-03-15 15:49:50Z arcanum $ */ + +/* avr/iom32.h - definitions for ATmega32 */ + +#ifndef _AVR_IOM32_H_ +#define _AVR_IOM32_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom32.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ +#define TWBR _SFR_IO8(0x00) +#define TWSR _SFR_IO8(0x01) +#define TWAR _SFR_IO8(0x02) +#define TWDR _SFR_IO8(0x03) + +/* ADC */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) +#define ADCSRA _SFR_IO8(0x06) +#define ADMUX _SFR_IO8(0x07) + +/* analog comparator */ +#define ACSR _SFR_IO8(0x08) + +/* USART */ +#define UBRRL _SFR_IO8(0x09) +#define UCSRB _SFR_IO8(0x0A) +#define UCSRA _SFR_IO8(0x0B) +#define UDR _SFR_IO8(0x0C) + +/* SPI */ +#define SPCR _SFR_IO8(0x0D) +#define SPSR _SFR_IO8(0x0E) +#define SPDR _SFR_IO8(0x0F) + +/* Port D */ +#define PIND _SFR_IO8(0x10) +#define DDRD _SFR_IO8(0x11) +#define PORTD _SFR_IO8(0x12) + +/* Port C */ +#define PINC _SFR_IO8(0x13) +#define DDRC _SFR_IO8(0x14) +#define PORTC _SFR_IO8(0x15) + +/* Port B */ +#define PINB _SFR_IO8(0x16) +#define DDRB _SFR_IO8(0x17) +#define PORTB _SFR_IO8(0x18) + +/* Port A */ +#define PINA _SFR_IO8(0x19) +#define DDRA _SFR_IO8(0x1A) +#define PORTA _SFR_IO8(0x1B) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO16(0x1E) +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +#define UBRRH _SFR_IO8(0x20) +#define UCSRC UBRRH + +#define WDTCR _SFR_IO8(0x21) + +#define ASSR _SFR_IO8(0x22) + +/* Timer 2 */ +#define OCR2 _SFR_IO8(0x23) +#define TCNT2 _SFR_IO8(0x24) +#define TCCR2 _SFR_IO8(0x25) + +/* Timer 1 */ +#define ICR1 _SFR_IO16(0x26) +#define ICR1L _SFR_IO8(0x26) +#define ICR1H _SFR_IO8(0x27) +#define OCR1B _SFR_IO16(0x28) +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) +#define TCCR1B _SFR_IO8(0x2E) +#define TCCR1A _SFR_IO8(0x2F) + +#define SFIOR _SFR_IO8(0x30) + +#define OSCCAL _SFR_IO8(0x31) +#define OCDR OSCCAL + +/* Timer 0 */ +#define TCNT0 _SFR_IO8(0x32) +#define TCCR0 _SFR_IO8(0x33) + +#define MCUSR _SFR_IO8(0x34) +#define MCUCSR MCUSR +#define MCUCR _SFR_IO8(0x35) + +#define TWCR _SFR_IO8(0x36) + +#define SPMCR _SFR_IO8(0x37) + +#define TIFR _SFR_IO8(0x38) +#define TIMSK _SFR_IO8(0x39) + +#define GIFR _SFR_IO8(0x3A) +#define GIMSK _SFR_IO8(0x3B) +#define GICR GIMSK + +#define OCR0 _SFR_IO8(0x3C) + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt Request 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt Request 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* External Interrupt Request 2 */ +#define INT2_vect_num 3 +#define INT2_vect _VECTOR(3) +#define SIG_INTERRUPT2 _VECTOR(3) + +/* Timer/Counter2 Compare Match */ +#define TIMER2_COMP_vect_num 4 +#define TIMER2_COMP_vect _VECTOR(4) +#define SIG_OUTPUT_COMPARE2 _VECTOR(4) + +/* Timer/Counter2 Overflow */ +#define TIMER2_OVF_vect_num 5 +#define TIMER2_OVF_vect _VECTOR(5) +#define SIG_OVERFLOW2 _VECTOR(5) + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect_num 6 +#define TIMER1_CAPT_vect _VECTOR(6) +#define SIG_INPUT_CAPTURE1 _VECTOR(6) + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect_num 7 +#define TIMER1_COMPA_vect _VECTOR(7) +#define SIG_OUTPUT_COMPARE1A _VECTOR(7) + +/* Timer/Counter1 Compare Match B */ +#define TIMER1_COMPB_vect_num 8 +#define TIMER1_COMPB_vect _VECTOR(8) +#define SIG_OUTPUT_COMPARE1B _VECTOR(8) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 9 +#define TIMER1_OVF_vect _VECTOR(9) +#define SIG_OVERFLOW1 _VECTOR(9) + +/* Timer/Counter0 Compare Match */ +#define TIMER0_COMP_vect_num 10 +#define TIMER0_COMP_vect _VECTOR(10) +#define SIG_OUTPUT_COMPARE0 _VECTOR(10) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 11 +#define TIMER0_OVF_vect _VECTOR(11) +#define SIG_OVERFLOW0 _VECTOR(11) + +/* Serial Transfer Complete */ +#define SPI_STC_vect_num 12 +#define SPI_STC_vect _VECTOR(12) +#define SIG_SPI _VECTOR(12) + +/* USART, Rx Complete */ +#define USART_RXC_vect_num 13 +#define USART_RXC_vect _VECTOR(13) +#define SIG_USART_RECV _VECTOR(13) +#define SIG_UART_RECV _VECTOR(13) + +/* USART Data Register Empty */ +#define USART_UDRE_vect_num 14 +#define USART_UDRE_vect _VECTOR(14) +#define SIG_USART_DATA _VECTOR(14) +#define SIG_UART_DATA _VECTOR(14) + +/* USART, Tx Complete */ +#define USART_TXC_vect_num 15 +#define USART_TXC_vect _VECTOR(15) +#define SIG_USART_TRANS _VECTOR(15) +#define SIG_UART_TRANS _VECTOR(15) + +/* ADC Conversion Complete */ +#define ADC_vect_num 16 +#define ADC_vect _VECTOR(16) +#define SIG_ADC _VECTOR(16) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 17 +#define EE_RDY_vect _VECTOR(17) +#define SIG_EEPROM_READY _VECTOR(17) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 18 +#define ANA_COMP_vect _VECTOR(18) +#define SIG_COMPARATOR _VECTOR(18) + +/* 2-wire Serial Interface */ +#define TWI_vect_num 19 +#define TWI_vect _VECTOR(19) +#define SIG_2WIRE_SERIAL _VECTOR(19) + +/* Store Program Memory Ready */ +#define SPM_RDY_vect_num 20 +#define SPM_RDY_vect _VECTOR(20) +#define SIG_SPM_READY _VECTOR(20) + +#define _VECTORS_SIZE 84 + +/* Bit numbers */ + +/* GICR */ +#define INT1 7 +#define INT0 6 +#define INT2 5 +#define IVSEL 1 +#define IVCE 0 + +/* GIFR */ +#define INTF1 7 +#define INTF0 6 +#define INTF2 5 + +/* TIMSK */ +#define OCIE2 7 +#define TOIE2 6 +#define TICIE1 5 +#define OCIE1A 4 +#define OCIE1B 3 +#define TOIE1 2 +#define OCIE0 1 +#define TOIE0 0 + +/* TIFR */ +#define OCF2 7 +#define TOV2 6 +#define ICF1 5 +#define OCF1A 4 +#define OCF1B 3 +#define TOV1 2 +#define OCF0 1 +#define TOV0 0 + +/* SPMCR */ +#define SPMIE 7 +#define RWWSB 6 +/* bit 5 reserved */ +#define RWWSRE 4 +#define BLBSET 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 + +/* TWCR */ +#define TWINT 7 +#define TWEA 6 +#define TWSTA 5 +#define TWSTO 4 +#define TWWC 3 +#define TWEN 2 +/* bit 1 reserved */ +#define TWIE 0 + +/* TWAR */ +#define TWA6 7 +#define TWA5 6 +#define TWA4 5 +#define TWA3 4 +#define TWA2 3 +#define TWA1 2 +#define TWA0 1 +#define TWGCE 0 + +/* TWSR */ +#define TWS7 7 +#define TWS6 6 +#define TWS5 5 +#define TWS4 4 +#define TWS3 3 +/* bit 2 reserved */ +#define TWPS1 1 +#define TWPS0 0 + +/* MCUCR */ +#define SE 7 +#define SM2 6 +#define SM1 5 +#define SM0 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/* MCUCSR */ +#define JTD 7 +#define ISC2 6 +/* bit 5 reserved */ +#define JTRF 4 +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +/* SFIOR */ +#define ADTS2 7 +#define ADTS1 6 +#define ADTS0 5 +/* bit 4 reserved */ +#define ACME 3 +#define PUD 2 +#define PSR2 1 +#define PSR10 0 + +/* TCCR0 */ +#define FOC0 7 +#define WGM00 6 +#define COM01 5 +#define COM00 4 +#define WGM01 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* TCCR2 */ +#define FOC2 7 +#define WGM20 6 +#define COM21 5 +#define COM20 4 +#define WGM21 3 +#define CS22 2 +#define CS21 1 +#define CS20 0 + +/* ASSR */ +/* bits 7-4 reserved */ +#define AS2 3 +#define TCN2UB 2 +#define OCR2UB 1 +#define TCR2UB 0 + +/* TCCR1A */ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define FOC1A 3 +#define FOC1B 2 +#define WGM11 1 +#define WGM10 0 + +/* TCCR1B */ +#define ICNC1 7 +#define ICES1 6 +/* bit 5 reserved */ +#define WGM13 4 +#define WGM12 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* WDTCR */ +/* bits 7-5 reserved */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* PA7-PA0 = ADC7-ADC0 */ +/* PORTA */ +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* DDRA */ +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +/* PINA */ +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +/* + PB7 = SCK + PB6 = MISO + PB5 = MOSI + PB4 = SS# + PB3 = OC0/AIN1 + PB2 = INT2/AIN0 + PB1 = T1 + PB0 = XCK/T0 + */ + +/* PORTB */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* DDRB */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* PINB */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* + PC7 = TOSC2 + PC6 = TOSC1 + PC1 = SDA + PC0 = SCL + */ +/* PORTC */ +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* DDRC */ +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +/* PINC */ +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +/* + PD7 = OC2 + PD6 = ICP + PD5 = OC1A + PD4 = OC1B + PD3 = INT1 + PD2 = INT0 + PD1 = TXD + PD0 = RXD + */ + +/* PORTD */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* DDRD */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* PIND */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* SPSR */ +#define SPIF 7 +#define WCOL 6 +/* bits 5-1 reserved */ +#define SPI2X 0 + +/* SPCR */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* UCSRA */ +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 +#define PE 2 +#define U2X 1 +#define MPCM 0 + +/* UCSRB */ +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define UCSZ2 2 +#define RXB8 1 +#define TXB8 0 + +/* UCSRC */ +#define URSEL 7 +#define UMSEL 6 +#define UPM1 5 +#define UPM0 4 +#define USBS 3 +#define UCSZ1 2 +#define UCSZ0 1 +#define UCPOL 0 + +/* ACSR */ +#define ACD 7 +#define ACBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +/* ADCSRA */ +#define ADEN 7 +#define ADSC 6 +#define ADATE 5 +#define ADIF 4 +#define ADIE 3 +#define ADPS2 2 +#define ADPS1 1 +#define ADPS0 0 + +/* ADMUX */ +#define REFS1 7 +#define REFS0 6 +#define ADLAR 5 +#define MUX4 4 +#define MUX3 3 +#define MUX2 2 +#define MUX1 1 +#define MUX0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define SPM_PAGESIZE 128 +#define RAMSTART (0x60) +#define RAMEND 0x85F +#define XRAMEND RAMEND +#define E2END 0x3FF +#define E2PAGESIZE 4 +#define FLASHEND 0x7FFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 2 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_BODEN (unsigned char)~_BV(6) +#define FUSE_BODLEVEL (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_CKOPT (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x02 + + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_INTERRUPT1 +#pragma GCC poison SIG_INTERRUPT2 +#pragma GCC poison SIG_OUTPUT_COMPARE2 +#pragma GCC poison SIG_OVERFLOW2 +#pragma GCC poison SIG_INPUT_CAPTURE1 +#pragma GCC poison SIG_OUTPUT_COMPARE1A +#pragma GCC poison SIG_OUTPUT_COMPARE1B +#pragma GCC poison SIG_OVERFLOW1 +#pragma GCC poison SIG_OUTPUT_COMPARE0 +#pragma GCC poison SIG_OVERFLOW0 +#pragma GCC poison SIG_SPI +#pragma GCC poison SIG_USART_RECV +#pragma GCC poison SIG_UART_RECV +#pragma GCC poison SIG_USART_DATA +#pragma GCC poison SIG_UART_DATA +#pragma GCC poison SIG_USART_TRANS +#pragma GCC poison SIG_UART_TRANS +#pragma GCC poison SIG_ADC +#pragma GCC poison SIG_EEPROM_READY +#pragma GCC poison SIG_COMPARATOR +#pragma GCC poison SIG_2WIRE_SERIAL +#pragma GCC poison SIG_SPM_READY + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + +#define SLEEP_MODE_IDLE (0x00<<4) +#define SLEEP_MODE_ADC (0x01<<4) +#define SLEEP_MODE_PWR_DOWN (0x02<<4) +#define SLEEP_MODE_PWR_SAVE (0x03<<4) +#define SLEEP_MODE_STANDBY (0x06<<4) +#define SLEEP_MODE_EXT_STANDBY (0x07<<4) + +#endif /* _AVR_IOM32_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom3208.h b/hardware/tools/avr/avr/include/avr/iom3208.h new file mode 100644 index 0000000000000000000000000000000000000000..336bdd07b1eba006c1ff780cefd0e56cd032f0b9 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom3208.h @@ -0,0 +1,4955 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom3208.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATMEGA3208_H_INCLUDED +#define _AVR_ATMEGA3208_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[1]; + register8_t DACREF; /* Referance scale control */ + register8_t reserved_3[1]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_PIN2_gc = (0x02<<0), /* Negative Pin 2 */ + AC_MUXNEG_DACREF_gc = (0x03<<0), /* DAC Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ + ADC_MUXPOS_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ + ADC_MUXPOS_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ + ADC_MUXPOS_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ + ADC_MUXPOS_DACREF_gc = (0x1C<<0), /* AC DAC Reference */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temperature sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* 0V (GND) */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t SEQCTRL1; /* Sequential Control 1 */ + register8_t reserved_1[2]; + register8_t INTCTRL0; /* Interrupt Control 0 */ + register8_t reserved_2[1]; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t LUT2CTRLA; /* LUT Control 2 A */ + register8_t LUT2CTRLB; /* LUT Control 2 B */ + register8_t LUT2CTRLC; /* LUT Control 2 C */ + register8_t TRUTH2; /* Truth 2 */ + register8_t LUT3CTRLA; /* LUT Control 3 A */ + register8_t LUT3CTRLB; /* LUT Control 3 B */ + register8_t LUT3CTRLC; /* LUT Control 3 C */ + register8_t TRUTH3; /* Truth 3 */ + register8_t reserved_3[40]; +} CCL_t; + +/* Clock Source Selection select */ +typedef enum CCL_CLKSRC_enum +{ + CCL_CLKSRC_CLKPER_gc = (0x00<<1), /* CLK_PER is clocking the LUT */ + CCL_CLKSRC_IN2_gc = (0x01<<1), /* IN[2] is clocking the LUT */ + CCL_CLKSRC_OSC20M_gc = (0x04<<1), /* 20MHz oscillator before prescaler is clocking the LUT */ + CCL_CLKSRC_OSCULP32K_gc = (0x05<<1), /* 32kHz oscillator is clocking the LUT */ + CCL_CLKSRC_OSCULP1K_gc = (0x06<<1), /* 32kHz oscillator after DIV32 is clocking the LUT */ +} CCL_CLKSRC_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL0_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_USART0_gc = (0x08<<0), /* USART0 TXD input source */ + CCL_INSEL0_SPI0_gc = (0x09<<0), /* SPI0 MOSI input source */ + CCL_INSEL0_TCA0_gc = (0x0A<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCB0_gc = (0x0C<<0), /* TCB0 WO input source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENTA_gc = (0x03<<4), /* Event input source A */ + CCL_INSEL1_EVENTB_gc = (0x04<<4), /* Event input source B */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_USART1_gc = (0x08<<4), /* USART1 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x09<<4), /* SPI0 MOSI input source */ + CCL_INSEL1_TCA0_gc = (0x0A<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCB1_gc = (0x0C<<4), /* TCB1 WO input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL2_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_USART2_gc = (0x08<<0), /* USART2 TXD input source */ + CCL_INSEL2_SPI0_gc = (0x09<<0), /* SPI0 SCK input source */ + CCL_INSEL2_TCA0_gc = (0x0A<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCB2_gc = (0x0C<<0), /* TCB2 WO input source */ +} CCL_INSEL2_t; + +/* Interrupt Mode for LUT0 select */ +typedef enum CCL_INTMODE0_enum +{ + CCL_INTMODE0_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled */ + CCL_INTMODE0_RISING_gc = (0x01<<0), /* Sense rising edge */ + CCL_INTMODE0_FALLING_gc = (0x02<<0), /* Sense falling edge */ + CCL_INTMODE0_BOTH_gc = (0x03<<0), /* Sense both edges */ +} CCL_INTMODE0_t; + +/* Interrupt Mode for LUT1 select */ +typedef enum CCL_INTMODE1_enum +{ + CCL_INTMODE1_INTDISABLE_gc = (0x00<<2), /* Interrupt disabled */ + CCL_INTMODE1_RISING_gc = (0x01<<2), /* Sense rising edge */ + CCL_INTMODE1_FALLING_gc = (0x02<<2), /* Sense falling edge */ + CCL_INTMODE1_BOTH_gc = (0x03<<2), /* Sense both edges */ +} CCL_INTMODE1_t; + +/* Interrupt Mode for LUT2 select */ +typedef enum CCL_INTMODE2_enum +{ + CCL_INTMODE2_INTDISABLE_gc = (0x00<<4), /* Interrupt disabled */ + CCL_INTMODE2_RISING_gc = (0x01<<4), /* Sense rising edge */ + CCL_INTMODE2_FALLING_gc = (0x02<<4), /* Sense falling edge */ + CCL_INTMODE2_BOTH_gc = (0x03<<4), /* Sense both edges */ +} CCL_INTMODE2_t; + +/* Interrupt Mode for LUT3 select */ +typedef enum CCL_INTMODE3_enum +{ + CCL_INTMODE3_INTDISABLE_gc = (0x00<<6), /* Interrupt disabled */ + CCL_INTMODE3_RISING_gc = (0x01<<6), /* Sense rising edge */ + CCL_INTMODE3_FALLING_gc = (0x02<<6), /* Sense falling edge */ + CCL_INTMODE3_BOTH_gc = (0x03<<6), /* Sense both edges */ +} CCL_INTMODE3_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL0_enum +{ + CCL_SEQSEL0_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL0_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL0_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL0_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL0_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL0_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL1_enum +{ + CCL_SEQSEL1_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL1_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL1_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL1_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL1_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL1_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1k cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16k cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32k cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t STROBE; /* Channel Strobe */ + register8_t reserved_1[15]; + register8_t CHANNEL0; /* Multiplexer Channel 0 */ + register8_t CHANNEL1; /* Multiplexer Channel 1 */ + register8_t CHANNEL2; /* Multiplexer Channel 2 */ + register8_t CHANNEL3; /* Multiplexer Channel 3 */ + register8_t CHANNEL4; /* Multiplexer Channel 4 */ + register8_t CHANNEL5; /* Multiplexer Channel 5 */ + register8_t reserved_2[10]; + register8_t USERCCLLUT0A; /* User CCL LUT0 Event A */ + register8_t USERCCLLUT0B; /* User CCL LUT0 Event B */ + register8_t USERCCLLUT1A; /* User CCL LUT1 Event A */ + register8_t USERCCLLUT1B; /* User CCL LUT1 Event B */ + register8_t USERCCLLUT2A; /* User CCL LUT2 Event A */ + register8_t USERCCLLUT2B; /* User CCL LUT2 Event B */ + register8_t USERCCLLUT3A; /* User CCL LUT3 Event A */ + register8_t USERCCLLUT3B; /* User CCL LUT3 Event B */ + register8_t USERADC0; /* User ADC0 */ + register8_t USEREVOUTA; /* User EVOUT Port A */ + register8_t USEREVOUTB; /* User EVOUT Port B */ + register8_t USEREVOUTC; /* User EVOUT Port C */ + register8_t USEREVOUTD; /* User EVOUT Port D */ + register8_t USEREVOUTE; /* User EVOUT Port E */ + register8_t USEREVOUTF; /* User EVOUT Port F */ + register8_t USERUSART0; /* User USART0 */ + register8_t USERUSART1; /* User USART1 */ + register8_t USERUSART2; /* User USART2 */ + register8_t USERUSART3; /* User USART3 */ + register8_t USERTCA0; /* User TCA0 */ + register8_t USERTCB0; /* User TCB0 */ + register8_t USERTCB1; /* User TCB1 */ + register8_t USERTCB2; /* User TCB2 */ + register8_t USERTCB3; /* User TCB3 */ + register8_t reserved_3[8]; +} EVSYS_t; + +/* Channel selector select */ +typedef enum EVSYS_CHANNEL_enum +{ + EVSYS_CHANNEL_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL_CHANNEL0_gc = (0x01<<0), /* Connect user to event channel 0 */ + EVSYS_CHANNEL_CHANNEL1_gc = (0x02<<0), /* Connect user to event channel 1 */ + EVSYS_CHANNEL_CHANNEL2_gc = (0x03<<0), /* Connect user to event channel 2 */ + EVSYS_CHANNEL_CHANNEL3_gc = (0x04<<0), /* Connect user to event channel 3 */ + EVSYS_CHANNEL_CHANNEL4_gc = (0x05<<0), /* Connect user to event channel 4 */ + EVSYS_CHANNEL_CHANNEL5_gc = (0x06<<0), /* Connect user to event channel 5 */ +} EVSYS_CHANNEL_t; + +/* Generator selector select */ +typedef enum EVSYS_GENERATOR_enum +{ + EVSYS_GENERATOR_OFF_gc = (0x00<<0), /* Off */ + EVSYS_GENERATOR_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_GENERATOR_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_GENERATOR_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_GENERATOR_RTC_PIT0_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_GENERATOR_RTC_PIT1_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_GENERATOR_RTC_PIT2_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_GENERATOR_RTC_PIT3_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_GENERATOR_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_GENERATOR_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_GENERATOR_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_GENERATOR_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_GENERATOR_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_GENERATOR_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready Event */ + EVSYS_GENERATOR_PORT0_PIN0_gc = (0x40<<0), /* Port 0 Pin 0 */ + EVSYS_GENERATOR_PORT0_PIN1_gc = (0x41<<0), /* Port 0 Pin 1 */ + EVSYS_GENERATOR_PORT0_PIN2_gc = (0x42<<0), /* Port 0 Pin 2 */ + EVSYS_GENERATOR_PORT0_PIN3_gc = (0x43<<0), /* Port 0 Pin 3 */ + EVSYS_GENERATOR_PORT0_PIN4_gc = (0x44<<0), /* Port 0 Pin 4 */ + EVSYS_GENERATOR_PORT0_PIN5_gc = (0x45<<0), /* Port 0 Pin 5 */ + EVSYS_GENERATOR_PORT0_PIN6_gc = (0x46<<0), /* Port 0 Pin 6 */ + EVSYS_GENERATOR_PORT0_PIN7_gc = (0x47<<0), /* Port 0 Pin 7 */ + EVSYS_GENERATOR_PORT1_PIN0_gc = (0x48<<0), /* Port 1 Pin 0 */ + EVSYS_GENERATOR_PORT1_PIN1_gc = (0x49<<0), /* Port 1 Pin 1 */ + EVSYS_GENERATOR_PORT1_PIN2_gc = (0x4A<<0), /* Port 1 Pin 2 */ + EVSYS_GENERATOR_PORT1_PIN3_gc = (0x4B<<0), /* Port 1 Pin 3 */ + EVSYS_GENERATOR_PORT1_PIN4_gc = (0x4C<<0), /* Port 1 Pin 4 */ + EVSYS_GENERATOR_PORT1_PIN5_gc = (0x4D<<0), /* Port 1 Pin 5 */ + EVSYS_GENERATOR_PORT1_PIN6_gc = (0x4E<<0), /* Port 1 Pin 6 */ + EVSYS_GENERATOR_PORT1_PIN7_gc = (0x4F<<0), /* Port 1 Pin 7 */ + EVSYS_GENERATOR_USART0_XCK_gc = (0x60<<0), /* USART 0 Xclock */ + EVSYS_GENERATOR_USART1_XCK_gc = (0x61<<0), /* USART 1 Xclock */ + EVSYS_GENERATOR_USART2_XCK_gc = (0x62<<0), /* USART 2 Xclock */ + EVSYS_GENERATOR_USART3_XCK_gc = (0x63<<0), /* USART 3 Xclock */ + EVSYS_GENERATOR_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_GENERATOR_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_GENERATOR_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow (split mode) */ + EVSYS_GENERATOR_TCA0_CMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_GENERATOR_TCA0_CMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_GENERATOR_TCA0_CMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_GENERATOR_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_GENERATOR_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_GENERATOR_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_GENERATOR_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ +} EVSYS_GENERATOR_t; + +/* Software event on channels select */ +typedef enum EVSYS_STROBE0_enum +{ + EVSYS_STROBE0_EV_STROBE_CH0_gc = (0x01<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH1_gc = (0x02<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH2_gc = (0x04<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH3_gc = (0x08<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH4_gc = (0x10<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH5_gc = (0x20<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH6_gc = (0x40<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH7_gc = (0x80<<0), /* */ +} EVSYS_STROBE0_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<3), /* GPIO mode */ + RSTPINCFG_RST_gc = (0x01<<3), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock Bits */ + register8_t reserved_1[1]; +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t PORTCTRL; /* Port Control */ + register8_t reserved_1[5]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t EVSYSROUTEA; /* Port Multiplexer EVSYS */ + register8_t CCLROUTEA; /* Port Multiplexer CCL */ + register8_t USARTROUTEA; /* Port Multiplexer USART register A */ + register8_t TWISPIROUTEA; /* Port Multiplexer TWI and SPI */ + register8_t TCAROUTEA; /* Port Multiplexer TCA */ + register8_t TCBROUTEA; /* Port Multiplexer TCB */ + register8_t reserved_1[10]; +} PORTMUX_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<0), /* SPI0 on PA[7:4] */ + PORTMUX_SPI0_ALT1_gc = (0x01<<0), /* SPI0 on PC[3:0] */ + PORTMUX_SPI0_ALT2_gc = (0x02<<0), /* SPI0 on PE[3:0] */ + PORTMUX_SPI0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 select */ +typedef enum PORTMUX_TCA0_enum +{ + PORTMUX_TCA0_PORTA_gc = (0x00<<0), /* TCA0 pins on PA[5:0] */ + PORTMUX_TCA0_PORTB_gc = (0x01<<0), /* TCA0 pins on PB[5:0] */ + PORTMUX_TCA0_PORTC_gc = (0x02<<0), /* TCA0 pins on PC[5:0] */ + PORTMUX_TCA0_PORTD_gc = (0x03<<0), /* TCA0 pins on PD[5:0] */ + PORTMUX_TCA0_PORTE_gc = (0x04<<0), /* TCA0 pins on PE[5:0] */ + PORTMUX_TCA0_PORTF_gc = (0x05<<0), /* TCA0 pins on PF[5:0] */ +} PORTMUX_TCA0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* SCL/SDA on PA[3:2], Slave mode on PC[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT1_gc = (0x01<<4), /* SCL/SDA on PA[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT2_gc = (0x02<<4), /* SCL/SDA on PC[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* USART0 on PA[3:0] */ + PORTMUX_USART0_ALT1_gc = (0x01<<0), /* USART0 on PA[7:4] */ + PORTMUX_USART0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_USART0_t; + +/* Port Multiplexer USART1 select */ +typedef enum PORTMUX_USART1_enum +{ + PORTMUX_USART1_DEFAULT_gc = (0x00<<2), /* USART1 on PC[3:0] */ + PORTMUX_USART1_ALT1_gc = (0x01<<2), /* USART1 on PC[7:4] */ + PORTMUX_USART1_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_USART1_t; + +/* Port Multiplexer USART2 select */ +typedef enum PORTMUX_USART2_enum +{ + PORTMUX_USART2_DEFAULT_gc = (0x00<<4), /* USART2 on PF[3:0] */ + PORTMUX_USART2_ALT1_gc = (0x01<<4), /* USART2 on PF[6:4] */ + PORTMUX_USART2_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_USART2_t; + +/* Port Multiplexer USART3 select */ +typedef enum PORTMUX_USART3_enum +{ + PORTMUX_USART3_DEFAULT_gc = (0x00<<6), /* USART3 on PB[3:0] */ + PORTMUX_USART3_ALT1_gc = (0x01<<6), /* USART3 on PB[5:4] */ + PORTMUX_USART3_NONE_gc = (0x03<<6), /* Not connected to any pins */ +} PORTMUX_USART3_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t CALIB; /* Calibration */ + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_1[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_2[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_3[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[7]; + register8_t OSCCAL32K; /* Oscillator Calibration for 32kHz ULP */ + register8_t reserved_2[3]; + register8_t OSCCAL16M0; /* Oscillator Calibration 16 MHz Byte 0 */ + register8_t OSCCAL16M1; /* Oscillator Calibration 16 MHz Byte 1 */ + register8_t OSCCAL20M0; /* Oscillator Calibration 20 MHz Byte 0 */ + register8_t OSCCAL20M1; /* Oscillator Calibration 20 MHz Byte 1 */ + register8_t reserved_3[4]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_4[9]; + register8_t CHECKSUM1; /* CRC Checksum Byte 1 */ + register8_t reserved_5[16]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[21]; + register8_t OCDM; /* OCD Message Register */ + register8_t OCDMS; /* OCD Message Status */ + register8_t reserved_3[6]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t DUALCTRL; /* Dual Control */ + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_1[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t CTRLD; /* Control D */ + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_1[1]; +} USART_t; + +/* Auto Baud Window select */ +typedef enum USART_ABW_enum +{ + USART_ABW_WDW0_gc = (0x00<<6), /* 18% tolerance */ + USART_ABW_WDW1_gc = (0x01<<6), /* 15% tolerance */ + USART_ABW_WDW2_gc = (0x02<<6), /* 21% tolerance */ + USART_ABW_WDW3_gc = (0x03<<6), /* 25% tolerance */ +} USART_ABW_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ + register8_t USERROW32; /* User Row Byte 32 */ + register8_t USERROW33; /* User Row Byte 33 */ + register8_t USERROW34; /* User Row Byte 34 */ + register8_t USERROW35; /* User Row Byte 35 */ + register8_t USERROW36; /* User Row Byte 36 */ + register8_t USERROW37; /* User Row Byte 37 */ + register8_t USERROW38; /* User Row Byte 38 */ + register8_t USERROW39; /* User Row Byte 39 */ + register8_t USERROW40; /* User Row Byte 40 */ + register8_t USERROW41; /* User Row Byte 41 */ + register8_t USERROW42; /* User Row Byte 42 */ + register8_t USERROW43; /* User Row Byte 43 */ + register8_t USERROW44; /* User Row Byte 44 */ + register8_t USERROW45; /* User Row Byte 45 */ + register8_t USERROW46; /* User Row Byte 46 */ + register8_t USERROW47; /* User Row Byte 47 */ + register8_t USERROW48; /* User Row Byte 48 */ + register8_t USERROW49; /* User Row Byte 49 */ + register8_t USERROW50; /* User Row Byte 50 */ + register8_t USERROW51; /* User Row Byte 51 */ + register8_t USERROW52; /* User Row Byte 52 */ + register8_t USERROW53; /* User Row Byte 53 */ + register8_t USERROW54; /* User Row Byte 54 */ + register8_t USERROW55; /* User Row Byte 55 */ + register8_t USERROW56; /* User Row Byte 56 */ + register8_t USERROW57; /* User Row Byte 57 */ + register8_t USERROW58; /* User Row Byte 58 */ + register8_t USERROW59; /* User Row Byte 59 */ + register8_t USERROW60; /* User Row Byte 60 */ + register8_t USERROW61; /* User Row Byte 61 */ + register8_t USERROW62; /* User Row Byte 62 */ + register8_t USERROW63; /* User Row Byte 63 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* AC0 reference select select */ +typedef enum VREF_AC0REFSEL_enum +{ + VREF_AC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_AC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_AC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_AC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_AC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ + VREF_AC0REFSEL_AVDD_gc = (0x07<<0), /* AVDD */ +} VREF_AC0REFSEL_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define VPORTD (*(VPORT_t *) 0x000C) /* Virtual Ports */ +#define VPORTE (*(VPORT_t *) 0x0010) /* Virtual Ports */ +#define VPORTF (*(VPORT_t *) 0x0014) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0460) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0480) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x04A0) /* I/O Ports */ +#define PORTMUX (*(PORTMUX_t *) 0x05E0) /* Port Multiplexer */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1 (*(USART_t *) 0x0820) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2 (*(USART_t *) 0x0840) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x08A0) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A80) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0A90) /* 16-bit Timer Type B */ +#define TCB2 (*(TCB_t *) 0x0AA0) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* VPORT (VPORTD) - Virtual Ports */ +#define VPORTD_DIR _SFR_MEM8(0x000C) +#define VPORTD_OUT _SFR_MEM8(0x000D) +#define VPORTD_IN _SFR_MEM8(0x000E) +#define VPORTD_INTFLAGS _SFR_MEM8(0x000F) + + +/* VPORT (VPORTE) - Virtual Ports */ +#define VPORTE_DIR _SFR_MEM8(0x0010) +#define VPORTE_OUT _SFR_MEM8(0x0011) +#define VPORTE_IN _SFR_MEM8(0x0012) +#define VPORTE_INTFLAGS _SFR_MEM8(0x0013) + + +/* VPORT (VPORTF) - Virtual Ports */ +#define VPORTF_DIR _SFR_MEM8(0x0014) +#define VPORTF_OUT _SFR_MEM8(0x0015) +#define VPORTF_IN _SFR_MEM8(0x0016) +#define VPORTF_INTFLAGS _SFR_MEM8(0x0017) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CALIB _SFR_MEM8(0x0146) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_STROBE _SFR_MEM8(0x0180) +#define EVSYS_CHANNEL0 _SFR_MEM8(0x0190) +#define EVSYS_CHANNEL1 _SFR_MEM8(0x0191) +#define EVSYS_CHANNEL2 _SFR_MEM8(0x0192) +#define EVSYS_CHANNEL3 _SFR_MEM8(0x0193) +#define EVSYS_CHANNEL4 _SFR_MEM8(0x0194) +#define EVSYS_CHANNEL5 _SFR_MEM8(0x0195) +#define EVSYS_USERCCLLUT0A _SFR_MEM8(0x01A0) +#define EVSYS_USERCCLLUT0B _SFR_MEM8(0x01A1) +#define EVSYS_USERCCLLUT1A _SFR_MEM8(0x01A2) +#define EVSYS_USERCCLLUT1B _SFR_MEM8(0x01A3) +#define EVSYS_USERCCLLUT2A _SFR_MEM8(0x01A4) +#define EVSYS_USERCCLLUT2B _SFR_MEM8(0x01A5) +#define EVSYS_USERCCLLUT3A _SFR_MEM8(0x01A6) +#define EVSYS_USERCCLLUT3B _SFR_MEM8(0x01A7) +#define EVSYS_USERADC0 _SFR_MEM8(0x01A8) +#define EVSYS_USEREVOUTA _SFR_MEM8(0x01A9) +#define EVSYS_USEREVOUTB _SFR_MEM8(0x01AA) +#define EVSYS_USEREVOUTC _SFR_MEM8(0x01AB) +#define EVSYS_USEREVOUTD _SFR_MEM8(0x01AC) +#define EVSYS_USEREVOUTE _SFR_MEM8(0x01AD) +#define EVSYS_USEREVOUTF _SFR_MEM8(0x01AE) +#define EVSYS_USERUSART0 _SFR_MEM8(0x01AF) +#define EVSYS_USERUSART1 _SFR_MEM8(0x01B0) +#define EVSYS_USERUSART2 _SFR_MEM8(0x01B1) +#define EVSYS_USERUSART3 _SFR_MEM8(0x01B2) +#define EVSYS_USERTCA0 _SFR_MEM8(0x01B3) +#define EVSYS_USERTCB0 _SFR_MEM8(0x01B4) +#define EVSYS_USERTCB1 _SFR_MEM8(0x01B5) +#define EVSYS_USERTCB2 _SFR_MEM8(0x01B6) +#define EVSYS_USERTCB3 _SFR_MEM8(0x01B7) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_SEQCTRL1 _SFR_MEM8(0x01C2) +#define CCL_INTCTRL0 _SFR_MEM8(0x01C5) +#define CCL_INTFLAGS _SFR_MEM8(0x01C7) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C8) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C9) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01CA) +#define CCL_TRUTH0 _SFR_MEM8(0x01CB) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01CC) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CD) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CE) +#define CCL_TRUTH1 _SFR_MEM8(0x01CF) +#define CCL_LUT2CTRLA _SFR_MEM8(0x01D0) +#define CCL_LUT2CTRLB _SFR_MEM8(0x01D1) +#define CCL_LUT2CTRLC _SFR_MEM8(0x01D2) +#define CCL_TRUTH2 _SFR_MEM8(0x01D3) +#define CCL_LUT3CTRLA _SFR_MEM8(0x01D4) +#define CCL_LUT3CTRLB _SFR_MEM8(0x01D5) +#define CCL_LUT3CTRLC _SFR_MEM8(0x01D6) +#define CCL_TRUTH3 _SFR_MEM8(0x01D7) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PORTCTRL _SFR_MEM8(0x040A) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PORTCTRL _SFR_MEM8(0x042A) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PORTCTRL _SFR_MEM8(0x044A) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* PORT (PORTD) - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0460) +#define PORTD_DIRSET _SFR_MEM8(0x0461) +#define PORTD_DIRCLR _SFR_MEM8(0x0462) +#define PORTD_DIRTGL _SFR_MEM8(0x0463) +#define PORTD_OUT _SFR_MEM8(0x0464) +#define PORTD_OUTSET _SFR_MEM8(0x0465) +#define PORTD_OUTCLR _SFR_MEM8(0x0466) +#define PORTD_OUTTGL _SFR_MEM8(0x0467) +#define PORTD_IN _SFR_MEM8(0x0468) +#define PORTD_INTFLAGS _SFR_MEM8(0x0469) +#define PORTD_PORTCTRL _SFR_MEM8(0x046A) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0470) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0471) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0472) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0473) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0474) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0475) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0476) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0477) + + +/* PORT (PORTE) - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0480) +#define PORTE_DIRSET _SFR_MEM8(0x0481) +#define PORTE_DIRCLR _SFR_MEM8(0x0482) +#define PORTE_DIRTGL _SFR_MEM8(0x0483) +#define PORTE_OUT _SFR_MEM8(0x0484) +#define PORTE_OUTSET _SFR_MEM8(0x0485) +#define PORTE_OUTCLR _SFR_MEM8(0x0486) +#define PORTE_OUTTGL _SFR_MEM8(0x0487) +#define PORTE_IN _SFR_MEM8(0x0488) +#define PORTE_INTFLAGS _SFR_MEM8(0x0489) +#define PORTE_PORTCTRL _SFR_MEM8(0x048A) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0490) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0491) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0492) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0493) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0494) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0495) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0496) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0497) + + +/* PORT (PORTF) - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x04A0) +#define PORTF_DIRSET _SFR_MEM8(0x04A1) +#define PORTF_DIRCLR _SFR_MEM8(0x04A2) +#define PORTF_DIRTGL _SFR_MEM8(0x04A3) +#define PORTF_OUT _SFR_MEM8(0x04A4) +#define PORTF_OUTSET _SFR_MEM8(0x04A5) +#define PORTF_OUTCLR _SFR_MEM8(0x04A6) +#define PORTF_OUTTGL _SFR_MEM8(0x04A7) +#define PORTF_IN _SFR_MEM8(0x04A8) +#define PORTF_INTFLAGS _SFR_MEM8(0x04A9) +#define PORTF_PORTCTRL _SFR_MEM8(0x04AA) +#define PORTF_PIN0CTRL _SFR_MEM8(0x04B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x04B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x04B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x04B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x04B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x04B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x04B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x04B7) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_EVSYSROUTEA _SFR_MEM8(0x05E0) +#define PORTMUX_CCLROUTEA _SFR_MEM8(0x05E1) +#define PORTMUX_USARTROUTEA _SFR_MEM8(0x05E2) +#define PORTMUX_TWISPIROUTEA _SFR_MEM8(0x05E3) +#define PORTMUX_TCAROUTEA _SFR_MEM8(0x05E4) +#define PORTMUX_TCBROUTEA _SFR_MEM8(0x05E5) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_DACREF _SFR_MEM8(0x0684) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_CTRLD _SFR_MEM8(0x080A) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* USART (USART1) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1_RXDATAL _SFR_MEM8(0x0820) +#define USART1_RXDATAH _SFR_MEM8(0x0821) +#define USART1_TXDATAL _SFR_MEM8(0x0822) +#define USART1_TXDATAH _SFR_MEM8(0x0823) +#define USART1_STATUS _SFR_MEM8(0x0824) +#define USART1_CTRLA _SFR_MEM8(0x0825) +#define USART1_CTRLB _SFR_MEM8(0x0826) +#define USART1_CTRLC _SFR_MEM8(0x0827) +#define USART1_BAUD _SFR_MEM16(0x0828) +#define USART1_BAUDL _SFR_MEM8(0x0828) +#define USART1_BAUDH _SFR_MEM8(0x0829) +#define USART1_CTRLD _SFR_MEM8(0x082A) +#define USART1_DBGCTRL _SFR_MEM8(0x082B) +#define USART1_EVCTRL _SFR_MEM8(0x082C) +#define USART1_TXPLCTRL _SFR_MEM8(0x082D) +#define USART1_RXPLCTRL _SFR_MEM8(0x082E) + + +/* USART (USART2) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2_RXDATAL _SFR_MEM8(0x0840) +#define USART2_RXDATAH _SFR_MEM8(0x0841) +#define USART2_TXDATAL _SFR_MEM8(0x0842) +#define USART2_TXDATAH _SFR_MEM8(0x0843) +#define USART2_STATUS _SFR_MEM8(0x0844) +#define USART2_CTRLA _SFR_MEM8(0x0845) +#define USART2_CTRLB _SFR_MEM8(0x0846) +#define USART2_CTRLC _SFR_MEM8(0x0847) +#define USART2_BAUD _SFR_MEM16(0x0848) +#define USART2_BAUDL _SFR_MEM8(0x0848) +#define USART2_BAUDH _SFR_MEM8(0x0849) +#define USART2_CTRLD _SFR_MEM8(0x084A) +#define USART2_DBGCTRL _SFR_MEM8(0x084B) +#define USART2_EVCTRL _SFR_MEM8(0x084C) +#define USART2_TXPLCTRL _SFR_MEM8(0x084D) +#define USART2_RXPLCTRL _SFR_MEM8(0x084E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x08A0) +#define TWI0_DUALCTRL _SFR_MEM8(0x08A1) +#define TWI0_DBGCTRL _SFR_MEM8(0x08A2) +#define TWI0_MCTRLA _SFR_MEM8(0x08A3) +#define TWI0_MCTRLB _SFR_MEM8(0x08A4) +#define TWI0_MSTATUS _SFR_MEM8(0x08A5) +#define TWI0_MBAUD _SFR_MEM8(0x08A6) +#define TWI0_MADDR _SFR_MEM8(0x08A7) +#define TWI0_MDATA _SFR_MEM8(0x08A8) +#define TWI0_SCTRLA _SFR_MEM8(0x08A9) +#define TWI0_SCTRLB _SFR_MEM8(0x08AA) +#define TWI0_SSTATUS _SFR_MEM8(0x08AB) +#define TWI0_SADDR _SFR_MEM8(0x08AC) +#define TWI0_SDATA _SFR_MEM8(0x08AD) +#define TWI0_SADDRMASK _SFR_MEM8(0x08AE) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x08C0) +#define SPI0_CTRLB _SFR_MEM8(0x08C1) +#define SPI0_INTCTRL _SFR_MEM8(0x08C2) +#define SPI0_INTFLAGS _SFR_MEM8(0x08C3) +#define SPI0_DATA _SFR_MEM8(0x08C4) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A80) +#define TCB0_CTRLB _SFR_MEM8(0x0A81) +#define TCB0_EVCTRL _SFR_MEM8(0x0A84) +#define TCB0_INTCTRL _SFR_MEM8(0x0A85) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A86) +#define TCB0_STATUS _SFR_MEM8(0x0A87) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A88) +#define TCB0_TEMP _SFR_MEM8(0x0A89) +#define TCB0_CNT _SFR_MEM16(0x0A8A) +#define TCB0_CNTL _SFR_MEM8(0x0A8A) +#define TCB0_CNTH _SFR_MEM8(0x0A8B) +#define TCB0_CCMP _SFR_MEM16(0x0A8C) +#define TCB0_CCMPL _SFR_MEM8(0x0A8C) +#define TCB0_CCMPH _SFR_MEM8(0x0A8D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0A90) +#define TCB1_CTRLB _SFR_MEM8(0x0A91) +#define TCB1_EVCTRL _SFR_MEM8(0x0A94) +#define TCB1_INTCTRL _SFR_MEM8(0x0A95) +#define TCB1_INTFLAGS _SFR_MEM8(0x0A96) +#define TCB1_STATUS _SFR_MEM8(0x0A97) +#define TCB1_DBGCTRL _SFR_MEM8(0x0A98) +#define TCB1_TEMP _SFR_MEM8(0x0A99) +#define TCB1_CNT _SFR_MEM16(0x0A9A) +#define TCB1_CNTL _SFR_MEM8(0x0A9A) +#define TCB1_CNTH _SFR_MEM8(0x0A9B) +#define TCB1_CCMP _SFR_MEM16(0x0A9C) +#define TCB1_CCMPL _SFR_MEM8(0x0A9C) +#define TCB1_CCMPH _SFR_MEM8(0x0A9D) + + +/* TCB (TCB2) - 16-bit Timer Type B */ +#define TCB2_CTRLA _SFR_MEM8(0x0AA0) +#define TCB2_CTRLB _SFR_MEM8(0x0AA1) +#define TCB2_EVCTRL _SFR_MEM8(0x0AA4) +#define TCB2_INTCTRL _SFR_MEM8(0x0AA5) +#define TCB2_INTFLAGS _SFR_MEM8(0x0AA6) +#define TCB2_STATUS _SFR_MEM8(0x0AA7) +#define TCB2_DBGCTRL _SFR_MEM8(0x0AA8) +#define TCB2_TEMP _SFR_MEM8(0x0AA9) +#define TCB2_CNT _SFR_MEM16(0x0AAA) +#define TCB2_CNTL _SFR_MEM8(0x0AAA) +#define TCB2_CNTH _SFR_MEM8(0x0AAB) +#define TCB2_CCMP _SFR_MEM16(0x0AAC) +#define TCB2_CCMPL _SFR_MEM8(0x0AAC) +#define TCB2_CCMPH _SFR_MEM8(0x0AAD) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) +#define SYSCFG_OCDM _SFR_MEM8(0x0F18) +#define SYSCFG_OCDMS _SFR_MEM8(0x0F19) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_OSCCAL32K _SFR_MEM8(0x1114) +#define SIGROW_OSCCAL16M0 _SFR_MEM8(0x1118) +#define SIGROW_OSCCAL16M1 _SFR_MEM8(0x1119) +#define SIGROW_OSCCAL20M0 _SFR_MEM8(0x111A) +#define SIGROW_OSCCAL20M1 _SFR_MEM8(0x111B) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) +#define SIGROW_CHECKSUM1 _SFR_MEM8(0x112F) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) +#define USERROW_USERROW32 _SFR_MEM8(0x1320) +#define USERROW_USERROW33 _SFR_MEM8(0x1321) +#define USERROW_USERROW34 _SFR_MEM8(0x1322) +#define USERROW_USERROW35 _SFR_MEM8(0x1323) +#define USERROW_USERROW36 _SFR_MEM8(0x1324) +#define USERROW_USERROW37 _SFR_MEM8(0x1325) +#define USERROW_USERROW38 _SFR_MEM8(0x1326) +#define USERROW_USERROW39 _SFR_MEM8(0x1327) +#define USERROW_USERROW40 _SFR_MEM8(0x1328) +#define USERROW_USERROW41 _SFR_MEM8(0x1329) +#define USERROW_USERROW42 _SFR_MEM8(0x132A) +#define USERROW_USERROW43 _SFR_MEM8(0x132B) +#define USERROW_USERROW44 _SFR_MEM8(0x132C) +#define USERROW_USERROW45 _SFR_MEM8(0x132D) +#define USERROW_USERROW46 _SFR_MEM8(0x132E) +#define USERROW_USERROW47 _SFR_MEM8(0x132F) +#define USERROW_USERROW48 _SFR_MEM8(0x1330) +#define USERROW_USERROW49 _SFR_MEM8(0x1331) +#define USERROW_USERROW50 _SFR_MEM8(0x1332) +#define USERROW_USERROW51 _SFR_MEM8(0x1333) +#define USERROW_USERROW52 _SFR_MEM8(0x1334) +#define USERROW_USERROW53 _SFR_MEM8(0x1335) +#define USERROW_USERROW54 _SFR_MEM8(0x1336) +#define USERROW_USERROW55 _SFR_MEM8(0x1337) +#define USERROW_USERROW56 _SFR_MEM8(0x1338) +#define USERROW_USERROW57 _SFR_MEM8(0x1339) +#define USERROW_USERROW58 _SFR_MEM8(0x133A) +#define USERROW_USERROW59 _SFR_MEM8(0x133B) +#define USERROW_USERROW60 _SFR_MEM8(0x133C) +#define USERROW_USERROW61 _SFR_MEM8(0x133D) +#define USERROW_USERROW62 _SFR_MEM8(0x133E) +#define USERROW_USERROW63 _SFR_MEM8(0x133F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.DACREF bit masks and bit positions */ +#define AC_DATA_gm 0xFF /* DAC voltage reference group mask. */ +#define AC_DATA_gp 0 /* DAC voltage reference group position. */ +#define AC_DATA0_bm (1<<0) /* DAC voltage reference bit 0 mask. */ +#define AC_DATA0_bp 0 /* DAC voltage reference bit 0 position. */ +#define AC_DATA1_bm (1<<1) /* DAC voltage reference bit 1 mask. */ +#define AC_DATA1_bp 1 /* DAC voltage reference bit 1 position. */ +#define AC_DATA2_bm (1<<2) /* DAC voltage reference bit 2 mask. */ +#define AC_DATA2_bp 2 /* DAC voltage reference bit 2 position. */ +#define AC_DATA3_bm (1<<3) /* DAC voltage reference bit 3 mask. */ +#define AC_DATA3_bp 3 /* DAC voltage reference bit 3 position. */ +#define AC_DATA4_bm (1<<4) /* DAC voltage reference bit 4 mask. */ +#define AC_DATA4_bp 4 /* DAC voltage reference bit 4 position. */ +#define AC_DATA5_bm (1<<5) /* DAC voltage reference bit 5 mask. */ +#define AC_DATA5_bp 5 /* DAC voltage reference bit 5 position. */ +#define AC_DATA6_bm (1<<6) /* DAC voltage reference bit 6 mask. */ +#define AC_DATA6_bp 6 /* DAC voltage reference bit 6 position. */ +#define AC_DATA7_bm (1<<7) /* DAC voltage reference bit 7 mask. */ +#define AC_DATA7_bp 7 /* DAC voltage reference bit 7 position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL0_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL0_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL00_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL00_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL01_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL01_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL02_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL02_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.SEQCTRL1 bit masks and bit positions */ +#define CCL_SEQSEL1_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL1_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL10_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL10_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL11_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL11_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL12_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL12_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.INTCTRL0 bit masks and bit positions */ +#define CCL_INTMODE0_gm 0x03 /* Interrupt Mode for LUT0 group mask. */ +#define CCL_INTMODE0_gp 0 /* Interrupt Mode for LUT0 group position. */ +#define CCL_INTMODE00_bm (1<<0) /* Interrupt Mode for LUT0 bit 0 mask. */ +#define CCL_INTMODE00_bp 0 /* Interrupt Mode for LUT0 bit 0 position. */ +#define CCL_INTMODE01_bm (1<<1) /* Interrupt Mode for LUT0 bit 1 mask. */ +#define CCL_INTMODE01_bp 1 /* Interrupt Mode for LUT0 bit 1 position. */ +#define CCL_INTMODE1_gm 0x0C /* Interrupt Mode for LUT1 group mask. */ +#define CCL_INTMODE1_gp 2 /* Interrupt Mode for LUT1 group position. */ +#define CCL_INTMODE10_bm (1<<2) /* Interrupt Mode for LUT1 bit 0 mask. */ +#define CCL_INTMODE10_bp 2 /* Interrupt Mode for LUT1 bit 0 position. */ +#define CCL_INTMODE11_bm (1<<3) /* Interrupt Mode for LUT1 bit 1 mask. */ +#define CCL_INTMODE11_bp 3 /* Interrupt Mode for LUT1 bit 1 position. */ +#define CCL_INTMODE2_gm 0x30 /* Interrupt Mode for LUT2 group mask. */ +#define CCL_INTMODE2_gp 4 /* Interrupt Mode for LUT2 group position. */ +#define CCL_INTMODE20_bm (1<<4) /* Interrupt Mode for LUT2 bit 0 mask. */ +#define CCL_INTMODE20_bp 4 /* Interrupt Mode for LUT2 bit 0 position. */ +#define CCL_INTMODE21_bm (1<<5) /* Interrupt Mode for LUT2 bit 1 mask. */ +#define CCL_INTMODE21_bp 5 /* Interrupt Mode for LUT2 bit 1 position. */ +#define CCL_INTMODE3_gm 0xC0 /* Interrupt Mode for LUT3 group mask. */ +#define CCL_INTMODE3_gp 6 /* Interrupt Mode for LUT3 group position. */ +#define CCL_INTMODE30_bm (1<<6) /* Interrupt Mode for LUT3 bit 0 mask. */ +#define CCL_INTMODE30_bp 6 /* Interrupt Mode for LUT3 bit 0 position. */ +#define CCL_INTMODE31_bm (1<<7) /* Interrupt Mode for LUT3 bit 1 mask. */ +#define CCL_INTMODE31_bp 7 /* Interrupt Mode for LUT3 bit 1 position. */ + +/* CCL.INTFLAGS bit masks and bit positions */ +#define CCL_INT_gm 0x0F /* Interrupt Flags group mask. */ +#define CCL_INT_gp 0 /* Interrupt Flags group position. */ +#define CCL_INT0_bm (1<<0) /* Interrupt Flags bit 0 mask. */ +#define CCL_INT0_bp 0 /* Interrupt Flags bit 0 position. */ +#define CCL_INT1_bm (1<<1) /* Interrupt Flags bit 1 mask. */ +#define CCL_INT1_bp 1 /* Interrupt Flags bit 1 position. */ +#define CCL_INT2_bm (1<<2) /* Interrupt Flags bit 2 mask. */ +#define CCL_INT2_bp 2 /* Interrupt Flags bit 2 position. */ +#define CCL_INT3_bm (1<<3) /* Interrupt Flags bit 3 mask. */ +#define CCL_INT3_bp 3 /* Interrupt Flags bit 3 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_CLKSRC_gm 0x0E /* Clock Source Selection group mask. */ +#define CCL_CLKSRC_gp 1 /* Clock Source Selection group position. */ +#define CCL_CLKSRC0_bm (1<<1) /* Clock Source Selection bit 0 mask. */ +#define CCL_CLKSRC0_bp 1 /* Clock Source Selection bit 0 position. */ +#define CCL_CLKSRC1_bm (1<<2) /* Clock Source Selection bit 1 mask. */ +#define CCL_CLKSRC1_bp 2 /* Clock Source Selection bit 1 position. */ +#define CCL_CLKSRC2_bm (1<<3) /* Clock Source Selection bit 2 mask. */ +#define CCL_CLKSRC2_bp 3 /* Clock Source Selection bit 2 position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_OUTEN_bm 0x40 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 6 /* Output Enable bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT2CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT2CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT2CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT3CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT3CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT3CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x7F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ +#define CLKCTRL_CAL20M6_bm (1<<6) /* Calibration bit 6 mask. */ +#define CLKCTRL_CAL20M6_bp 6 /* Calibration bit 6 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.STROBE bit masks and bit positions */ +#define EVSYS_STROBE0_gm 0xFF /* Software event on channels group mask. */ +#define EVSYS_STROBE0_gp 0 /* Software event on channels group position. */ +#define EVSYS_STROBE00_bm (1<<0) /* Software event on channels bit 0 mask. */ +#define EVSYS_STROBE00_bp 0 /* Software event on channels bit 0 position. */ +#define EVSYS_STROBE01_bm (1<<1) /* Software event on channels bit 1 mask. */ +#define EVSYS_STROBE01_bp 1 /* Software event on channels bit 1 position. */ +#define EVSYS_STROBE02_bm (1<<2) /* Software event on channels bit 2 mask. */ +#define EVSYS_STROBE02_bp 2 /* Software event on channels bit 2 position. */ +#define EVSYS_STROBE03_bm (1<<3) /* Software event on channels bit 3 mask. */ +#define EVSYS_STROBE03_bp 3 /* Software event on channels bit 3 position. */ +#define EVSYS_STROBE04_bm (1<<4) /* Software event on channels bit 4 mask. */ +#define EVSYS_STROBE04_bp 4 /* Software event on channels bit 4 position. */ +#define EVSYS_STROBE05_bm (1<<5) /* Software event on channels bit 5 mask. */ +#define EVSYS_STROBE05_bp 5 /* Software event on channels bit 5 position. */ +#define EVSYS_STROBE06_bm (1<<6) /* Software event on channels bit 6 mask. */ +#define EVSYS_STROBE06_bp 6 /* Software event on channels bit 6 position. */ +#define EVSYS_STROBE07_bm (1<<7) /* Software event on channels bit 7 mask. */ +#define EVSYS_STROBE07_bp 7 /* Software event on channels bit 7 position. */ + +/* EVSYS.CHANNEL0 bit masks and bit positions */ +#define EVSYS_GENERATOR_gm 0xFF /* Generator selector group mask. */ +#define EVSYS_GENERATOR_gp 0 /* Generator selector group position. */ +#define EVSYS_GENERATOR0_bm (1<<0) /* Generator selector bit 0 mask. */ +#define EVSYS_GENERATOR0_bp 0 /* Generator selector bit 0 position. */ +#define EVSYS_GENERATOR1_bm (1<<1) /* Generator selector bit 1 mask. */ +#define EVSYS_GENERATOR1_bp 1 /* Generator selector bit 1 position. */ +#define EVSYS_GENERATOR2_bm (1<<2) /* Generator selector bit 2 mask. */ +#define EVSYS_GENERATOR2_bp 2 /* Generator selector bit 2 position. */ +#define EVSYS_GENERATOR3_bm (1<<3) /* Generator selector bit 3 mask. */ +#define EVSYS_GENERATOR3_bp 3 /* Generator selector bit 3 position. */ +#define EVSYS_GENERATOR4_bm (1<<4) /* Generator selector bit 4 mask. */ +#define EVSYS_GENERATOR4_bp 4 /* Generator selector bit 4 position. */ +#define EVSYS_GENERATOR5_bm (1<<5) /* Generator selector bit 5 mask. */ +#define EVSYS_GENERATOR5_bp 5 /* Generator selector bit 5 position. */ +#define EVSYS_GENERATOR6_bm (1<<6) /* Generator selector bit 6 mask. */ +#define EVSYS_GENERATOR6_bp 6 /* Generator selector bit 6 position. */ +#define EVSYS_GENERATOR7_bm (1<<7) /* Generator selector bit 7 mask. */ +#define EVSYS_GENERATOR7_bp 7 /* Generator selector bit 7 position. */ + +/* EVSYS.CHANNEL1 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL2 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL3 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL4 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL5 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.USERCCLLUT0A bit masks and bit positions */ +#define EVSYS_CHANNEL_gm 0xFF /* Channel selector group mask. */ +#define EVSYS_CHANNEL_gp 0 /* Channel selector group position. */ +#define EVSYS_CHANNEL0_bm (1<<0) /* Channel selector bit 0 mask. */ +#define EVSYS_CHANNEL0_bp 0 /* Channel selector bit 0 position. */ +#define EVSYS_CHANNEL1_bm (1<<1) /* Channel selector bit 1 mask. */ +#define EVSYS_CHANNEL1_bp 1 /* Channel selector bit 1 position. */ +#define EVSYS_CHANNEL2_bm (1<<2) /* Channel selector bit 2 mask. */ +#define EVSYS_CHANNEL2_bp 2 /* Channel selector bit 2 position. */ +#define EVSYS_CHANNEL3_bm (1<<3) /* Channel selector bit 3 mask. */ +#define EVSYS_CHANNEL3_bp 3 /* Channel selector bit 3 position. */ +#define EVSYS_CHANNEL4_bm (1<<4) /* Channel selector bit 4 mask. */ +#define EVSYS_CHANNEL4_bp 4 /* Channel selector bit 4 position. */ +#define EVSYS_CHANNEL5_bm (1<<5) /* Channel selector bit 5 mask. */ +#define EVSYS_CHANNEL5_bp 5 /* Channel selector bit 5 position. */ +#define EVSYS_CHANNEL6_bm (1<<6) /* Channel selector bit 6 mask. */ +#define EVSYS_CHANNEL6_bp 6 /* Channel selector bit 6 position. */ +#define EVSYS_CHANNEL7_bm (1<<7) /* Channel selector bit 7 mask. */ +#define EVSYS_CHANNEL7_bp 7 /* Channel selector bit 7 position. */ + +/* EVSYS.USERCCLLUT0B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT1A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT1B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT2A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT2B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT3A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT3B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERADC0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTA bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTB bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTC bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTD bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTE bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTF bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART1 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART2 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART3 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCA0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB1 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB2 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB3 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_bm 0x08 /* Reset Pin Configuration bit mask. */ +#define FUSE_RSTPINCFG_bp 3 /* Reset Pin Configuration bit position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PORTCTRL bit masks and bit positions */ +#define PORT_SRL_bm 0x01 /* Slew Rate Limit Enable bit mask. */ +#define PORT_SRL_bp 0 /* Slew Rate Limit Enable bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.EVSYSROUTEA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_EVOUT3_bm 0x08 /* Event Output 3 bit mask. */ +#define PORTMUX_EVOUT3_bp 3 /* Event Output 3 bit position. */ +#define PORTMUX_EVOUT4_bm 0x10 /* Event Output 4 bit mask. */ +#define PORTMUX_EVOUT4_bp 4 /* Event Output 4 bit position. */ +#define PORTMUX_EVOUT5_bm 0x20 /* Event Output 5 bit mask. */ +#define PORTMUX_EVOUT5_bp 5 /* Event Output 5 bit position. */ + +/* PORTMUX.CCLROUTEA bit masks and bit positions */ +#define PORTMUX_LUT0_bm 0x01 /* CCL LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 0 /* CCL LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x02 /* CCL LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 1 /* CCL LUT1 bit position. */ +#define PORTMUX_LUT2_bm 0x04 /* CCL LUT2 bit mask. */ +#define PORTMUX_LUT2_bp 2 /* CCL LUT2 bit position. */ +#define PORTMUX_LUT3_bm 0x08 /* CCL LUT3 bit mask. */ +#define PORTMUX_LUT3_bp 3 /* CCL LUT3 bit position. */ + +/* PORTMUX.USARTROUTEA bit masks and bit positions */ +#define PORTMUX_USART0_gm 0x03 /* Port Multiplexer USART0 group mask. */ +#define PORTMUX_USART0_gp 0 /* Port Multiplexer USART0 group position. */ +#define PORTMUX_USART00_bm (1<<0) /* Port Multiplexer USART0 bit 0 mask. */ +#define PORTMUX_USART00_bp 0 /* Port Multiplexer USART0 bit 0 position. */ +#define PORTMUX_USART01_bm (1<<1) /* Port Multiplexer USART0 bit 1 mask. */ +#define PORTMUX_USART01_bp 1 /* Port Multiplexer USART0 bit 1 position. */ +#define PORTMUX_USART1_gm 0x0C /* Port Multiplexer USART1 group mask. */ +#define PORTMUX_USART1_gp 2 /* Port Multiplexer USART1 group position. */ +#define PORTMUX_USART10_bm (1<<2) /* Port Multiplexer USART1 bit 0 mask. */ +#define PORTMUX_USART10_bp 2 /* Port Multiplexer USART1 bit 0 position. */ +#define PORTMUX_USART11_bm (1<<3) /* Port Multiplexer USART1 bit 1 mask. */ +#define PORTMUX_USART11_bp 3 /* Port Multiplexer USART1 bit 1 position. */ +#define PORTMUX_USART2_gm 0x30 /* Port Multiplexer USART2 group mask. */ +#define PORTMUX_USART2_gp 4 /* Port Multiplexer USART2 group position. */ +#define PORTMUX_USART20_bm (1<<4) /* Port Multiplexer USART2 bit 0 mask. */ +#define PORTMUX_USART20_bp 4 /* Port Multiplexer USART2 bit 0 position. */ +#define PORTMUX_USART21_bm (1<<5) /* Port Multiplexer USART2 bit 1 mask. */ +#define PORTMUX_USART21_bp 5 /* Port Multiplexer USART2 bit 1 position. */ +#define PORTMUX_USART3_gm 0xC0 /* Port Multiplexer USART3 group mask. */ +#define PORTMUX_USART3_gp 6 /* Port Multiplexer USART3 group position. */ +#define PORTMUX_USART30_bm (1<<6) /* Port Multiplexer USART3 bit 0 mask. */ +#define PORTMUX_USART30_bp 6 /* Port Multiplexer USART3 bit 0 position. */ +#define PORTMUX_USART31_bm (1<<7) /* Port Multiplexer USART3 bit 1 mask. */ +#define PORTMUX_USART31_bp 7 /* Port Multiplexer USART3 bit 1 position. */ + +/* PORTMUX.TWISPIROUTEA bit masks and bit positions */ +#define PORTMUX_SPI0_gm 0x03 /* Port Multiplexer SPI0 group mask. */ +#define PORTMUX_SPI0_gp 0 /* Port Multiplexer SPI0 group position. */ +#define PORTMUX_SPI00_bm (1<<0) /* Port Multiplexer SPI0 bit 0 mask. */ +#define PORTMUX_SPI00_bp 0 /* Port Multiplexer SPI0 bit 0 position. */ +#define PORTMUX_SPI01_bm (1<<1) /* Port Multiplexer SPI0 bit 1 mask. */ +#define PORTMUX_SPI01_bp 1 /* Port Multiplexer SPI0 bit 1 position. */ +#define PORTMUX_TWI0_gm 0x30 /* Port Multiplexer TWI0 group mask. */ +#define PORTMUX_TWI0_gp 4 /* Port Multiplexer TWI0 group position. */ +#define PORTMUX_TWI00_bm (1<<4) /* Port Multiplexer TWI0 bit 0 mask. */ +#define PORTMUX_TWI00_bp 4 /* Port Multiplexer TWI0 bit 0 position. */ +#define PORTMUX_TWI01_bm (1<<5) /* Port Multiplexer TWI0 bit 1 mask. */ +#define PORTMUX_TWI01_bp 5 /* Port Multiplexer TWI0 bit 1 position. */ + +/* PORTMUX.TCAROUTEA bit masks and bit positions */ +#define PORTMUX_TCA0_gm 0x07 /* Port Multiplexer TCA0 group mask. */ +#define PORTMUX_TCA0_gp 0 /* Port Multiplexer TCA0 group position. */ +#define PORTMUX_TCA00_bm (1<<0) /* Port Multiplexer TCA0 bit 0 mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 bit 0 position. */ +#define PORTMUX_TCA01_bm (1<<1) /* Port Multiplexer TCA0 bit 1 mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 bit 1 position. */ +#define PORTMUX_TCA02_bm (1<<2) /* Port Multiplexer TCA0 bit 2 mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 bit 2 position. */ + +/* PORTMUX.TCBROUTEA bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ +#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ +#define PORTMUX_TCB2_bm 0x04 /* Port Multiplexer TCB2 bit mask. */ +#define PORTMUX_TCB2_bp 2 /* Port Multiplexer TCB2 bit position. */ +#define PORTMUX_TCB3_bm 0x08 /* Port Multiplexer TCB3 bit mask. */ +#define PORTMUX_TCB3_bp 3 /* Port Multiplexer TCB3 bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_CORREN_bm 0x04 /* Correction enable bit mask. */ +#define RTC_CORREN_bp 2 /* Correction enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_ERROR_gm 0x7F /* Error Correction Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Correction Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Correction Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Correction Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Correction Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Correction Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Correction Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Correction Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Correction Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Correction Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Correction Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Correction Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Correction Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Correction Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Correction Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Correction Value bit 6 position. */ +#define RTC_SIGN_bm 0x80 /* Error Correction Sign Bit bit mask. */ +#define RTC_SIGN_bp 7 /* Error Correction Sign Bit bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + + +/* SYSCFG.OCDMS bit masks and bit positions */ +#define SYSCFG_OCDMR_bm 0x01 /* OCD Message Read bit mask. */ +#define SYSCFG_OCDMR_bp 0 /* OCD Message Read bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DUALCTRL bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Dual Control Enable bit mask. */ +#define TWI_ENABLE_bp 0 /* Dual Control Enable bit position. */ +/* TWI_FMPEN is already defined. */ +/* TWI_SDAHOLD is already defined. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.CTRLD bit masks and bit positions */ +#define USART_ABW_gm 0xC0 /* Auto Baud Window group mask. */ +#define USART_ABW_gp 6 /* Auto Baud Window group position. */ +#define USART_ABW0_bm (1<<6) /* Auto Baud Window bit 0 mask. */ +#define USART_ABW0_bp 6 /* Auto Baud Window bit 0 position. */ +#define USART_ABW1_bm (1<<7) /* Auto Baud Window bit 1 mask. */ +#define USART_ABW1_bp 7 /* Auto Baud Window bit 1 position. */ + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_AC0REFSEL_gm 0x07 /* AC0 reference select group mask. */ +#define VREF_AC0REFSEL_gp 0 /* AC0 reference select group position. */ +#define VREF_AC0REFSEL0_bm (1<<0) /* AC0 reference select bit 0 mask. */ +#define VREF_AC0REFSEL0_bp 0 /* AC0 reference select bit 0 position. */ +#define VREF_AC0REFSEL1_bm (1<<1) /* AC0 reference select bit 1 mask. */ +#define VREF_AC0REFSEL1_bp 1 /* AC0 reference select bit 1 position. */ +#define VREF_AC0REFSEL2_bm (1<<2) /* AC0 reference select bit 2 mask. */ +#define VREF_AC0REFSEL2_bp 2 /* AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_AC0REFEN_bm 0x01 /* AC0 DACREF reference enable bit mask. */ +#define VREF_AC0REFEN_bp 0 /* AC0 DACREF reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 3 +#define RTC_CNT_vect _VECTOR(3) /* */ +#define RTC_PIT_vect_num 4 +#define RTC_PIT_vect _VECTOR(4) /* */ + +/* CCL interrupt vectors */ +#define CCL_CCL_vect_num 5 +#define CCL_CCL_vect _VECTOR(5) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 6 +#define PORTA_PORT_vect _VECTOR(6) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 7 +#define TCA0_LUNF_vect _VECTOR(7) /* */ +#define TCA0_OVF_vect_num 7 +#define TCA0_OVF_vect _VECTOR(7) /* */ +#define TCA0_HUNF_vect_num 8 +#define TCA0_HUNF_vect _VECTOR(8) /* */ +#define TCA0_CMP0_vect_num 9 +#define TCA0_CMP0_vect _VECTOR(9) /* */ +#define TCA0_LCMP0_vect_num 9 +#define TCA0_LCMP0_vect _VECTOR(9) /* */ +#define TCA0_CMP1_vect_num 10 +#define TCA0_CMP1_vect _VECTOR(10) /* */ +#define TCA0_LCMP1_vect_num 10 +#define TCA0_LCMP1_vect _VECTOR(10) /* */ +#define TCA0_CMP2_vect_num 11 +#define TCA0_CMP2_vect _VECTOR(11) /* */ +#define TCA0_LCMP2_vect_num 11 +#define TCA0_LCMP2_vect _VECTOR(11) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 12 +#define TCB0_INT_vect _VECTOR(12) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 13 +#define TCB1_INT_vect _VECTOR(13) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 14 +#define TWI0_TWIS_vect _VECTOR(14) /* */ +#define TWI0_TWIM_vect_num 15 +#define TWI0_TWIM_vect _VECTOR(15) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 16 +#define SPI0_INT_vect _VECTOR(16) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 17 +#define USART0_RXC_vect _VECTOR(17) /* */ +#define USART0_DRE_vect_num 18 +#define USART0_DRE_vect _VECTOR(18) /* */ +#define USART0_TXC_vect_num 19 +#define USART0_TXC_vect _VECTOR(19) /* */ + +/* PORTD interrupt vectors */ +#define PORTD_PORT_vect_num 20 +#define PORTD_PORT_vect _VECTOR(20) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 21 +#define AC0_AC_vect _VECTOR(21) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 22 +#define ADC0_RESRDY_vect _VECTOR(22) /* */ +#define ADC0_WCOMP_vect_num 23 +#define ADC0_WCOMP_vect _VECTOR(23) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 24 +#define PORTC_PORT_vect _VECTOR(24) /* */ + +/* TCB2 interrupt vectors */ +#define TCB2_INT_vect_num 25 +#define TCB2_INT_vect _VECTOR(25) /* */ + +/* USART1 interrupt vectors */ +#define USART1_RXC_vect_num 26 +#define USART1_RXC_vect _VECTOR(26) /* */ +#define USART1_DRE_vect_num 27 +#define USART1_DRE_vect _VECTOR(27) /* */ +#define USART1_TXC_vect_num 28 +#define USART1_TXC_vect _VECTOR(28) /* */ + +/* PORTF interrupt vectors */ +#define PORTF_PORT_vect_num 29 +#define PORTF_PORT_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +/* USART2 interrupt vectors */ +#define USART2_RXC_vect_num 31 +#define USART2_RXC_vect _VECTOR(31) /* */ +#define USART2_DRE_vect_num 32 +#define USART2_DRE_vect _VECTOR(32) /* */ +#define USART2_TXC_vect_num 33 +#define USART2_TXC_vect _VECTOR(33) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 34 +#define PORTB_PORT_vect _VECTOR(34) /* */ + +/* PORTE interrupt vectors */ +#define PORTE_PORT_vect_num 35 +#define PORTE_PORT_vect _VECTOR(35) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (36 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (65536) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (65536U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (64) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (64U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (64) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (64U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3000) +# define INTERNAL_SRAM_SIZE (4096) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3000U) +# define INTERNAL_SRAM_SIZE (4096U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (64) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (64U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x4000) +# define MAPPED_PROGMEM_SIZE (32768) +# define MAPPED_PROGMEM_PAGE_SIZE (128) +#else +# define MAPPED_PROGMEM_START (0x4000U) +# define MAPPED_PROGMEM_SIZE (32768U) +# define MAPPED_PROGMEM_PAGE_SIZE (128U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (125) +# define PROD_SIGNATURES_PAGE_SIZE (128) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (125U) +# define PROD_SIGNATURES_PAGE_SIZE (128U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (128) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (128U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (64) +# define USER_SIGNATURES_PAGE_SIZE (64) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (64U) +# define USER_SIGNATURES_PAGE_SIZE (64U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (32768) +# define PROGMEM_PAGE_SIZE (128) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (32768U) +# define PROGMEM_PAGE_SIZE (128U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG (unsigned char)_BV(3) /* Reset Pin Configuration */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x30 + + +#endif /* #ifdef _AVR_ATMEGA3208_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iom3209.h b/hardware/tools/avr/avr/include/avr/iom3209.h new file mode 100644 index 0000000000000000000000000000000000000000..041b2720634d6f2117f8473d9cd84466183cb3fb --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom3209.h @@ -0,0 +1,5017 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom3209.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATMEGA3209_H_INCLUDED +#define _AVR_ATMEGA3209_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[1]; + register8_t DACREF; /* Referance scale control */ + register8_t reserved_3[1]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_PIN2_gc = (0x02<<0), /* Negative Pin 2 */ + AC_MUXNEG_DACREF_gc = (0x03<<0), /* DAC Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ + ADC_MUXPOS_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ + ADC_MUXPOS_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ + ADC_MUXPOS_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ + ADC_MUXPOS_DACREF_gc = (0x1C<<0), /* AC DAC Reference */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temperature sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* 0V (GND) */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t SEQCTRL1; /* Sequential Control 1 */ + register8_t reserved_1[2]; + register8_t INTCTRL0; /* Interrupt Control 0 */ + register8_t reserved_2[1]; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t LUT2CTRLA; /* LUT Control 2 A */ + register8_t LUT2CTRLB; /* LUT Control 2 B */ + register8_t LUT2CTRLC; /* LUT Control 2 C */ + register8_t TRUTH2; /* Truth 2 */ + register8_t LUT3CTRLA; /* LUT Control 3 A */ + register8_t LUT3CTRLB; /* LUT Control 3 B */ + register8_t LUT3CTRLC; /* LUT Control 3 C */ + register8_t TRUTH3; /* Truth 3 */ + register8_t reserved_3[40]; +} CCL_t; + +/* Clock Source Selection select */ +typedef enum CCL_CLKSRC_enum +{ + CCL_CLKSRC_CLKPER_gc = (0x00<<1), /* CLK_PER is clocking the LUT */ + CCL_CLKSRC_IN2_gc = (0x01<<1), /* IN[2] is clocking the LUT */ + CCL_CLKSRC_OSC20M_gc = (0x04<<1), /* 20MHz oscillator before prescaler is clocking the LUT */ + CCL_CLKSRC_OSCULP32K_gc = (0x05<<1), /* 32kHz oscillator is clocking the LUT */ + CCL_CLKSRC_OSCULP1K_gc = (0x06<<1), /* 32kHz oscillator after DIV32 is clocking the LUT */ +} CCL_CLKSRC_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL0_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_USART0_gc = (0x08<<0), /* USART0 TXD input source */ + CCL_INSEL0_SPI0_gc = (0x09<<0), /* SPI0 MOSI input source */ + CCL_INSEL0_TCA0_gc = (0x0A<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCB0_gc = (0x0C<<0), /* TCB0 WO input source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENTA_gc = (0x03<<4), /* Event input source A */ + CCL_INSEL1_EVENTB_gc = (0x04<<4), /* Event input source B */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_USART1_gc = (0x08<<4), /* USART1 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x09<<4), /* SPI0 MOSI input source */ + CCL_INSEL1_TCA0_gc = (0x0A<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCB1_gc = (0x0C<<4), /* TCB1 WO input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL2_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_USART2_gc = (0x08<<0), /* USART2 TXD input source */ + CCL_INSEL2_SPI0_gc = (0x09<<0), /* SPI0 SCK input source */ + CCL_INSEL2_TCA0_gc = (0x0A<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCB2_gc = (0x0C<<0), /* TCB2 WO input source */ +} CCL_INSEL2_t; + +/* Interrupt Mode for LUT0 select */ +typedef enum CCL_INTMODE0_enum +{ + CCL_INTMODE0_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled */ + CCL_INTMODE0_RISING_gc = (0x01<<0), /* Sense rising edge */ + CCL_INTMODE0_FALLING_gc = (0x02<<0), /* Sense falling edge */ + CCL_INTMODE0_BOTH_gc = (0x03<<0), /* Sense both edges */ +} CCL_INTMODE0_t; + +/* Interrupt Mode for LUT1 select */ +typedef enum CCL_INTMODE1_enum +{ + CCL_INTMODE1_INTDISABLE_gc = (0x00<<2), /* Interrupt disabled */ + CCL_INTMODE1_RISING_gc = (0x01<<2), /* Sense rising edge */ + CCL_INTMODE1_FALLING_gc = (0x02<<2), /* Sense falling edge */ + CCL_INTMODE1_BOTH_gc = (0x03<<2), /* Sense both edges */ +} CCL_INTMODE1_t; + +/* Interrupt Mode for LUT2 select */ +typedef enum CCL_INTMODE2_enum +{ + CCL_INTMODE2_INTDISABLE_gc = (0x00<<4), /* Interrupt disabled */ + CCL_INTMODE2_RISING_gc = (0x01<<4), /* Sense rising edge */ + CCL_INTMODE2_FALLING_gc = (0x02<<4), /* Sense falling edge */ + CCL_INTMODE2_BOTH_gc = (0x03<<4), /* Sense both edges */ +} CCL_INTMODE2_t; + +/* Interrupt Mode for LUT3 select */ +typedef enum CCL_INTMODE3_enum +{ + CCL_INTMODE3_INTDISABLE_gc = (0x00<<6), /* Interrupt disabled */ + CCL_INTMODE3_RISING_gc = (0x01<<6), /* Sense rising edge */ + CCL_INTMODE3_FALLING_gc = (0x02<<6), /* Sense falling edge */ + CCL_INTMODE3_BOTH_gc = (0x03<<6), /* Sense both edges */ +} CCL_INTMODE3_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL0_enum +{ + CCL_SEQSEL0_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL0_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL0_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL0_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL0_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL0_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL1_enum +{ + CCL_SEQSEL1_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL1_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL1_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL1_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL1_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL1_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1k cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16k cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32k cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t STROBE; /* Channel Strobe */ + register8_t reserved_1[15]; + register8_t CHANNEL0; /* Multiplexer Channel 0 */ + register8_t CHANNEL1; /* Multiplexer Channel 1 */ + register8_t CHANNEL2; /* Multiplexer Channel 2 */ + register8_t CHANNEL3; /* Multiplexer Channel 3 */ + register8_t CHANNEL4; /* Multiplexer Channel 4 */ + register8_t CHANNEL5; /* Multiplexer Channel 5 */ + register8_t CHANNEL6; /* Multiplexer Channel 6 */ + register8_t CHANNEL7; /* Multiplexer Channel 7 */ + register8_t reserved_2[8]; + register8_t USERCCLLUT0A; /* User CCL LUT0 Event A */ + register8_t USERCCLLUT0B; /* User CCL LUT0 Event B */ + register8_t USERCCLLUT1A; /* User CCL LUT1 Event A */ + register8_t USERCCLLUT1B; /* User CCL LUT1 Event B */ + register8_t USERCCLLUT2A; /* User CCL LUT2 Event A */ + register8_t USERCCLLUT2B; /* User CCL LUT2 Event B */ + register8_t USERCCLLUT3A; /* User CCL LUT3 Event A */ + register8_t USERCCLLUT3B; /* User CCL LUT3 Event B */ + register8_t USERADC0; /* User ADC0 */ + register8_t USEREVOUTA; /* User EVOUT Port A */ + register8_t USEREVOUTB; /* User EVOUT Port B */ + register8_t USEREVOUTC; /* User EVOUT Port C */ + register8_t USEREVOUTD; /* User EVOUT Port D */ + register8_t USEREVOUTE; /* User EVOUT Port E */ + register8_t USEREVOUTF; /* User EVOUT Port F */ + register8_t USERUSART0; /* User USART0 */ + register8_t USERUSART1; /* User USART1 */ + register8_t USERUSART2; /* User USART2 */ + register8_t USERUSART3; /* User USART3 */ + register8_t USERTCA0; /* User TCA0 */ + register8_t USERTCB0; /* User TCB0 */ + register8_t USERTCB1; /* User TCB1 */ + register8_t USERTCB2; /* User TCB2 */ + register8_t USERTCB3; /* User TCB3 */ + register8_t reserved_3[8]; +} EVSYS_t; + +/* Channel selector select */ +typedef enum EVSYS_CHANNEL_enum +{ + EVSYS_CHANNEL_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL_CHANNEL0_gc = (0x01<<0), /* Connect user to event channel 0 */ + EVSYS_CHANNEL_CHANNEL1_gc = (0x02<<0), /* Connect user to event channel 1 */ + EVSYS_CHANNEL_CHANNEL2_gc = (0x03<<0), /* Connect user to event channel 2 */ + EVSYS_CHANNEL_CHANNEL3_gc = (0x04<<0), /* Connect user to event channel 3 */ + EVSYS_CHANNEL_CHANNEL4_gc = (0x05<<0), /* Connect user to event channel 4 */ + EVSYS_CHANNEL_CHANNEL5_gc = (0x06<<0), /* Connect user to event channel 5 */ + EVSYS_CHANNEL_CHANNEL6_gc = (0x07<<0), /* Connect user to event channel 6 */ + EVSYS_CHANNEL_CHANNEL7_gc = (0x08<<0), /* Connect user to event channel 7 */ +} EVSYS_CHANNEL_t; + +/* Generator selector select */ +typedef enum EVSYS_GENERATOR_enum +{ + EVSYS_GENERATOR_OFF_gc = (0x00<<0), /* Off */ + EVSYS_GENERATOR_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_GENERATOR_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_GENERATOR_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_GENERATOR_RTC_PIT0_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_GENERATOR_RTC_PIT1_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_GENERATOR_RTC_PIT2_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_GENERATOR_RTC_PIT3_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_GENERATOR_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_GENERATOR_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_GENERATOR_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_GENERATOR_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_GENERATOR_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_GENERATOR_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready Event */ + EVSYS_GENERATOR_PORT0_PIN0_gc = (0x40<<0), /* Port 0 Pin 0 */ + EVSYS_GENERATOR_PORT0_PIN1_gc = (0x41<<0), /* Port 0 Pin 1 */ + EVSYS_GENERATOR_PORT0_PIN2_gc = (0x42<<0), /* Port 0 Pin 2 */ + EVSYS_GENERATOR_PORT0_PIN3_gc = (0x43<<0), /* Port 0 Pin 3 */ + EVSYS_GENERATOR_PORT0_PIN4_gc = (0x44<<0), /* Port 0 Pin 4 */ + EVSYS_GENERATOR_PORT0_PIN5_gc = (0x45<<0), /* Port 0 Pin 5 */ + EVSYS_GENERATOR_PORT0_PIN6_gc = (0x46<<0), /* Port 0 Pin 6 */ + EVSYS_GENERATOR_PORT0_PIN7_gc = (0x47<<0), /* Port 0 Pin 7 */ + EVSYS_GENERATOR_PORT1_PIN0_gc = (0x48<<0), /* Port 1 Pin 0 */ + EVSYS_GENERATOR_PORT1_PIN1_gc = (0x49<<0), /* Port 1 Pin 1 */ + EVSYS_GENERATOR_PORT1_PIN2_gc = (0x4A<<0), /* Port 1 Pin 2 */ + EVSYS_GENERATOR_PORT1_PIN3_gc = (0x4B<<0), /* Port 1 Pin 3 */ + EVSYS_GENERATOR_PORT1_PIN4_gc = (0x4C<<0), /* Port 1 Pin 4 */ + EVSYS_GENERATOR_PORT1_PIN5_gc = (0x4D<<0), /* Port 1 Pin 5 */ + EVSYS_GENERATOR_PORT1_PIN6_gc = (0x4E<<0), /* Port 1 Pin 6 */ + EVSYS_GENERATOR_PORT1_PIN7_gc = (0x4F<<0), /* Port 1 Pin 7 */ + EVSYS_GENERATOR_USART0_XCK_gc = (0x60<<0), /* USART 0 Xclock */ + EVSYS_GENERATOR_USART1_XCK_gc = (0x61<<0), /* USART 1 Xclock */ + EVSYS_GENERATOR_USART2_XCK_gc = (0x62<<0), /* USART 2 Xclock */ + EVSYS_GENERATOR_USART3_XCK_gc = (0x63<<0), /* USART 3 Xclock */ + EVSYS_GENERATOR_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_GENERATOR_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_GENERATOR_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow (split mode) */ + EVSYS_GENERATOR_TCA0_CMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_GENERATOR_TCA0_CMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_GENERATOR_TCA0_CMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_GENERATOR_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_GENERATOR_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_GENERATOR_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_GENERATOR_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ +} EVSYS_GENERATOR_t; + +/* Software event on channels select */ +typedef enum EVSYS_STROBE0_enum +{ + EVSYS_STROBE0_EV_STROBE_CH0_gc = (0x01<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH1_gc = (0x02<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH2_gc = (0x04<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH3_gc = (0x08<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH4_gc = (0x10<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH5_gc = (0x20<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH6_gc = (0x40<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH7_gc = (0x80<<0), /* */ +} EVSYS_STROBE0_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<3), /* GPIO mode */ + RSTPINCFG_RST_gc = (0x01<<3), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock Bits */ + register8_t reserved_1[1]; +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t PORTCTRL; /* Port Control */ + register8_t reserved_1[5]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t EVSYSROUTEA; /* Port Multiplexer EVSYS */ + register8_t CCLROUTEA; /* Port Multiplexer CCL */ + register8_t USARTROUTEA; /* Port Multiplexer USART register A */ + register8_t TWISPIROUTEA; /* Port Multiplexer TWI and SPI */ + register8_t TCAROUTEA; /* Port Multiplexer TCA */ + register8_t TCBROUTEA; /* Port Multiplexer TCB */ + register8_t reserved_1[10]; +} PORTMUX_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<0), /* SPI0 on PA[7:4] */ + PORTMUX_SPI0_ALT1_gc = (0x01<<0), /* SPI0 on PC[3:0] */ + PORTMUX_SPI0_ALT2_gc = (0x02<<0), /* SPI0 on PE[3:0] */ + PORTMUX_SPI0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 select */ +typedef enum PORTMUX_TCA0_enum +{ + PORTMUX_TCA0_PORTA_gc = (0x00<<0), /* TCA0 pins on PA[5:0] */ + PORTMUX_TCA0_PORTB_gc = (0x01<<0), /* TCA0 pins on PB[5:0] */ + PORTMUX_TCA0_PORTC_gc = (0x02<<0), /* TCA0 pins on PC[5:0] */ + PORTMUX_TCA0_PORTD_gc = (0x03<<0), /* TCA0 pins on PD[5:0] */ + PORTMUX_TCA0_PORTE_gc = (0x04<<0), /* TCA0 pins on PE[5:0] */ + PORTMUX_TCA0_PORTF_gc = (0x05<<0), /* TCA0 pins on PF[5:0] */ +} PORTMUX_TCA0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* SCL/SDA on PA[3:2], Slave mode on PC[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT1_gc = (0x01<<4), /* SCL/SDA on PA[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT2_gc = (0x02<<4), /* SCL/SDA on PC[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* USART0 on PA[3:0] */ + PORTMUX_USART0_ALT1_gc = (0x01<<0), /* USART0 on PA[7:4] */ + PORTMUX_USART0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_USART0_t; + +/* Port Multiplexer USART1 select */ +typedef enum PORTMUX_USART1_enum +{ + PORTMUX_USART1_DEFAULT_gc = (0x00<<2), /* USART1 on PC[3:0] */ + PORTMUX_USART1_ALT1_gc = (0x01<<2), /* USART1 on PC[7:4] */ + PORTMUX_USART1_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_USART1_t; + +/* Port Multiplexer USART2 select */ +typedef enum PORTMUX_USART2_enum +{ + PORTMUX_USART2_DEFAULT_gc = (0x00<<4), /* USART2 on PF[3:0] */ + PORTMUX_USART2_ALT1_gc = (0x01<<4), /* USART2 on PF[6:4] */ + PORTMUX_USART2_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_USART2_t; + +/* Port Multiplexer USART3 select */ +typedef enum PORTMUX_USART3_enum +{ + PORTMUX_USART3_DEFAULT_gc = (0x00<<6), /* USART3 on PB[3:0] */ + PORTMUX_USART3_ALT1_gc = (0x01<<6), /* USART3 on PB[5:4] */ + PORTMUX_USART3_NONE_gc = (0x03<<6), /* Not connected to any pins */ +} PORTMUX_USART3_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t CALIB; /* Calibration */ + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_1[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_2[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_3[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[7]; + register8_t OSCCAL32K; /* Oscillator Calibration for 32kHz ULP */ + register8_t reserved_2[3]; + register8_t OSCCAL16M0; /* Oscillator Calibration 16 MHz Byte 0 */ + register8_t OSCCAL16M1; /* Oscillator Calibration 16 MHz Byte 1 */ + register8_t OSCCAL20M0; /* Oscillator Calibration 20 MHz Byte 0 */ + register8_t OSCCAL20M1; /* Oscillator Calibration 20 MHz Byte 1 */ + register8_t reserved_3[4]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_4[9]; + register8_t CHECKSUM1; /* CRC Checksum Byte 1 */ + register8_t reserved_5[16]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[21]; + register8_t OCDM; /* OCD Message Register */ + register8_t OCDMS; /* OCD Message Status */ + register8_t reserved_3[6]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t DUALCTRL; /* Dual Control */ + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_1[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t CTRLD; /* Control D */ + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_1[1]; +} USART_t; + +/* Auto Baud Window select */ +typedef enum USART_ABW_enum +{ + USART_ABW_WDW0_gc = (0x00<<6), /* 18% tolerance */ + USART_ABW_WDW1_gc = (0x01<<6), /* 15% tolerance */ + USART_ABW_WDW2_gc = (0x02<<6), /* 21% tolerance */ + USART_ABW_WDW3_gc = (0x03<<6), /* 25% tolerance */ +} USART_ABW_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ + register8_t USERROW32; /* User Row Byte 32 */ + register8_t USERROW33; /* User Row Byte 33 */ + register8_t USERROW34; /* User Row Byte 34 */ + register8_t USERROW35; /* User Row Byte 35 */ + register8_t USERROW36; /* User Row Byte 36 */ + register8_t USERROW37; /* User Row Byte 37 */ + register8_t USERROW38; /* User Row Byte 38 */ + register8_t USERROW39; /* User Row Byte 39 */ + register8_t USERROW40; /* User Row Byte 40 */ + register8_t USERROW41; /* User Row Byte 41 */ + register8_t USERROW42; /* User Row Byte 42 */ + register8_t USERROW43; /* User Row Byte 43 */ + register8_t USERROW44; /* User Row Byte 44 */ + register8_t USERROW45; /* User Row Byte 45 */ + register8_t USERROW46; /* User Row Byte 46 */ + register8_t USERROW47; /* User Row Byte 47 */ + register8_t USERROW48; /* User Row Byte 48 */ + register8_t USERROW49; /* User Row Byte 49 */ + register8_t USERROW50; /* User Row Byte 50 */ + register8_t USERROW51; /* User Row Byte 51 */ + register8_t USERROW52; /* User Row Byte 52 */ + register8_t USERROW53; /* User Row Byte 53 */ + register8_t USERROW54; /* User Row Byte 54 */ + register8_t USERROW55; /* User Row Byte 55 */ + register8_t USERROW56; /* User Row Byte 56 */ + register8_t USERROW57; /* User Row Byte 57 */ + register8_t USERROW58; /* User Row Byte 58 */ + register8_t USERROW59; /* User Row Byte 59 */ + register8_t USERROW60; /* User Row Byte 60 */ + register8_t USERROW61; /* User Row Byte 61 */ + register8_t USERROW62; /* User Row Byte 62 */ + register8_t USERROW63; /* User Row Byte 63 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* AC0 reference select select */ +typedef enum VREF_AC0REFSEL_enum +{ + VREF_AC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_AC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_AC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_AC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_AC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ + VREF_AC0REFSEL_AVDD_gc = (0x07<<0), /* AVDD */ +} VREF_AC0REFSEL_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define VPORTD (*(VPORT_t *) 0x000C) /* Virtual Ports */ +#define VPORTE (*(VPORT_t *) 0x0010) /* Virtual Ports */ +#define VPORTF (*(VPORT_t *) 0x0014) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0460) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0480) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x04A0) /* I/O Ports */ +#define PORTMUX (*(PORTMUX_t *) 0x05E0) /* Port Multiplexer */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1 (*(USART_t *) 0x0820) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2 (*(USART_t *) 0x0840) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART3 (*(USART_t *) 0x0860) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x08A0) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A80) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0A90) /* 16-bit Timer Type B */ +#define TCB2 (*(TCB_t *) 0x0AA0) /* 16-bit Timer Type B */ +#define TCB3 (*(TCB_t *) 0x0AB0) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* VPORT (VPORTD) - Virtual Ports */ +#define VPORTD_DIR _SFR_MEM8(0x000C) +#define VPORTD_OUT _SFR_MEM8(0x000D) +#define VPORTD_IN _SFR_MEM8(0x000E) +#define VPORTD_INTFLAGS _SFR_MEM8(0x000F) + + +/* VPORT (VPORTE) - Virtual Ports */ +#define VPORTE_DIR _SFR_MEM8(0x0010) +#define VPORTE_OUT _SFR_MEM8(0x0011) +#define VPORTE_IN _SFR_MEM8(0x0012) +#define VPORTE_INTFLAGS _SFR_MEM8(0x0013) + + +/* VPORT (VPORTF) - Virtual Ports */ +#define VPORTF_DIR _SFR_MEM8(0x0014) +#define VPORTF_OUT _SFR_MEM8(0x0015) +#define VPORTF_IN _SFR_MEM8(0x0016) +#define VPORTF_INTFLAGS _SFR_MEM8(0x0017) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CALIB _SFR_MEM8(0x0146) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_STROBE _SFR_MEM8(0x0180) +#define EVSYS_CHANNEL0 _SFR_MEM8(0x0190) +#define EVSYS_CHANNEL1 _SFR_MEM8(0x0191) +#define EVSYS_CHANNEL2 _SFR_MEM8(0x0192) +#define EVSYS_CHANNEL3 _SFR_MEM8(0x0193) +#define EVSYS_CHANNEL4 _SFR_MEM8(0x0194) +#define EVSYS_CHANNEL5 _SFR_MEM8(0x0195) +#define EVSYS_CHANNEL6 _SFR_MEM8(0x0196) +#define EVSYS_CHANNEL7 _SFR_MEM8(0x0197) +#define EVSYS_USERCCLLUT0A _SFR_MEM8(0x01A0) +#define EVSYS_USERCCLLUT0B _SFR_MEM8(0x01A1) +#define EVSYS_USERCCLLUT1A _SFR_MEM8(0x01A2) +#define EVSYS_USERCCLLUT1B _SFR_MEM8(0x01A3) +#define EVSYS_USERCCLLUT2A _SFR_MEM8(0x01A4) +#define EVSYS_USERCCLLUT2B _SFR_MEM8(0x01A5) +#define EVSYS_USERCCLLUT3A _SFR_MEM8(0x01A6) +#define EVSYS_USERCCLLUT3B _SFR_MEM8(0x01A7) +#define EVSYS_USERADC0 _SFR_MEM8(0x01A8) +#define EVSYS_USEREVOUTA _SFR_MEM8(0x01A9) +#define EVSYS_USEREVOUTB _SFR_MEM8(0x01AA) +#define EVSYS_USEREVOUTC _SFR_MEM8(0x01AB) +#define EVSYS_USEREVOUTD _SFR_MEM8(0x01AC) +#define EVSYS_USEREVOUTE _SFR_MEM8(0x01AD) +#define EVSYS_USEREVOUTF _SFR_MEM8(0x01AE) +#define EVSYS_USERUSART0 _SFR_MEM8(0x01AF) +#define EVSYS_USERUSART1 _SFR_MEM8(0x01B0) +#define EVSYS_USERUSART2 _SFR_MEM8(0x01B1) +#define EVSYS_USERUSART3 _SFR_MEM8(0x01B2) +#define EVSYS_USERTCA0 _SFR_MEM8(0x01B3) +#define EVSYS_USERTCB0 _SFR_MEM8(0x01B4) +#define EVSYS_USERTCB1 _SFR_MEM8(0x01B5) +#define EVSYS_USERTCB2 _SFR_MEM8(0x01B6) +#define EVSYS_USERTCB3 _SFR_MEM8(0x01B7) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_SEQCTRL1 _SFR_MEM8(0x01C2) +#define CCL_INTCTRL0 _SFR_MEM8(0x01C5) +#define CCL_INTFLAGS _SFR_MEM8(0x01C7) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C8) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C9) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01CA) +#define CCL_TRUTH0 _SFR_MEM8(0x01CB) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01CC) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CD) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CE) +#define CCL_TRUTH1 _SFR_MEM8(0x01CF) +#define CCL_LUT2CTRLA _SFR_MEM8(0x01D0) +#define CCL_LUT2CTRLB _SFR_MEM8(0x01D1) +#define CCL_LUT2CTRLC _SFR_MEM8(0x01D2) +#define CCL_TRUTH2 _SFR_MEM8(0x01D3) +#define CCL_LUT3CTRLA _SFR_MEM8(0x01D4) +#define CCL_LUT3CTRLB _SFR_MEM8(0x01D5) +#define CCL_LUT3CTRLC _SFR_MEM8(0x01D6) +#define CCL_TRUTH3 _SFR_MEM8(0x01D7) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PORTCTRL _SFR_MEM8(0x040A) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PORTCTRL _SFR_MEM8(0x042A) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PORTCTRL _SFR_MEM8(0x044A) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* PORT (PORTD) - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0460) +#define PORTD_DIRSET _SFR_MEM8(0x0461) +#define PORTD_DIRCLR _SFR_MEM8(0x0462) +#define PORTD_DIRTGL _SFR_MEM8(0x0463) +#define PORTD_OUT _SFR_MEM8(0x0464) +#define PORTD_OUTSET _SFR_MEM8(0x0465) +#define PORTD_OUTCLR _SFR_MEM8(0x0466) +#define PORTD_OUTTGL _SFR_MEM8(0x0467) +#define PORTD_IN _SFR_MEM8(0x0468) +#define PORTD_INTFLAGS _SFR_MEM8(0x0469) +#define PORTD_PORTCTRL _SFR_MEM8(0x046A) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0470) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0471) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0472) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0473) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0474) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0475) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0476) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0477) + + +/* PORT (PORTE) - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0480) +#define PORTE_DIRSET _SFR_MEM8(0x0481) +#define PORTE_DIRCLR _SFR_MEM8(0x0482) +#define PORTE_DIRTGL _SFR_MEM8(0x0483) +#define PORTE_OUT _SFR_MEM8(0x0484) +#define PORTE_OUTSET _SFR_MEM8(0x0485) +#define PORTE_OUTCLR _SFR_MEM8(0x0486) +#define PORTE_OUTTGL _SFR_MEM8(0x0487) +#define PORTE_IN _SFR_MEM8(0x0488) +#define PORTE_INTFLAGS _SFR_MEM8(0x0489) +#define PORTE_PORTCTRL _SFR_MEM8(0x048A) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0490) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0491) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0492) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0493) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0494) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0495) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0496) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0497) + + +/* PORT (PORTF) - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x04A0) +#define PORTF_DIRSET _SFR_MEM8(0x04A1) +#define PORTF_DIRCLR _SFR_MEM8(0x04A2) +#define PORTF_DIRTGL _SFR_MEM8(0x04A3) +#define PORTF_OUT _SFR_MEM8(0x04A4) +#define PORTF_OUTSET _SFR_MEM8(0x04A5) +#define PORTF_OUTCLR _SFR_MEM8(0x04A6) +#define PORTF_OUTTGL _SFR_MEM8(0x04A7) +#define PORTF_IN _SFR_MEM8(0x04A8) +#define PORTF_INTFLAGS _SFR_MEM8(0x04A9) +#define PORTF_PORTCTRL _SFR_MEM8(0x04AA) +#define PORTF_PIN0CTRL _SFR_MEM8(0x04B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x04B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x04B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x04B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x04B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x04B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x04B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x04B7) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_EVSYSROUTEA _SFR_MEM8(0x05E0) +#define PORTMUX_CCLROUTEA _SFR_MEM8(0x05E1) +#define PORTMUX_USARTROUTEA _SFR_MEM8(0x05E2) +#define PORTMUX_TWISPIROUTEA _SFR_MEM8(0x05E3) +#define PORTMUX_TCAROUTEA _SFR_MEM8(0x05E4) +#define PORTMUX_TCBROUTEA _SFR_MEM8(0x05E5) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_DACREF _SFR_MEM8(0x0684) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_CTRLD _SFR_MEM8(0x080A) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* USART (USART1) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1_RXDATAL _SFR_MEM8(0x0820) +#define USART1_RXDATAH _SFR_MEM8(0x0821) +#define USART1_TXDATAL _SFR_MEM8(0x0822) +#define USART1_TXDATAH _SFR_MEM8(0x0823) +#define USART1_STATUS _SFR_MEM8(0x0824) +#define USART1_CTRLA _SFR_MEM8(0x0825) +#define USART1_CTRLB _SFR_MEM8(0x0826) +#define USART1_CTRLC _SFR_MEM8(0x0827) +#define USART1_BAUD _SFR_MEM16(0x0828) +#define USART1_BAUDL _SFR_MEM8(0x0828) +#define USART1_BAUDH _SFR_MEM8(0x0829) +#define USART1_CTRLD _SFR_MEM8(0x082A) +#define USART1_DBGCTRL _SFR_MEM8(0x082B) +#define USART1_EVCTRL _SFR_MEM8(0x082C) +#define USART1_TXPLCTRL _SFR_MEM8(0x082D) +#define USART1_RXPLCTRL _SFR_MEM8(0x082E) + + +/* USART (USART2) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2_RXDATAL _SFR_MEM8(0x0840) +#define USART2_RXDATAH _SFR_MEM8(0x0841) +#define USART2_TXDATAL _SFR_MEM8(0x0842) +#define USART2_TXDATAH _SFR_MEM8(0x0843) +#define USART2_STATUS _SFR_MEM8(0x0844) +#define USART2_CTRLA _SFR_MEM8(0x0845) +#define USART2_CTRLB _SFR_MEM8(0x0846) +#define USART2_CTRLC _SFR_MEM8(0x0847) +#define USART2_BAUD _SFR_MEM16(0x0848) +#define USART2_BAUDL _SFR_MEM8(0x0848) +#define USART2_BAUDH _SFR_MEM8(0x0849) +#define USART2_CTRLD _SFR_MEM8(0x084A) +#define USART2_DBGCTRL _SFR_MEM8(0x084B) +#define USART2_EVCTRL _SFR_MEM8(0x084C) +#define USART2_TXPLCTRL _SFR_MEM8(0x084D) +#define USART2_RXPLCTRL _SFR_MEM8(0x084E) + + +/* USART (USART3) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART3_RXDATAL _SFR_MEM8(0x0860) +#define USART3_RXDATAH _SFR_MEM8(0x0861) +#define USART3_TXDATAL _SFR_MEM8(0x0862) +#define USART3_TXDATAH _SFR_MEM8(0x0863) +#define USART3_STATUS _SFR_MEM8(0x0864) +#define USART3_CTRLA _SFR_MEM8(0x0865) +#define USART3_CTRLB _SFR_MEM8(0x0866) +#define USART3_CTRLC _SFR_MEM8(0x0867) +#define USART3_BAUD _SFR_MEM16(0x0868) +#define USART3_BAUDL _SFR_MEM8(0x0868) +#define USART3_BAUDH _SFR_MEM8(0x0869) +#define USART3_CTRLD _SFR_MEM8(0x086A) +#define USART3_DBGCTRL _SFR_MEM8(0x086B) +#define USART3_EVCTRL _SFR_MEM8(0x086C) +#define USART3_TXPLCTRL _SFR_MEM8(0x086D) +#define USART3_RXPLCTRL _SFR_MEM8(0x086E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x08A0) +#define TWI0_DUALCTRL _SFR_MEM8(0x08A1) +#define TWI0_DBGCTRL _SFR_MEM8(0x08A2) +#define TWI0_MCTRLA _SFR_MEM8(0x08A3) +#define TWI0_MCTRLB _SFR_MEM8(0x08A4) +#define TWI0_MSTATUS _SFR_MEM8(0x08A5) +#define TWI0_MBAUD _SFR_MEM8(0x08A6) +#define TWI0_MADDR _SFR_MEM8(0x08A7) +#define TWI0_MDATA _SFR_MEM8(0x08A8) +#define TWI0_SCTRLA _SFR_MEM8(0x08A9) +#define TWI0_SCTRLB _SFR_MEM8(0x08AA) +#define TWI0_SSTATUS _SFR_MEM8(0x08AB) +#define TWI0_SADDR _SFR_MEM8(0x08AC) +#define TWI0_SDATA _SFR_MEM8(0x08AD) +#define TWI0_SADDRMASK _SFR_MEM8(0x08AE) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x08C0) +#define SPI0_CTRLB _SFR_MEM8(0x08C1) +#define SPI0_INTCTRL _SFR_MEM8(0x08C2) +#define SPI0_INTFLAGS _SFR_MEM8(0x08C3) +#define SPI0_DATA _SFR_MEM8(0x08C4) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A80) +#define TCB0_CTRLB _SFR_MEM8(0x0A81) +#define TCB0_EVCTRL _SFR_MEM8(0x0A84) +#define TCB0_INTCTRL _SFR_MEM8(0x0A85) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A86) +#define TCB0_STATUS _SFR_MEM8(0x0A87) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A88) +#define TCB0_TEMP _SFR_MEM8(0x0A89) +#define TCB0_CNT _SFR_MEM16(0x0A8A) +#define TCB0_CNTL _SFR_MEM8(0x0A8A) +#define TCB0_CNTH _SFR_MEM8(0x0A8B) +#define TCB0_CCMP _SFR_MEM16(0x0A8C) +#define TCB0_CCMPL _SFR_MEM8(0x0A8C) +#define TCB0_CCMPH _SFR_MEM8(0x0A8D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0A90) +#define TCB1_CTRLB _SFR_MEM8(0x0A91) +#define TCB1_EVCTRL _SFR_MEM8(0x0A94) +#define TCB1_INTCTRL _SFR_MEM8(0x0A95) +#define TCB1_INTFLAGS _SFR_MEM8(0x0A96) +#define TCB1_STATUS _SFR_MEM8(0x0A97) +#define TCB1_DBGCTRL _SFR_MEM8(0x0A98) +#define TCB1_TEMP _SFR_MEM8(0x0A99) +#define TCB1_CNT _SFR_MEM16(0x0A9A) +#define TCB1_CNTL _SFR_MEM8(0x0A9A) +#define TCB1_CNTH _SFR_MEM8(0x0A9B) +#define TCB1_CCMP _SFR_MEM16(0x0A9C) +#define TCB1_CCMPL _SFR_MEM8(0x0A9C) +#define TCB1_CCMPH _SFR_MEM8(0x0A9D) + + +/* TCB (TCB2) - 16-bit Timer Type B */ +#define TCB2_CTRLA _SFR_MEM8(0x0AA0) +#define TCB2_CTRLB _SFR_MEM8(0x0AA1) +#define TCB2_EVCTRL _SFR_MEM8(0x0AA4) +#define TCB2_INTCTRL _SFR_MEM8(0x0AA5) +#define TCB2_INTFLAGS _SFR_MEM8(0x0AA6) +#define TCB2_STATUS _SFR_MEM8(0x0AA7) +#define TCB2_DBGCTRL _SFR_MEM8(0x0AA8) +#define TCB2_TEMP _SFR_MEM8(0x0AA9) +#define TCB2_CNT _SFR_MEM16(0x0AAA) +#define TCB2_CNTL _SFR_MEM8(0x0AAA) +#define TCB2_CNTH _SFR_MEM8(0x0AAB) +#define TCB2_CCMP _SFR_MEM16(0x0AAC) +#define TCB2_CCMPL _SFR_MEM8(0x0AAC) +#define TCB2_CCMPH _SFR_MEM8(0x0AAD) + + +/* TCB (TCB3) - 16-bit Timer Type B */ +#define TCB3_CTRLA _SFR_MEM8(0x0AB0) +#define TCB3_CTRLB _SFR_MEM8(0x0AB1) +#define TCB3_EVCTRL _SFR_MEM8(0x0AB4) +#define TCB3_INTCTRL _SFR_MEM8(0x0AB5) +#define TCB3_INTFLAGS _SFR_MEM8(0x0AB6) +#define TCB3_STATUS _SFR_MEM8(0x0AB7) +#define TCB3_DBGCTRL _SFR_MEM8(0x0AB8) +#define TCB3_TEMP _SFR_MEM8(0x0AB9) +#define TCB3_CNT _SFR_MEM16(0x0ABA) +#define TCB3_CNTL _SFR_MEM8(0x0ABA) +#define TCB3_CNTH _SFR_MEM8(0x0ABB) +#define TCB3_CCMP _SFR_MEM16(0x0ABC) +#define TCB3_CCMPL _SFR_MEM8(0x0ABC) +#define TCB3_CCMPH _SFR_MEM8(0x0ABD) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) +#define SYSCFG_OCDM _SFR_MEM8(0x0F18) +#define SYSCFG_OCDMS _SFR_MEM8(0x0F19) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_OSCCAL32K _SFR_MEM8(0x1114) +#define SIGROW_OSCCAL16M0 _SFR_MEM8(0x1118) +#define SIGROW_OSCCAL16M1 _SFR_MEM8(0x1119) +#define SIGROW_OSCCAL20M0 _SFR_MEM8(0x111A) +#define SIGROW_OSCCAL20M1 _SFR_MEM8(0x111B) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) +#define SIGROW_CHECKSUM1 _SFR_MEM8(0x112F) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) +#define USERROW_USERROW32 _SFR_MEM8(0x1320) +#define USERROW_USERROW33 _SFR_MEM8(0x1321) +#define USERROW_USERROW34 _SFR_MEM8(0x1322) +#define USERROW_USERROW35 _SFR_MEM8(0x1323) +#define USERROW_USERROW36 _SFR_MEM8(0x1324) +#define USERROW_USERROW37 _SFR_MEM8(0x1325) +#define USERROW_USERROW38 _SFR_MEM8(0x1326) +#define USERROW_USERROW39 _SFR_MEM8(0x1327) +#define USERROW_USERROW40 _SFR_MEM8(0x1328) +#define USERROW_USERROW41 _SFR_MEM8(0x1329) +#define USERROW_USERROW42 _SFR_MEM8(0x132A) +#define USERROW_USERROW43 _SFR_MEM8(0x132B) +#define USERROW_USERROW44 _SFR_MEM8(0x132C) +#define USERROW_USERROW45 _SFR_MEM8(0x132D) +#define USERROW_USERROW46 _SFR_MEM8(0x132E) +#define USERROW_USERROW47 _SFR_MEM8(0x132F) +#define USERROW_USERROW48 _SFR_MEM8(0x1330) +#define USERROW_USERROW49 _SFR_MEM8(0x1331) +#define USERROW_USERROW50 _SFR_MEM8(0x1332) +#define USERROW_USERROW51 _SFR_MEM8(0x1333) +#define USERROW_USERROW52 _SFR_MEM8(0x1334) +#define USERROW_USERROW53 _SFR_MEM8(0x1335) +#define USERROW_USERROW54 _SFR_MEM8(0x1336) +#define USERROW_USERROW55 _SFR_MEM8(0x1337) +#define USERROW_USERROW56 _SFR_MEM8(0x1338) +#define USERROW_USERROW57 _SFR_MEM8(0x1339) +#define USERROW_USERROW58 _SFR_MEM8(0x133A) +#define USERROW_USERROW59 _SFR_MEM8(0x133B) +#define USERROW_USERROW60 _SFR_MEM8(0x133C) +#define USERROW_USERROW61 _SFR_MEM8(0x133D) +#define USERROW_USERROW62 _SFR_MEM8(0x133E) +#define USERROW_USERROW63 _SFR_MEM8(0x133F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.DACREF bit masks and bit positions */ +#define AC_DATA_gm 0xFF /* DAC voltage reference group mask. */ +#define AC_DATA_gp 0 /* DAC voltage reference group position. */ +#define AC_DATA0_bm (1<<0) /* DAC voltage reference bit 0 mask. */ +#define AC_DATA0_bp 0 /* DAC voltage reference bit 0 position. */ +#define AC_DATA1_bm (1<<1) /* DAC voltage reference bit 1 mask. */ +#define AC_DATA1_bp 1 /* DAC voltage reference bit 1 position. */ +#define AC_DATA2_bm (1<<2) /* DAC voltage reference bit 2 mask. */ +#define AC_DATA2_bp 2 /* DAC voltage reference bit 2 position. */ +#define AC_DATA3_bm (1<<3) /* DAC voltage reference bit 3 mask. */ +#define AC_DATA3_bp 3 /* DAC voltage reference bit 3 position. */ +#define AC_DATA4_bm (1<<4) /* DAC voltage reference bit 4 mask. */ +#define AC_DATA4_bp 4 /* DAC voltage reference bit 4 position. */ +#define AC_DATA5_bm (1<<5) /* DAC voltage reference bit 5 mask. */ +#define AC_DATA5_bp 5 /* DAC voltage reference bit 5 position. */ +#define AC_DATA6_bm (1<<6) /* DAC voltage reference bit 6 mask. */ +#define AC_DATA6_bp 6 /* DAC voltage reference bit 6 position. */ +#define AC_DATA7_bm (1<<7) /* DAC voltage reference bit 7 mask. */ +#define AC_DATA7_bp 7 /* DAC voltage reference bit 7 position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL0_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL0_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL00_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL00_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL01_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL01_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL02_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL02_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.SEQCTRL1 bit masks and bit positions */ +#define CCL_SEQSEL1_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL1_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL10_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL10_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL11_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL11_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL12_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL12_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.INTCTRL0 bit masks and bit positions */ +#define CCL_INTMODE0_gm 0x03 /* Interrupt Mode for LUT0 group mask. */ +#define CCL_INTMODE0_gp 0 /* Interrupt Mode for LUT0 group position. */ +#define CCL_INTMODE00_bm (1<<0) /* Interrupt Mode for LUT0 bit 0 mask. */ +#define CCL_INTMODE00_bp 0 /* Interrupt Mode for LUT0 bit 0 position. */ +#define CCL_INTMODE01_bm (1<<1) /* Interrupt Mode for LUT0 bit 1 mask. */ +#define CCL_INTMODE01_bp 1 /* Interrupt Mode for LUT0 bit 1 position. */ +#define CCL_INTMODE1_gm 0x0C /* Interrupt Mode for LUT1 group mask. */ +#define CCL_INTMODE1_gp 2 /* Interrupt Mode for LUT1 group position. */ +#define CCL_INTMODE10_bm (1<<2) /* Interrupt Mode for LUT1 bit 0 mask. */ +#define CCL_INTMODE10_bp 2 /* Interrupt Mode for LUT1 bit 0 position. */ +#define CCL_INTMODE11_bm (1<<3) /* Interrupt Mode for LUT1 bit 1 mask. */ +#define CCL_INTMODE11_bp 3 /* Interrupt Mode for LUT1 bit 1 position. */ +#define CCL_INTMODE2_gm 0x30 /* Interrupt Mode for LUT2 group mask. */ +#define CCL_INTMODE2_gp 4 /* Interrupt Mode for LUT2 group position. */ +#define CCL_INTMODE20_bm (1<<4) /* Interrupt Mode for LUT2 bit 0 mask. */ +#define CCL_INTMODE20_bp 4 /* Interrupt Mode for LUT2 bit 0 position. */ +#define CCL_INTMODE21_bm (1<<5) /* Interrupt Mode for LUT2 bit 1 mask. */ +#define CCL_INTMODE21_bp 5 /* Interrupt Mode for LUT2 bit 1 position. */ +#define CCL_INTMODE3_gm 0xC0 /* Interrupt Mode for LUT3 group mask. */ +#define CCL_INTMODE3_gp 6 /* Interrupt Mode for LUT3 group position. */ +#define CCL_INTMODE30_bm (1<<6) /* Interrupt Mode for LUT3 bit 0 mask. */ +#define CCL_INTMODE30_bp 6 /* Interrupt Mode for LUT3 bit 0 position. */ +#define CCL_INTMODE31_bm (1<<7) /* Interrupt Mode for LUT3 bit 1 mask. */ +#define CCL_INTMODE31_bp 7 /* Interrupt Mode for LUT3 bit 1 position. */ + +/* CCL.INTFLAGS bit masks and bit positions */ +#define CCL_INT_gm 0x0F /* Interrupt Flags group mask. */ +#define CCL_INT_gp 0 /* Interrupt Flags group position. */ +#define CCL_INT0_bm (1<<0) /* Interrupt Flags bit 0 mask. */ +#define CCL_INT0_bp 0 /* Interrupt Flags bit 0 position. */ +#define CCL_INT1_bm (1<<1) /* Interrupt Flags bit 1 mask. */ +#define CCL_INT1_bp 1 /* Interrupt Flags bit 1 position. */ +#define CCL_INT2_bm (1<<2) /* Interrupt Flags bit 2 mask. */ +#define CCL_INT2_bp 2 /* Interrupt Flags bit 2 position. */ +#define CCL_INT3_bm (1<<3) /* Interrupt Flags bit 3 mask. */ +#define CCL_INT3_bp 3 /* Interrupt Flags bit 3 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_CLKSRC_gm 0x0E /* Clock Source Selection group mask. */ +#define CCL_CLKSRC_gp 1 /* Clock Source Selection group position. */ +#define CCL_CLKSRC0_bm (1<<1) /* Clock Source Selection bit 0 mask. */ +#define CCL_CLKSRC0_bp 1 /* Clock Source Selection bit 0 position. */ +#define CCL_CLKSRC1_bm (1<<2) /* Clock Source Selection bit 1 mask. */ +#define CCL_CLKSRC1_bp 2 /* Clock Source Selection bit 1 position. */ +#define CCL_CLKSRC2_bm (1<<3) /* Clock Source Selection bit 2 mask. */ +#define CCL_CLKSRC2_bp 3 /* Clock Source Selection bit 2 position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_OUTEN_bm 0x40 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 6 /* Output Enable bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT2CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT2CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT2CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT3CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT3CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT3CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x7F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ +#define CLKCTRL_CAL20M6_bm (1<<6) /* Calibration bit 6 mask. */ +#define CLKCTRL_CAL20M6_bp 6 /* Calibration bit 6 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.STROBE bit masks and bit positions */ +#define EVSYS_STROBE0_gm 0xFF /* Software event on channels group mask. */ +#define EVSYS_STROBE0_gp 0 /* Software event on channels group position. */ +#define EVSYS_STROBE00_bm (1<<0) /* Software event on channels bit 0 mask. */ +#define EVSYS_STROBE00_bp 0 /* Software event on channels bit 0 position. */ +#define EVSYS_STROBE01_bm (1<<1) /* Software event on channels bit 1 mask. */ +#define EVSYS_STROBE01_bp 1 /* Software event on channels bit 1 position. */ +#define EVSYS_STROBE02_bm (1<<2) /* Software event on channels bit 2 mask. */ +#define EVSYS_STROBE02_bp 2 /* Software event on channels bit 2 position. */ +#define EVSYS_STROBE03_bm (1<<3) /* Software event on channels bit 3 mask. */ +#define EVSYS_STROBE03_bp 3 /* Software event on channels bit 3 position. */ +#define EVSYS_STROBE04_bm (1<<4) /* Software event on channels bit 4 mask. */ +#define EVSYS_STROBE04_bp 4 /* Software event on channels bit 4 position. */ +#define EVSYS_STROBE05_bm (1<<5) /* Software event on channels bit 5 mask. */ +#define EVSYS_STROBE05_bp 5 /* Software event on channels bit 5 position. */ +#define EVSYS_STROBE06_bm (1<<6) /* Software event on channels bit 6 mask. */ +#define EVSYS_STROBE06_bp 6 /* Software event on channels bit 6 position. */ +#define EVSYS_STROBE07_bm (1<<7) /* Software event on channels bit 7 mask. */ +#define EVSYS_STROBE07_bp 7 /* Software event on channels bit 7 position. */ + +/* EVSYS.CHANNEL0 bit masks and bit positions */ +#define EVSYS_GENERATOR_gm 0xFF /* Generator selector group mask. */ +#define EVSYS_GENERATOR_gp 0 /* Generator selector group position. */ +#define EVSYS_GENERATOR0_bm (1<<0) /* Generator selector bit 0 mask. */ +#define EVSYS_GENERATOR0_bp 0 /* Generator selector bit 0 position. */ +#define EVSYS_GENERATOR1_bm (1<<1) /* Generator selector bit 1 mask. */ +#define EVSYS_GENERATOR1_bp 1 /* Generator selector bit 1 position. */ +#define EVSYS_GENERATOR2_bm (1<<2) /* Generator selector bit 2 mask. */ +#define EVSYS_GENERATOR2_bp 2 /* Generator selector bit 2 position. */ +#define EVSYS_GENERATOR3_bm (1<<3) /* Generator selector bit 3 mask. */ +#define EVSYS_GENERATOR3_bp 3 /* Generator selector bit 3 position. */ +#define EVSYS_GENERATOR4_bm (1<<4) /* Generator selector bit 4 mask. */ +#define EVSYS_GENERATOR4_bp 4 /* Generator selector bit 4 position. */ +#define EVSYS_GENERATOR5_bm (1<<5) /* Generator selector bit 5 mask. */ +#define EVSYS_GENERATOR5_bp 5 /* Generator selector bit 5 position. */ +#define EVSYS_GENERATOR6_bm (1<<6) /* Generator selector bit 6 mask. */ +#define EVSYS_GENERATOR6_bp 6 /* Generator selector bit 6 position. */ +#define EVSYS_GENERATOR7_bm (1<<7) /* Generator selector bit 7 mask. */ +#define EVSYS_GENERATOR7_bp 7 /* Generator selector bit 7 position. */ + +/* EVSYS.CHANNEL1 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL2 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL3 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL4 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL5 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL6 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL7 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.USERCCLLUT0A bit masks and bit positions */ +#define EVSYS_CHANNEL_gm 0xFF /* Channel selector group mask. */ +#define EVSYS_CHANNEL_gp 0 /* Channel selector group position. */ +#define EVSYS_CHANNEL0_bm (1<<0) /* Channel selector bit 0 mask. */ +#define EVSYS_CHANNEL0_bp 0 /* Channel selector bit 0 position. */ +#define EVSYS_CHANNEL1_bm (1<<1) /* Channel selector bit 1 mask. */ +#define EVSYS_CHANNEL1_bp 1 /* Channel selector bit 1 position. */ +#define EVSYS_CHANNEL2_bm (1<<2) /* Channel selector bit 2 mask. */ +#define EVSYS_CHANNEL2_bp 2 /* Channel selector bit 2 position. */ +#define EVSYS_CHANNEL3_bm (1<<3) /* Channel selector bit 3 mask. */ +#define EVSYS_CHANNEL3_bp 3 /* Channel selector bit 3 position. */ +#define EVSYS_CHANNEL4_bm (1<<4) /* Channel selector bit 4 mask. */ +#define EVSYS_CHANNEL4_bp 4 /* Channel selector bit 4 position. */ +#define EVSYS_CHANNEL5_bm (1<<5) /* Channel selector bit 5 mask. */ +#define EVSYS_CHANNEL5_bp 5 /* Channel selector bit 5 position. */ +#define EVSYS_CHANNEL6_bm (1<<6) /* Channel selector bit 6 mask. */ +#define EVSYS_CHANNEL6_bp 6 /* Channel selector bit 6 position. */ +#define EVSYS_CHANNEL7_bm (1<<7) /* Channel selector bit 7 mask. */ +#define EVSYS_CHANNEL7_bp 7 /* Channel selector bit 7 position. */ + +/* EVSYS.USERCCLLUT0B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT1A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT1B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT2A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT2B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT3A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT3B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERADC0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTA bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTB bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTC bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTD bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTE bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTF bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART1 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART2 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART3 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCA0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB1 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB2 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB3 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_bm 0x08 /* Reset Pin Configuration bit mask. */ +#define FUSE_RSTPINCFG_bp 3 /* Reset Pin Configuration bit position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PORTCTRL bit masks and bit positions */ +#define PORT_SRL_bm 0x01 /* Slew Rate Limit Enable bit mask. */ +#define PORT_SRL_bp 0 /* Slew Rate Limit Enable bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.EVSYSROUTEA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_EVOUT3_bm 0x08 /* Event Output 3 bit mask. */ +#define PORTMUX_EVOUT3_bp 3 /* Event Output 3 bit position. */ +#define PORTMUX_EVOUT4_bm 0x10 /* Event Output 4 bit mask. */ +#define PORTMUX_EVOUT4_bp 4 /* Event Output 4 bit position. */ +#define PORTMUX_EVOUT5_bm 0x20 /* Event Output 5 bit mask. */ +#define PORTMUX_EVOUT5_bp 5 /* Event Output 5 bit position. */ + +/* PORTMUX.CCLROUTEA bit masks and bit positions */ +#define PORTMUX_LUT0_bm 0x01 /* CCL LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 0 /* CCL LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x02 /* CCL LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 1 /* CCL LUT1 bit position. */ +#define PORTMUX_LUT2_bm 0x04 /* CCL LUT2 bit mask. */ +#define PORTMUX_LUT2_bp 2 /* CCL LUT2 bit position. */ +#define PORTMUX_LUT3_bm 0x08 /* CCL LUT3 bit mask. */ +#define PORTMUX_LUT3_bp 3 /* CCL LUT3 bit position. */ + +/* PORTMUX.USARTROUTEA bit masks and bit positions */ +#define PORTMUX_USART0_gm 0x03 /* Port Multiplexer USART0 group mask. */ +#define PORTMUX_USART0_gp 0 /* Port Multiplexer USART0 group position. */ +#define PORTMUX_USART00_bm (1<<0) /* Port Multiplexer USART0 bit 0 mask. */ +#define PORTMUX_USART00_bp 0 /* Port Multiplexer USART0 bit 0 position. */ +#define PORTMUX_USART01_bm (1<<1) /* Port Multiplexer USART0 bit 1 mask. */ +#define PORTMUX_USART01_bp 1 /* Port Multiplexer USART0 bit 1 position. */ +#define PORTMUX_USART1_gm 0x0C /* Port Multiplexer USART1 group mask. */ +#define PORTMUX_USART1_gp 2 /* Port Multiplexer USART1 group position. */ +#define PORTMUX_USART10_bm (1<<2) /* Port Multiplexer USART1 bit 0 mask. */ +#define PORTMUX_USART10_bp 2 /* Port Multiplexer USART1 bit 0 position. */ +#define PORTMUX_USART11_bm (1<<3) /* Port Multiplexer USART1 bit 1 mask. */ +#define PORTMUX_USART11_bp 3 /* Port Multiplexer USART1 bit 1 position. */ +#define PORTMUX_USART2_gm 0x30 /* Port Multiplexer USART2 group mask. */ +#define PORTMUX_USART2_gp 4 /* Port Multiplexer USART2 group position. */ +#define PORTMUX_USART20_bm (1<<4) /* Port Multiplexer USART2 bit 0 mask. */ +#define PORTMUX_USART20_bp 4 /* Port Multiplexer USART2 bit 0 position. */ +#define PORTMUX_USART21_bm (1<<5) /* Port Multiplexer USART2 bit 1 mask. */ +#define PORTMUX_USART21_bp 5 /* Port Multiplexer USART2 bit 1 position. */ +#define PORTMUX_USART3_gm 0xC0 /* Port Multiplexer USART3 group mask. */ +#define PORTMUX_USART3_gp 6 /* Port Multiplexer USART3 group position. */ +#define PORTMUX_USART30_bm (1<<6) /* Port Multiplexer USART3 bit 0 mask. */ +#define PORTMUX_USART30_bp 6 /* Port Multiplexer USART3 bit 0 position. */ +#define PORTMUX_USART31_bm (1<<7) /* Port Multiplexer USART3 bit 1 mask. */ +#define PORTMUX_USART31_bp 7 /* Port Multiplexer USART3 bit 1 position. */ + +/* PORTMUX.TWISPIROUTEA bit masks and bit positions */ +#define PORTMUX_SPI0_gm 0x03 /* Port Multiplexer SPI0 group mask. */ +#define PORTMUX_SPI0_gp 0 /* Port Multiplexer SPI0 group position. */ +#define PORTMUX_SPI00_bm (1<<0) /* Port Multiplexer SPI0 bit 0 mask. */ +#define PORTMUX_SPI00_bp 0 /* Port Multiplexer SPI0 bit 0 position. */ +#define PORTMUX_SPI01_bm (1<<1) /* Port Multiplexer SPI0 bit 1 mask. */ +#define PORTMUX_SPI01_bp 1 /* Port Multiplexer SPI0 bit 1 position. */ +#define PORTMUX_TWI0_gm 0x30 /* Port Multiplexer TWI0 group mask. */ +#define PORTMUX_TWI0_gp 4 /* Port Multiplexer TWI0 group position. */ +#define PORTMUX_TWI00_bm (1<<4) /* Port Multiplexer TWI0 bit 0 mask. */ +#define PORTMUX_TWI00_bp 4 /* Port Multiplexer TWI0 bit 0 position. */ +#define PORTMUX_TWI01_bm (1<<5) /* Port Multiplexer TWI0 bit 1 mask. */ +#define PORTMUX_TWI01_bp 5 /* Port Multiplexer TWI0 bit 1 position. */ + +/* PORTMUX.TCAROUTEA bit masks and bit positions */ +#define PORTMUX_TCA0_gm 0x07 /* Port Multiplexer TCA0 group mask. */ +#define PORTMUX_TCA0_gp 0 /* Port Multiplexer TCA0 group position. */ +#define PORTMUX_TCA00_bm (1<<0) /* Port Multiplexer TCA0 bit 0 mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 bit 0 position. */ +#define PORTMUX_TCA01_bm (1<<1) /* Port Multiplexer TCA0 bit 1 mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 bit 1 position. */ +#define PORTMUX_TCA02_bm (1<<2) /* Port Multiplexer TCA0 bit 2 mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 bit 2 position. */ + +/* PORTMUX.TCBROUTEA bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ +#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ +#define PORTMUX_TCB2_bm 0x04 /* Port Multiplexer TCB2 bit mask. */ +#define PORTMUX_TCB2_bp 2 /* Port Multiplexer TCB2 bit position. */ +#define PORTMUX_TCB3_bm 0x08 /* Port Multiplexer TCB3 bit mask. */ +#define PORTMUX_TCB3_bp 3 /* Port Multiplexer TCB3 bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_CORREN_bm 0x04 /* Correction enable bit mask. */ +#define RTC_CORREN_bp 2 /* Correction enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_ERROR_gm 0x7F /* Error Correction Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Correction Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Correction Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Correction Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Correction Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Correction Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Correction Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Correction Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Correction Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Correction Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Correction Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Correction Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Correction Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Correction Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Correction Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Correction Value bit 6 position. */ +#define RTC_SIGN_bm 0x80 /* Error Correction Sign Bit bit mask. */ +#define RTC_SIGN_bp 7 /* Error Correction Sign Bit bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + + +/* SYSCFG.OCDMS bit masks and bit positions */ +#define SYSCFG_OCDMR_bm 0x01 /* OCD Message Read bit mask. */ +#define SYSCFG_OCDMR_bp 0 /* OCD Message Read bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DUALCTRL bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Dual Control Enable bit mask. */ +#define TWI_ENABLE_bp 0 /* Dual Control Enable bit position. */ +/* TWI_FMPEN is already defined. */ +/* TWI_SDAHOLD is already defined. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.CTRLD bit masks and bit positions */ +#define USART_ABW_gm 0xC0 /* Auto Baud Window group mask. */ +#define USART_ABW_gp 6 /* Auto Baud Window group position. */ +#define USART_ABW0_bm (1<<6) /* Auto Baud Window bit 0 mask. */ +#define USART_ABW0_bp 6 /* Auto Baud Window bit 0 position. */ +#define USART_ABW1_bm (1<<7) /* Auto Baud Window bit 1 mask. */ +#define USART_ABW1_bp 7 /* Auto Baud Window bit 1 position. */ + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_AC0REFSEL_gm 0x07 /* AC0 reference select group mask. */ +#define VREF_AC0REFSEL_gp 0 /* AC0 reference select group position. */ +#define VREF_AC0REFSEL0_bm (1<<0) /* AC0 reference select bit 0 mask. */ +#define VREF_AC0REFSEL0_bp 0 /* AC0 reference select bit 0 position. */ +#define VREF_AC0REFSEL1_bm (1<<1) /* AC0 reference select bit 1 mask. */ +#define VREF_AC0REFSEL1_bp 1 /* AC0 reference select bit 1 position. */ +#define VREF_AC0REFSEL2_bm (1<<2) /* AC0 reference select bit 2 mask. */ +#define VREF_AC0REFSEL2_bp 2 /* AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_AC0REFEN_bm 0x01 /* AC0 DACREF reference enable bit mask. */ +#define VREF_AC0REFEN_bp 0 /* AC0 DACREF reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 3 +#define RTC_CNT_vect _VECTOR(3) /* */ +#define RTC_PIT_vect_num 4 +#define RTC_PIT_vect _VECTOR(4) /* */ + +/* CCL interrupt vectors */ +#define CCL_CCL_vect_num 5 +#define CCL_CCL_vect _VECTOR(5) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 6 +#define PORTA_PORT_vect _VECTOR(6) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 7 +#define TCA0_LUNF_vect _VECTOR(7) /* */ +#define TCA0_OVF_vect_num 7 +#define TCA0_OVF_vect _VECTOR(7) /* */ +#define TCA0_HUNF_vect_num 8 +#define TCA0_HUNF_vect _VECTOR(8) /* */ +#define TCA0_CMP0_vect_num 9 +#define TCA0_CMP0_vect _VECTOR(9) /* */ +#define TCA0_LCMP0_vect_num 9 +#define TCA0_LCMP0_vect _VECTOR(9) /* */ +#define TCA0_CMP1_vect_num 10 +#define TCA0_CMP1_vect _VECTOR(10) /* */ +#define TCA0_LCMP1_vect_num 10 +#define TCA0_LCMP1_vect _VECTOR(10) /* */ +#define TCA0_CMP2_vect_num 11 +#define TCA0_CMP2_vect _VECTOR(11) /* */ +#define TCA0_LCMP2_vect_num 11 +#define TCA0_LCMP2_vect _VECTOR(11) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 12 +#define TCB0_INT_vect _VECTOR(12) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 13 +#define TCB1_INT_vect _VECTOR(13) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 14 +#define TWI0_TWIS_vect _VECTOR(14) /* */ +#define TWI0_TWIM_vect_num 15 +#define TWI0_TWIM_vect _VECTOR(15) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 16 +#define SPI0_INT_vect _VECTOR(16) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 17 +#define USART0_RXC_vect _VECTOR(17) /* */ +#define USART0_DRE_vect_num 18 +#define USART0_DRE_vect _VECTOR(18) /* */ +#define USART0_TXC_vect_num 19 +#define USART0_TXC_vect _VECTOR(19) /* */ + +/* PORTD interrupt vectors */ +#define PORTD_PORT_vect_num 20 +#define PORTD_PORT_vect _VECTOR(20) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 21 +#define AC0_AC_vect _VECTOR(21) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 22 +#define ADC0_RESRDY_vect _VECTOR(22) /* */ +#define ADC0_WCOMP_vect_num 23 +#define ADC0_WCOMP_vect _VECTOR(23) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 24 +#define PORTC_PORT_vect _VECTOR(24) /* */ + +/* TCB2 interrupt vectors */ +#define TCB2_INT_vect_num 25 +#define TCB2_INT_vect _VECTOR(25) /* */ + +/* USART1 interrupt vectors */ +#define USART1_RXC_vect_num 26 +#define USART1_RXC_vect _VECTOR(26) /* */ +#define USART1_DRE_vect_num 27 +#define USART1_DRE_vect _VECTOR(27) /* */ +#define USART1_TXC_vect_num 28 +#define USART1_TXC_vect _VECTOR(28) /* */ + +/* PORTF interrupt vectors */ +#define PORTF_PORT_vect_num 29 +#define PORTF_PORT_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +/* USART2 interrupt vectors */ +#define USART2_RXC_vect_num 31 +#define USART2_RXC_vect _VECTOR(31) /* */ +#define USART2_DRE_vect_num 32 +#define USART2_DRE_vect _VECTOR(32) /* */ +#define USART2_TXC_vect_num 33 +#define USART2_TXC_vect _VECTOR(33) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 34 +#define PORTB_PORT_vect _VECTOR(34) /* */ + +/* PORTE interrupt vectors */ +#define PORTE_PORT_vect_num 35 +#define PORTE_PORT_vect _VECTOR(35) /* */ + +/* TCB3 interrupt vectors */ +#define TCB3_INT_vect_num 36 +#define TCB3_INT_vect _VECTOR(36) /* */ + +/* USART3 interrupt vectors */ +#define USART3_RXC_vect_num 37 +#define USART3_RXC_vect _VECTOR(37) /* */ +#define USART3_DRE_vect_num 38 +#define USART3_DRE_vect _VECTOR(38) /* */ +#define USART3_TXC_vect_num 39 +#define USART3_TXC_vect _VECTOR(39) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (40 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (65536) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (65536U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (64) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (64U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (64) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (64U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3000) +# define INTERNAL_SRAM_SIZE (4096) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3000U) +# define INTERNAL_SRAM_SIZE (4096U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (64) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (64U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x4000) +# define MAPPED_PROGMEM_SIZE (32768) +# define MAPPED_PROGMEM_PAGE_SIZE (128) +#else +# define MAPPED_PROGMEM_START (0x4000U) +# define MAPPED_PROGMEM_SIZE (32768U) +# define MAPPED_PROGMEM_PAGE_SIZE (128U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (125) +# define PROD_SIGNATURES_PAGE_SIZE (128) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (125U) +# define PROD_SIGNATURES_PAGE_SIZE (128U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (128) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (128U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (64) +# define USER_SIGNATURES_PAGE_SIZE (64) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (64U) +# define USER_SIGNATURES_PAGE_SIZE (64U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (32768) +# define PROGMEM_PAGE_SIZE (128) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (32768U) +# define PROGMEM_PAGE_SIZE (128U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG (unsigned char)_BV(3) /* Reset Pin Configuration */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x31 + + +#endif /* #ifdef _AVR_ATMEGA3209_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iom323.h b/hardware/tools/avr/avr/include/avr/iom323.h new file mode 100644 index 0000000000000000000000000000000000000000..44ca22701dcc2a8303b7326530a9baa6ee48ae7e --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom323.h @@ -0,0 +1,744 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom323.h 2234 2011-03-16 04:32:21Z arcanum $ */ + +/* avr/iom323.h - definitions for ATmega323 */ + +#ifndef _AVR_IOM323_H_ +#define _AVR_IOM323_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom323.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ +#define TWBR _SFR_IO8(0x00) +#define TWSR _SFR_IO8(0x01) +#define TWAR _SFR_IO8(0x02) +#define TWDR _SFR_IO8(0x03) + +/* ADC */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) +#define ADCSR _SFR_IO8(0x06) +#define ADMUX _SFR_IO8(0x07) + +/* analog comparator */ +#define ACSR _SFR_IO8(0x08) + +/* UART */ +#define UBRR _SFR_IO8(0x09) +#define UBRRL UBRR +#define UCSRB _SFR_IO8(0x0A) +#define UCSRA _SFR_IO8(0x0B) +#define UDR _SFR_IO8(0x0C) + +/* SPI */ +#define SPCR _SFR_IO8(0x0D) +#define SPSR _SFR_IO8(0x0E) +#define SPDR _SFR_IO8(0x0F) + +/* Port D */ +#define PIND _SFR_IO8(0x10) +#define DDRD _SFR_IO8(0x11) +#define PORTD _SFR_IO8(0x12) + +/* Port C */ +#define PINC _SFR_IO8(0x13) +#define DDRC _SFR_IO8(0x14) +#define PORTC _SFR_IO8(0x15) + +/* Port B */ +#define PINB _SFR_IO8(0x16) +#define DDRB _SFR_IO8(0x17) +#define PORTB _SFR_IO8(0x18) + +/* Port A */ +#define PINA _SFR_IO8(0x19) +#define DDRA _SFR_IO8(0x1A) +#define PORTA _SFR_IO8(0x1B) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO16(0x1E) +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +#define UBRRH _SFR_IO8(0x20) +#define UCSRC UBRRH + +#define WDTCR _SFR_IO8(0x21) + +#define ASSR _SFR_IO8(0x22) + +/* Timer 2 */ +#define OCR2 _SFR_IO8(0x23) +#define TCNT2 _SFR_IO8(0x24) +#define TCCR2 _SFR_IO8(0x25) + +/* Timer 1 */ +#define ICR1 _SFR_IO16(0x26) +#define ICR1L _SFR_IO8(0x26) +#define ICR1H _SFR_IO8(0x27) +#define OCR1B _SFR_IO16(0x28) +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) +#define TCCR1B _SFR_IO8(0x2E) +#define TCCR1A _SFR_IO8(0x2F) + +#define SFIOR _SFR_IO8(0x30) + +#define OSCCAL _SFR_IO8(0x31) + +/* Timer 0 */ +#define TCNT0 _SFR_IO8(0x32) +#define TCCR0 _SFR_IO8(0x33) + +#define MCUSR _SFR_IO8(0x34) +#define MCUCSR MCUSR +#define MCUCR _SFR_IO8(0x35) + +#define TWCR _SFR_IO8(0x36) + +#define SPMCR _SFR_IO8(0x37) + +#define TIFR _SFR_IO8(0x38) +#define TIMSK _SFR_IO8(0x39) + +#define GIFR _SFR_IO8(0x3A) +#define GIMSK _SFR_IO8(0x3B) +#define GICR GIMSK + +#define OCR0 _SFR_IO8(0x3C) + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt Request 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt Request 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* External Interrupt Request 2 */ +#define INT2_vect_num 3 +#define INT2_vect _VECTOR(3) +#define SIG_INTERRUPT2 _VECTOR(3) + +/* Timer/Counter2 Compare Match */ +#define TIMER2_COMP_vect_num 4 +#define TIMER2_COMP_vect _VECTOR(4) +#define SIG_OUTPUT_COMPARE2 _VECTOR(4) + +/* Timer/Counter2 Overflow */ +#define TIMER2_OVF_vect_num 5 +#define TIMER2_OVF_vect _VECTOR(5) +#define SIG_OVERFLOW2 _VECTOR(5) + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect_num 6 +#define TIMER1_CAPT_vect _VECTOR(6) +#define SIG_INPUT_CAPTURE1 _VECTOR(6) + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect_num 7 +#define TIMER1_COMPA_vect _VECTOR(7) +#define SIG_OUTPUT_COMPARE1A _VECTOR(7) + +/* Timer/Counter1 Compare Match B */ +#define TIMER1_COMPB_vect_num 8 +#define TIMER1_COMPB_vect _VECTOR(8) +#define SIG_OUTPUT_COMPARE1B _VECTOR(8) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 9 +#define TIMER1_OVF_vect _VECTOR(9) +#define SIG_OVERFLOW1 _VECTOR(9) + +/* Timer/Counter0 Compare Match */ +#define TIMER0_COMP_vect_num 10 +#define TIMER0_COMP_vect _VECTOR(10) +#define SIG_OUTPUT_COMPARE0 _VECTOR(10) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 11 +#define TIMER0_OVF_vect _VECTOR(11) +#define SIG_OVERFLOW0 _VECTOR(11) + +/* Serial Transfer Complete */ +#define SPI_STC_vect_num 12 +#define SPI_STC_vect _VECTOR(12) +#define SIG_SPI _VECTOR(12) + +/* USART, Rx Complete */ +#define USART_RXC_vect_num 13 +#define USART_RXC_vect _VECTOR(13) +#define SIG_UART_RECV _VECTOR(13) + +/* USART Data Register Empty */ +#define USART_UDRE_vect_num 14 +#define USART_UDRE_vect _VECTOR(14) +#define SIG_UART_DATA _VECTOR(14) + +/* USART, Tx Complete */ +#define USART_TXC_vect_num 15 +#define USART_TXC_vect _VECTOR(15) +#define SIG_UART_TRANS _VECTOR(15) + +/* ADC Conversion Complete */ +#define ADC_vect_num 16 +#define ADC_vect _VECTOR(16) +#define SIG_ADC _VECTOR(16) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 17 +#define EE_RDY_vect _VECTOR(17) +#define SIG_EEPROM_READY _VECTOR(17) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 18 +#define ANA_COMP_vect _VECTOR(18) +#define SIG_COMPARATOR _VECTOR(18) + +/* 2-wire Serial Interface */ +#define TWI_vect_num 19 +#define TWI_vect _VECTOR(19) +#define SIG_2WIRE_SERIAL _VECTOR(19) + +/* Store Program Memory Ready */ +#define SPM_RDY_vect_num 20 +#define SPM_RDY_vect _VECTOR(20) + +#define _VECTORS_SIZE 80 + + +/* Bit numbers */ + +/* GIMSK */ +#define INT1 7 +#define INT0 6 +#define INT2 5 +#define IVSEL 1 +#define IVCE 0 + +/* GIFR */ +#define INTF1 7 +#define INTF0 6 +#define INTF2 5 + +/* TIMSK */ +#define OCIE2 7 +#define TOIE2 6 +#define TICIE1 5 +#define OCIE1A 4 +#define OCIE1B 3 +#define TOIE1 2 +#define OCIE0 1 +#define TOIE0 0 + +/* TIFR */ +#define OCF2 7 +#define TOV2 6 +#define ICF1 5 +#define OCF1A 4 +#define OCF1B 3 +#define TOV1 2 +#define OCF0 1 +#define TOV0 0 + +/* SPMCR */ +#define SPMIE 7 +#define ASB 6 +/* bit 5 reserved */ +#define ASRE 4 +#define BLBSET 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 + +/* TWCR */ +#define TWINT 7 +#define TWEA 6 +#define TWSTA 5 +#define TWSTO 4 +#define TWWC 3 +#define TWEN 2 +#define TWI_TST 1 +#define TWIE 0 + +/* TWAR */ +#define TWGCE 0 + +/* TWSR */ +#define TWS7 7 +#define TWS6 6 +#define TWS5 5 +#define TWS4 4 +#define TWS3 3 +/* bits 2-0 reserved */ + +/* MCUCR */ +/* bit 7 reserved (SM2?) */ +#define SE 7 +#define SM2 6 +#define SM1 5 +#define SM0 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/* MCUCSR */ +#define JTD 7 +#define ISC2 6 +#define EIH 5 +#define JTRF 4 +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +/* SFIOR */ +#define RPDD 7 +#define RPDC 6 +#define RPDB 5 +#define RPDA 4 +#define ACME 3 +#define PUD 2 +#define PSR2 1 +#define PSR10 0 + +/* TCCR0 */ +#define FOC0 7 +#define PWM0 6 +#define COM01 5 +#define COM00 4 +#define CTC0 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* TCCR2 */ +#define FOC2 7 +#define PWM2 6 +#define COM21 5 +#define COM20 4 +#define CTC2 3 +#define CS22 2 +#define CS21 1 +#define CS20 0 + +/* ASSR */ +/* bits 7-4 reserved */ +#define AS2 3 +#define TCN2UB 2 +#define OCR2UB 1 +#define TCR2UB 0 + +/* TCCR1A */ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define FOC1A 3 +#define FOC1B 2 +#define PWM11 1 +#define PWM10 0 + +/* TCCR1B */ +#define ICNC1 7 +#define ICES1 6 +/* bit 5 reserved */ +#define CTC11 4 +#define CTC10 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* WDTCR */ +/* bits 7-5 reserved */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* PA7-PA0 = ADC7-ADC0 */ +/* PORTA */ +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* DDRA */ +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +/* PINA */ +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +/* + PB7 = SCK + PB6 = MISO + PB5 = MOSI + PB4 = SS# + PB3 = AIN1 + PB2 = AIN0 + PB1 = T1 + PB0 = T0 + */ + +/* PORTB */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* DDRB */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* PINB */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* + PC7 = TOSC2 + PC6 = TOSC1 + PC1 = SDA + PC0 = SCL + */ +/* PORTC */ +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* DDRC */ +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +/* PINC */ +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +/* + PD7 = OC2 + PD6 = ICP + PD5 = OC1A + PD4 = OC1B + PD3 = INT1 + PD2 = INT0 + PD1 = TXD + PD0 = RXD + */ + +/* PORTD */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* DDRD */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* PIND */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* + PE2 = ALE + PE1 = OC1B + PE0 = ICP / INT2 + */ + +/* SPSR */ +#define SPIF 7 +#define WCOL 6 +#define SPI2X 0 + +/* SPCR */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* UCSRA */ +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 +#define PE 2 +#define U2X 1 +#define MPCM 0 + +/* UCSRB */ +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define UCSZ2 2 +#define CHR9 2 +#define RXB8 1 +#define TXB8 0 + +/* UCSRC */ +#define URSEL 7 +#define UMSEL 6 +#define UPM1 5 +#define UPM0 4 +#define USBS 3 +#define UCSZ1 2 +#define UCSZ0 1 +#define UCPOL 0 + +/* ACSR */ +#define ACD 7 +#define AINBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +/* ADCSR */ +#define ADEN 7 +#define ADSC 6 +#define ADFR 5 +#define ADIF 4 +#define ADIE 3 +#define ADPS2 2 +#define ADPS1 1 +#define ADPS0 0 + +/* ADMUX */ +#define REFS1 7 +#define REFS0 6 +#define ADLAR 5 +#define MUX4 4 +#define MUX3 3 +#define MUX2 2 +#define MUX1 1 +#define MUX0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define SPM_PAGESIZE 128 +#define RAMSTART 0x60 +#define RAMEND 0x85F +#define XRAMEND RAMEND +#define E2END 0x3FF +#define E2PAGESIZE 0 +#define FLASHEND 0x7FFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 2 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_BODEN (unsigned char)~_BV(6) +#define FUSE_BODLEVEL (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_JTAGEN) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x01 + + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_INTERRUPT1 +#pragma GCC poison SIG_INTERRUPT2 +#pragma GCC poison SIG_OUTPUT_COMPARE2 +#pragma GCC poison SIG_OVERFLOW2 +#pragma GCC poison SIG_INPUT_CAPTURE1 +#pragma GCC poison SIG_OUTPUT_COMPARE1A +#pragma GCC poison SIG_OUTPUT_COMPARE1B +#pragma GCC poison SIG_OVERFLOW1 +#pragma GCC poison SIG_OUTPUT_COMPARE0 +#pragma GCC poison SIG_OVERFLOW0 +#pragma GCC poison SIG_SPI +#pragma GCC poison SIG_UART_RECV +#pragma GCC poison SIG_UART_DATA +#pragma GCC poison SIG_UART_TRANS +#pragma GCC poison SIG_ADC +#pragma GCC poison SIG_EEPROM_READY +#pragma GCC poison SIG_COMPARATOR +#pragma GCC poison SIG_2WIRE_SERIAL + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + + +#define SLEEP_MODE_IDLE (0x00<<4) +#define SLEEP_MODE_ADC (0x01<<4) +#define SLEEP_MODE_PWR_DOWN (0x02<<4) +#define SLEEP_MODE_PWR_SAVE (0x03<<4) +#define SLEEP_MODE_STANDBY (0x06<<4) +#define SLEEP_MODE_EXT_STANDBY (0x07<<4) + +#endif /* _AVR_IOM323_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom324a.h b/hardware/tools/avr/avr/include/avr/iom324a.h new file mode 100644 index 0000000000000000000000000000000000000000..3ae54fb299416fe3152f38f7b2bc8a329cd1fb26 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom324a.h @@ -0,0 +1,1014 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_ATMEGA324A_H_INCLUDED +#define _AVR_ATMEGA324A_H_INCLUDED + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom324a.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR0 _SFR_IO8(0x2C) +#define SPR00 0 +#define SPR10 1 +#define CPHA0 2 +#define CPOL0 3 +#define MSTR0 4 +#define DORD0 5 +#define SPE0 6 +#define SPIE0 7 + +#define SPSR0 _SFR_IO8(0x2D) +#define SPI2X0 0 +#define WCOL0 6 +#define SPIF0 7 + +#define SPDR0 _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR0 _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRUSART1 4 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom324p.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR0 _SFR_IO8(0x2C) +#define SPR00 0 +#define SPR10 1 +#define CPHA0 2 +#define CPOL0 3 +#define MSTR0 4 +#define DORD0 5 +#define SPE0 6 +#define SPIE0 7 + +#define SPSR0 _SFR_IO8(0x2D) +#define SPI2X0 0 +#define WCOL0 6 +#define SPIF0 7 + +#define SPDR0 _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR0 _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRUSART1 4 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom324pa.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega324PA_H_ +#define _AVR_ATmega324PA_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINA _SFR_IO8(0x00) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 +#define PINA4 4 +#define PINA5 5 +#define PINA6 6 +#define PINA7 7 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 +#define PORTA4 4 +#define PORTA5 5 +#define PORTA6 6 +#define PORTA7 7 + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 +#define EEAR10 2 +#define EEAR11 3 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR0 _SFR_IO8(0x2C) +#define SPR00 0 +#define SPR10 1 +#define CPHA0 2 +#define CPOL0 3 +#define MSTR0 4 +#define DORD0 5 +#define SPE0 6 +#define SPIE0 7 + +#define SPSR0 _SFR_IO8(0x2D) +#define SPI2X0 0 +#define WCOL0 6 +#define SPIF0 7 + +#define SPDR0 _SFR_IO8(0x2E) +#define SPDRB0 0 +#define SPDRB1 1 +#define SPDRB2 2 +#define SPDRB3 3 +#define SPDRB4 4 +#define SPDRB5 5 +#define SPDRB6 6 +#define SPDRB7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 +#define JTD 7 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR0 _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRUSART1 4 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom324pb.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +/* Reserved [0x0F..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define ICF3 5 + +#define TIFR4 _SFR_IO8(0x19) +#define TOV4 0 +#define OCF4A 1 +#define OCF4B 2 +#define ICF4 5 + +/* Reserved [0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 +#define PCIF4 4 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR0 _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR0 _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR0 _SFR_IO8(0x2E) + +#define ACSRB _SFR_IO8(0x2F) +#define ACOE 0 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define XFDCSR _SFR_MEM8(0x62) +#define XFDIE 0 +#define XFDIF 1 + +#define PRR2 _SFR_MEM8(0x63) +#define PRTWI1 0 +#define PRSPI1 1 +#define PRUSART2 2 +#define PRPTC 3 + +#define __AVR_HAVE_PRR2 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom325.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDE7 7 +#define DDE6 6 +#define DDE5 5 +#define DDE4 4 +#define DDE3 3 +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PE7 7 +#define PE6 6 +#define PE5 5 +#define PE4 4 +#define PE3 3 +#define PE2 2 +#define PE1 1 +#define PE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDF7 7 +#define DDF6 6 +#define DDF5 5 +#define DDF4 4 +#define DDF3 3 +#define DDF2 2 +#define DDF1 1 +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PF7 7 +#define PF6 6 +#define PF5 5 +#define PF4 4 +#define PF3 3 +#define PF2 2 +#define PF1 1 +#define PF0 0 + +#define PING _SFR_IO8(0x12) +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDG4 4 +#define DDG3 3 +#define DDG2 2 +#define DDG1 1 +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PG4 4 +#define PG3 3 +#define PG2 2 +#define PG1 1 +#define PG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 + +/* Reserved [0x18..0x1B] */ + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define PCIF0 4 +#define PCIF1 5 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define PCIE0 4 +#define PCIE1 5 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0X20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0X22) + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + + +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 +#define PSR2 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM0A0 4 +#define COM0A1 5 +#define WGM00 6 +#define FOC0A 7 + +/* Reserved [0x25] */ + +#define TCNT0 _SFR_IO8(0X26) + +#define OCR0A _SFR_IO8(0X27) + +/* Reserved [0x28..0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0X2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 +#define IDRD 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +#define MCUCR _SFR_IO8(0X35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#if defined(__AVR_ATmega325P__) +#define BODSE 5 +#define BODS 6 +#endif +#define JTD 7 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom3250.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDE7 7 +#define DDE6 6 +#define DDE5 5 +#define DDE4 4 +#define DDE3 3 +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PE7 7 +#define PE6 6 +#define PE5 5 +#define PE4 4 +#define PE3 3 +#define PE2 2 +#define PE1 1 +#define PE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDF7 7 +#define DDF6 6 +#define DDF5 5 +#define DDF4 4 +#define DDF3 3 +#define DDF2 2 +#define DDF1 1 +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PF7 7 +#define PF6 6 +#define PF5 5 +#define PF4 4 +#define PF3 3 +#define PF2 2 +#define PF1 1 +#define PF0 0 + +#define PING _SFR_IO8(0x12) +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDG4 4 +#define DDG3 3 +#define DDG2 2 +#define DDG1 1 +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PG4 4 +#define PG3 3 +#define PG2 2 +#define PG1 1 +#define PG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 + +/* Reserved [0x18..0x1B] */ + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define PCIF0 4 +#define PCIF1 5 +#define PCIF2 6 +#define PCIF3 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define PCIE0 4 +#define PCIE1 5 +#define PCIE2 6 +#define PCIE3 7 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0X20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0X22) + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 +#define PSR2 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM0A0 4 +#define COM0A1 5 +#define WGM00 6 +#define FOC0A 7 + +/* Reserved [0x25] */ + +#define TCNT0 _SFR_IO8(0X26) + +#define OCR0A _SFR_IO8(0X27) + +/* Reserved [0x28..0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0X2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 +#define IDRD 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +#define MCUCR _SFR_IO8(0X35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#if defined(__AVR_ATmega3250P__) +#define BODSE 5 +#define BODS 6 +#endif +#define JTD 7 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom3250pa.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_IO8(0x12) +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 + +/* Reserved [0x18..0x1B] */ + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define PCIF0 4 +#define PCIF1 5 +#define PCIF2 6 +#define PCIF3 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define PCIE0 4 +#define PCIE1 5 +#define PCIE2 6 +#define PCIE3 7 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSR310 0 +#define TSM 7 +#define PSR2 1 + +#define TCCR0A _SFR_IO8(0x24) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM0A0 4 +#define COM0A1 5 +#define WGM00 6 +#define FOC0A 7 + +/* Reserved [0x25] */ + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +/* Reserved [0x28..0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRLCD 4 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom325pa.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_IO8(0x12) +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 + +/* Reserved [0x18..0x1B] */ + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define PCIF0 4 +#define PCIF1 5 +#define PCIF2 6 +#define PCIF3 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define PCIE0 4 +#define PCIE1 5 +#define PCIE2 6 +#define PCIE3 7 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSR310 0 +#define TSM 7 +#define PSR2 1 + +#define TCCR0A _SFR_IO8(0x24) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM0A0 4 +#define COM0A1 5 +#define WGM00 6 +#define FOC0A 7 + +/* Reserved [0x25] */ + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +/* Reserved [0x28..0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRLCD 4 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom328p.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_IOM328P_H_ +#define _AVR_IOM328P_H_ 1 + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 + +#define _EEPROM_REG_LOCATIONS_ 1F2021 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 /* only for backwards compatibility with previous + * avr-libc versions; not an official name */ +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom328pb.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +/* Reserved [0x0F..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define ICF3 5 + +#define TIFR4 _SFR_IO8(0x19) +#define TOV4 0 +#define OCF4A 1 +#define OCF4B 2 +#define ICF4 5 + +/* Reserved [0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR0 _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR0 _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR0 _SFR_IO8(0x2E) + +#define ACSRB _SFR_IO8(0x2F) +#define ACOE 0 + +#define ACSRA _SFR_IO8(0x30) + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define XFDCSR _SFR_MEM8(0x62) +#define XFDIE 0 +#define XFDIF 1 + +/* Reserved [0x63] */ + +#define PRR0 _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI0 2 +#define PRTIM1 3 +#define PRUSART1 4 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI0 7 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom329.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDE7 7 +#define DDE6 6 +#define DDE5 5 +#define DDE4 4 +#define DDE3 3 +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PE7 7 +#define PE6 6 +#define PE5 5 +#define PE4 4 +#define PE3 3 +#define PE2 2 +#define PE1 1 +#define PE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDF7 7 +#define DDF6 6 +#define DDF5 5 +#define DDF4 4 +#define DDF3 3 +#define DDF2 2 +#define DDF1 1 +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PF7 7 +#define PF6 6 +#define PF5 5 +#define PF4 4 +#define PF3 3 +#define PF2 2 +#define PF1 1 +#define PF0 0 + +#define PING _SFR_IO8(0x12) +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDG4 4 +#define DDG3 3 +#define DDG2 2 +#define DDG1 1 +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PG4 4 +#define PG3 3 +#define PG2 2 +#define PG1 1 +#define PG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 + +/* Reserved [0x18..0x1B] */ + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define PCIF0 4 +#define PCIF1 5 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define PCIE0 4 +#define PCIE1 5 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +#define EEDR _SFR_IO8(0X20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0X22) + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 +#define PSR2 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM0A0 4 +#define COM0A1 5 +#define WGM00 6 +#define FOC0A 7 + +/* Reserved [0x25] */ + +#define TCNT0 _SFR_IO8(0X26) + +#define OCR0A _SFR_IO8(0X27) + +/* Reserved [0x28..0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0X2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 +#define IDRD 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +#define MCUCR _SFR_IO8(0X35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#if defined(__AVR_ATmega329P__) +#define BODSE 5 +#define BODS 6 +#endif +#define JTD 7 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRLCD 4 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom3290.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDE7 7 +#define DDE6 6 +#define DDE5 5 +#define DDE4 4 +#define DDE3 3 +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PE7 7 +#define PE6 6 +#define PE5 5 +#define PE4 4 +#define PE3 3 +#define PE2 2 +#define PE1 1 +#define PE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDF7 7 +#define DDF6 6 +#define DDF5 5 +#define DDF4 4 +#define DDF3 3 +#define DDF2 2 +#define DDF1 1 +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PF7 7 +#define PF6 6 +#define PF5 5 +#define PF4 4 +#define PF3 3 +#define PF2 2 +#define PF1 1 +#define PF0 0 + +#define PING _SFR_IO8(0x12) +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDG4 4 +#define DDG3 3 +#define DDG2 2 +#define DDG1 1 +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PG4 4 +#define PG3 3 +#define PG2 2 +#define PG1 1 +#define PG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 + +/* Reserved [0x18..0x1B] */ + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define PCIF0 4 +#define PCIF1 5 +#define PCIF2 6 +#define PCIF3 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define PCIE0 4 +#define PCIE1 5 +#define PCIE2 6 +#define PCIE3 7 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +#define EEDR _SFR_IO8(0X20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0X22) + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 +#define PSR2 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM0A0 4 +#define COM0A1 5 +#define WGM00 6 +#define FOC0A 7 + +/* Reserved [0x25] */ + +#define TCNT0 _SFR_IO8(0X26) + +#define OCR0A _SFR_IO8(0X27) + +/* Reserved [0x28..0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0X2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 +#define IDRD 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +#define MCUCR _SFR_IO8(0X35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#if defined(__AVR_ATmega3290P__) +#define BODSE 5 +#define BODS 6 +#endif +#define JTD 7 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRLCD 4 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom3290pa.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_IO8(0x12) +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 + +/* Reserved [0x18..0x1B] */ + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define PCIF0 4 +#define PCIF1 5 +#define PCIF2 6 +#define PCIF3 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define PCIE0 4 +#define PCIE1 5 +#define PCIE2 6 +#define PCIE3 7 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSR310 0 +#define TSM 7 +#define PSR2 1 + +#define TCCR0A _SFR_IO8(0x24) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM0A0 4 +#define COM0A1 5 +#define WGM00 6 +#define FOC0A 7 + +/* Reserved [0x25] */ + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +/* Reserved [0x28..0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRLCD 4 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom329p.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_IO8(0x12) +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 + +/* Reserved [0x18..0x1B] */ + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define PCIF0 4 +#define PCIF1 5 +#define PCIF2 6 +#define PCIF3 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define PCIE0 4 +#define PCIE1 5 +#define PCIE2 6 +#define PCIE3 7 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 +#define TSM 7 +#define PSR2 1 + +#define TCCR0A _SFR_IO8(0x24) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM0A0 4 +#define COM0A1 5 +#define WGM00 6 +#define FOC0A 7 + +/* Reserved [0x25] */ + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +/* Reserved [0x28..0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRLCD 4 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom32a.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define TWBR _SFR_IO8(0x00) + +#define TWSR _SFR_IO8(0x01) +#define TWPS0 0 +#define TWPS1 1 +#define TWS3 3 +#define TWS4 4 +#define TWS5 5 +#define TWS6 6 +#define TWS7 7 + +#define TWAR _SFR_IO8(0x02) + +#define TWDR _SFR_IO8(0x03) + +/* Combine ADCL and ADCH */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) + +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) + +#define ADCSRA _SFR_IO8(0x06) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +#define ADMUX _SFR_IO8(0x07) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define MUX4 4 +#define ADLAR 5 +#define REFS0 6 +#define REFS1 7 + +#define ACSR _SFR_IO8(0x08) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define UBRRL _SFR_IO8(0x09) + +#define UCSRB _SFR_IO8(0x0A) +#define TXB8 0 +#define RXB8 1 +#define UCSZ2 2 +#define TXEN 3 +#define RXEN 4 +#define UDRIE 5 +#define TXCIE 6 +#define RXCIE 7 + +#define UCSRA _SFR_IO8(0x0B) +#define MPCM 0 +#define U2X 1 +#define UPE 2 +#define DOR 3 +#define FE 4 +#define UDRE 5 +#define TXC 6 +#define RXC 7 + +#define UDR _SFR_IO8(0x0C) + +#define SPCR _SFR_IO8(0x0D) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x0E) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x0F) + +#define PIND _SFR_IO8(0x10) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x11) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x12) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINC _SFR_IO8(0x13) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x14) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x15) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PINB _SFR_IO8(0x16) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x17) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x18) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINA _SFR_IO8(0x19) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x1A) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x1B) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0x1D) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x1E) + +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +#define UCSRC _SFR_IO8(0x20) +#define UCPOL 0 +#define UCSZ0 1 +#define UCSZ1 2 +#define USBS 3 +#define UPM0 4 +#define UPM1 5 +#define UMSEL 6 +#define URSEL 7 + +#define UBRRH _SFR_IO8(0x20) + +#define WDTCR _SFR_IO8(0x21) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDTOE 4 + +#define ASSR _SFR_IO8(0x22) +#define TCR2UB 0 +#define OCR2UB 1 +#define TCN2UB 2 +#define AS2 3 + +#define OCR2 _SFR_IO8(0x23) + +#define TCNT2 _SFR_IO8(0x24) + +#define TCCR2 _SFR_IO8(0x25) +#define CS20 0 +#define CS21 1 +#define CS22 2 +#define WGM21 3 +#define COM20 4 +#define COM21 5 +#define WGM20 6 +#define FOC2 7 + +/* Combine ICR1L and ICR1H */ +#define ICR1 _SFR_IO16(0x26) + +#define ICR1L _SFR_IO8(0x26) +#define ICR1H _SFR_IO8(0x27) + +/* Combine OCR1BL and OCR1BH */ +#define OCR1B _SFR_IO16(0x28) + +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Combine OCR1AL and OCR1AH */ +#define OCR1A _SFR_IO16(0x2A) + +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Combine TCNT1L and TCNT1H */ +#define TCNT1 _SFR_IO16(0x2C) + +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +#define TCCR1B _SFR_IO8(0x2E) +#define CS10 0 +#define CS11 1 +#define CS12 2 +#define WGM12 3 +#define WGM13 4 +#define ICES1 6 +#define ICNC1 7 + +#define TCCR1A _SFR_IO8(0x2F) +#define WGM10 0 +#define WGM11 1 +#define FOC1B 2 +#define FOC1A 3 +#define COM1B0 4 +#define COM1B1 5 +#define COM1A0 6 +#define COM1A1 7 + +#define SFIOR _SFR_IO8(0x30) +#define PSR2 0 +#define PSR10 0 +#define PUD 2 +#define ACME 3 +#define ADTS0 5 +#define ADTS1 6 +#define ADTS2 7 + +#define OSCCAL _SFR_IO8(0x31) +#define OSCCAL0 0 +#define OSCCAL1 1 +#define OSCCAL2 2 +#define OSCCAL3 3 +#define OSCCAL4 4 +#define OSCCAL5 5 +#define OSCCAL6 6 +#define OSCCAL7 7 + +#define TCNT0 _SFR_IO8(0x32) + +#define TCCR0 _SFR_IO8(0x33) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM00 4 +#define COM01 5 +#define WGM00 6 +#define FOC0 7 + +#define MCUCSR _SFR_IO8(0x34) +#define ISC2 6 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 +#define JTD 7 + +#define MCUCR _SFR_IO8(0x35) +#define ISC00 0 +#define ISC01 1 +#define ISC10 2 +#define ISC11 3 +#define SM0 4 +#define SM1 5 +#define SM2 6 +#define SE 7 + +#define TWCR _SFR_IO8(0x36) +#define TWIE 0 +#define TWEN 2 +#define TWWC 3 +#define TWSTO 4 +#define TWSTA 5 +#define TWEA 6 +#define TWINT 7 + +#define SPMCR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +#define TIFR _SFR_IO8(0x38) +#define TOV0 0 +#define OCF0 1 +#define TOV2 6 +#define OCF2 7 +#define TOV1 2 +#define OCF1B 3 +#define OCF1A 4 +#define ICF1 5 + +#define TIMSK _SFR_IO8(0x39) +#define TOIE0 0 +#define OCIE0 1 +#define TOIE2 6 +#define OCIE2 7 +#define TOIE1 2 +#define OCIE1B 3 +#define OCIE1A 4 +#define TICIE1 5 + +#define GIFR _SFR_IO8(0x3A) +#define INTF2 5 +#define INTF0 6 +#define INTF1 7 + +#define GICR _SFR_IO8(0x3B) +#define IVCE 0 +#define IVSEL 1 +#define INT2 5 +#define INT0 6 +#define INT1 7 + +#define OCR0 _SFR_IO8(0x3C) + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + + + +/* Values and associated defines */ + + +#define SLEEP_MODE_IDLE (0x00<<4) +#define SLEEP_MODE_ADC (0x01<<4) +#define SLEEP_MODE_PWR_DOWN (0x02<<4) +#define SLEEP_MODE_PWR_SAVE (0x03<<4) +#define SLEEP_MODE_STANDBY (0x06<<4) +#define SLEEP_MODE_EXT_STANDBY (0x07<<4) + +/* Interrupt vectors */ +/* Vector 0 is the reset vector */ +/* External Interrupt Request 0 */ +#define INT0_vect _VECTOR(1) +#define INT0_vect_num 1 + +/* External Interrupt Request 1 */ +#define INT1_vect _VECTOR(2) +#define INT1_vect_num 2 + +/* External Interrupt Request 2 */ +#define INT2_vect _VECTOR(3) +#define INT2_vect_num 3 + +/* Timer/Counter2 Compare Match */ +#define TIMER2_COMP_vect _VECTOR(4) +#define TIMER2_COMP_vect_num 4 + +/* Timer/Counter2 Overflow */ +#define TIMER2_OVF_vect _VECTOR(5) +#define TIMER2_OVF_vect_num 5 + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect _VECTOR(6) +#define TIMER1_CAPT_vect_num 6 + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect _VECTOR(7) +#define TIMER1_COMPA_vect_num 7 + +/* Timer/Counter1 Compare Match B */ +#define TIMER1_COMPB_vect _VECTOR(8) +#define TIMER1_COMPB_vect_num 8 + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect _VECTOR(9) +#define TIMER1_OVF_vect_num 9 + +/* Timer/Counter0 Compare Match */ +#define TIMER0_COMP_vect _VECTOR(10) +#define TIMER0_COMP_vect_num 10 + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect _VECTOR(11) +#define TIMER0_OVF_vect_num 11 + +/* Serial Transfer Complete */ +#define SPI_STC_vect _VECTOR(12) +#define SPI_STC_vect_num 12 + +/* USART, Rx Complete */ +#define USART_RXC_vect _VECTOR(13) +#define USART_RXC_vect_num 13 + +/* USART Data Register Empty */ +#define USART_UDRE_vect _VECTOR(14) +#define USART_UDRE_vect_num 14 + +/* USART, Tx Complete */ +#define USART_TXC_vect _VECTOR(15) +#define USART_TXC_vect_num 15 + +/* ADC Conversion Complete */ +#define ADC_vect _VECTOR(16) +#define ADC_vect_num 16 + +/* EEPROM Ready */ +#define EE_RDY_vect _VECTOR(17) +#define EE_RDY_vect_num 17 + +/* Analog Comparator */ +#define ANA_COMP_vect _VECTOR(18) +#define ANA_COMP_vect_num 18 + +/* 2-wire Serial Interface */ +#define TWI_vect _VECTOR(19) +#define TWI_vect_num 19 + +/* Store Program Memory Ready */ +#define SPM_RDY_vect _VECTOR(20) +#define SPM_RDY_vect_num 20 + +#define _VECTORS_SIZE 84 + + +/* Constants */ + +#define SPM_PAGESIZE 128 +#define FLASHSTART 0x0000 +#define FLASHEND 0x7FFF +#define RAMSTART 0x0060 +#define RAMSIZE 2048 +#define RAMEND 0x085F +#define E2START 0 +#define E2SIZE 1024 +#define E2PAGESIZE 4 +#define E2END 0x03FF +#define XRAMEND RAMEND + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 2 + +/* Low Fuse Byte */ +#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) +#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) +#define FUSE_BODEN (unsigned char)~_BV(6) +#define FUSE_BODLEVEL (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_SUT_CKSEL1 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4) + + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_CKOPT (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x02 + + +#endif /* #ifdef _AVR_ATMEGA32A_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iom32c1.h b/hardware/tools/avr/avr/include/avr/iom32c1.h new file mode 100644 index 0000000000000000000000000000000000000000..e92cfe44027553a476bbf82fa54a05d399142f2b --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom32c1.h @@ -0,0 +1,1320 @@ +/* Copyright (c) 2009 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom32c1.h 2183 2010-09-21 05:37:46Z aboyapati $ */ + +/* avr/iom32c1.h - definitions for ATmega32C1 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom32c1.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega32C1_H_ +#define _AVR_ATmega32C1_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define PINE _SFR_IO8(0x0C) +#define PINE0 0 +#define PINE1 1 +#define PINE2 2 + +#define DDRE _SFR_IO8(0x0D) +#define DDE0 0 +#define DDE1 1 +#define DDE2 2 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE0 0 +#define PORTE1 1 +#define PORTE2 2 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define GPIOR1 _SFR_IO8(0x19) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x1A) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 + +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 +#define PSRSYNC 0 +#define ICPSEL1 6 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 +#define PLLE 1 +#define PLLF 2 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define AC0O 0 +#define AC1O 1 +#define AC2O 2 +#define AC3O 3 +#define AC0IF 4 +#define AC1IF 5 +#define AC2IF 6 +#define AC3IF 7 + +#define DWDR _SFR_IO8(0x31) + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define SPIPS 7 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRLIN 1 +#define PRSPI 2 +#define PRTIM0 3 +#define PRTIM1 4 +#define PRPSC 5 +#define PRCAN 6 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom32hvb.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega32HVB_H_ +#define _AVR_ATmega32HVB_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINA _SFR_IO8(0x00) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 + +#define PORTA _SFR_IO8(0x02) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define ICF0 3 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 3 + +#define OSICSR _SFR_IO8(0x17) +#define OSIEN 0 +#define OSIST 1 +#define OSISEL0 4 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define ICS0 3 +#define ICES0 4 +#define ICNC0 5 +#define ICEN0 6 +#define TCW0 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 + +#define TCNT0 _SFR_IO16(0x26) + +#define TCNT0L _SFR_IO8(0x26) +#define TCNT0L0 0 +#define TCNT0L1 1 +#define TCNT0L2 2 +#define TCNT0L3 3 +#define TCNT0L4 4 +#define TCNT0L5 5 +#define TCNT0L6 6 +#define TCNT0L7 7 + +#define TCNT0H _SFR_IO8(0x27) +#define TCNT0H0 0 +#define TCNT0H1 1 +#define TCNT0H2 2 +#define TCNT0H3 3 +#define TCNT0H4 4 +#define TCNT0H5 5 +#define TCNT0H6 6 +#define TCNT0H7 7 + +#define OCR0A _SFR_IO8(0x28) +#define OCR0A0 0 +#define OCR0A1 1 +#define OCR0A2 2 +#define OCR0A3 3 +#define OCR0A4 4 +#define OCR0A5 5 +#define OCR0A6 6 +#define OCR0A7 7 + +#define OCR0B _SFR_IO8(0x29) +#define OCR0B0 0 +#define OCR0B1 1 +#define OCR0B2 2 +#define OCR0B3 3 +#define OCR0B4 4 +#define OCR0B5 5 +#define OCR0B6 6 +#define OCR0B7 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define DWDR _SFR_IO8(0x31) + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BODRF 2 +#define WDRF 3 +#define OCDRF 4 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define CKOE 5 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define LBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPCE 7 + +#define PRR0 _SFR_MEM8(0x64) +#define PRVADC 0 +#define PRTIM0 1 +#define PRTIM1 2 +#define PRSPI 3 +#define PRVRM 5 +#define PRTWI 6 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom32hvbrevb.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_IOM32HVBREVB_H_ +#define _AVR_IOM32HVBREVB_H_ 1 + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 + +#define PORTA _SFR_IO8(0x02) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define ICF0 3 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 3 + +#define OSICSR _SFR_IO8(0x17) +#define OSIEN 0 +#define OSIST 1 +#define OSISEL0 4 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define ICS0 3 +#define ICES0 4 +#define ICNC0 5 +#define ICEN0 6 +#define TCW0 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 + +#define TCNT0 _SFR_IO16(0x26) + +#define TCNT0L _SFR_IO8(0x26) +#define TCNT0L0 0 +#define TCNT0L1 1 +#define TCNT0L2 2 +#define TCNT0L3 3 +#define TCNT0L4 4 +#define TCNT0L5 5 +#define TCNT0L6 6 +#define TCNT0L7 7 + +#define TCNT0H _SFR_IO8(0x27) +#define TCNT0H0 0 +#define TCNT0H1 1 +#define TCNT0H2 2 +#define TCNT0H3 3 +#define TCNT0H4 4 +#define TCNT0H5 5 +#define TCNT0H6 6 +#define TCNT0H7 7 + +#define OCR0A _SFR_IO8(0x28) +#define OCR0A0 0 +#define OCR0A1 1 +#define OCR0A2 2 +#define OCR0A3 3 +#define OCR0A4 4 +#define OCR0A5 5 +#define OCR0A6 6 +#define OCR0A7 7 + +#define OCR0B _SFR_IO8(0x29) +#define OCR0B0 0 +#define OCR0B1 1 +#define OCR0B2 2 +#define OCR0B3 3 +#define OCR0B4 4 +#define OCR0B5 5 +#define OCR0B6 6 +#define OCR0B7 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BODRF 2 +#define WDRF 3 +#define OCDRF 4 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define CKOE 5 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define LBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPCE 7 + +#define PRR0 _SFR_MEM8(0x64) +#define PRVADC 0 +#define PRTIM0 1 +#define PRTIM1 2 +#define PRSPI 3 +#define PRVRM 5 +#define PRTWI 6 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom32m1.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega32M1_H_ +#define _AVR_ATmega32M1_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define PINE _SFR_IO8(0x0C) +#define PINE0 0 +#define PINE1 1 +#define PINE2 2 + +#define DDRE _SFR_IO8(0x0D) +#define DDE0 0 +#define DDE1 1 +#define DDE2 2 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE0 0 +#define PORTE1 1 +#define PORTE2 2 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define GPIOR1 _SFR_IO8(0x19) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x1A) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 + +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 +#define PSRSYNC 0 +#define ICPSEL1 6 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 +#define PLLE 1 +#define PLLF 2 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define AC0O 0 +#define AC1O 1 +#define AC2O 2 +#define AC3O 3 +#define AC0IF 4 +#define AC1IF 5 +#define AC2IF 6 +#define AC3IF 7 + +#define DWDR _SFR_IO8(0x31) + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define SPIPS 7 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRLIN 1 +#define PRSPI 2 +#define PRTIM0 3 +#define PRTIM1 4 +#define PRPSC 5 +#define PRCAN 6 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom32u2.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega32U2_H_ +#define _AVR_ATmega32U2_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define OCF1C 3 +#define ICF1 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 +#define EEAR10 2 +#define EEAR11 3 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 +#define PLLE 1 +#define PLLP0 2 +#define PLLP1 3 +#define PLLP2 4 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define DWDR _SFR_IO8(0x31) +#define DWDR0 0 +#define DWDR1 1 +#define DWDR2 2 +#define DWDR3 3 +#define DWDR4 4 +#define DWDR5 5 +#define DWDR6 6 +#define DWDR7 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define USBRF 5 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define EIND _SFR_IO8(0x3C) +#define EIND0 0 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define WDTCKD _SFR_MEM8(0x62) +#define WCLKD0 0 +#define WCLKD1 1 +#define WDEWIE 2 +#define WDEWIF 3 + +#define REGCR _SFR_MEM8(0x63) +#define REGDIS 0 + +#define PRR0 _SFR_MEM8(0x64) +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom32u4.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_IOM32U4_H_ +#define _AVR_IOM32U4_H_ 1 + + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define PINE _SFR_IO8(0x0C) +#define PINE2 2 +#define PINE6 6 + +#define DDRE _SFR_IO8(0x0D) +#define DDE2 2 +#define DDE6 6 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE2 2 +#define PORTE6 6 + +#define PINF _SFR_IO8(0x0F) +#define PINF0 0 +#define PINF1 1 +#define PINF4 4 +#define PINF5 5 +#define PINF6 6 +#define PINF7 7 + +#define DDRF _SFR_IO8(0x10) +#define DDF0 0 +#define DDF1 1 +#define DDF4 4 +#define DDF5 5 +#define DDF6 6 +#define DDF7 7 + +#define PORTF _SFR_IO8(0x11) +#define PORTF0 0 +#define PORTF1 1 +#define PORTF4 4 +#define PORTF5 5 +#define PORTF6 6 +#define PORTF7 7 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define OCF1C 3 +#define ICF1 5 + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define OCF3C 3 +#define ICF3 5 + +#define TIFR4 _SFR_IO8(0x19) +#define TOV4 2 +#define OCF4B 5 +#define OCF4A 6 +#define OCF4D 7 + +#define TIFR5 _SFR_IO8(0x1A) + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 +#define EEAR10 2 +#define EEAR11 3 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 +#define PLLE 1 +#define PINDIV 4 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +#define PLLFRQ _SFR_IO8(0x32) +#define PDIV0 0 +#define PDIV1 1 +#define PDIV2 2 +#define PDIV3 3 +#define PLLTM0 4 +#define PLLTM1 5 +#define PLLUSB 6 +#define PINMUX 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define JTD 7 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define RAMPZ _SFR_IO8(0x3B) +#define RAMPZ0 0 + +#define EIND _SFR_IO8(0x3C) +#define EIND0 0 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR0 _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom32u6.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega32U6_H_ +#define _AVR_ATmega32U6_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINA _SFR_IO8(0x00) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 +#define PINA4 4 +#define PINA5 5 +#define PINA6 6 +#define PINA7 7 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 +#define PORTA4 4 +#define PORTA5 5 +#define PORTA6 6 +#define PORTA7 7 + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define PINE _SFR_IO8(0x0C) +#define PINE0 0 +#define PINE1 1 +#define PINE2 2 +#define PINE3 3 +#define PINE4 4 +#define PINE5 5 +#define PINE6 6 +#define PINE7 7 + +#define DDRE _SFR_IO8(0x0D) +#define DDE0 0 +#define DDE1 1 +#define DDE2 2 +#define DDE3 3 +#define DDE4 4 +#define DDE5 5 +#define DDE6 6 +#define DDE7 7 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE0 0 +#define PORTE1 1 +#define PORTE2 2 +#define PORTE3 3 +#define PORTE4 4 +#define PORTE5 5 +#define PORTE6 6 +#define PORTE7 7 + +#define PINF _SFR_IO8(0x0F) +#define PINF0 0 +#define PINF1 1 +#define PINF2 2 +#define PINF3 3 +#define PINF4 4 +#define PINF5 5 +#define PINF6 6 +#define PINF7 7 + +#define DDRF _SFR_IO8(0x10) +#define DDF0 0 +#define DDF1 1 +#define DDF2 2 +#define DDF3 3 +#define DDF4 4 +#define DDF5 5 +#define DDF6 6 +#define DDF7 7 + +#define PORTF _SFR_IO8(0x11) +#define PORTF0 0 +#define PORTF1 1 +#define PORTF2 2 +#define PORTF3 3 +#define PORTF4 4 +#define PORTF5 5 +#define PORTF6 6 +#define PORTF7 7 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define OCF1C 3 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define OCF3C 3 +#define ICF3 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 +#define EEAR10 2 +#define EEAR11 3 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 +#define PLLE 1 +#define PLLP0 2 +#define PLLP1 3 +#define PLLP2 4 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define JTD 7 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR0 _SFR_MEM8(0x64) +#define PRADC 0 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom406.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Reserved [0x06..0x07] */ + +#define PORTC _SFR_IO8(0x08) +#define PC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD1 1 +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PD1 1 +#define PD0 0 + +/* Reserved [0x0C..0x14] */ + +/* Timer/Counter0 Interrupt Flag Register */ +#define TIFR0 _SFR_IO8(0x15) +#define OCF0B 2 +#define OCF0A 1 +#define TOV0 0 + +/* Timer/Counter1 Interrupt Flag Register */ +#define TIFR1 _SFR_IO8(0x16) +#define OCF1A 1 +#define TOV1 0 + +/* Reserved [0x17..0x1A] */ + +/* Pin Change Interrupt Control Register */ +#define PCIFR _SFR_IO8(0x1B) +#define PCIF1 1 +#define PCIF0 0 + +/* External Interrupt Flag Register */ +#define EIFR _SFR_IO8(0x1C) +#define INTF3 3 +#define INTF2 2 +#define INTF1 1 +#define INTF0 0 + +/* External Interrupt MaSK register */ +#define EIMSK _SFR_IO8(0x1D) +#define INT3 3 +#define INT2 2 +#define INT1 1 +#define INT0 0 + +/* General Purpose I/O Register 0 */ +#define GPIOR0 _SFR_IO8(0x1E) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1F) +#define EEPM1 5 +#define EEPM0 4 +#define EERIE 3 +#define EEMPE 2 +#define EEPE 1 +#define EERE 0 + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x20) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +/* General Timer/Counter Control Register */ +#define GTCCR _SFR_IO8(0x23) +#define TSM 7 +#define PSRSYNC 0 + +/* Timer/Counter Control Register A */ +#define TCCR0A _SFR_IO8(0x24) +#define COM0A1 7 +#define COM0A0 6 +#define COM0B1 5 +#define COM0B0 4 +#define WGM01 1 +#define WGM00 0 + +/* Timer/Counter Control Register B */ +#define TCCR0B _SFR_IO8(0x25) +#define FOC0A 7 +#define FOC0B 6 +#define WGM02 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* Timer/Counter 0 */ +#define TCNT0 _SFR_IO8(0x26) + +/* Output Compare Register A */ +#define OCR0A _SFR_IO8(0x27) + +/* Output Compare Register B */ +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +/* General Purpose I/O Register 1 */ +#define GPIOR1 _SFR_IO8(0x2A) + +/* General Purpose I/O Register 2 */ +#define GPIOR2 _SFR_IO8(0x2B) + +/* Reserved [0x2C..0x30] */ + +/* On-chip Debug Register */ +#define OCDR _SFR_IO8(0x31) + +/* Reserved [0x32] */ + +/* Sleep Mode Control Register */ +#define SMCR _SFR_IO8(0x33) +#define SM2 3 +#define SM1 2 +#define SM0 1 +#define SE 0 + +/* MCU Status Register */ +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define WDRF 3 +#define BODRF 2 +#define EXTRF 1 +#define PORF 0 + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define PUD 4 +#define IVSEL 1 +#define IVCE 0 + +/* Reserved [0x36] */ + +/* Store Program Memory Control and Status Register */ +#define SPMCSR _SFR_IO8(0x37) +#define SPMIE 7 +#define RWWSB 6 +#define SIGRD 5 +#define RWWSRE 4 +#define BLBSET 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 + +/* Reserved [0x36..0x3C] */ + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Extended I/O registers */ + +/* Watchdog Timer Control Register */ +#define WDTCSR _SFR_MEM8(0x60) +#define WDIF 7 +#define WDIE 6 +#define WDP3 5 +#define WDCE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* Reserved [0x61] */ + +/* Wake-up Timer Control and Status Register */ +#define WUTCSR _SFR_MEM8(0x62) +#define WUTIF 7 +#define WUTIE 6 +#define WUTCF 5 +#define WUTR 4 +#define WUTE 3 +#define WUTP2 2 +#define WUTP1 1 +#define WUTP0 0 + +/* Reserved [0x63] */ + +/* Power Reduction Register 0 */ +#define PRR0 _SFR_MEM8(0x64) +#define PRTWI 3 +#define PRTIM1 2 +#define PRTIM0 1 +#define PRVADC 0 + +#define __AVR_HAVE_PRR0 ((1< + +/* Constants */ +#define SPM_PAGESIZE 64 +#define RAMSTART (0x100) +#define RAMEND 0x2FF +#define XRAMEND RAMEND +#define E2END 0xFF +#define E2PAGESIZE 4 +#define FLASHEND 0xFFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ +#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) + +/* High Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ +#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ +#define HFUSE_DEFAULT (FUSE_SPIEN) + +/* Extended Fuse Byte */ +#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x92 +#define SIGNATURE_2 0x05 + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) + +#endif /* _AVR_IOM48_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom4808.h b/hardware/tools/avr/avr/include/avr/iom4808.h new file mode 100644 index 0000000000000000000000000000000000000000..45f19eb0c35e228de6e18742ecbb7afbedc290a2 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom4808.h @@ -0,0 +1,4955 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom4808.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATMEGA4808_H_INCLUDED +#define _AVR_ATMEGA4808_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[1]; + register8_t DACREF; /* Referance scale control */ + register8_t reserved_3[1]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_PIN2_gc = (0x02<<0), /* Negative Pin 2 */ + AC_MUXNEG_DACREF_gc = (0x03<<0), /* DAC Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ + ADC_MUXPOS_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ + ADC_MUXPOS_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ + ADC_MUXPOS_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ + ADC_MUXPOS_DACREF_gc = (0x1C<<0), /* AC DAC Reference */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temperature sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* 0V (GND) */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t SEQCTRL1; /* Sequential Control 1 */ + register8_t reserved_1[2]; + register8_t INTCTRL0; /* Interrupt Control 0 */ + register8_t reserved_2[1]; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t LUT2CTRLA; /* LUT Control 2 A */ + register8_t LUT2CTRLB; /* LUT Control 2 B */ + register8_t LUT2CTRLC; /* LUT Control 2 C */ + register8_t TRUTH2; /* Truth 2 */ + register8_t LUT3CTRLA; /* LUT Control 3 A */ + register8_t LUT3CTRLB; /* LUT Control 3 B */ + register8_t LUT3CTRLC; /* LUT Control 3 C */ + register8_t TRUTH3; /* Truth 3 */ + register8_t reserved_3[40]; +} CCL_t; + +/* Clock Source Selection select */ +typedef enum CCL_CLKSRC_enum +{ + CCL_CLKSRC_CLKPER_gc = (0x00<<1), /* CLK_PER is clocking the LUT */ + CCL_CLKSRC_IN2_gc = (0x01<<1), /* IN[2] is clocking the LUT */ + CCL_CLKSRC_OSC20M_gc = (0x04<<1), /* 20MHz oscillator before prescaler is clocking the LUT */ + CCL_CLKSRC_OSCULP32K_gc = (0x05<<1), /* 32kHz oscillator is clocking the LUT */ + CCL_CLKSRC_OSCULP1K_gc = (0x06<<1), /* 32kHz oscillator after DIV32 is clocking the LUT */ +} CCL_CLKSRC_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL0_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_USART0_gc = (0x08<<0), /* USART0 TXD input source */ + CCL_INSEL0_SPI0_gc = (0x09<<0), /* SPI0 MOSI input source */ + CCL_INSEL0_TCA0_gc = (0x0A<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCB0_gc = (0x0C<<0), /* TCB0 WO input source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENTA_gc = (0x03<<4), /* Event input source A */ + CCL_INSEL1_EVENTB_gc = (0x04<<4), /* Event input source B */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_USART1_gc = (0x08<<4), /* USART1 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x09<<4), /* SPI0 MOSI input source */ + CCL_INSEL1_TCA0_gc = (0x0A<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCB1_gc = (0x0C<<4), /* TCB1 WO input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL2_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_USART2_gc = (0x08<<0), /* USART2 TXD input source */ + CCL_INSEL2_SPI0_gc = (0x09<<0), /* SPI0 SCK input source */ + CCL_INSEL2_TCA0_gc = (0x0A<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCB2_gc = (0x0C<<0), /* TCB2 WO input source */ +} CCL_INSEL2_t; + +/* Interrupt Mode for LUT0 select */ +typedef enum CCL_INTMODE0_enum +{ + CCL_INTMODE0_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled */ + CCL_INTMODE0_RISING_gc = (0x01<<0), /* Sense rising edge */ + CCL_INTMODE0_FALLING_gc = (0x02<<0), /* Sense falling edge */ + CCL_INTMODE0_BOTH_gc = (0x03<<0), /* Sense both edges */ +} CCL_INTMODE0_t; + +/* Interrupt Mode for LUT1 select */ +typedef enum CCL_INTMODE1_enum +{ + CCL_INTMODE1_INTDISABLE_gc = (0x00<<2), /* Interrupt disabled */ + CCL_INTMODE1_RISING_gc = (0x01<<2), /* Sense rising edge */ + CCL_INTMODE1_FALLING_gc = (0x02<<2), /* Sense falling edge */ + CCL_INTMODE1_BOTH_gc = (0x03<<2), /* Sense both edges */ +} CCL_INTMODE1_t; + +/* Interrupt Mode for LUT2 select */ +typedef enum CCL_INTMODE2_enum +{ + CCL_INTMODE2_INTDISABLE_gc = (0x00<<4), /* Interrupt disabled */ + CCL_INTMODE2_RISING_gc = (0x01<<4), /* Sense rising edge */ + CCL_INTMODE2_FALLING_gc = (0x02<<4), /* Sense falling edge */ + CCL_INTMODE2_BOTH_gc = (0x03<<4), /* Sense both edges */ +} CCL_INTMODE2_t; + +/* Interrupt Mode for LUT3 select */ +typedef enum CCL_INTMODE3_enum +{ + CCL_INTMODE3_INTDISABLE_gc = (0x00<<6), /* Interrupt disabled */ + CCL_INTMODE3_RISING_gc = (0x01<<6), /* Sense rising edge */ + CCL_INTMODE3_FALLING_gc = (0x02<<6), /* Sense falling edge */ + CCL_INTMODE3_BOTH_gc = (0x03<<6), /* Sense both edges */ +} CCL_INTMODE3_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL0_enum +{ + CCL_SEQSEL0_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL0_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL0_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL0_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL0_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL0_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL1_enum +{ + CCL_SEQSEL1_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL1_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL1_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL1_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL1_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL1_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1k cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16k cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32k cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t STROBE; /* Channel Strobe */ + register8_t reserved_1[15]; + register8_t CHANNEL0; /* Multiplexer Channel 0 */ + register8_t CHANNEL1; /* Multiplexer Channel 1 */ + register8_t CHANNEL2; /* Multiplexer Channel 2 */ + register8_t CHANNEL3; /* Multiplexer Channel 3 */ + register8_t CHANNEL4; /* Multiplexer Channel 4 */ + register8_t CHANNEL5; /* Multiplexer Channel 5 */ + register8_t reserved_2[10]; + register8_t USERCCLLUT0A; /* User CCL LUT0 Event A */ + register8_t USERCCLLUT0B; /* User CCL LUT0 Event B */ + register8_t USERCCLLUT1A; /* User CCL LUT1 Event A */ + register8_t USERCCLLUT1B; /* User CCL LUT1 Event B */ + register8_t USERCCLLUT2A; /* User CCL LUT2 Event A */ + register8_t USERCCLLUT2B; /* User CCL LUT2 Event B */ + register8_t USERCCLLUT3A; /* User CCL LUT3 Event A */ + register8_t USERCCLLUT3B; /* User CCL LUT3 Event B */ + register8_t USERADC0; /* User ADC0 */ + register8_t USEREVOUTA; /* User EVOUT Port A */ + register8_t USEREVOUTB; /* User EVOUT Port B */ + register8_t USEREVOUTC; /* User EVOUT Port C */ + register8_t USEREVOUTD; /* User EVOUT Port D */ + register8_t USEREVOUTE; /* User EVOUT Port E */ + register8_t USEREVOUTF; /* User EVOUT Port F */ + register8_t USERUSART0; /* User USART0 */ + register8_t USERUSART1; /* User USART1 */ + register8_t USERUSART2; /* User USART2 */ + register8_t USERUSART3; /* User USART3 */ + register8_t USERTCA0; /* User TCA0 */ + register8_t USERTCB0; /* User TCB0 */ + register8_t USERTCB1; /* User TCB1 */ + register8_t USERTCB2; /* User TCB2 */ + register8_t USERTCB3; /* User TCB3 */ + register8_t reserved_3[8]; +} EVSYS_t; + +/* Channel selector select */ +typedef enum EVSYS_CHANNEL_enum +{ + EVSYS_CHANNEL_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL_CHANNEL0_gc = (0x01<<0), /* Connect user to event channel 0 */ + EVSYS_CHANNEL_CHANNEL1_gc = (0x02<<0), /* Connect user to event channel 1 */ + EVSYS_CHANNEL_CHANNEL2_gc = (0x03<<0), /* Connect user to event channel 2 */ + EVSYS_CHANNEL_CHANNEL3_gc = (0x04<<0), /* Connect user to event channel 3 */ + EVSYS_CHANNEL_CHANNEL4_gc = (0x05<<0), /* Connect user to event channel 4 */ + EVSYS_CHANNEL_CHANNEL5_gc = (0x06<<0), /* Connect user to event channel 5 */ +} EVSYS_CHANNEL_t; + +/* Generator selector select */ +typedef enum EVSYS_GENERATOR_enum +{ + EVSYS_GENERATOR_OFF_gc = (0x00<<0), /* Off */ + EVSYS_GENERATOR_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_GENERATOR_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_GENERATOR_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_GENERATOR_RTC_PIT0_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_GENERATOR_RTC_PIT1_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_GENERATOR_RTC_PIT2_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_GENERATOR_RTC_PIT3_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_GENERATOR_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_GENERATOR_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_GENERATOR_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_GENERATOR_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_GENERATOR_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_GENERATOR_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready Event */ + EVSYS_GENERATOR_PORT0_PIN0_gc = (0x40<<0), /* Port 0 Pin 0 */ + EVSYS_GENERATOR_PORT0_PIN1_gc = (0x41<<0), /* Port 0 Pin 1 */ + EVSYS_GENERATOR_PORT0_PIN2_gc = (0x42<<0), /* Port 0 Pin 2 */ + EVSYS_GENERATOR_PORT0_PIN3_gc = (0x43<<0), /* Port 0 Pin 3 */ + EVSYS_GENERATOR_PORT0_PIN4_gc = (0x44<<0), /* Port 0 Pin 4 */ + EVSYS_GENERATOR_PORT0_PIN5_gc = (0x45<<0), /* Port 0 Pin 5 */ + EVSYS_GENERATOR_PORT0_PIN6_gc = (0x46<<0), /* Port 0 Pin 6 */ + EVSYS_GENERATOR_PORT0_PIN7_gc = (0x47<<0), /* Port 0 Pin 7 */ + EVSYS_GENERATOR_PORT1_PIN0_gc = (0x48<<0), /* Port 1 Pin 0 */ + EVSYS_GENERATOR_PORT1_PIN1_gc = (0x49<<0), /* Port 1 Pin 1 */ + EVSYS_GENERATOR_PORT1_PIN2_gc = (0x4A<<0), /* Port 1 Pin 2 */ + EVSYS_GENERATOR_PORT1_PIN3_gc = (0x4B<<0), /* Port 1 Pin 3 */ + EVSYS_GENERATOR_PORT1_PIN4_gc = (0x4C<<0), /* Port 1 Pin 4 */ + EVSYS_GENERATOR_PORT1_PIN5_gc = (0x4D<<0), /* Port 1 Pin 5 */ + EVSYS_GENERATOR_PORT1_PIN6_gc = (0x4E<<0), /* Port 1 Pin 6 */ + EVSYS_GENERATOR_PORT1_PIN7_gc = (0x4F<<0), /* Port 1 Pin 7 */ + EVSYS_GENERATOR_USART0_XCK_gc = (0x60<<0), /* USART 0 Xclock */ + EVSYS_GENERATOR_USART1_XCK_gc = (0x61<<0), /* USART 1 Xclock */ + EVSYS_GENERATOR_USART2_XCK_gc = (0x62<<0), /* USART 2 Xclock */ + EVSYS_GENERATOR_USART3_XCK_gc = (0x63<<0), /* USART 3 Xclock */ + EVSYS_GENERATOR_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_GENERATOR_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_GENERATOR_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow (split mode) */ + EVSYS_GENERATOR_TCA0_CMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_GENERATOR_TCA0_CMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_GENERATOR_TCA0_CMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_GENERATOR_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_GENERATOR_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_GENERATOR_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_GENERATOR_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ +} EVSYS_GENERATOR_t; + +/* Software event on channels select */ +typedef enum EVSYS_STROBE0_enum +{ + EVSYS_STROBE0_EV_STROBE_CH0_gc = (0x01<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH1_gc = (0x02<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH2_gc = (0x04<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH3_gc = (0x08<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH4_gc = (0x10<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH5_gc = (0x20<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH6_gc = (0x40<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH7_gc = (0x80<<0), /* */ +} EVSYS_STROBE0_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<3), /* GPIO mode */ + RSTPINCFG_RST_gc = (0x01<<3), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock Bits */ + register8_t reserved_1[1]; +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t PORTCTRL; /* Port Control */ + register8_t reserved_1[5]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t EVSYSROUTEA; /* Port Multiplexer EVSYS */ + register8_t CCLROUTEA; /* Port Multiplexer CCL */ + register8_t USARTROUTEA; /* Port Multiplexer USART register A */ + register8_t TWISPIROUTEA; /* Port Multiplexer TWI and SPI */ + register8_t TCAROUTEA; /* Port Multiplexer TCA */ + register8_t TCBROUTEA; /* Port Multiplexer TCB */ + register8_t reserved_1[10]; +} PORTMUX_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<0), /* SPI0 on PA[7:4] */ + PORTMUX_SPI0_ALT1_gc = (0x01<<0), /* SPI0 on PC[3:0] */ + PORTMUX_SPI0_ALT2_gc = (0x02<<0), /* SPI0 on PE[3:0] */ + PORTMUX_SPI0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 select */ +typedef enum PORTMUX_TCA0_enum +{ + PORTMUX_TCA0_PORTA_gc = (0x00<<0), /* TCA0 pins on PA[5:0] */ + PORTMUX_TCA0_PORTB_gc = (0x01<<0), /* TCA0 pins on PB[5:0] */ + PORTMUX_TCA0_PORTC_gc = (0x02<<0), /* TCA0 pins on PC[5:0] */ + PORTMUX_TCA0_PORTD_gc = (0x03<<0), /* TCA0 pins on PD[5:0] */ + PORTMUX_TCA0_PORTE_gc = (0x04<<0), /* TCA0 pins on PE[5:0] */ + PORTMUX_TCA0_PORTF_gc = (0x05<<0), /* TCA0 pins on PF[5:0] */ +} PORTMUX_TCA0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* SCL/SDA on PA[3:2], Slave mode on PC[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT1_gc = (0x01<<4), /* SCL/SDA on PA[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT2_gc = (0x02<<4), /* SCL/SDA on PC[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* USART0 on PA[3:0] */ + PORTMUX_USART0_ALT1_gc = (0x01<<0), /* USART0 on PA[7:4] */ + PORTMUX_USART0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_USART0_t; + +/* Port Multiplexer USART1 select */ +typedef enum PORTMUX_USART1_enum +{ + PORTMUX_USART1_DEFAULT_gc = (0x00<<2), /* USART1 on PC[3:0] */ + PORTMUX_USART1_ALT1_gc = (0x01<<2), /* USART1 on PC[7:4] */ + PORTMUX_USART1_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_USART1_t; + +/* Port Multiplexer USART2 select */ +typedef enum PORTMUX_USART2_enum +{ + PORTMUX_USART2_DEFAULT_gc = (0x00<<4), /* USART2 on PF[3:0] */ + PORTMUX_USART2_ALT1_gc = (0x01<<4), /* USART2 on PF[6:4] */ + PORTMUX_USART2_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_USART2_t; + +/* Port Multiplexer USART3 select */ +typedef enum PORTMUX_USART3_enum +{ + PORTMUX_USART3_DEFAULT_gc = (0x00<<6), /* USART3 on PB[3:0] */ + PORTMUX_USART3_ALT1_gc = (0x01<<6), /* USART3 on PB[5:4] */ + PORTMUX_USART3_NONE_gc = (0x03<<6), /* Not connected to any pins */ +} PORTMUX_USART3_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t CALIB; /* Calibration */ + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_1[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_2[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_3[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[7]; + register8_t OSCCAL32K; /* Oscillator Calibration for 32kHz ULP */ + register8_t reserved_2[3]; + register8_t OSCCAL16M0; /* Oscillator Calibration 16 MHz Byte 0 */ + register8_t OSCCAL16M1; /* Oscillator Calibration 16 MHz Byte 1 */ + register8_t OSCCAL20M0; /* Oscillator Calibration 20 MHz Byte 0 */ + register8_t OSCCAL20M1; /* Oscillator Calibration 20 MHz Byte 1 */ + register8_t reserved_3[4]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_4[9]; + register8_t CHECKSUM1; /* CRC Checksum Byte 1 */ + register8_t reserved_5[16]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[21]; + register8_t OCDM; /* OCD Message Register */ + register8_t OCDMS; /* OCD Message Status */ + register8_t reserved_3[6]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t DUALCTRL; /* Dual Control */ + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_1[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t CTRLD; /* Control D */ + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_1[1]; +} USART_t; + +/* Auto Baud Window select */ +typedef enum USART_ABW_enum +{ + USART_ABW_WDW0_gc = (0x00<<6), /* 18% tolerance */ + USART_ABW_WDW1_gc = (0x01<<6), /* 15% tolerance */ + USART_ABW_WDW2_gc = (0x02<<6), /* 21% tolerance */ + USART_ABW_WDW3_gc = (0x03<<6), /* 25% tolerance */ +} USART_ABW_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ + register8_t USERROW32; /* User Row Byte 32 */ + register8_t USERROW33; /* User Row Byte 33 */ + register8_t USERROW34; /* User Row Byte 34 */ + register8_t USERROW35; /* User Row Byte 35 */ + register8_t USERROW36; /* User Row Byte 36 */ + register8_t USERROW37; /* User Row Byte 37 */ + register8_t USERROW38; /* User Row Byte 38 */ + register8_t USERROW39; /* User Row Byte 39 */ + register8_t USERROW40; /* User Row Byte 40 */ + register8_t USERROW41; /* User Row Byte 41 */ + register8_t USERROW42; /* User Row Byte 42 */ + register8_t USERROW43; /* User Row Byte 43 */ + register8_t USERROW44; /* User Row Byte 44 */ + register8_t USERROW45; /* User Row Byte 45 */ + register8_t USERROW46; /* User Row Byte 46 */ + register8_t USERROW47; /* User Row Byte 47 */ + register8_t USERROW48; /* User Row Byte 48 */ + register8_t USERROW49; /* User Row Byte 49 */ + register8_t USERROW50; /* User Row Byte 50 */ + register8_t USERROW51; /* User Row Byte 51 */ + register8_t USERROW52; /* User Row Byte 52 */ + register8_t USERROW53; /* User Row Byte 53 */ + register8_t USERROW54; /* User Row Byte 54 */ + register8_t USERROW55; /* User Row Byte 55 */ + register8_t USERROW56; /* User Row Byte 56 */ + register8_t USERROW57; /* User Row Byte 57 */ + register8_t USERROW58; /* User Row Byte 58 */ + register8_t USERROW59; /* User Row Byte 59 */ + register8_t USERROW60; /* User Row Byte 60 */ + register8_t USERROW61; /* User Row Byte 61 */ + register8_t USERROW62; /* User Row Byte 62 */ + register8_t USERROW63; /* User Row Byte 63 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* AC0 reference select select */ +typedef enum VREF_AC0REFSEL_enum +{ + VREF_AC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_AC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_AC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_AC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_AC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ + VREF_AC0REFSEL_AVDD_gc = (0x07<<0), /* AVDD */ +} VREF_AC0REFSEL_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define VPORTD (*(VPORT_t *) 0x000C) /* Virtual Ports */ +#define VPORTE (*(VPORT_t *) 0x0010) /* Virtual Ports */ +#define VPORTF (*(VPORT_t *) 0x0014) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0460) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0480) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x04A0) /* I/O Ports */ +#define PORTMUX (*(PORTMUX_t *) 0x05E0) /* Port Multiplexer */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1 (*(USART_t *) 0x0820) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2 (*(USART_t *) 0x0840) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x08A0) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A80) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0A90) /* 16-bit Timer Type B */ +#define TCB2 (*(TCB_t *) 0x0AA0) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* VPORT (VPORTD) - Virtual Ports */ +#define VPORTD_DIR _SFR_MEM8(0x000C) +#define VPORTD_OUT _SFR_MEM8(0x000D) +#define VPORTD_IN _SFR_MEM8(0x000E) +#define VPORTD_INTFLAGS _SFR_MEM8(0x000F) + + +/* VPORT (VPORTE) - Virtual Ports */ +#define VPORTE_DIR _SFR_MEM8(0x0010) +#define VPORTE_OUT _SFR_MEM8(0x0011) +#define VPORTE_IN _SFR_MEM8(0x0012) +#define VPORTE_INTFLAGS _SFR_MEM8(0x0013) + + +/* VPORT (VPORTF) - Virtual Ports */ +#define VPORTF_DIR _SFR_MEM8(0x0014) +#define VPORTF_OUT _SFR_MEM8(0x0015) +#define VPORTF_IN _SFR_MEM8(0x0016) +#define VPORTF_INTFLAGS _SFR_MEM8(0x0017) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CALIB _SFR_MEM8(0x0146) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_STROBE _SFR_MEM8(0x0180) +#define EVSYS_CHANNEL0 _SFR_MEM8(0x0190) +#define EVSYS_CHANNEL1 _SFR_MEM8(0x0191) +#define EVSYS_CHANNEL2 _SFR_MEM8(0x0192) +#define EVSYS_CHANNEL3 _SFR_MEM8(0x0193) +#define EVSYS_CHANNEL4 _SFR_MEM8(0x0194) +#define EVSYS_CHANNEL5 _SFR_MEM8(0x0195) +#define EVSYS_USERCCLLUT0A _SFR_MEM8(0x01A0) +#define EVSYS_USERCCLLUT0B _SFR_MEM8(0x01A1) +#define EVSYS_USERCCLLUT1A _SFR_MEM8(0x01A2) +#define EVSYS_USERCCLLUT1B _SFR_MEM8(0x01A3) +#define EVSYS_USERCCLLUT2A _SFR_MEM8(0x01A4) +#define EVSYS_USERCCLLUT2B _SFR_MEM8(0x01A5) +#define EVSYS_USERCCLLUT3A _SFR_MEM8(0x01A6) +#define EVSYS_USERCCLLUT3B _SFR_MEM8(0x01A7) +#define EVSYS_USERADC0 _SFR_MEM8(0x01A8) +#define EVSYS_USEREVOUTA _SFR_MEM8(0x01A9) +#define EVSYS_USEREVOUTB _SFR_MEM8(0x01AA) +#define EVSYS_USEREVOUTC _SFR_MEM8(0x01AB) +#define EVSYS_USEREVOUTD _SFR_MEM8(0x01AC) +#define EVSYS_USEREVOUTE _SFR_MEM8(0x01AD) +#define EVSYS_USEREVOUTF _SFR_MEM8(0x01AE) +#define EVSYS_USERUSART0 _SFR_MEM8(0x01AF) +#define EVSYS_USERUSART1 _SFR_MEM8(0x01B0) +#define EVSYS_USERUSART2 _SFR_MEM8(0x01B1) +#define EVSYS_USERUSART3 _SFR_MEM8(0x01B2) +#define EVSYS_USERTCA0 _SFR_MEM8(0x01B3) +#define EVSYS_USERTCB0 _SFR_MEM8(0x01B4) +#define EVSYS_USERTCB1 _SFR_MEM8(0x01B5) +#define EVSYS_USERTCB2 _SFR_MEM8(0x01B6) +#define EVSYS_USERTCB3 _SFR_MEM8(0x01B7) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_SEQCTRL1 _SFR_MEM8(0x01C2) +#define CCL_INTCTRL0 _SFR_MEM8(0x01C5) +#define CCL_INTFLAGS _SFR_MEM8(0x01C7) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C8) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C9) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01CA) +#define CCL_TRUTH0 _SFR_MEM8(0x01CB) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01CC) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CD) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CE) +#define CCL_TRUTH1 _SFR_MEM8(0x01CF) +#define CCL_LUT2CTRLA _SFR_MEM8(0x01D0) +#define CCL_LUT2CTRLB _SFR_MEM8(0x01D1) +#define CCL_LUT2CTRLC _SFR_MEM8(0x01D2) +#define CCL_TRUTH2 _SFR_MEM8(0x01D3) +#define CCL_LUT3CTRLA _SFR_MEM8(0x01D4) +#define CCL_LUT3CTRLB _SFR_MEM8(0x01D5) +#define CCL_LUT3CTRLC _SFR_MEM8(0x01D6) +#define CCL_TRUTH3 _SFR_MEM8(0x01D7) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PORTCTRL _SFR_MEM8(0x040A) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PORTCTRL _SFR_MEM8(0x042A) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PORTCTRL _SFR_MEM8(0x044A) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* PORT (PORTD) - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0460) +#define PORTD_DIRSET _SFR_MEM8(0x0461) +#define PORTD_DIRCLR _SFR_MEM8(0x0462) +#define PORTD_DIRTGL _SFR_MEM8(0x0463) +#define PORTD_OUT _SFR_MEM8(0x0464) +#define PORTD_OUTSET _SFR_MEM8(0x0465) +#define PORTD_OUTCLR _SFR_MEM8(0x0466) +#define PORTD_OUTTGL _SFR_MEM8(0x0467) +#define PORTD_IN _SFR_MEM8(0x0468) +#define PORTD_INTFLAGS _SFR_MEM8(0x0469) +#define PORTD_PORTCTRL _SFR_MEM8(0x046A) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0470) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0471) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0472) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0473) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0474) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0475) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0476) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0477) + + +/* PORT (PORTE) - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0480) +#define PORTE_DIRSET _SFR_MEM8(0x0481) +#define PORTE_DIRCLR _SFR_MEM8(0x0482) +#define PORTE_DIRTGL _SFR_MEM8(0x0483) +#define PORTE_OUT _SFR_MEM8(0x0484) +#define PORTE_OUTSET _SFR_MEM8(0x0485) +#define PORTE_OUTCLR _SFR_MEM8(0x0486) +#define PORTE_OUTTGL _SFR_MEM8(0x0487) +#define PORTE_IN _SFR_MEM8(0x0488) +#define PORTE_INTFLAGS _SFR_MEM8(0x0489) +#define PORTE_PORTCTRL _SFR_MEM8(0x048A) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0490) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0491) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0492) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0493) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0494) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0495) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0496) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0497) + + +/* PORT (PORTF) - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x04A0) +#define PORTF_DIRSET _SFR_MEM8(0x04A1) +#define PORTF_DIRCLR _SFR_MEM8(0x04A2) +#define PORTF_DIRTGL _SFR_MEM8(0x04A3) +#define PORTF_OUT _SFR_MEM8(0x04A4) +#define PORTF_OUTSET _SFR_MEM8(0x04A5) +#define PORTF_OUTCLR _SFR_MEM8(0x04A6) +#define PORTF_OUTTGL _SFR_MEM8(0x04A7) +#define PORTF_IN _SFR_MEM8(0x04A8) +#define PORTF_INTFLAGS _SFR_MEM8(0x04A9) +#define PORTF_PORTCTRL _SFR_MEM8(0x04AA) +#define PORTF_PIN0CTRL _SFR_MEM8(0x04B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x04B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x04B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x04B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x04B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x04B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x04B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x04B7) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_EVSYSROUTEA _SFR_MEM8(0x05E0) +#define PORTMUX_CCLROUTEA _SFR_MEM8(0x05E1) +#define PORTMUX_USARTROUTEA _SFR_MEM8(0x05E2) +#define PORTMUX_TWISPIROUTEA _SFR_MEM8(0x05E3) +#define PORTMUX_TCAROUTEA _SFR_MEM8(0x05E4) +#define PORTMUX_TCBROUTEA _SFR_MEM8(0x05E5) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_DACREF _SFR_MEM8(0x0684) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_CTRLD _SFR_MEM8(0x080A) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* USART (USART1) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1_RXDATAL _SFR_MEM8(0x0820) +#define USART1_RXDATAH _SFR_MEM8(0x0821) +#define USART1_TXDATAL _SFR_MEM8(0x0822) +#define USART1_TXDATAH _SFR_MEM8(0x0823) +#define USART1_STATUS _SFR_MEM8(0x0824) +#define USART1_CTRLA _SFR_MEM8(0x0825) +#define USART1_CTRLB _SFR_MEM8(0x0826) +#define USART1_CTRLC _SFR_MEM8(0x0827) +#define USART1_BAUD _SFR_MEM16(0x0828) +#define USART1_BAUDL _SFR_MEM8(0x0828) +#define USART1_BAUDH _SFR_MEM8(0x0829) +#define USART1_CTRLD _SFR_MEM8(0x082A) +#define USART1_DBGCTRL _SFR_MEM8(0x082B) +#define USART1_EVCTRL _SFR_MEM8(0x082C) +#define USART1_TXPLCTRL _SFR_MEM8(0x082D) +#define USART1_RXPLCTRL _SFR_MEM8(0x082E) + + +/* USART (USART2) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2_RXDATAL _SFR_MEM8(0x0840) +#define USART2_RXDATAH _SFR_MEM8(0x0841) +#define USART2_TXDATAL _SFR_MEM8(0x0842) +#define USART2_TXDATAH _SFR_MEM8(0x0843) +#define USART2_STATUS _SFR_MEM8(0x0844) +#define USART2_CTRLA _SFR_MEM8(0x0845) +#define USART2_CTRLB _SFR_MEM8(0x0846) +#define USART2_CTRLC _SFR_MEM8(0x0847) +#define USART2_BAUD _SFR_MEM16(0x0848) +#define USART2_BAUDL _SFR_MEM8(0x0848) +#define USART2_BAUDH _SFR_MEM8(0x0849) +#define USART2_CTRLD _SFR_MEM8(0x084A) +#define USART2_DBGCTRL _SFR_MEM8(0x084B) +#define USART2_EVCTRL _SFR_MEM8(0x084C) +#define USART2_TXPLCTRL _SFR_MEM8(0x084D) +#define USART2_RXPLCTRL _SFR_MEM8(0x084E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x08A0) +#define TWI0_DUALCTRL _SFR_MEM8(0x08A1) +#define TWI0_DBGCTRL _SFR_MEM8(0x08A2) +#define TWI0_MCTRLA _SFR_MEM8(0x08A3) +#define TWI0_MCTRLB _SFR_MEM8(0x08A4) +#define TWI0_MSTATUS _SFR_MEM8(0x08A5) +#define TWI0_MBAUD _SFR_MEM8(0x08A6) +#define TWI0_MADDR _SFR_MEM8(0x08A7) +#define TWI0_MDATA _SFR_MEM8(0x08A8) +#define TWI0_SCTRLA _SFR_MEM8(0x08A9) +#define TWI0_SCTRLB _SFR_MEM8(0x08AA) +#define TWI0_SSTATUS _SFR_MEM8(0x08AB) +#define TWI0_SADDR _SFR_MEM8(0x08AC) +#define TWI0_SDATA _SFR_MEM8(0x08AD) +#define TWI0_SADDRMASK _SFR_MEM8(0x08AE) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x08C0) +#define SPI0_CTRLB _SFR_MEM8(0x08C1) +#define SPI0_INTCTRL _SFR_MEM8(0x08C2) +#define SPI0_INTFLAGS _SFR_MEM8(0x08C3) +#define SPI0_DATA _SFR_MEM8(0x08C4) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A80) +#define TCB0_CTRLB _SFR_MEM8(0x0A81) +#define TCB0_EVCTRL _SFR_MEM8(0x0A84) +#define TCB0_INTCTRL _SFR_MEM8(0x0A85) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A86) +#define TCB0_STATUS _SFR_MEM8(0x0A87) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A88) +#define TCB0_TEMP _SFR_MEM8(0x0A89) +#define TCB0_CNT _SFR_MEM16(0x0A8A) +#define TCB0_CNTL _SFR_MEM8(0x0A8A) +#define TCB0_CNTH _SFR_MEM8(0x0A8B) +#define TCB0_CCMP _SFR_MEM16(0x0A8C) +#define TCB0_CCMPL _SFR_MEM8(0x0A8C) +#define TCB0_CCMPH _SFR_MEM8(0x0A8D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0A90) +#define TCB1_CTRLB _SFR_MEM8(0x0A91) +#define TCB1_EVCTRL _SFR_MEM8(0x0A94) +#define TCB1_INTCTRL _SFR_MEM8(0x0A95) +#define TCB1_INTFLAGS _SFR_MEM8(0x0A96) +#define TCB1_STATUS _SFR_MEM8(0x0A97) +#define TCB1_DBGCTRL _SFR_MEM8(0x0A98) +#define TCB1_TEMP _SFR_MEM8(0x0A99) +#define TCB1_CNT _SFR_MEM16(0x0A9A) +#define TCB1_CNTL _SFR_MEM8(0x0A9A) +#define TCB1_CNTH _SFR_MEM8(0x0A9B) +#define TCB1_CCMP _SFR_MEM16(0x0A9C) +#define TCB1_CCMPL _SFR_MEM8(0x0A9C) +#define TCB1_CCMPH _SFR_MEM8(0x0A9D) + + +/* TCB (TCB2) - 16-bit Timer Type B */ +#define TCB2_CTRLA _SFR_MEM8(0x0AA0) +#define TCB2_CTRLB _SFR_MEM8(0x0AA1) +#define TCB2_EVCTRL _SFR_MEM8(0x0AA4) +#define TCB2_INTCTRL _SFR_MEM8(0x0AA5) +#define TCB2_INTFLAGS _SFR_MEM8(0x0AA6) +#define TCB2_STATUS _SFR_MEM8(0x0AA7) +#define TCB2_DBGCTRL _SFR_MEM8(0x0AA8) +#define TCB2_TEMP _SFR_MEM8(0x0AA9) +#define TCB2_CNT _SFR_MEM16(0x0AAA) +#define TCB2_CNTL _SFR_MEM8(0x0AAA) +#define TCB2_CNTH _SFR_MEM8(0x0AAB) +#define TCB2_CCMP _SFR_MEM16(0x0AAC) +#define TCB2_CCMPL _SFR_MEM8(0x0AAC) +#define TCB2_CCMPH _SFR_MEM8(0x0AAD) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) +#define SYSCFG_OCDM _SFR_MEM8(0x0F18) +#define SYSCFG_OCDMS _SFR_MEM8(0x0F19) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_OSCCAL32K _SFR_MEM8(0x1114) +#define SIGROW_OSCCAL16M0 _SFR_MEM8(0x1118) +#define SIGROW_OSCCAL16M1 _SFR_MEM8(0x1119) +#define SIGROW_OSCCAL20M0 _SFR_MEM8(0x111A) +#define SIGROW_OSCCAL20M1 _SFR_MEM8(0x111B) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) +#define SIGROW_CHECKSUM1 _SFR_MEM8(0x112F) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) +#define USERROW_USERROW32 _SFR_MEM8(0x1320) +#define USERROW_USERROW33 _SFR_MEM8(0x1321) +#define USERROW_USERROW34 _SFR_MEM8(0x1322) +#define USERROW_USERROW35 _SFR_MEM8(0x1323) +#define USERROW_USERROW36 _SFR_MEM8(0x1324) +#define USERROW_USERROW37 _SFR_MEM8(0x1325) +#define USERROW_USERROW38 _SFR_MEM8(0x1326) +#define USERROW_USERROW39 _SFR_MEM8(0x1327) +#define USERROW_USERROW40 _SFR_MEM8(0x1328) +#define USERROW_USERROW41 _SFR_MEM8(0x1329) +#define USERROW_USERROW42 _SFR_MEM8(0x132A) +#define USERROW_USERROW43 _SFR_MEM8(0x132B) +#define USERROW_USERROW44 _SFR_MEM8(0x132C) +#define USERROW_USERROW45 _SFR_MEM8(0x132D) +#define USERROW_USERROW46 _SFR_MEM8(0x132E) +#define USERROW_USERROW47 _SFR_MEM8(0x132F) +#define USERROW_USERROW48 _SFR_MEM8(0x1330) +#define USERROW_USERROW49 _SFR_MEM8(0x1331) +#define USERROW_USERROW50 _SFR_MEM8(0x1332) +#define USERROW_USERROW51 _SFR_MEM8(0x1333) +#define USERROW_USERROW52 _SFR_MEM8(0x1334) +#define USERROW_USERROW53 _SFR_MEM8(0x1335) +#define USERROW_USERROW54 _SFR_MEM8(0x1336) +#define USERROW_USERROW55 _SFR_MEM8(0x1337) +#define USERROW_USERROW56 _SFR_MEM8(0x1338) +#define USERROW_USERROW57 _SFR_MEM8(0x1339) +#define USERROW_USERROW58 _SFR_MEM8(0x133A) +#define USERROW_USERROW59 _SFR_MEM8(0x133B) +#define USERROW_USERROW60 _SFR_MEM8(0x133C) +#define USERROW_USERROW61 _SFR_MEM8(0x133D) +#define USERROW_USERROW62 _SFR_MEM8(0x133E) +#define USERROW_USERROW63 _SFR_MEM8(0x133F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.DACREF bit masks and bit positions */ +#define AC_DATA_gm 0xFF /* DAC voltage reference group mask. */ +#define AC_DATA_gp 0 /* DAC voltage reference group position. */ +#define AC_DATA0_bm (1<<0) /* DAC voltage reference bit 0 mask. */ +#define AC_DATA0_bp 0 /* DAC voltage reference bit 0 position. */ +#define AC_DATA1_bm (1<<1) /* DAC voltage reference bit 1 mask. */ +#define AC_DATA1_bp 1 /* DAC voltage reference bit 1 position. */ +#define AC_DATA2_bm (1<<2) /* DAC voltage reference bit 2 mask. */ +#define AC_DATA2_bp 2 /* DAC voltage reference bit 2 position. */ +#define AC_DATA3_bm (1<<3) /* DAC voltage reference bit 3 mask. */ +#define AC_DATA3_bp 3 /* DAC voltage reference bit 3 position. */ +#define AC_DATA4_bm (1<<4) /* DAC voltage reference bit 4 mask. */ +#define AC_DATA4_bp 4 /* DAC voltage reference bit 4 position. */ +#define AC_DATA5_bm (1<<5) /* DAC voltage reference bit 5 mask. */ +#define AC_DATA5_bp 5 /* DAC voltage reference bit 5 position. */ +#define AC_DATA6_bm (1<<6) /* DAC voltage reference bit 6 mask. */ +#define AC_DATA6_bp 6 /* DAC voltage reference bit 6 position. */ +#define AC_DATA7_bm (1<<7) /* DAC voltage reference bit 7 mask. */ +#define AC_DATA7_bp 7 /* DAC voltage reference bit 7 position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL0_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL0_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL00_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL00_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL01_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL01_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL02_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL02_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.SEQCTRL1 bit masks and bit positions */ +#define CCL_SEQSEL1_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL1_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL10_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL10_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL11_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL11_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL12_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL12_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.INTCTRL0 bit masks and bit positions */ +#define CCL_INTMODE0_gm 0x03 /* Interrupt Mode for LUT0 group mask. */ +#define CCL_INTMODE0_gp 0 /* Interrupt Mode for LUT0 group position. */ +#define CCL_INTMODE00_bm (1<<0) /* Interrupt Mode for LUT0 bit 0 mask. */ +#define CCL_INTMODE00_bp 0 /* Interrupt Mode for LUT0 bit 0 position. */ +#define CCL_INTMODE01_bm (1<<1) /* Interrupt Mode for LUT0 bit 1 mask. */ +#define CCL_INTMODE01_bp 1 /* Interrupt Mode for LUT0 bit 1 position. */ +#define CCL_INTMODE1_gm 0x0C /* Interrupt Mode for LUT1 group mask. */ +#define CCL_INTMODE1_gp 2 /* Interrupt Mode for LUT1 group position. */ +#define CCL_INTMODE10_bm (1<<2) /* Interrupt Mode for LUT1 bit 0 mask. */ +#define CCL_INTMODE10_bp 2 /* Interrupt Mode for LUT1 bit 0 position. */ +#define CCL_INTMODE11_bm (1<<3) /* Interrupt Mode for LUT1 bit 1 mask. */ +#define CCL_INTMODE11_bp 3 /* Interrupt Mode for LUT1 bit 1 position. */ +#define CCL_INTMODE2_gm 0x30 /* Interrupt Mode for LUT2 group mask. */ +#define CCL_INTMODE2_gp 4 /* Interrupt Mode for LUT2 group position. */ +#define CCL_INTMODE20_bm (1<<4) /* Interrupt Mode for LUT2 bit 0 mask. */ +#define CCL_INTMODE20_bp 4 /* Interrupt Mode for LUT2 bit 0 position. */ +#define CCL_INTMODE21_bm (1<<5) /* Interrupt Mode for LUT2 bit 1 mask. */ +#define CCL_INTMODE21_bp 5 /* Interrupt Mode for LUT2 bit 1 position. */ +#define CCL_INTMODE3_gm 0xC0 /* Interrupt Mode for LUT3 group mask. */ +#define CCL_INTMODE3_gp 6 /* Interrupt Mode for LUT3 group position. */ +#define CCL_INTMODE30_bm (1<<6) /* Interrupt Mode for LUT3 bit 0 mask. */ +#define CCL_INTMODE30_bp 6 /* Interrupt Mode for LUT3 bit 0 position. */ +#define CCL_INTMODE31_bm (1<<7) /* Interrupt Mode for LUT3 bit 1 mask. */ +#define CCL_INTMODE31_bp 7 /* Interrupt Mode for LUT3 bit 1 position. */ + +/* CCL.INTFLAGS bit masks and bit positions */ +#define CCL_INT_gm 0x0F /* Interrupt Flags group mask. */ +#define CCL_INT_gp 0 /* Interrupt Flags group position. */ +#define CCL_INT0_bm (1<<0) /* Interrupt Flags bit 0 mask. */ +#define CCL_INT0_bp 0 /* Interrupt Flags bit 0 position. */ +#define CCL_INT1_bm (1<<1) /* Interrupt Flags bit 1 mask. */ +#define CCL_INT1_bp 1 /* Interrupt Flags bit 1 position. */ +#define CCL_INT2_bm (1<<2) /* Interrupt Flags bit 2 mask. */ +#define CCL_INT2_bp 2 /* Interrupt Flags bit 2 position. */ +#define CCL_INT3_bm (1<<3) /* Interrupt Flags bit 3 mask. */ +#define CCL_INT3_bp 3 /* Interrupt Flags bit 3 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_CLKSRC_gm 0x0E /* Clock Source Selection group mask. */ +#define CCL_CLKSRC_gp 1 /* Clock Source Selection group position. */ +#define CCL_CLKSRC0_bm (1<<1) /* Clock Source Selection bit 0 mask. */ +#define CCL_CLKSRC0_bp 1 /* Clock Source Selection bit 0 position. */ +#define CCL_CLKSRC1_bm (1<<2) /* Clock Source Selection bit 1 mask. */ +#define CCL_CLKSRC1_bp 2 /* Clock Source Selection bit 1 position. */ +#define CCL_CLKSRC2_bm (1<<3) /* Clock Source Selection bit 2 mask. */ +#define CCL_CLKSRC2_bp 3 /* Clock Source Selection bit 2 position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_OUTEN_bm 0x40 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 6 /* Output Enable bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT2CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT2CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT2CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT3CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT3CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT3CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x7F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ +#define CLKCTRL_CAL20M6_bm (1<<6) /* Calibration bit 6 mask. */ +#define CLKCTRL_CAL20M6_bp 6 /* Calibration bit 6 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.STROBE bit masks and bit positions */ +#define EVSYS_STROBE0_gm 0xFF /* Software event on channels group mask. */ +#define EVSYS_STROBE0_gp 0 /* Software event on channels group position. */ +#define EVSYS_STROBE00_bm (1<<0) /* Software event on channels bit 0 mask. */ +#define EVSYS_STROBE00_bp 0 /* Software event on channels bit 0 position. */ +#define EVSYS_STROBE01_bm (1<<1) /* Software event on channels bit 1 mask. */ +#define EVSYS_STROBE01_bp 1 /* Software event on channels bit 1 position. */ +#define EVSYS_STROBE02_bm (1<<2) /* Software event on channels bit 2 mask. */ +#define EVSYS_STROBE02_bp 2 /* Software event on channels bit 2 position. */ +#define EVSYS_STROBE03_bm (1<<3) /* Software event on channels bit 3 mask. */ +#define EVSYS_STROBE03_bp 3 /* Software event on channels bit 3 position. */ +#define EVSYS_STROBE04_bm (1<<4) /* Software event on channels bit 4 mask. */ +#define EVSYS_STROBE04_bp 4 /* Software event on channels bit 4 position. */ +#define EVSYS_STROBE05_bm (1<<5) /* Software event on channels bit 5 mask. */ +#define EVSYS_STROBE05_bp 5 /* Software event on channels bit 5 position. */ +#define EVSYS_STROBE06_bm (1<<6) /* Software event on channels bit 6 mask. */ +#define EVSYS_STROBE06_bp 6 /* Software event on channels bit 6 position. */ +#define EVSYS_STROBE07_bm (1<<7) /* Software event on channels bit 7 mask. */ +#define EVSYS_STROBE07_bp 7 /* Software event on channels bit 7 position. */ + +/* EVSYS.CHANNEL0 bit masks and bit positions */ +#define EVSYS_GENERATOR_gm 0xFF /* Generator selector group mask. */ +#define EVSYS_GENERATOR_gp 0 /* Generator selector group position. */ +#define EVSYS_GENERATOR0_bm (1<<0) /* Generator selector bit 0 mask. */ +#define EVSYS_GENERATOR0_bp 0 /* Generator selector bit 0 position. */ +#define EVSYS_GENERATOR1_bm (1<<1) /* Generator selector bit 1 mask. */ +#define EVSYS_GENERATOR1_bp 1 /* Generator selector bit 1 position. */ +#define EVSYS_GENERATOR2_bm (1<<2) /* Generator selector bit 2 mask. */ +#define EVSYS_GENERATOR2_bp 2 /* Generator selector bit 2 position. */ +#define EVSYS_GENERATOR3_bm (1<<3) /* Generator selector bit 3 mask. */ +#define EVSYS_GENERATOR3_bp 3 /* Generator selector bit 3 position. */ +#define EVSYS_GENERATOR4_bm (1<<4) /* Generator selector bit 4 mask. */ +#define EVSYS_GENERATOR4_bp 4 /* Generator selector bit 4 position. */ +#define EVSYS_GENERATOR5_bm (1<<5) /* Generator selector bit 5 mask. */ +#define EVSYS_GENERATOR5_bp 5 /* Generator selector bit 5 position. */ +#define EVSYS_GENERATOR6_bm (1<<6) /* Generator selector bit 6 mask. */ +#define EVSYS_GENERATOR6_bp 6 /* Generator selector bit 6 position. */ +#define EVSYS_GENERATOR7_bm (1<<7) /* Generator selector bit 7 mask. */ +#define EVSYS_GENERATOR7_bp 7 /* Generator selector bit 7 position. */ + +/* EVSYS.CHANNEL1 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL2 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL3 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL4 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL5 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.USERCCLLUT0A bit masks and bit positions */ +#define EVSYS_CHANNEL_gm 0xFF /* Channel selector group mask. */ +#define EVSYS_CHANNEL_gp 0 /* Channel selector group position. */ +#define EVSYS_CHANNEL0_bm (1<<0) /* Channel selector bit 0 mask. */ +#define EVSYS_CHANNEL0_bp 0 /* Channel selector bit 0 position. */ +#define EVSYS_CHANNEL1_bm (1<<1) /* Channel selector bit 1 mask. */ +#define EVSYS_CHANNEL1_bp 1 /* Channel selector bit 1 position. */ +#define EVSYS_CHANNEL2_bm (1<<2) /* Channel selector bit 2 mask. */ +#define EVSYS_CHANNEL2_bp 2 /* Channel selector bit 2 position. */ +#define EVSYS_CHANNEL3_bm (1<<3) /* Channel selector bit 3 mask. */ +#define EVSYS_CHANNEL3_bp 3 /* Channel selector bit 3 position. */ +#define EVSYS_CHANNEL4_bm (1<<4) /* Channel selector bit 4 mask. */ +#define EVSYS_CHANNEL4_bp 4 /* Channel selector bit 4 position. */ +#define EVSYS_CHANNEL5_bm (1<<5) /* Channel selector bit 5 mask. */ +#define EVSYS_CHANNEL5_bp 5 /* Channel selector bit 5 position. */ +#define EVSYS_CHANNEL6_bm (1<<6) /* Channel selector bit 6 mask. */ +#define EVSYS_CHANNEL6_bp 6 /* Channel selector bit 6 position. */ +#define EVSYS_CHANNEL7_bm (1<<7) /* Channel selector bit 7 mask. */ +#define EVSYS_CHANNEL7_bp 7 /* Channel selector bit 7 position. */ + +/* EVSYS.USERCCLLUT0B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT1A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT1B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT2A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT2B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT3A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT3B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERADC0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTA bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTB bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTC bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTD bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTE bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTF bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART1 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART2 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART3 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCA0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB1 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB2 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB3 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_bm 0x08 /* Reset Pin Configuration bit mask. */ +#define FUSE_RSTPINCFG_bp 3 /* Reset Pin Configuration bit position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PORTCTRL bit masks and bit positions */ +#define PORT_SRL_bm 0x01 /* Slew Rate Limit Enable bit mask. */ +#define PORT_SRL_bp 0 /* Slew Rate Limit Enable bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.EVSYSROUTEA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_EVOUT3_bm 0x08 /* Event Output 3 bit mask. */ +#define PORTMUX_EVOUT3_bp 3 /* Event Output 3 bit position. */ +#define PORTMUX_EVOUT4_bm 0x10 /* Event Output 4 bit mask. */ +#define PORTMUX_EVOUT4_bp 4 /* Event Output 4 bit position. */ +#define PORTMUX_EVOUT5_bm 0x20 /* Event Output 5 bit mask. */ +#define PORTMUX_EVOUT5_bp 5 /* Event Output 5 bit position. */ + +/* PORTMUX.CCLROUTEA bit masks and bit positions */ +#define PORTMUX_LUT0_bm 0x01 /* CCL LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 0 /* CCL LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x02 /* CCL LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 1 /* CCL LUT1 bit position. */ +#define PORTMUX_LUT2_bm 0x04 /* CCL LUT2 bit mask. */ +#define PORTMUX_LUT2_bp 2 /* CCL LUT2 bit position. */ +#define PORTMUX_LUT3_bm 0x08 /* CCL LUT3 bit mask. */ +#define PORTMUX_LUT3_bp 3 /* CCL LUT3 bit position. */ + +/* PORTMUX.USARTROUTEA bit masks and bit positions */ +#define PORTMUX_USART0_gm 0x03 /* Port Multiplexer USART0 group mask. */ +#define PORTMUX_USART0_gp 0 /* Port Multiplexer USART0 group position. */ +#define PORTMUX_USART00_bm (1<<0) /* Port Multiplexer USART0 bit 0 mask. */ +#define PORTMUX_USART00_bp 0 /* Port Multiplexer USART0 bit 0 position. */ +#define PORTMUX_USART01_bm (1<<1) /* Port Multiplexer USART0 bit 1 mask. */ +#define PORTMUX_USART01_bp 1 /* Port Multiplexer USART0 bit 1 position. */ +#define PORTMUX_USART1_gm 0x0C /* Port Multiplexer USART1 group mask. */ +#define PORTMUX_USART1_gp 2 /* Port Multiplexer USART1 group position. */ +#define PORTMUX_USART10_bm (1<<2) /* Port Multiplexer USART1 bit 0 mask. */ +#define PORTMUX_USART10_bp 2 /* Port Multiplexer USART1 bit 0 position. */ +#define PORTMUX_USART11_bm (1<<3) /* Port Multiplexer USART1 bit 1 mask. */ +#define PORTMUX_USART11_bp 3 /* Port Multiplexer USART1 bit 1 position. */ +#define PORTMUX_USART2_gm 0x30 /* Port Multiplexer USART2 group mask. */ +#define PORTMUX_USART2_gp 4 /* Port Multiplexer USART2 group position. */ +#define PORTMUX_USART20_bm (1<<4) /* Port Multiplexer USART2 bit 0 mask. */ +#define PORTMUX_USART20_bp 4 /* Port Multiplexer USART2 bit 0 position. */ +#define PORTMUX_USART21_bm (1<<5) /* Port Multiplexer USART2 bit 1 mask. */ +#define PORTMUX_USART21_bp 5 /* Port Multiplexer USART2 bit 1 position. */ +#define PORTMUX_USART3_gm 0xC0 /* Port Multiplexer USART3 group mask. */ +#define PORTMUX_USART3_gp 6 /* Port Multiplexer USART3 group position. */ +#define PORTMUX_USART30_bm (1<<6) /* Port Multiplexer USART3 bit 0 mask. */ +#define PORTMUX_USART30_bp 6 /* Port Multiplexer USART3 bit 0 position. */ +#define PORTMUX_USART31_bm (1<<7) /* Port Multiplexer USART3 bit 1 mask. */ +#define PORTMUX_USART31_bp 7 /* Port Multiplexer USART3 bit 1 position. */ + +/* PORTMUX.TWISPIROUTEA bit masks and bit positions */ +#define PORTMUX_SPI0_gm 0x03 /* Port Multiplexer SPI0 group mask. */ +#define PORTMUX_SPI0_gp 0 /* Port Multiplexer SPI0 group position. */ +#define PORTMUX_SPI00_bm (1<<0) /* Port Multiplexer SPI0 bit 0 mask. */ +#define PORTMUX_SPI00_bp 0 /* Port Multiplexer SPI0 bit 0 position. */ +#define PORTMUX_SPI01_bm (1<<1) /* Port Multiplexer SPI0 bit 1 mask. */ +#define PORTMUX_SPI01_bp 1 /* Port Multiplexer SPI0 bit 1 position. */ +#define PORTMUX_TWI0_gm 0x30 /* Port Multiplexer TWI0 group mask. */ +#define PORTMUX_TWI0_gp 4 /* Port Multiplexer TWI0 group position. */ +#define PORTMUX_TWI00_bm (1<<4) /* Port Multiplexer TWI0 bit 0 mask. */ +#define PORTMUX_TWI00_bp 4 /* Port Multiplexer TWI0 bit 0 position. */ +#define PORTMUX_TWI01_bm (1<<5) /* Port Multiplexer TWI0 bit 1 mask. */ +#define PORTMUX_TWI01_bp 5 /* Port Multiplexer TWI0 bit 1 position. */ + +/* PORTMUX.TCAROUTEA bit masks and bit positions */ +#define PORTMUX_TCA0_gm 0x07 /* Port Multiplexer TCA0 group mask. */ +#define PORTMUX_TCA0_gp 0 /* Port Multiplexer TCA0 group position. */ +#define PORTMUX_TCA00_bm (1<<0) /* Port Multiplexer TCA0 bit 0 mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 bit 0 position. */ +#define PORTMUX_TCA01_bm (1<<1) /* Port Multiplexer TCA0 bit 1 mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 bit 1 position. */ +#define PORTMUX_TCA02_bm (1<<2) /* Port Multiplexer TCA0 bit 2 mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 bit 2 position. */ + +/* PORTMUX.TCBROUTEA bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ +#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ +#define PORTMUX_TCB2_bm 0x04 /* Port Multiplexer TCB2 bit mask. */ +#define PORTMUX_TCB2_bp 2 /* Port Multiplexer TCB2 bit position. */ +#define PORTMUX_TCB3_bm 0x08 /* Port Multiplexer TCB3 bit mask. */ +#define PORTMUX_TCB3_bp 3 /* Port Multiplexer TCB3 bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_CORREN_bm 0x04 /* Correction enable bit mask. */ +#define RTC_CORREN_bp 2 /* Correction enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_ERROR_gm 0x7F /* Error Correction Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Correction Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Correction Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Correction Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Correction Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Correction Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Correction Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Correction Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Correction Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Correction Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Correction Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Correction Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Correction Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Correction Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Correction Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Correction Value bit 6 position. */ +#define RTC_SIGN_bm 0x80 /* Error Correction Sign Bit bit mask. */ +#define RTC_SIGN_bp 7 /* Error Correction Sign Bit bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + + +/* SYSCFG.OCDMS bit masks and bit positions */ +#define SYSCFG_OCDMR_bm 0x01 /* OCD Message Read bit mask. */ +#define SYSCFG_OCDMR_bp 0 /* OCD Message Read bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DUALCTRL bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Dual Control Enable bit mask. */ +#define TWI_ENABLE_bp 0 /* Dual Control Enable bit position. */ +/* TWI_FMPEN is already defined. */ +/* TWI_SDAHOLD is already defined. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.CTRLD bit masks and bit positions */ +#define USART_ABW_gm 0xC0 /* Auto Baud Window group mask. */ +#define USART_ABW_gp 6 /* Auto Baud Window group position. */ +#define USART_ABW0_bm (1<<6) /* Auto Baud Window bit 0 mask. */ +#define USART_ABW0_bp 6 /* Auto Baud Window bit 0 position. */ +#define USART_ABW1_bm (1<<7) /* Auto Baud Window bit 1 mask. */ +#define USART_ABW1_bp 7 /* Auto Baud Window bit 1 position. */ + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_AC0REFSEL_gm 0x07 /* AC0 reference select group mask. */ +#define VREF_AC0REFSEL_gp 0 /* AC0 reference select group position. */ +#define VREF_AC0REFSEL0_bm (1<<0) /* AC0 reference select bit 0 mask. */ +#define VREF_AC0REFSEL0_bp 0 /* AC0 reference select bit 0 position. */ +#define VREF_AC0REFSEL1_bm (1<<1) /* AC0 reference select bit 1 mask. */ +#define VREF_AC0REFSEL1_bp 1 /* AC0 reference select bit 1 position. */ +#define VREF_AC0REFSEL2_bm (1<<2) /* AC0 reference select bit 2 mask. */ +#define VREF_AC0REFSEL2_bp 2 /* AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_AC0REFEN_bm 0x01 /* AC0 DACREF reference enable bit mask. */ +#define VREF_AC0REFEN_bp 0 /* AC0 DACREF reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 3 +#define RTC_CNT_vect _VECTOR(3) /* */ +#define RTC_PIT_vect_num 4 +#define RTC_PIT_vect _VECTOR(4) /* */ + +/* CCL interrupt vectors */ +#define CCL_CCL_vect_num 5 +#define CCL_CCL_vect _VECTOR(5) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 6 +#define PORTA_PORT_vect _VECTOR(6) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 7 +#define TCA0_LUNF_vect _VECTOR(7) /* */ +#define TCA0_OVF_vect_num 7 +#define TCA0_OVF_vect _VECTOR(7) /* */ +#define TCA0_HUNF_vect_num 8 +#define TCA0_HUNF_vect _VECTOR(8) /* */ +#define TCA0_CMP0_vect_num 9 +#define TCA0_CMP0_vect _VECTOR(9) /* */ +#define TCA0_LCMP0_vect_num 9 +#define TCA0_LCMP0_vect _VECTOR(9) /* */ +#define TCA0_CMP1_vect_num 10 +#define TCA0_CMP1_vect _VECTOR(10) /* */ +#define TCA0_LCMP1_vect_num 10 +#define TCA0_LCMP1_vect _VECTOR(10) /* */ +#define TCA0_CMP2_vect_num 11 +#define TCA0_CMP2_vect _VECTOR(11) /* */ +#define TCA0_LCMP2_vect_num 11 +#define TCA0_LCMP2_vect _VECTOR(11) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 12 +#define TCB0_INT_vect _VECTOR(12) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 13 +#define TCB1_INT_vect _VECTOR(13) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 14 +#define TWI0_TWIS_vect _VECTOR(14) /* */ +#define TWI0_TWIM_vect_num 15 +#define TWI0_TWIM_vect _VECTOR(15) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 16 +#define SPI0_INT_vect _VECTOR(16) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 17 +#define USART0_RXC_vect _VECTOR(17) /* */ +#define USART0_DRE_vect_num 18 +#define USART0_DRE_vect _VECTOR(18) /* */ +#define USART0_TXC_vect_num 19 +#define USART0_TXC_vect _VECTOR(19) /* */ + +/* PORTD interrupt vectors */ +#define PORTD_PORT_vect_num 20 +#define PORTD_PORT_vect _VECTOR(20) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 21 +#define AC0_AC_vect _VECTOR(21) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 22 +#define ADC0_RESRDY_vect _VECTOR(22) /* */ +#define ADC0_WCOMP_vect_num 23 +#define ADC0_WCOMP_vect _VECTOR(23) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 24 +#define PORTC_PORT_vect _VECTOR(24) /* */ + +/* TCB2 interrupt vectors */ +#define TCB2_INT_vect_num 25 +#define TCB2_INT_vect _VECTOR(25) /* */ + +/* USART1 interrupt vectors */ +#define USART1_RXC_vect_num 26 +#define USART1_RXC_vect _VECTOR(26) /* */ +#define USART1_DRE_vect_num 27 +#define USART1_DRE_vect _VECTOR(27) /* */ +#define USART1_TXC_vect_num 28 +#define USART1_TXC_vect _VECTOR(28) /* */ + +/* PORTF interrupt vectors */ +#define PORTF_PORT_vect_num 29 +#define PORTF_PORT_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +/* USART2 interrupt vectors */ +#define USART2_RXC_vect_num 31 +#define USART2_RXC_vect _VECTOR(31) /* */ +#define USART2_DRE_vect_num 32 +#define USART2_DRE_vect _VECTOR(32) /* */ +#define USART2_TXC_vect_num 33 +#define USART2_TXC_vect _VECTOR(33) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 34 +#define PORTB_PORT_vect _VECTOR(34) /* */ + +/* PORTE interrupt vectors */ +#define PORTE_PORT_vect_num 35 +#define PORTE_PORT_vect _VECTOR(35) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (36 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (65536) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (65536U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (64) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (64U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (64) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (64U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x2800) +# define INTERNAL_SRAM_SIZE (6144) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x2800U) +# define INTERNAL_SRAM_SIZE (6144U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (64) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (64U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x4000) +# define MAPPED_PROGMEM_SIZE (49152) +# define MAPPED_PROGMEM_PAGE_SIZE (128) +#else +# define MAPPED_PROGMEM_START (0x4000U) +# define MAPPED_PROGMEM_SIZE (49152U) +# define MAPPED_PROGMEM_PAGE_SIZE (128U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (125) +# define PROD_SIGNATURES_PAGE_SIZE (128) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (125U) +# define PROD_SIGNATURES_PAGE_SIZE (128U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (128) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (128U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (64) +# define USER_SIGNATURES_PAGE_SIZE (64) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (64U) +# define USER_SIGNATURES_PAGE_SIZE (64U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (49152) +# define PROGMEM_PAGE_SIZE (128) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (49152U) +# define PROGMEM_PAGE_SIZE (128U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG (unsigned char)_BV(3) /* Reset Pin Configuration */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x50 + + +#endif /* #ifdef _AVR_ATMEGA4808_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iom4809.h b/hardware/tools/avr/avr/include/avr/iom4809.h new file mode 100644 index 0000000000000000000000000000000000000000..93e8d88db563d7ba2c7950cb91788534470b2e55 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom4809.h @@ -0,0 +1,5017 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom4809.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATMEGA4809_H_INCLUDED +#define _AVR_ATMEGA4809_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[1]; + register8_t DACREF; /* Referance scale control */ + register8_t reserved_3[1]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_PIN2_gc = (0x02<<0), /* Negative Pin 2 */ + AC_MUXNEG_DACREF_gc = (0x03<<0), /* DAC Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ + ADC_MUXPOS_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ + ADC_MUXPOS_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ + ADC_MUXPOS_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ + ADC_MUXPOS_DACREF_gc = (0x1C<<0), /* AC DAC Reference */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temperature sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* 0V (GND) */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t SEQCTRL1; /* Sequential Control 1 */ + register8_t reserved_1[2]; + register8_t INTCTRL0; /* Interrupt Control 0 */ + register8_t reserved_2[1]; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t LUT2CTRLA; /* LUT Control 2 A */ + register8_t LUT2CTRLB; /* LUT Control 2 B */ + register8_t LUT2CTRLC; /* LUT Control 2 C */ + register8_t TRUTH2; /* Truth 2 */ + register8_t LUT3CTRLA; /* LUT Control 3 A */ + register8_t LUT3CTRLB; /* LUT Control 3 B */ + register8_t LUT3CTRLC; /* LUT Control 3 C */ + register8_t TRUTH3; /* Truth 3 */ + register8_t reserved_3[40]; +} CCL_t; + +/* Clock Source Selection select */ +typedef enum CCL_CLKSRC_enum +{ + CCL_CLKSRC_CLKPER_gc = (0x00<<1), /* CLK_PER is clocking the LUT */ + CCL_CLKSRC_IN2_gc = (0x01<<1), /* IN[2] is clocking the LUT */ + CCL_CLKSRC_OSC20M_gc = (0x04<<1), /* 20MHz oscillator before prescaler is clocking the LUT */ + CCL_CLKSRC_OSCULP32K_gc = (0x05<<1), /* 32kHz oscillator is clocking the LUT */ + CCL_CLKSRC_OSCULP1K_gc = (0x06<<1), /* 32kHz oscillator after DIV32 is clocking the LUT */ +} CCL_CLKSRC_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL0_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_USART0_gc = (0x08<<0), /* USART0 TXD input source */ + CCL_INSEL0_SPI0_gc = (0x09<<0), /* SPI0 MOSI input source */ + CCL_INSEL0_TCA0_gc = (0x0A<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCB0_gc = (0x0C<<0), /* TCB0 WO input source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENTA_gc = (0x03<<4), /* Event input source A */ + CCL_INSEL1_EVENTB_gc = (0x04<<4), /* Event input source B */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_USART1_gc = (0x08<<4), /* USART1 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x09<<4), /* SPI0 MOSI input source */ + CCL_INSEL1_TCA0_gc = (0x0A<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCB1_gc = (0x0C<<4), /* TCB1 WO input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL2_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_USART2_gc = (0x08<<0), /* USART2 TXD input source */ + CCL_INSEL2_SPI0_gc = (0x09<<0), /* SPI0 SCK input source */ + CCL_INSEL2_TCA0_gc = (0x0A<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCB2_gc = (0x0C<<0), /* TCB2 WO input source */ +} CCL_INSEL2_t; + +/* Interrupt Mode for LUT0 select */ +typedef enum CCL_INTMODE0_enum +{ + CCL_INTMODE0_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled */ + CCL_INTMODE0_RISING_gc = (0x01<<0), /* Sense rising edge */ + CCL_INTMODE0_FALLING_gc = (0x02<<0), /* Sense falling edge */ + CCL_INTMODE0_BOTH_gc = (0x03<<0), /* Sense both edges */ +} CCL_INTMODE0_t; + +/* Interrupt Mode for LUT1 select */ +typedef enum CCL_INTMODE1_enum +{ + CCL_INTMODE1_INTDISABLE_gc = (0x00<<2), /* Interrupt disabled */ + CCL_INTMODE1_RISING_gc = (0x01<<2), /* Sense rising edge */ + CCL_INTMODE1_FALLING_gc = (0x02<<2), /* Sense falling edge */ + CCL_INTMODE1_BOTH_gc = (0x03<<2), /* Sense both edges */ +} CCL_INTMODE1_t; + +/* Interrupt Mode for LUT2 select */ +typedef enum CCL_INTMODE2_enum +{ + CCL_INTMODE2_INTDISABLE_gc = (0x00<<4), /* Interrupt disabled */ + CCL_INTMODE2_RISING_gc = (0x01<<4), /* Sense rising edge */ + CCL_INTMODE2_FALLING_gc = (0x02<<4), /* Sense falling edge */ + CCL_INTMODE2_BOTH_gc = (0x03<<4), /* Sense both edges */ +} CCL_INTMODE2_t; + +/* Interrupt Mode for LUT3 select */ +typedef enum CCL_INTMODE3_enum +{ + CCL_INTMODE3_INTDISABLE_gc = (0x00<<6), /* Interrupt disabled */ + CCL_INTMODE3_RISING_gc = (0x01<<6), /* Sense rising edge */ + CCL_INTMODE3_FALLING_gc = (0x02<<6), /* Sense falling edge */ + CCL_INTMODE3_BOTH_gc = (0x03<<6), /* Sense both edges */ +} CCL_INTMODE3_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL0_enum +{ + CCL_SEQSEL0_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL0_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL0_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL0_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL0_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL0_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL1_enum +{ + CCL_SEQSEL1_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL1_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL1_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL1_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL1_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL1_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1k cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16k cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32k cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t STROBE; /* Channel Strobe */ + register8_t reserved_1[15]; + register8_t CHANNEL0; /* Multiplexer Channel 0 */ + register8_t CHANNEL1; /* Multiplexer Channel 1 */ + register8_t CHANNEL2; /* Multiplexer Channel 2 */ + register8_t CHANNEL3; /* Multiplexer Channel 3 */ + register8_t CHANNEL4; /* Multiplexer Channel 4 */ + register8_t CHANNEL5; /* Multiplexer Channel 5 */ + register8_t CHANNEL6; /* Multiplexer Channel 6 */ + register8_t CHANNEL7; /* Multiplexer Channel 7 */ + register8_t reserved_2[8]; + register8_t USERCCLLUT0A; /* User CCL LUT0 Event A */ + register8_t USERCCLLUT0B; /* User CCL LUT0 Event B */ + register8_t USERCCLLUT1A; /* User CCL LUT1 Event A */ + register8_t USERCCLLUT1B; /* User CCL LUT1 Event B */ + register8_t USERCCLLUT2A; /* User CCL LUT2 Event A */ + register8_t USERCCLLUT2B; /* User CCL LUT2 Event B */ + register8_t USERCCLLUT3A; /* User CCL LUT3 Event A */ + register8_t USERCCLLUT3B; /* User CCL LUT3 Event B */ + register8_t USERADC0; /* User ADC0 */ + register8_t USEREVOUTA; /* User EVOUT Port A */ + register8_t USEREVOUTB; /* User EVOUT Port B */ + register8_t USEREVOUTC; /* User EVOUT Port C */ + register8_t USEREVOUTD; /* User EVOUT Port D */ + register8_t USEREVOUTE; /* User EVOUT Port E */ + register8_t USEREVOUTF; /* User EVOUT Port F */ + register8_t USERUSART0; /* User USART0 */ + register8_t USERUSART1; /* User USART1 */ + register8_t USERUSART2; /* User USART2 */ + register8_t USERUSART3; /* User USART3 */ + register8_t USERTCA0; /* User TCA0 */ + register8_t USERTCB0; /* User TCB0 */ + register8_t USERTCB1; /* User TCB1 */ + register8_t USERTCB2; /* User TCB2 */ + register8_t USERTCB3; /* User TCB3 */ + register8_t reserved_3[8]; +} EVSYS_t; + +/* Channel selector select */ +typedef enum EVSYS_CHANNEL_enum +{ + EVSYS_CHANNEL_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL_CHANNEL0_gc = (0x01<<0), /* Connect user to event channel 0 */ + EVSYS_CHANNEL_CHANNEL1_gc = (0x02<<0), /* Connect user to event channel 1 */ + EVSYS_CHANNEL_CHANNEL2_gc = (0x03<<0), /* Connect user to event channel 2 */ + EVSYS_CHANNEL_CHANNEL3_gc = (0x04<<0), /* Connect user to event channel 3 */ + EVSYS_CHANNEL_CHANNEL4_gc = (0x05<<0), /* Connect user to event channel 4 */ + EVSYS_CHANNEL_CHANNEL5_gc = (0x06<<0), /* Connect user to event channel 5 */ + EVSYS_CHANNEL_CHANNEL6_gc = (0x07<<0), /* Connect user to event channel 6 */ + EVSYS_CHANNEL_CHANNEL7_gc = (0x08<<0), /* Connect user to event channel 7 */ +} EVSYS_CHANNEL_t; + +/* Generator selector select */ +typedef enum EVSYS_GENERATOR_enum +{ + EVSYS_GENERATOR_OFF_gc = (0x00<<0), /* Off */ + EVSYS_GENERATOR_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_GENERATOR_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_GENERATOR_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_GENERATOR_RTC_PIT0_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_GENERATOR_RTC_PIT1_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_GENERATOR_RTC_PIT2_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_GENERATOR_RTC_PIT3_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_GENERATOR_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_GENERATOR_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_GENERATOR_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_GENERATOR_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_GENERATOR_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_GENERATOR_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready Event */ + EVSYS_GENERATOR_PORT0_PIN0_gc = (0x40<<0), /* Port 0 Pin 0 */ + EVSYS_GENERATOR_PORT0_PIN1_gc = (0x41<<0), /* Port 0 Pin 1 */ + EVSYS_GENERATOR_PORT0_PIN2_gc = (0x42<<0), /* Port 0 Pin 2 */ + EVSYS_GENERATOR_PORT0_PIN3_gc = (0x43<<0), /* Port 0 Pin 3 */ + EVSYS_GENERATOR_PORT0_PIN4_gc = (0x44<<0), /* Port 0 Pin 4 */ + EVSYS_GENERATOR_PORT0_PIN5_gc = (0x45<<0), /* Port 0 Pin 5 */ + EVSYS_GENERATOR_PORT0_PIN6_gc = (0x46<<0), /* Port 0 Pin 6 */ + EVSYS_GENERATOR_PORT0_PIN7_gc = (0x47<<0), /* Port 0 Pin 7 */ + EVSYS_GENERATOR_PORT1_PIN0_gc = (0x48<<0), /* Port 1 Pin 0 */ + EVSYS_GENERATOR_PORT1_PIN1_gc = (0x49<<0), /* Port 1 Pin 1 */ + EVSYS_GENERATOR_PORT1_PIN2_gc = (0x4A<<0), /* Port 1 Pin 2 */ + EVSYS_GENERATOR_PORT1_PIN3_gc = (0x4B<<0), /* Port 1 Pin 3 */ + EVSYS_GENERATOR_PORT1_PIN4_gc = (0x4C<<0), /* Port 1 Pin 4 */ + EVSYS_GENERATOR_PORT1_PIN5_gc = (0x4D<<0), /* Port 1 Pin 5 */ + EVSYS_GENERATOR_PORT1_PIN6_gc = (0x4E<<0), /* Port 1 Pin 6 */ + EVSYS_GENERATOR_PORT1_PIN7_gc = (0x4F<<0), /* Port 1 Pin 7 */ + EVSYS_GENERATOR_USART0_XCK_gc = (0x60<<0), /* USART 0 Xclock */ + EVSYS_GENERATOR_USART1_XCK_gc = (0x61<<0), /* USART 1 Xclock */ + EVSYS_GENERATOR_USART2_XCK_gc = (0x62<<0), /* USART 2 Xclock */ + EVSYS_GENERATOR_USART3_XCK_gc = (0x63<<0), /* USART 3 Xclock */ + EVSYS_GENERATOR_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_GENERATOR_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_GENERATOR_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow (split mode) */ + EVSYS_GENERATOR_TCA0_CMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_GENERATOR_TCA0_CMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_GENERATOR_TCA0_CMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_GENERATOR_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_GENERATOR_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_GENERATOR_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_GENERATOR_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ +} EVSYS_GENERATOR_t; + +/* Software event on channels select */ +typedef enum EVSYS_STROBE0_enum +{ + EVSYS_STROBE0_EV_STROBE_CH0_gc = (0x01<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH1_gc = (0x02<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH2_gc = (0x04<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH3_gc = (0x08<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH4_gc = (0x10<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH5_gc = (0x20<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH6_gc = (0x40<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH7_gc = (0x80<<0), /* */ +} EVSYS_STROBE0_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<3), /* GPIO mode */ + RSTPINCFG_RST_gc = (0x01<<3), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock Bits */ + register8_t reserved_1[1]; +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t PORTCTRL; /* Port Control */ + register8_t reserved_1[5]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t EVSYSROUTEA; /* Port Multiplexer EVSYS */ + register8_t CCLROUTEA; /* Port Multiplexer CCL */ + register8_t USARTROUTEA; /* Port Multiplexer USART register A */ + register8_t TWISPIROUTEA; /* Port Multiplexer TWI and SPI */ + register8_t TCAROUTEA; /* Port Multiplexer TCA */ + register8_t TCBROUTEA; /* Port Multiplexer TCB */ + register8_t reserved_1[10]; +} PORTMUX_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<0), /* SPI0 on PA[7:4] */ + PORTMUX_SPI0_ALT1_gc = (0x01<<0), /* SPI0 on PC[3:0] */ + PORTMUX_SPI0_ALT2_gc = (0x02<<0), /* SPI0 on PE[3:0] */ + PORTMUX_SPI0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 select */ +typedef enum PORTMUX_TCA0_enum +{ + PORTMUX_TCA0_PORTA_gc = (0x00<<0), /* TCA0 pins on PA[5:0] */ + PORTMUX_TCA0_PORTB_gc = (0x01<<0), /* TCA0 pins on PB[5:0] */ + PORTMUX_TCA0_PORTC_gc = (0x02<<0), /* TCA0 pins on PC[5:0] */ + PORTMUX_TCA0_PORTD_gc = (0x03<<0), /* TCA0 pins on PD[5:0] */ + PORTMUX_TCA0_PORTE_gc = (0x04<<0), /* TCA0 pins on PE[5:0] */ + PORTMUX_TCA0_PORTF_gc = (0x05<<0), /* TCA0 pins on PF[5:0] */ +} PORTMUX_TCA0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* SCL/SDA on PA[3:2], Slave mode on PC[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT1_gc = (0x01<<4), /* SCL/SDA on PA[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT2_gc = (0x02<<4), /* SCL/SDA on PC[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* USART0 on PA[3:0] */ + PORTMUX_USART0_ALT1_gc = (0x01<<0), /* USART0 on PA[7:4] */ + PORTMUX_USART0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_USART0_t; + +/* Port Multiplexer USART1 select */ +typedef enum PORTMUX_USART1_enum +{ + PORTMUX_USART1_DEFAULT_gc = (0x00<<2), /* USART1 on PC[3:0] */ + PORTMUX_USART1_ALT1_gc = (0x01<<2), /* USART1 on PC[7:4] */ + PORTMUX_USART1_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_USART1_t; + +/* Port Multiplexer USART2 select */ +typedef enum PORTMUX_USART2_enum +{ + PORTMUX_USART2_DEFAULT_gc = (0x00<<4), /* USART2 on PF[3:0] */ + PORTMUX_USART2_ALT1_gc = (0x01<<4), /* USART2 on PF[6:4] */ + PORTMUX_USART2_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_USART2_t; + +/* Port Multiplexer USART3 select */ +typedef enum PORTMUX_USART3_enum +{ + PORTMUX_USART3_DEFAULT_gc = (0x00<<6), /* USART3 on PB[3:0] */ + PORTMUX_USART3_ALT1_gc = (0x01<<6), /* USART3 on PB[5:4] */ + PORTMUX_USART3_NONE_gc = (0x03<<6), /* Not connected to any pins */ +} PORTMUX_USART3_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t CALIB; /* Calibration */ + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_1[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_2[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_3[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[7]; + register8_t OSCCAL32K; /* Oscillator Calibration for 32kHz ULP */ + register8_t reserved_2[3]; + register8_t OSCCAL16M0; /* Oscillator Calibration 16 MHz Byte 0 */ + register8_t OSCCAL16M1; /* Oscillator Calibration 16 MHz Byte 1 */ + register8_t OSCCAL20M0; /* Oscillator Calibration 20 MHz Byte 0 */ + register8_t OSCCAL20M1; /* Oscillator Calibration 20 MHz Byte 1 */ + register8_t reserved_3[4]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_4[9]; + register8_t CHECKSUM1; /* CRC Checksum Byte 1 */ + register8_t reserved_5[16]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[21]; + register8_t OCDM; /* OCD Message Register */ + register8_t OCDMS; /* OCD Message Status */ + register8_t reserved_3[6]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t DUALCTRL; /* Dual Control */ + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_1[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t CTRLD; /* Control D */ + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_1[1]; +} USART_t; + +/* Auto Baud Window select */ +typedef enum USART_ABW_enum +{ + USART_ABW_WDW0_gc = (0x00<<6), /* 18% tolerance */ + USART_ABW_WDW1_gc = (0x01<<6), /* 15% tolerance */ + USART_ABW_WDW2_gc = (0x02<<6), /* 21% tolerance */ + USART_ABW_WDW3_gc = (0x03<<6), /* 25% tolerance */ +} USART_ABW_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ + register8_t USERROW32; /* User Row Byte 32 */ + register8_t USERROW33; /* User Row Byte 33 */ + register8_t USERROW34; /* User Row Byte 34 */ + register8_t USERROW35; /* User Row Byte 35 */ + register8_t USERROW36; /* User Row Byte 36 */ + register8_t USERROW37; /* User Row Byte 37 */ + register8_t USERROW38; /* User Row Byte 38 */ + register8_t USERROW39; /* User Row Byte 39 */ + register8_t USERROW40; /* User Row Byte 40 */ + register8_t USERROW41; /* User Row Byte 41 */ + register8_t USERROW42; /* User Row Byte 42 */ + register8_t USERROW43; /* User Row Byte 43 */ + register8_t USERROW44; /* User Row Byte 44 */ + register8_t USERROW45; /* User Row Byte 45 */ + register8_t USERROW46; /* User Row Byte 46 */ + register8_t USERROW47; /* User Row Byte 47 */ + register8_t USERROW48; /* User Row Byte 48 */ + register8_t USERROW49; /* User Row Byte 49 */ + register8_t USERROW50; /* User Row Byte 50 */ + register8_t USERROW51; /* User Row Byte 51 */ + register8_t USERROW52; /* User Row Byte 52 */ + register8_t USERROW53; /* User Row Byte 53 */ + register8_t USERROW54; /* User Row Byte 54 */ + register8_t USERROW55; /* User Row Byte 55 */ + register8_t USERROW56; /* User Row Byte 56 */ + register8_t USERROW57; /* User Row Byte 57 */ + register8_t USERROW58; /* User Row Byte 58 */ + register8_t USERROW59; /* User Row Byte 59 */ + register8_t USERROW60; /* User Row Byte 60 */ + register8_t USERROW61; /* User Row Byte 61 */ + register8_t USERROW62; /* User Row Byte 62 */ + register8_t USERROW63; /* User Row Byte 63 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* AC0 reference select select */ +typedef enum VREF_AC0REFSEL_enum +{ + VREF_AC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_AC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_AC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_AC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_AC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ + VREF_AC0REFSEL_AVDD_gc = (0x07<<0), /* AVDD */ +} VREF_AC0REFSEL_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define VPORTD (*(VPORT_t *) 0x000C) /* Virtual Ports */ +#define VPORTE (*(VPORT_t *) 0x0010) /* Virtual Ports */ +#define VPORTF (*(VPORT_t *) 0x0014) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0460) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0480) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x04A0) /* I/O Ports */ +#define PORTMUX (*(PORTMUX_t *) 0x05E0) /* Port Multiplexer */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1 (*(USART_t *) 0x0820) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2 (*(USART_t *) 0x0840) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART3 (*(USART_t *) 0x0860) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x08A0) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A80) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0A90) /* 16-bit Timer Type B */ +#define TCB2 (*(TCB_t *) 0x0AA0) /* 16-bit Timer Type B */ +#define TCB3 (*(TCB_t *) 0x0AB0) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* VPORT (VPORTD) - Virtual Ports */ +#define VPORTD_DIR _SFR_MEM8(0x000C) +#define VPORTD_OUT _SFR_MEM8(0x000D) +#define VPORTD_IN _SFR_MEM8(0x000E) +#define VPORTD_INTFLAGS _SFR_MEM8(0x000F) + + +/* VPORT (VPORTE) - Virtual Ports */ +#define VPORTE_DIR _SFR_MEM8(0x0010) +#define VPORTE_OUT _SFR_MEM8(0x0011) +#define VPORTE_IN _SFR_MEM8(0x0012) +#define VPORTE_INTFLAGS _SFR_MEM8(0x0013) + + +/* VPORT (VPORTF) - Virtual Ports */ +#define VPORTF_DIR _SFR_MEM8(0x0014) +#define VPORTF_OUT _SFR_MEM8(0x0015) +#define VPORTF_IN _SFR_MEM8(0x0016) +#define VPORTF_INTFLAGS _SFR_MEM8(0x0017) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CALIB _SFR_MEM8(0x0146) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_STROBE _SFR_MEM8(0x0180) +#define EVSYS_CHANNEL0 _SFR_MEM8(0x0190) +#define EVSYS_CHANNEL1 _SFR_MEM8(0x0191) +#define EVSYS_CHANNEL2 _SFR_MEM8(0x0192) +#define EVSYS_CHANNEL3 _SFR_MEM8(0x0193) +#define EVSYS_CHANNEL4 _SFR_MEM8(0x0194) +#define EVSYS_CHANNEL5 _SFR_MEM8(0x0195) +#define EVSYS_CHANNEL6 _SFR_MEM8(0x0196) +#define EVSYS_CHANNEL7 _SFR_MEM8(0x0197) +#define EVSYS_USERCCLLUT0A _SFR_MEM8(0x01A0) +#define EVSYS_USERCCLLUT0B _SFR_MEM8(0x01A1) +#define EVSYS_USERCCLLUT1A _SFR_MEM8(0x01A2) +#define EVSYS_USERCCLLUT1B _SFR_MEM8(0x01A3) +#define EVSYS_USERCCLLUT2A _SFR_MEM8(0x01A4) +#define EVSYS_USERCCLLUT2B _SFR_MEM8(0x01A5) +#define EVSYS_USERCCLLUT3A _SFR_MEM8(0x01A6) +#define EVSYS_USERCCLLUT3B _SFR_MEM8(0x01A7) +#define EVSYS_USERADC0 _SFR_MEM8(0x01A8) +#define EVSYS_USEREVOUTA _SFR_MEM8(0x01A9) +#define EVSYS_USEREVOUTB _SFR_MEM8(0x01AA) +#define EVSYS_USEREVOUTC _SFR_MEM8(0x01AB) +#define EVSYS_USEREVOUTD _SFR_MEM8(0x01AC) +#define EVSYS_USEREVOUTE _SFR_MEM8(0x01AD) +#define EVSYS_USEREVOUTF _SFR_MEM8(0x01AE) +#define EVSYS_USERUSART0 _SFR_MEM8(0x01AF) +#define EVSYS_USERUSART1 _SFR_MEM8(0x01B0) +#define EVSYS_USERUSART2 _SFR_MEM8(0x01B1) +#define EVSYS_USERUSART3 _SFR_MEM8(0x01B2) +#define EVSYS_USERTCA0 _SFR_MEM8(0x01B3) +#define EVSYS_USERTCB0 _SFR_MEM8(0x01B4) +#define EVSYS_USERTCB1 _SFR_MEM8(0x01B5) +#define EVSYS_USERTCB2 _SFR_MEM8(0x01B6) +#define EVSYS_USERTCB3 _SFR_MEM8(0x01B7) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_SEQCTRL1 _SFR_MEM8(0x01C2) +#define CCL_INTCTRL0 _SFR_MEM8(0x01C5) +#define CCL_INTFLAGS _SFR_MEM8(0x01C7) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C8) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C9) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01CA) +#define CCL_TRUTH0 _SFR_MEM8(0x01CB) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01CC) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CD) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CE) +#define CCL_TRUTH1 _SFR_MEM8(0x01CF) +#define CCL_LUT2CTRLA _SFR_MEM8(0x01D0) +#define CCL_LUT2CTRLB _SFR_MEM8(0x01D1) +#define CCL_LUT2CTRLC _SFR_MEM8(0x01D2) +#define CCL_TRUTH2 _SFR_MEM8(0x01D3) +#define CCL_LUT3CTRLA _SFR_MEM8(0x01D4) +#define CCL_LUT3CTRLB _SFR_MEM8(0x01D5) +#define CCL_LUT3CTRLC _SFR_MEM8(0x01D6) +#define CCL_TRUTH3 _SFR_MEM8(0x01D7) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PORTCTRL _SFR_MEM8(0x040A) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PORTCTRL _SFR_MEM8(0x042A) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PORTCTRL _SFR_MEM8(0x044A) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* PORT (PORTD) - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0460) +#define PORTD_DIRSET _SFR_MEM8(0x0461) +#define PORTD_DIRCLR _SFR_MEM8(0x0462) +#define PORTD_DIRTGL _SFR_MEM8(0x0463) +#define PORTD_OUT _SFR_MEM8(0x0464) +#define PORTD_OUTSET _SFR_MEM8(0x0465) +#define PORTD_OUTCLR _SFR_MEM8(0x0466) +#define PORTD_OUTTGL _SFR_MEM8(0x0467) +#define PORTD_IN _SFR_MEM8(0x0468) +#define PORTD_INTFLAGS _SFR_MEM8(0x0469) +#define PORTD_PORTCTRL _SFR_MEM8(0x046A) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0470) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0471) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0472) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0473) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0474) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0475) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0476) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0477) + + +/* PORT (PORTE) - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0480) +#define PORTE_DIRSET _SFR_MEM8(0x0481) +#define PORTE_DIRCLR _SFR_MEM8(0x0482) +#define PORTE_DIRTGL _SFR_MEM8(0x0483) +#define PORTE_OUT _SFR_MEM8(0x0484) +#define PORTE_OUTSET _SFR_MEM8(0x0485) +#define PORTE_OUTCLR _SFR_MEM8(0x0486) +#define PORTE_OUTTGL _SFR_MEM8(0x0487) +#define PORTE_IN _SFR_MEM8(0x0488) +#define PORTE_INTFLAGS _SFR_MEM8(0x0489) +#define PORTE_PORTCTRL _SFR_MEM8(0x048A) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0490) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0491) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0492) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0493) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0494) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0495) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0496) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0497) + + +/* PORT (PORTF) - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x04A0) +#define PORTF_DIRSET _SFR_MEM8(0x04A1) +#define PORTF_DIRCLR _SFR_MEM8(0x04A2) +#define PORTF_DIRTGL _SFR_MEM8(0x04A3) +#define PORTF_OUT _SFR_MEM8(0x04A4) +#define PORTF_OUTSET _SFR_MEM8(0x04A5) +#define PORTF_OUTCLR _SFR_MEM8(0x04A6) +#define PORTF_OUTTGL _SFR_MEM8(0x04A7) +#define PORTF_IN _SFR_MEM8(0x04A8) +#define PORTF_INTFLAGS _SFR_MEM8(0x04A9) +#define PORTF_PORTCTRL _SFR_MEM8(0x04AA) +#define PORTF_PIN0CTRL _SFR_MEM8(0x04B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x04B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x04B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x04B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x04B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x04B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x04B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x04B7) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_EVSYSROUTEA _SFR_MEM8(0x05E0) +#define PORTMUX_CCLROUTEA _SFR_MEM8(0x05E1) +#define PORTMUX_USARTROUTEA _SFR_MEM8(0x05E2) +#define PORTMUX_TWISPIROUTEA _SFR_MEM8(0x05E3) +#define PORTMUX_TCAROUTEA _SFR_MEM8(0x05E4) +#define PORTMUX_TCBROUTEA _SFR_MEM8(0x05E5) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_DACREF _SFR_MEM8(0x0684) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_CTRLD _SFR_MEM8(0x080A) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* USART (USART1) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1_RXDATAL _SFR_MEM8(0x0820) +#define USART1_RXDATAH _SFR_MEM8(0x0821) +#define USART1_TXDATAL _SFR_MEM8(0x0822) +#define USART1_TXDATAH _SFR_MEM8(0x0823) +#define USART1_STATUS _SFR_MEM8(0x0824) +#define USART1_CTRLA _SFR_MEM8(0x0825) +#define USART1_CTRLB _SFR_MEM8(0x0826) +#define USART1_CTRLC _SFR_MEM8(0x0827) +#define USART1_BAUD _SFR_MEM16(0x0828) +#define USART1_BAUDL _SFR_MEM8(0x0828) +#define USART1_BAUDH _SFR_MEM8(0x0829) +#define USART1_CTRLD _SFR_MEM8(0x082A) +#define USART1_DBGCTRL _SFR_MEM8(0x082B) +#define USART1_EVCTRL _SFR_MEM8(0x082C) +#define USART1_TXPLCTRL _SFR_MEM8(0x082D) +#define USART1_RXPLCTRL _SFR_MEM8(0x082E) + + +/* USART (USART2) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2_RXDATAL _SFR_MEM8(0x0840) +#define USART2_RXDATAH _SFR_MEM8(0x0841) +#define USART2_TXDATAL _SFR_MEM8(0x0842) +#define USART2_TXDATAH _SFR_MEM8(0x0843) +#define USART2_STATUS _SFR_MEM8(0x0844) +#define USART2_CTRLA _SFR_MEM8(0x0845) +#define USART2_CTRLB _SFR_MEM8(0x0846) +#define USART2_CTRLC _SFR_MEM8(0x0847) +#define USART2_BAUD _SFR_MEM16(0x0848) +#define USART2_BAUDL _SFR_MEM8(0x0848) +#define USART2_BAUDH _SFR_MEM8(0x0849) +#define USART2_CTRLD _SFR_MEM8(0x084A) +#define USART2_DBGCTRL _SFR_MEM8(0x084B) +#define USART2_EVCTRL _SFR_MEM8(0x084C) +#define USART2_TXPLCTRL _SFR_MEM8(0x084D) +#define USART2_RXPLCTRL _SFR_MEM8(0x084E) + + +/* USART (USART3) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART3_RXDATAL _SFR_MEM8(0x0860) +#define USART3_RXDATAH _SFR_MEM8(0x0861) +#define USART3_TXDATAL _SFR_MEM8(0x0862) +#define USART3_TXDATAH _SFR_MEM8(0x0863) +#define USART3_STATUS _SFR_MEM8(0x0864) +#define USART3_CTRLA _SFR_MEM8(0x0865) +#define USART3_CTRLB _SFR_MEM8(0x0866) +#define USART3_CTRLC _SFR_MEM8(0x0867) +#define USART3_BAUD _SFR_MEM16(0x0868) +#define USART3_BAUDL _SFR_MEM8(0x0868) +#define USART3_BAUDH _SFR_MEM8(0x0869) +#define USART3_CTRLD _SFR_MEM8(0x086A) +#define USART3_DBGCTRL _SFR_MEM8(0x086B) +#define USART3_EVCTRL _SFR_MEM8(0x086C) +#define USART3_TXPLCTRL _SFR_MEM8(0x086D) +#define USART3_RXPLCTRL _SFR_MEM8(0x086E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x08A0) +#define TWI0_DUALCTRL _SFR_MEM8(0x08A1) +#define TWI0_DBGCTRL _SFR_MEM8(0x08A2) +#define TWI0_MCTRLA _SFR_MEM8(0x08A3) +#define TWI0_MCTRLB _SFR_MEM8(0x08A4) +#define TWI0_MSTATUS _SFR_MEM8(0x08A5) +#define TWI0_MBAUD _SFR_MEM8(0x08A6) +#define TWI0_MADDR _SFR_MEM8(0x08A7) +#define TWI0_MDATA _SFR_MEM8(0x08A8) +#define TWI0_SCTRLA _SFR_MEM8(0x08A9) +#define TWI0_SCTRLB _SFR_MEM8(0x08AA) +#define TWI0_SSTATUS _SFR_MEM8(0x08AB) +#define TWI0_SADDR _SFR_MEM8(0x08AC) +#define TWI0_SDATA _SFR_MEM8(0x08AD) +#define TWI0_SADDRMASK _SFR_MEM8(0x08AE) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x08C0) +#define SPI0_CTRLB _SFR_MEM8(0x08C1) +#define SPI0_INTCTRL _SFR_MEM8(0x08C2) +#define SPI0_INTFLAGS _SFR_MEM8(0x08C3) +#define SPI0_DATA _SFR_MEM8(0x08C4) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A80) +#define TCB0_CTRLB _SFR_MEM8(0x0A81) +#define TCB0_EVCTRL _SFR_MEM8(0x0A84) +#define TCB0_INTCTRL _SFR_MEM8(0x0A85) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A86) +#define TCB0_STATUS _SFR_MEM8(0x0A87) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A88) +#define TCB0_TEMP _SFR_MEM8(0x0A89) +#define TCB0_CNT _SFR_MEM16(0x0A8A) +#define TCB0_CNTL _SFR_MEM8(0x0A8A) +#define TCB0_CNTH _SFR_MEM8(0x0A8B) +#define TCB0_CCMP _SFR_MEM16(0x0A8C) +#define TCB0_CCMPL _SFR_MEM8(0x0A8C) +#define TCB0_CCMPH _SFR_MEM8(0x0A8D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0A90) +#define TCB1_CTRLB _SFR_MEM8(0x0A91) +#define TCB1_EVCTRL _SFR_MEM8(0x0A94) +#define TCB1_INTCTRL _SFR_MEM8(0x0A95) +#define TCB1_INTFLAGS _SFR_MEM8(0x0A96) +#define TCB1_STATUS _SFR_MEM8(0x0A97) +#define TCB1_DBGCTRL _SFR_MEM8(0x0A98) +#define TCB1_TEMP _SFR_MEM8(0x0A99) +#define TCB1_CNT _SFR_MEM16(0x0A9A) +#define TCB1_CNTL _SFR_MEM8(0x0A9A) +#define TCB1_CNTH _SFR_MEM8(0x0A9B) +#define TCB1_CCMP _SFR_MEM16(0x0A9C) +#define TCB1_CCMPL _SFR_MEM8(0x0A9C) +#define TCB1_CCMPH _SFR_MEM8(0x0A9D) + + +/* TCB (TCB2) - 16-bit Timer Type B */ +#define TCB2_CTRLA _SFR_MEM8(0x0AA0) +#define TCB2_CTRLB _SFR_MEM8(0x0AA1) +#define TCB2_EVCTRL _SFR_MEM8(0x0AA4) +#define TCB2_INTCTRL _SFR_MEM8(0x0AA5) +#define TCB2_INTFLAGS _SFR_MEM8(0x0AA6) +#define TCB2_STATUS _SFR_MEM8(0x0AA7) +#define TCB2_DBGCTRL _SFR_MEM8(0x0AA8) +#define TCB2_TEMP _SFR_MEM8(0x0AA9) +#define TCB2_CNT _SFR_MEM16(0x0AAA) +#define TCB2_CNTL _SFR_MEM8(0x0AAA) +#define TCB2_CNTH _SFR_MEM8(0x0AAB) +#define TCB2_CCMP _SFR_MEM16(0x0AAC) +#define TCB2_CCMPL _SFR_MEM8(0x0AAC) +#define TCB2_CCMPH _SFR_MEM8(0x0AAD) + + +/* TCB (TCB3) - 16-bit Timer Type B */ +#define TCB3_CTRLA _SFR_MEM8(0x0AB0) +#define TCB3_CTRLB _SFR_MEM8(0x0AB1) +#define TCB3_EVCTRL _SFR_MEM8(0x0AB4) +#define TCB3_INTCTRL _SFR_MEM8(0x0AB5) +#define TCB3_INTFLAGS _SFR_MEM8(0x0AB6) +#define TCB3_STATUS _SFR_MEM8(0x0AB7) +#define TCB3_DBGCTRL _SFR_MEM8(0x0AB8) +#define TCB3_TEMP _SFR_MEM8(0x0AB9) +#define TCB3_CNT _SFR_MEM16(0x0ABA) +#define TCB3_CNTL _SFR_MEM8(0x0ABA) +#define TCB3_CNTH _SFR_MEM8(0x0ABB) +#define TCB3_CCMP _SFR_MEM16(0x0ABC) +#define TCB3_CCMPL _SFR_MEM8(0x0ABC) +#define TCB3_CCMPH _SFR_MEM8(0x0ABD) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) +#define SYSCFG_OCDM _SFR_MEM8(0x0F18) +#define SYSCFG_OCDMS _SFR_MEM8(0x0F19) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_OSCCAL32K _SFR_MEM8(0x1114) +#define SIGROW_OSCCAL16M0 _SFR_MEM8(0x1118) +#define SIGROW_OSCCAL16M1 _SFR_MEM8(0x1119) +#define SIGROW_OSCCAL20M0 _SFR_MEM8(0x111A) +#define SIGROW_OSCCAL20M1 _SFR_MEM8(0x111B) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) +#define SIGROW_CHECKSUM1 _SFR_MEM8(0x112F) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) +#define USERROW_USERROW32 _SFR_MEM8(0x1320) +#define USERROW_USERROW33 _SFR_MEM8(0x1321) +#define USERROW_USERROW34 _SFR_MEM8(0x1322) +#define USERROW_USERROW35 _SFR_MEM8(0x1323) +#define USERROW_USERROW36 _SFR_MEM8(0x1324) +#define USERROW_USERROW37 _SFR_MEM8(0x1325) +#define USERROW_USERROW38 _SFR_MEM8(0x1326) +#define USERROW_USERROW39 _SFR_MEM8(0x1327) +#define USERROW_USERROW40 _SFR_MEM8(0x1328) +#define USERROW_USERROW41 _SFR_MEM8(0x1329) +#define USERROW_USERROW42 _SFR_MEM8(0x132A) +#define USERROW_USERROW43 _SFR_MEM8(0x132B) +#define USERROW_USERROW44 _SFR_MEM8(0x132C) +#define USERROW_USERROW45 _SFR_MEM8(0x132D) +#define USERROW_USERROW46 _SFR_MEM8(0x132E) +#define USERROW_USERROW47 _SFR_MEM8(0x132F) +#define USERROW_USERROW48 _SFR_MEM8(0x1330) +#define USERROW_USERROW49 _SFR_MEM8(0x1331) +#define USERROW_USERROW50 _SFR_MEM8(0x1332) +#define USERROW_USERROW51 _SFR_MEM8(0x1333) +#define USERROW_USERROW52 _SFR_MEM8(0x1334) +#define USERROW_USERROW53 _SFR_MEM8(0x1335) +#define USERROW_USERROW54 _SFR_MEM8(0x1336) +#define USERROW_USERROW55 _SFR_MEM8(0x1337) +#define USERROW_USERROW56 _SFR_MEM8(0x1338) +#define USERROW_USERROW57 _SFR_MEM8(0x1339) +#define USERROW_USERROW58 _SFR_MEM8(0x133A) +#define USERROW_USERROW59 _SFR_MEM8(0x133B) +#define USERROW_USERROW60 _SFR_MEM8(0x133C) +#define USERROW_USERROW61 _SFR_MEM8(0x133D) +#define USERROW_USERROW62 _SFR_MEM8(0x133E) +#define USERROW_USERROW63 _SFR_MEM8(0x133F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.DACREF bit masks and bit positions */ +#define AC_DATA_gm 0xFF /* DAC voltage reference group mask. */ +#define AC_DATA_gp 0 /* DAC voltage reference group position. */ +#define AC_DATA0_bm (1<<0) /* DAC voltage reference bit 0 mask. */ +#define AC_DATA0_bp 0 /* DAC voltage reference bit 0 position. */ +#define AC_DATA1_bm (1<<1) /* DAC voltage reference bit 1 mask. */ +#define AC_DATA1_bp 1 /* DAC voltage reference bit 1 position. */ +#define AC_DATA2_bm (1<<2) /* DAC voltage reference bit 2 mask. */ +#define AC_DATA2_bp 2 /* DAC voltage reference bit 2 position. */ +#define AC_DATA3_bm (1<<3) /* DAC voltage reference bit 3 mask. */ +#define AC_DATA3_bp 3 /* DAC voltage reference bit 3 position. */ +#define AC_DATA4_bm (1<<4) /* DAC voltage reference bit 4 mask. */ +#define AC_DATA4_bp 4 /* DAC voltage reference bit 4 position. */ +#define AC_DATA5_bm (1<<5) /* DAC voltage reference bit 5 mask. */ +#define AC_DATA5_bp 5 /* DAC voltage reference bit 5 position. */ +#define AC_DATA6_bm (1<<6) /* DAC voltage reference bit 6 mask. */ +#define AC_DATA6_bp 6 /* DAC voltage reference bit 6 position. */ +#define AC_DATA7_bm (1<<7) /* DAC voltage reference bit 7 mask. */ +#define AC_DATA7_bp 7 /* DAC voltage reference bit 7 position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL0_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL0_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL00_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL00_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL01_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL01_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL02_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL02_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.SEQCTRL1 bit masks and bit positions */ +#define CCL_SEQSEL1_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL1_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL10_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL10_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL11_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL11_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL12_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL12_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.INTCTRL0 bit masks and bit positions */ +#define CCL_INTMODE0_gm 0x03 /* Interrupt Mode for LUT0 group mask. */ +#define CCL_INTMODE0_gp 0 /* Interrupt Mode for LUT0 group position. */ +#define CCL_INTMODE00_bm (1<<0) /* Interrupt Mode for LUT0 bit 0 mask. */ +#define CCL_INTMODE00_bp 0 /* Interrupt Mode for LUT0 bit 0 position. */ +#define CCL_INTMODE01_bm (1<<1) /* Interrupt Mode for LUT0 bit 1 mask. */ +#define CCL_INTMODE01_bp 1 /* Interrupt Mode for LUT0 bit 1 position. */ +#define CCL_INTMODE1_gm 0x0C /* Interrupt Mode for LUT1 group mask. */ +#define CCL_INTMODE1_gp 2 /* Interrupt Mode for LUT1 group position. */ +#define CCL_INTMODE10_bm (1<<2) /* Interrupt Mode for LUT1 bit 0 mask. */ +#define CCL_INTMODE10_bp 2 /* Interrupt Mode for LUT1 bit 0 position. */ +#define CCL_INTMODE11_bm (1<<3) /* Interrupt Mode for LUT1 bit 1 mask. */ +#define CCL_INTMODE11_bp 3 /* Interrupt Mode for LUT1 bit 1 position. */ +#define CCL_INTMODE2_gm 0x30 /* Interrupt Mode for LUT2 group mask. */ +#define CCL_INTMODE2_gp 4 /* Interrupt Mode for LUT2 group position. */ +#define CCL_INTMODE20_bm (1<<4) /* Interrupt Mode for LUT2 bit 0 mask. */ +#define CCL_INTMODE20_bp 4 /* Interrupt Mode for LUT2 bit 0 position. */ +#define CCL_INTMODE21_bm (1<<5) /* Interrupt Mode for LUT2 bit 1 mask. */ +#define CCL_INTMODE21_bp 5 /* Interrupt Mode for LUT2 bit 1 position. */ +#define CCL_INTMODE3_gm 0xC0 /* Interrupt Mode for LUT3 group mask. */ +#define CCL_INTMODE3_gp 6 /* Interrupt Mode for LUT3 group position. */ +#define CCL_INTMODE30_bm (1<<6) /* Interrupt Mode for LUT3 bit 0 mask. */ +#define CCL_INTMODE30_bp 6 /* Interrupt Mode for LUT3 bit 0 position. */ +#define CCL_INTMODE31_bm (1<<7) /* Interrupt Mode for LUT3 bit 1 mask. */ +#define CCL_INTMODE31_bp 7 /* Interrupt Mode for LUT3 bit 1 position. */ + +/* CCL.INTFLAGS bit masks and bit positions */ +#define CCL_INT_gm 0x0F /* Interrupt Flags group mask. */ +#define CCL_INT_gp 0 /* Interrupt Flags group position. */ +#define CCL_INT0_bm (1<<0) /* Interrupt Flags bit 0 mask. */ +#define CCL_INT0_bp 0 /* Interrupt Flags bit 0 position. */ +#define CCL_INT1_bm (1<<1) /* Interrupt Flags bit 1 mask. */ +#define CCL_INT1_bp 1 /* Interrupt Flags bit 1 position. */ +#define CCL_INT2_bm (1<<2) /* Interrupt Flags bit 2 mask. */ +#define CCL_INT2_bp 2 /* Interrupt Flags bit 2 position. */ +#define CCL_INT3_bm (1<<3) /* Interrupt Flags bit 3 mask. */ +#define CCL_INT3_bp 3 /* Interrupt Flags bit 3 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_CLKSRC_gm 0x0E /* Clock Source Selection group mask. */ +#define CCL_CLKSRC_gp 1 /* Clock Source Selection group position. */ +#define CCL_CLKSRC0_bm (1<<1) /* Clock Source Selection bit 0 mask. */ +#define CCL_CLKSRC0_bp 1 /* Clock Source Selection bit 0 position. */ +#define CCL_CLKSRC1_bm (1<<2) /* Clock Source Selection bit 1 mask. */ +#define CCL_CLKSRC1_bp 2 /* Clock Source Selection bit 1 position. */ +#define CCL_CLKSRC2_bm (1<<3) /* Clock Source Selection bit 2 mask. */ +#define CCL_CLKSRC2_bp 3 /* Clock Source Selection bit 2 position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_OUTEN_bm 0x40 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 6 /* Output Enable bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT2CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT2CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT2CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT3CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT3CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT3CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x7F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ +#define CLKCTRL_CAL20M6_bm (1<<6) /* Calibration bit 6 mask. */ +#define CLKCTRL_CAL20M6_bp 6 /* Calibration bit 6 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.STROBE bit masks and bit positions */ +#define EVSYS_STROBE0_gm 0xFF /* Software event on channels group mask. */ +#define EVSYS_STROBE0_gp 0 /* Software event on channels group position. */ +#define EVSYS_STROBE00_bm (1<<0) /* Software event on channels bit 0 mask. */ +#define EVSYS_STROBE00_bp 0 /* Software event on channels bit 0 position. */ +#define EVSYS_STROBE01_bm (1<<1) /* Software event on channels bit 1 mask. */ +#define EVSYS_STROBE01_bp 1 /* Software event on channels bit 1 position. */ +#define EVSYS_STROBE02_bm (1<<2) /* Software event on channels bit 2 mask. */ +#define EVSYS_STROBE02_bp 2 /* Software event on channels bit 2 position. */ +#define EVSYS_STROBE03_bm (1<<3) /* Software event on channels bit 3 mask. */ +#define EVSYS_STROBE03_bp 3 /* Software event on channels bit 3 position. */ +#define EVSYS_STROBE04_bm (1<<4) /* Software event on channels bit 4 mask. */ +#define EVSYS_STROBE04_bp 4 /* Software event on channels bit 4 position. */ +#define EVSYS_STROBE05_bm (1<<5) /* Software event on channels bit 5 mask. */ +#define EVSYS_STROBE05_bp 5 /* Software event on channels bit 5 position. */ +#define EVSYS_STROBE06_bm (1<<6) /* Software event on channels bit 6 mask. */ +#define EVSYS_STROBE06_bp 6 /* Software event on channels bit 6 position. */ +#define EVSYS_STROBE07_bm (1<<7) /* Software event on channels bit 7 mask. */ +#define EVSYS_STROBE07_bp 7 /* Software event on channels bit 7 position. */ + +/* EVSYS.CHANNEL0 bit masks and bit positions */ +#define EVSYS_GENERATOR_gm 0xFF /* Generator selector group mask. */ +#define EVSYS_GENERATOR_gp 0 /* Generator selector group position. */ +#define EVSYS_GENERATOR0_bm (1<<0) /* Generator selector bit 0 mask. */ +#define EVSYS_GENERATOR0_bp 0 /* Generator selector bit 0 position. */ +#define EVSYS_GENERATOR1_bm (1<<1) /* Generator selector bit 1 mask. */ +#define EVSYS_GENERATOR1_bp 1 /* Generator selector bit 1 position. */ +#define EVSYS_GENERATOR2_bm (1<<2) /* Generator selector bit 2 mask. */ +#define EVSYS_GENERATOR2_bp 2 /* Generator selector bit 2 position. */ +#define EVSYS_GENERATOR3_bm (1<<3) /* Generator selector bit 3 mask. */ +#define EVSYS_GENERATOR3_bp 3 /* Generator selector bit 3 position. */ +#define EVSYS_GENERATOR4_bm (1<<4) /* Generator selector bit 4 mask. */ +#define EVSYS_GENERATOR4_bp 4 /* Generator selector bit 4 position. */ +#define EVSYS_GENERATOR5_bm (1<<5) /* Generator selector bit 5 mask. */ +#define EVSYS_GENERATOR5_bp 5 /* Generator selector bit 5 position. */ +#define EVSYS_GENERATOR6_bm (1<<6) /* Generator selector bit 6 mask. */ +#define EVSYS_GENERATOR6_bp 6 /* Generator selector bit 6 position. */ +#define EVSYS_GENERATOR7_bm (1<<7) /* Generator selector bit 7 mask. */ +#define EVSYS_GENERATOR7_bp 7 /* Generator selector bit 7 position. */ + +/* EVSYS.CHANNEL1 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL2 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL3 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL4 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL5 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL6 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL7 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.USERCCLLUT0A bit masks and bit positions */ +#define EVSYS_CHANNEL_gm 0xFF /* Channel selector group mask. */ +#define EVSYS_CHANNEL_gp 0 /* Channel selector group position. */ +#define EVSYS_CHANNEL0_bm (1<<0) /* Channel selector bit 0 mask. */ +#define EVSYS_CHANNEL0_bp 0 /* Channel selector bit 0 position. */ +#define EVSYS_CHANNEL1_bm (1<<1) /* Channel selector bit 1 mask. */ +#define EVSYS_CHANNEL1_bp 1 /* Channel selector bit 1 position. */ +#define EVSYS_CHANNEL2_bm (1<<2) /* Channel selector bit 2 mask. */ +#define EVSYS_CHANNEL2_bp 2 /* Channel selector bit 2 position. */ +#define EVSYS_CHANNEL3_bm (1<<3) /* Channel selector bit 3 mask. */ +#define EVSYS_CHANNEL3_bp 3 /* Channel selector bit 3 position. */ +#define EVSYS_CHANNEL4_bm (1<<4) /* Channel selector bit 4 mask. */ +#define EVSYS_CHANNEL4_bp 4 /* Channel selector bit 4 position. */ +#define EVSYS_CHANNEL5_bm (1<<5) /* Channel selector bit 5 mask. */ +#define EVSYS_CHANNEL5_bp 5 /* Channel selector bit 5 position. */ +#define EVSYS_CHANNEL6_bm (1<<6) /* Channel selector bit 6 mask. */ +#define EVSYS_CHANNEL6_bp 6 /* Channel selector bit 6 position. */ +#define EVSYS_CHANNEL7_bm (1<<7) /* Channel selector bit 7 mask. */ +#define EVSYS_CHANNEL7_bp 7 /* Channel selector bit 7 position. */ + +/* EVSYS.USERCCLLUT0B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT1A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT1B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT2A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT2B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT3A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT3B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERADC0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTA bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTB bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTC bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTD bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTE bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTF bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART1 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART2 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART3 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCA0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB1 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB2 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB3 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_bm 0x08 /* Reset Pin Configuration bit mask. */ +#define FUSE_RSTPINCFG_bp 3 /* Reset Pin Configuration bit position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PORTCTRL bit masks and bit positions */ +#define PORT_SRL_bm 0x01 /* Slew Rate Limit Enable bit mask. */ +#define PORT_SRL_bp 0 /* Slew Rate Limit Enable bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.EVSYSROUTEA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_EVOUT3_bm 0x08 /* Event Output 3 bit mask. */ +#define PORTMUX_EVOUT3_bp 3 /* Event Output 3 bit position. */ +#define PORTMUX_EVOUT4_bm 0x10 /* Event Output 4 bit mask. */ +#define PORTMUX_EVOUT4_bp 4 /* Event Output 4 bit position. */ +#define PORTMUX_EVOUT5_bm 0x20 /* Event Output 5 bit mask. */ +#define PORTMUX_EVOUT5_bp 5 /* Event Output 5 bit position. */ + +/* PORTMUX.CCLROUTEA bit masks and bit positions */ +#define PORTMUX_LUT0_bm 0x01 /* CCL LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 0 /* CCL LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x02 /* CCL LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 1 /* CCL LUT1 bit position. */ +#define PORTMUX_LUT2_bm 0x04 /* CCL LUT2 bit mask. */ +#define PORTMUX_LUT2_bp 2 /* CCL LUT2 bit position. */ +#define PORTMUX_LUT3_bm 0x08 /* CCL LUT3 bit mask. */ +#define PORTMUX_LUT3_bp 3 /* CCL LUT3 bit position. */ + +/* PORTMUX.USARTROUTEA bit masks and bit positions */ +#define PORTMUX_USART0_gm 0x03 /* Port Multiplexer USART0 group mask. */ +#define PORTMUX_USART0_gp 0 /* Port Multiplexer USART0 group position. */ +#define PORTMUX_USART00_bm (1<<0) /* Port Multiplexer USART0 bit 0 mask. */ +#define PORTMUX_USART00_bp 0 /* Port Multiplexer USART0 bit 0 position. */ +#define PORTMUX_USART01_bm (1<<1) /* Port Multiplexer USART0 bit 1 mask. */ +#define PORTMUX_USART01_bp 1 /* Port Multiplexer USART0 bit 1 position. */ +#define PORTMUX_USART1_gm 0x0C /* Port Multiplexer USART1 group mask. */ +#define PORTMUX_USART1_gp 2 /* Port Multiplexer USART1 group position. */ +#define PORTMUX_USART10_bm (1<<2) /* Port Multiplexer USART1 bit 0 mask. */ +#define PORTMUX_USART10_bp 2 /* Port Multiplexer USART1 bit 0 position. */ +#define PORTMUX_USART11_bm (1<<3) /* Port Multiplexer USART1 bit 1 mask. */ +#define PORTMUX_USART11_bp 3 /* Port Multiplexer USART1 bit 1 position. */ +#define PORTMUX_USART2_gm 0x30 /* Port Multiplexer USART2 group mask. */ +#define PORTMUX_USART2_gp 4 /* Port Multiplexer USART2 group position. */ +#define PORTMUX_USART20_bm (1<<4) /* Port Multiplexer USART2 bit 0 mask. */ +#define PORTMUX_USART20_bp 4 /* Port Multiplexer USART2 bit 0 position. */ +#define PORTMUX_USART21_bm (1<<5) /* Port Multiplexer USART2 bit 1 mask. */ +#define PORTMUX_USART21_bp 5 /* Port Multiplexer USART2 bit 1 position. */ +#define PORTMUX_USART3_gm 0xC0 /* Port Multiplexer USART3 group mask. */ +#define PORTMUX_USART3_gp 6 /* Port Multiplexer USART3 group position. */ +#define PORTMUX_USART30_bm (1<<6) /* Port Multiplexer USART3 bit 0 mask. */ +#define PORTMUX_USART30_bp 6 /* Port Multiplexer USART3 bit 0 position. */ +#define PORTMUX_USART31_bm (1<<7) /* Port Multiplexer USART3 bit 1 mask. */ +#define PORTMUX_USART31_bp 7 /* Port Multiplexer USART3 bit 1 position. */ + +/* PORTMUX.TWISPIROUTEA bit masks and bit positions */ +#define PORTMUX_SPI0_gm 0x03 /* Port Multiplexer SPI0 group mask. */ +#define PORTMUX_SPI0_gp 0 /* Port Multiplexer SPI0 group position. */ +#define PORTMUX_SPI00_bm (1<<0) /* Port Multiplexer SPI0 bit 0 mask. */ +#define PORTMUX_SPI00_bp 0 /* Port Multiplexer SPI0 bit 0 position. */ +#define PORTMUX_SPI01_bm (1<<1) /* Port Multiplexer SPI0 bit 1 mask. */ +#define PORTMUX_SPI01_bp 1 /* Port Multiplexer SPI0 bit 1 position. */ +#define PORTMUX_TWI0_gm 0x30 /* Port Multiplexer TWI0 group mask. */ +#define PORTMUX_TWI0_gp 4 /* Port Multiplexer TWI0 group position. */ +#define PORTMUX_TWI00_bm (1<<4) /* Port Multiplexer TWI0 bit 0 mask. */ +#define PORTMUX_TWI00_bp 4 /* Port Multiplexer TWI0 bit 0 position. */ +#define PORTMUX_TWI01_bm (1<<5) /* Port Multiplexer TWI0 bit 1 mask. */ +#define PORTMUX_TWI01_bp 5 /* Port Multiplexer TWI0 bit 1 position. */ + +/* PORTMUX.TCAROUTEA bit masks and bit positions */ +#define PORTMUX_TCA0_gm 0x07 /* Port Multiplexer TCA0 group mask. */ +#define PORTMUX_TCA0_gp 0 /* Port Multiplexer TCA0 group position. */ +#define PORTMUX_TCA00_bm (1<<0) /* Port Multiplexer TCA0 bit 0 mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 bit 0 position. */ +#define PORTMUX_TCA01_bm (1<<1) /* Port Multiplexer TCA0 bit 1 mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 bit 1 position. */ +#define PORTMUX_TCA02_bm (1<<2) /* Port Multiplexer TCA0 bit 2 mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 bit 2 position. */ + +/* PORTMUX.TCBROUTEA bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ +#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ +#define PORTMUX_TCB2_bm 0x04 /* Port Multiplexer TCB2 bit mask. */ +#define PORTMUX_TCB2_bp 2 /* Port Multiplexer TCB2 bit position. */ +#define PORTMUX_TCB3_bm 0x08 /* Port Multiplexer TCB3 bit mask. */ +#define PORTMUX_TCB3_bp 3 /* Port Multiplexer TCB3 bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_CORREN_bm 0x04 /* Correction enable bit mask. */ +#define RTC_CORREN_bp 2 /* Correction enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_ERROR_gm 0x7F /* Error Correction Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Correction Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Correction Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Correction Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Correction Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Correction Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Correction Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Correction Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Correction Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Correction Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Correction Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Correction Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Correction Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Correction Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Correction Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Correction Value bit 6 position. */ +#define RTC_SIGN_bm 0x80 /* Error Correction Sign Bit bit mask. */ +#define RTC_SIGN_bp 7 /* Error Correction Sign Bit bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + + +/* SYSCFG.OCDMS bit masks and bit positions */ +#define SYSCFG_OCDMR_bm 0x01 /* OCD Message Read bit mask. */ +#define SYSCFG_OCDMR_bp 0 /* OCD Message Read bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DUALCTRL bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Dual Control Enable bit mask. */ +#define TWI_ENABLE_bp 0 /* Dual Control Enable bit position. */ +/* TWI_FMPEN is already defined. */ +/* TWI_SDAHOLD is already defined. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.CTRLD bit masks and bit positions */ +#define USART_ABW_gm 0xC0 /* Auto Baud Window group mask. */ +#define USART_ABW_gp 6 /* Auto Baud Window group position. */ +#define USART_ABW0_bm (1<<6) /* Auto Baud Window bit 0 mask. */ +#define USART_ABW0_bp 6 /* Auto Baud Window bit 0 position. */ +#define USART_ABW1_bm (1<<7) /* Auto Baud Window bit 1 mask. */ +#define USART_ABW1_bp 7 /* Auto Baud Window bit 1 position. */ + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_AC0REFSEL_gm 0x07 /* AC0 reference select group mask. */ +#define VREF_AC0REFSEL_gp 0 /* AC0 reference select group position. */ +#define VREF_AC0REFSEL0_bm (1<<0) /* AC0 reference select bit 0 mask. */ +#define VREF_AC0REFSEL0_bp 0 /* AC0 reference select bit 0 position. */ +#define VREF_AC0REFSEL1_bm (1<<1) /* AC0 reference select bit 1 mask. */ +#define VREF_AC0REFSEL1_bp 1 /* AC0 reference select bit 1 position. */ +#define VREF_AC0REFSEL2_bm (1<<2) /* AC0 reference select bit 2 mask. */ +#define VREF_AC0REFSEL2_bp 2 /* AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_AC0REFEN_bm 0x01 /* AC0 DACREF reference enable bit mask. */ +#define VREF_AC0REFEN_bp 0 /* AC0 DACREF reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 3 +#define RTC_CNT_vect _VECTOR(3) /* */ +#define RTC_PIT_vect_num 4 +#define RTC_PIT_vect _VECTOR(4) /* */ + +/* CCL interrupt vectors */ +#define CCL_CCL_vect_num 5 +#define CCL_CCL_vect _VECTOR(5) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 6 +#define PORTA_PORT_vect _VECTOR(6) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 7 +#define TCA0_LUNF_vect _VECTOR(7) /* */ +#define TCA0_OVF_vect_num 7 +#define TCA0_OVF_vect _VECTOR(7) /* */ +#define TCA0_HUNF_vect_num 8 +#define TCA0_HUNF_vect _VECTOR(8) /* */ +#define TCA0_CMP0_vect_num 9 +#define TCA0_CMP0_vect _VECTOR(9) /* */ +#define TCA0_LCMP0_vect_num 9 +#define TCA0_LCMP0_vect _VECTOR(9) /* */ +#define TCA0_CMP1_vect_num 10 +#define TCA0_CMP1_vect _VECTOR(10) /* */ +#define TCA0_LCMP1_vect_num 10 +#define TCA0_LCMP1_vect _VECTOR(10) /* */ +#define TCA0_CMP2_vect_num 11 +#define TCA0_CMP2_vect _VECTOR(11) /* */ +#define TCA0_LCMP2_vect_num 11 +#define TCA0_LCMP2_vect _VECTOR(11) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 12 +#define TCB0_INT_vect _VECTOR(12) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 13 +#define TCB1_INT_vect _VECTOR(13) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 14 +#define TWI0_TWIS_vect _VECTOR(14) /* */ +#define TWI0_TWIM_vect_num 15 +#define TWI0_TWIM_vect _VECTOR(15) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 16 +#define SPI0_INT_vect _VECTOR(16) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 17 +#define USART0_RXC_vect _VECTOR(17) /* */ +#define USART0_DRE_vect_num 18 +#define USART0_DRE_vect _VECTOR(18) /* */ +#define USART0_TXC_vect_num 19 +#define USART0_TXC_vect _VECTOR(19) /* */ + +/* PORTD interrupt vectors */ +#define PORTD_PORT_vect_num 20 +#define PORTD_PORT_vect _VECTOR(20) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 21 +#define AC0_AC_vect _VECTOR(21) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 22 +#define ADC0_RESRDY_vect _VECTOR(22) /* */ +#define ADC0_WCOMP_vect_num 23 +#define ADC0_WCOMP_vect _VECTOR(23) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 24 +#define PORTC_PORT_vect _VECTOR(24) /* */ + +/* TCB2 interrupt vectors */ +#define TCB2_INT_vect_num 25 +#define TCB2_INT_vect _VECTOR(25) /* */ + +/* USART1 interrupt vectors */ +#define USART1_RXC_vect_num 26 +#define USART1_RXC_vect _VECTOR(26) /* */ +#define USART1_DRE_vect_num 27 +#define USART1_DRE_vect _VECTOR(27) /* */ +#define USART1_TXC_vect_num 28 +#define USART1_TXC_vect _VECTOR(28) /* */ + +/* PORTF interrupt vectors */ +#define PORTF_PORT_vect_num 29 +#define PORTF_PORT_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +/* USART2 interrupt vectors */ +#define USART2_RXC_vect_num 31 +#define USART2_RXC_vect _VECTOR(31) /* */ +#define USART2_DRE_vect_num 32 +#define USART2_DRE_vect _VECTOR(32) /* */ +#define USART2_TXC_vect_num 33 +#define USART2_TXC_vect _VECTOR(33) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 34 +#define PORTB_PORT_vect _VECTOR(34) /* */ + +/* PORTE interrupt vectors */ +#define PORTE_PORT_vect_num 35 +#define PORTE_PORT_vect _VECTOR(35) /* */ + +/* TCB3 interrupt vectors */ +#define TCB3_INT_vect_num 36 +#define TCB3_INT_vect _VECTOR(36) /* */ + +/* USART3 interrupt vectors */ +#define USART3_RXC_vect_num 37 +#define USART3_RXC_vect _VECTOR(37) /* */ +#define USART3_DRE_vect_num 38 +#define USART3_DRE_vect _VECTOR(38) /* */ +#define USART3_TXC_vect_num 39 +#define USART3_TXC_vect _VECTOR(39) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (40 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (65536) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (65536U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (64) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (64U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (64) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (64U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x2800) +# define INTERNAL_SRAM_SIZE (6144) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x2800U) +# define INTERNAL_SRAM_SIZE (6144U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (64) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (64U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x4000) +# define MAPPED_PROGMEM_SIZE (49152) +# define MAPPED_PROGMEM_PAGE_SIZE (128) +#else +# define MAPPED_PROGMEM_START (0x4000U) +# define MAPPED_PROGMEM_SIZE (49152U) +# define MAPPED_PROGMEM_PAGE_SIZE (128U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (125) +# define PROD_SIGNATURES_PAGE_SIZE (128) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (125U) +# define PROD_SIGNATURES_PAGE_SIZE (128U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (128) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (128U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (64) +# define USER_SIGNATURES_PAGE_SIZE (64) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (64U) +# define USER_SIGNATURES_PAGE_SIZE (64U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (49152) +# define PROGMEM_PAGE_SIZE (128) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (49152U) +# define PROGMEM_PAGE_SIZE (128U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG (unsigned char)_BV(3) /* Reset Pin Configuration */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x51 + + +#endif /* #ifdef _AVR_ATMEGA4809_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iom48a.h b/hardware/tools/avr/avr/include/avr/iom48a.h new file mode 100644 index 0000000000000000000000000000000000000000..8992147e874e443380245a4c27a1a91e8975069a --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom48a.h @@ -0,0 +1,35 @@ +/***************************************************************************** + * + * Copyright (C) 2011 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + +#include "iom48.h" +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) diff --git a/hardware/tools/avr/avr/include/avr/iom48p.h b/hardware/tools/avr/avr/include/avr/iom48p.h new file mode 100644 index 0000000000000000000000000000000000000000..57a0702b343b27d8b497cf8aad1af095be361318 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom48p.h @@ -0,0 +1,936 @@ +/* Copyright (c) 2007 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +/* $Id: iom48p.h 2225 2011-03-02 16:27:26Z arcanum $ */ + +/* avr/iom48p.h - definitions for ATmega48P. */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom48p.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_IOM48P_H_ +#define _AVR_IOM48P_H_ 1 + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +/* Only valid for ATmega88P-168P-328P */ +/* EEARH _SFR_IO8(0x22) */ + +#define EEPROM_REG_LOCATIONS 1F2021 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom48pa.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +#define EEARL _SFR_IO8(0x21) + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom48pb.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define ACSRB _SFR_IO8(0x0F) +#define ACOE 0 + +/* Reserved [0x10..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +#define EEARL _SFR_IO8(0x21) + +/* Reserved [0x22] */ + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom64.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* Input Pins, Port F */ +#define PINF _SFR_IO8(0x00) + +/* Input Pins, Port E */ +#define PINE _SFR_IO8(0x01) + +/* Data Direction Register, Port E */ +#define DDRE _SFR_IO8(0x02) + +/* Data Register, Port E */ +#define PORTE _SFR_IO8(0x03) + +/* ADC Data Register */ +#define ADCW _SFR_IO16(0x04) /* for backwards compatibility */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) + +/* ADC Control and Status Register A */ +#define ADCSR _SFR_IO8(0x06) /* for backwards compatibility */ +#define ADCSRA _SFR_IO8(0x06) + +/* ADC Multiplexer select */ +#define ADMUX _SFR_IO8(0x07) + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) + +/* USART0 Baud Rate Register Low */ +#define UBRR0L _SFR_IO8(0x09) + +/* USART0 Control and Status Register B */ +#define UCSR0B _SFR_IO8(0x0A) + +/* USART0 Control and Status Register A */ +#define UCSR0A _SFR_IO8(0x0B) + +/* USART0 I/O Data Register */ +#define UDR0 _SFR_IO8(0x0C) + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x0D) + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x0E) + +/* SPI I/O Data Register */ +#define SPDR _SFR_IO8(0x0F) + +/* Input Pins, Port D */ +#define PIND _SFR_IO8(0x10) + +/* Data Direction Register, Port D */ +#define DDRD _SFR_IO8(0x11) + +/* Data Register, Port D */ +#define PORTD _SFR_IO8(0x12) + +/* Input Pins, Port C */ +#define PINC _SFR_IO8(0x13) + +/* Data Direction Register, Port C */ +#define DDRC _SFR_IO8(0x14) + +/* Data Register, Port C */ +#define PORTC _SFR_IO8(0x15) + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* Input Pins, Port A */ +#define PINA _SFR_IO8(0x19) + +/* Data Direction Register, Port A */ +#define DDRA _SFR_IO8(0x1A) + +/* Data Register, Port A */ +#define PORTA _SFR_IO8(0x1B) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO16(0x1E) +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +/* Special Function I/O Register */ +#define SFIOR _SFR_IO8(0x20) + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* On-chip Debug Register */ +#define OCDR _SFR_IO8(0x22) + +/* Timer2 Output Compare Register */ +#define OCR2 _SFR_IO8(0x23) + +/* Timer/Counter 2 */ +#define TCNT2 _SFR_IO8(0x24) + +/* Timer/Counter 2 Control register */ +#define TCCR2 _SFR_IO8(0x25) + +/* T/C 1 Input Capture Register */ +#define ICR1 _SFR_IO16(0x26) +#define ICR1L _SFR_IO8(0x26) +#define ICR1H _SFR_IO8(0x27) + +/* Timer/Counter1 Output Compare Register B */ +#define OCR1B _SFR_IO16(0x28) +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Timer/Counter1 Output Compare Register A */ +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Timer/Counter 1 */ +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +/* Timer/Counter 1 Control and Status Register */ +#define TCCR1B _SFR_IO8(0x2E) + +/* Timer/Counter 1 Control Register */ +#define TCCR1A _SFR_IO8(0x2F) + +/* Timer/Counter 0 Asynchronous Control & Status Register */ +#define ASSR _SFR_IO8(0x30) + +/* Output Compare Register 0 */ +#define OCR0 _SFR_IO8(0x31) + +/* Timer/Counter 0 */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter 0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU Status Register */ +#define MCUSR _SFR_IO8(0x34) /* for backwards compatibility */ +#define MCUCSR _SFR_IO8(0x34) + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* Timer/Counter Interrupt Flag Register */ +#define TIFR _SFR_IO8(0x36) + +/* Timer/Counter Interrupt MaSK register */ +#define TIMSK _SFR_IO8(0x37) + +/* External Interrupt Flag Register */ +#define EIFR _SFR_IO8(0x38) + +/* External Interrupt MaSK register */ +#define EIMSK _SFR_IO8(0x39) + +/* External Interrupt Control Register B */ +#define EICRB _SFR_IO8(0x3A) + +/* XDIV Divide control register */ +#define XDIV _SFR_IO8(0x3C) + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Extended I/O registers */ + +/* Data Direction Register, Port F */ +#define DDRF _SFR_MEM8(0x61) + +/* Data Register, Port F */ +#define PORTF _SFR_MEM8(0x62) + +/* Input Pins, Port G */ +#define PING _SFR_MEM8(0x63) + +/* Data Direction Register, Port G */ +#define DDRG _SFR_MEM8(0x64) + +/* Data Register, Port G */ +#define PORTG _SFR_MEM8(0x65) + +/* Store Program Memory Control and Status Register */ +#define SPMCR _SFR_MEM8(0x68) +#define SPMCSR _SFR_MEM8(0x68) /* for backwards compatibility with m128*/ + +/* External Interrupt Control Register A */ +#define EICRA _SFR_MEM8(0x6A) + +/* External Memory Control Register B */ +#define XMCRB _SFR_MEM8(0x6C) + +/* External Memory Control Register A */ +#define XMCRA _SFR_MEM8(0x6D) + +/* Oscillator Calibration Register */ +#define OSCCAL _SFR_MEM8(0x6F) + +/* 2-wire Serial Interface Bit Rate Register */ +#define TWBR _SFR_MEM8(0x70) + +/* 2-wire Serial Interface Status Register */ +#define TWSR _SFR_MEM8(0x71) + +/* 2-wire Serial Interface Address Register */ +#define TWAR _SFR_MEM8(0x72) + +/* 2-wire Serial Interface Data Register */ +#define TWDR _SFR_MEM8(0x73) + +/* 2-wire Serial Interface Control Register */ +#define TWCR _SFR_MEM8(0x74) + +/* Time Counter 1 Output Compare Register C */ +#define OCR1C _SFR_MEM16(0x78) +#define OCR1CL _SFR_MEM8(0x78) +#define OCR1CH _SFR_MEM8(0x79) + +/* Timer/Counter 1 Control Register C */ +#define TCCR1C _SFR_MEM8(0x7A) + +/* Extended Timer Interrupt Flag Register */ +#define ETIFR _SFR_MEM8(0x7C) + +/* Extended Timer Interrupt Mask Register */ +#define ETIMSK _SFR_MEM8(0x7D) + +/* Timer/Counter 3 Input Capture Register */ +#define ICR3 _SFR_MEM16(0x80) +#define ICR3L _SFR_MEM8(0x80) +#define ICR3H _SFR_MEM8(0x81) + +/* Timer/Counter 3 Output Compare Register C */ +#define OCR3C _SFR_MEM16(0x82) +#define OCR3CL _SFR_MEM8(0x82) +#define OCR3CH _SFR_MEM8(0x83) + +/* Timer/Counter 3 Output Compare Register B */ +#define OCR3B _SFR_MEM16(0x84) +#define OCR3BL _SFR_MEM8(0x84) +#define OCR3BH _SFR_MEM8(0x85) + +/* Timer/Counter 3 Output Compare Register A */ +#define OCR3A _SFR_MEM16(0x86) +#define OCR3AL _SFR_MEM8(0x86) +#define OCR3AH _SFR_MEM8(0x87) + +/* Timer/Counter 3 Counter Register */ +#define TCNT3 _SFR_MEM16(0x88) +#define TCNT3L _SFR_MEM8(0x88) +#define TCNT3H _SFR_MEM8(0x89) + +/* Timer/Counter 3 Control Register B */ +#define TCCR3B _SFR_MEM8(0x8A) + +/* Timer/Counter 3 Control Register A */ +#define TCCR3A _SFR_MEM8(0x8B) + +/* Timer/Counter 3 Control Register C */ +#define TCCR3C _SFR_MEM8(0x8C) + +/* ADC Control and Status Register B */ +#define ADCSRB _SFR_MEM8(0x8E) + +/* USART0 Baud Rate Register High */ +#define UBRR0H _SFR_MEM8(0x90) + +/* USART0 Control and Status Register C */ +#define UCSR0C _SFR_MEM8(0x95) + +/* USART1 Baud Rate Register High */ +#define UBRR1H _SFR_MEM8(0x98) + +/* USART1 Baud Rate Register Low*/ +#define UBRR1L _SFR_MEM8(0x99) + +/* USART1 Control and Status Register B */ +#define UCSR1B _SFR_MEM8(0x9A) + +/* USART1 Control and Status Register A */ +#define UCSR1A _SFR_MEM8(0x9B) + +/* USART1 I/O Data Register */ +#define UDR1 _SFR_MEM8(0x9C) + +/* USART1 Control and Status Register C */ +#define UCSR1C _SFR_MEM8(0x9D) + +/* Interrupt vectors */ + +/* External Interrupt Request 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt Request 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* External Interrupt Request 2 */ +#define INT2_vect_num 3 +#define INT2_vect _VECTOR(3) +#define SIG_INTERRUPT2 _VECTOR(3) + +/* External Interrupt Request 3 */ +#define INT3_vect_num 4 +#define INT3_vect _VECTOR(4) +#define SIG_INTERRUPT3 _VECTOR(4) + +/* External Interrupt Request 4 */ +#define INT4_vect_num 5 +#define INT4_vect _VECTOR(5) +#define SIG_INTERRUPT4 _VECTOR(5) + +/* External Interrupt Request 5 */ +#define INT5_vect_num 6 +#define INT5_vect _VECTOR(6) +#define SIG_INTERRUPT5 _VECTOR(6) + +/* External Interrupt Request 6 */ +#define INT6_vect_num 7 +#define INT6_vect _VECTOR(7) +#define SIG_INTERRUPT6 _VECTOR(7) + +/* External Interrupt Request 7 */ +#define INT7_vect_num 8 +#define INT7_vect _VECTOR(8) +#define SIG_INTERRUPT7 _VECTOR(8) + +/* Timer/Counter2 Compare Match */ +#define TIMER2_COMP_vect_num 9 +#define TIMER2_COMP_vect _VECTOR(9) +#define SIG_OUTPUT_COMPARE2 _VECTOR(9) + +/* Timer/Counter2 Overflow */ +#define TIMER2_OVF_vect_num 10 +#define TIMER2_OVF_vect _VECTOR(10) +#define SIG_OVERFLOW2 _VECTOR(10) + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect_num 11 +#define TIMER1_CAPT_vect _VECTOR(11) +#define SIG_INPUT_CAPTURE1 _VECTOR(11) + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect_num 12 +#define TIMER1_COMPA_vect _VECTOR(12) +#define SIG_OUTPUT_COMPARE1A _VECTOR(12) + +/* Timer/Counter Compare Match B */ +#define TIMER1_COMPB_vect_num 13 +#define TIMER1_COMPB_vect _VECTOR(13) +#define SIG_OUTPUT_COMPARE1B _VECTOR(13) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 14 +#define TIMER1_OVF_vect _VECTOR(14) +#define SIG_OVERFLOW1 _VECTOR(14) + +/* Timer/Counter0 Compare Match */ +#define TIMER0_COMP_vect_num 15 +#define TIMER0_COMP_vect _VECTOR(15) +#define SIG_OUTPUT_COMPARE0 _VECTOR(15) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 16 +#define TIMER0_OVF_vect _VECTOR(16) +#define SIG_OVERFLOW0 _VECTOR(16) + +/* SPI Serial Transfer Complete */ +#define SPI_STC_vect_num 17 +#define SPI_STC_vect _VECTOR(17) +#define SIG_SPI _VECTOR(17) + +/* USART0, Rx Complete */ +#define USART0_RX_vect_num 18 +#define USART0_RX_vect _VECTOR(18) +#define SIG_UART0_RECV _VECTOR(18) + +/* USART0 Data Register Empty */ +#define USART0_UDRE_vect_num 19 +#define USART0_UDRE_vect _VECTOR(19) +#define SIG_UART0_DATA _VECTOR(19) + +/* USART0, Tx Complete */ +#define USART0_TX_vect_num 20 +#define USART0_TX_vect _VECTOR(20) +#define SIG_UART0_TRANS _VECTOR(20) + +/* ADC Conversion Complete */ +#define ADC_vect_num 21 +#define ADC_vect _VECTOR(21) +#define SIG_ADC _VECTOR(21) + +/* EEPROM Ready */ +#define EE_READY_vect_num 22 +#define EE_READY_vect _VECTOR(22) +#define SIG_EEPROM_READY _VECTOR(22) + +/* Analog Comparator */ +#define ANALOG_COMP_vect_num 23 +#define ANALOG_COMP_vect _VECTOR(23) +#define SIG_COMPARATOR _VECTOR(23) + +/* Timer/Counter1 Compare Match C */ +#define TIMER1_COMPC_vect_num 24 +#define TIMER1_COMPC_vect _VECTOR(24) +#define SIG_OUTPUT_COMPARE1C _VECTOR(24) + +/* Timer/Counter3 Capture Event */ +#define TIMER3_CAPT_vect_num 25 +#define TIMER3_CAPT_vect _VECTOR(25) +#define SIG_INPUT_CAPTURE3 _VECTOR(25) + +/* Timer/Counter3 Compare Match A */ +#define TIMER3_COMPA_vect_num 26 +#define TIMER3_COMPA_vect _VECTOR(26) +#define SIG_OUTPUT_COMPARE3A _VECTOR(26) + +/* Timer/Counter3 Compare Match B */ +#define TIMER3_COMPB_vect_num 27 +#define TIMER3_COMPB_vect _VECTOR(27) +#define SIG_OUTPUT_COMPARE3B _VECTOR(27) + +/* Timer/Counter3 Compare Match C */ +#define TIMER3_COMPC_vect_num 28 +#define TIMER3_COMPC_vect _VECTOR(28) +#define SIG_OUTPUT_COMPARE3C _VECTOR(28) + +/* Timer/Counter3 Overflow */ +#define TIMER3_OVF_vect_num 29 +#define TIMER3_OVF_vect _VECTOR(29) +#define SIG_OVERFLOW3 _VECTOR(29) + +/* USART1, Rx Complete */ +#define USART1_RX_vect_num 30 +#define USART1_RX_vect _VECTOR(30) +#define SIG_UART1_RECV _VECTOR(30) + +/* USART1, Data Register Empty */ +#define USART1_UDRE_vect_num 31 +#define USART1_UDRE_vect _VECTOR(31) +#define SIG_UART1_DATA _VECTOR(31) + +/* USART1, Tx Complete */ +#define USART1_TX_vect_num 32 +#define USART1_TX_vect _VECTOR(32) +#define SIG_UART1_TRANS _VECTOR(32) + +/* 2-wire Serial Interface */ +#define TWI_vect_num 33 +#define TWI_vect _VECTOR(33) +#define SIG_2WIRE_SERIAL _VECTOR(33) + +/* Store Program Memory Read */ +#define SPM_READY_vect_num 34 +#define SPM_READY_vect _VECTOR(34) +#define SIG_SPM_READY _VECTOR(34) + +#define _VECTORS_SIZE 140 + +/* + The Register Bit names are represented by their bit number (0-7). +*/ + +/* 2-wire Control Register - TWCR */ +#define TWINT 7 +#define TWEA 6 +#define TWSTA 5 +#define TWSTO 4 +#define TWWC 3 +#define TWEN 2 +#define TWIE 0 + +/* 2-wire Address Register - TWAR */ +#define TWA6 7 +#define TWA5 6 +#define TWA4 5 +#define TWA3 4 +#define TWA2 3 +#define TWA1 2 +#define TWA0 1 +#define TWGCE 0 + +/* 2-wire Status Register - TWSR */ +#define TWS7 7 +#define TWS6 6 +#define TWS5 5 +#define TWS4 4 +#define TWS3 3 +#define TWPS1 1 +#define TWPS0 0 + +/* External Memory Control Register A - XMCRA */ +#define SRL2 6 +#define SRL1 5 +#define SRL0 4 +#define SRW01 3 +#define SRW00 2 +#define SRW11 1 + +/* External Memory Control Register B - XMCRA */ +#define XMBK 7 +#define XMM2 2 +#define XMM1 1 +#define XMM0 0 + +/* XDIV Divide control register - XDIV */ +#define XDIVEN 7 +#define XDIV6 6 +#define XDIV5 5 +#define XDIV4 4 +#define XDIV3 3 +#define XDIV2 2 +#define XDIV1 1 +#define XDIV0 0 + +/* External Interrupt Control Register A - EICRA */ +#define ISC31 7 +#define ISC30 6 +#define ISC21 5 +#define ISC20 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/* External Interrupt Control Register B - EICRB */ +#define ISC71 7 +#define ISC70 6 +#define ISC61 5 +#define ISC60 4 +#define ISC51 3 +#define ISC50 2 +#define ISC41 1 +#define ISC40 0 + +/* Store Program Memory Control Register - SPMCSR, SPMCR */ +#define SPMIE 7 +#define RWWSB 6 +#define RWWSRE 4 +#define BLBSET 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 + +/* External Interrupt MaSK register - EIMSK */ +#define INT7 7 +#define INT6 6 +#define INT5 5 +#define INT4 4 +#define INT3 3 +#define INT2 2 +#define INT1 1 +#define INT0 0 + +/* External Interrupt Flag Register - EIFR */ +#define INTF7 7 +#define INTF6 6 +#define INTF5 5 +#define INTF4 4 +#define INTF3 3 +#define INTF2 2 +#define INTF1 1 +#define INTF0 0 + +/* Timer/Counter Interrupt MaSK register - TIMSK */ +#define OCIE2 7 +#define TOIE2 6 +#define TICIE1 5 +#define OCIE1A 4 +#define OCIE1B 3 +#define TOIE1 2 +#define OCIE0 1 +#define TOIE0 0 + +/* Timer/Counter Interrupt Flag Register - TIFR */ +#define OCF2 7 +#define TOV2 6 +#define ICF1 5 +#define OCF1A 4 +#define OCF1B 3 +#define TOV1 2 +#define OCF0 1 +#define TOV0 0 + +/* Extended Timer Interrupt MaSK register - ETIMSK */ +#define TICIE3 5 +#define OCIE3A 4 +#define OCIE3B 3 +#define TOIE3 2 +#define OCIE3C 1 +#define OCIE1C 0 + +/* Extended Timer Interrupt Flag Register - ETIFR */ +#define ICF3 5 +#define OCF3A 4 +#define OCF3B 3 +#define TOV3 2 +#define OCF3C 1 +#define OCF1C 0 + +/* MCU Control Register - MCUCR */ +#define SRE 7 +#define SRW10 6 +#define SE 5 +#define SM1 4 +#define SM0 3 +#define SM2 2 +#define IVSEL 1 +#define IVCE 0 + +/* MCU Control And Status Register - MCUCSR */ +#define JTD 7 +#define JTRF 4 +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +/* Timer/Counter Control Register (generic) */ +#define FOC 7 +#define WGM0 6 +#define COM1 5 +#define COM0 4 +#define WGM1 3 +#define CS2 2 +#define CS1 1 +#define CS0 0 + +/* Timer/Counter 0 Control Register - TCCR0 */ +#define FOC0 7 +#define WGM00 6 +#define COM01 5 +#define COM00 4 +#define WGM01 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* Timer/Counter 2 Control Register - TCCR2 */ +#define FOC2 7 +#define WGM20 6 +#define COM21 5 +#define COM20 4 +#define WGM21 3 +#define CS22 2 +#define CS21 1 +#define CS20 0 + +/* Timer/Counter 0 Asynchronous Control & Status Register - ASSR */ +#define AS0 3 +#define TCN0UB 2 +#define OCR0UB 1 +#define TCR0UB 0 + +/* Timer/Counter Control Register A (generic) */ +#define COMA1 7 +#define COMA0 6 +#define COMB1 5 +#define COMB0 4 +#define COMC1 3 +#define COMC0 2 +#define WGMA1 1 +#define WGMA0 0 + +/* Timer/Counter 1 Control and Status Register A - TCCR1A */ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define COM1C1 3 +#define COM1C0 2 +#define WGM11 1 +#define WGM10 0 + +/* Timer/Counter 3 Control and Status Register A - TCCR3A */ +#define COM3A1 7 +#define COM3A0 6 +#define COM3B1 5 +#define COM3B0 4 +#define COM3C1 3 +#define COM3C0 2 +#define WGM31 1 +#define WGM30 0 + +/* Timer/Counter Control and Status Register B (generic) */ +#define ICNC 7 +#define ICES 6 +#define WGMB3 4 +#define WGMB2 3 +#define CSB2 2 +#define CSB1 1 +#define CSB0 0 + +/* Timer/Counter 1 Control and Status Register B - TCCR1B */ +#define ICNC1 7 +#define ICES1 6 +#define WGM13 4 +#define WGM12 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* Timer/Counter 3 Control and Status Register B - TCCR3B */ +#define ICNC3 7 +#define ICES3 6 +#define WGM33 4 +#define WGM32 3 +#define CS32 2 +#define CS31 1 +#define CS30 0 + +/* Timer/Counter Control Register C (generic) */ +#define FOCA 7 +#define FOCB 6 +#define FOCC 5 + +/* Timer/Counter 3 Control Register C - TCCR3C */ +#define FOC3A 7 +#define FOC3B 6 +#define FOC3C 5 + +/* Timer/Counter 1 Control Register C - TCCR1C */ +#define FOC1A 7 +#define FOC1B 6 +#define FOC1C 5 + +/* On-chip Debug Register - OCDR */ +#define IDRD 7 +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Watchdog Timer Control Register - WDTCR */ +#define WDCE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* + The ADHSM bit has been removed from all documentation, + as being not needed at all since the comparator has proven + to be fast enough even without feeding it more power. +*/ + +/* Special Function I/O Register - SFIOR */ +#define TSM 7 +#define ACME 3 +#define PUD 2 +#define PSR0 1 +#define PSR321 0 + +/* Port Data Register (generic) */ +#define PORT7 7 +#define PORT6 6 +#define PORT5 5 +#define PORT4 4 +#define PORT3 3 +#define PORT2 2 +#define PORT1 1 +#define PORT0 0 + +/* Port Data Direction Register (generic) */ +#define DD7 7 +#define DD6 6 +#define DD5 5 +#define DD4 4 +#define DD3 3 +#define DD2 2 +#define DD1 1 +#define DD0 0 + +/* Port Input Pins (generic) */ +#define PIN7 7 +#define PIN6 6 +#define PIN5 5 +#define PIN4 4 +#define PIN3 3 +#define PIN2 2 +#define PIN1 1 +#define PIN0 0 + +/* SPI Status Register - SPSR */ +#define SPIF 7 +#define WCOL 6 +#define SPI2X 0 + +/* SPI Control Register - SPCR */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* USART Register C (generic) */ +#define UMSEL 6 +#define UPM1 5 +#define UPM0 4 +#define USBS 3 +#define UCSZ1 2 +#define UCSZ0 1 +#define UCPOL 0 + +/* USART1 Register C - UCSR1C */ +#define UMSEL1 6 +#define UPM11 5 +#define UPM10 4 +#define USBS1 3 +#define UCSZ11 2 +#define UCSZ10 1 +#define UCPOL1 0 + +/* USART0 Register C - UCSR0C */ +#define UMSEL0 6 +#define UPM01 5 +#define UPM00 4 +#define USBS0 3 +#define UCSZ01 2 +#define UCSZ00 1 +#define UCPOL0 0 + +/* USART Status Register A (generic) */ +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 +#define UPE 2 +#define U2X 1 +#define MPCM 0 + +/* USART1 Status Register A - UCSR1A */ +#define RXC1 7 +#define TXC1 6 +#define UDRE1 5 +#define FE1 4 +#define DOR1 3 +#define UPE1 2 +#define U2X1 1 +#define MPCM1 0 + +/* USART0 Status Register A - UCSR0A */ +#define RXC0 7 +#define TXC0 6 +#define UDRE0 5 +#define FE0 4 +#define DOR0 3 +#define UPE0 2 +#define U2X0 1 +#define MPCM0 0 + +/* USART Control Register B (generic) */ +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define UCSZ 2 +#define UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ +#define RXB8 1 +#define TXB8 0 + +/* USART1 Control Register B - UCSR1B */ +#define RXCIE1 7 +#define TXCIE1 6 +#define UDRIE1 5 +#define RXEN1 4 +#define TXEN1 3 +#define UCSZ12 2 +#define RXB81 1 +#define TXB81 0 + +/* USART0 Control Register B - UCSR0B */ +#define RXCIE0 7 +#define TXCIE0 6 +#define UDRIE0 5 +#define RXEN0 4 +#define TXEN0 3 +#define UCSZ02 2 +#define RXB80 1 +#define TXB80 0 + +/* Analog Comparator Control and Status Register - ACSR */ +#define ACD 7 +#define ACBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +/* ADC Control and Status Register B - ADCSRB */ +#define ADTS2 2 +#define ADTS1 1 +#define ADTS0 0 + +/* ADC Control and status Register A - ADCSRA */ +#define ADEN 7 +#define ADSC 6 +#define ADATE 5 +#define ADIF 4 +#define ADIE 3 +#define ADPS2 2 +#define ADPS1 1 +#define ADPS0 0 + +/* ADC Multiplexer select - ADMUX */ +#define REFS1 7 +#define REFS0 6 +#define ADLAR 5 +#define MUX4 4 +#define MUX3 3 +#define MUX2 2 +#define MUX1 1 +#define MUX0 0 + +/* Port A Data Register - PORTA */ +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* Port A Data Direction Register - DDRA */ +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +/* Port A Input Pins - PINA */ +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +/* Port B Data Register - PORTB */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Port B Data Direction Register - DDRB */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Port B Input Pins - PINB */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* Port C Data Register - PORTC */ +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* Port C Data Direction Register - DDRC */ +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +/* Port C Input Pins - PINC */ +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +/* Port D Data Register - PORTD */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* Port D Data Direction Register - DDRD */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* Port D Input Pins - PIND */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* Port E Data Register - PORTE */ +#define PE7 7 +#define PE6 6 +#define PE5 5 +#define PE4 4 +#define PE3 3 +#define PE2 2 +#define PE1 1 +#define PE0 0 + +/* Port E Data Direction Register - DDRE */ +#define DDE7 7 +#define DDE6 6 +#define DDE5 5 +#define DDE4 4 +#define DDE3 3 +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +/* Port E Input Pins - PINE */ +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +/* Port F Data Register - PORTF */ +#define PF7 7 +#define PF6 6 +#define PF5 5 +#define PF4 4 +#define PF3 3 +#define PF2 2 +#define PF1 1 +#define PF0 0 + +/* Port F Data Direction Register - DDRF */ +#define DDF7 7 +#define DDF6 6 +#define DDF5 5 +#define DDF4 4 +#define DDF3 3 +#define DDF2 2 +#define DDF1 1 +#define DDF0 0 + +/* Port F Input Pins - PINF */ +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +/* Port G Data Register - PORTG */ +#define PG4 4 +#define PG3 3 +#define PG2 2 +#define PG1 1 +#define PG0 0 + +/* Port G Data Direction Register - DDRG */ +#define DDG4 4 +#define DDG3 3 +#define DDG2 2 +#define DDG1 1 +#define DDG0 0 + +/* Port G Input Pins - PING */ +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define SPM_PAGESIZE 256 +#define RAMSTART 0x100 +#define RAMEND 0x10FF /* Last On-Chip SRAM Location */ +#define XRAMEND 0xFFFF +#define E2END 0x07FF +#define E2PAGESIZE 8 +#define FLASHEND 0xFFFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_BODEN (unsigned char)~_BV(6) +#define FUSE_BODLEVEL (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_CKOPT (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + +/* Extended Fuse Byte */ +#define FUSE_WDTON (unsigned char)~_BV(0) +#define FUSE_M103C (unsigned char)~_BV(1) +#define EFUSE_DEFAULT (FUSE_M103C) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x02 + + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_INTERRUPT1 +#pragma GCC poison SIG_INTERRUPT2 +#pragma GCC poison SIG_INTERRUPT3 +#pragma GCC poison SIG_INTERRUPT4 +#pragma GCC poison SIG_INTERRUPT5 +#pragma GCC poison SIG_INTERRUPT6 +#pragma GCC poison SIG_INTERRUPT7 +#pragma GCC poison SIG_OUTPUT_COMPARE2 +#pragma GCC poison SIG_OVERFLOW2 +#pragma GCC poison SIG_INPUT_CAPTURE1 +#pragma GCC poison SIG_OUTPUT_COMPARE1A +#pragma GCC poison SIG_OUTPUT_COMPARE1B +#pragma GCC poison SIG_OVERFLOW1 +#pragma GCC poison SIG_OUTPUT_COMPARE0 +#pragma GCC poison SIG_OVERFLOW0 +#pragma GCC poison SIG_SPI +#pragma GCC poison SIG_UART0_RECV +#pragma GCC poison SIG_UART0_DATA +#pragma GCC poison SIG_UART0_TRANS +#pragma GCC poison SIG_ADC +#pragma GCC poison SIG_EEPROM_READY +#pragma GCC poison SIG_COMPARATOR +#pragma GCC poison SIG_OUTPUT_COMPARE1C +#pragma GCC poison SIG_INPUT_CAPTURE3 +#pragma GCC poison SIG_OUTPUT_COMPARE3A +#pragma GCC poison SIG_OUTPUT_COMPARE3B +#pragma GCC poison SIG_OUTPUT_COMPARE3C +#pragma GCC poison SIG_OVERFLOW3 +#pragma GCC poison SIG_UART1_RECV +#pragma GCC poison SIG_UART1_DATA +#pragma GCC poison SIG_UART1_TRANS +#pragma GCC poison SIG_2WIRE_SERIAL +#pragma GCC poison SIG_SPM_READY + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + +#define SLEEP_MODE_IDLE (0x00<<2) +#define SLEEP_MODE_ADC (0x02<<2) +#define SLEEP_MODE_PWR_DOWN (0x04<<2) +#define SLEEP_MODE_PWR_SAVE (0x06<<2) +#define SLEEP_MODE_STANDBY (0x05<<2) +#define SLEEP_MODE_EXT_STANDBY (0x07<<2) + +#endif /* _AVR_IOM64_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom640.h b/hardware/tools/avr/avr/include/avr/iom640.h new file mode 100644 index 0000000000000000000000000000000000000000..92574e86bea4dc7faed483db33b04376b635404d --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom640.h @@ -0,0 +1,101 @@ +/* Copyright (c) 2005 Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom640.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ + +/* avr/iom640.h - definitions for ATmega640 */ + +#ifndef _AVR_IOM640_H_ +#define _AVR_IOM640_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 256 +#define RAMSTART 0x200 +#define RAMEND 0x21FF +#define XRAMEND 0xFFFF +#define E2END 0xFFF +#define E2PAGESIZE 8 +#define FLASHEND 0xFFFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + +/* Extended Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x08 + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +#endif /* _AVR_IOM640_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom644.h b/hardware/tools/avr/avr/include/avr/iom644.h new file mode 100644 index 0000000000000000000000000000000000000000..c8dba8416e0da9d42bb238b57e56e5550dc31672 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom644.h @@ -0,0 +1,101 @@ +/* Copyright (c) 2005 Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* avr/iom644.h - definitions for ATmega644 */ + +/* $Id: iom644.h 2115 2010-04-05 23:19:53Z arcanum $ */ + +#ifndef _AVR_IOM644_H_ +#define _AVR_IOM644_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 256 +#define RAMSTART (0x100) +#define RAMEND 0x10FF +#define XRAMEND RAMEND +#define E2END 0x7FF +#define E2PAGESIZE 8 +#define FLASHEND 0xFFFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + +/* Extended Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x09 + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +#endif /* _AVR_IOM644_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom644a.h b/hardware/tools/avr/avr/include/avr/iom644a.h new file mode 100644 index 0000000000000000000000000000000000000000..49d4e3b20717380ba903b5ebbd06f49641fcf15d --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom644a.h @@ -0,0 +1,34 @@ +/***************************************************************************** + * + * Copyright (C) 2011 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + +#include "iom644.h" diff --git a/hardware/tools/avr/avr/include/avr/iom644p.h b/hardware/tools/avr/avr/include/avr/iom644p.h new file mode 100644 index 0000000000000000000000000000000000000000..e0e609417b24d45c387f909acd5fb110c2966d3a --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom644p.h @@ -0,0 +1,101 @@ +/* Copyright (c) 2005 Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* avr/iom644p.h - definitions for ATmega644P */ + +/* $Id: iom644p.h 2115 2010-04-05 23:19:53Z arcanum $ */ + +#ifndef _AVR_IOM644P_H_ +#define _AVR_IOM644P_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 256 +#define RAMSTART (0x100) +#define RAMEND 0x10FF +#define XRAMEND RAMEND +#define E2END 0x7FF +#define E2PAGESIZE 8 +#define FLASHEND 0xFFFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + +/* Extended Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x0A + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +#endif /* _AVR_IOM644P_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom644pa.h b/hardware/tools/avr/avr/include/avr/iom644pa.h new file mode 100644 index 0000000000000000000000000000000000000000..5c3f3a8b8640d0d1f60343a7ebdd0dc93ad68783 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom644pa.h @@ -0,0 +1,1387 @@ +/* Copyright (c) 2009 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom644pa.h 2035 2009-11-02 02:44:17Z arcanum $ */ + +/* avr/iom644PA.h - definitions for ATmega644PA */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom644PA.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega644PA_H_ +#define _AVR_ATmega644PA_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINA _SFR_IO8(0x00) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 +#define PINA4 4 +#define PINA5 5 +#define PINA6 6 +#define PINA7 7 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 +#define PORTA4 4 +#define PORTA5 5 +#define PORTA6 6 +#define PORTA7 7 + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 +#define EEAR10 2 +#define EEAR11 3 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 +#define JTD 7 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR0 _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRUSART1 4 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom644rfr2.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_IO8(0x12) +#define PING7 7 +#define PING6 6 +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDRG7 7 +// Inserted "DDG7" from "DDRG7" due to compatibility +#define DDG7 7 +#define DDRG6 6 +// Inserted "DDG6" from "DDRG6" due to compatibility +#define DDG6 6 +#define DDRG5 5 +// Inserted "DDG5" from "DDRG5" due to compatibility +#define DDG5 5 +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PORTG7 7 +#define PORTG6 6 +#define PORTG5 5 +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define Res0 3 +#define Res1 4 +#define Res2 5 +#define Res3 6 +#define Res4 7 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define OCF1C 3 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define OCF3C 3 +#define ICF3 5 + +#define TIFR4 _SFR_IO8(0x19) +#define TOV4 0 +#define OCF4A 1 +#define OCF4B 2 +#define OCF4C 3 +#define ICF4 5 + +#define TIFR5 _SFR_IO8(0x1A) +#define TOV5 0 +#define OCF5A 1 +#define OCF5B 2 +#define OCF5C 3 +#define ICF5 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62] */ + +#define PRR2 _SFR_MEM8(0x63) +#define PRRAM0 0 +#define PRRAM1 1 +#define PRRAM2 2 +#define PRRAM3 3 + +#define __AVR_HAVE_PRR2 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom645.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDE7 7 +#define DDE6 6 +#define DDE5 5 +#define DDE4 4 +#define DDE3 3 +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PE7 7 +#define PE6 6 +#define PE5 5 +#define PE4 4 +#define PE3 3 +#define PE2 2 +#define PE1 1 +#define PE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDF7 7 +#define DDF6 6 +#define DDF5 5 +#define DDF4 4 +#define DDF3 3 +#define DDF2 2 +#define DDF1 1 +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PF7 7 +#define PF6 6 +#define PF5 5 +#define PF4 4 +#define PF3 3 +#define PF2 2 +#define PF1 1 +#define PF0 0 + +#define PING _SFR_IO8(0x12) +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDG4 4 +#define DDG3 3 +#define DDG2 2 +#define DDG1 1 +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PG4 4 +#define PG3 3 +#define PG2 2 +#define PG1 1 +#define PG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 + +/* Reserved [0x18..0x1B] */ + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define PCIF0 4 +#define PCIF1 5 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define PCIE0 4 +#define PCIE1 5 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0X20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0X22) + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 +#define PSR2 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM0A0 4 +#define COM0A1 5 +#define WGM00 6 +#define FOC0A 7 + +/* Reserved [0x25] */ + +#define TCNT0 _SFR_IO8(0X26) + +#define OCR0A _SFR_IO8(0X27) + +/* Reserved [0x28..0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0X2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 +#define IDRD 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +#define MCUCR _SFR_IO8(0X35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define JTD 7 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom6450.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDE7 7 +#define DDE6 6 +#define DDE5 5 +#define DDE4 4 +#define DDE3 3 +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PE7 7 +#define PE6 6 +#define PE5 5 +#define PE4 4 +#define PE3 3 +#define PE2 2 +#define PE1 1 +#define PE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDF7 7 +#define DDF6 6 +#define DDF5 5 +#define DDF4 4 +#define DDF3 3 +#define DDF2 2 +#define DDF1 1 +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PF7 7 +#define PF6 6 +#define PF5 5 +#define PF4 4 +#define PF3 3 +#define PF2 2 +#define PF1 1 +#define PF0 0 + +#define PING _SFR_IO8(0x12) +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDG4 4 +#define DDG3 3 +#define DDG2 2 +#define DDG1 1 +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PG4 4 +#define PG3 3 +#define PG2 2 +#define PG1 1 +#define PG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 + +/* Reserved [0x18..0x1B] */ + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define PCIF0 4 +#define PCIF1 5 +#define PCIF2 6 +#define PCIF3 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define PCIE0 4 +#define PCIE1 5 +#define PCIE2 6 +#define PCIE3 7 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0X20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0X22) + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 +#define PSR2 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM0A0 4 +#define COM0A1 5 +#define WGM00 6 +#define FOC0A 7 + +/* Reserved [0x25] */ + +#define TCNT0 _SFR_IO8(0X26) + +#define OCR0A _SFR_IO8(0X27) + +/* Reserved [0x28..0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0X2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 +#define IDRD 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +#define MCUCR _SFR_IO8(0X35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define JTD 7 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom649.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDE7 7 +#define DDE6 6 +#define DDE5 5 +#define DDE4 4 +#define DDE3 3 +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PE7 7 +#define PE6 6 +#define PE5 5 +#define PE4 4 +#define PE3 3 +#define PE2 2 +#define PE1 1 +#define PE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDF7 7 +#define DDF6 6 +#define DDF5 5 +#define DDF4 4 +#define DDF3 3 +#define DDF2 2 +#define DDF1 1 +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PF7 7 +#define PF6 6 +#define PF5 5 +#define PF4 4 +#define PF3 3 +#define PF2 2 +#define PF1 1 +#define PF0 0 + +#define PING _SFR_IO8(0x12) +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDG4 4 +#define DDG3 3 +#define DDG2 2 +#define DDG1 1 +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PG4 4 +#define PG3 3 +#define PG2 2 +#define PG1 1 +#define PG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 + +/* Reserved [0x18..0x1B] */ + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define PCIF0 4 +#define PCIF1 5 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define PCIE0 4 +#define PCIE1 5 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +#define EEDR _SFR_IO8(0X20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0X22) + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 +#define PSR2 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM0A0 4 +#define COM0A1 5 +#define WGM00 6 +#define FOC0A 7 + +/* Reserved [0x25] */ + +#define TCNT0 _SFR_IO8(0X26) + +#define OCR0A _SFR_IO8(0X27) + +/* Reserved [0x28..0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0X2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 +#define IDRD 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +#define MCUCR _SFR_IO8(0X35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define JTD 7 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRLCD 4 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom6490.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDE7 7 +#define DDE6 6 +#define DDE5 5 +#define DDE4 4 +#define DDE3 3 +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PE7 7 +#define PE6 6 +#define PE5 5 +#define PE4 4 +#define PE3 3 +#define PE2 2 +#define PE1 1 +#define PE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDF7 7 +#define DDF6 6 +#define DDF5 5 +#define DDF4 4 +#define DDF3 3 +#define DDF2 2 +#define DDF1 1 +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PF7 7 +#define PF6 6 +#define PF5 5 +#define PF4 4 +#define PF3 3 +#define PF2 2 +#define PF1 1 +#define PF0 0 + +#define PING _SFR_IO8(0x12) +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDG4 4 +#define DDG3 3 +#define DDG2 2 +#define DDG1 1 +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PG4 4 +#define PG3 3 +#define PG2 2 +#define PG1 1 +#define PG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 + +/* Reserved [0x18..0x1B] */ + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define PCIF0 4 +#define PCIF1 5 +#define PCIF2 6 +#define PCIF3 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define PCIE0 4 +#define PCIE1 5 +#define PCIE2 6 +#define PCIE3 7 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +#define EEDR _SFR_IO8(0X20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0X22) + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 +#define PSR2 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM0A0 4 +#define COM0A1 5 +#define WGM00 6 +#define FOC0A 7 + +/* Reserved [0x25] */ + +#define TCNT0 _SFR_IO8(0X26) + +#define OCR0A _SFR_IO8(0X27) + +/* Reserved [0x28..0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0X2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 +#define IDRD 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +#define MCUCR _SFR_IO8(0X35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define JTD 7 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRLCD 4 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom649p.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega649_H_ +#define _AVR_ATmega649_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINA _SFR_IO8(0x00) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 +#define PINA4 4 +#define PINA5 5 +#define PINA6 6 +#define PINA7 7 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 +#define PORTA4 4 +#define PORTA5 5 +#define PORTA6 6 +#define PORTA7 7 + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define PINE _SFR_IO8(0x0C) +#define PINE0 0 +#define PINE1 1 +#define PINE2 2 +#define PINE3 3 +#define PINE4 4 +#define PINE5 5 +#define PINE6 6 +#define PINE7 7 + +#define DDRE _SFR_IO8(0x0D) +#define DDE0 0 +#define DDE1 1 +#define DDE2 2 +#define DDE3 3 +#define DDE4 4 +#define DDE5 5 +#define DDE6 6 +#define DDE7 7 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE0 0 +#define PORTE1 1 +#define PORTE2 2 +#define PORTE3 3 +#define PORTE4 4 +#define PORTE5 5 +#define PORTE6 6 +#define PORTE7 7 + +#define PINF _SFR_IO8(0x0F) +#define PINF0 0 +#define PINF1 1 +#define PINF2 2 +#define PINF3 3 +#define PINF4 4 +#define PINF5 5 +#define PINF6 6 +#define PINF7 7 + +#define DDRF _SFR_IO8(0x10) +#define DDF0 0 +#define DDF1 1 +#define DDF2 2 +#define DDF3 3 +#define DDF4 4 +#define DDF5 5 +#define DDF6 6 +#define DDF7 7 + +#define PORTF _SFR_IO8(0x11) +#define PORTF0 0 +#define PORTF1 1 +#define PORTF2 2 +#define PORTF3 3 +#define PORTF4 4 +#define PORTF5 5 +#define PORTF6 6 +#define PORTF7 7 + +#define PING _SFR_IO8(0x12) +#define PING0 0 +#define PING1 1 +#define PING2 2 +#define PING3 3 +#define PING4 4 +#define PING5 5 + +#define DDRG _SFR_IO8(0x13) +#define DDG0 0 +#define DDG1 1 +#define DDG2 2 +#define DDG3 3 +#define DDG4 4 + +#define PORTG _SFR_IO8(0x14) +#define PORTG0 0 +#define PORTG1 1 +#define PORTG2 2 +#define PORTG3 3 +#define PORTG4 4 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define PCIF0 4 +#define PCIF1 5 +#define PCIF2 6 +#define PCIF3 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define PCIE0 4 +#define PCIE1 5 +#define PCIE2 6 +#define PCIE3 7 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARL0 0 +#define EEARL1 1 +#define EEARL2 2 +#define EEARL3 3 +#define EEARL4 4 +#define EEARL5 5 +#define EEARL6 6 +#define EEARL7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 +#define EEAR10 2 + +#define GTCCR _SFR_IO8(0x23) +#define PSR310 0 +#define PSR2 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM0A0 4 +#define COM0A1 5 +#define WGM00 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A0 0 +#define OCR0A1 1 +#define OCR0A2 2 +#define OCR0A3 3 +#define OCR0A4 4 +#define OCR0A5 5 +#define OCR0A6 6 +#define OCR0A7 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define JTD 7 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRLCD 4 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom64a.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINF _SFR_IO8(0x00) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define PINE _SFR_IO8(0x01) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x02) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x03) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +/* Combine ADCL and ADCH */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) + +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) + +#define ADCSRA _SFR_IO8(0x06) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +#define ADMUX _SFR_IO8(0x07) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define MUX4 4 +#define ADLAR 5 +#define REFS0 6 +#define REFS1 7 + +#define ACSR _SFR_IO8(0x08) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define UBRR0L _SFR_IO8(0x09) + +#define UCSR0B _SFR_IO8(0x0A) +#define TXB80 0 +#define RXB80 1 +#define UCSZ02 2 +#define TXEN0 3 +#define RXEN0 4 +#define UDRIE0 5 +#define TXCIE0 6 +#define RXCIE0 7 + +#define UCSR0A _SFR_IO8(0x0B) +#define MPCM0 0 +#define U2X0 1 +#define UPE0 2 +#define DOR0 3 +#define FE0 4 +#define UDRE0 5 +#define TXC0 6 +#define RXC0 7 + +#define UDR0 _SFR_IO8(0x0C) + +#define SPCR _SFR_IO8(0x0D) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x0E) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x0F) + +#define PIND _SFR_IO8(0x10) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x11) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x12) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINC _SFR_IO8(0x13) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x14) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x15) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PINB _SFR_IO8(0x16) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x17) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x18) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINA _SFR_IO8(0x19) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x1A) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x1B) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0x1D) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x1E) + +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +#define SFIOR _SFR_IO8(0x20) +#define ACME 3 +#define PSR321 0 +#define PSR0 1 +#define PUD 2 +#define TSM 7 + +#define WDTCR _SFR_IO8(0x21) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define OCDR _SFR_IO8(0x22) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +#define OCR2 _SFR_IO8(0x23) + +#define TCNT2 _SFR_IO8(0x24) + +#define TCCR2 _SFR_IO8(0x25) +#define CS20 0 +#define CS21 1 +#define CS22 2 +#define WGM21 3 +#define COM20 4 +#define COM21 5 +#define WGM20 6 +#define FOC2 7 + +/* Combine ICR1L and ICR1H */ +#define ICR1 _SFR_IO16(0x26) + +#define ICR1L _SFR_IO8(0x26) +#define ICR1H _SFR_IO8(0x27) + +/* Combine OCR1BL and OCR1BH */ +#define OCR1B _SFR_IO16(0x28) + +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Combine OCR1AL and OCR1AH */ +#define OCR1A _SFR_IO16(0x2A) + +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Combine TCNT1L and TCNT1H */ +#define TCNT1 _SFR_IO16(0x2C) + +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +#define TCCR1B _SFR_IO8(0x2E) +#define CS10 0 +#define CS11 1 +#define CS12 2 +#define WGM12 3 +#define WGM13 4 +#define ICES1 6 +#define ICNC1 7 + +#define TCCR1A _SFR_IO8(0x2F) +#define WGM10 0 +#define WGM11 1 +#define COM1C0 2 +#define COM1C1 3 +#define COM1B0 4 +#define COM1B1 5 +#define COM1A0 6 +#define COM1A1 7 + +#define ASSR _SFR_IO8(0x30) +#define TCR0UB 0 +#define OCR0UB 1 +#define TCN0UB 2 +#define AS0 3 + +#define OCR0 _SFR_IO8(0x31) + +#define TCNT0 _SFR_IO8(0x32) + +#define TCCR0 _SFR_IO8(0x33) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM00 4 +#define COM01 5 +#define WGM00 6 +#define FOC0 7 + +#define MCUCSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define JTRF 4 +#define JTD 7 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define SM2 2 +#define SM0 3 +#define SM1 4 +#define SE 5 +#define SRW10 6 +#define SRE 7 + +#define TIFR _SFR_IO8(0x36) +#define TOV0 0 +#define OCF0 1 +#define TOV1 2 +#define OCF1B 3 +#define OCF1A 4 +#define ICF1 5 +#define TOV2 6 +#define OCF2 7 + +#define TIMSK _SFR_IO8(0x37) +#define TOIE0 0 +#define OCIE0 1 +#define TOIE1 2 +#define OCIE1B 3 +#define OCIE1A 4 +#define TICIE1 5 +#define TOIE2 6 +#define OCIE2 7 + +#define EIFR _SFR_IO8(0x38) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x39) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define EICRB _SFR_IO8(0x3A) +#define ISC40 0 +#define ISC41 1 +#define ISC50 2 +#define ISC51 3 +#define ISC60 4 +#define ISC61 5 +#define ISC70 6 +#define ISC71 7 + +/* Reserved [0x3B] */ + +#define XDIV _SFR_IO8(0x3C) +#define XDIV0 0 +#define XDIV1 1 +#define XDIV2 2 +#define XDIV3 3 +#define XDIV4 4 +#define XDIV5 5 +#define XDIV6 6 +#define XDIVEN 7 + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +/* Reserved [0x40..0x60] */ + +#define DDRF _SFR_MEM8(0x61) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_MEM8(0x62) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_MEM8(0x63) +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_MEM8(0x64) +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_MEM8(0x65) +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +/* Reserved [0x66..0x67] */ + +#define SPMCSR _SFR_MEM8(0x68) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x69] */ + +#define EICRA _SFR_MEM8(0x6A) +#define ISC00 0 +#define ISC01 1 +#define ISC10 2 +#define ISC11 3 +#define ISC20 4 +#define ISC21 5 +#define ISC30 6 +#define ISC31 7 + +/* Reserved [0x6B] */ + +#define XMCRB _SFR_MEM8(0x6C) +#define XMM0 0 +#define XMM1 1 +#define XMM2 2 +#define XMBK 7 + +#define XMCRA _SFR_MEM8(0x6D) +#define SRW11 1 +#define SRW00 2 +#define SRW01 3 +#define SRL0 4 +#define SRL1 5 +#define SRL2 6 + +/* Reserved [0x6E] */ + +#define OSCCAL _SFR_MEM8(0x6F) +#define OSCCAL0 0 +#define OSCCAL1 1 +#define OSCCAL2 2 +#define OSCCAL3 3 +#define OSCCAL4 4 +#define OSCCAL5 5 +#define OSCCAL6 6 +#define OSCCAL7 7 + +#define TWBR _SFR_MEM8(0x70) + +#define TWSR _SFR_MEM8(0x71) +#define TWPS0 0 +#define TWPS1 1 +#define TWS3 3 +#define TWS4 4 +#define TWS5 5 +#define TWS6 6 +#define TWS7 7 + +#define TWAR _SFR_MEM8(0x72) +#define TWGCE 0 +#define TWA0 1 +#define TWA1 2 +#define TWA2 3 +#define TWA3 4 +#define TWA4 5 +#define TWA5 6 +#define TWA6 7 + +#define TWDR _SFR_MEM8(0x73) + +#define TWCR _SFR_MEM8(0x74) +#define TWIE 0 +#define TWEN 2 +#define TWWC 3 +#define TWSTO 4 +#define TWSTA 5 +#define TWEA 6 +#define TWINT 7 + +/* Reserved [0x75..0x77] */ + +/* Combine OCR1CL and OCR1CH */ +#define OCR1C _SFR_MEM16(0x78) + +#define OCR1CL _SFR_MEM8(0x78) +#define OCR1CH _SFR_MEM8(0x79) + +#define TCCR1C _SFR_MEM8(0x7A) +#define FOC1C 5 +#define FOC1B 6 +#define FOC1A 7 + +/* Reserved [0x7B] */ + +#define ETIFR _SFR_MEM8(0x7C) +#define OCF1C 0 +#define OCF3C 1 +#define TOV3 2 +#define OCF3B 3 +#define OCF3A 4 +#define ICF3 5 + +#define ETIMSK _SFR_MEM8(0x7D) +#define OCIE1C 0 +#define OCIE3C 1 +#define TOIE3 2 +#define OCIE3B 3 +#define OCIE3A 4 +#define TICIE3 5 + +/* Reserved [0x7E..0x7F] */ + +/* Combine ICR3L and ICR3H */ +#define ICR3 _SFR_MEM16(0x80) + +#define ICR3L _SFR_MEM8(0x80) +#define ICR3H _SFR_MEM8(0x81) + +/* Combine OCR3CL and OCR3CH */ +#define OCR3C _SFR_MEM16(0x82) + +#define OCR3CL _SFR_MEM8(0x82) +#define OCR3CH _SFR_MEM8(0x83) + +/* Combine OCR3BL and OCR3BH */ +#define OCR3B _SFR_MEM16(0x84) + +#define OCR3BL _SFR_MEM8(0x84) +#define OCR3BH _SFR_MEM8(0x85) + +/* Combine OCR3AL and OCR3AH */ +#define OCR3A _SFR_MEM16(0x86) + +#define OCR3AL _SFR_MEM8(0x86) +#define OCR3AH _SFR_MEM8(0x87) + +/* Combine TCNT3L and TCNT3H */ +#define TCNT3 _SFR_MEM16(0x88) + +#define TCNT3L _SFR_MEM8(0x88) +#define TCNT3H _SFR_MEM8(0x89) + +#define TCCR3B _SFR_MEM8(0x8A) +#define CS30 0 +#define CS31 1 +#define CS32 2 +#define WGM32 3 +#define WGM33 4 +#define ICES3 6 +#define ICNC3 7 + +#define TCCR3A _SFR_MEM8(0x8B) +#define WGM30 0 +#define WGM31 1 +#define COM3C0 2 +#define COM3C1 3 +#define COM3B0 4 +#define COM3B1 5 +#define COM3A0 6 +#define COM3A1 7 + +#define TCCR3C _SFR_MEM8(0x8C) +#define FOC3C 5 +#define FOC3B 6 +#define FOC3A 7 + +/* Reserved [0x8D] */ + +#define ADCSRB _SFR_MEM8(0x8E) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 + +/* Reserved [0x8F] */ + +#define UBRR0H _SFR_MEM8(0x90) + +/* Reserved [0x91..0x94] */ + +#define UCSR0C _SFR_MEM8(0x95) +#define UCPOL0 0 +#define UCSZ00 1 +#define UCSZ01 2 +#define USBS0 3 +#define UPM00 4 +#define UPM01 5 +#define UMSEL0 6 + +/* Reserved [0x96..0x97] */ + +#define UBRR1H _SFR_MEM8(0x98) + +#define UBRR1L _SFR_MEM8(0x99) + +#define UCSR1B _SFR_MEM8(0x9A) +#define TXB81 0 +#define RXB81 1 +#define UCSZ12 2 +#define TXEN1 3 +#define RXEN1 4 +#define UDRIE1 5 +#define TXCIE1 6 +#define RXCIE1 7 + +#define UCSR1A _SFR_MEM8(0x9B) +#define MPCM1 0 +#define U2X1 1 +#define UPE1 2 +#define DOR1 3 +#define FE1 4 +#define UDRE1 5 +#define TXC1 6 +#define RXC1 7 + +#define UDR1 _SFR_MEM8(0x9C) + +#define UCSR1C _SFR_MEM8(0x9D) +#define UCPOL1 0 +#define UCSZ10 1 +#define UCSZ11 2 +#define USBS1 3 +#define UPM10 4 +#define UPM11 5 +#define UMSEL1 6 + + + +/* Values and associated defines */ + + +#define SLEEP_MODE_IDLE (0x00<<2) +#define SLEEP_MODE_ADC (0x02<<2) +#define SLEEP_MODE_PWR_DOWN (0x04<<2) +#define SLEEP_MODE_PWR_SAVE (0x06<<2) +#define SLEEP_MODE_STANDBY (0x05<<2) +#define SLEEP_MODE_EXT_STANDBY (0x07<<2) + +/* Interrupt vectors */ +/* Vector 0 is the reset vector */ +/* External Interrupt Request 0 */ +#define INT0_vect _VECTOR(1) +#define INT0_vect_num 1 + +/* External Interrupt Request 1 */ +#define INT1_vect _VECTOR(2) +#define INT1_vect_num 2 + +/* External Interrupt Request 2 */ +#define INT2_vect _VECTOR(3) +#define INT2_vect_num 3 + +/* External Interrupt Request 3 */ +#define INT3_vect _VECTOR(4) +#define INT3_vect_num 4 + +/* External Interrupt Request 4 */ +#define INT4_vect _VECTOR(5) +#define INT4_vect_num 5 + +/* External Interrupt Request 5 */ +#define INT5_vect _VECTOR(6) +#define INT5_vect_num 6 + +/* External Interrupt Request 6 */ +#define INT6_vect _VECTOR(7) +#define INT6_vect_num 7 + +/* External Interrupt Request 7 */ +#define INT7_vect _VECTOR(8) +#define INT7_vect_num 8 + +/* Timer/Counter2 Compare Match */ +#define TIMER2_COMP_vect _VECTOR(9) +#define TIMER2_COMP_vect_num 9 + +/* Timer/Counter2 Overflow */ +#define TIMER2_OVF_vect _VECTOR(10) +#define TIMER2_OVF_vect_num 10 + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect _VECTOR(11) +#define TIMER1_CAPT_vect_num 11 + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect _VECTOR(12) +#define TIMER1_COMPA_vect_num 12 + +/* Timer/Counter Compare Match B */ +#define TIMER1_COMPB_vect _VECTOR(13) +#define TIMER1_COMPB_vect_num 13 + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect _VECTOR(14) +#define TIMER1_OVF_vect_num 14 + +/* Timer/Counter0 Compare Match */ +#define TIMER0_COMP_vect _VECTOR(15) +#define TIMER0_COMP_vect_num 15 + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect _VECTOR(16) +#define TIMER0_OVF_vect_num 16 + +/* SPI Serial Transfer Complete */ +#define SPI_STC_vect _VECTOR(17) +#define SPI_STC_vect_num 17 + +/* USART0, Rx Complete */ +#define USART0_RX_vect _VECTOR(18) +#define USART0_RX_vect_num 18 + +/* USART0 Data Register Empty */ +#define USART0_UDRE_vect _VECTOR(19) +#define USART0_UDRE_vect_num 19 + +/* USART0, Tx Complete */ +#define USART0_TX_vect _VECTOR(20) +#define USART0_TX_vect_num 20 + +/* ADC Conversion Complete */ +#define ADC_vect _VECTOR(21) +#define ADC_vect_num 21 + +/* EEPROM Ready */ +#define EE_READY_vect _VECTOR(22) +#define EE_READY_vect_num 22 + +/* Analog Comparator */ +#define ANALOG_COMP_vect _VECTOR(23) +#define ANALOG_COMP_vect_num 23 + +/* Timer/Counter1 Compare Match C */ +#define TIMER1_COMPC_vect _VECTOR(24) +#define TIMER1_COMPC_vect_num 24 + +/* Timer/Counter3 Capture Event */ +#define TIMER3_CAPT_vect _VECTOR(25) +#define TIMER3_CAPT_vect_num 25 + +/* Timer/Counter3 Compare Match A */ +#define TIMER3_COMPA_vect _VECTOR(26) +#define TIMER3_COMPA_vect_num 26 + +/* Timer/Counter3 Compare Match B */ +#define TIMER3_COMPB_vect _VECTOR(27) +#define TIMER3_COMPB_vect_num 27 + +/* Timer/Counter3 Compare Match C */ +#define TIMER3_COMPC_vect _VECTOR(28) +#define TIMER3_COMPC_vect_num 28 + +/* Timer/Counter3 Overflow */ +#define TIMER3_OVF_vect _VECTOR(29) +#define TIMER3_OVF_vect_num 29 + +/* USART1, Rx Complete */ +#define USART1_RX_vect _VECTOR(30) +#define USART1_RX_vect_num 30 + +/* USART1, Data Register Empty */ +#define USART1_UDRE_vect _VECTOR(31) +#define USART1_UDRE_vect_num 31 + +/* USART1, Tx Complete */ +#define USART1_TX_vect _VECTOR(32) +#define USART1_TX_vect_num 32 + +/* 2-wire Serial Interface */ +#define TWI_vect _VECTOR(33) +#define TWI_vect_num 33 + +/* Store Program Memory Read */ +#define SPM_READY_vect _VECTOR(34) +#define SPM_READY_vect_num 34 + +#define _VECTORS_SIZE 140 + + +/* Constants */ + +#define SPM_PAGESIZE 256 +#define FLASHSTART 0x0000 +#define FLASHEND 0xFFFF +#define RAMSTART 0x0100 +#define RAMSIZE 4096 +#define RAMEND 0x10FF +#define E2START 0 +#define E2SIZE 2048 +#define E2PAGESIZE 8 +#define E2END 0x07FF +#define XRAMEND RAMEND + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) +#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) +#define FUSE_BODEN (unsigned char)~_BV(6) +#define FUSE_BODLEVEL (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_SUT_CKSEL1 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4) + + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_CKOPT (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + + +/* Extended Fuse Byte */ +#define FUSE_WDTON (unsigned char)~_BV(0) +#define FUSE_CompMode (unsigned char)~_BV(1) +#define EFUSE_DEFAULT (FUSE_CompMode) + + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x02 + + +#endif /* #ifdef _AVR_ATMEGA64A_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iom64c1.h b/hardware/tools/avr/avr/include/avr/iom64c1.h new file mode 100644 index 0000000000000000000000000000000000000000..c68534106e9ce3731ad1f287390125fd0d8fa306 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom64c1.h @@ -0,0 +1,1321 @@ +/* Copyright (c) 2009 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom64c1.h 2183 2010-09-21 05:37:46Z aboyapati $ */ + +/* avr/iom64c1.h - definitions for ATmega64C1 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom64c1.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega64C1_H_ +#define _AVR_ATmega64C1_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define PINE _SFR_IO8(0x0C) +#define PINE0 0 +#define PINE1 1 +#define PINE2 2 + +#define DDRE _SFR_IO8(0x0D) +#define DDE0 0 +#define DDE1 1 +#define DDE2 2 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE0 0 +#define PORTE1 1 +#define PORTE2 2 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define GPIOR1 _SFR_IO8(0x19) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x1A) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 +#define EEAR10 2 + +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 +#define PSRSYNC 0 +#define ICPSEL1 6 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 +#define PLLE 1 +#define PLLF 2 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define AC0O 0 +#define AC1O 1 +#define AC2O 2 +#define AC3O 3 +#define AC0IF 4 +#define AC1IF 5 +#define AC2IF 6 +#define AC3IF 7 + +#define DWDR _SFR_IO8(0x31) + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define SPIPS 7 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRLIN 1 +#define PRSPI 2 +#define PRTIM0 3 +#define PRTIM1 4 +#define PRPSC 5 +#define PRCAN 6 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom64hve.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega64HVE_H_ +#define _AVR_ATmega64HVE_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINA _SFR_IO8(0x00) +#define PINA0 0 +#define PINA1 1 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 + +#define PORTA _SFR_IO8(0x02) +#define PORTA0 0 +#define PORTA1 1 + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define ICF0 3 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 3 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define ICS0 3 +#define ICES0 4 +#define ICNC0 5 +#define ICEN0 6 +#define TCW0 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 + +#define TCNT0 _SFR_IO16(0x26) + +#define TCNT0L _SFR_IO8(0x26) +#define TCNT0L0 0 +#define TCNT0L1 1 +#define TCNT0L2 2 +#define TCNT0L3 3 +#define TCNT0L4 4 +#define TCNT0L5 5 +#define TCNT0L6 6 +#define TCNT0L7 7 + +#define TCNT0H _SFR_IO8(0x27) +#define TCNT0H0 0 +#define TCNT0H1 1 +#define TCNT0H2 2 +#define TCNT0H3 3 +#define TCNT0H4 4 +#define TCNT0H5 5 +#define TCNT0H6 6 +#define TCNT0H7 7 + +#define OCR0A _SFR_IO8(0x28) +#define OCR0A0 0 +#define OCR0A1 1 +#define OCR0A2 2 +#define OCR0A3 3 +#define OCR0A4 4 +#define OCR0A5 5 +#define OCR0A6 6 +#define OCR0A7 7 + +#define OCR0B _SFR_IO8(0x29) +#define OCR0B0 0 +#define OCR0B1 1 +#define OCR0B2 2 +#define OCR0B3 3 +#define OCR0B4 4 +#define OCR0B5 5 +#define OCR0B6 6 +#define OCR0B7 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define TCCR0C _SFR_IO8(0x2F) + +#define OCDR _SFR_IO8(0x31) + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BODRF 2 +#define WDRF 3 +#define OCDRF 4 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define CKOE 5 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define LBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPCE 7 + +#define WUTCSR _SFR_MEM8(0x62) +#define WUTP0 0 +#define WUTP1 1 +#define WUTP2 2 +#define WUTE 3 +#define WUTR 4 +#define WUTIE 6 +#define WUTIF 7 + +#define WDTCLR _SFR_MEM8(0x63) +#define WDCLE 0 +#define WDCL0 1 +#define WDCL1 2 + +#define PRR0 _SFR_MEM8(0x64) +#define PRTIM0 0 +#define PRTIM1 1 +#define PRSPI 2 +#define PRLIN 3 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom64hve2.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +/* Reserved [0x06..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define ICF0 3 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 3 + +/* Reserved [0x17..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define ICS0 3 +#define ICES0 4 +#define ICNC0 5 +#define ICEN0 6 +#define TCW0 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 + +/* Combine TCNT0L and TCNT0H */ +#define TCNT0 _SFR_IO16(0x26) + +#define TCNT0L _SFR_IO8(0x26) +#define TCNT0H _SFR_IO8(0x27) + +#define OCR0A _SFR_IO8(0x28) + +#define OCR0B _SFR_IO8(0x29) + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BODRF 2 +#define WDRF 3 +#define OCDRF 4 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define CKOE 5 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define LBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPCE 7 + +#define WUTCSR _SFR_MEM8(0x62) +#define WUTP0 0 +#define WUTP1 1 +#define WUTP2 2 +#define WUTE 3 +#define WUTR 4 +#define WUTIE 6 +#define WUTIF 7 + +#define WDTCLR _SFR_MEM8(0x63) +#define WDCLE 0 +#define WDCL0 1 +#define WDCL1 2 + +#define PRR0 _SFR_MEM8(0x64) +#define PRTIM0 0 +#define PRTIM1 1 +#define PRSPI 2 +#define PRLIN 3 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom64m1.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega64M1_H_ +#define _AVR_ATmega64M1_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define PINE _SFR_IO8(0x0C) +#define PINE0 0 +#define PINE1 1 +#define PINE2 2 + +#define DDRE _SFR_IO8(0x0D) +#define DDE0 0 +#define DDE1 1 +#define DDE2 2 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE0 0 +#define PORTE1 1 +#define PORTE2 2 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define GPIOR1 _SFR_IO8(0x19) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x1A) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 +#define EEAR10 2 + +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 +#define PSRSYNC 0 +#define ICPSEL1 6 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 +#define PLLE 1 +#define PLLF 2 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define AC0O 0 +#define AC1O 1 +#define AC2O 2 +#define AC3O 3 +#define AC0IF 4 +#define AC1IF 5 +#define AC2IF 6 +#define AC3IF 7 + +#define DWDR _SFR_IO8(0x31) + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define SPIPS 7 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRLIN 1 +#define PRSPI 2 +#define PRTIM0 3 +#define PRTIM1 4 +#define PRPSC 5 +#define PRCAN 6 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom64rfr2.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_IO8(0x12) +#define PING7 7 +#define PING6 6 +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDRG7 7 +// Inserted "DDG7" from "DDRG7" due to compatibility +#define DDG7 7 +#define DDRG6 6 +// Inserted "DDG6" from "DDRG6" due to compatibility +#define DDG6 6 +#define DDRG5 5 +// Inserted "DDG5" from "DDRG5" due to compatibility +#define DDG5 5 +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PORTG7 7 +#define PORTG6 6 +#define PORTG5 5 +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define Res0 3 +#define Res1 4 +#define Res2 5 +#define Res3 6 +#define Res4 7 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define OCF1C 3 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define OCF3C 3 +#define ICF3 5 + +#define TIFR4 _SFR_IO8(0x19) +#define TOV4 0 +#define OCF4A 1 +#define OCF4B 2 +#define OCF4C 3 +#define ICF4 5 + +#define TIFR5 _SFR_IO8(0x1A) +#define TOV5 0 +#define OCF5A 1 +#define OCF5B 2 +#define OCF5C 3 +#define ICF5 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62] */ + +#define PRR2 _SFR_MEM8(0x63) +#define PRRAM0 0 +#define PRRAM1 1 +#define PRRAM2 2 +#define PRRAM3 3 + +#define __AVR_HAVE_PRR2 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom8.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ +#define TWBR _SFR_IO8(0x00) +#define TWSR _SFR_IO8(0x01) +#define TWAR _SFR_IO8(0x02) +#define TWDR _SFR_IO8(0x03) + +/* ADC */ +#define ADCW _SFR_IO16(0x04) +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) +#define ADCSR _SFR_IO8(0x06) +#define ADCSRA _SFR_IO8(0x06) /* Changed in 2486H-AVR-09/02 */ +#define ADMUX _SFR_IO8(0x07) + +/* analog comparator */ +#define ACSR _SFR_IO8(0x08) + +/* USART */ +#define UBRRL _SFR_IO8(0x09) +#define UCSRB _SFR_IO8(0x0A) +#define UCSRA _SFR_IO8(0x0B) +#define UDR _SFR_IO8(0x0C) + +/* SPI */ +#define SPCR _SFR_IO8(0x0D) +#define SPSR _SFR_IO8(0x0E) +#define SPDR _SFR_IO8(0x0F) + +/* Port D */ +#define PIND _SFR_IO8(0x10) +#define DDRD _SFR_IO8(0x11) +#define PORTD _SFR_IO8(0x12) + +/* Port C */ +#define PINC _SFR_IO8(0x13) +#define DDRC _SFR_IO8(0x14) +#define PORTC _SFR_IO8(0x15) + +/* Port B */ +#define PINB _SFR_IO8(0x16) +#define DDRB _SFR_IO8(0x17) +#define PORTB _SFR_IO8(0x18) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO16(0x1E) +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +#define UCSRC _SFR_IO8(0x20) +#define UBRRH _SFR_IO8(0x20) + +#define WDTCR _SFR_IO8(0x21) +#define ASSR _SFR_IO8(0x22) + +/* Timer 2 */ +#define OCR2 _SFR_IO8(0x23) +#define TCNT2 _SFR_IO8(0x24) +#define TCCR2 _SFR_IO8(0x25) + +/* Timer 1 */ +#define ICR1 _SFR_IO16(0x26) +#define ICR1L _SFR_IO8(0x26) +#define ICR1H _SFR_IO8(0x27) +#define OCR1B _SFR_IO16(0x28) +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) +#define TCCR1B _SFR_IO8(0x2E) +#define TCCR1A _SFR_IO8(0x2F) + +#define SFIOR _SFR_IO8(0x30) + +#define OSCCAL _SFR_IO8(0x31) + +/* Timer 0 */ +#define TCNT0 _SFR_IO8(0x32) +#define TCCR0 _SFR_IO8(0x33) + +#define MCUCSR _SFR_IO8(0x34) +#define MCUSR _SFR_IO8(0x34) /* Defined as an alias for MCUCSR. */ + +#define MCUCR _SFR_IO8(0x35) + +#define TWCR _SFR_IO8(0x36) + +#define SPMCR _SFR_IO8(0x37) + +#define TIFR _SFR_IO8(0x38) +#define TIMSK _SFR_IO8(0x39) + +#define GIFR _SFR_IO8(0x3A) +#define GIMSK _SFR_IO8(0x3B) +#define GICR _SFR_IO8(0x3B) /* Changed in 2486H-AVR-09/02 */ + +/* 0x3C reserved (OCR0?) */ + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt Request 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt Request 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* Timer/Counter2 Compare Match */ +#define TIMER2_COMP_vect_num 3 +#define TIMER2_COMP_vect _VECTOR(3) +#define SIG_OUTPUT_COMPARE2 _VECTOR(3) + +/* Timer/Counter2 Overflow */ +#define TIMER2_OVF_vect_num 4 +#define TIMER2_OVF_vect _VECTOR(4) +#define SIG_OVERFLOW2 _VECTOR(4) + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect_num 5 +#define TIMER1_CAPT_vect _VECTOR(5) +#define SIG_INPUT_CAPTURE1 _VECTOR(5) + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect_num 6 +#define TIMER1_COMPA_vect _VECTOR(6) +#define SIG_OUTPUT_COMPARE1A _VECTOR(6) + +/* Timer/Counter1 Compare Match B */ +#define TIMER1_COMPB_vect_num 7 +#define TIMER1_COMPB_vect _VECTOR(7) +#define SIG_OUTPUT_COMPARE1B _VECTOR(7) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 8 +#define TIMER1_OVF_vect _VECTOR(8) +#define SIG_OVERFLOW1 _VECTOR(8) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 9 +#define TIMER0_OVF_vect _VECTOR(9) +#define SIG_OVERFLOW0 _VECTOR(9) + +/* Serial Transfer Complete */ +#define SPI_STC_vect_num 10 +#define SPI_STC_vect _VECTOR(10) +#define SIG_SPI _VECTOR(10) + +/* USART, Rx Complete */ +#define USART_RXC_vect_num 11 +#define USART_RXC_vect _VECTOR(11) +#define SIG_UART_RECV _VECTOR(11) + +/* USART Data Register Empty */ +#define USART_UDRE_vect_num 12 +#define USART_UDRE_vect _VECTOR(12) +#define SIG_UART_DATA _VECTOR(12) + +/* USART, Tx Complete */ +#define USART_TXC_vect_num 13 +#define USART_TXC_vect _VECTOR(13) +#define SIG_UART_TRANS _VECTOR(13) + +/* ADC Conversion Complete */ +#define ADC_vect_num 14 +#define ADC_vect _VECTOR(14) +#define SIG_ADC _VECTOR(14) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 15 +#define EE_RDY_vect _VECTOR(15) +#define SIG_EEPROM_READY _VECTOR(15) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 16 +#define ANA_COMP_vect _VECTOR(16) +#define SIG_COMPARATOR _VECTOR(16) + +/* 2-wire Serial Interface */ +#define TWI_vect_num 17 +#define TWI_vect _VECTOR(17) +#define SIG_2WIRE_SERIAL _VECTOR(17) + +/* Store Program Memory Ready */ +#define SPM_RDY_vect_num 18 +#define SPM_RDY_vect _VECTOR(18) +#define SIG_SPM_READY _VECTOR(18) + +#define _VECTORS_SIZE 38 + +/* Bit numbers */ + +/* GIMSK / GICR */ +#define INT1 7 +#define INT0 6 +#define IVSEL 1 +#define IVCE 0 + +/* GIFR */ +#define INTF1 7 +#define INTF0 6 + +/* TIMSK */ +#define OCIE2 7 +#define TOIE2 6 +#define TICIE1 5 +#define OCIE1A 4 +#define OCIE1B 3 +#define TOIE1 2 +/* bit 1 reserved (OCIE0?) */ +#define TOIE0 0 + +/* TIFR */ +#define OCF2 7 +#define TOV2 6 +#define ICF1 5 +#define OCF1A 4 +#define OCF1B 3 +#define TOV1 2 +/* bit 1 reserved (OCF0?) */ +#define TOV0 0 + +/* SPMCR */ +#define SPMIE 7 +#define RWWSB 6 +/* bit 5 reserved */ +#define RWWSRE 4 +#define BLBSET 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 + +/* TWCR */ +#define TWINT 7 +#define TWEA 6 +#define TWSTA 5 +#define TWSTO 4 +#define TWWC 3 +#define TWEN 2 +/* bit 1 reserved (TWI_TST?) */ +#define TWIE 0 + +/* TWAR */ +#define TWA6 7 +#define TWA5 6 +#define TWA4 5 +#define TWA3 4 +#define TWA2 3 +#define TWA1 2 +#define TWA0 1 +#define TWGCE 0 + +/* TWSR */ +#define TWS7 7 +#define TWS6 6 +#define TWS5 5 +#define TWS4 4 +#define TWS3 3 +/* bit 2 reserved */ +#define TWPS1 1 +#define TWPS0 0 + +/* MCUCR */ +#define SE 7 +#define SM2 6 +#define SM1 5 +#define SM0 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/* MCUCSR */ +/* bits 7-4 reserved */ +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +/* + The ADHSM bit has been removed from all documentation, + as being not needed at all since the comparator has proven + to be fast enough even without feeding it more power. +*/ + +/* SFIOR */ +/* bits 7-5 reserved */ +#define ACME 3 +#define PUD 2 +#define PSR2 1 +#define PSR10 0 + +/* TCCR0 */ +/* bits 7-3 reserved */ +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* TCCR2 */ +#define FOC2 7 +#define WGM20 6 +#define COM21 5 +#define COM20 4 +#define WGM21 3 +#define CS22 2 +#define CS21 1 +#define CS20 0 + +/* ASSR */ +/* bits 7-4 reserved */ +#define AS2 3 +#define TCN2UB 2 +#define OCR2UB 1 +#define TCR2UB 0 + +/* TCCR1A */ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define FOC1A 3 +#define FOC1B 2 +#define WGM11 1 +#define WGM10 0 + +/* TCCR1B */ +#define ICNC1 7 +#define ICES1 6 +/* bit 5 reserved */ +#define WGM13 4 +#define WGM12 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* WDTCR */ +/* bits 7-5 reserved */ +#define WDCE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* UBRRH */ +#define URSEL 7 + +/* UCSRC */ +#define URSEL 7 +#define UMSEL 6 +#define UPM1 5 +#define UPM0 4 +#define USBS 3 +#define UCSZ1 2 +#define UCSZ0 1 +#define UCPOL 0 + +/* PORTB */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* DDRB */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* PINB */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* PORTC */ +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* DDRC */ +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +/* PINC */ +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +/* PORTD */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* DDRD */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* PIND */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* SPSR */ +#define SPIF 7 +#define WCOL 6 +#define SPI2X 0 + +/* SPCR */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* UCSRA */ +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 +#define PE 2 +#define U2X 1 +#define MPCM 0 + +/* UCSRB */ +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define UCSZ2 2 +#define RXB8 1 +#define TXB8 0 + +/* ACSR */ +#define ACD 7 +#define ACBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +/* ADCSR / ADCSRA */ +#define ADEN 7 +#define ADSC 6 +#define ADFR 5 +#define ADIF 4 +#define ADIE 3 +#define ADPS2 2 +#define ADPS1 1 +#define ADPS0 0 + +/* ADMUX */ +#define REFS1 7 +#define REFS0 6 +#define ADLAR 5 +/* bit 4 reserved */ +#define MUX3 3 +#define MUX2 2 +#define MUX1 1 +#define MUX0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define SPM_PAGESIZE 64 +#define RAMSTART (0x60) +#define RAMEND 0x45F +#define XRAMEND RAMEND +#define E2END 0x1FF +#define E2PAGESIZE 4 +#define FLASHEND 0x1FFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 2 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_BODEN (unsigned char)~_BV(6) +#define FUSE_BODLEVEL (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_CKOPT (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_WDTON (unsigned char)~_BV(6) +#define FUSE_RSTDISBL (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x07 + + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_INTERRUPT1 +#pragma GCC poison SIG_OUTPUT_COMPARE2 +#pragma GCC poison SIG_OVERFLOW2 +#pragma GCC poison SIG_INPUT_CAPTURE1 +#pragma GCC poison SIG_OUTPUT_COMPARE1A +#pragma GCC poison SIG_OUTPUT_COMPARE1B +#pragma GCC poison SIG_OVERFLOW1 +#pragma GCC poison SIG_OVERFLOW0 +#pragma GCC poison SIG_SPI +#pragma GCC poison SIG_UART_RECV +#pragma GCC poison SIG_UART_DATA +#pragma GCC poison SIG_UART_TRANS +#pragma GCC poison SIG_ADC +#pragma GCC poison SIG_EEPROM_READY +#pragma GCC poison SIG_COMPARATOR +#pragma GCC poison SIG_2WIRE_SERIAL +#pragma GCC poison SIG_SPM_READY + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + +#define SLEEP_MODE_IDLE (0x00<<4) +#define SLEEP_MODE_ADC (0x01<<4) +#define SLEEP_MODE_PWR_DOWN (0x02<<4) +#define SLEEP_MODE_PWR_SAVE (0x03<<4) +#define SLEEP_MODE_STANDBY (0x06<<4) + +#endif /* _AVR_IOM8_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom808.h b/hardware/tools/avr/avr/include/avr/iom808.h new file mode 100644 index 0000000000000000000000000000000000000000..ebb8cd4d65bf0e7cb3fa1ece9c5d30d255580020 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom808.h @@ -0,0 +1,4955 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom808.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATMEGA808_H_INCLUDED +#define _AVR_ATMEGA808_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[1]; + register8_t DACREF; /* Referance scale control */ + register8_t reserved_3[1]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_PIN2_gc = (0x02<<0), /* Negative Pin 2 */ + AC_MUXNEG_DACREF_gc = (0x03<<0), /* DAC Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ + ADC_MUXPOS_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ + ADC_MUXPOS_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ + ADC_MUXPOS_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ + ADC_MUXPOS_DACREF_gc = (0x1C<<0), /* AC DAC Reference */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temperature sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* 0V (GND) */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t SEQCTRL1; /* Sequential Control 1 */ + register8_t reserved_1[2]; + register8_t INTCTRL0; /* Interrupt Control 0 */ + register8_t reserved_2[1]; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t LUT2CTRLA; /* LUT Control 2 A */ + register8_t LUT2CTRLB; /* LUT Control 2 B */ + register8_t LUT2CTRLC; /* LUT Control 2 C */ + register8_t TRUTH2; /* Truth 2 */ + register8_t LUT3CTRLA; /* LUT Control 3 A */ + register8_t LUT3CTRLB; /* LUT Control 3 B */ + register8_t LUT3CTRLC; /* LUT Control 3 C */ + register8_t TRUTH3; /* Truth 3 */ + register8_t reserved_3[40]; +} CCL_t; + +/* Clock Source Selection select */ +typedef enum CCL_CLKSRC_enum +{ + CCL_CLKSRC_CLKPER_gc = (0x00<<1), /* CLK_PER is clocking the LUT */ + CCL_CLKSRC_IN2_gc = (0x01<<1), /* IN[2] is clocking the LUT */ + CCL_CLKSRC_OSC20M_gc = (0x04<<1), /* 20MHz oscillator before prescaler is clocking the LUT */ + CCL_CLKSRC_OSCULP32K_gc = (0x05<<1), /* 32kHz oscillator is clocking the LUT */ + CCL_CLKSRC_OSCULP1K_gc = (0x06<<1), /* 32kHz oscillator after DIV32 is clocking the LUT */ +} CCL_CLKSRC_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL0_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_USART0_gc = (0x08<<0), /* USART0 TXD input source */ + CCL_INSEL0_SPI0_gc = (0x09<<0), /* SPI0 MOSI input source */ + CCL_INSEL0_TCA0_gc = (0x0A<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCB0_gc = (0x0C<<0), /* TCB0 WO input source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENTA_gc = (0x03<<4), /* Event input source A */ + CCL_INSEL1_EVENTB_gc = (0x04<<4), /* Event input source B */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_USART1_gc = (0x08<<4), /* USART1 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x09<<4), /* SPI0 MOSI input source */ + CCL_INSEL1_TCA0_gc = (0x0A<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCB1_gc = (0x0C<<4), /* TCB1 WO input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL2_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_USART2_gc = (0x08<<0), /* USART2 TXD input source */ + CCL_INSEL2_SPI0_gc = (0x09<<0), /* SPI0 SCK input source */ + CCL_INSEL2_TCA0_gc = (0x0A<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCB2_gc = (0x0C<<0), /* TCB2 WO input source */ +} CCL_INSEL2_t; + +/* Interrupt Mode for LUT0 select */ +typedef enum CCL_INTMODE0_enum +{ + CCL_INTMODE0_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled */ + CCL_INTMODE0_RISING_gc = (0x01<<0), /* Sense rising edge */ + CCL_INTMODE0_FALLING_gc = (0x02<<0), /* Sense falling edge */ + CCL_INTMODE0_BOTH_gc = (0x03<<0), /* Sense both edges */ +} CCL_INTMODE0_t; + +/* Interrupt Mode for LUT1 select */ +typedef enum CCL_INTMODE1_enum +{ + CCL_INTMODE1_INTDISABLE_gc = (0x00<<2), /* Interrupt disabled */ + CCL_INTMODE1_RISING_gc = (0x01<<2), /* Sense rising edge */ + CCL_INTMODE1_FALLING_gc = (0x02<<2), /* Sense falling edge */ + CCL_INTMODE1_BOTH_gc = (0x03<<2), /* Sense both edges */ +} CCL_INTMODE1_t; + +/* Interrupt Mode for LUT2 select */ +typedef enum CCL_INTMODE2_enum +{ + CCL_INTMODE2_INTDISABLE_gc = (0x00<<4), /* Interrupt disabled */ + CCL_INTMODE2_RISING_gc = (0x01<<4), /* Sense rising edge */ + CCL_INTMODE2_FALLING_gc = (0x02<<4), /* Sense falling edge */ + CCL_INTMODE2_BOTH_gc = (0x03<<4), /* Sense both edges */ +} CCL_INTMODE2_t; + +/* Interrupt Mode for LUT3 select */ +typedef enum CCL_INTMODE3_enum +{ + CCL_INTMODE3_INTDISABLE_gc = (0x00<<6), /* Interrupt disabled */ + CCL_INTMODE3_RISING_gc = (0x01<<6), /* Sense rising edge */ + CCL_INTMODE3_FALLING_gc = (0x02<<6), /* Sense falling edge */ + CCL_INTMODE3_BOTH_gc = (0x03<<6), /* Sense both edges */ +} CCL_INTMODE3_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL0_enum +{ + CCL_SEQSEL0_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL0_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL0_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL0_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL0_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL0_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL1_enum +{ + CCL_SEQSEL1_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL1_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL1_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL1_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL1_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL1_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1k cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16k cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32k cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t STROBE; /* Channel Strobe */ + register8_t reserved_1[15]; + register8_t CHANNEL0; /* Multiplexer Channel 0 */ + register8_t CHANNEL1; /* Multiplexer Channel 1 */ + register8_t CHANNEL2; /* Multiplexer Channel 2 */ + register8_t CHANNEL3; /* Multiplexer Channel 3 */ + register8_t CHANNEL4; /* Multiplexer Channel 4 */ + register8_t CHANNEL5; /* Multiplexer Channel 5 */ + register8_t reserved_2[10]; + register8_t USERCCLLUT0A; /* User CCL LUT0 Event A */ + register8_t USERCCLLUT0B; /* User CCL LUT0 Event B */ + register8_t USERCCLLUT1A; /* User CCL LUT1 Event A */ + register8_t USERCCLLUT1B; /* User CCL LUT1 Event B */ + register8_t USERCCLLUT2A; /* User CCL LUT2 Event A */ + register8_t USERCCLLUT2B; /* User CCL LUT2 Event B */ + register8_t USERCCLLUT3A; /* User CCL LUT3 Event A */ + register8_t USERCCLLUT3B; /* User CCL LUT3 Event B */ + register8_t USERADC0; /* User ADC0 */ + register8_t USEREVOUTA; /* User EVOUT Port A */ + register8_t USEREVOUTB; /* User EVOUT Port B */ + register8_t USEREVOUTC; /* User EVOUT Port C */ + register8_t USEREVOUTD; /* User EVOUT Port D */ + register8_t USEREVOUTE; /* User EVOUT Port E */ + register8_t USEREVOUTF; /* User EVOUT Port F */ + register8_t USERUSART0; /* User USART0 */ + register8_t USERUSART1; /* User USART1 */ + register8_t USERUSART2; /* User USART2 */ + register8_t USERUSART3; /* User USART3 */ + register8_t USERTCA0; /* User TCA0 */ + register8_t USERTCB0; /* User TCB0 */ + register8_t USERTCB1; /* User TCB1 */ + register8_t USERTCB2; /* User TCB2 */ + register8_t USERTCB3; /* User TCB3 */ + register8_t reserved_3[8]; +} EVSYS_t; + +/* Channel selector select */ +typedef enum EVSYS_CHANNEL_enum +{ + EVSYS_CHANNEL_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL_CHANNEL0_gc = (0x01<<0), /* Connect user to event channel 0 */ + EVSYS_CHANNEL_CHANNEL1_gc = (0x02<<0), /* Connect user to event channel 1 */ + EVSYS_CHANNEL_CHANNEL2_gc = (0x03<<0), /* Connect user to event channel 2 */ + EVSYS_CHANNEL_CHANNEL3_gc = (0x04<<0), /* Connect user to event channel 3 */ + EVSYS_CHANNEL_CHANNEL4_gc = (0x05<<0), /* Connect user to event channel 4 */ + EVSYS_CHANNEL_CHANNEL5_gc = (0x06<<0), /* Connect user to event channel 5 */ +} EVSYS_CHANNEL_t; + +/* Generator selector select */ +typedef enum EVSYS_GENERATOR_enum +{ + EVSYS_GENERATOR_OFF_gc = (0x00<<0), /* Off */ + EVSYS_GENERATOR_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_GENERATOR_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_GENERATOR_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_GENERATOR_RTC_PIT0_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_GENERATOR_RTC_PIT1_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_GENERATOR_RTC_PIT2_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_GENERATOR_RTC_PIT3_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_GENERATOR_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_GENERATOR_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_GENERATOR_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_GENERATOR_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_GENERATOR_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_GENERATOR_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready Event */ + EVSYS_GENERATOR_PORT0_PIN0_gc = (0x40<<0), /* Port 0 Pin 0 */ + EVSYS_GENERATOR_PORT0_PIN1_gc = (0x41<<0), /* Port 0 Pin 1 */ + EVSYS_GENERATOR_PORT0_PIN2_gc = (0x42<<0), /* Port 0 Pin 2 */ + EVSYS_GENERATOR_PORT0_PIN3_gc = (0x43<<0), /* Port 0 Pin 3 */ + EVSYS_GENERATOR_PORT0_PIN4_gc = (0x44<<0), /* Port 0 Pin 4 */ + EVSYS_GENERATOR_PORT0_PIN5_gc = (0x45<<0), /* Port 0 Pin 5 */ + EVSYS_GENERATOR_PORT0_PIN6_gc = (0x46<<0), /* Port 0 Pin 6 */ + EVSYS_GENERATOR_PORT0_PIN7_gc = (0x47<<0), /* Port 0 Pin 7 */ + EVSYS_GENERATOR_PORT1_PIN0_gc = (0x48<<0), /* Port 1 Pin 0 */ + EVSYS_GENERATOR_PORT1_PIN1_gc = (0x49<<0), /* Port 1 Pin 1 */ + EVSYS_GENERATOR_PORT1_PIN2_gc = (0x4A<<0), /* Port 1 Pin 2 */ + EVSYS_GENERATOR_PORT1_PIN3_gc = (0x4B<<0), /* Port 1 Pin 3 */ + EVSYS_GENERATOR_PORT1_PIN4_gc = (0x4C<<0), /* Port 1 Pin 4 */ + EVSYS_GENERATOR_PORT1_PIN5_gc = (0x4D<<0), /* Port 1 Pin 5 */ + EVSYS_GENERATOR_PORT1_PIN6_gc = (0x4E<<0), /* Port 1 Pin 6 */ + EVSYS_GENERATOR_PORT1_PIN7_gc = (0x4F<<0), /* Port 1 Pin 7 */ + EVSYS_GENERATOR_USART0_XCK_gc = (0x60<<0), /* USART 0 Xclock */ + EVSYS_GENERATOR_USART1_XCK_gc = (0x61<<0), /* USART 1 Xclock */ + EVSYS_GENERATOR_USART2_XCK_gc = (0x62<<0), /* USART 2 Xclock */ + EVSYS_GENERATOR_USART3_XCK_gc = (0x63<<0), /* USART 3 Xclock */ + EVSYS_GENERATOR_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_GENERATOR_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_GENERATOR_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow (split mode) */ + EVSYS_GENERATOR_TCA0_CMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_GENERATOR_TCA0_CMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_GENERATOR_TCA0_CMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_GENERATOR_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_GENERATOR_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_GENERATOR_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_GENERATOR_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ +} EVSYS_GENERATOR_t; + +/* Software event on channels select */ +typedef enum EVSYS_STROBE0_enum +{ + EVSYS_STROBE0_EV_STROBE_CH0_gc = (0x01<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH1_gc = (0x02<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH2_gc = (0x04<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH3_gc = (0x08<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH4_gc = (0x10<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH5_gc = (0x20<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH6_gc = (0x40<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH7_gc = (0x80<<0), /* */ +} EVSYS_STROBE0_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<3), /* GPIO mode */ + RSTPINCFG_RST_gc = (0x01<<3), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock Bits */ + register8_t reserved_1[1]; +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t PORTCTRL; /* Port Control */ + register8_t reserved_1[5]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t EVSYSROUTEA; /* Port Multiplexer EVSYS */ + register8_t CCLROUTEA; /* Port Multiplexer CCL */ + register8_t USARTROUTEA; /* Port Multiplexer USART register A */ + register8_t TWISPIROUTEA; /* Port Multiplexer TWI and SPI */ + register8_t TCAROUTEA; /* Port Multiplexer TCA */ + register8_t TCBROUTEA; /* Port Multiplexer TCB */ + register8_t reserved_1[10]; +} PORTMUX_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<0), /* SPI0 on PA[7:4] */ + PORTMUX_SPI0_ALT1_gc = (0x01<<0), /* SPI0 on PC[3:0] */ + PORTMUX_SPI0_ALT2_gc = (0x02<<0), /* SPI0 on PE[3:0] */ + PORTMUX_SPI0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 select */ +typedef enum PORTMUX_TCA0_enum +{ + PORTMUX_TCA0_PORTA_gc = (0x00<<0), /* TCA0 pins on PA[5:0] */ + PORTMUX_TCA0_PORTB_gc = (0x01<<0), /* TCA0 pins on PB[5:0] */ + PORTMUX_TCA0_PORTC_gc = (0x02<<0), /* TCA0 pins on PC[5:0] */ + PORTMUX_TCA0_PORTD_gc = (0x03<<0), /* TCA0 pins on PD[5:0] */ + PORTMUX_TCA0_PORTE_gc = (0x04<<0), /* TCA0 pins on PE[5:0] */ + PORTMUX_TCA0_PORTF_gc = (0x05<<0), /* TCA0 pins on PF[5:0] */ +} PORTMUX_TCA0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* SCL/SDA on PA[3:2], Slave mode on PC[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT1_gc = (0x01<<4), /* SCL/SDA on PA[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT2_gc = (0x02<<4), /* SCL/SDA on PC[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* USART0 on PA[3:0] */ + PORTMUX_USART0_ALT1_gc = (0x01<<0), /* USART0 on PA[7:4] */ + PORTMUX_USART0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_USART0_t; + +/* Port Multiplexer USART1 select */ +typedef enum PORTMUX_USART1_enum +{ + PORTMUX_USART1_DEFAULT_gc = (0x00<<2), /* USART1 on PC[3:0] */ + PORTMUX_USART1_ALT1_gc = (0x01<<2), /* USART1 on PC[7:4] */ + PORTMUX_USART1_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_USART1_t; + +/* Port Multiplexer USART2 select */ +typedef enum PORTMUX_USART2_enum +{ + PORTMUX_USART2_DEFAULT_gc = (0x00<<4), /* USART2 on PF[3:0] */ + PORTMUX_USART2_ALT1_gc = (0x01<<4), /* USART2 on PF[6:4] */ + PORTMUX_USART2_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_USART2_t; + +/* Port Multiplexer USART3 select */ +typedef enum PORTMUX_USART3_enum +{ + PORTMUX_USART3_DEFAULT_gc = (0x00<<6), /* USART3 on PB[3:0] */ + PORTMUX_USART3_ALT1_gc = (0x01<<6), /* USART3 on PB[5:4] */ + PORTMUX_USART3_NONE_gc = (0x03<<6), /* Not connected to any pins */ +} PORTMUX_USART3_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t CALIB; /* Calibration */ + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_1[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_2[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_3[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[7]; + register8_t OSCCAL32K; /* Oscillator Calibration for 32kHz ULP */ + register8_t reserved_2[3]; + register8_t OSCCAL16M0; /* Oscillator Calibration 16 MHz Byte 0 */ + register8_t OSCCAL16M1; /* Oscillator Calibration 16 MHz Byte 1 */ + register8_t OSCCAL20M0; /* Oscillator Calibration 20 MHz Byte 0 */ + register8_t OSCCAL20M1; /* Oscillator Calibration 20 MHz Byte 1 */ + register8_t reserved_3[4]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_4[9]; + register8_t CHECKSUM1; /* CRC Checksum Byte 1 */ + register8_t reserved_5[16]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[21]; + register8_t OCDM; /* OCD Message Register */ + register8_t OCDMS; /* OCD Message Status */ + register8_t reserved_3[6]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t DUALCTRL; /* Dual Control */ + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_1[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t CTRLD; /* Control D */ + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_1[1]; +} USART_t; + +/* Auto Baud Window select */ +typedef enum USART_ABW_enum +{ + USART_ABW_WDW0_gc = (0x00<<6), /* 18% tolerance */ + USART_ABW_WDW1_gc = (0x01<<6), /* 15% tolerance */ + USART_ABW_WDW2_gc = (0x02<<6), /* 21% tolerance */ + USART_ABW_WDW3_gc = (0x03<<6), /* 25% tolerance */ +} USART_ABW_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ + register8_t USERROW32; /* User Row Byte 32 */ + register8_t USERROW33; /* User Row Byte 33 */ + register8_t USERROW34; /* User Row Byte 34 */ + register8_t USERROW35; /* User Row Byte 35 */ + register8_t USERROW36; /* User Row Byte 36 */ + register8_t USERROW37; /* User Row Byte 37 */ + register8_t USERROW38; /* User Row Byte 38 */ + register8_t USERROW39; /* User Row Byte 39 */ + register8_t USERROW40; /* User Row Byte 40 */ + register8_t USERROW41; /* User Row Byte 41 */ + register8_t USERROW42; /* User Row Byte 42 */ + register8_t USERROW43; /* User Row Byte 43 */ + register8_t USERROW44; /* User Row Byte 44 */ + register8_t USERROW45; /* User Row Byte 45 */ + register8_t USERROW46; /* User Row Byte 46 */ + register8_t USERROW47; /* User Row Byte 47 */ + register8_t USERROW48; /* User Row Byte 48 */ + register8_t USERROW49; /* User Row Byte 49 */ + register8_t USERROW50; /* User Row Byte 50 */ + register8_t USERROW51; /* User Row Byte 51 */ + register8_t USERROW52; /* User Row Byte 52 */ + register8_t USERROW53; /* User Row Byte 53 */ + register8_t USERROW54; /* User Row Byte 54 */ + register8_t USERROW55; /* User Row Byte 55 */ + register8_t USERROW56; /* User Row Byte 56 */ + register8_t USERROW57; /* User Row Byte 57 */ + register8_t USERROW58; /* User Row Byte 58 */ + register8_t USERROW59; /* User Row Byte 59 */ + register8_t USERROW60; /* User Row Byte 60 */ + register8_t USERROW61; /* User Row Byte 61 */ + register8_t USERROW62; /* User Row Byte 62 */ + register8_t USERROW63; /* User Row Byte 63 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* AC0 reference select select */ +typedef enum VREF_AC0REFSEL_enum +{ + VREF_AC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_AC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_AC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_AC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_AC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ + VREF_AC0REFSEL_AVDD_gc = (0x07<<0), /* AVDD as Voltage reference */ +} VREF_AC0REFSEL_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define VPORTD (*(VPORT_t *) 0x000C) /* Virtual Ports */ +#define VPORTE (*(VPORT_t *) 0x0010) /* Virtual Ports */ +#define VPORTF (*(VPORT_t *) 0x0014) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0460) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0480) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x04A0) /* I/O Ports */ +#define PORTMUX (*(PORTMUX_t *) 0x05E0) /* Port Multiplexer */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1 (*(USART_t *) 0x0820) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2 (*(USART_t *) 0x0840) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x08A0) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A80) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0A90) /* 16-bit Timer Type B */ +#define TCB2 (*(TCB_t *) 0x0AA0) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* VPORT (VPORTD) - Virtual Ports */ +#define VPORTD_DIR _SFR_MEM8(0x000C) +#define VPORTD_OUT _SFR_MEM8(0x000D) +#define VPORTD_IN _SFR_MEM8(0x000E) +#define VPORTD_INTFLAGS _SFR_MEM8(0x000F) + + +/* VPORT (VPORTE) - Virtual Ports */ +#define VPORTE_DIR _SFR_MEM8(0x0010) +#define VPORTE_OUT _SFR_MEM8(0x0011) +#define VPORTE_IN _SFR_MEM8(0x0012) +#define VPORTE_INTFLAGS _SFR_MEM8(0x0013) + + +/* VPORT (VPORTF) - Virtual Ports */ +#define VPORTF_DIR _SFR_MEM8(0x0014) +#define VPORTF_OUT _SFR_MEM8(0x0015) +#define VPORTF_IN _SFR_MEM8(0x0016) +#define VPORTF_INTFLAGS _SFR_MEM8(0x0017) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CALIB _SFR_MEM8(0x0146) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_STROBE _SFR_MEM8(0x0180) +#define EVSYS_CHANNEL0 _SFR_MEM8(0x0190) +#define EVSYS_CHANNEL1 _SFR_MEM8(0x0191) +#define EVSYS_CHANNEL2 _SFR_MEM8(0x0192) +#define EVSYS_CHANNEL3 _SFR_MEM8(0x0193) +#define EVSYS_CHANNEL4 _SFR_MEM8(0x0194) +#define EVSYS_CHANNEL5 _SFR_MEM8(0x0195) +#define EVSYS_USERCCLLUT0A _SFR_MEM8(0x01A0) +#define EVSYS_USERCCLLUT0B _SFR_MEM8(0x01A1) +#define EVSYS_USERCCLLUT1A _SFR_MEM8(0x01A2) +#define EVSYS_USERCCLLUT1B _SFR_MEM8(0x01A3) +#define EVSYS_USERCCLLUT2A _SFR_MEM8(0x01A4) +#define EVSYS_USERCCLLUT2B _SFR_MEM8(0x01A5) +#define EVSYS_USERCCLLUT3A _SFR_MEM8(0x01A6) +#define EVSYS_USERCCLLUT3B _SFR_MEM8(0x01A7) +#define EVSYS_USERADC0 _SFR_MEM8(0x01A8) +#define EVSYS_USEREVOUTA _SFR_MEM8(0x01A9) +#define EVSYS_USEREVOUTB _SFR_MEM8(0x01AA) +#define EVSYS_USEREVOUTC _SFR_MEM8(0x01AB) +#define EVSYS_USEREVOUTD _SFR_MEM8(0x01AC) +#define EVSYS_USEREVOUTE _SFR_MEM8(0x01AD) +#define EVSYS_USEREVOUTF _SFR_MEM8(0x01AE) +#define EVSYS_USERUSART0 _SFR_MEM8(0x01AF) +#define EVSYS_USERUSART1 _SFR_MEM8(0x01B0) +#define EVSYS_USERUSART2 _SFR_MEM8(0x01B1) +#define EVSYS_USERUSART3 _SFR_MEM8(0x01B2) +#define EVSYS_USERTCA0 _SFR_MEM8(0x01B3) +#define EVSYS_USERTCB0 _SFR_MEM8(0x01B4) +#define EVSYS_USERTCB1 _SFR_MEM8(0x01B5) +#define EVSYS_USERTCB2 _SFR_MEM8(0x01B6) +#define EVSYS_USERTCB3 _SFR_MEM8(0x01B7) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_SEQCTRL1 _SFR_MEM8(0x01C2) +#define CCL_INTCTRL0 _SFR_MEM8(0x01C5) +#define CCL_INTFLAGS _SFR_MEM8(0x01C7) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C8) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C9) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01CA) +#define CCL_TRUTH0 _SFR_MEM8(0x01CB) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01CC) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CD) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CE) +#define CCL_TRUTH1 _SFR_MEM8(0x01CF) +#define CCL_LUT2CTRLA _SFR_MEM8(0x01D0) +#define CCL_LUT2CTRLB _SFR_MEM8(0x01D1) +#define CCL_LUT2CTRLC _SFR_MEM8(0x01D2) +#define CCL_TRUTH2 _SFR_MEM8(0x01D3) +#define CCL_LUT3CTRLA _SFR_MEM8(0x01D4) +#define CCL_LUT3CTRLB _SFR_MEM8(0x01D5) +#define CCL_LUT3CTRLC _SFR_MEM8(0x01D6) +#define CCL_TRUTH3 _SFR_MEM8(0x01D7) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PORTCTRL _SFR_MEM8(0x040A) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PORTCTRL _SFR_MEM8(0x042A) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PORTCTRL _SFR_MEM8(0x044A) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* PORT (PORTD) - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0460) +#define PORTD_DIRSET _SFR_MEM8(0x0461) +#define PORTD_DIRCLR _SFR_MEM8(0x0462) +#define PORTD_DIRTGL _SFR_MEM8(0x0463) +#define PORTD_OUT _SFR_MEM8(0x0464) +#define PORTD_OUTSET _SFR_MEM8(0x0465) +#define PORTD_OUTCLR _SFR_MEM8(0x0466) +#define PORTD_OUTTGL _SFR_MEM8(0x0467) +#define PORTD_IN _SFR_MEM8(0x0468) +#define PORTD_INTFLAGS _SFR_MEM8(0x0469) +#define PORTD_PORTCTRL _SFR_MEM8(0x046A) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0470) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0471) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0472) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0473) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0474) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0475) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0476) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0477) + + +/* PORT (PORTE) - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0480) +#define PORTE_DIRSET _SFR_MEM8(0x0481) +#define PORTE_DIRCLR _SFR_MEM8(0x0482) +#define PORTE_DIRTGL _SFR_MEM8(0x0483) +#define PORTE_OUT _SFR_MEM8(0x0484) +#define PORTE_OUTSET _SFR_MEM8(0x0485) +#define PORTE_OUTCLR _SFR_MEM8(0x0486) +#define PORTE_OUTTGL _SFR_MEM8(0x0487) +#define PORTE_IN _SFR_MEM8(0x0488) +#define PORTE_INTFLAGS _SFR_MEM8(0x0489) +#define PORTE_PORTCTRL _SFR_MEM8(0x048A) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0490) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0491) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0492) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0493) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0494) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0495) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0496) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0497) + + +/* PORT (PORTF) - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x04A0) +#define PORTF_DIRSET _SFR_MEM8(0x04A1) +#define PORTF_DIRCLR _SFR_MEM8(0x04A2) +#define PORTF_DIRTGL _SFR_MEM8(0x04A3) +#define PORTF_OUT _SFR_MEM8(0x04A4) +#define PORTF_OUTSET _SFR_MEM8(0x04A5) +#define PORTF_OUTCLR _SFR_MEM8(0x04A6) +#define PORTF_OUTTGL _SFR_MEM8(0x04A7) +#define PORTF_IN _SFR_MEM8(0x04A8) +#define PORTF_INTFLAGS _SFR_MEM8(0x04A9) +#define PORTF_PORTCTRL _SFR_MEM8(0x04AA) +#define PORTF_PIN0CTRL _SFR_MEM8(0x04B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x04B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x04B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x04B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x04B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x04B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x04B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x04B7) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_EVSYSROUTEA _SFR_MEM8(0x05E0) +#define PORTMUX_CCLROUTEA _SFR_MEM8(0x05E1) +#define PORTMUX_USARTROUTEA _SFR_MEM8(0x05E2) +#define PORTMUX_TWISPIROUTEA _SFR_MEM8(0x05E3) +#define PORTMUX_TCAROUTEA _SFR_MEM8(0x05E4) +#define PORTMUX_TCBROUTEA _SFR_MEM8(0x05E5) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_DACREF _SFR_MEM8(0x0684) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_CTRLD _SFR_MEM8(0x080A) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* USART (USART1) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1_RXDATAL _SFR_MEM8(0x0820) +#define USART1_RXDATAH _SFR_MEM8(0x0821) +#define USART1_TXDATAL _SFR_MEM8(0x0822) +#define USART1_TXDATAH _SFR_MEM8(0x0823) +#define USART1_STATUS _SFR_MEM8(0x0824) +#define USART1_CTRLA _SFR_MEM8(0x0825) +#define USART1_CTRLB _SFR_MEM8(0x0826) +#define USART1_CTRLC _SFR_MEM8(0x0827) +#define USART1_BAUD _SFR_MEM16(0x0828) +#define USART1_BAUDL _SFR_MEM8(0x0828) +#define USART1_BAUDH _SFR_MEM8(0x0829) +#define USART1_CTRLD _SFR_MEM8(0x082A) +#define USART1_DBGCTRL _SFR_MEM8(0x082B) +#define USART1_EVCTRL _SFR_MEM8(0x082C) +#define USART1_TXPLCTRL _SFR_MEM8(0x082D) +#define USART1_RXPLCTRL _SFR_MEM8(0x082E) + + +/* USART (USART2) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2_RXDATAL _SFR_MEM8(0x0840) +#define USART2_RXDATAH _SFR_MEM8(0x0841) +#define USART2_TXDATAL _SFR_MEM8(0x0842) +#define USART2_TXDATAH _SFR_MEM8(0x0843) +#define USART2_STATUS _SFR_MEM8(0x0844) +#define USART2_CTRLA _SFR_MEM8(0x0845) +#define USART2_CTRLB _SFR_MEM8(0x0846) +#define USART2_CTRLC _SFR_MEM8(0x0847) +#define USART2_BAUD _SFR_MEM16(0x0848) +#define USART2_BAUDL _SFR_MEM8(0x0848) +#define USART2_BAUDH _SFR_MEM8(0x0849) +#define USART2_CTRLD _SFR_MEM8(0x084A) +#define USART2_DBGCTRL _SFR_MEM8(0x084B) +#define USART2_EVCTRL _SFR_MEM8(0x084C) +#define USART2_TXPLCTRL _SFR_MEM8(0x084D) +#define USART2_RXPLCTRL _SFR_MEM8(0x084E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x08A0) +#define TWI0_DUALCTRL _SFR_MEM8(0x08A1) +#define TWI0_DBGCTRL _SFR_MEM8(0x08A2) +#define TWI0_MCTRLA _SFR_MEM8(0x08A3) +#define TWI0_MCTRLB _SFR_MEM8(0x08A4) +#define TWI0_MSTATUS _SFR_MEM8(0x08A5) +#define TWI0_MBAUD _SFR_MEM8(0x08A6) +#define TWI0_MADDR _SFR_MEM8(0x08A7) +#define TWI0_MDATA _SFR_MEM8(0x08A8) +#define TWI0_SCTRLA _SFR_MEM8(0x08A9) +#define TWI0_SCTRLB _SFR_MEM8(0x08AA) +#define TWI0_SSTATUS _SFR_MEM8(0x08AB) +#define TWI0_SADDR _SFR_MEM8(0x08AC) +#define TWI0_SDATA _SFR_MEM8(0x08AD) +#define TWI0_SADDRMASK _SFR_MEM8(0x08AE) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x08C0) +#define SPI0_CTRLB _SFR_MEM8(0x08C1) +#define SPI0_INTCTRL _SFR_MEM8(0x08C2) +#define SPI0_INTFLAGS _SFR_MEM8(0x08C3) +#define SPI0_DATA _SFR_MEM8(0x08C4) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A80) +#define TCB0_CTRLB _SFR_MEM8(0x0A81) +#define TCB0_EVCTRL _SFR_MEM8(0x0A84) +#define TCB0_INTCTRL _SFR_MEM8(0x0A85) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A86) +#define TCB0_STATUS _SFR_MEM8(0x0A87) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A88) +#define TCB0_TEMP _SFR_MEM8(0x0A89) +#define TCB0_CNT _SFR_MEM16(0x0A8A) +#define TCB0_CNTL _SFR_MEM8(0x0A8A) +#define TCB0_CNTH _SFR_MEM8(0x0A8B) +#define TCB0_CCMP _SFR_MEM16(0x0A8C) +#define TCB0_CCMPL _SFR_MEM8(0x0A8C) +#define TCB0_CCMPH _SFR_MEM8(0x0A8D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0A90) +#define TCB1_CTRLB _SFR_MEM8(0x0A91) +#define TCB1_EVCTRL _SFR_MEM8(0x0A94) +#define TCB1_INTCTRL _SFR_MEM8(0x0A95) +#define TCB1_INTFLAGS _SFR_MEM8(0x0A96) +#define TCB1_STATUS _SFR_MEM8(0x0A97) +#define TCB1_DBGCTRL _SFR_MEM8(0x0A98) +#define TCB1_TEMP _SFR_MEM8(0x0A99) +#define TCB1_CNT _SFR_MEM16(0x0A9A) +#define TCB1_CNTL _SFR_MEM8(0x0A9A) +#define TCB1_CNTH _SFR_MEM8(0x0A9B) +#define TCB1_CCMP _SFR_MEM16(0x0A9C) +#define TCB1_CCMPL _SFR_MEM8(0x0A9C) +#define TCB1_CCMPH _SFR_MEM8(0x0A9D) + + +/* TCB (TCB2) - 16-bit Timer Type B */ +#define TCB2_CTRLA _SFR_MEM8(0x0AA0) +#define TCB2_CTRLB _SFR_MEM8(0x0AA1) +#define TCB2_EVCTRL _SFR_MEM8(0x0AA4) +#define TCB2_INTCTRL _SFR_MEM8(0x0AA5) +#define TCB2_INTFLAGS _SFR_MEM8(0x0AA6) +#define TCB2_STATUS _SFR_MEM8(0x0AA7) +#define TCB2_DBGCTRL _SFR_MEM8(0x0AA8) +#define TCB2_TEMP _SFR_MEM8(0x0AA9) +#define TCB2_CNT _SFR_MEM16(0x0AAA) +#define TCB2_CNTL _SFR_MEM8(0x0AAA) +#define TCB2_CNTH _SFR_MEM8(0x0AAB) +#define TCB2_CCMP _SFR_MEM16(0x0AAC) +#define TCB2_CCMPL _SFR_MEM8(0x0AAC) +#define TCB2_CCMPH _SFR_MEM8(0x0AAD) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) +#define SYSCFG_OCDM _SFR_MEM8(0x0F18) +#define SYSCFG_OCDMS _SFR_MEM8(0x0F19) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_OSCCAL32K _SFR_MEM8(0x1114) +#define SIGROW_OSCCAL16M0 _SFR_MEM8(0x1118) +#define SIGROW_OSCCAL16M1 _SFR_MEM8(0x1119) +#define SIGROW_OSCCAL20M0 _SFR_MEM8(0x111A) +#define SIGROW_OSCCAL20M1 _SFR_MEM8(0x111B) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) +#define SIGROW_CHECKSUM1 _SFR_MEM8(0x112F) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) +#define USERROW_USERROW32 _SFR_MEM8(0x1320) +#define USERROW_USERROW33 _SFR_MEM8(0x1321) +#define USERROW_USERROW34 _SFR_MEM8(0x1322) +#define USERROW_USERROW35 _SFR_MEM8(0x1323) +#define USERROW_USERROW36 _SFR_MEM8(0x1324) +#define USERROW_USERROW37 _SFR_MEM8(0x1325) +#define USERROW_USERROW38 _SFR_MEM8(0x1326) +#define USERROW_USERROW39 _SFR_MEM8(0x1327) +#define USERROW_USERROW40 _SFR_MEM8(0x1328) +#define USERROW_USERROW41 _SFR_MEM8(0x1329) +#define USERROW_USERROW42 _SFR_MEM8(0x132A) +#define USERROW_USERROW43 _SFR_MEM8(0x132B) +#define USERROW_USERROW44 _SFR_MEM8(0x132C) +#define USERROW_USERROW45 _SFR_MEM8(0x132D) +#define USERROW_USERROW46 _SFR_MEM8(0x132E) +#define USERROW_USERROW47 _SFR_MEM8(0x132F) +#define USERROW_USERROW48 _SFR_MEM8(0x1330) +#define USERROW_USERROW49 _SFR_MEM8(0x1331) +#define USERROW_USERROW50 _SFR_MEM8(0x1332) +#define USERROW_USERROW51 _SFR_MEM8(0x1333) +#define USERROW_USERROW52 _SFR_MEM8(0x1334) +#define USERROW_USERROW53 _SFR_MEM8(0x1335) +#define USERROW_USERROW54 _SFR_MEM8(0x1336) +#define USERROW_USERROW55 _SFR_MEM8(0x1337) +#define USERROW_USERROW56 _SFR_MEM8(0x1338) +#define USERROW_USERROW57 _SFR_MEM8(0x1339) +#define USERROW_USERROW58 _SFR_MEM8(0x133A) +#define USERROW_USERROW59 _SFR_MEM8(0x133B) +#define USERROW_USERROW60 _SFR_MEM8(0x133C) +#define USERROW_USERROW61 _SFR_MEM8(0x133D) +#define USERROW_USERROW62 _SFR_MEM8(0x133E) +#define USERROW_USERROW63 _SFR_MEM8(0x133F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.DACREF bit masks and bit positions */ +#define AC_DATA_gm 0xFF /* DAC voltage reference group mask. */ +#define AC_DATA_gp 0 /* DAC voltage reference group position. */ +#define AC_DATA0_bm (1<<0) /* DAC voltage reference bit 0 mask. */ +#define AC_DATA0_bp 0 /* DAC voltage reference bit 0 position. */ +#define AC_DATA1_bm (1<<1) /* DAC voltage reference bit 1 mask. */ +#define AC_DATA1_bp 1 /* DAC voltage reference bit 1 position. */ +#define AC_DATA2_bm (1<<2) /* DAC voltage reference bit 2 mask. */ +#define AC_DATA2_bp 2 /* DAC voltage reference bit 2 position. */ +#define AC_DATA3_bm (1<<3) /* DAC voltage reference bit 3 mask. */ +#define AC_DATA3_bp 3 /* DAC voltage reference bit 3 position. */ +#define AC_DATA4_bm (1<<4) /* DAC voltage reference bit 4 mask. */ +#define AC_DATA4_bp 4 /* DAC voltage reference bit 4 position. */ +#define AC_DATA5_bm (1<<5) /* DAC voltage reference bit 5 mask. */ +#define AC_DATA5_bp 5 /* DAC voltage reference bit 5 position. */ +#define AC_DATA6_bm (1<<6) /* DAC voltage reference bit 6 mask. */ +#define AC_DATA6_bp 6 /* DAC voltage reference bit 6 position. */ +#define AC_DATA7_bm (1<<7) /* DAC voltage reference bit 7 mask. */ +#define AC_DATA7_bp 7 /* DAC voltage reference bit 7 position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL0_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL0_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL00_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL00_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL01_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL01_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL02_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL02_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.SEQCTRL1 bit masks and bit positions */ +#define CCL_SEQSEL1_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL1_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL10_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL10_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL11_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL11_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL12_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL12_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.INTCTRL0 bit masks and bit positions */ +#define CCL_INTMODE0_gm 0x03 /* Interrupt Mode for LUT0 group mask. */ +#define CCL_INTMODE0_gp 0 /* Interrupt Mode for LUT0 group position. */ +#define CCL_INTMODE00_bm (1<<0) /* Interrupt Mode for LUT0 bit 0 mask. */ +#define CCL_INTMODE00_bp 0 /* Interrupt Mode for LUT0 bit 0 position. */ +#define CCL_INTMODE01_bm (1<<1) /* Interrupt Mode for LUT0 bit 1 mask. */ +#define CCL_INTMODE01_bp 1 /* Interrupt Mode for LUT0 bit 1 position. */ +#define CCL_INTMODE1_gm 0x0C /* Interrupt Mode for LUT1 group mask. */ +#define CCL_INTMODE1_gp 2 /* Interrupt Mode for LUT1 group position. */ +#define CCL_INTMODE10_bm (1<<2) /* Interrupt Mode for LUT1 bit 0 mask. */ +#define CCL_INTMODE10_bp 2 /* Interrupt Mode for LUT1 bit 0 position. */ +#define CCL_INTMODE11_bm (1<<3) /* Interrupt Mode for LUT1 bit 1 mask. */ +#define CCL_INTMODE11_bp 3 /* Interrupt Mode for LUT1 bit 1 position. */ +#define CCL_INTMODE2_gm 0x30 /* Interrupt Mode for LUT2 group mask. */ +#define CCL_INTMODE2_gp 4 /* Interrupt Mode for LUT2 group position. */ +#define CCL_INTMODE20_bm (1<<4) /* Interrupt Mode for LUT2 bit 0 mask. */ +#define CCL_INTMODE20_bp 4 /* Interrupt Mode for LUT2 bit 0 position. */ +#define CCL_INTMODE21_bm (1<<5) /* Interrupt Mode for LUT2 bit 1 mask. */ +#define CCL_INTMODE21_bp 5 /* Interrupt Mode for LUT2 bit 1 position. */ +#define CCL_INTMODE3_gm 0xC0 /* Interrupt Mode for LUT3 group mask. */ +#define CCL_INTMODE3_gp 6 /* Interrupt Mode for LUT3 group position. */ +#define CCL_INTMODE30_bm (1<<6) /* Interrupt Mode for LUT3 bit 0 mask. */ +#define CCL_INTMODE30_bp 6 /* Interrupt Mode for LUT3 bit 0 position. */ +#define CCL_INTMODE31_bm (1<<7) /* Interrupt Mode for LUT3 bit 1 mask. */ +#define CCL_INTMODE31_bp 7 /* Interrupt Mode for LUT3 bit 1 position. */ + +/* CCL.INTFLAGS bit masks and bit positions */ +#define CCL_INT_gm 0x0F /* Interrupt Flags group mask. */ +#define CCL_INT_gp 0 /* Interrupt Flags group position. */ +#define CCL_INT0_bm (1<<0) /* Interrupt Flags bit 0 mask. */ +#define CCL_INT0_bp 0 /* Interrupt Flags bit 0 position. */ +#define CCL_INT1_bm (1<<1) /* Interrupt Flags bit 1 mask. */ +#define CCL_INT1_bp 1 /* Interrupt Flags bit 1 position. */ +#define CCL_INT2_bm (1<<2) /* Interrupt Flags bit 2 mask. */ +#define CCL_INT2_bp 2 /* Interrupt Flags bit 2 position. */ +#define CCL_INT3_bm (1<<3) /* Interrupt Flags bit 3 mask. */ +#define CCL_INT3_bp 3 /* Interrupt Flags bit 3 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_CLKSRC_gm 0x0E /* Clock Source Selection group mask. */ +#define CCL_CLKSRC_gp 1 /* Clock Source Selection group position. */ +#define CCL_CLKSRC0_bm (1<<1) /* Clock Source Selection bit 0 mask. */ +#define CCL_CLKSRC0_bp 1 /* Clock Source Selection bit 0 position. */ +#define CCL_CLKSRC1_bm (1<<2) /* Clock Source Selection bit 1 mask. */ +#define CCL_CLKSRC1_bp 2 /* Clock Source Selection bit 1 position. */ +#define CCL_CLKSRC2_bm (1<<3) /* Clock Source Selection bit 2 mask. */ +#define CCL_CLKSRC2_bp 3 /* Clock Source Selection bit 2 position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_OUTEN_bm 0x40 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 6 /* Output Enable bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT2CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT2CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT2CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT3CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT3CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT3CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x7F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ +#define CLKCTRL_CAL20M6_bm (1<<6) /* Calibration bit 6 mask. */ +#define CLKCTRL_CAL20M6_bp 6 /* Calibration bit 6 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.STROBE bit masks and bit positions */ +#define EVSYS_STROBE0_gm 0xFF /* Software event on channels group mask. */ +#define EVSYS_STROBE0_gp 0 /* Software event on channels group position. */ +#define EVSYS_STROBE00_bm (1<<0) /* Software event on channels bit 0 mask. */ +#define EVSYS_STROBE00_bp 0 /* Software event on channels bit 0 position. */ +#define EVSYS_STROBE01_bm (1<<1) /* Software event on channels bit 1 mask. */ +#define EVSYS_STROBE01_bp 1 /* Software event on channels bit 1 position. */ +#define EVSYS_STROBE02_bm (1<<2) /* Software event on channels bit 2 mask. */ +#define EVSYS_STROBE02_bp 2 /* Software event on channels bit 2 position. */ +#define EVSYS_STROBE03_bm (1<<3) /* Software event on channels bit 3 mask. */ +#define EVSYS_STROBE03_bp 3 /* Software event on channels bit 3 position. */ +#define EVSYS_STROBE04_bm (1<<4) /* Software event on channels bit 4 mask. */ +#define EVSYS_STROBE04_bp 4 /* Software event on channels bit 4 position. */ +#define EVSYS_STROBE05_bm (1<<5) /* Software event on channels bit 5 mask. */ +#define EVSYS_STROBE05_bp 5 /* Software event on channels bit 5 position. */ +#define EVSYS_STROBE06_bm (1<<6) /* Software event on channels bit 6 mask. */ +#define EVSYS_STROBE06_bp 6 /* Software event on channels bit 6 position. */ +#define EVSYS_STROBE07_bm (1<<7) /* Software event on channels bit 7 mask. */ +#define EVSYS_STROBE07_bp 7 /* Software event on channels bit 7 position. */ + +/* EVSYS.CHANNEL0 bit masks and bit positions */ +#define EVSYS_GENERATOR_gm 0xFF /* Generator selector group mask. */ +#define EVSYS_GENERATOR_gp 0 /* Generator selector group position. */ +#define EVSYS_GENERATOR0_bm (1<<0) /* Generator selector bit 0 mask. */ +#define EVSYS_GENERATOR0_bp 0 /* Generator selector bit 0 position. */ +#define EVSYS_GENERATOR1_bm (1<<1) /* Generator selector bit 1 mask. */ +#define EVSYS_GENERATOR1_bp 1 /* Generator selector bit 1 position. */ +#define EVSYS_GENERATOR2_bm (1<<2) /* Generator selector bit 2 mask. */ +#define EVSYS_GENERATOR2_bp 2 /* Generator selector bit 2 position. */ +#define EVSYS_GENERATOR3_bm (1<<3) /* Generator selector bit 3 mask. */ +#define EVSYS_GENERATOR3_bp 3 /* Generator selector bit 3 position. */ +#define EVSYS_GENERATOR4_bm (1<<4) /* Generator selector bit 4 mask. */ +#define EVSYS_GENERATOR4_bp 4 /* Generator selector bit 4 position. */ +#define EVSYS_GENERATOR5_bm (1<<5) /* Generator selector bit 5 mask. */ +#define EVSYS_GENERATOR5_bp 5 /* Generator selector bit 5 position. */ +#define EVSYS_GENERATOR6_bm (1<<6) /* Generator selector bit 6 mask. */ +#define EVSYS_GENERATOR6_bp 6 /* Generator selector bit 6 position. */ +#define EVSYS_GENERATOR7_bm (1<<7) /* Generator selector bit 7 mask. */ +#define EVSYS_GENERATOR7_bp 7 /* Generator selector bit 7 position. */ + +/* EVSYS.CHANNEL1 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL2 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL3 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL4 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL5 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.USERCCLLUT0A bit masks and bit positions */ +#define EVSYS_CHANNEL_gm 0xFF /* Channel selector group mask. */ +#define EVSYS_CHANNEL_gp 0 /* Channel selector group position. */ +#define EVSYS_CHANNEL0_bm (1<<0) /* Channel selector bit 0 mask. */ +#define EVSYS_CHANNEL0_bp 0 /* Channel selector bit 0 position. */ +#define EVSYS_CHANNEL1_bm (1<<1) /* Channel selector bit 1 mask. */ +#define EVSYS_CHANNEL1_bp 1 /* Channel selector bit 1 position. */ +#define EVSYS_CHANNEL2_bm (1<<2) /* Channel selector bit 2 mask. */ +#define EVSYS_CHANNEL2_bp 2 /* Channel selector bit 2 position. */ +#define EVSYS_CHANNEL3_bm (1<<3) /* Channel selector bit 3 mask. */ +#define EVSYS_CHANNEL3_bp 3 /* Channel selector bit 3 position. */ +#define EVSYS_CHANNEL4_bm (1<<4) /* Channel selector bit 4 mask. */ +#define EVSYS_CHANNEL4_bp 4 /* Channel selector bit 4 position. */ +#define EVSYS_CHANNEL5_bm (1<<5) /* Channel selector bit 5 mask. */ +#define EVSYS_CHANNEL5_bp 5 /* Channel selector bit 5 position. */ +#define EVSYS_CHANNEL6_bm (1<<6) /* Channel selector bit 6 mask. */ +#define EVSYS_CHANNEL6_bp 6 /* Channel selector bit 6 position. */ +#define EVSYS_CHANNEL7_bm (1<<7) /* Channel selector bit 7 mask. */ +#define EVSYS_CHANNEL7_bp 7 /* Channel selector bit 7 position. */ + +/* EVSYS.USERCCLLUT0B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT1A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT1B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT2A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT2B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT3A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT3B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERADC0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTA bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTB bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTC bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTD bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTE bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTF bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART1 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART2 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART3 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCA0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB1 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB2 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB3 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_bm 0x08 /* Reset Pin Configuration bit mask. */ +#define FUSE_RSTPINCFG_bp 3 /* Reset Pin Configuration bit position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PORTCTRL bit masks and bit positions */ +#define PORT_SRL_bm 0x01 /* Slew Rate Limit Enable bit mask. */ +#define PORT_SRL_bp 0 /* Slew Rate Limit Enable bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.EVSYSROUTEA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_EVOUT3_bm 0x08 /* Event Output 3 bit mask. */ +#define PORTMUX_EVOUT3_bp 3 /* Event Output 3 bit position. */ +#define PORTMUX_EVOUT4_bm 0x10 /* Event Output 4 bit mask. */ +#define PORTMUX_EVOUT4_bp 4 /* Event Output 4 bit position. */ +#define PORTMUX_EVOUT5_bm 0x20 /* Event Output 5 bit mask. */ +#define PORTMUX_EVOUT5_bp 5 /* Event Output 5 bit position. */ + +/* PORTMUX.CCLROUTEA bit masks and bit positions */ +#define PORTMUX_LUT0_bm 0x01 /* CCL LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 0 /* CCL LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x02 /* CCL LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 1 /* CCL LUT1 bit position. */ +#define PORTMUX_LUT2_bm 0x04 /* CCL LUT2 bit mask. */ +#define PORTMUX_LUT2_bp 2 /* CCL LUT2 bit position. */ +#define PORTMUX_LUT3_bm 0x08 /* CCL LUT3 bit mask. */ +#define PORTMUX_LUT3_bp 3 /* CCL LUT3 bit position. */ + +/* PORTMUX.USARTROUTEA bit masks and bit positions */ +#define PORTMUX_USART0_gm 0x03 /* Port Multiplexer USART0 group mask. */ +#define PORTMUX_USART0_gp 0 /* Port Multiplexer USART0 group position. */ +#define PORTMUX_USART00_bm (1<<0) /* Port Multiplexer USART0 bit 0 mask. */ +#define PORTMUX_USART00_bp 0 /* Port Multiplexer USART0 bit 0 position. */ +#define PORTMUX_USART01_bm (1<<1) /* Port Multiplexer USART0 bit 1 mask. */ +#define PORTMUX_USART01_bp 1 /* Port Multiplexer USART0 bit 1 position. */ +#define PORTMUX_USART1_gm 0x0C /* Port Multiplexer USART1 group mask. */ +#define PORTMUX_USART1_gp 2 /* Port Multiplexer USART1 group position. */ +#define PORTMUX_USART10_bm (1<<2) /* Port Multiplexer USART1 bit 0 mask. */ +#define PORTMUX_USART10_bp 2 /* Port Multiplexer USART1 bit 0 position. */ +#define PORTMUX_USART11_bm (1<<3) /* Port Multiplexer USART1 bit 1 mask. */ +#define PORTMUX_USART11_bp 3 /* Port Multiplexer USART1 bit 1 position. */ +#define PORTMUX_USART2_gm 0x30 /* Port Multiplexer USART2 group mask. */ +#define PORTMUX_USART2_gp 4 /* Port Multiplexer USART2 group position. */ +#define PORTMUX_USART20_bm (1<<4) /* Port Multiplexer USART2 bit 0 mask. */ +#define PORTMUX_USART20_bp 4 /* Port Multiplexer USART2 bit 0 position. */ +#define PORTMUX_USART21_bm (1<<5) /* Port Multiplexer USART2 bit 1 mask. */ +#define PORTMUX_USART21_bp 5 /* Port Multiplexer USART2 bit 1 position. */ +#define PORTMUX_USART3_gm 0xC0 /* Port Multiplexer USART3 group mask. */ +#define PORTMUX_USART3_gp 6 /* Port Multiplexer USART3 group position. */ +#define PORTMUX_USART30_bm (1<<6) /* Port Multiplexer USART3 bit 0 mask. */ +#define PORTMUX_USART30_bp 6 /* Port Multiplexer USART3 bit 0 position. */ +#define PORTMUX_USART31_bm (1<<7) /* Port Multiplexer USART3 bit 1 mask. */ +#define PORTMUX_USART31_bp 7 /* Port Multiplexer USART3 bit 1 position. */ + +/* PORTMUX.TWISPIROUTEA bit masks and bit positions */ +#define PORTMUX_SPI0_gm 0x03 /* Port Multiplexer SPI0 group mask. */ +#define PORTMUX_SPI0_gp 0 /* Port Multiplexer SPI0 group position. */ +#define PORTMUX_SPI00_bm (1<<0) /* Port Multiplexer SPI0 bit 0 mask. */ +#define PORTMUX_SPI00_bp 0 /* Port Multiplexer SPI0 bit 0 position. */ +#define PORTMUX_SPI01_bm (1<<1) /* Port Multiplexer SPI0 bit 1 mask. */ +#define PORTMUX_SPI01_bp 1 /* Port Multiplexer SPI0 bit 1 position. */ +#define PORTMUX_TWI0_gm 0x30 /* Port Multiplexer TWI0 group mask. */ +#define PORTMUX_TWI0_gp 4 /* Port Multiplexer TWI0 group position. */ +#define PORTMUX_TWI00_bm (1<<4) /* Port Multiplexer TWI0 bit 0 mask. */ +#define PORTMUX_TWI00_bp 4 /* Port Multiplexer TWI0 bit 0 position. */ +#define PORTMUX_TWI01_bm (1<<5) /* Port Multiplexer TWI0 bit 1 mask. */ +#define PORTMUX_TWI01_bp 5 /* Port Multiplexer TWI0 bit 1 position. */ + +/* PORTMUX.TCAROUTEA bit masks and bit positions */ +#define PORTMUX_TCA0_gm 0x07 /* Port Multiplexer TCA0 group mask. */ +#define PORTMUX_TCA0_gp 0 /* Port Multiplexer TCA0 group position. */ +#define PORTMUX_TCA00_bm (1<<0) /* Port Multiplexer TCA0 bit 0 mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 bit 0 position. */ +#define PORTMUX_TCA01_bm (1<<1) /* Port Multiplexer TCA0 bit 1 mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 bit 1 position. */ +#define PORTMUX_TCA02_bm (1<<2) /* Port Multiplexer TCA0 bit 2 mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 bit 2 position. */ + +/* PORTMUX.TCBROUTEA bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ +#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ +#define PORTMUX_TCB2_bm 0x04 /* Port Multiplexer TCB2 bit mask. */ +#define PORTMUX_TCB2_bp 2 /* Port Multiplexer TCB2 bit position. */ +#define PORTMUX_TCB3_bm 0x08 /* Port Multiplexer TCB3 bit mask. */ +#define PORTMUX_TCB3_bp 3 /* Port Multiplexer TCB3 bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_CORREN_bm 0x04 /* Correction enable bit mask. */ +#define RTC_CORREN_bp 2 /* Correction enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_ERROR_gm 0x7F /* Error Correction Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Correction Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Correction Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Correction Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Correction Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Correction Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Correction Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Correction Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Correction Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Correction Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Correction Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Correction Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Correction Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Correction Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Correction Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Correction Value bit 6 position. */ +#define RTC_SIGN_bm 0x80 /* Error Correction Sign Bit bit mask. */ +#define RTC_SIGN_bp 7 /* Error Correction Sign Bit bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + + +/* SYSCFG.OCDMS bit masks and bit positions */ +#define SYSCFG_OCDMR_bm 0x01 /* OCD Message Read bit mask. */ +#define SYSCFG_OCDMR_bp 0 /* OCD Message Read bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DUALCTRL bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Dual Control Enable bit mask. */ +#define TWI_ENABLE_bp 0 /* Dual Control Enable bit position. */ +/* TWI_FMPEN is already defined. */ +/* TWI_SDAHOLD is already defined. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.CTRLD bit masks and bit positions */ +#define USART_ABW_gm 0xC0 /* Auto Baud Window group mask. */ +#define USART_ABW_gp 6 /* Auto Baud Window group position. */ +#define USART_ABW0_bm (1<<6) /* Auto Baud Window bit 0 mask. */ +#define USART_ABW0_bp 6 /* Auto Baud Window bit 0 position. */ +#define USART_ABW1_bm (1<<7) /* Auto Baud Window bit 1 mask. */ +#define USART_ABW1_bp 7 /* Auto Baud Window bit 1 position. */ + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_AC0REFSEL_gm 0x07 /* AC0 reference select group mask. */ +#define VREF_AC0REFSEL_gp 0 /* AC0 reference select group position. */ +#define VREF_AC0REFSEL0_bm (1<<0) /* AC0 reference select bit 0 mask. */ +#define VREF_AC0REFSEL0_bp 0 /* AC0 reference select bit 0 position. */ +#define VREF_AC0REFSEL1_bm (1<<1) /* AC0 reference select bit 1 mask. */ +#define VREF_AC0REFSEL1_bp 1 /* AC0 reference select bit 1 position. */ +#define VREF_AC0REFSEL2_bm (1<<2) /* AC0 reference select bit 2 mask. */ +#define VREF_AC0REFSEL2_bp 2 /* AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_AC0REFEN_bm 0x01 /* AC0 DACREF reference enable bit mask. */ +#define VREF_AC0REFEN_bp 0 /* AC0 DACREF reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 3 +#define RTC_CNT_vect _VECTOR(3) /* */ +#define RTC_PIT_vect_num 4 +#define RTC_PIT_vect _VECTOR(4) /* */ + +/* CCL interrupt vectors */ +#define CCL_CCL_vect_num 5 +#define CCL_CCL_vect _VECTOR(5) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 6 +#define PORTA_PORT_vect _VECTOR(6) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 7 +#define TCA0_LUNF_vect _VECTOR(7) /* */ +#define TCA0_OVF_vect_num 7 +#define TCA0_OVF_vect _VECTOR(7) /* */ +#define TCA0_HUNF_vect_num 8 +#define TCA0_HUNF_vect _VECTOR(8) /* */ +#define TCA0_CMP0_vect_num 9 +#define TCA0_CMP0_vect _VECTOR(9) /* */ +#define TCA0_LCMP0_vect_num 9 +#define TCA0_LCMP0_vect _VECTOR(9) /* */ +#define TCA0_CMP1_vect_num 10 +#define TCA0_CMP1_vect _VECTOR(10) /* */ +#define TCA0_LCMP1_vect_num 10 +#define TCA0_LCMP1_vect _VECTOR(10) /* */ +#define TCA0_CMP2_vect_num 11 +#define TCA0_CMP2_vect _VECTOR(11) /* */ +#define TCA0_LCMP2_vect_num 11 +#define TCA0_LCMP2_vect _VECTOR(11) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 12 +#define TCB0_INT_vect _VECTOR(12) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 13 +#define TCB1_INT_vect _VECTOR(13) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 14 +#define TWI0_TWIS_vect _VECTOR(14) /* */ +#define TWI0_TWIM_vect_num 15 +#define TWI0_TWIM_vect _VECTOR(15) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 16 +#define SPI0_INT_vect _VECTOR(16) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 17 +#define USART0_RXC_vect _VECTOR(17) /* */ +#define USART0_DRE_vect_num 18 +#define USART0_DRE_vect _VECTOR(18) /* */ +#define USART0_TXC_vect_num 19 +#define USART0_TXC_vect _VECTOR(19) /* */ + +/* PORTD interrupt vectors */ +#define PORTD_PORT_vect_num 20 +#define PORTD_PORT_vect _VECTOR(20) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 21 +#define AC0_AC_vect _VECTOR(21) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 22 +#define ADC0_RESRDY_vect _VECTOR(22) /* */ +#define ADC0_WCOMP_vect_num 23 +#define ADC0_WCOMP_vect _VECTOR(23) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 24 +#define PORTC_PORT_vect _VECTOR(24) /* */ + +/* TCB2 interrupt vectors */ +#define TCB2_INT_vect_num 25 +#define TCB2_INT_vect _VECTOR(25) /* */ + +/* USART1 interrupt vectors */ +#define USART1_RXC_vect_num 26 +#define USART1_RXC_vect _VECTOR(26) /* */ +#define USART1_DRE_vect_num 27 +#define USART1_DRE_vect _VECTOR(27) /* */ +#define USART1_TXC_vect_num 28 +#define USART1_TXC_vect _VECTOR(28) /* */ + +/* PORTF interrupt vectors */ +#define PORTF_PORT_vect_num 29 +#define PORTF_PORT_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +/* USART2 interrupt vectors */ +#define USART2_RXC_vect_num 31 +#define USART2_RXC_vect _VECTOR(31) /* */ +#define USART2_DRE_vect_num 32 +#define USART2_DRE_vect _VECTOR(32) /* */ +#define USART2_TXC_vect_num 33 +#define USART2_TXC_vect _VECTOR(33) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 34 +#define PORTB_PORT_vect _VECTOR(34) /* */ + +/* PORTE interrupt vectors */ +#define PORTE_PORT_vect_num 35 +#define PORTE_PORT_vect _VECTOR(35) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (36 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (8192) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (8192U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3C00) +# define INTERNAL_SRAM_SIZE (1024) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3C00U) +# define INTERNAL_SRAM_SIZE (1024U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x4000) +# define MAPPED_PROGMEM_SIZE (8192) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x4000U) +# define MAPPED_PROGMEM_SIZE (8192U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (8192) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (8192U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG (unsigned char)_BV(3) /* Reset Pin Configuration */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x26 + + +#endif /* #ifdef _AVR_ATMEGA808_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iom809.h b/hardware/tools/avr/avr/include/avr/iom809.h new file mode 100644 index 0000000000000000000000000000000000000000..43401149f4fb38273609ea64af9314630910f9c0 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom809.h @@ -0,0 +1,5017 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom809.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATMEGA809_H_INCLUDED +#define _AVR_ATMEGA809_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[1]; + register8_t DACREF; /* Referance scale control */ + register8_t reserved_3[1]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_PIN2_gc = (0x02<<0), /* Negative Pin 2 */ + AC_MUXNEG_DACREF_gc = (0x03<<0), /* DAC Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ + ADC_MUXPOS_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ + ADC_MUXPOS_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ + ADC_MUXPOS_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ + ADC_MUXPOS_DACREF_gc = (0x1C<<0), /* AC DAC Reference */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temperature sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* 0V (GND) */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t SEQCTRL1; /* Sequential Control 1 */ + register8_t reserved_1[2]; + register8_t INTCTRL0; /* Interrupt Control 0 */ + register8_t reserved_2[1]; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t LUT2CTRLA; /* LUT Control 2 A */ + register8_t LUT2CTRLB; /* LUT Control 2 B */ + register8_t LUT2CTRLC; /* LUT Control 2 C */ + register8_t TRUTH2; /* Truth 2 */ + register8_t LUT3CTRLA; /* LUT Control 3 A */ + register8_t LUT3CTRLB; /* LUT Control 3 B */ + register8_t LUT3CTRLC; /* LUT Control 3 C */ + register8_t TRUTH3; /* Truth 3 */ + register8_t reserved_3[40]; +} CCL_t; + +/* Clock Source Selection select */ +typedef enum CCL_CLKSRC_enum +{ + CCL_CLKSRC_CLKPER_gc = (0x00<<1), /* CLK_PER is clocking the LUT */ + CCL_CLKSRC_IN2_gc = (0x01<<1), /* IN[2] is clocking the LUT */ + CCL_CLKSRC_OSC20M_gc = (0x04<<1), /* 20MHz oscillator before prescaler is clocking the LUT */ + CCL_CLKSRC_OSCULP32K_gc = (0x05<<1), /* 32kHz oscillator is clocking the LUT */ + CCL_CLKSRC_OSCULP1K_gc = (0x06<<1), /* 32kHz oscillator after DIV32 is clocking the LUT */ +} CCL_CLKSRC_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL0_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_USART0_gc = (0x08<<0), /* USART0 TXD input source */ + CCL_INSEL0_SPI0_gc = (0x09<<0), /* SPI0 MOSI input source */ + CCL_INSEL0_TCA0_gc = (0x0A<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCB0_gc = (0x0C<<0), /* TCB0 WO input source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENTA_gc = (0x03<<4), /* Event input source A */ + CCL_INSEL1_EVENTB_gc = (0x04<<4), /* Event input source B */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_USART1_gc = (0x08<<4), /* USART1 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x09<<4), /* SPI0 MOSI input source */ + CCL_INSEL1_TCA0_gc = (0x0A<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCB1_gc = (0x0C<<4), /* TCB1 WO input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL2_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_USART2_gc = (0x08<<0), /* USART2 TXD input source */ + CCL_INSEL2_SPI0_gc = (0x09<<0), /* SPI0 SCK input source */ + CCL_INSEL2_TCA0_gc = (0x0A<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCB2_gc = (0x0C<<0), /* TCB2 WO input source */ +} CCL_INSEL2_t; + +/* Interrupt Mode for LUT0 select */ +typedef enum CCL_INTMODE0_enum +{ + CCL_INTMODE0_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled */ + CCL_INTMODE0_RISING_gc = (0x01<<0), /* Sense rising edge */ + CCL_INTMODE0_FALLING_gc = (0x02<<0), /* Sense falling edge */ + CCL_INTMODE0_BOTH_gc = (0x03<<0), /* Sense both edges */ +} CCL_INTMODE0_t; + +/* Interrupt Mode for LUT1 select */ +typedef enum CCL_INTMODE1_enum +{ + CCL_INTMODE1_INTDISABLE_gc = (0x00<<2), /* Interrupt disabled */ + CCL_INTMODE1_RISING_gc = (0x01<<2), /* Sense rising edge */ + CCL_INTMODE1_FALLING_gc = (0x02<<2), /* Sense falling edge */ + CCL_INTMODE1_BOTH_gc = (0x03<<2), /* Sense both edges */ +} CCL_INTMODE1_t; + +/* Interrupt Mode for LUT2 select */ +typedef enum CCL_INTMODE2_enum +{ + CCL_INTMODE2_INTDISABLE_gc = (0x00<<4), /* Interrupt disabled */ + CCL_INTMODE2_RISING_gc = (0x01<<4), /* Sense rising edge */ + CCL_INTMODE2_FALLING_gc = (0x02<<4), /* Sense falling edge */ + CCL_INTMODE2_BOTH_gc = (0x03<<4), /* Sense both edges */ +} CCL_INTMODE2_t; + +/* Interrupt Mode for LUT3 select */ +typedef enum CCL_INTMODE3_enum +{ + CCL_INTMODE3_INTDISABLE_gc = (0x00<<6), /* Interrupt disabled */ + CCL_INTMODE3_RISING_gc = (0x01<<6), /* Sense rising edge */ + CCL_INTMODE3_FALLING_gc = (0x02<<6), /* Sense falling edge */ + CCL_INTMODE3_BOTH_gc = (0x03<<6), /* Sense both edges */ +} CCL_INTMODE3_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL0_enum +{ + CCL_SEQSEL0_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL0_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL0_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL0_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL0_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL0_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL1_enum +{ + CCL_SEQSEL1_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL1_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL1_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL1_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL1_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL1_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1k cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16k cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32k cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t STROBE; /* Channel Strobe */ + register8_t reserved_1[15]; + register8_t CHANNEL0; /* Multiplexer Channel 0 */ + register8_t CHANNEL1; /* Multiplexer Channel 1 */ + register8_t CHANNEL2; /* Multiplexer Channel 2 */ + register8_t CHANNEL3; /* Multiplexer Channel 3 */ + register8_t CHANNEL4; /* Multiplexer Channel 4 */ + register8_t CHANNEL5; /* Multiplexer Channel 5 */ + register8_t CHANNEL6; /* Multiplexer Channel 6 */ + register8_t CHANNEL7; /* Multiplexer Channel 7 */ + register8_t reserved_2[8]; + register8_t USERCCLLUT0A; /* User CCL LUT0 Event A */ + register8_t USERCCLLUT0B; /* User CCL LUT0 Event B */ + register8_t USERCCLLUT1A; /* User CCL LUT1 Event A */ + register8_t USERCCLLUT1B; /* User CCL LUT1 Event B */ + register8_t USERCCLLUT2A; /* User CCL LUT2 Event A */ + register8_t USERCCLLUT2B; /* User CCL LUT2 Event B */ + register8_t USERCCLLUT3A; /* User CCL LUT3 Event A */ + register8_t USERCCLLUT3B; /* User CCL LUT3 Event B */ + register8_t USERADC0; /* User ADC0 */ + register8_t USEREVOUTA; /* User EVOUT Port A */ + register8_t USEREVOUTB; /* User EVOUT Port B */ + register8_t USEREVOUTC; /* User EVOUT Port C */ + register8_t USEREVOUTD; /* User EVOUT Port D */ + register8_t USEREVOUTE; /* User EVOUT Port E */ + register8_t USEREVOUTF; /* User EVOUT Port F */ + register8_t USERUSART0; /* User USART0 */ + register8_t USERUSART1; /* User USART1 */ + register8_t USERUSART2; /* User USART2 */ + register8_t USERUSART3; /* User USART3 */ + register8_t USERTCA0; /* User TCA0 */ + register8_t USERTCB0; /* User TCB0 */ + register8_t USERTCB1; /* User TCB1 */ + register8_t USERTCB2; /* User TCB2 */ + register8_t USERTCB3; /* User TCB3 */ + register8_t reserved_3[8]; +} EVSYS_t; + +/* Channel selector select */ +typedef enum EVSYS_CHANNEL_enum +{ + EVSYS_CHANNEL_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL_CHANNEL0_gc = (0x01<<0), /* Connect user to event channel 0 */ + EVSYS_CHANNEL_CHANNEL1_gc = (0x02<<0), /* Connect user to event channel 1 */ + EVSYS_CHANNEL_CHANNEL2_gc = (0x03<<0), /* Connect user to event channel 2 */ + EVSYS_CHANNEL_CHANNEL3_gc = (0x04<<0), /* Connect user to event channel 3 */ + EVSYS_CHANNEL_CHANNEL4_gc = (0x05<<0), /* Connect user to event channel 4 */ + EVSYS_CHANNEL_CHANNEL5_gc = (0x06<<0), /* Connect user to event channel 5 */ + EVSYS_CHANNEL_CHANNEL6_gc = (0x07<<0), /* Connect user to event channel 6 */ + EVSYS_CHANNEL_CHANNEL7_gc = (0x08<<0), /* Connect user to event channel 7 */ +} EVSYS_CHANNEL_t; + +/* Generator selector select */ +typedef enum EVSYS_GENERATOR_enum +{ + EVSYS_GENERATOR_OFF_gc = (0x00<<0), /* Off */ + EVSYS_GENERATOR_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_GENERATOR_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_GENERATOR_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_GENERATOR_RTC_PIT0_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_GENERATOR_RTC_PIT1_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_GENERATOR_RTC_PIT2_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_GENERATOR_RTC_PIT3_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_GENERATOR_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_GENERATOR_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_GENERATOR_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_GENERATOR_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_GENERATOR_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_GENERATOR_ADC0_RESRDY_gc = (0x24<<0), /* ADC 0 Result Ready Event */ + EVSYS_GENERATOR_PORT0_PIN0_gc = (0x40<<0), /* Port 0 Pin 0 */ + EVSYS_GENERATOR_PORT0_PIN1_gc = (0x41<<0), /* Port 0 Pin 1 */ + EVSYS_GENERATOR_PORT0_PIN2_gc = (0x42<<0), /* Port 0 Pin 2 */ + EVSYS_GENERATOR_PORT0_PIN3_gc = (0x43<<0), /* Port 0 Pin 3 */ + EVSYS_GENERATOR_PORT0_PIN4_gc = (0x44<<0), /* Port 0 Pin 4 */ + EVSYS_GENERATOR_PORT0_PIN5_gc = (0x45<<0), /* Port 0 Pin 5 */ + EVSYS_GENERATOR_PORT0_PIN6_gc = (0x46<<0), /* Port 0 Pin 6 */ + EVSYS_GENERATOR_PORT0_PIN7_gc = (0x47<<0), /* Port 0 Pin 7 */ + EVSYS_GENERATOR_PORT1_PIN0_gc = (0x48<<0), /* Port 1 Pin 0 */ + EVSYS_GENERATOR_PORT1_PIN1_gc = (0x49<<0), /* Port 1 Pin 1 */ + EVSYS_GENERATOR_PORT1_PIN2_gc = (0x4A<<0), /* Port 1 Pin 2 */ + EVSYS_GENERATOR_PORT1_PIN3_gc = (0x4B<<0), /* Port 1 Pin 3 */ + EVSYS_GENERATOR_PORT1_PIN4_gc = (0x4C<<0), /* Port 1 Pin 4 */ + EVSYS_GENERATOR_PORT1_PIN5_gc = (0x4D<<0), /* Port 1 Pin 5 */ + EVSYS_GENERATOR_PORT1_PIN6_gc = (0x4E<<0), /* Port 1 Pin 6 */ + EVSYS_GENERATOR_PORT1_PIN7_gc = (0x4F<<0), /* Port 1 Pin 7 */ + EVSYS_GENERATOR_USART0_XCK_gc = (0x60<<0), /* USART 0 Xclock */ + EVSYS_GENERATOR_USART1_XCK_gc = (0x61<<0), /* USART 1 Xclock */ + EVSYS_GENERATOR_USART2_XCK_gc = (0x62<<0), /* USART 2 Xclock */ + EVSYS_GENERATOR_USART3_XCK_gc = (0x63<<0), /* USART 3 Xclock */ + EVSYS_GENERATOR_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_GENERATOR_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_GENERATOR_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow (split mode) */ + EVSYS_GENERATOR_TCA0_CMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_GENERATOR_TCA0_CMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_GENERATOR_TCA0_CMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_GENERATOR_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_GENERATOR_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_GENERATOR_TCB2_CAPT_gc = (0xA4<<0), /* Timer/Counter B2 capture */ + EVSYS_GENERATOR_TCB3_CAPT_gc = (0xA6<<0), /* Timer/Counter B3 capture */ +} EVSYS_GENERATOR_t; + +/* Software event on channels select */ +typedef enum EVSYS_STROBE0_enum +{ + EVSYS_STROBE0_EV_STROBE_CH0_gc = (0x01<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH1_gc = (0x02<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH2_gc = (0x04<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH3_gc = (0x08<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH4_gc = (0x10<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH5_gc = (0x20<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH6_gc = (0x40<<0), /* */ + EVSYS_STROBE0_EV_STROBE_CH7_gc = (0x80<<0), /* */ +} EVSYS_STROBE0_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<3), /* GPIO mode */ + RSTPINCFG_RST_gc = (0x01<<3), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock Bits */ + register8_t reserved_1[1]; +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t PORTCTRL; /* Port Control */ + register8_t reserved_1[5]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t EVSYSROUTEA; /* Port Multiplexer EVSYS */ + register8_t CCLROUTEA; /* Port Multiplexer CCL */ + register8_t USARTROUTEA; /* Port Multiplexer USART register A */ + register8_t TWISPIROUTEA; /* Port Multiplexer TWI and SPI */ + register8_t TCAROUTEA; /* Port Multiplexer TCA */ + register8_t TCBROUTEA; /* Port Multiplexer TCB */ + register8_t reserved_1[10]; +} PORTMUX_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<0), /* SPI0 on PA[7:4] */ + PORTMUX_SPI0_ALT1_gc = (0x01<<0), /* SPI0 on PC[3:0] */ + PORTMUX_SPI0_ALT2_gc = (0x02<<0), /* SPI0 on PE[3:0] */ + PORTMUX_SPI0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 select */ +typedef enum PORTMUX_TCA0_enum +{ + PORTMUX_TCA0_PORTA_gc = (0x00<<0), /* TCA0 pins on PA[5:0] */ + PORTMUX_TCA0_PORTB_gc = (0x01<<0), /* TCA0 pins on PB[5:0] */ + PORTMUX_TCA0_PORTC_gc = (0x02<<0), /* TCA0 pins on PC[5:0] */ + PORTMUX_TCA0_PORTD_gc = (0x03<<0), /* TCA0 pins on PD[5:0] */ + PORTMUX_TCA0_PORTE_gc = (0x04<<0), /* TCA0 pins on PE[5:0] */ + PORTMUX_TCA0_PORTF_gc = (0x05<<0), /* TCA0 pins on PF[5:0] */ +} PORTMUX_TCA0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* SCL/SDA on PA[3:2], Slave mode on PC[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT1_gc = (0x01<<4), /* SCL/SDA on PA[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT2_gc = (0x02<<4), /* SCL/SDA on PC[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* USART0 on PA[3:0] */ + PORTMUX_USART0_ALT1_gc = (0x01<<0), /* USART0 on PA[7:4] */ + PORTMUX_USART0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_USART0_t; + +/* Port Multiplexer USART1 select */ +typedef enum PORTMUX_USART1_enum +{ + PORTMUX_USART1_DEFAULT_gc = (0x00<<2), /* USART1 on PC[3:0] */ + PORTMUX_USART1_ALT1_gc = (0x01<<2), /* USART1 on PC[7:4] */ + PORTMUX_USART1_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_USART1_t; + +/* Port Multiplexer USART2 select */ +typedef enum PORTMUX_USART2_enum +{ + PORTMUX_USART2_DEFAULT_gc = (0x00<<4), /* USART2 on PF[3:0] */ + PORTMUX_USART2_ALT1_gc = (0x01<<4), /* USART2 on PF[6:4] */ + PORTMUX_USART2_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_USART2_t; + +/* Port Multiplexer USART3 select */ +typedef enum PORTMUX_USART3_enum +{ + PORTMUX_USART3_DEFAULT_gc = (0x00<<6), /* USART3 on PB[3:0] */ + PORTMUX_USART3_ALT1_gc = (0x01<<6), /* USART3 on PB[5:4] */ + PORTMUX_USART3_NONE_gc = (0x03<<6), /* Not connected to any pins */ +} PORTMUX_USART3_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t CALIB; /* Calibration */ + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_1[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_2[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_3[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[7]; + register8_t OSCCAL32K; /* Oscillator Calibration for 32kHz ULP */ + register8_t reserved_2[3]; + register8_t OSCCAL16M0; /* Oscillator Calibration 16 MHz Byte 0 */ + register8_t OSCCAL16M1; /* Oscillator Calibration 16 MHz Byte 1 */ + register8_t OSCCAL20M0; /* Oscillator Calibration 20 MHz Byte 0 */ + register8_t OSCCAL20M1; /* Oscillator Calibration 20 MHz Byte 1 */ + register8_t reserved_3[4]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_4[9]; + register8_t CHECKSUM1; /* CRC Checksum Byte 1 */ + register8_t reserved_5[16]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[21]; + register8_t OCDM; /* OCD Message Register */ + register8_t OCDMS; /* OCD Message Status */ + register8_t reserved_3[6]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t DUALCTRL; /* Dual Control */ + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_1[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t CTRLD; /* Control D */ + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_1[1]; +} USART_t; + +/* Auto Baud Window select */ +typedef enum USART_ABW_enum +{ + USART_ABW_WDW0_gc = (0x00<<6), /* 18% tolerance */ + USART_ABW_WDW1_gc = (0x01<<6), /* 15% tolerance */ + USART_ABW_WDW2_gc = (0x02<<6), /* 21% tolerance */ + USART_ABW_WDW3_gc = (0x03<<6), /* 25% tolerance */ +} USART_ABW_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ + register8_t USERROW32; /* User Row Byte 32 */ + register8_t USERROW33; /* User Row Byte 33 */ + register8_t USERROW34; /* User Row Byte 34 */ + register8_t USERROW35; /* User Row Byte 35 */ + register8_t USERROW36; /* User Row Byte 36 */ + register8_t USERROW37; /* User Row Byte 37 */ + register8_t USERROW38; /* User Row Byte 38 */ + register8_t USERROW39; /* User Row Byte 39 */ + register8_t USERROW40; /* User Row Byte 40 */ + register8_t USERROW41; /* User Row Byte 41 */ + register8_t USERROW42; /* User Row Byte 42 */ + register8_t USERROW43; /* User Row Byte 43 */ + register8_t USERROW44; /* User Row Byte 44 */ + register8_t USERROW45; /* User Row Byte 45 */ + register8_t USERROW46; /* User Row Byte 46 */ + register8_t USERROW47; /* User Row Byte 47 */ + register8_t USERROW48; /* User Row Byte 48 */ + register8_t USERROW49; /* User Row Byte 49 */ + register8_t USERROW50; /* User Row Byte 50 */ + register8_t USERROW51; /* User Row Byte 51 */ + register8_t USERROW52; /* User Row Byte 52 */ + register8_t USERROW53; /* User Row Byte 53 */ + register8_t USERROW54; /* User Row Byte 54 */ + register8_t USERROW55; /* User Row Byte 55 */ + register8_t USERROW56; /* User Row Byte 56 */ + register8_t USERROW57; /* User Row Byte 57 */ + register8_t USERROW58; /* User Row Byte 58 */ + register8_t USERROW59; /* User Row Byte 59 */ + register8_t USERROW60; /* User Row Byte 60 */ + register8_t USERROW61; /* User Row Byte 61 */ + register8_t USERROW62; /* User Row Byte 62 */ + register8_t USERROW63; /* User Row Byte 63 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* AC0 reference select select */ +typedef enum VREF_AC0REFSEL_enum +{ + VREF_AC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_AC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_AC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_AC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_AC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ + VREF_AC0REFSEL_AVDD_gc = (0x07<<0), /* AVDD as Voltage reference */ +} VREF_AC0REFSEL_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define VPORTD (*(VPORT_t *) 0x000C) /* Virtual Ports */ +#define VPORTE (*(VPORT_t *) 0x0010) /* Virtual Ports */ +#define VPORTF (*(VPORT_t *) 0x0014) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0460) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0480) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x04A0) /* I/O Ports */ +#define PORTMUX (*(PORTMUX_t *) 0x05E0) /* Port Multiplexer */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1 (*(USART_t *) 0x0820) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2 (*(USART_t *) 0x0840) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART3 (*(USART_t *) 0x0860) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x08A0) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A80) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0A90) /* 16-bit Timer Type B */ +#define TCB2 (*(TCB_t *) 0x0AA0) /* 16-bit Timer Type B */ +#define TCB3 (*(TCB_t *) 0x0AB0) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* VPORT (VPORTD) - Virtual Ports */ +#define VPORTD_DIR _SFR_MEM8(0x000C) +#define VPORTD_OUT _SFR_MEM8(0x000D) +#define VPORTD_IN _SFR_MEM8(0x000E) +#define VPORTD_INTFLAGS _SFR_MEM8(0x000F) + + +/* VPORT (VPORTE) - Virtual Ports */ +#define VPORTE_DIR _SFR_MEM8(0x0010) +#define VPORTE_OUT _SFR_MEM8(0x0011) +#define VPORTE_IN _SFR_MEM8(0x0012) +#define VPORTE_INTFLAGS _SFR_MEM8(0x0013) + + +/* VPORT (VPORTF) - Virtual Ports */ +#define VPORTF_DIR _SFR_MEM8(0x0014) +#define VPORTF_OUT _SFR_MEM8(0x0015) +#define VPORTF_IN _SFR_MEM8(0x0016) +#define VPORTF_INTFLAGS _SFR_MEM8(0x0017) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CALIB _SFR_MEM8(0x0146) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_STROBE _SFR_MEM8(0x0180) +#define EVSYS_CHANNEL0 _SFR_MEM8(0x0190) +#define EVSYS_CHANNEL1 _SFR_MEM8(0x0191) +#define EVSYS_CHANNEL2 _SFR_MEM8(0x0192) +#define EVSYS_CHANNEL3 _SFR_MEM8(0x0193) +#define EVSYS_CHANNEL4 _SFR_MEM8(0x0194) +#define EVSYS_CHANNEL5 _SFR_MEM8(0x0195) +#define EVSYS_CHANNEL6 _SFR_MEM8(0x0196) +#define EVSYS_CHANNEL7 _SFR_MEM8(0x0197) +#define EVSYS_USERCCLLUT0A _SFR_MEM8(0x01A0) +#define EVSYS_USERCCLLUT0B _SFR_MEM8(0x01A1) +#define EVSYS_USERCCLLUT1A _SFR_MEM8(0x01A2) +#define EVSYS_USERCCLLUT1B _SFR_MEM8(0x01A3) +#define EVSYS_USERCCLLUT2A _SFR_MEM8(0x01A4) +#define EVSYS_USERCCLLUT2B _SFR_MEM8(0x01A5) +#define EVSYS_USERCCLLUT3A _SFR_MEM8(0x01A6) +#define EVSYS_USERCCLLUT3B _SFR_MEM8(0x01A7) +#define EVSYS_USERADC0 _SFR_MEM8(0x01A8) +#define EVSYS_USEREVOUTA _SFR_MEM8(0x01A9) +#define EVSYS_USEREVOUTB _SFR_MEM8(0x01AA) +#define EVSYS_USEREVOUTC _SFR_MEM8(0x01AB) +#define EVSYS_USEREVOUTD _SFR_MEM8(0x01AC) +#define EVSYS_USEREVOUTE _SFR_MEM8(0x01AD) +#define EVSYS_USEREVOUTF _SFR_MEM8(0x01AE) +#define EVSYS_USERUSART0 _SFR_MEM8(0x01AF) +#define EVSYS_USERUSART1 _SFR_MEM8(0x01B0) +#define EVSYS_USERUSART2 _SFR_MEM8(0x01B1) +#define EVSYS_USERUSART3 _SFR_MEM8(0x01B2) +#define EVSYS_USERTCA0 _SFR_MEM8(0x01B3) +#define EVSYS_USERTCB0 _SFR_MEM8(0x01B4) +#define EVSYS_USERTCB1 _SFR_MEM8(0x01B5) +#define EVSYS_USERTCB2 _SFR_MEM8(0x01B6) +#define EVSYS_USERTCB3 _SFR_MEM8(0x01B7) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_SEQCTRL1 _SFR_MEM8(0x01C2) +#define CCL_INTCTRL0 _SFR_MEM8(0x01C5) +#define CCL_INTFLAGS _SFR_MEM8(0x01C7) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C8) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C9) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01CA) +#define CCL_TRUTH0 _SFR_MEM8(0x01CB) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01CC) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CD) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CE) +#define CCL_TRUTH1 _SFR_MEM8(0x01CF) +#define CCL_LUT2CTRLA _SFR_MEM8(0x01D0) +#define CCL_LUT2CTRLB _SFR_MEM8(0x01D1) +#define CCL_LUT2CTRLC _SFR_MEM8(0x01D2) +#define CCL_TRUTH2 _SFR_MEM8(0x01D3) +#define CCL_LUT3CTRLA _SFR_MEM8(0x01D4) +#define CCL_LUT3CTRLB _SFR_MEM8(0x01D5) +#define CCL_LUT3CTRLC _SFR_MEM8(0x01D6) +#define CCL_TRUTH3 _SFR_MEM8(0x01D7) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PORTCTRL _SFR_MEM8(0x040A) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PORTCTRL _SFR_MEM8(0x042A) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PORTCTRL _SFR_MEM8(0x044A) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* PORT (PORTD) - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0460) +#define PORTD_DIRSET _SFR_MEM8(0x0461) +#define PORTD_DIRCLR _SFR_MEM8(0x0462) +#define PORTD_DIRTGL _SFR_MEM8(0x0463) +#define PORTD_OUT _SFR_MEM8(0x0464) +#define PORTD_OUTSET _SFR_MEM8(0x0465) +#define PORTD_OUTCLR _SFR_MEM8(0x0466) +#define PORTD_OUTTGL _SFR_MEM8(0x0467) +#define PORTD_IN _SFR_MEM8(0x0468) +#define PORTD_INTFLAGS _SFR_MEM8(0x0469) +#define PORTD_PORTCTRL _SFR_MEM8(0x046A) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0470) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0471) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0472) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0473) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0474) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0475) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0476) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0477) + + +/* PORT (PORTE) - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0480) +#define PORTE_DIRSET _SFR_MEM8(0x0481) +#define PORTE_DIRCLR _SFR_MEM8(0x0482) +#define PORTE_DIRTGL _SFR_MEM8(0x0483) +#define PORTE_OUT _SFR_MEM8(0x0484) +#define PORTE_OUTSET _SFR_MEM8(0x0485) +#define PORTE_OUTCLR _SFR_MEM8(0x0486) +#define PORTE_OUTTGL _SFR_MEM8(0x0487) +#define PORTE_IN _SFR_MEM8(0x0488) +#define PORTE_INTFLAGS _SFR_MEM8(0x0489) +#define PORTE_PORTCTRL _SFR_MEM8(0x048A) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0490) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0491) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0492) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0493) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0494) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0495) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0496) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0497) + + +/* PORT (PORTF) - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x04A0) +#define PORTF_DIRSET _SFR_MEM8(0x04A1) +#define PORTF_DIRCLR _SFR_MEM8(0x04A2) +#define PORTF_DIRTGL _SFR_MEM8(0x04A3) +#define PORTF_OUT _SFR_MEM8(0x04A4) +#define PORTF_OUTSET _SFR_MEM8(0x04A5) +#define PORTF_OUTCLR _SFR_MEM8(0x04A6) +#define PORTF_OUTTGL _SFR_MEM8(0x04A7) +#define PORTF_IN _SFR_MEM8(0x04A8) +#define PORTF_INTFLAGS _SFR_MEM8(0x04A9) +#define PORTF_PORTCTRL _SFR_MEM8(0x04AA) +#define PORTF_PIN0CTRL _SFR_MEM8(0x04B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x04B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x04B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x04B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x04B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x04B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x04B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x04B7) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_EVSYSROUTEA _SFR_MEM8(0x05E0) +#define PORTMUX_CCLROUTEA _SFR_MEM8(0x05E1) +#define PORTMUX_USARTROUTEA _SFR_MEM8(0x05E2) +#define PORTMUX_TWISPIROUTEA _SFR_MEM8(0x05E3) +#define PORTMUX_TCAROUTEA _SFR_MEM8(0x05E4) +#define PORTMUX_TCBROUTEA _SFR_MEM8(0x05E5) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_DACREF _SFR_MEM8(0x0684) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_CTRLD _SFR_MEM8(0x080A) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* USART (USART1) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1_RXDATAL _SFR_MEM8(0x0820) +#define USART1_RXDATAH _SFR_MEM8(0x0821) +#define USART1_TXDATAL _SFR_MEM8(0x0822) +#define USART1_TXDATAH _SFR_MEM8(0x0823) +#define USART1_STATUS _SFR_MEM8(0x0824) +#define USART1_CTRLA _SFR_MEM8(0x0825) +#define USART1_CTRLB _SFR_MEM8(0x0826) +#define USART1_CTRLC _SFR_MEM8(0x0827) +#define USART1_BAUD _SFR_MEM16(0x0828) +#define USART1_BAUDL _SFR_MEM8(0x0828) +#define USART1_BAUDH _SFR_MEM8(0x0829) +#define USART1_CTRLD _SFR_MEM8(0x082A) +#define USART1_DBGCTRL _SFR_MEM8(0x082B) +#define USART1_EVCTRL _SFR_MEM8(0x082C) +#define USART1_TXPLCTRL _SFR_MEM8(0x082D) +#define USART1_RXPLCTRL _SFR_MEM8(0x082E) + + +/* USART (USART2) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART2_RXDATAL _SFR_MEM8(0x0840) +#define USART2_RXDATAH _SFR_MEM8(0x0841) +#define USART2_TXDATAL _SFR_MEM8(0x0842) +#define USART2_TXDATAH _SFR_MEM8(0x0843) +#define USART2_STATUS _SFR_MEM8(0x0844) +#define USART2_CTRLA _SFR_MEM8(0x0845) +#define USART2_CTRLB _SFR_MEM8(0x0846) +#define USART2_CTRLC _SFR_MEM8(0x0847) +#define USART2_BAUD _SFR_MEM16(0x0848) +#define USART2_BAUDL _SFR_MEM8(0x0848) +#define USART2_BAUDH _SFR_MEM8(0x0849) +#define USART2_CTRLD _SFR_MEM8(0x084A) +#define USART2_DBGCTRL _SFR_MEM8(0x084B) +#define USART2_EVCTRL _SFR_MEM8(0x084C) +#define USART2_TXPLCTRL _SFR_MEM8(0x084D) +#define USART2_RXPLCTRL _SFR_MEM8(0x084E) + + +/* USART (USART3) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART3_RXDATAL _SFR_MEM8(0x0860) +#define USART3_RXDATAH _SFR_MEM8(0x0861) +#define USART3_TXDATAL _SFR_MEM8(0x0862) +#define USART3_TXDATAH _SFR_MEM8(0x0863) +#define USART3_STATUS _SFR_MEM8(0x0864) +#define USART3_CTRLA _SFR_MEM8(0x0865) +#define USART3_CTRLB _SFR_MEM8(0x0866) +#define USART3_CTRLC _SFR_MEM8(0x0867) +#define USART3_BAUD _SFR_MEM16(0x0868) +#define USART3_BAUDL _SFR_MEM8(0x0868) +#define USART3_BAUDH _SFR_MEM8(0x0869) +#define USART3_CTRLD _SFR_MEM8(0x086A) +#define USART3_DBGCTRL _SFR_MEM8(0x086B) +#define USART3_EVCTRL _SFR_MEM8(0x086C) +#define USART3_TXPLCTRL _SFR_MEM8(0x086D) +#define USART3_RXPLCTRL _SFR_MEM8(0x086E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x08A0) +#define TWI0_DUALCTRL _SFR_MEM8(0x08A1) +#define TWI0_DBGCTRL _SFR_MEM8(0x08A2) +#define TWI0_MCTRLA _SFR_MEM8(0x08A3) +#define TWI0_MCTRLB _SFR_MEM8(0x08A4) +#define TWI0_MSTATUS _SFR_MEM8(0x08A5) +#define TWI0_MBAUD _SFR_MEM8(0x08A6) +#define TWI0_MADDR _SFR_MEM8(0x08A7) +#define TWI0_MDATA _SFR_MEM8(0x08A8) +#define TWI0_SCTRLA _SFR_MEM8(0x08A9) +#define TWI0_SCTRLB _SFR_MEM8(0x08AA) +#define TWI0_SSTATUS _SFR_MEM8(0x08AB) +#define TWI0_SADDR _SFR_MEM8(0x08AC) +#define TWI0_SDATA _SFR_MEM8(0x08AD) +#define TWI0_SADDRMASK _SFR_MEM8(0x08AE) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x08C0) +#define SPI0_CTRLB _SFR_MEM8(0x08C1) +#define SPI0_INTCTRL _SFR_MEM8(0x08C2) +#define SPI0_INTFLAGS _SFR_MEM8(0x08C3) +#define SPI0_DATA _SFR_MEM8(0x08C4) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A80) +#define TCB0_CTRLB _SFR_MEM8(0x0A81) +#define TCB0_EVCTRL _SFR_MEM8(0x0A84) +#define TCB0_INTCTRL _SFR_MEM8(0x0A85) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A86) +#define TCB0_STATUS _SFR_MEM8(0x0A87) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A88) +#define TCB0_TEMP _SFR_MEM8(0x0A89) +#define TCB0_CNT _SFR_MEM16(0x0A8A) +#define TCB0_CNTL _SFR_MEM8(0x0A8A) +#define TCB0_CNTH _SFR_MEM8(0x0A8B) +#define TCB0_CCMP _SFR_MEM16(0x0A8C) +#define TCB0_CCMPL _SFR_MEM8(0x0A8C) +#define TCB0_CCMPH _SFR_MEM8(0x0A8D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0A90) +#define TCB1_CTRLB _SFR_MEM8(0x0A91) +#define TCB1_EVCTRL _SFR_MEM8(0x0A94) +#define TCB1_INTCTRL _SFR_MEM8(0x0A95) +#define TCB1_INTFLAGS _SFR_MEM8(0x0A96) +#define TCB1_STATUS _SFR_MEM8(0x0A97) +#define TCB1_DBGCTRL _SFR_MEM8(0x0A98) +#define TCB1_TEMP _SFR_MEM8(0x0A99) +#define TCB1_CNT _SFR_MEM16(0x0A9A) +#define TCB1_CNTL _SFR_MEM8(0x0A9A) +#define TCB1_CNTH _SFR_MEM8(0x0A9B) +#define TCB1_CCMP _SFR_MEM16(0x0A9C) +#define TCB1_CCMPL _SFR_MEM8(0x0A9C) +#define TCB1_CCMPH _SFR_MEM8(0x0A9D) + + +/* TCB (TCB2) - 16-bit Timer Type B */ +#define TCB2_CTRLA _SFR_MEM8(0x0AA0) +#define TCB2_CTRLB _SFR_MEM8(0x0AA1) +#define TCB2_EVCTRL _SFR_MEM8(0x0AA4) +#define TCB2_INTCTRL _SFR_MEM8(0x0AA5) +#define TCB2_INTFLAGS _SFR_MEM8(0x0AA6) +#define TCB2_STATUS _SFR_MEM8(0x0AA7) +#define TCB2_DBGCTRL _SFR_MEM8(0x0AA8) +#define TCB2_TEMP _SFR_MEM8(0x0AA9) +#define TCB2_CNT _SFR_MEM16(0x0AAA) +#define TCB2_CNTL _SFR_MEM8(0x0AAA) +#define TCB2_CNTH _SFR_MEM8(0x0AAB) +#define TCB2_CCMP _SFR_MEM16(0x0AAC) +#define TCB2_CCMPL _SFR_MEM8(0x0AAC) +#define TCB2_CCMPH _SFR_MEM8(0x0AAD) + + +/* TCB (TCB3) - 16-bit Timer Type B */ +#define TCB3_CTRLA _SFR_MEM8(0x0AB0) +#define TCB3_CTRLB _SFR_MEM8(0x0AB1) +#define TCB3_EVCTRL _SFR_MEM8(0x0AB4) +#define TCB3_INTCTRL _SFR_MEM8(0x0AB5) +#define TCB3_INTFLAGS _SFR_MEM8(0x0AB6) +#define TCB3_STATUS _SFR_MEM8(0x0AB7) +#define TCB3_DBGCTRL _SFR_MEM8(0x0AB8) +#define TCB3_TEMP _SFR_MEM8(0x0AB9) +#define TCB3_CNT _SFR_MEM16(0x0ABA) +#define TCB3_CNTL _SFR_MEM8(0x0ABA) +#define TCB3_CNTH _SFR_MEM8(0x0ABB) +#define TCB3_CCMP _SFR_MEM16(0x0ABC) +#define TCB3_CCMPL _SFR_MEM8(0x0ABC) +#define TCB3_CCMPH _SFR_MEM8(0x0ABD) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) +#define SYSCFG_OCDM _SFR_MEM8(0x0F18) +#define SYSCFG_OCDMS _SFR_MEM8(0x0F19) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_OSCCAL32K _SFR_MEM8(0x1114) +#define SIGROW_OSCCAL16M0 _SFR_MEM8(0x1118) +#define SIGROW_OSCCAL16M1 _SFR_MEM8(0x1119) +#define SIGROW_OSCCAL20M0 _SFR_MEM8(0x111A) +#define SIGROW_OSCCAL20M1 _SFR_MEM8(0x111B) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) +#define SIGROW_CHECKSUM1 _SFR_MEM8(0x112F) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) +#define USERROW_USERROW32 _SFR_MEM8(0x1320) +#define USERROW_USERROW33 _SFR_MEM8(0x1321) +#define USERROW_USERROW34 _SFR_MEM8(0x1322) +#define USERROW_USERROW35 _SFR_MEM8(0x1323) +#define USERROW_USERROW36 _SFR_MEM8(0x1324) +#define USERROW_USERROW37 _SFR_MEM8(0x1325) +#define USERROW_USERROW38 _SFR_MEM8(0x1326) +#define USERROW_USERROW39 _SFR_MEM8(0x1327) +#define USERROW_USERROW40 _SFR_MEM8(0x1328) +#define USERROW_USERROW41 _SFR_MEM8(0x1329) +#define USERROW_USERROW42 _SFR_MEM8(0x132A) +#define USERROW_USERROW43 _SFR_MEM8(0x132B) +#define USERROW_USERROW44 _SFR_MEM8(0x132C) +#define USERROW_USERROW45 _SFR_MEM8(0x132D) +#define USERROW_USERROW46 _SFR_MEM8(0x132E) +#define USERROW_USERROW47 _SFR_MEM8(0x132F) +#define USERROW_USERROW48 _SFR_MEM8(0x1330) +#define USERROW_USERROW49 _SFR_MEM8(0x1331) +#define USERROW_USERROW50 _SFR_MEM8(0x1332) +#define USERROW_USERROW51 _SFR_MEM8(0x1333) +#define USERROW_USERROW52 _SFR_MEM8(0x1334) +#define USERROW_USERROW53 _SFR_MEM8(0x1335) +#define USERROW_USERROW54 _SFR_MEM8(0x1336) +#define USERROW_USERROW55 _SFR_MEM8(0x1337) +#define USERROW_USERROW56 _SFR_MEM8(0x1338) +#define USERROW_USERROW57 _SFR_MEM8(0x1339) +#define USERROW_USERROW58 _SFR_MEM8(0x133A) +#define USERROW_USERROW59 _SFR_MEM8(0x133B) +#define USERROW_USERROW60 _SFR_MEM8(0x133C) +#define USERROW_USERROW61 _SFR_MEM8(0x133D) +#define USERROW_USERROW62 _SFR_MEM8(0x133E) +#define USERROW_USERROW63 _SFR_MEM8(0x133F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.DACREF bit masks and bit positions */ +#define AC_DATA_gm 0xFF /* DAC voltage reference group mask. */ +#define AC_DATA_gp 0 /* DAC voltage reference group position. */ +#define AC_DATA0_bm (1<<0) /* DAC voltage reference bit 0 mask. */ +#define AC_DATA0_bp 0 /* DAC voltage reference bit 0 position. */ +#define AC_DATA1_bm (1<<1) /* DAC voltage reference bit 1 mask. */ +#define AC_DATA1_bp 1 /* DAC voltage reference bit 1 position. */ +#define AC_DATA2_bm (1<<2) /* DAC voltage reference bit 2 mask. */ +#define AC_DATA2_bp 2 /* DAC voltage reference bit 2 position. */ +#define AC_DATA3_bm (1<<3) /* DAC voltage reference bit 3 mask. */ +#define AC_DATA3_bp 3 /* DAC voltage reference bit 3 position. */ +#define AC_DATA4_bm (1<<4) /* DAC voltage reference bit 4 mask. */ +#define AC_DATA4_bp 4 /* DAC voltage reference bit 4 position. */ +#define AC_DATA5_bm (1<<5) /* DAC voltage reference bit 5 mask. */ +#define AC_DATA5_bp 5 /* DAC voltage reference bit 5 position. */ +#define AC_DATA6_bm (1<<6) /* DAC voltage reference bit 6 mask. */ +#define AC_DATA6_bp 6 /* DAC voltage reference bit 6 position. */ +#define AC_DATA7_bm (1<<7) /* DAC voltage reference bit 7 mask. */ +#define AC_DATA7_bp 7 /* DAC voltage reference bit 7 position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL0_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL0_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL00_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL00_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL01_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL01_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL02_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL02_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.SEQCTRL1 bit masks and bit positions */ +#define CCL_SEQSEL1_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL1_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL10_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL10_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL11_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL11_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL12_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL12_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.INTCTRL0 bit masks and bit positions */ +#define CCL_INTMODE0_gm 0x03 /* Interrupt Mode for LUT0 group mask. */ +#define CCL_INTMODE0_gp 0 /* Interrupt Mode for LUT0 group position. */ +#define CCL_INTMODE00_bm (1<<0) /* Interrupt Mode for LUT0 bit 0 mask. */ +#define CCL_INTMODE00_bp 0 /* Interrupt Mode for LUT0 bit 0 position. */ +#define CCL_INTMODE01_bm (1<<1) /* Interrupt Mode for LUT0 bit 1 mask. */ +#define CCL_INTMODE01_bp 1 /* Interrupt Mode for LUT0 bit 1 position. */ +#define CCL_INTMODE1_gm 0x0C /* Interrupt Mode for LUT1 group mask. */ +#define CCL_INTMODE1_gp 2 /* Interrupt Mode for LUT1 group position. */ +#define CCL_INTMODE10_bm (1<<2) /* Interrupt Mode for LUT1 bit 0 mask. */ +#define CCL_INTMODE10_bp 2 /* Interrupt Mode for LUT1 bit 0 position. */ +#define CCL_INTMODE11_bm (1<<3) /* Interrupt Mode for LUT1 bit 1 mask. */ +#define CCL_INTMODE11_bp 3 /* Interrupt Mode for LUT1 bit 1 position. */ +#define CCL_INTMODE2_gm 0x30 /* Interrupt Mode for LUT2 group mask. */ +#define CCL_INTMODE2_gp 4 /* Interrupt Mode for LUT2 group position. */ +#define CCL_INTMODE20_bm (1<<4) /* Interrupt Mode for LUT2 bit 0 mask. */ +#define CCL_INTMODE20_bp 4 /* Interrupt Mode for LUT2 bit 0 position. */ +#define CCL_INTMODE21_bm (1<<5) /* Interrupt Mode for LUT2 bit 1 mask. */ +#define CCL_INTMODE21_bp 5 /* Interrupt Mode for LUT2 bit 1 position. */ +#define CCL_INTMODE3_gm 0xC0 /* Interrupt Mode for LUT3 group mask. */ +#define CCL_INTMODE3_gp 6 /* Interrupt Mode for LUT3 group position. */ +#define CCL_INTMODE30_bm (1<<6) /* Interrupt Mode for LUT3 bit 0 mask. */ +#define CCL_INTMODE30_bp 6 /* Interrupt Mode for LUT3 bit 0 position. */ +#define CCL_INTMODE31_bm (1<<7) /* Interrupt Mode for LUT3 bit 1 mask. */ +#define CCL_INTMODE31_bp 7 /* Interrupt Mode for LUT3 bit 1 position. */ + +/* CCL.INTFLAGS bit masks and bit positions */ +#define CCL_INT_gm 0x0F /* Interrupt Flags group mask. */ +#define CCL_INT_gp 0 /* Interrupt Flags group position. */ +#define CCL_INT0_bm (1<<0) /* Interrupt Flags bit 0 mask. */ +#define CCL_INT0_bp 0 /* Interrupt Flags bit 0 position. */ +#define CCL_INT1_bm (1<<1) /* Interrupt Flags bit 1 mask. */ +#define CCL_INT1_bp 1 /* Interrupt Flags bit 1 position. */ +#define CCL_INT2_bm (1<<2) /* Interrupt Flags bit 2 mask. */ +#define CCL_INT2_bp 2 /* Interrupt Flags bit 2 position. */ +#define CCL_INT3_bm (1<<3) /* Interrupt Flags bit 3 mask. */ +#define CCL_INT3_bp 3 /* Interrupt Flags bit 3 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_CLKSRC_gm 0x0E /* Clock Source Selection group mask. */ +#define CCL_CLKSRC_gp 1 /* Clock Source Selection group position. */ +#define CCL_CLKSRC0_bm (1<<1) /* Clock Source Selection bit 0 mask. */ +#define CCL_CLKSRC0_bp 1 /* Clock Source Selection bit 0 position. */ +#define CCL_CLKSRC1_bm (1<<2) /* Clock Source Selection bit 1 mask. */ +#define CCL_CLKSRC1_bp 2 /* Clock Source Selection bit 1 position. */ +#define CCL_CLKSRC2_bm (1<<3) /* Clock Source Selection bit 2 mask. */ +#define CCL_CLKSRC2_bp 3 /* Clock Source Selection bit 2 position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_OUTEN_bm 0x40 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 6 /* Output Enable bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT2CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT2CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT2CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT3CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT3CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT3CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x7F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ +#define CLKCTRL_CAL20M6_bm (1<<6) /* Calibration bit 6 mask. */ +#define CLKCTRL_CAL20M6_bp 6 /* Calibration bit 6 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.STROBE bit masks and bit positions */ +#define EVSYS_STROBE0_gm 0xFF /* Software event on channels group mask. */ +#define EVSYS_STROBE0_gp 0 /* Software event on channels group position. */ +#define EVSYS_STROBE00_bm (1<<0) /* Software event on channels bit 0 mask. */ +#define EVSYS_STROBE00_bp 0 /* Software event on channels bit 0 position. */ +#define EVSYS_STROBE01_bm (1<<1) /* Software event on channels bit 1 mask. */ +#define EVSYS_STROBE01_bp 1 /* Software event on channels bit 1 position. */ +#define EVSYS_STROBE02_bm (1<<2) /* Software event on channels bit 2 mask. */ +#define EVSYS_STROBE02_bp 2 /* Software event on channels bit 2 position. */ +#define EVSYS_STROBE03_bm (1<<3) /* Software event on channels bit 3 mask. */ +#define EVSYS_STROBE03_bp 3 /* Software event on channels bit 3 position. */ +#define EVSYS_STROBE04_bm (1<<4) /* Software event on channels bit 4 mask. */ +#define EVSYS_STROBE04_bp 4 /* Software event on channels bit 4 position. */ +#define EVSYS_STROBE05_bm (1<<5) /* Software event on channels bit 5 mask. */ +#define EVSYS_STROBE05_bp 5 /* Software event on channels bit 5 position. */ +#define EVSYS_STROBE06_bm (1<<6) /* Software event on channels bit 6 mask. */ +#define EVSYS_STROBE06_bp 6 /* Software event on channels bit 6 position. */ +#define EVSYS_STROBE07_bm (1<<7) /* Software event on channels bit 7 mask. */ +#define EVSYS_STROBE07_bp 7 /* Software event on channels bit 7 position. */ + +/* EVSYS.CHANNEL0 bit masks and bit positions */ +#define EVSYS_GENERATOR_gm 0xFF /* Generator selector group mask. */ +#define EVSYS_GENERATOR_gp 0 /* Generator selector group position. */ +#define EVSYS_GENERATOR0_bm (1<<0) /* Generator selector bit 0 mask. */ +#define EVSYS_GENERATOR0_bp 0 /* Generator selector bit 0 position. */ +#define EVSYS_GENERATOR1_bm (1<<1) /* Generator selector bit 1 mask. */ +#define EVSYS_GENERATOR1_bp 1 /* Generator selector bit 1 position. */ +#define EVSYS_GENERATOR2_bm (1<<2) /* Generator selector bit 2 mask. */ +#define EVSYS_GENERATOR2_bp 2 /* Generator selector bit 2 position. */ +#define EVSYS_GENERATOR3_bm (1<<3) /* Generator selector bit 3 mask. */ +#define EVSYS_GENERATOR3_bp 3 /* Generator selector bit 3 position. */ +#define EVSYS_GENERATOR4_bm (1<<4) /* Generator selector bit 4 mask. */ +#define EVSYS_GENERATOR4_bp 4 /* Generator selector bit 4 position. */ +#define EVSYS_GENERATOR5_bm (1<<5) /* Generator selector bit 5 mask. */ +#define EVSYS_GENERATOR5_bp 5 /* Generator selector bit 5 position. */ +#define EVSYS_GENERATOR6_bm (1<<6) /* Generator selector bit 6 mask. */ +#define EVSYS_GENERATOR6_bp 6 /* Generator selector bit 6 position. */ +#define EVSYS_GENERATOR7_bm (1<<7) /* Generator selector bit 7 mask. */ +#define EVSYS_GENERATOR7_bp 7 /* Generator selector bit 7 position. */ + +/* EVSYS.CHANNEL1 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL2 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL3 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL4 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL5 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL6 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.CHANNEL7 bit masks and bit positions */ +/* EVSYS_GENERATOR is already defined. */ + +/* EVSYS.USERCCLLUT0A bit masks and bit positions */ +#define EVSYS_CHANNEL_gm 0xFF /* Channel selector group mask. */ +#define EVSYS_CHANNEL_gp 0 /* Channel selector group position. */ +#define EVSYS_CHANNEL0_bm (1<<0) /* Channel selector bit 0 mask. */ +#define EVSYS_CHANNEL0_bp 0 /* Channel selector bit 0 position. */ +#define EVSYS_CHANNEL1_bm (1<<1) /* Channel selector bit 1 mask. */ +#define EVSYS_CHANNEL1_bp 1 /* Channel selector bit 1 position. */ +#define EVSYS_CHANNEL2_bm (1<<2) /* Channel selector bit 2 mask. */ +#define EVSYS_CHANNEL2_bp 2 /* Channel selector bit 2 position. */ +#define EVSYS_CHANNEL3_bm (1<<3) /* Channel selector bit 3 mask. */ +#define EVSYS_CHANNEL3_bp 3 /* Channel selector bit 3 position. */ +#define EVSYS_CHANNEL4_bm (1<<4) /* Channel selector bit 4 mask. */ +#define EVSYS_CHANNEL4_bp 4 /* Channel selector bit 4 position. */ +#define EVSYS_CHANNEL5_bm (1<<5) /* Channel selector bit 5 mask. */ +#define EVSYS_CHANNEL5_bp 5 /* Channel selector bit 5 position. */ +#define EVSYS_CHANNEL6_bm (1<<6) /* Channel selector bit 6 mask. */ +#define EVSYS_CHANNEL6_bp 6 /* Channel selector bit 6 position. */ +#define EVSYS_CHANNEL7_bm (1<<7) /* Channel selector bit 7 mask. */ +#define EVSYS_CHANNEL7_bp 7 /* Channel selector bit 7 position. */ + +/* EVSYS.USERCCLLUT0B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT1A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT1B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT2A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT2B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT3A bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERCCLLUT3B bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERADC0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTA bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTB bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTC bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTD bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTE bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USEREVOUTF bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART1 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART2 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERUSART3 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCA0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB0 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB1 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB2 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* EVSYS.USERTCB3 bit masks and bit positions */ +/* EVSYS_CHANNEL is already defined. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_bm 0x08 /* Reset Pin Configuration bit mask. */ +#define FUSE_RSTPINCFG_bp 3 /* Reset Pin Configuration bit position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PORTCTRL bit masks and bit positions */ +#define PORT_SRL_bm 0x01 /* Slew Rate Limit Enable bit mask. */ +#define PORT_SRL_bp 0 /* Slew Rate Limit Enable bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.EVSYSROUTEA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_EVOUT3_bm 0x08 /* Event Output 3 bit mask. */ +#define PORTMUX_EVOUT3_bp 3 /* Event Output 3 bit position. */ +#define PORTMUX_EVOUT4_bm 0x10 /* Event Output 4 bit mask. */ +#define PORTMUX_EVOUT4_bp 4 /* Event Output 4 bit position. */ +#define PORTMUX_EVOUT5_bm 0x20 /* Event Output 5 bit mask. */ +#define PORTMUX_EVOUT5_bp 5 /* Event Output 5 bit position. */ + +/* PORTMUX.CCLROUTEA bit masks and bit positions */ +#define PORTMUX_LUT0_bm 0x01 /* CCL LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 0 /* CCL LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x02 /* CCL LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 1 /* CCL LUT1 bit position. */ +#define PORTMUX_LUT2_bm 0x04 /* CCL LUT2 bit mask. */ +#define PORTMUX_LUT2_bp 2 /* CCL LUT2 bit position. */ +#define PORTMUX_LUT3_bm 0x08 /* CCL LUT3 bit mask. */ +#define PORTMUX_LUT3_bp 3 /* CCL LUT3 bit position. */ + +/* PORTMUX.USARTROUTEA bit masks and bit positions */ +#define PORTMUX_USART0_gm 0x03 /* Port Multiplexer USART0 group mask. */ +#define PORTMUX_USART0_gp 0 /* Port Multiplexer USART0 group position. */ +#define PORTMUX_USART00_bm (1<<0) /* Port Multiplexer USART0 bit 0 mask. */ +#define PORTMUX_USART00_bp 0 /* Port Multiplexer USART0 bit 0 position. */ +#define PORTMUX_USART01_bm (1<<1) /* Port Multiplexer USART0 bit 1 mask. */ +#define PORTMUX_USART01_bp 1 /* Port Multiplexer USART0 bit 1 position. */ +#define PORTMUX_USART1_gm 0x0C /* Port Multiplexer USART1 group mask. */ +#define PORTMUX_USART1_gp 2 /* Port Multiplexer USART1 group position. */ +#define PORTMUX_USART10_bm (1<<2) /* Port Multiplexer USART1 bit 0 mask. */ +#define PORTMUX_USART10_bp 2 /* Port Multiplexer USART1 bit 0 position. */ +#define PORTMUX_USART11_bm (1<<3) /* Port Multiplexer USART1 bit 1 mask. */ +#define PORTMUX_USART11_bp 3 /* Port Multiplexer USART1 bit 1 position. */ +#define PORTMUX_USART2_gm 0x30 /* Port Multiplexer USART2 group mask. */ +#define PORTMUX_USART2_gp 4 /* Port Multiplexer USART2 group position. */ +#define PORTMUX_USART20_bm (1<<4) /* Port Multiplexer USART2 bit 0 mask. */ +#define PORTMUX_USART20_bp 4 /* Port Multiplexer USART2 bit 0 position. */ +#define PORTMUX_USART21_bm (1<<5) /* Port Multiplexer USART2 bit 1 mask. */ +#define PORTMUX_USART21_bp 5 /* Port Multiplexer USART2 bit 1 position. */ +#define PORTMUX_USART3_gm 0xC0 /* Port Multiplexer USART3 group mask. */ +#define PORTMUX_USART3_gp 6 /* Port Multiplexer USART3 group position. */ +#define PORTMUX_USART30_bm (1<<6) /* Port Multiplexer USART3 bit 0 mask. */ +#define PORTMUX_USART30_bp 6 /* Port Multiplexer USART3 bit 0 position. */ +#define PORTMUX_USART31_bm (1<<7) /* Port Multiplexer USART3 bit 1 mask. */ +#define PORTMUX_USART31_bp 7 /* Port Multiplexer USART3 bit 1 position. */ + +/* PORTMUX.TWISPIROUTEA bit masks and bit positions */ +#define PORTMUX_SPI0_gm 0x03 /* Port Multiplexer SPI0 group mask. */ +#define PORTMUX_SPI0_gp 0 /* Port Multiplexer SPI0 group position. */ +#define PORTMUX_SPI00_bm (1<<0) /* Port Multiplexer SPI0 bit 0 mask. */ +#define PORTMUX_SPI00_bp 0 /* Port Multiplexer SPI0 bit 0 position. */ +#define PORTMUX_SPI01_bm (1<<1) /* Port Multiplexer SPI0 bit 1 mask. */ +#define PORTMUX_SPI01_bp 1 /* Port Multiplexer SPI0 bit 1 position. */ +#define PORTMUX_TWI0_gm 0x30 /* Port Multiplexer TWI0 group mask. */ +#define PORTMUX_TWI0_gp 4 /* Port Multiplexer TWI0 group position. */ +#define PORTMUX_TWI00_bm (1<<4) /* Port Multiplexer TWI0 bit 0 mask. */ +#define PORTMUX_TWI00_bp 4 /* Port Multiplexer TWI0 bit 0 position. */ +#define PORTMUX_TWI01_bm (1<<5) /* Port Multiplexer TWI0 bit 1 mask. */ +#define PORTMUX_TWI01_bp 5 /* Port Multiplexer TWI0 bit 1 position. */ + +/* PORTMUX.TCAROUTEA bit masks and bit positions */ +#define PORTMUX_TCA0_gm 0x07 /* Port Multiplexer TCA0 group mask. */ +#define PORTMUX_TCA0_gp 0 /* Port Multiplexer TCA0 group position. */ +#define PORTMUX_TCA00_bm (1<<0) /* Port Multiplexer TCA0 bit 0 mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 bit 0 position. */ +#define PORTMUX_TCA01_bm (1<<1) /* Port Multiplexer TCA0 bit 1 mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 bit 1 position. */ +#define PORTMUX_TCA02_bm (1<<2) /* Port Multiplexer TCA0 bit 2 mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 bit 2 position. */ + +/* PORTMUX.TCBROUTEA bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ +#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ +#define PORTMUX_TCB2_bm 0x04 /* Port Multiplexer TCB2 bit mask. */ +#define PORTMUX_TCB2_bp 2 /* Port Multiplexer TCB2 bit position. */ +#define PORTMUX_TCB3_bm 0x08 /* Port Multiplexer TCB3 bit mask. */ +#define PORTMUX_TCB3_bp 3 /* Port Multiplexer TCB3 bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_CORREN_bm 0x04 /* Correction enable bit mask. */ +#define RTC_CORREN_bp 2 /* Correction enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_ERROR_gm 0x7F /* Error Correction Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Correction Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Correction Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Correction Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Correction Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Correction Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Correction Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Correction Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Correction Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Correction Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Correction Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Correction Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Correction Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Correction Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Correction Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Correction Value bit 6 position. */ +#define RTC_SIGN_bm 0x80 /* Error Correction Sign Bit bit mask. */ +#define RTC_SIGN_bp 7 /* Error Correction Sign Bit bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + + +/* SYSCFG.OCDMS bit masks and bit positions */ +#define SYSCFG_OCDMR_bm 0x01 /* OCD Message Read bit mask. */ +#define SYSCFG_OCDMR_bp 0 /* OCD Message Read bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DUALCTRL bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Dual Control Enable bit mask. */ +#define TWI_ENABLE_bp 0 /* Dual Control Enable bit position. */ +/* TWI_FMPEN is already defined. */ +/* TWI_SDAHOLD is already defined. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.CTRLD bit masks and bit positions */ +#define USART_ABW_gm 0xC0 /* Auto Baud Window group mask. */ +#define USART_ABW_gp 6 /* Auto Baud Window group position. */ +#define USART_ABW0_bm (1<<6) /* Auto Baud Window bit 0 mask. */ +#define USART_ABW0_bp 6 /* Auto Baud Window bit 0 position. */ +#define USART_ABW1_bm (1<<7) /* Auto Baud Window bit 1 mask. */ +#define USART_ABW1_bp 7 /* Auto Baud Window bit 1 position. */ + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_AC0REFSEL_gm 0x07 /* AC0 reference select group mask. */ +#define VREF_AC0REFSEL_gp 0 /* AC0 reference select group position. */ +#define VREF_AC0REFSEL0_bm (1<<0) /* AC0 reference select bit 0 mask. */ +#define VREF_AC0REFSEL0_bp 0 /* AC0 reference select bit 0 position. */ +#define VREF_AC0REFSEL1_bm (1<<1) /* AC0 reference select bit 1 mask. */ +#define VREF_AC0REFSEL1_bp 1 /* AC0 reference select bit 1 position. */ +#define VREF_AC0REFSEL2_bm (1<<2) /* AC0 reference select bit 2 mask. */ +#define VREF_AC0REFSEL2_bp 2 /* AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_AC0REFEN_bm 0x01 /* AC0 DACREF reference enable bit mask. */ +#define VREF_AC0REFEN_bp 0 /* AC0 DACREF reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 3 +#define RTC_CNT_vect _VECTOR(3) /* */ +#define RTC_PIT_vect_num 4 +#define RTC_PIT_vect _VECTOR(4) /* */ + +/* CCL interrupt vectors */ +#define CCL_CCL_vect_num 5 +#define CCL_CCL_vect _VECTOR(5) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 6 +#define PORTA_PORT_vect _VECTOR(6) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 7 +#define TCA0_LUNF_vect _VECTOR(7) /* */ +#define TCA0_OVF_vect_num 7 +#define TCA0_OVF_vect _VECTOR(7) /* */ +#define TCA0_HUNF_vect_num 8 +#define TCA0_HUNF_vect _VECTOR(8) /* */ +#define TCA0_CMP0_vect_num 9 +#define TCA0_CMP0_vect _VECTOR(9) /* */ +#define TCA0_LCMP0_vect_num 9 +#define TCA0_LCMP0_vect _VECTOR(9) /* */ +#define TCA0_CMP1_vect_num 10 +#define TCA0_CMP1_vect _VECTOR(10) /* */ +#define TCA0_LCMP1_vect_num 10 +#define TCA0_LCMP1_vect _VECTOR(10) /* */ +#define TCA0_CMP2_vect_num 11 +#define TCA0_CMP2_vect _VECTOR(11) /* */ +#define TCA0_LCMP2_vect_num 11 +#define TCA0_LCMP2_vect _VECTOR(11) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 12 +#define TCB0_INT_vect _VECTOR(12) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 13 +#define TCB1_INT_vect _VECTOR(13) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 14 +#define TWI0_TWIS_vect _VECTOR(14) /* */ +#define TWI0_TWIM_vect_num 15 +#define TWI0_TWIM_vect _VECTOR(15) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 16 +#define SPI0_INT_vect _VECTOR(16) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 17 +#define USART0_RXC_vect _VECTOR(17) /* */ +#define USART0_DRE_vect_num 18 +#define USART0_DRE_vect _VECTOR(18) /* */ +#define USART0_TXC_vect_num 19 +#define USART0_TXC_vect _VECTOR(19) /* */ + +/* PORTD interrupt vectors */ +#define PORTD_PORT_vect_num 20 +#define PORTD_PORT_vect _VECTOR(20) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 21 +#define AC0_AC_vect _VECTOR(21) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 22 +#define ADC0_RESRDY_vect _VECTOR(22) /* */ +#define ADC0_WCOMP_vect_num 23 +#define ADC0_WCOMP_vect _VECTOR(23) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 24 +#define PORTC_PORT_vect _VECTOR(24) /* */ + +/* TCB2 interrupt vectors */ +#define TCB2_INT_vect_num 25 +#define TCB2_INT_vect _VECTOR(25) /* */ + +/* USART1 interrupt vectors */ +#define USART1_RXC_vect_num 26 +#define USART1_RXC_vect _VECTOR(26) /* */ +#define USART1_DRE_vect_num 27 +#define USART1_DRE_vect _VECTOR(27) /* */ +#define USART1_TXC_vect_num 28 +#define USART1_TXC_vect _VECTOR(28) /* */ + +/* PORTF interrupt vectors */ +#define PORTF_PORT_vect_num 29 +#define PORTF_PORT_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +/* USART2 interrupt vectors */ +#define USART2_RXC_vect_num 31 +#define USART2_RXC_vect _VECTOR(31) /* */ +#define USART2_DRE_vect_num 32 +#define USART2_DRE_vect _VECTOR(32) /* */ +#define USART2_TXC_vect_num 33 +#define USART2_TXC_vect _VECTOR(33) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 34 +#define PORTB_PORT_vect _VECTOR(34) /* */ + +/* PORTE interrupt vectors */ +#define PORTE_PORT_vect_num 35 +#define PORTE_PORT_vect _VECTOR(35) /* */ + +/* TCB3 interrupt vectors */ +#define TCB3_INT_vect_num 36 +#define TCB3_INT_vect _VECTOR(36) /* */ + +/* USART3 interrupt vectors */ +#define USART3_RXC_vect_num 37 +#define USART3_RXC_vect _VECTOR(37) /* */ +#define USART3_DRE_vect_num 38 +#define USART3_DRE_vect _VECTOR(38) /* */ +#define USART3_TXC_vect_num 39 +#define USART3_TXC_vect _VECTOR(39) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (40 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (8192) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (8192U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3C00) +# define INTERNAL_SRAM_SIZE (1024) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3C00U) +# define INTERNAL_SRAM_SIZE (1024U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x4000) +# define MAPPED_PROGMEM_SIZE (8192) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x4000U) +# define MAPPED_PROGMEM_SIZE (8192U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (8192) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (8192U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG (unsigned char)_BV(3) /* Reset Pin Configuration */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x2A + + +#endif /* #ifdef _AVR_ATMEGA809_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iom8515.h b/hardware/tools/avr/avr/include/avr/iom8515.h new file mode 100644 index 0000000000000000000000000000000000000000..c49dc837f140b81723a6714a8d4c5e451f40c5a4 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom8515.h @@ -0,0 +1,687 @@ +/* Copyright (c) 2002, Steinar Haugen + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom8515.h 2235 2011-03-17 04:13:14Z arcanum $ */ + +/* avr/iom8515.h - definitions for ATmega8515 */ + +#ifndef _AVR_IOM8515_H_ +#define _AVR_IOM8515_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom8515.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* Oscillator Calibration Register */ +#define OSCCAL _SFR_IO8(0x04) + +/* Input Pins, Port E */ +#define PINE _SFR_IO8(0x05) + +/* Data Direction Register, Port E */ +#define DDRE _SFR_IO8(0x06) + +/* Data Register, Port E */ +#define PORTE _SFR_IO8(0x07) + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) + +/* USART Baud Rate Register */ +#define UBRRL _SFR_IO8(0x09) + +/* USART Control and Status Register B */ +#define UCSRB _SFR_IO8(0x0A) + +/* USART Control and Status Register A */ +#define UCSRA _SFR_IO8(0x0B) + +/* USART I/O Data Register */ +#define UDR _SFR_IO8(0x0C) + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x0D) + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x0E) + +/* SPI I/O Data Register */ +#define SPDR _SFR_IO8(0x0F) + +/* Input Pins, Port D */ +#define PIND _SFR_IO8(0x10) + +/* Data Direction Register, Port D */ +#define DDRD _SFR_IO8(0x11) + +/* Data Register, Port D */ +#define PORTD _SFR_IO8(0x12) + +/* Input Pins, Port C */ +#define PINC _SFR_IO8(0x13) + +/* Data Direction Register, Port C */ +#define DDRC _SFR_IO8(0x14) + +/* Data Register, Port C */ +#define PORTC _SFR_IO8(0x15) + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* Input Pins, Port A */ +#define PINA _SFR_IO8(0x19) + +/* Data Direction Register, Port A */ +#define DDRA _SFR_IO8(0x1A) + +/* Data Register, Port A */ +#define PORTA _SFR_IO8(0x1B) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO16(0x1E) +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +/* USART Baud Rate Register HI */ +/* USART Control and Status Register C */ +#define UBRRH _SFR_IO8(0x20) +#define UCSRC UBRRH + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* T/C 1 Input Capture Register */ +#define ICR1 _SFR_IO16(0x24) +#define ICR1L _SFR_IO8(0x24) +#define ICR1H _SFR_IO8(0x25) + +/* Timer/Counter1 Output Compare Register B */ +#define OCR1B _SFR_IO16(0x28) +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Timer/Counter1 Output Compare Register A */ +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Timer/Counter 1 */ +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +/* Timer/Counter 1 Control and Status Register */ +#define TCCR1B _SFR_IO8(0x2E) + +/* Timer/Counter 1 Control Register */ +#define TCCR1A _SFR_IO8(0x2F) + +/* Special Function IO Register */ +#define SFIOR _SFR_IO8(0x30) + +/* Timer/Counter 0 Output Compare Register */ +#define OCR0 _SFR_IO8(0x31) + +/* Timer/Counter 0 */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter 0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU Control and Status Register */ +#define MCUCSR _SFR_IO8(0x34) + +/* MCU Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* Extended MCU Control Register */ +#define EMCUCR _SFR_IO8(0x36) + +/* Store Program Memory Control Register */ +#define SPMCR _SFR_IO8(0x37) + +/* Timer/Counter Interrupt Flag register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK register */ +#define TIMSK _SFR_IO8(0x39) + +/* General Interrupt Flag Register */ +#define GIFR _SFR_IO8(0x3A) + +/* General Interrupt Control Register */ +#define GICR _SFR_IO8(0x3B) + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt Request 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt Request 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect_num 3 +#define TIMER1_CAPT_vect _VECTOR(3) +#define SIG_INPUT_CAPTURE1 _VECTOR(3) + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect_num 4 +#define TIMER1_COMPA_vect _VECTOR(4) +#define SIG_OUTPUT_COMPARE1A _VECTOR(4) + +/* Timer/Counter1 Compare MatchB */ +#define TIMER1_COMPB_vect_num 5 +#define TIMER1_COMPB_vect _VECTOR(5) +#define SIG_OUTPUT_COMPARE1B _VECTOR(5) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 6 +#define TIMER1_OVF_vect _VECTOR(6) +#define SIG_OVERFLOW1 _VECTOR(6) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 7 +#define TIMER0_OVF_vect _VECTOR(7) +#define SIG_OVERFLOW0 _VECTOR(7) + +/* Serial Transfer Complete */ +#define SPI_STC_vect_num 8 +#define SPI_STC_vect _VECTOR(8) +#define SIG_SPI _VECTOR(8) + +/* UART, Rx Complete */ +#define USART_RX_vect_num 9 +#define USART_RX_vect _VECTOR(9) +#define UART_RX_vect _VECTOR(9) /* For compatability only */ +#define SIG_UART_RECV _VECTOR(9) /* For compatability only */ + +/* UART Data Register Empty */ +#define USART_UDRE_vect_num 10 +#define USART_UDRE_vect _VECTOR(10) +#define UART_UDRE_vect _VECTOR(10) /* For compatability only */ +#define SIG_UART_DATA _VECTOR(10) /* For compatability only */ + +/* UART, Tx Complete */ +#define USART_TX_vect_num 11 +#define USART_TX_vect _VECTOR(11) +#define UART_TX_vect _VECTOR(11) /* For compatability only */ +#define SIG_UART_TRANS _VECTOR(11) /* For compatability only */ + +/* Analog Comparator */ +#define ANA_COMP_vect_num 12 +#define ANA_COMP_vect _VECTOR(12) +#define SIG_COMPARATOR _VECTOR(12) + +/* External Interrupt Request 2 */ +#define INT2_vect_num 13 +#define INT2_vect _VECTOR(13) +#define SIG_INTERRUPT2 _VECTOR(13) + +/* Timer 0 Compare Match */ +#define TIMER0_COMP_vect_num 14 +#define TIMER0_COMP_vect _VECTOR(14) +#define SIG_OUTPUT_COMPARE0 _VECTOR(14) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 15 +#define EE_RDY_vect _VECTOR(15) +#define SIG_EEPROM_READY _VECTOR(15) + +/* Store Program Memory Ready */ +#define SPM_RDY_vect_num 16 +#define SPM_RDY_vect _VECTOR(16) +#define SIG_SPM_READY _VECTOR(16) + +#define _VECTORS_SIZE 34 + +/* + The Register Bit names are represented by their bit number (0-7). +*/ + +/* General Interrupt Control Register */ +#define INT1 7 +#define INT0 6 +#define INT2 5 +#define IVSEL 1 +#define IVCE 0 + +/* General Interrupt Flag Register */ +#define INTF1 7 +#define INTF0 6 +#define INTF2 5 + +/* Timer/Counter Interrupt MaSK Register */ +#define TOIE1 7 +#define OCIE1A 6 +#define OCIE1B 5 +#define TICIE1 3 +#define TOIE0 1 +#define OCIE0 0 + +/* Timer/Counter Interrupt Flag Register */ +#define TOV1 7 +#define OCF1A 6 +#define OCF1B 5 +#define ICF1 3 +#define TOV0 1 +#define OCF0 0 + +/* Store Program Memory Control Register */ +#define SPMIE 7 +#define RWWSB 6 +#define RWWSRE 4 +#define BLBSET 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 + +/* Extended MCU Control Register */ +#define SM0 7 +#define SRL2 6 +#define SRL1 5 +#define SRL0 4 +#define SRW01 3 +#define SRW00 2 +#define SRW11 1 +#define ISC2 0 + +/* MCU Control Register */ +#define SRE 7 +#define SRW10 6 +#define SE 5 +#define SM1 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/* MCU Control and Status Register */ +#define SM2 5 +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +/* Timer/Counter 0 Control Register */ +#define FOC0 7 +#define WGM00 6 +#define COM01 5 +#define COM00 4 +#define WGM01 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* Special Function IO Register */ +#define XMBK 6 +#define XMM2 5 +#define XMM1 4 +#define XMM0 3 +#define PUD 2 +#define PSR10 0 + +/* Timer/Counter 1 Control Register */ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define FOC1A 3 +#define FOC1B 2 +#define WGM11 1 +#define WGM10 0 + +/* Timer/Counter 1 Control and Status Register */ +#define ICNC1 7 +#define ICES1 6 +#define WGM13 4 +#define WGM12 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* Watchdog Timer Control Register */ +#define WDCE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* USART Control and Status Register C */ +#define URSEL 7 +#define UMSEL 6 +#define UPM1 5 +#define UPM0 4 +#define USBS 3 +#define UCSZ1 2 +#define UCSZ0 1 +#define UCPOL 0 + +/* Data Register, Port A */ +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* Data Direction Register, Port A */ +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +/* Input Pins, Port A */ +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +/* Data Register, Port B */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Data Direction Register, Port B */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Input Pins, Port B */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* Data Register, Port C */ +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* Data Direction Register, Port C */ +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +/* Input Pins, Port C */ +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +/* Data Register, Port D */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* Data Direction Register, Port D */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* Input Pins, Port D */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* SPI Status Register */ +#define SPIF 7 +#define WCOL 6 +#define SPI2X 0 + +/* SPI Control Register */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* USART Control and Status Register A */ +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 +#define PE 2 +#define U2X 1 +#define MPCM 0 + +/* USART Control and Status Register B */ +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define UCSZ2 2 +#define RXB8 1 +#define TXB8 0 + +/* Analog Comparator Control and Status Register */ +#define ACD 7 +#define ACBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +/* Data Register, Port E */ +#define PE2 2 +#define PE1 1 +#define PE0 0 + +/* Data Direction Register, Port E */ +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +/* Input Pins, Port E */ +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define SPM_PAGESIZE 64 +#define RAMSTART (0x60) +#define RAMEND 0x25F /* Last On-Chip SRAM Location */ +#define XRAMEND 0xFFFF +#define E2END 0x1FF +#define E2PAGESIZE 4 +#define FLASHEND 0x1FFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 2 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_BODEN (unsigned char)~_BV(6) +#define FUSE_BODLEVEL (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_CKOPT (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_WDTON (unsigned char)~_BV(6) +#define FUSE_S8515C (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x06 + + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_INTERRUPT1 +#pragma GCC poison SIG_INPUT_CAPTURE1 +#pragma GCC poison SIG_OUTPUT_COMPARE1A +#pragma GCC poison SIG_OUTPUT_COMPARE1B +#pragma GCC poison SIG_OVERFLOW1 +#pragma GCC poison SIG_OVERFLOW0 +#pragma GCC poison SIG_SPI +#pragma GCC poison UART_RX_vect +#pragma GCC poison SIG_UART_RECV +#pragma GCC poison UART_UDRE_vect +#pragma GCC poison SIG_UART_DATA +#pragma GCC poison UART_TX_vect +#pragma GCC poison SIG_UART_TRANS +#pragma GCC poison SIG_COMPARATOR +#pragma GCC poison SIG_INTERRUPT2 +#pragma GCC poison SIG_OUTPUT_COMPARE0 +#pragma GCC poison SIG_EEPROM_READY +#pragma GCC poison SIG_SPM_READY + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + +#define SLEEP_MODE_IDLE 0 +#define SLEEP_MODE_PWR_DOWN 1 +#define SLEEP_MODE_PWR_SAVE 2 +#define SLEEP_MODE_ADC 3 +#define SLEEP_MODE_STANDBY 4 +#define SLEEP_MODE_EXT_STANDBY 5 + +#endif /* _AVR_IOM8515_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom8535.h b/hardware/tools/avr/avr/include/avr/iom8535.h new file mode 100644 index 0000000000000000000000000000000000000000..8cfa7447fe82c5e979139e26c395376355af771f --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom8535.h @@ -0,0 +1,772 @@ +/* Copyright (c) 2002, Steinar Haugen + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom8535.h 2235 2011-03-17 04:13:14Z arcanum $ */ + +/* avr/iom8535.h - definitions for ATmega8535 */ + +#ifndef _AVR_IOM8535_H_ +#define _AVR_IOM8535_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom8535.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ +#define TWBR _SFR_IO8(0x00) +#define TWSR _SFR_IO8(0x01) +#define TWAR _SFR_IO8(0x02) +#define TWDR _SFR_IO8(0x03) + +/* ADC Data register */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) + +/* ADC Control and Status Register */ +#define ADCSRA _SFR_IO8(0x06) + +/* ADC MUX */ +#define ADMUX _SFR_IO8(0x07) + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) + +/* USART Baud Rate Register */ +#define UBRRL _SFR_IO8(0x09) + +/* USART Control and Status Register B */ +#define UCSRB _SFR_IO8(0x0A) + +/* USART Control and Status Register A */ +#define UCSRA _SFR_IO8(0x0B) + +/* USART I/O Data Register */ +#define UDR _SFR_IO8(0x0C) + +/* SPI Control Register */ +#define SPCR _SFR_IO8(0x0D) + +/* SPI Status Register */ +#define SPSR _SFR_IO8(0x0E) + +/* SPI I/O Data Register */ +#define SPDR _SFR_IO8(0x0F) + +/* Input Pins, Port D */ +#define PIND _SFR_IO8(0x10) + +/* Data Direction Register, Port D */ +#define DDRD _SFR_IO8(0x11) + +/* Data Register, Port D */ +#define PORTD _SFR_IO8(0x12) + +/* Input Pins, Port C */ +#define PINC _SFR_IO8(0x13) + +/* Data Direction Register, Port C */ +#define DDRC _SFR_IO8(0x14) + +/* Data Register, Port C */ +#define PORTC _SFR_IO8(0x15) + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* Input Pins, Port A */ +#define PINA _SFR_IO8(0x19) + +/* Data Direction Register, Port A */ +#define DDRA _SFR_IO8(0x1A) + +/* Data Register, Port A */ +#define PORTA _SFR_IO8(0x1B) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO16(0x1E) +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +/* USART Baud Rate Register HI */ +/* USART Control and Status Register C */ +#define UBRRH _SFR_IO8(0x20) +#define UCSRC UBRRH + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* Asynchronous mode Status Register */ +#define ASSR _SFR_IO8(0x22) + +/* Timer/Counter2 Output Compare Register */ +#define OCR2 _SFR_IO8(0x23) + +/* Timer/Counter 2 */ +#define TCNT2 _SFR_IO8(0x24) + +/* Timer/Counter 2 Control Register */ +#define TCCR2 _SFR_IO8(0x25) + +/* T/C 1 Input Capture Register */ +#define ICR1 _SFR_IO16(0x26) +#define ICR1L _SFR_IO8(0x26) +#define ICR1H _SFR_IO8(0x27) + +/* Timer/Counter1 Output Compare Register B */ +#define OCR1B _SFR_IO16(0x28) +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Timer/Counter1 Output Compare Register A */ +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Timer/Counter 1 */ +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +/* Timer/Counter 1 Control and Status Register */ +#define TCCR1B _SFR_IO8(0x2E) + +/* Timer/Counter 1 Control Register */ +#define TCCR1A _SFR_IO8(0x2F) + +/* Special Function IO Register */ +#define SFIOR _SFR_IO8(0x30) + +/* Oscillator Calibration Register */ +#define OSCCAL _SFR_IO8(0x31) + +/* Timer/Counter 0 */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter 0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU Control and Status Register */ +#define MCUCSR _SFR_IO8(0x34) + +/* MCU Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* TWI Control Register */ +#define TWCR _SFR_IO8(0x36) + +/* Store Program Memory Control Register */ +#define SPMCR _SFR_IO8(0x37) + +/* Timer/Counter Interrupt Flag register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK register */ +#define TIMSK _SFR_IO8(0x39) + +/* General Interrupt Flag Register */ +#define GIFR _SFR_IO8(0x3A) + +/* General Interrupt MaSK register */ +#define GICR _SFR_IO8(0x3B) + +/* Timer/Counter 0 Output Compare Register */ +#define OCR0 _SFR_IO8(0x3C) + +/* 0x3D..0x3E SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* Timer/Counter2 Compare Match */ +#define TIMER2_COMP_vect_num 3 +#define TIMER2_COMP_vect _VECTOR(3) +#define SIG_OUTPUT_COMPARE2 _VECTOR(3) + +/* Timer/Counter2 Overflow */ +#define TIMER2_OVF_vect_num 4 +#define TIMER2_OVF_vect _VECTOR(4) +#define SIG_OVERFLOW2 _VECTOR(4) + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect_num 5 +#define TIMER1_CAPT_vect _VECTOR(5) +#define SIG_INPUT_CAPTURE1 _VECTOR(5) + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect_num 6 +#define TIMER1_COMPA_vect _VECTOR(6) +#define SIG_OUTPUT_COMPARE1A _VECTOR(6) + +/* Timer/Counter1 Compare Match B */ +#define TIMER1_COMPB_vect_num 7 +#define TIMER1_COMPB_vect _VECTOR(7) +#define SIG_OUTPUT_COMPARE1B _VECTOR(7) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 8 +#define TIMER1_OVF_vect _VECTOR(8) +#define SIG_OVERFLOW1 _VECTOR(8) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 9 +#define TIMER0_OVF_vect _VECTOR(9) +#define SIG_OVERFLOW0 _VECTOR(9) + +/* SPI Serial Transfer Complete */ +#define SPI_STC_vect_num 10 +#define SPI_STC_vect _VECTOR(10) +#define SIG_SPI _VECTOR(10) + +/* USART, RX Complete */ +#define USART_RX_vect_num 11 +#define USART_RX_vect _VECTOR(11) +#define SIG_UART_RECV _VECTOR(11) + +/* USART Data Register Empty */ +#define USART_UDRE_vect_num 12 +#define USART_UDRE_vect _VECTOR(12) +#define SIG_UART_DATA _VECTOR(12) + +/* USART, TX Complete */ +#define USART_TX_vect_num 13 +#define USART_TX_vect _VECTOR(13) +#define SIG_UART_TRANS _VECTOR(13) + +/* ADC Conversion Complete */ +#define ADC_vect_num 14 +#define ADC_vect _VECTOR(14) +#define SIG_ADC _VECTOR(14) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 15 +#define EE_RDY_vect _VECTOR(15) +#define SIG_EEPROM_READY _VECTOR(15) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 16 +#define ANA_COMP_vect _VECTOR(16) +#define SIG_COMPARATOR _VECTOR(16) + +/* Two-wire Serial Interface */ +#define TWI_vect_num 17 +#define TWI_vect _VECTOR(17) +#define SIG_2WIRE_SERIAL _VECTOR(17) + +/* External Interrupt Request 2 */ +#define INT2_vect_num 18 +#define INT2_vect _VECTOR(18) +#define SIG_INTERRUPT2 _VECTOR(18) + +/* TimerCounter0 Compare Match */ +#define TIMER0_COMP_vect_num 19 +#define TIMER0_COMP_vect _VECTOR(19) +#define SIG_OUTPUT_COMPARE0 _VECTOR(19) + +/* Store Program Memory Read */ +#define SPM_RDY_vect_num 20 +#define SPM_RDY_vect _VECTOR(20) +#define SIG_SPM_READY _VECTOR(20) + +#define _VECTORS_SIZE 42 + +/* + The Register Bit names are represented by their bit number (0-7). +*/ + +/* General Interrupt Control Register */ +#define INT1 7 +#define INT0 6 +#define INT2 5 +#define IVSEL 1 +#define IVCE 0 + +/* General Interrupt Flag Register */ +#define INTF1 7 +#define INTF0 6 +#define INTF2 5 + +/* Timer/Counter Interrupt MaSK register */ +#define OCIE2 7 +#define TOIE2 6 +#define TICIE1 5 +#define OCIE1A 4 +#define OCIE1B 3 +#define TOIE1 2 +#define OCIE0 1 +#define TOIE0 0 + +/* Timer/Counter Interrupt Flag register */ +#define OCF2 7 +#define TOV2 6 +#define ICF1 5 +#define OCF1A 4 +#define OCF1B 3 +#define TOV1 2 +#define OCF0 1 +#define TOV0 0 + +/* Store Program Memory Control Register */ +#define SPMIE 7 +#define RWWSB 6 +#define RWWSRE 4 +#define BLBSET 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 + +/* TWI Control Register */ +#define TWINT 7 +#define TWEA 6 +#define TWSTA 5 +#define TWSTO 4 +#define TWWC 3 +#define TWEN 2 +#define TWIE 0 + +/* MCU Control Register */ +#define SM2 7 +#define SE 6 +#define SM1 5 +#define SM0 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/* MCU Control and Status Register */ +#define ISC2 6 +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +/* Timer/Counter 0 Control Register */ +#define FOC0 7 +#define WGM00 6 +#define COM01 5 +#define COM00 4 +#define WGM01 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* + The ADHSM bit has been removed from all documentation, + as being not needed at all since the comparator has proven + to be fast enough even without feeding it more power. +*/ + +/* Special Function IO Register */ +#define ADTS2 7 +#define ADTS1 6 +#define ADTS0 5 +#define ACME 3 +#define PUD 2 +#define PSR2 1 +#define PSR10 0 + +/* Timer/Counter 1 Control Register */ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define FOC1A 3 +#define FOC1B 2 +#define WGM11 1 +#define WGM10 0 + +/* Timer/Counter 1 Control and Status Register */ +#define ICNC1 7 +#define ICES1 6 +#define WGM13 4 +#define WGM12 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* Timer/Counter 2 Control Register */ +#define FOC2 7 +#define WGM20 6 +#define COM21 5 +#define COM20 4 +#define WGM21 3 +#define CS22 2 +#define CS21 1 +#define CS20 0 + +/* Asynchronous mode Status Register */ +#define AS2 3 +#define TCN2UB 2 +#define OCR2UB 1 +#define TCR2UB 0 + +/* Watchdog Timer Control Register */ +#define WDCE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* USART Control and Status Register C */ +#define URSEL 7 +#define UMSEL 6 +#define UPM1 5 +#define UPM0 4 +#define USBS 3 +#define UCSZ1 2 +#define UCSZ0 1 +#define UCPOL 0 + +/* Data Register, Port A */ +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* Data Direction Register, Port A */ +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +/* Input Pins, Port A */ +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +/* Data Register, Port B */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Data Direction Register, Port B */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Input Pins, Port B */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* Data Register, Port C */ +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* Data Direction Register, Port C */ +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +/* Input Pins, Port C */ +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +/* Data Register, Port D */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* Data Direction Register, Port D */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* Input Pins, Port D */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* SPI Status Register */ +#define SPIF 7 +#define WCOL 6 +#define SPI2X 0 + +/* SPI Control Register */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +/* USART Control and Status Register A */ +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 +#define PE 2 +#define U2X 1 +#define MPCM 0 + +/* USART Control and Status Register B */ +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define UCSZ2 2 +#define RXB8 1 +#define TXB8 0 + +/* Analog Comparator Control and Status Register */ +#define ACD 7 +#define ACBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +/* ADC Multiplexer Selection Register */ +#define REFS1 7 +#define REFS0 6 +#define ADLAR 5 +#define MUX4 4 +#define MUX3 3 +#define MUX2 2 +#define MUX1 1 +#define MUX0 0 + +/* ADC Control and Status Register */ +#define ADEN 7 +#define ADSC 6 +#define ADATE 5 +#define ADIF 4 +#define ADIE 3 +#define ADPS2 2 +#define ADPS1 1 +#define ADPS0 0 + +/* TWI (Slave) Address Register */ +#define TWGCE 0 + +/* TWI Status Register */ +#define TWS7 7 +#define TWS6 6 +#define TWS5 5 +#define TWS4 4 +#define TWS3 3 +#define TWPS1 1 +#define TWPS0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define SPM_PAGESIZE 64 +#define RAMSTART (0x60) +#define RAMEND 0x25F /* Last On-Chip SRAM Location */ +#define XRAMEND RAMEND +#define E2END 0x1FF +#define E2PAGESIZE 4 +#define FLASHEND 0x1FFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 2 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_BODEN (unsigned char)~_BV(6) +#define FUSE_BODLEVEL (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_CKOPT (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_WDTON (unsigned char)~_BV(6) +#define FUSE_S8535C (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x08 + + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_INTERRUPT1 +#pragma GCC poison SIG_OUTPUT_COMPARE2 +#pragma GCC poison SIG_OVERFLOW2 +#pragma GCC poison SIG_INPUT_CAPTURE1 +#pragma GCC poison SIG_OUTPUT_COMPARE1A +#pragma GCC poison SIG_OUTPUT_COMPARE1B +#pragma GCC poison SIG_OVERFLOW1 +#pragma GCC poison SIG_OVERFLOW0 +#pragma GCC poison SIG_SPI +#pragma GCC poison SIG_UART_RECV +#pragma GCC poison SIG_UART_DATA +#pragma GCC poison SIG_UART_TRANS +#pragma GCC poison SIG_ADC +#pragma GCC poison SIG_EEPROM_READY +#pragma GCC poison SIG_COMPARATOR +#pragma GCC poison SIG_2WIRE_SERIAL +#pragma GCC poison SIG_INTERRUPT2 +#pragma GCC poison SIG_OUTPUT_COMPARE0 +#pragma GCC poison SIG_SPM_READY + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + + +#define SLEEP_MODE_IDLE (0x00<<4) +#define SLEEP_MODE_ADC (0x01<<4) +#define SLEEP_MODE_PWR_DOWN (0x02<<4) +#define SLEEP_MODE_PWR_SAVE (0x03<<4) +#define SLEEP_MODE_STANDBY (0x0A<<4) +#define SLEEP_MODE_EXT_STANDBY (0x0B<<4) + +#endif /* _AVR_IOM8535_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom88.h b/hardware/tools/avr/avr/include/avr/iom88.h new file mode 100644 index 0000000000000000000000000000000000000000..ece11b27965835870f74d140394e8c3389e02beb --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom88.h @@ -0,0 +1,97 @@ +/* Copyright (c) 2004, Theodore A. Roth + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom88.h 2115 2010-04-05 23:19:53Z arcanum $ */ + +#ifndef _AVR_IOM88_H_ +#define _AVR_IOM88_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 64 +#define RAMSTART (0x100) +#define RAMEND 0x4FF +#define XRAMEND RAMEND +#define E2END 0x1FF +#define E2PAGESIZE 4 +#define FLASHEND 0x1FFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ +#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ +#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ +#define HFUSE_DEFAULT (FUSE_SPIEN) + +/* Extended Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x0A + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) + +#endif /* _AVR_IOM88_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iom88a.h b/hardware/tools/avr/avr/include/avr/iom88a.h new file mode 100644 index 0000000000000000000000000000000000000000..d01dbf4f3afecf0d405d158c27b904b1863463f6 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom88a.h @@ -0,0 +1,35 @@ +/***************************************************************************** + * + * Copyright (C) 2011 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + +#include "iom88.h" +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) diff --git a/hardware/tools/avr/avr/include/avr/iom88p.h b/hardware/tools/avr/avr/include/avr/iom88p.h new file mode 100644 index 0000000000000000000000000000000000000000..39fab866adda2c72265be1e338a0d5499af78dd1 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom88p.h @@ -0,0 +1,941 @@ +/* Copyright (c) 2007 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +/* $Id: iom88p.h 2225 2011-03-02 16:27:26Z arcanum $ */ + +/* avr/iom88p.h - definitions for ATmega88P. */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom88p.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_IOM88P_H_ +#define _AVR_IOM88P_H_ 1 + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 + +#define EEPROM_REG_LOCATIONS 1F2021 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom88pa.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega88PA_H_ +#define _AVR_ATmega88PA_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom88pb.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define ACSRB _SFR_IO8(0x0F) +#define ACOE 0 + +/* Reserved [0x10..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom8a.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define TWBR _SFR_IO8(0x00) + +#define TWSR _SFR_IO8(0x01) +#define TWPS0 0 +#define TWPS1 1 +#define TWS3 3 +#define TWS4 4 +#define TWS5 5 +#define TWS6 6 +#define TWS7 7 + +#define TWAR _SFR_IO8(0x02) +#define TWGCE 0 +#define TWA0 1 +#define TWA1 2 +#define TWA2 3 +#define TWA3 4 +#define TWA4 5 +#define TWA5 6 +#define TWA6 7 + +#define TWDR _SFR_IO8(0x03) + +/* Combine ADCL and ADCH */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) + +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) + +#define ADCSRA _SFR_IO8(0x06) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADFR 5 +#define ADSC 6 +#define ADEN 7 + +#define ADMUX _SFR_IO8(0x07) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define ADLAR 5 +#define REFS0 6 +#define REFS1 7 + +#define ACSR _SFR_IO8(0x08) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define UBRRL _SFR_IO8(0x09) + +#define UCSRB _SFR_IO8(0x0A) +#define TXB8 0 +#define RXB8 1 +#define UCSZ2 2 +#define TXEN 3 +#define RXEN 4 +#define UDRIE 5 +#define TXCIE 6 +#define RXCIE 7 + +#define UCSRA _SFR_IO8(0x0B) +#define MPCM 0 +#define U2X 1 +#define UPE 2 +#define DOR 3 +#define FE 4 +#define UDRE 5 +#define TXC 6 +#define RXC 7 + +#define UDR _SFR_IO8(0x0C) + +#define SPCR _SFR_IO8(0x0D) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x0E) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x0F) + +#define PIND _SFR_IO8(0x10) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x11) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x12) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINC _SFR_IO8(0x13) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x14) +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x15) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PINB _SFR_IO8(0x16) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x17) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x18) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +/* Reserved [0x19..0x1B] */ + +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0x1D) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x1E) + +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +#define UCSRC _SFR_IO8(0x20) +#define UCPOL 0 +#define UCSZ0 1 +#define UCSZ1 2 +#define USBS 3 +#define UPM0 4 +#define UPM1 5 +#define UMSEL 6 +#define URSEL 7 + +#define UBRRH _SFR_IO8(0x20) + +#define WDTCR _SFR_IO8(0x21) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define ASSR _SFR_IO8(0x22) +#define TCR2UB 0 +#define OCR2UB 1 +#define TCN2UB 2 +#define AS2 3 + +#define OCR2 _SFR_IO8(0x23) + +#define TCNT2 _SFR_IO8(0x24) + +#define TCCR2 _SFR_IO8(0x25) +#define CS20 0 +#define CS21 1 +#define CS22 2 +#define WGM21 3 +#define COM20 4 +#define COM21 5 +#define WGM20 6 +#define FOC2 7 + +/* Combine ICR1L and ICR1H */ +#define ICR1 _SFR_IO16(0x26) + +#define ICR1L _SFR_IO8(0x26) +#define ICR1H _SFR_IO8(0x27) + +/* Combine OCR1BL and OCR1BH */ +#define OCR1B _SFR_IO16(0x28) + +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Combine OCR1AL and OCR1AH */ +#define OCR1A _SFR_IO16(0x2A) + +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Combine TCNT1L and TCNT1H */ +#define TCNT1 _SFR_IO16(0x2C) + +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +#define TCCR1B _SFR_IO8(0x2E) +#define CS10 0 +#define CS11 1 +#define CS12 2 +#define WGM12 3 +#define WGM13 4 +#define ICES1 6 +#define ICNC1 7 + +#define TCCR1A _SFR_IO8(0x2F) +#define WGM10 0 +#define WGM11 1 +#define FOC1B 2 +#define FOC1A 3 +#define COM1B0 4 +#define COM1B1 5 +#define COM1A0 6 +#define COM1A1 7 + +#define SFIOR _SFR_IO8(0x30) +#define ACME 3 +#define PSR2 1 +#define PSR10 0 +#define PUD 2 +#define ADHSM 4 + +#define OSCCAL _SFR_IO8(0x31) +#define OSCCAL0 0 +#define OSCCAL1 1 +#define OSCCAL2 2 +#define OSCCAL3 3 +#define OSCCAL4 4 +#define OSCCAL5 5 +#define OSCCAL6 6 +#define OSCCAL7 7 + +#define TCNT0 _SFR_IO8(0x32) + +#define TCCR0 _SFR_IO8(0x33) +#define CS00 0 +#define CS01 1 +#define CS02 2 + +#define MCUCSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define ISC00 0 +#define ISC01 1 +#define ISC10 2 +#define ISC11 3 +#define SM0 4 +#define SM1 5 +#define SM2 6 +#define SE 7 + +#define TWCR _SFR_IO8(0x36) +#define TWIE 0 +#define TWEN 2 +#define TWWC 3 +#define TWSTO 4 +#define TWSTA 5 +#define TWEA 6 +#define TWINT 7 + +#define SPMCR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +#define TIFR _SFR_IO8(0x38) +#define TOV0 0 +#define TOV1 2 +#define OCF1B 3 +#define OCF1A 4 +#define ICF1 5 +#define TOV2 6 +#define OCF2 7 + +#define TIMSK _SFR_IO8(0x39) +#define TOIE0 0 +#define TOIE1 2 +#define OCIE1B 3 +#define OCIE1A 4 +#define TICIE1 5 +#define TOIE2 6 +#define OCIE2 7 + +#define GIFR _SFR_IO8(0x3A) +#define INTF0 6 +#define INTF1 7 + +#define GICR _SFR_IO8(0x3B) +#define IVCE 0 +#define IVSEL 1 +#define INT0 6 +#define INT1 7 + +/* Reserved [0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + + + +/* Values and associated defines */ + + +#define SLEEP_MODE_IDLE (0x00<<4) +#define SLEEP_MODE_ADC (0x01<<4) +#define SLEEP_MODE_PWR_DOWN (0x02<<4) +#define SLEEP_MODE_PWR_SAVE (0x03<<4) +#define SLEEP_MODE_STANDBY (0x06<<4) + +/* Interrupt vectors */ +/* Vector 0 is the reset vector */ +/* External Interrupt Request 0 */ +#define INT0_vect _VECTOR(1) +#define INT0_vect_num 1 + +/* External Interrupt Request 1 */ +#define INT1_vect _VECTOR(2) +#define INT1_vect_num 2 + +/* Timer/Counter2 Compare Match */ +#define TIMER2_COMP_vect _VECTOR(3) +#define TIMER2_COMP_vect_num 3 + +/* Timer/Counter2 Overflow */ +#define TIMER2_OVF_vect _VECTOR(4) +#define TIMER2_OVF_vect_num 4 + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect _VECTOR(5) +#define TIMER1_CAPT_vect_num 5 + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect _VECTOR(6) +#define TIMER1_COMPA_vect_num 6 + +/* Timer/Counter1 Compare Match B */ +#define TIMER1_COMPB_vect _VECTOR(7) +#define TIMER1_COMPB_vect_num 7 + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect _VECTOR(8) +#define TIMER1_OVF_vect_num 8 + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect _VECTOR(9) +#define TIMER0_OVF_vect_num 9 + +/* Serial Transfer Complete */ +#define SPI_STC_vect _VECTOR(10) +#define SPI_STC_vect_num 10 + +/* USART, Rx Complete */ +#define USART_RXC_vect _VECTOR(11) +#define USART_RXC_vect_num 11 + +/* USART Data Register Empty */ +#define USART_UDRE_vect _VECTOR(12) +#define USART_UDRE_vect_num 12 + +/* USART, Tx Complete */ +#define USART_TXC_vect _VECTOR(13) +#define USART_TXC_vect_num 13 + +/* ADC Conversion Complete */ +#define ADC_vect _VECTOR(14) +#define ADC_vect_num 14 + +/* EEPROM Ready */ +#define EE_RDY_vect _VECTOR(15) +#define EE_RDY_vect_num 15 + +/* Analog Comparator */ +#define ANA_COMP_vect _VECTOR(16) +#define ANA_COMP_vect_num 16 + +/* 2-wire Serial Interface */ +#define TWI_vect _VECTOR(17) +#define TWI_vect_num 17 + +/* Store Program Memory Ready */ +#define SPM_RDY_vect _VECTOR(18) +#define SPM_RDY_vect_num 18 + +#define _VECTORS_SIZE 38 + + +/* Constants */ + +#define SPM_PAGESIZE 64 +#define FLASHSTART 0x0000 +#define FLASHEND 0x1FFF +#define RAMSTART 0x0060 +#define RAMSIZE 1024 +#define RAMEND 0x045F +#define E2START 0 +#define E2SIZE 512 +#define E2PAGESIZE 4 +#define E2END 0x01FF +#define XRAMEND RAMEND + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 2 + +/* Low Fuse Byte */ +#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) +#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) +#define FUSE_BODEN (unsigned char)~_BV(6) +#define FUSE_BODLEVEL (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_SUT_CKSEL1 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4) + + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_CKOPT (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_WTDON (unsigned char)~_BV(6) +#define FUSE_RSTDISBL (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) + + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x07 + + +#endif /* #ifdef _AVR_ATMEGA8A_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iom8hva.h b/hardware/tools/avr/avr/include/avr/iom8hva.h new file mode 100644 index 0000000000000000000000000000000000000000..f900c58c2d57ea70771609dba1d14dd566f102c3 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom8hva.h @@ -0,0 +1,76 @@ +/* Copyright (c) 2007, Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom8hva.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ + +/* iom8hva.h - definitions for ATmega8HVA. */ + +#ifndef _AVR_IOM8HVA_H_ +#define _AVR_IOM8HVA_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 128 +#define RAMSTART 0x100 +#define RAMEND 0x2FF +#define XRAMEND RAMEND +#define E2END 0xFF +#define E2PAGESIZE 4 +#define FLASHEND 0x1FFF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 1 + +/* Low Fuse Byte */ +#define FUSE_SUT0 (unsigned char)~_BV(0) +#define FUSE_SUT1 (unsigned char)~_BV(1) +#define FUSE_SUT2 (unsigned char)~_BV(2) +#define FUSE_SELFPRGEN (unsigned char)~_BV(3) +#define FUSE_DWEN (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_EESAVE (unsigned char)~_BV(6) +#define FUSE_WDTON (unsigned char)~_BV(7) +#define FUSE_DEFAULT (FUSE_SPIEN) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_PWR_OFF (0x04<<1) + +#endif /* _AVR_IOM8HVA_H_ */ + diff --git a/hardware/tools/avr/avr/include/avr/iom8u2.h b/hardware/tools/avr/avr/include/avr/iom8u2.h new file mode 100644 index 0000000000000000000000000000000000000000..fa4c43a6019ff83736c745213939bbc6f327664f --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iom8u2.h @@ -0,0 +1,997 @@ +/* Copyright (c) 2009 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iom8u2.h 2245 2011-05-12 22:42:21Z arcanum $ */ + +/* avr/iom8u2.h - definitions for ATmega8U2 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom8u2.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATmega8U2_H_ +#define _AVR_ATmega8U2_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define OCF1C 3 +#define ICF1 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 +#define EEAR9 1 +#define EEAR10 2 +#define EEAR11 3 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 +#define PLLE 1 +#define PLLP0 2 +#define PLLP1 3 +#define PLLP2 4 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define DWDR _SFR_IO8(0x31) +#define DWDR0 0 +#define DWDR1 1 +#define DWDR2 2 +#define DWDR3 3 +#define DWDR4 4 +#define DWDR5 5 +#define DWDR6 6 +#define DWDR7 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define USBRF 5 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define EIND _SFR_IO8(0x3C) +#define EIND0 0 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define WDTCKD _SFR_MEM8(0x62) +#define WCLKD0 0 +#define WCLKD1 1 +#define WDEWIE 2 +#define WDEWIF 3 + +#define REGCR _SFR_MEM8(0x63) +#define REGDIS 0 + +#define PRR0 _SFR_MEM8(0x64) +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iomx8.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* Port B */ + +#define PINB _SFR_IO8 (0x03) +/* PINB */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8 (0x04) +/* DDRB */ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +#define PORTB _SFR_IO8 (0x05) +/* PORTB */ +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Port C */ + +#define PINC _SFR_IO8 (0x06) +/* PINC */ +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8 (0x07) +/* DDRC */ +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +#define PORTC _SFR_IO8 (0x08) +/* PORTC */ +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/* Port D */ + +#define PIND _SFR_IO8 (0x09) +/* PIND */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8 (0x0A) +/* DDRD */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +#define PORTD _SFR_IO8 (0x0B) +/* PORTD */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +#define TIFR0 _SFR_IO8 (0x15) +/* TIFR0 */ +#define OCF0B 2 +#define OCF0A 1 +#define TOV0 0 + +#define TIFR1 _SFR_IO8 (0x16) +/* TIFR1 */ +#define ICF1 5 +#define OCF1B 2 +#define OCF1A 1 +#define TOV1 0 + +#define TIFR2 _SFR_IO8 (0x17) +/* TIFR2 */ +#define OCF2B 2 +#define OCF2A 1 +#define TOV2 0 + +#define PCIFR _SFR_IO8 (0x1B) +/* PCIFR */ +#define PCIF2 2 +#define PCIF1 1 +#define PCIF0 0 + +#define EIFR _SFR_IO8 (0x1C) +/* EIFR */ +#define INTF1 1 +#define INTF0 0 + +#define EIMSK _SFR_IO8 (0x1D) +/* EIMSK */ +#define INT1 1 +#define INT0 0 + +#define GPIOR0 _SFR_IO8 (0x1E) + +#define EECR _SFR_IO8(0x1F) +/* EECT - EEPROM Control Register */ +#define EEPM1 5 +#define EEPM0 4 +#define EERIE 3 +#define EEMPE 2 +#define EEPE 1 +#define EERE 0 + +#define EEDR _SFR_IO8(0X20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0X22) +/* +Even though EEARH is not used by the mega48, the EEAR8 bit in the register +must be written to 0, according to the datasheet, hence the EEARH register +must be defined for the mega48. +*/ +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + + +#define GTCCR _SFR_IO8 (0x23) +/* GTCCR */ +#define TSM 7 +#define PSRASY 1 +#define PSRSYNC 0 + +#define TCCR0A _SFR_IO8 (0x24) +/* TCCR0A */ +#define COM0A1 7 +#define COM0A0 6 +#define COM0B1 5 +#define COM0B0 4 +#define WGM01 1 +#define WGM00 0 + +#define TCCR0B _SFR_IO8 (0x25) +/* TCCR0A */ +#define FOC0A 7 +#define FOC0B 6 +#define WGM02 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +#define TCNT0 _SFR_IO8 (0x26) +#define OCR0A _SFR_IO8 (0x27) +#define OCR0B _SFR_IO8 (0x28) + +#define GPIOR1 _SFR_IO8 (0x2A) +#define GPIOR2 _SFR_IO8 (0x2B) + +#define SPCR _SFR_IO8 (0x2C) +/* SPCR */ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +#define SPSR _SFR_IO8 (0x2D) +/* SPSR */ +#define SPIF 7 +#define WCOL 6 +#define SPI2X 0 + +#define SPDR _SFR_IO8 (0x2E) + +#define ACSR _SFR_IO8 (0x30) +/* ACSR */ +#define ACD 7 +#define ACBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +#define MONDR _SFR_IO8 (0x31) + +#define SMCR _SFR_IO8 (0x33) +/* SMCR */ +#define SM2 3 +#define SM1 2 +#define SM0 1 +#define SE 0 + +#define MCUSR _SFR_IO8 (0x34) +/* MCUSR */ +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +#define MCUCR _SFR_IO8 (0x35) +/* MCUCR */ +#define PUD 4 +#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) || defined (__AVR_ATmega48A__) || defined(__AVR_ATmega48PA__) +#define IVSEL 1 +#define IVCE 0 +#endif + +#define SPMCSR _SFR_IO8 (0x37) +/* SPMCSR */ +#define SPMIE 7 +#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) || (__AVR_ATmega88P__) || defined (__AVR_ATmega168P__) || (__AVR_ATmega88A__) || defined (__AVR_ATmega168A__) || (__AVR_ATmega88PA__) || defined (__AVR_ATmega168PA__) +# define RWWSB 6 +# define RWWSRE 4 +#endif +#if defined(__AVR_ATmega48A) || defined(__AVR_ATmega48PA) || defined(__AVR_ATmega88A) || defined(__AVR_ATmega88PA) || defined(__AVR_ATmega168A) || defined(__AVR_ATmega168PA) + #define SIGRD 5 +#endif +#define BLBSET 3 +#define PGWRT 2 +#define PGERS 1 +#define SELFPRGEN 0 +#define SPMEN 0 + +/* 0x3D..0x3E SP [defined in ] */ +/* 0x3F SREG [defined in ] */ + +#define WDTCSR _SFR_MEM8 (0x60) +/* WDTCSR */ +#define WDIF 7 +#define WDIE 6 +#define WDP3 5 +#define WDCE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +#define CLKPR _SFR_MEM8 (0x61) +/* CLKPR */ +#define CLKPCE 7 +#define CLKPS3 3 +#define CLKPS2 2 +#define CLKPS1 1 +#define CLKPS0 0 + +#define PRR _SFR_MEM8 (0x64) +/* PRR */ +#define PRTWI 7 +#define PRTIM2 6 +#define PRTIM0 5 +#define PRTIM1 3 +#define PRSPI 2 +#define PRUSART0 1 +#define PRADC 0 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iomxx0_1.h" +#else +# error "Attempt to include more than one file." +#endif + +#if defined(__AVR_ATmega640__) || defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__) +# define __ATmegaxx0__ +#elif defined(__AVR_ATmega1281__) || defined(__AVR_ATmega2561__) +# define __ATmegaxx1__ +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0X00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0X01) +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +#define PORTA _SFR_IO8(0X02) +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +#define PINB _SFR_IO8(0X03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDE7 7 +#define DDE6 6 +#define DDE5 5 +#define DDE4 4 +#define DDE3 3 +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PE7 7 +#define PE6 6 +#define PE5 5 +#define PE4 4 +#define PE3 3 +#define PE2 2 +#define PE1 1 +#define PE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDF7 7 +#define DDF6 6 +#define DDF5 5 +#define DDF4 4 +#define DDF3 3 +#define DDF2 2 +#define DDF1 1 +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PF7 7 +#define PF6 6 +#define PF5 5 +#define PF4 4 +#define PF3 3 +#define PF2 2 +#define PF1 1 +#define PF0 0 + +#define PING _SFR_IO8(0x12) +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDG5 5 +#define DDG4 4 +#define DDG3 3 +#define DDG2 2 +#define DDG1 1 +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PG5 5 +#define PG4 4 +#define PG3 3 +#define PG2 2 +#define PG1 1 +#define PG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define OCF0B 2 +#define OCF0A 1 +#define TOV0 0 + +#define TIFR1 _SFR_IO8(0x16) +#define ICF1 5 +#define OCF1C 3 +#define OCF1B 2 +#define OCF1A 1 +#define TOV1 0 + +#define TIFR2 _SFR_IO8(0x17) +#define OCF2B 2 +#define OCF2A 1 +#define TOV2 0 + +#define TIFR3 _SFR_IO8(0x18) +#define ICF3 5 +#define OCF3C 3 +#define OCF3B 2 +#define OCF3A 1 +#define TOV3 0 + +#define TIFR4 _SFR_IO8(0x19) +#define ICF4 5 +#define OCF4C 3 +#define OCF4B 2 +#define OCF4A 1 +#define TOV4 0 + +#define TIFR5 _SFR_IO8(0x1A) +#define ICF5 5 +#define OCF5C 3 +#define OCF5B 2 +#define OCF5A 1 +#define TOV5 0 + +#define PCIFR _SFR_IO8(0x1B) +#if defined(__ATmegaxx0__) +# define PCIF2 2 +#endif /* __ATmegaxx0__ */ +#define PCIF1 1 +#define PCIF0 0 + +#define EIFR _SFR_IO8(0x1C) +#define INTF7 7 +#define INTF6 6 +#define INTF5 5 +#define INTF4 4 +#define INTF3 3 +#define INTF2 2 +#define INTF1 1 +#define INTF0 0 + +#define EIMSK _SFR_IO8(0x1D) +#define INT7 7 +#define INT6 6 +#define INT5 5 +#define INT4 4 +#define INT3 3 +#define INT2 2 +#define INT1 1 +#define INT0 0 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EEPM1 5 +#define EEPM0 4 +#define EERIE 3 +#define EEMPE 2 +#define EEPE 1 +#define EERE 0 + +#define EEDR _SFR_IO8(0X20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0X22) + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +#define GTCCR _SFR_IO8(0x23) +#define TSM 7 +#define PSRASY 1 +#define PSRSYNC 0 + +#define TCCR0A _SFR_IO8(0x24) +#define COM0A1 7 +#define COM0A0 6 +#define COM0B1 5 +#define COM0B0 4 +#define WGM01 1 +#define WGM00 0 + +#define TCCR0B _SFR_IO8(0x25) +#define FOC0A 7 +#define FOC0B 6 +#define WGM02 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +#define TCNT0 _SFR_IO8(0X26) + +#define OCR0A _SFR_IO8(0X27) + +#define OCR0B _SFR_IO8(0X28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +#define SPSR _SFR_IO8(0x2D) +#define SPIF 7 +#define WCOL 6 +#define SPI2X 0 + +#define SPDR _SFR_IO8(0X2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACD 7 +#define ACBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +#define MONDR _SFR_IO8(0x31) +#define OCDR _SFR_IO8(0x31) +#define IDRD 7 +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SM2 3 +#define SM1 2 +#define SM0 1 +#define SE 0 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +#define MCUCR _SFR_IO8(0X35) +#define JTD 7 +#define PUD 4 +#define IVSEL 1 +#define IVCE 0 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMIE 7 +#define RWWSB 6 +#define SIGRD 5 +#define RWWSRE 4 +#define BLBSET 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 + +/* Reserved [0x38..0x3A] */ + +#define RAMPZ _SFR_IO8(0X3B) +#define RAMPZ0 0 + +#define EIND _SFR_IO8(0X3C) +#define EIND0 0 + +/* SP [0x3D..0x3E] */ +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDIF 7 +#define WDIE 6 +#define WDP3 5 +#define WDCE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPCE 7 +#define CLKPS3 3 +#define CLKPS2 2 +#define CLKPS1 1 +#define CLKPS0 0 + +/* Reserved [0x62..0x63] */ + +#define PRR0 _SFR_MEM8(0x64) +#define PRTWI 7 +#define PRTIM2 6 +#define PRTIM0 5 +#define PRTIM1 3 +#define PRSPI 2 +#define PRUSART0 1 +#define PRADC 0 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom164.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0X00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0X01) +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +#define PORTA _SFR_IO8(0X02) +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +#define PINB _SFR_IO8(0X03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* Reserved [0x0C..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define OCF0B 2 +#define OCF0A 1 +#define TOV0 0 + +#define TIFR1 _SFR_IO8(0x16) +#define ICF1 5 +#define OCF1B 2 +#define OCF1A 1 +#define TOV1 0 + +#define TIFR2 _SFR_IO8(0x17) +#define OCF2B 2 +#define OCF2A 1 +#define TOV2 0 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF3 3 +#define PCIF2 2 +#define PCIF1 1 +#define PCIF0 0 + +#define EIFR _SFR_IO8(0x1C) +#define INTF2 2 +#define INTF1 1 +#define INTF0 0 + +#define EIMSK _SFR_IO8(0x1D) +#define INT2 2 +#define INT1 1 +#define INT0 0 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +/* EECR - EEPROM Control Register */ +#define EEPM1 5 +#define EEPM0 4 +#define EERIE 3 +#define EEMPE 2 +#define EEPE 1 +#define EERE 0 + +#define EEDR _SFR_IO8(0X20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0X22) + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +#define GTCCR _SFR_IO8(0x23) +#define TSM 7 +#define PSRASY 1 +#define PSRSYNC 0 + +#define TCCR0A _SFR_IO8(0x24) +#define COM0A1 7 +#define COM0A0 6 +#define COM0B1 5 +#define COM0B0 4 +#define WGM01 1 +#define WGM00 0 + +#define TCCR0B _SFR_IO8(0x25) +#define FOC0A 7 +#define FOC0B 6 +#define WGM02 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +#define TCNT0 _SFR_IO8(0X26) + +#define OCR0A _SFR_IO8(0X27) + +#define OCR0B _SFR_IO8(0X28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +#define SPSR _SFR_IO8(0x2D) +#define SPIF 7 +#define WCOL 6 +#define SPI2X 0 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACD 7 +#define ACBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +#define MONDR _SFR_IO8(0x31) +#define OCDR _SFR_IO8(0x31) +#define IDRD 7 +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SM2 3 +#define SM1 2 +#define SM0 1 +#define SE 0 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +#define MCUCR _SFR_IO8(0X35) +#define JTD 7 +#if !defined(__AVR_ATmega644__) +#define BODS 6 +#define BODSE 5 +#endif +#define PUD 4 +#define IVSEL 1 +#define IVCE 0 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMIE 7 +#define RWWSB 6 +#define SIGRD 5 +#define RWWSRE 4 +#define BLBSET 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDIF 7 +#define WDIE 6 +#define WDP3 5 +#define WDCE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPCE 7 +#define CLKPS3 3 +#define CLKPS2 2 +#define CLKPS1 1 +#define CLKPS0 0 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) /* Datasheets: ATmega164P/324P/644P 8011D�AVR�02/07 + and ATmega644 2593L�AVR�02/07. */ +#define PRR0 _SFR_MEM8(0x64) /* AVR Studio 4.13, build 524. */ +#define PRTWI 7 +#define PRTIM2 6 +#define PRTIM0 5 +#if !defined(__AVR_ATmega644__) +# define PRUSART1 4 +#endif +#define PRTIM1 3 +#define PRSPI 2 +#define PRUSART0 1 +#define PRADC 0 + +#if !defined(__AVR_ATmega644__) +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iomxxhva.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0X00) +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA1 1 +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PA1 1 +#define PA0 0 + +#define PINB _SFR_IO8(0X03) +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 + +/* Reserved [0x7] */ + +#define PORTC _SFR_IO8(0x08) +#define PC0 0 + +/* Reserved [0x9..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define ICF0 3 +#define OCF0B 2 +#define OCF0A 1 +#define TOV0 0 + +#define TIFR1 _SFR_IO8(0x16) +#define ICF1 3 +#define OCF1B 2 +#define OCF1A 1 +#define TOV1 0 + +#define OSICSR _SFR_IO8(0x17) +#define OSISEL0 4 +#define OSIST 1 +#define OSIEN 0 + +/* Reserved [0x18..0x1B] */ + +#define EIFR _SFR_IO8(0x1C) +#define INTF2 2 +#define INTF1 1 +#define INTF0 0 + +#define EIMSK _SFR_IO8(0x1D) +#define INT2 2 +#define INT1 1 +#define INT0 0 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EEPM1 5 +#define EEPM0 4 +#define EERIE 3 +#define EEMPE 2 +#define EEPE 1 +#define EERE 0 + +#define EEDR _SFR_IO8(0x20) + +#define EEAR _SFR_IO8(0x21) +#define EEARL _SFR_IO8(0x21) + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +/* Reserved [0x22] */ + +#define GTCCR _SFR_IO8(0x23) +#define TSM 7 +#define PSRSYNC 0 + +#define TCCR0A _SFR_IO8(0x24) +#define TCW0 7 +#define ICEN0 6 +#define ICNC0 5 +#define ICES0 4 +#define ICS0 3 +#define WGM00 0 + +#define TCCR0B _SFR_IO8(0x25) +#define CS02 2 +#define CS01 1 +#define CS00 0 + +#define TCNT0 _SFR_IO16(0X26) +#define TCNT0L _SFR_IO8(0X26) +#define TCNT0H _SFR_IO8(0X27) + +#define OCR0A _SFR_IO8(0x28) + +#define OCR0B _SFR_IO8(0X29) + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +#define SPSR _SFR_IO8(0x2D) +#define SPIF 7 +#define WCOL 6 +#define SPI2X 0 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F..0x30] */ + +#define DWDR _SFR_IO8(0x31) +#define IDRD 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SM2 3 +#define SM1 2 +#define SM0 1 +#define SE 0 + +#define MCUSR _SFR_IO8(0x34) +#define OCDRF 4 +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +#define MCUCR _SFR_IO8(0x35) +#define CKOE 5 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SIGRD 5 +#define CTPB 4 +#define RFLB 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDIF 7 +#define WDIE 6 +#define WDP3 5 +#define WDCE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPCE 7 +#define CLKPS1 1 +#define CLKPS0 0 + +/* Reserved [0x62..0x63] */ + +#define PRR0 _SFR_MEM8(0x64) +#define PRVRM 5 +#define PRSPI 3 +#define PRTIM1 2 +#define PRTIM0 1 +#define PRVADC 0 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn10.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATtiny10_H_ +#define _AVR_ATtiny10_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINB _SFR_IO8(0x00) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 + +#define DDRB _SFR_IO8(0x01) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 + +#define PORTB _SFR_IO8(0x02) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 + +#define PUEB _SFR_IO8(0x03) +#define PUEB0 0 +#define PUEB1 1 +#define PUEB2 2 +#define PUEB3 3 + +#define PORTCR _SFR_IO8(0x0C) +#define BBMB 1 + +#define PCMSK _SFR_IO8(0x10) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 + +#define PCIFR _SFR_IO8(0x11) +#define PCIF0 0 + +#define PCICR _SFR_IO8(0x12) +#define PCIE0 0 + +#define EIMSK _SFR_IO8(0x13) +#define INT0 0 + +#define EIFR _SFR_IO8(0x14) +#define INTF0 0 + +#define EICRA _SFR_IO8(0x15) +#define ISC00 0 +#define ISC01 1 + +#define DIDR0 _SFR_IO8(0x17) +#define ADC0D 0 +#define AIN0D 0 +#define ADC1D 1 +#define AIN1D 1 +#define ADC2D 2 +#define ADC3D 3 + +#define ADCL _SFR_IO8(0x19) +#define ADC0 0 +#define ADC1 1 +#define ADC2 2 +#define ADC3 3 +#define ADC4 4 +#define ADC5 5 +#define ADC6 6 +#define ADC7 7 + +#define ADMUX _SFR_IO8(0x1B) +#define MUX0 0 +#define MUX1 1 + +#define ADCSRB _SFR_IO8(0x1C) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 + +#define ADCSRA _SFR_IO8(0x1D) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +#define ACSR _SFR_IO8(0x1F) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACD 7 + +#define ICR0 _SFR_IO16(0x22) + +#define ICR0L _SFR_IO8(0x22) +#define ICR0_0 0 +#define ICR0_1 1 +#define ICR0_2 2 +#define ICR0_3 3 +#define ICR0_4 4 +#define ICR0_5 5 +#define ICR0_6 6 +#define ICR0_7 7 + +#define ICR0H _SFR_IO8(0x23) +#define ICR0_8 0 +#define ICR0_9 1 +#define ICR0_10 2 +#define ICR0_11 3 +#define ICR0_12 4 +#define ICR0_13 5 +#define ICR0_14 6 +#define ICR0_15 7 + +#define OCR0B _SFR_IO16(0x24) + +#define OCR0BL _SFR_IO8(0x24) +#define OCR0B0 0 +#define OCR0B1 1 +#define OCR0B2 2 +#define OCR0B3 3 +#define OCR0B4 4 +#define OCR0B5 5 +#define OCR0B6 6 +#define OCR0B7 7 + +#define OCR0BH _SFR_IO8(0x25) +#define OCR0B8 0 +#define OCR0B9 1 +#define OCR0B10 2 +#define OCR0B11 3 +#define OCR0B12 4 +#define OCR0B13 5 +#define OCR0B14 6 +#define OCR0B15 7 + +#define OCR0A _SFR_IO16(0x26) + +#define OCR0AL _SFR_IO8(0x26) +#define OCR0A0 0 +#define OCR0A1 1 +#define OCR0A2 2 +#define OCR0A3 3 +#define OCR0A4 4 +#define OCR0A5 5 +#define OCR0A6 6 +#define OCR0A7 7 + +#define OCR0AH _SFR_IO8(0x27) +#define OCR0A8 0 +#define OCR0A9 1 +#define OCR0A10 2 +#define OCR0A11 3 +#define OCR0A12 4 +#define OCR0A13 5 +#define OCR0A14 6 +#define OCR0A15 7 + +#define TCNT0 _SFR_IO16(0x28) + +#define TCNT0L _SFR_IO8(0x28) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define TCNT0H _SFR_IO8(0x29) +#define TCNT0_8 0 +#define TCNT0_9 1 +#define TCNT0_10 2 +#define TCNT0_11 3 +#define TCNT0_12 4 +#define TCNT0_13 5 +#define TCNT0_14 6 +#define TCNT0_15 7 + +#define TIFR0 _SFR_IO8(0x2A) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define ICF0 5 + +#define TIMSK0 _SFR_IO8(0x2B) +#define TOIE0 0 +#define OCIE0A 1 +#define OCIE0B 2 +#define ICIE0 5 + +#define TCCR0C _SFR_IO8(0x2C) +#define FOC0B 6 +#define FOC0A 7 + +#define TCCR0B _SFR_IO8(0x2D) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define WGM03 4 +#define ICES0 6 +#define ICNC0 7 + +#define TCCR0A _SFR_IO8(0x2E) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define GTCCR _SFR_IO8(0x2F) +#define PSR 0 +#define TSM 7 + +#define WDTCSR _SFR_IO8(0x31) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define NVMCSR _SFR_IO8(0x32) +#define NVMBSY 7 + +#define NVMCMD _SFR_IO8(0x33) +#define NVMCMD0 0 +#define NVMCMD1 1 +#define NVMCMD2 2 +#define NVMCMD3 3 +#define NVMCMD4 4 +#define NVMCMD5 5 + +#define VLMCSR _SFR_IO8(0x34) +#define VLM0 0 +#define VLM1 1 +#define VLM2 2 +#define VLMIE 6 +#define VLMF 7 + +#define PRR _SFR_IO8(0x35) +#define PRTIM0 0 +#define PRADC 1 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn102.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PUEA _SFR_IO8(0x03) +#define PUEA7 7 +#define PUEA6 6 +#define PUEA5 5 +#define PUEA4 4 +#define PUEA3 3 +#define PUEA2 2 +#define PUEA1 1 +#define PUEA0 0 + +#define PINB _SFR_IO8(0x04) +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x05) +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x06) +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PUEB _SFR_IO8(0x07) +#define PUEB3 3 +#define PUEB2 2 +#define PUEB1 1 +#define PUEB0 0 + +#define UDR _SFR_IO8(0x08) + +/* Combine UBRRL and UBRRH */ +#define UBRR _SFR_IO16(0x09) + +#define UBRRL _SFR_IO8(0x09) +#define UBRRH _SFR_IO8(0x0A) + +#define UCSRD _SFR_IO8(0x0B) +#define SFDE 5 +#define RXS 6 +#define RXSIE 7 + +#define UCSRC _SFR_IO8(0x0C) +#define UCPOL 0 +#define UCSZ0 1 +#define UCSZ1 2 +#define USBS 3 +#define UPM0 4 +#define UPM1 5 +#define UMSEL0 6 +#define UMSEL1 7 + +#define UCSRB _SFR_IO8(0x0D) +#define TXB8 0 +#define RXB8 1 +#define UCSZ2 2 +#define TXEN 3 +#define RXEN 4 +#define UDRIE 5 +#define TXCIE 6 +#define RXCIE 7 + +#define UCSRA _SFR_IO8(0x0E) +#define MPCM 0 +#define U2X 1 +#define UPE 2 +#define DOR 3 +#define FE 4 +#define UDRE 5 +#define TXC 6 +#define RXC 7 + +#define PCMSK0 _SFR_IO8(0x0F) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 +#define PCINT4 4 +#define PCINT5 5 +#define PCINT6 6 +#define PCINT7 7 + +#define PCMSK1 _SFR_IO8(0x10) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 +#define PCINT11 3 + +#define PCIFR _SFR_IO8(0x11) +#define PCIF0 0 +#define PCIF1 1 + +#define PCICR _SFR_IO8(0x12) +#define PCIE0 0 +#define PCIE1 1 + +#define EIMSK _SFR_IO8(0x13) +#define INT0 0 + +#define EIFR _SFR_IO8(0x14) +#define INTF0 0 + +#define EICRA _SFR_IO8(0x15) +#define ISC00 0 +#define ISC01 1 + +#define PORTCR _SFR_IO8(0x16) +#define BBMA 0 +#define BBMB 1 + +#define DIDR0 _SFR_IO8(0x17) +#define ADC0D 0 +#define ADC1D 1 +#define ADC2D 2 +#define ADC3D 3 +#define ADC4D 4 +#define ADC5D 5 +#define ADC6D 6 +#define ADC7D 7 +#define AIN0D 0 +#define AIN1D 1 + +/* Reserved [0x18] */ + +#define ADCL _SFR_IO8(0x19) + +#define ADCH _SFR_IO8(0x1A) + +#define ADMUX _SFR_IO8(0x1B) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define REFS0 6 +#define REFS1 7 + +#define ADCSRB _SFR_IO8(0x1C) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 +#define ADLAR 7 + +#define ADCSRA _SFR_IO8(0x1D) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +#define ACSRB _SFR_IO8(0x1E) +#define ACPMUX 0 +#define ACOE 1 + +#define ACSRA _SFR_IO8(0x1F) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x20..0x21] */ + +/* Combine ICR0L and ICR0H */ +#define ICR0 _SFR_IO16(0x22) + +#define ICR0L _SFR_IO8(0x22) +#define ICR0H _SFR_IO8(0x23) + +/* Combine OCR0BL and OCR0BH */ +#define OCR0B _SFR_IO16(0x24) + +#define OCR0BL _SFR_IO8(0x24) +#define OCR0BH _SFR_IO8(0x25) + +/* Combine OCR0AL and OCR0AH */ +#define OCR0A _SFR_IO16(0x26) + +#define OCR0AL _SFR_IO8(0x26) +#define OCR0AH _SFR_IO8(0x27) + +/* Combine TCNT0L and TCNT0H */ +#define TCNT0 _SFR_IO16(0x28) + +#define TCNT0L _SFR_IO8(0x28) +#define TCNT0H _SFR_IO8(0x29) + +#define TIFR0 _SFR_IO8(0x2A) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define ICF0 5 + +#define TIMSK0 _SFR_IO8(0x2B) +#define TOIE0 0 +#define OCIE0A 1 +#define OCIE0B 2 +#define ICIE0 5 + +#define TCCR0C _SFR_IO8(0x2C) +#define FOC0B 6 +#define FOC0A 7 + +#define TCCR0B _SFR_IO8(0x2D) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define WGM03 4 +#define ICES0 6 +#define ICNC0 7 + +#define TCCR0A _SFR_IO8(0x2E) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define GTCCR _SFR_IO8(0x2F) +#define PSR 0 +#define REMAP 1 +#define TSM 7 + +/* Reserved [0x30] */ + +#define WDTCSR _SFR_IO8(0x31) +#define WDE 3 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define NVMCSR _SFR_IO8(0x32) +#define NVMBSY 7 + +#define NVMCMD _SFR_IO8(0x33) + +#define VLMCSR _SFR_IO8(0x34) +#define VLM0 0 +#define VLM1 1 +#define VLM2 2 +#define VLMIE 6 +#define VLMF 7 + +#define PRR _SFR_IO8(0x35) +#define PRTIM0 0 +#define PRADC 1 +#define PRUSART 2 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn104.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PUEA _SFR_IO8(0x03) +#define PUEA7 7 +#define PUEA6 6 +#define PUEA5 5 +#define PUEA4 4 +#define PUEA3 3 +#define PUEA2 2 +#define PUEA1 1 +#define PUEA0 0 + +#define PINB _SFR_IO8(0x04) +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x05) +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x06) +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PUEB _SFR_IO8(0x07) +#define PUEB3 3 +#define PUEB2 2 +#define PUEB1 1 +#define PUEB0 0 + +#define UDR _SFR_IO8(0x08) + +/* Combine UBRRL and UBRRH */ +#define UBRR _SFR_IO16(0x09) + +#define UBRRL _SFR_IO8(0x09) +#define UBRRH _SFR_IO8(0x0A) + +#define UCSRD _SFR_IO8(0x0B) +#define SFDE 5 +#define RXS 6 +#define RXSIE 7 + +#define UCSRC _SFR_IO8(0x0C) +#define UCPOL 0 +#define UCSZ0 1 +#define UCSZ1 2 +#define USBS 3 +#define UPM0 4 +#define UPM1 5 +#define UMSEL0 6 +#define UMSEL1 7 + +#define UCSRB _SFR_IO8(0x0D) +#define TXB8 0 +#define RXB8 1 +#define UCSZ2 2 +#define TXEN 3 +#define RXEN 4 +#define UDRIE 5 +#define TXCIE 6 +#define RXCIE 7 + +#define UCSRA _SFR_IO8(0x0E) +#define MPCM 0 +#define U2X 1 +#define UPE 2 +#define DOR 3 +#define FE 4 +#define UDRE 5 +#define TXC 6 +#define RXC 7 + +#define PCMSK0 _SFR_IO8(0x0F) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 +#define PCINT4 4 +#define PCINT5 5 +#define PCINT6 6 +#define PCINT7 7 + +#define PCMSK1 _SFR_IO8(0x10) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 +#define PCINT11 3 + +#define PCIFR _SFR_IO8(0x11) +#define PCIF0 0 +#define PCIF1 1 + +#define PCICR _SFR_IO8(0x12) +#define PCIE0 0 +#define PCIE1 1 + +#define EIMSK _SFR_IO8(0x13) +#define INT0 0 + +#define EIFR _SFR_IO8(0x14) +#define INTF0 0 + +#define EICRA _SFR_IO8(0x15) +#define ISC00 0 +#define ISC01 1 + +#define PORTCR _SFR_IO8(0x16) +#define BBMA 0 +#define BBMB 1 + +#define DIDR0 _SFR_IO8(0x17) +#define ADC0D 0 +#define ADC1D 1 +#define ADC2D 2 +#define ADC3D 3 +#define ADC4D 4 +#define ADC5D 5 +#define ADC6D 6 +#define ADC7D 7 +#define AIN0D 0 +#define AIN1D 1 + +/* Reserved [0x18] */ + +#define ADCL _SFR_IO8(0x19) + +#define ADCH _SFR_IO8(0x1A) + +#define ADMUX _SFR_IO8(0x1B) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define REFS0 6 +#define REFS1 7 + +#define ADCSRB _SFR_IO8(0x1C) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 +#define ADLAR 7 + +#define ADCSRA _SFR_IO8(0x1D) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +#define ACSRB _SFR_IO8(0x1E) +#define ACPMUX 0 +#define ACOE 1 + +#define ACSRA _SFR_IO8(0x1F) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x20..0x21] */ + +/* Combine ICR0L and ICR0H */ +#define ICR0 _SFR_IO16(0x22) + +#define ICR0L _SFR_IO8(0x22) +#define ICR0H _SFR_IO8(0x23) + +/* Combine OCR0BL and OCR0BH */ +#define OCR0B _SFR_IO16(0x24) + +#define OCR0BL _SFR_IO8(0x24) +#define OCR0BH _SFR_IO8(0x25) + +/* Combine OCR0AL and OCR0AH */ +#define OCR0A _SFR_IO16(0x26) + +#define OCR0AL _SFR_IO8(0x26) +#define OCR0AH _SFR_IO8(0x27) + +/* Combine TCNT0L and TCNT0H */ +#define TCNT0 _SFR_IO16(0x28) + +#define TCNT0L _SFR_IO8(0x28) +#define TCNT0H _SFR_IO8(0x29) + +#define TIFR0 _SFR_IO8(0x2A) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define ICF0 5 + +#define TIMSK0 _SFR_IO8(0x2B) +#define TOIE0 0 +#define OCIE0A 1 +#define OCIE0B 2 +#define ICIE0 5 + +#define TCCR0C _SFR_IO8(0x2C) +#define FOC0B 6 +#define FOC0A 7 + +#define TCCR0B _SFR_IO8(0x2D) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define WGM03 4 +#define ICES0 6 +#define ICNC0 7 + +#define TCCR0A _SFR_IO8(0x2E) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define GTCCR _SFR_IO8(0x2F) +#define PSR 0 +#define REMAP 1 +#define TSM 7 + +/* Reserved [0x30] */ + +#define WDTCSR _SFR_IO8(0x31) +#define WDE 3 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define NVMCSR _SFR_IO8(0x32) +#define NVMBSY 7 + +#define NVMCMD _SFR_IO8(0x33) + +#define VLMCSR _SFR_IO8(0x34) +#define VLM0 0 +#define VLM1 1 +#define VLM2 2 +#define VLMIE 6 +#define VLMF 7 + +#define PRR _SFR_IO8(0x35) +#define PRTIM0 0 +#define PRADC 1 +#define PRUSART 2 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn11.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef __ASSEMBLER__ +# warning "MCU not supported by the C compiler" +#endif + +/* I/O registers */ + +/* 0x00..0x07 reserved */ + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) + +/* 0x09..0x15 reserved */ + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* 0x19..0x20 reserved */ + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* 0x22..0x31 reserved */ + +/* Timer/Counter0 (8-bit) */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU general Status Register */ +#define MCUSR _SFR_IO8(0x34) + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* 0x36..0x37 reserved */ + +/* Timer/Counter Interrupt Flag Register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK Register */ +#define TIMSK _SFR_IO8(0x39) + +/* General Interrupt Flag Register */ +#define GIFR _SFR_IO8(0x3A) + +/* General Interrupt MaSK register */ +#define GIMSK _SFR_IO8(0x3B) + +/* 0x3C..0x3E reserved */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt Request 0 */ +#define IO_PINS_vect_num 2 +#define IO_PINS_vect _VECTOR(2) +#define SIG_PIN _VECTOR(2) +#define SIG_PIN_CHANGE _VECTOR(2) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 3 +#define TIMER0_OVF_vect _VECTOR(3) +#define SIG_OVERFLOW0 _VECTOR(3) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 4 +#define ANA_COMP_vect _VECTOR(4) +#define SIG_COMPARATOR _VECTOR(4) + +#define _VECTORS_SIZE 10 + +/* Bit numbers */ + +/* GIMSK */ +#define INT0 6 +#define PCIE 5 + +/* GIFR */ +#define INTF0 6 +#define PCIF 5 + +/* TIMSK */ +#define TOIE0 1 + +/* TIFR */ +#define TOV0 1 + +/* MCUCR */ +#define SE 5 +#define SM 4 +#define ISC01 1 +#define ISC00 0 + +/* TCCR0 */ +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* WDTCR */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* + PB5 = RESET# + PB4 = XTAL2 + PB3 = XTAL1 + PB2 = T0 + PB1 = INT0 / AIN1 + PB0 = AIN0 + */ + +/* PORTB */ +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* DDRB */ +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* PINB */ +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* ACSR */ +#define ACD 7 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIS1 1 +#define ACIS0 0 + +#define RAMSTART 0x60 +/* Last memory addresses */ +#define RAMEND 0x1F +#define XRAMEND 0x0 +#define E2END 0x0 +#define E2PAGESIZE 2 +#define FLASHEND 0x3FF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 1 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_RSTDISBL (unsigned char)~_BV(3) +#define FUSE_FSTRT (unsigned char)~_BV(4) +#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x90 +#define SIGNATURE_2 0x04 + + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_PIN +#pragma GCC poison SIG_PIN_CHANGE +#pragma GCC poison SIG_OVERFLOW0 +#pragma GCC poison SIG_COMPARATOR + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + +#define SLEEP_MODE_IDLE (0x00<<4) +#define SLEEP_MODE_PWR_DOWN (0x01<<4) + +#endif /* _AVR_IOTN11_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iotn12.h b/hardware/tools/avr/avr/include/avr/iotn12.h new file mode 100644 index 0000000000000000000000000000000000000000..cba6c3ea061183c9126c384269dc5694df5d8c61 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn12.h @@ -0,0 +1,288 @@ +/* Copyright (c) 2002,2005 Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iotn12.h 2236 2011-03-17 21:53:39Z arcanum $ */ + +/* avr/iotn12.h - definitions for ATtiny12 */ + +#ifndef _AVR_IOTN12_H_ +#define _AVR_IOTN12_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn12.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef __ASSEMBLER__ +# warning "MCU not supported by the C compiler" +#endif + +/* I/O registers */ + +/* 0x00..0x07 reserved */ + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) + +/* 0x09..0x15 reserved */ + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* 0x19..0x1B reserved */ + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO8(0x1E) +#define EEARL _SFR_IO8(0x1E) + +/* 0x1F..0x20 reserved */ + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* 0x22..0x30 reserved */ + +/* Oscillator Calibration Register */ +#define OSCCAL _SFR_IO8(0x31) + +/* Timer/Counter0 (8-bit) */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU general Status Register */ +#define MCUSR _SFR_IO8(0x34) + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* 0x36..0x37 reserved */ + +/* Timer/Counter Interrupt Flag Register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK Register */ +#define TIMSK _SFR_IO8(0x39) + +/* General Interrupt Flag Register */ +#define GIFR _SFR_IO8(0x3A) + +/* General Interrupt MaSK register */ +#define GIMSK _SFR_IO8(0x3B) + +/* 0x3C..0x3E reserved */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt Request 0 */ +#define IO_PINS_vect_num 2 +#define IO_PINS_vect _VECTOR(2) +#define SIG_PIN _VECTOR(2) +#define SIG_PIN_CHANGE _VECTOR(2) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 3 +#define TIMER0_OVF_vect _VECTOR(3) +#define SIG_OVERFLOW0 _VECTOR(3) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 4 +#define EE_RDY_vect _VECTOR(4) +#define SIG_EEPROM_READY _VECTOR(4) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 5 +#define ANA_COMP_vect _VECTOR(5) +#define SIG_COMPARATOR _VECTOR(5) + +#define _VECTORS_SIZE 12 + +/* Bit numbers */ + +/* GIMSK */ +#define INT0 6 +#define PCIE 5 + +/* GIFR */ +#define INTF0 6 +#define PCIF 5 + +/* TIMSK */ +#define TOIE0 1 + +/* TIFR */ +#define TOV0 1 + +/* MCUCR */ +#define PUD 6 +#define SE 5 +#define SM 4 +#define ISC01 1 +#define ISC00 0 + +/* TCCR0 */ +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* WDTCR */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* + PB5 = RESET# + PB4 = XTAL2 + PB3 = XTAL1 + PB2 = T0 / SCK + PB1 = INT0 / AIN1 / MISO + PB0 = AIN0 / MOSI + */ + +/* PORTB */ +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* DDRB */ +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* PINB */ +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* ACSR */ +#define ACD 7 +#define AINBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIS1 1 +#define ACIS0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +#define RAMSTART 0x60 +/* Last memory addresses */ +#define RAMEND 0x1F +#define XRAMEND 0x0 +#define E2END 0x3F +#define E2PAGESIZE 2 +#define FLASHEND 0x3FF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 1 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_RSTDISBL (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_BODEN (unsigned char)~_BV(6) +#define FUSE_BODLEVEL (unsigned char)~_BV(7) +#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SPIEN & FUSE_BODLEVEL) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x90 +#define SIGNATURE_2 0x05 + + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_PIN +#pragma GCC poison SIG_PIN_CHANGE +#pragma GCC poison SIG_OVERFLOW0 +#pragma GCC poison SIG_EEPROM_READY +#pragma GCC poison SIG_COMPARATOR + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + +#define SLEEP_MODE_IDLE (0x00<<4) +#define SLEEP_MODE_PWR_DOWN (0x01<<4) + +#endif /* _AVR_IOTN12_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iotn13.h b/hardware/tools/avr/avr/include/avr/iotn13.h new file mode 100644 index 0000000000000000000000000000000000000000..4e5750024916fb8f5903dc0a3415b3c8a30ad067 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn13.h @@ -0,0 +1,395 @@ +/* Copyright (c) 2004, Theodore A. Roth + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iotn13.h 2236 2011-03-17 21:53:39Z arcanum $ */ + +/* avr/iotn13.h - definitions for ATtiny13 */ + +/* Verified 5/20/04 by Bruce Graham */ + +#ifndef _AVR_IOTN13_H_ +#define _AVR_IOTN13_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn13.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers and bit names */ + +/* ADC Control and Status Register B */ +#define ADCSRB _SFR_IO8(0x03) +# define ACME 6 +# define ADTS2 2 +# define ADTS1 1 +# define ADTS0 0 + +/* ADC Data Register */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16 (0x04) +#endif +#define ADCW _SFR_IO16 (0x04) +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) + +/* ADC Control and Status Register A */ +#define ADCSRA _SFR_IO8(0x06) +# define ADEN 7 +# define ADSC 6 +# define ADATE 5 +# define ADIF 4 +# define ADIE 3 +# define ADPS2 2 +# define ADPS1 1 +# define ADPS0 0 + +/* ADC Multiplex Selection Register */ +#define ADMUX _SFR_IO8(0x07) +# define REFS0 6 +# define ADLAR 5 +# define MUX1 1 +# define MUX0 0 + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) +# define ACD 7 +# define ACBG 6 +# define ACO 5 +# define ACI 4 +# define ACIE 3 +# define ACIS1 1 +# define ACIS0 0 + +/* Digital Input Disable Register 0 */ +#define DIDR0 _SFR_IO8(0x14) +# define ADC0D 5 +# define ADC2D 4 +# define ADC3D 3 +# define ADC1D 2 +# define AIN1D 1 +# define AIN0D 0 + +/* PIN Change Mask Register */ +#define PCMSK _SFR_IO8(0x15) +# define PCINT5 5 +# define PCINT4 4 +# define PCINT3 3 +# define PCINT2 2 +# define PCINT1 1 +# define PCINT0 0 + +/* Port B Pin Utilization [2535D-AVR-04/04] + - PORTB5 = PCINT5/RESET#/ADC0/dW + - PORTB4 = PCINT4/ADC2 + - PORTB3 = PCINT3/CLKI/ADC3 + - PORTB2 = SCK/ADC1/T0/PCINT2 + - PORTB1 = MISO/AIN1/OC0B/INT0/PCINT1 + - PORTB0 = MOSI/AIN0/OC0A/PCINT0 */ + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) +# define PINB5 5 +# define PINB4 4 +# define PINB3 3 +# define PINB2 2 +# define PINB1 1 +# define PINB0 0 + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) +# define DDB5 5 +# define DDB4 4 +# define DDB3 3 +# define DDB2 2 +# define DDB1 1 +# define DDB0 0 + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) +# define PB5 5 +# define PB4 4 +# define PB3 3 +# define PB2 2 +# define PB1 1 +# define PB0 0 + +/* ATtiny EEPROM Control Register EECR */ +#define EECR _SFR_IO8(0x1C) +#define EEPM1 5 +#define EEPM0 4 +#define EERIE 3 +#define EEMPE 2 +#define EEPE 1 +#define EERE 0 + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* The EEPROM Address Register EEAR[6:0] */ +#define EEAR _SFR_IO8(0x1E) +#define EEARL _SFR_IO8(0x1E) + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) +# define WDTIF 7 +# define WDTIE 6 +# define WDP3 5 +# define WDCE 4 +# define WDE 3 +# define WDP2 2 +# define WDP1 1 +# define WDP0 0 + +/* Clock Prescale Register */ +#define CLKPR _SFR_IO8(0x26) +# define CLKPCE 7 +# define CLKPS3 3 +# define CLKPS2 2 +# define CLKPS1 1 +# define CLKPS0 0 + +/* General Timer/Counter Control Register */ +#define GTCCR _SFR_IO8(0x28) +# define TSM 7 +# define PSR10 0 + +/* Output Compare 0 Register B */ +#define OCR0B _SFR_IO8(0x29) + +/* debugWIRE Data Register */ +#define DWDR _SFR_IO8(0x2e) + +/* Timer/Counter 0 Control Register A */ +#define TCCR0A _SFR_IO8(0x2f) +# define COM0A1 7 +# define COM0A0 6 +# define COM0B1 5 +# define COM0B0 4 +# define WGM01 1 +# define WGM00 0 + +/* Oscillator Calibration Register */ +#define OSCCAL _SFR_IO8(0x31) + +/* Timer/Counter0 (8-bit) */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter 0 Control Register B */ +#define TCCR0B _SFR_IO8(0x33) +# define FOC0A 7 +# define FOC0B 6 +# define WGM02 3 +# define CS02 2 +# define CS01 1 +# define CS00 0 + +/* MCU General Status Register */ +#define MCUSR _SFR_IO8(0x34) +# define WDRF 3 +# define BORF 2 +# define EXTRF 1 +# define PORF 0 + +/* MCU General Control Register */ +#define MCUCR _SFR_IO8(0x35) +# define PUD 6 +# define SE 5 +# define SM1 4 +# define SM0 3 +# define ISC01 1 +# define ISC00 0 + +/* Output Compare 0 REgister A */ +#define OCR0A _SFR_IO8(0x36) + +/* Store Program Memory Control and Status Register */ +#define SPMCSR _SFR_IO8(0x37) +# define CTPB 4 +# define RFLB 3 +# define PGWRT 2 +# define PGERS 1 +# define SPMEN 0 +# define SELFPRGEN 0 + +/* Timer/Counter 0 Interrupt Flag Register */ +#define TIFR0 _SFR_IO8(0x38) +# define OCF0B 3 +# define OCF0A 2 +# define TOV0 1 + +/* Timer/Counter 0 Interrupt MaSK Register */ +#define TIMSK0 _SFR_IO8(0x39) +# define OCIE0B 3 +# define OCIE0A 2 +# define TOIE0 1 + +/* General Interrupt Flag Register */ +#define GIFR _SFR_IO8(0x3a) +# define INTF0 6 +# define PCIF 5 + +/* General Interrupt MaSK register */ +#define GIMSK _SFR_IO8(0x3b) +# define INT0 6 +# define PCIE 5 + +/* SPL and SREG are defined in */ + +/* From the datasheet: + 1 0x0000 RESET External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset + 2 0x0001 INT0 External Interrupt Request 0 + 3 0x0002 PCINT0 Pin Change Interrupt Request 0 + 4 0x0003 TIM0_OVF Timer/Counter Overflow + 5 0x0004 EE_RDY EEPROM Ready + 6 0x0005 ANA_COMP Analog Comparator + 7 0x0006 TIM0_COMPA Timer/Counter Compare Match A + 8 0x0007 TIM0_COMPB Timer/Counter Compare Match B + 9 0x0008 WDT Watchdog Time-out + 10 0x0009 ADC ADC Conversion Complete */ + +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt Request 0 */ +#define PCINT0_vect_num 2 +#define PCINT0_vect _VECTOR(2) +#define SIG_PIN_CHANGE0 _VECTOR(2) + +/* Timer/Counter0 Overflow */ +#define TIM0_OVF_vect_num 3 +#define TIM0_OVF_vect _VECTOR(3) +#define SIG_OVERFLOW0 _VECTOR(3) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 4 +#define EE_RDY_vect _VECTOR(4) +#define SIG_EEPROM_READY _VECTOR(4) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 5 +#define ANA_COMP_vect _VECTOR(5) +#define SIG_COMPARATOR _VECTOR(5) + +/* Timer/Counter Compare Match A */ +#define TIM0_COMPA_vect_num 6 +#define TIM0_COMPA_vect _VECTOR(6) +#define SIG_OUTPUT_COMPARE0A _VECTOR(6) + +/* Timer/Counter Compare Match B */ +#define TIM0_COMPB_vect_num 7 +#define TIM0_COMPB_vect _VECTOR(7) +#define SIG_OUTPUT_COMPARE0B _VECTOR(7) + +/* Watchdog Time-out */ +#define WDT_vect_num 8 +#define WDT_vect _VECTOR(8) +#define SIG_WATCHDOG_TIMEOUT _VECTOR(8) + +/* ADC Conversion Complete */ +#define ADC_vect_num 9 +#define ADC_vect _VECTOR(9) +#define SIG_ADC _VECTOR(9) + +#define _VECTORS_SIZE 20 + +#define SPM_PAGESIZE 32 +#define RAMSTART (0x60) +#define RAMEND 0x9F +#define XRAMEND RAMEND +#define E2END 0x3F +#define E2PAGESIZE 4 +#define FLASHEND 0x3FF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 2 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_SUT0 (unsigned char)~_BV(2) +#define FUSE_SUT1 (unsigned char)~_BV(3) +#define FUSE_CKDIV8 (unsigned char)~_BV(4) +#define FUSE_WDTON (unsigned char)~_BV(5) +#define FUSE_EESAVE (unsigned char)~_BV(6) +#define FUSE_SPIEN (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT0 & FUSE_CKDIV8 & FUSE_SPIEN) + +/* High Fuse Byte */ +#define FUSE_RSTDISBL (unsigned char)~_BV(0) +#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +#define FUSE_DWEN (unsigned char)~_BV(3) +#define FUSE_SPMEN (unsigned char)~_BV(4) +#define HFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x90 +#define SIGNATURE_2 0x07 + + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_PIN_CHANGE0 +#pragma GCC poison SIG_OVERFLOW0 +#pragma GCC poison SIG_EEPROM_READY +#pragma GCC poison SIG_COMPARATOR +#pragma GCC poison SIG_OUTPUT_COMPARE0A +#pragma GCC poison SIG_OUTPUT_COMPARE0B +#pragma GCC poison SIG_WATCHDOG_TIMEOUT +#pragma GCC poison SIG_ADC + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + +#define SLEEP_MODE_IDLE (0x00<<3) +#define SLEEP_MODE_ADC (0x01<<3) +#define SLEEP_MODE_PWR_DOWN (0x02<<3) + +#endif /* _AVR_IOTN13_H_*/ diff --git a/hardware/tools/avr/avr/include/avr/iotn13a.h b/hardware/tools/avr/avr/include/avr/iotn13a.h new file mode 100644 index 0000000000000000000000000000000000000000..cb9db8f8636ae0876f0a4d198ee26783669eb21d --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn13a.h @@ -0,0 +1,394 @@ +/* Copyright (c) 2008 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iotn13a.h 1955 2009-04-28 08:51:16Z arcanum $ */ + +/* avr/iotn13a.h - definitions for ATtiny13 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn13a.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATTINY13A_H_ +#define _AVR_ATTINY13A_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define ADCSRB _SFR_IO8(0x03) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 +#define ACME 6 + +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) + +#define ADCL _SFR_IO8(0x04) +#define ADCL0 0 +#define ADCL1 1 +#define ADCL2 2 +#define ADCL3 3 +#define ADCL4 4 +#define ADCL5 5 +#define ADCL6 6 +#define ADCL7 7 + +#define ADCH _SFR_IO8(0x05) +#define ADCH0 0 +#define ADCH1 1 +#define ADCH2 2 +#define ADCH3 3 +#define ADCH4 4 +#define ADCH5 5 +#define ADCH6 6 +#define ADCH7 7 + +#define ADCSRA _SFR_IO8(0x06) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +#define ADMUX _SFR_IO8(0x07) +#define MUX0 0 +#define MUX1 1 +#define ADLAR 5 +#define REFS0 6 + +#define ACSR _SFR_IO8(0x08) +#define ACIS0 0 +#define ACIS1 1 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define DIDR0 _SFR_IO8(0x14) +#define AIN0D 0 +#define AIN1D 1 +#define ADC1D 2 +#define ADC3D 3 +#define ADC2D 4 +#define ADC0D 5 + +#define PCMSK _SFR_IO8(0x15) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 +#define PCINT4 4 +#define PCINT5 5 + +#define PINB _SFR_IO8(0x16) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 + +#define DDRB _SFR_IO8(0x17) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 + +#define PORTB _SFR_IO8(0x18) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 + +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEWE 1 +#define EEPE EEWE +#define EEMWE 2 +#define EEMPE EEMWE +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x1D) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEARL _SFR_IO8(0x1E) + +#define EEAR _SFR_IO8(0x1E) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 + +#define WDTCR _SFR_IO8(0x21) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDTIE 6 +#define WDTIF 7 + +#define PRR _SFR_IO8(0x25) +#define PRADC 0 +#define PRTIM0 1 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn15.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef __ASSEMBLER__ +# warning "MCU not supported by the C compiler" +#endif + +/* I/O registers */ + +/* 0x00..0x03 reserved */ + +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16 (0x04) +#endif +#define ADCW _SFR_IO16(0x04) +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) +#define ADCSR _SFR_IO8(0x06) +#define ADMUX _SFR_IO8(0x07) + +/* Analog Comparator Control and Status Register */ +#define ACSR _SFR_IO8(0x08) + +/* 0x09..0x15 reserved */ + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* 0x19..0x1B reserved */ + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO8(0x1E) +#define EEARL _SFR_IO8(0x1E) + +/* 0x1F..0x20 reserved */ + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* 0x22..0x2B reserved */ +#define SFIOR _SFR_IO8(0x2C) + +#define OCR1B _SFR_IO8(0x2D) +#define OCR1A _SFR_IO8(0x2E) +#define TCNT1 _SFR_IO8(0x2F) +#define TCCR1 _SFR_IO8(0x30) + +/* Oscillator Calibration Register */ +#define OSCCAL _SFR_IO8(0x31) + +/* Timer/Counter0 (8-bit) */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU general Status Register */ +#define MCUSR _SFR_IO8(0x34) + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* 0x36..0x37 reserved */ + +/* Timer/Counter Interrupt Flag Register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK Register */ +#define TIMSK _SFR_IO8(0x39) + +/* General Interrupt Flag Register */ +#define GIFR _SFR_IO8(0x3A) + +/* General Interrupt MaSK register */ +#define GIMSK _SFR_IO8(0x3B) + +/* 0x3C..0x3E reserved */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt Request 0 */ +#define IO_PINS_vect_num 2 +#define IO_PINS_vect _VECTOR(2) +#define SIG_PIN _VECTOR(2) +#define SIG_PIN_CHANGE _VECTOR(2) + +/* Timer/Counter1 Compare Match */ +#define TIMER1_COMP_vect_num 3 +#define TIMER1_COMP_vect _VECTOR(3) +#define SIG_OUTPUT_COMPARE1A _VECTOR(3) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 4 +#define TIMER1_OVF_vect _VECTOR(4) +#define SIG_OVERFLOW1 _VECTOR(4) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 5 +#define TIMER0_OVF_vect _VECTOR(5) +#define SIG_OVERFLOW0 _VECTOR(5) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 6 +#define EE_RDY_vect _VECTOR(6) +#define SIG_EEPROM_READY _VECTOR(6) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 7 +#define ANA_COMP_vect _VECTOR(7) +#define SIG_COMPARATOR _VECTOR(7) + +/* ADC Conversion Ready */ +#define ADC_vect_num 8 +#define ADC_vect _VECTOR(8) +#define SIG_ADC _VECTOR(8) + +#define _VECTORS_SIZE 18 + +/* Bit numbers */ + +/* GIMSK */ +#define INT0 6 +#define PCIE 5 + +/* GIFR */ +#define INTF0 6 +#define PCIF 5 + +/* TIMSK */ +#define OCIE1 6 +#define TOIE1 2 +#define TOIE0 1 + +/* TIFR */ +#define OCF1 6 +#define TOV1 2 +#define TOV0 1 + +/* MCUCR */ +#define PUD 6 +#define SE 5 +#define SM1 4 +#define SM0 3 +#define ISC01 1 +#define ISC00 0 + +/* MCUSR */ +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +/* TCCR0 */ +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* TCCR1 */ +#define CTC1 7 +#define PWM1 6 +#define COM1A1 5 +#define COM1A0 4 +#define CS13 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* SFIOR */ +#define FOC1A 2 +#define PSR1 1 +#define PSR0 0 + +/* WDTCR */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* + PB5 = RESET# / ADC0 + PB4 = ADC3 + PB3 = ADC2 + PB2 = SCK / ADC1 / T0 / INT0 + PB1 = MISO / AIN1 / OCP + PB0 = MOSI / AIN0 / AREF + */ + +/* PORTB */ +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* DDRB */ +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* PINB */ +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* ACSR */ +#define ACD 7 +#define GREF 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIS1 1 +#define ACIS0 0 + +/* ADMUX */ +#define REFS1 7 +#define REFS0 6 +#define ADLAR 5 +#define MUX2 2 +#define MUX1 1 +#define MUX0 0 + +/* ADCSR */ +#define ADEN 7 +#define ADSC 6 +#define ADFR 5 +#define ADIF 4 +#define ADIE 3 +#define ADPS2 2 +#define ADPS1 1 +#define ADPS0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +#define RAMSTART 0x60 +/* Last memory addresses */ +#define RAMEND 0x1F +#define XRAMEND 0x0 +#define E2END 0x3F +#define E2PAGESIZE 2 +#define FLASHEND 0x3FF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 1 + +/* Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_RSTDISBL (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_BODEN (unsigned char)~_BV(6) +#define FUSE_BODLEVEL (unsigned char)~_BV(7) +#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_SPIEN) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x90 +#define SIGNATURE_2 0x06 + + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_PIN +#pragma GCC poison SIG_PIN_CHANGE +#pragma GCC poison SIG_OUTPUT_COMPARE1A +#pragma GCC poison SIG_OVERFLOW1 +#pragma GCC poison SIG_OVERFLOW0 +#pragma GCC poison SIG_EEPROM_READY +#pragma GCC poison SIG_COMPARATOR +#pragma GCC poison SIG_ADC + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + +#define SLEEP_MODE_IDLE (0x00<<3) +#define SLEEP_MODE_ADC (0x01<<3) +#define SLEEP_MODE_PWR_DOWN (0x02<<3) + +#endif /* _AVR_IOTN15_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iotn1604.h b/hardware/tools/avr/avr/include/avr/iotn1604.h new file mode 100644 index 0000000000000000000000000000000000000000..814d3809e26caafdbd8b05005fd74dcaeb0882ad --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn1604.h @@ -0,0 +1,4640 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn1604.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY1604_H_INCLUDED +#define _AVR_ATTINY1604_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor/DAC1 */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[51]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[7]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t reserved_1[6]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t reserved_2[7]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t ASYNCUSER11; /* Asynchronous User Ch 11 Input Selection - TCB1 */ + register8_t ASYNCUSER12; /* Asynchronous User Ch 12 Input Selection - ADC1 */ + register8_t reserved_3[3]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ + EVSYS_ASYNCCH0_AC1_OUT_gc = (0x13<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH0_AC2_OUT_gc = (0x14<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ + EVSYS_ASYNCCH1_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH1_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 11 Input Selection - TCB1 select */ +typedef enum EVSYS_ASYNCUSER11_enum +{ + EVSYS_ASYNCUSER11_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER11_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER11_t; + +/* Asynchronous User Ch 12 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER12_enum +{ + EVSYS_ASYNCUSER12_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER12_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER12_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ + EVSYS_SYNCCH0_TCB1_gc = (0x15<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous User Ch 0 - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[2]; +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_ASYNCUSER11 _SFR_MEM8(0x019D) +#define EVSYS_ASYNCUSER12 _SFR_MEM8(0x019E) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.ASYNCUSER11 bit masks and bit positions */ +#define EVSYS_ASYNCUSER11_gm 0xFF /* Asynchronous User Ch 11 Input Selection - TCB1 group mask. */ +#define EVSYS_ASYNCUSER11_gp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 group position. */ +#define EVSYS_ASYNCUSER110_bm (1<<0) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 mask. */ +#define EVSYS_ASYNCUSER110_bp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 position. */ +#define EVSYS_ASYNCUSER111_bm (1<<1) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 mask. */ +#define EVSYS_ASYNCUSER111_bp 1 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 position. */ +#define EVSYS_ASYNCUSER112_bm (1<<2) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 mask. */ +#define EVSYS_ASYNCUSER112_bp 2 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 position. */ +#define EVSYS_ASYNCUSER113_bm (1<<3) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 mask. */ +#define EVSYS_ASYNCUSER113_bp 3 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 position. */ +#define EVSYS_ASYNCUSER114_bm (1<<4) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 mask. */ +#define EVSYS_ASYNCUSER114_bp 4 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 position. */ +#define EVSYS_ASYNCUSER115_bm (1<<5) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 mask. */ +#define EVSYS_ASYNCUSER115_bp 5 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 position. */ +#define EVSYS_ASYNCUSER116_bm (1<<6) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 mask. */ +#define EVSYS_ASYNCUSER116_bp 6 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 position. */ +#define EVSYS_ASYNCUSER117_bm (1<<7) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 mask. */ +#define EVSYS_ASYNCUSER117_bp 7 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 position. */ + +/* EVSYS.ASYNCUSER12 bit masks and bit positions */ +#define EVSYS_ASYNCUSER12_gm 0xFF /* Asynchronous User Ch 12 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER12_gp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER120_bm (1<<0) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER120_bp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER121_bm (1<<1) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER121_bp 1 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER122_bm (1<<2) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER122_bp 2 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER123_bm (1<<3) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER123_bp 3 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER124_bm (1<<4) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER124_bp 4 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER125_bm (1<<5) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER125_bp 5 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER126_bm (1<<6) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER126_bp 6 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER127_bm (1<<7) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER127_bp 7 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 5 +#define PORTC_PORT_vect _VECTOR(5) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 17 +#define AC0_AC_vect _VECTOR(17) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 20 +#define ADC0_RESRDY_vect _VECTOR(20) /* */ +#define ADC0_WCOMP_vect_num 21 +#define ADC0_WCOMP_vect _VECTOR(21) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 24 +#define TWI0_TWIS_vect _VECTOR(24) /* */ +#define TWI0_TWIM_vect_num 25 +#define TWI0_TWIM_vect _VECTOR(25) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 26 +#define SPI0_INT_vect _VECTOR(26) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 27 +#define USART0_RXC_vect _VECTOR(27) /* */ +#define USART0_DRE_vect_num 28 +#define USART0_DRE_vect _VECTOR(28) /* */ +#define USART0_TXC_vect_num 29 +#define USART0_TXC_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (31 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (49152) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (49152U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3C00) +# define INTERNAL_SRAM_SIZE (1024) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3C00U) +# define INTERNAL_SRAM_SIZE (1024U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (16384) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (16384U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (16384) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (16384U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x25 + + +#endif /* #ifdef _AVR_ATTINY1604_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn1606.h b/hardware/tools/avr/avr/include/avr/iotn1606.h new file mode 100644 index 0000000000000000000000000000000000000000..5eb45dbb787969613d1a08d5cf1e26be8780d358 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn1606.h @@ -0,0 +1,4640 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn1606.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY1606_H_INCLUDED +#define _AVR_ATTINY1606_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor/DAC1 */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[51]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[7]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t reserved_1[6]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t reserved_2[7]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t ASYNCUSER11; /* Asynchronous User Ch 11 Input Selection - TCB1 */ + register8_t ASYNCUSER12; /* Asynchronous User Ch 12 Input Selection - ADC1 */ + register8_t reserved_3[3]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ + EVSYS_ASYNCCH0_AC1_OUT_gc = (0x13<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH0_AC2_OUT_gc = (0x14<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ + EVSYS_ASYNCCH1_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH1_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 11 Input Selection - TCB1 select */ +typedef enum EVSYS_ASYNCUSER11_enum +{ + EVSYS_ASYNCUSER11_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER11_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER11_t; + +/* Asynchronous User Ch 12 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER12_enum +{ + EVSYS_ASYNCUSER12_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER12_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER12_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ + EVSYS_SYNCCH0_TCB1_gc = (0x15<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous User Ch 0 - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[2]; +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_ASYNCUSER11 _SFR_MEM8(0x019D) +#define EVSYS_ASYNCUSER12 _SFR_MEM8(0x019E) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.ASYNCUSER11 bit masks and bit positions */ +#define EVSYS_ASYNCUSER11_gm 0xFF /* Asynchronous User Ch 11 Input Selection - TCB1 group mask. */ +#define EVSYS_ASYNCUSER11_gp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 group position. */ +#define EVSYS_ASYNCUSER110_bm (1<<0) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 mask. */ +#define EVSYS_ASYNCUSER110_bp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 position. */ +#define EVSYS_ASYNCUSER111_bm (1<<1) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 mask. */ +#define EVSYS_ASYNCUSER111_bp 1 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 position. */ +#define EVSYS_ASYNCUSER112_bm (1<<2) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 mask. */ +#define EVSYS_ASYNCUSER112_bp 2 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 position. */ +#define EVSYS_ASYNCUSER113_bm (1<<3) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 mask. */ +#define EVSYS_ASYNCUSER113_bp 3 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 position. */ +#define EVSYS_ASYNCUSER114_bm (1<<4) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 mask. */ +#define EVSYS_ASYNCUSER114_bp 4 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 position. */ +#define EVSYS_ASYNCUSER115_bm (1<<5) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 mask. */ +#define EVSYS_ASYNCUSER115_bp 5 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 position. */ +#define EVSYS_ASYNCUSER116_bm (1<<6) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 mask. */ +#define EVSYS_ASYNCUSER116_bp 6 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 position. */ +#define EVSYS_ASYNCUSER117_bm (1<<7) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 mask. */ +#define EVSYS_ASYNCUSER117_bp 7 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 position. */ + +/* EVSYS.ASYNCUSER12 bit masks and bit positions */ +#define EVSYS_ASYNCUSER12_gm 0xFF /* Asynchronous User Ch 12 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER12_gp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER120_bm (1<<0) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER120_bp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER121_bm (1<<1) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER121_bp 1 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER122_bm (1<<2) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER122_bp 2 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER123_bm (1<<3) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER123_bp 3 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER124_bm (1<<4) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER124_bp 4 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER125_bm (1<<5) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER125_bp 5 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER126_bm (1<<6) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER126_bp 6 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER127_bm (1<<7) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER127_bp 7 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 5 +#define PORTC_PORT_vect _VECTOR(5) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 17 +#define AC0_AC_vect _VECTOR(17) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 20 +#define ADC0_RESRDY_vect _VECTOR(20) /* */ +#define ADC0_WCOMP_vect_num 21 +#define ADC0_WCOMP_vect _VECTOR(21) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 24 +#define TWI0_TWIS_vect _VECTOR(24) /* */ +#define TWI0_TWIM_vect_num 25 +#define TWI0_TWIM_vect _VECTOR(25) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 26 +#define SPI0_INT_vect _VECTOR(26) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 27 +#define USART0_RXC_vect _VECTOR(27) /* */ +#define USART0_DRE_vect_num 28 +#define USART0_DRE_vect _VECTOR(28) /* */ +#define USART0_TXC_vect_num 29 +#define USART0_TXC_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (31 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (49152) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (49152U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3C00) +# define INTERNAL_SRAM_SIZE (1024) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3C00U) +# define INTERNAL_SRAM_SIZE (1024U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (16384) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (16384U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (16384) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (16384U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x24 + + +#endif /* #ifdef _AVR_ATTINY1606_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn1607.h b/hardware/tools/avr/avr/include/avr/iotn1607.h new file mode 100644 index 0000000000000000000000000000000000000000..7b7aae11d061eb2d3e670658de28879ad4691e5a --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn1607.h @@ -0,0 +1,4640 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn1607.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY1607_H_INCLUDED +#define _AVR_ATTINY1607_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor/DAC1 */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[51]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[7]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t reserved_1[6]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t reserved_2[7]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t ASYNCUSER11; /* Asynchronous User Ch 11 Input Selection - TCB1 */ + register8_t ASYNCUSER12; /* Asynchronous User Ch 12 Input Selection - ADC1 */ + register8_t reserved_3[3]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ + EVSYS_ASYNCCH0_AC1_OUT_gc = (0x13<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH0_AC2_OUT_gc = (0x14<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ + EVSYS_ASYNCCH1_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH1_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 11 Input Selection - TCB1 select */ +typedef enum EVSYS_ASYNCUSER11_enum +{ + EVSYS_ASYNCUSER11_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER11_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER11_t; + +/* Asynchronous User Ch 12 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER12_enum +{ + EVSYS_ASYNCUSER12_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER12_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER12_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ + EVSYS_SYNCCH0_TCB1_gc = (0x15<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous User Ch 0 - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[2]; +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_ASYNCUSER11 _SFR_MEM8(0x019D) +#define EVSYS_ASYNCUSER12 _SFR_MEM8(0x019E) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.ASYNCUSER11 bit masks and bit positions */ +#define EVSYS_ASYNCUSER11_gm 0xFF /* Asynchronous User Ch 11 Input Selection - TCB1 group mask. */ +#define EVSYS_ASYNCUSER11_gp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 group position. */ +#define EVSYS_ASYNCUSER110_bm (1<<0) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 mask. */ +#define EVSYS_ASYNCUSER110_bp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 position. */ +#define EVSYS_ASYNCUSER111_bm (1<<1) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 mask. */ +#define EVSYS_ASYNCUSER111_bp 1 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 position. */ +#define EVSYS_ASYNCUSER112_bm (1<<2) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 mask. */ +#define EVSYS_ASYNCUSER112_bp 2 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 position. */ +#define EVSYS_ASYNCUSER113_bm (1<<3) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 mask. */ +#define EVSYS_ASYNCUSER113_bp 3 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 position. */ +#define EVSYS_ASYNCUSER114_bm (1<<4) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 mask. */ +#define EVSYS_ASYNCUSER114_bp 4 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 position. */ +#define EVSYS_ASYNCUSER115_bm (1<<5) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 mask. */ +#define EVSYS_ASYNCUSER115_bp 5 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 position. */ +#define EVSYS_ASYNCUSER116_bm (1<<6) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 mask. */ +#define EVSYS_ASYNCUSER116_bp 6 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 position. */ +#define EVSYS_ASYNCUSER117_bm (1<<7) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 mask. */ +#define EVSYS_ASYNCUSER117_bp 7 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 position. */ + +/* EVSYS.ASYNCUSER12 bit masks and bit positions */ +#define EVSYS_ASYNCUSER12_gm 0xFF /* Asynchronous User Ch 12 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER12_gp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER120_bm (1<<0) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER120_bp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER121_bm (1<<1) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER121_bp 1 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER122_bm (1<<2) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER122_bp 2 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER123_bm (1<<3) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER123_bp 3 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER124_bm (1<<4) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER124_bp 4 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER125_bm (1<<5) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER125_bp 5 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER126_bm (1<<6) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER126_bp 6 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER127_bm (1<<7) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER127_bp 7 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 5 +#define PORTC_PORT_vect _VECTOR(5) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 17 +#define AC0_AC_vect _VECTOR(17) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 20 +#define ADC0_RESRDY_vect _VECTOR(20) /* */ +#define ADC0_WCOMP_vect_num 21 +#define ADC0_WCOMP_vect _VECTOR(21) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 24 +#define TWI0_TWIS_vect _VECTOR(24) /* */ +#define TWI0_TWIM_vect_num 25 +#define TWI0_TWIM_vect _VECTOR(25) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 26 +#define SPI0_INT_vect _VECTOR(26) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 27 +#define USART0_RXC_vect _VECTOR(27) /* */ +#define USART0_DRE_vect_num 28 +#define USART0_DRE_vect _VECTOR(28) /* */ +#define USART0_TXC_vect_num 29 +#define USART0_TXC_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (31 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (49152) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (49152U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3C00) +# define INTERNAL_SRAM_SIZE (1024) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3C00U) +# define INTERNAL_SRAM_SIZE (1024U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (16384) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (16384U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (16384) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (16384U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x23 + + +#endif /* #ifdef _AVR_ATTINY1607_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn1614.h b/hardware/tools/avr/avr/include/avr/iotn1614.h new file mode 100644 index 0000000000000000000000000000000000000000..cd50421b6c70314056bda30d2c5d7d225d93b030 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn1614.h @@ -0,0 +1,5517 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn1614.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY1614_H_INCLUDED +#define _AVR_ATTINY1614_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ + AC_MUXNEG_DAC_gc = (0x03<<0), /* DAC output */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_PTC_gc = (0x1B<<0), /* PTC/DAC2 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0/DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor/DAC1 */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[51]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1K cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16K cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32K cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64K cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t DATA; /* DATA Register */ + register8_t reserved_1[2]; +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t ASYNCCH2; /* Asynchronous Channel 2 Generator Selection */ + register8_t ASYNCCH3; /* Asynchronous Channel 3 Generator Selection */ + register8_t reserved_1[4]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t ASYNCUSER11; /* Asynchronous User Ch 11 Input Selection - TCB1 */ + register8_t ASYNCUSER12; /* Asynchronous User Ch 12 Input Selection - ADC1 */ + register8_t reserved_3[3]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ + EVSYS_ASYNCCH0_AC1_OUT_gc = (0x13<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH0_AC2_OUT_gc = (0x14<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ + EVSYS_ASYNCCH1_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH1_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous Channel 2 Generator Selection select */ +typedef enum EVSYS_ASYNCCH2_enum +{ + EVSYS_ASYNCCH2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH2_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH2_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH2_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH2_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH2_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH2_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH2_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH2_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH2_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH2_PORTC_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PC0 */ + EVSYS_ASYNCCH2_PORTC_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PC1 */ + EVSYS_ASYNCCH2_PORTC_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PC2 */ + EVSYS_ASYNCCH2_PORTC_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PC3 */ + EVSYS_ASYNCCH2_PORTC_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PC4 */ + EVSYS_ASYNCCH2_PORTC_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PC5 */ + EVSYS_ASYNCCH2_AC1_OUT_gc = (0x10<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH2_AC2_OUT_gc = (0x11<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH2_t; + +/* Asynchronous Channel 3 Generator Selection select */ +typedef enum EVSYS_ASYNCCH3_enum +{ + EVSYS_ASYNCCH3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH3_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH3_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH3_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH3_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter type D compare B clear */ + EVSYS_ASYNCCH3_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter type D compare A set */ + EVSYS_ASYNCCH3_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter type D compare B set */ + EVSYS_ASYNCCH3_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter type D program event */ + EVSYS_ASYNCCH3_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH3_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH3_PIT_DIV8192_gc = (0x0A<<0), /* Periodic Interrupt CLK_RTC div 8192 */ + EVSYS_ASYNCCH3_PIT_DIV4096_gc = (0x0B<<0), /* Periodic Interrupt CLK_RTC div 4096 */ + EVSYS_ASYNCCH3_PIT_DIV2048_gc = (0x0C<<0), /* Periodic Interrupt CLK_RTC div 2048 */ + EVSYS_ASYNCCH3_PIT_DIV1024_gc = (0x0D<<0), /* Periodic Interrupt CLK_RTC div 1024 */ + EVSYS_ASYNCCH3_PIT_DIV512_gc = (0x0E<<0), /* Periodic Interrupt CLK_RTC div 512 */ + EVSYS_ASYNCCH3_PIT_DIV256_gc = (0x0F<<0), /* Periodic Interrupt CLK_RTC div 256 */ + EVSYS_ASYNCCH3_PIT_DIV128_gc = (0x10<<0), /* Periodic Interrupt CLK_RTC div 128 */ + EVSYS_ASYNCCH3_PIT_DIV64_gc = (0x11<<0), /* Periodic Interrupt CLK_RTC div 64 */ + EVSYS_ASYNCCH3_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH3_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH3_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 11 Input Selection - TCB1 select */ +typedef enum EVSYS_ASYNCUSER11_enum +{ + EVSYS_ASYNCUSER11_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER11_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER11_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER11_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER11_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER11_t; + +/* Asynchronous User Ch 12 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER12_enum +{ + EVSYS_ASYNCUSER12_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER12_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER12_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER12_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER12_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER12_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ + EVSYS_SYNCCH0_TCB1_gc = (0x15<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ + EVSYS_SYNCCH1_TCB1_gc = (0x10<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB0 select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TCB1 select */ +typedef enum PORTMUX_TCB1_enum +{ + PORTMUX_TCB1_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCB1_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCB1_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_20MHZ_gc = (0x00<<5), /* 20 MHz oscillator */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External clock */ + TCD_CLKSEL_SYSCLK_gc = (0x03<<5), /* System clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Syncronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selevted clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selevted clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selevted clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selevted clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* ADC1 reference select select */ +typedef enum VREF_ADC1REFSEL_enum +{ + VREF_ADC1REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC1REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC1REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC1REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC1REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC1REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* DAC1/AC1 reference select select */ +typedef enum VREF_DAC1REFSEL_enum +{ + VREF_DAC1REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC1REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC1REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC1REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC1REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC1REFSEL_t; + +/* DAC2/AC2 reference select select */ +typedef enum VREF_DAC2REFSEL_enum +{ + VREF_DAC2REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC2REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC2REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC2REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC2REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC2REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define ADC1 (*(ADC_t *) 0x0640) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define AC1 (*(AC_t *) 0x0688) /* Analog Comparator */ +#define AC2 (*(AC_t *) 0x0690) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x06A0) /* Digital to Analog Converter */ +#define DAC1 (*(DAC_t *) 0x06A8) /* Digital to Analog Converter */ +#define DAC2 (*(DAC_t *) 0x06B0) /* Digital to Analog Converter */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0A50) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0A80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) +#define VREF_CTRLC _SFR_MEM8(0x00A2) +#define VREF_CTRLD _SFR_MEM8(0x00A3) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_ASYNCCH2 _SFR_MEM8(0x0184) +#define EVSYS_ASYNCCH3 _SFR_MEM8(0x0185) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_ASYNCUSER11 _SFR_MEM8(0x019D) +#define EVSYS_ASYNCUSER12 _SFR_MEM8(0x019E) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* ADC (ADC1) - Analog to Digital Converter */ +#define ADC1_CTRLA _SFR_MEM8(0x0640) +#define ADC1_CTRLB _SFR_MEM8(0x0641) +#define ADC1_CTRLC _SFR_MEM8(0x0642) +#define ADC1_CTRLD _SFR_MEM8(0x0643) +#define ADC1_CTRLE _SFR_MEM8(0x0644) +#define ADC1_SAMPCTRL _SFR_MEM8(0x0645) +#define ADC1_MUXPOS _SFR_MEM8(0x0646) +#define ADC1_COMMAND _SFR_MEM8(0x0648) +#define ADC1_EVCTRL _SFR_MEM8(0x0649) +#define ADC1_INTCTRL _SFR_MEM8(0x064A) +#define ADC1_INTFLAGS _SFR_MEM8(0x064B) +#define ADC1_DBGCTRL _SFR_MEM8(0x064C) +#define ADC1_TEMP _SFR_MEM8(0x064D) +#define ADC1_RES _SFR_MEM16(0x0650) +#define ADC1_RESL _SFR_MEM8(0x0650) +#define ADC1_RESH _SFR_MEM8(0x0651) +#define ADC1_WINLT _SFR_MEM16(0x0652) +#define ADC1_WINLTL _SFR_MEM8(0x0652) +#define ADC1_WINLTH _SFR_MEM8(0x0653) +#define ADC1_WINHT _SFR_MEM16(0x0654) +#define ADC1_WINHTL _SFR_MEM8(0x0654) +#define ADC1_WINHTH _SFR_MEM8(0x0655) +#define ADC1_CALIB _SFR_MEM8(0x0656) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* AC (AC1) - Analog Comparator */ +#define AC1_CTRLA _SFR_MEM8(0x0688) +#define AC1_MUXCTRLA _SFR_MEM8(0x068A) +#define AC1_INTCTRL _SFR_MEM8(0x068E) +#define AC1_STATUS _SFR_MEM8(0x068F) + + +/* AC (AC2) - Analog Comparator */ +#define AC2_CTRLA _SFR_MEM8(0x0690) +#define AC2_MUXCTRLA _SFR_MEM8(0x0692) +#define AC2_INTCTRL _SFR_MEM8(0x0696) +#define AC2_STATUS _SFR_MEM8(0x0697) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x06A0) +#define DAC0_DATA _SFR_MEM8(0x06A1) + + +/* DAC (DAC1) - Digital to Analog Converter */ +#define DAC1_CTRLA _SFR_MEM8(0x06A8) +#define DAC1_DATA _SFR_MEM8(0x06A9) + + +/* DAC (DAC2) - Digital to Analog Converter */ +#define DAC2_CTRLA _SFR_MEM8(0x06B0) +#define DAC2_DATA _SFR_MEM8(0x06B1) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0A50) +#define TCB1_CTRLB _SFR_MEM8(0x0A51) +#define TCB1_EVCTRL _SFR_MEM8(0x0A54) +#define TCB1_INTCTRL _SFR_MEM8(0x0A55) +#define TCB1_INTFLAGS _SFR_MEM8(0x0A56) +#define TCB1_STATUS _SFR_MEM8(0x0A57) +#define TCB1_DBGCTRL _SFR_MEM8(0x0A58) +#define TCB1_TEMP _SFR_MEM8(0x0A59) +#define TCB1_CNT _SFR_MEM16(0x0A5A) +#define TCB1_CNTL _SFR_MEM8(0x0A5A) +#define TCB1_CNTH _SFR_MEM8(0x0A5B) +#define TCB1_CCMP _SFR_MEM16(0x0A5C) +#define TCB1_CCMPL _SFR_MEM8(0x0A5C) +#define TCB1_CCMPH _SFR_MEM8(0x0A5D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0A80) +#define TCD0_CTRLB _SFR_MEM8(0x0A81) +#define TCD0_CTRLC _SFR_MEM8(0x0A82) +#define TCD0_CTRLD _SFR_MEM8(0x0A83) +#define TCD0_CTRLE _SFR_MEM8(0x0A84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0A88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0A89) +#define TCD0_INTCTRL _SFR_MEM8(0x0A8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0A8D) +#define TCD0_STATUS _SFR_MEM8(0x0A8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0A90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0A91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0A92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0A94) +#define TCD0_DLYVAL _SFR_MEM8(0x0A95) +#define TCD0_DITCTRL _SFR_MEM8(0x0A98) +#define TCD0_DITVAL _SFR_MEM8(0x0A99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0A9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0AA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0AA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0AA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0AA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0AA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0AA5) +#define TCD0_CMPASET _SFR_MEM16(0x0AA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0AA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0AA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0AAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0AAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0AAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0AAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0AAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0AAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0AAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0AAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0AAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH2 bit masks and bit positions */ +#define EVSYS_ASYNCCH2_gm 0xFF /* Asynchronous Channel 2 Generator Selection group mask. */ +#define EVSYS_ASYNCCH2_gp 0 /* Asynchronous Channel 2 Generator Selection group position. */ +#define EVSYS_ASYNCCH20_bm (1<<0) /* Asynchronous Channel 2 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH20_bp 0 /* Asynchronous Channel 2 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH21_bm (1<<1) /* Asynchronous Channel 2 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH21_bp 1 /* Asynchronous Channel 2 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH22_bm (1<<2) /* Asynchronous Channel 2 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH22_bp 2 /* Asynchronous Channel 2 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH23_bm (1<<3) /* Asynchronous Channel 2 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH23_bp 3 /* Asynchronous Channel 2 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH24_bm (1<<4) /* Asynchronous Channel 2 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH24_bp 4 /* Asynchronous Channel 2 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH25_bm (1<<5) /* Asynchronous Channel 2 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH25_bp 5 /* Asynchronous Channel 2 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH26_bm (1<<6) /* Asynchronous Channel 2 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH26_bp 6 /* Asynchronous Channel 2 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH27_bm (1<<7) /* Asynchronous Channel 2 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH27_bp 7 /* Asynchronous Channel 2 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH3 bit masks and bit positions */ +#define EVSYS_ASYNCCH3_gm 0xFF /* Asynchronous Channel 3 Generator Selection group mask. */ +#define EVSYS_ASYNCCH3_gp 0 /* Asynchronous Channel 3 Generator Selection group position. */ +#define EVSYS_ASYNCCH30_bm (1<<0) /* Asynchronous Channel 3 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH30_bp 0 /* Asynchronous Channel 3 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH31_bm (1<<1) /* Asynchronous Channel 3 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH31_bp 1 /* Asynchronous Channel 3 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH32_bm (1<<2) /* Asynchronous Channel 3 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH32_bp 2 /* Asynchronous Channel 3 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH33_bm (1<<3) /* Asynchronous Channel 3 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH33_bp 3 /* Asynchronous Channel 3 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH34_bm (1<<4) /* Asynchronous Channel 3 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH34_bp 4 /* Asynchronous Channel 3 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH35_bm (1<<5) /* Asynchronous Channel 3 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH35_bp 5 /* Asynchronous Channel 3 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH36_bm (1<<6) /* Asynchronous Channel 3 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH36_bp 6 /* Asynchronous Channel 3 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH37_bm (1<<7) /* Asynchronous Channel 3 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH37_bp 7 /* Asynchronous Channel 3 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.ASYNCUSER11 bit masks and bit positions */ +#define EVSYS_ASYNCUSER11_gm 0xFF /* Asynchronous User Ch 11 Input Selection - TCB1 group mask. */ +#define EVSYS_ASYNCUSER11_gp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 group position. */ +#define EVSYS_ASYNCUSER110_bm (1<<0) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 mask. */ +#define EVSYS_ASYNCUSER110_bp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 position. */ +#define EVSYS_ASYNCUSER111_bm (1<<1) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 mask. */ +#define EVSYS_ASYNCUSER111_bp 1 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 position. */ +#define EVSYS_ASYNCUSER112_bm (1<<2) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 mask. */ +#define EVSYS_ASYNCUSER112_bp 2 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 position. */ +#define EVSYS_ASYNCUSER113_bm (1<<3) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 mask. */ +#define EVSYS_ASYNCUSER113_bp 3 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 position. */ +#define EVSYS_ASYNCUSER114_bm (1<<4) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 mask. */ +#define EVSYS_ASYNCUSER114_bp 4 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 position. */ +#define EVSYS_ASYNCUSER115_bm (1<<5) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 mask. */ +#define EVSYS_ASYNCUSER115_bp 5 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 position. */ +#define EVSYS_ASYNCUSER116_bm (1<<6) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 mask. */ +#define EVSYS_ASYNCUSER116_bp 6 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 position. */ +#define EVSYS_ASYNCUSER117_bm (1<<7) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 mask. */ +#define EVSYS_ASYNCUSER117_bp 7 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 position. */ + +/* EVSYS.ASYNCUSER12 bit masks and bit positions */ +#define EVSYS_ASYNCUSER12_gm 0xFF /* Asynchronous User Ch 12 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER12_gp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER120_bm (1<<0) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER120_bp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER121_bm (1<<1) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER121_bp 1 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER122_bm (1<<2) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER122_bp 2 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER123_bm (1<<3) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER123_bp 3 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER124_bm (1<<4) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER124_bp 4 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER125_bm (1<<5) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER125_bp 5 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER126_bm (1<<6) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER126_bp 6 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER127_bm (1<<7) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER127_bp 7 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ +#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Syncronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Syncronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Syncronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Syncronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Syncronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Syncronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ +#define VREF_DAC1REFEN_bm 0x08 /* DAC1/AC1 reference enable bit mask. */ +#define VREF_DAC1REFEN_bp 3 /* DAC1/AC1 reference enable bit position. */ +#define VREF_ADC1REFEN_bm 0x10 /* ADC1 reference enable bit mask. */ +#define VREF_ADC1REFEN_bp 4 /* ADC1 reference enable bit position. */ +#define VREF_DAC2REFEN_bm 0x20 /* DAC2/AC2 reference enable bit mask. */ +#define VREF_DAC2REFEN_bp 5 /* DAC2/AC2 reference enable bit position. */ + +/* VREF.CTRLC bit masks and bit positions */ +#define VREF_DAC1REFSEL_gm 0x07 /* DAC1/AC1 reference select group mask. */ +#define VREF_DAC1REFSEL_gp 0 /* DAC1/AC1 reference select group position. */ +#define VREF_DAC1REFSEL0_bm (1<<0) /* DAC1/AC1 reference select bit 0 mask. */ +#define VREF_DAC1REFSEL0_bp 0 /* DAC1/AC1 reference select bit 0 position. */ +#define VREF_DAC1REFSEL1_bm (1<<1) /* DAC1/AC1 reference select bit 1 mask. */ +#define VREF_DAC1REFSEL1_bp 1 /* DAC1/AC1 reference select bit 1 position. */ +#define VREF_DAC1REFSEL2_bm (1<<2) /* DAC1/AC1 reference select bit 2 mask. */ +#define VREF_DAC1REFSEL2_bp 2 /* DAC1/AC1 reference select bit 2 position. */ +#define VREF_ADC1REFSEL_gm 0x70 /* ADC1 reference select group mask. */ +#define VREF_ADC1REFSEL_gp 4 /* ADC1 reference select group position. */ +#define VREF_ADC1REFSEL0_bm (1<<4) /* ADC1 reference select bit 0 mask. */ +#define VREF_ADC1REFSEL0_bp 4 /* ADC1 reference select bit 0 position. */ +#define VREF_ADC1REFSEL1_bm (1<<5) /* ADC1 reference select bit 1 mask. */ +#define VREF_ADC1REFSEL1_bp 5 /* ADC1 reference select bit 1 position. */ +#define VREF_ADC1REFSEL2_bm (1<<6) /* ADC1 reference select bit 2 mask. */ +#define VREF_ADC1REFSEL2_bp 6 /* ADC1 reference select bit 2 position. */ + +/* VREF.CTRLD bit masks and bit positions */ +#define VREF_DAC2REFSEL_gm 0x07 /* DAC2/AC2 reference select group mask. */ +#define VREF_DAC2REFSEL_gp 0 /* DAC2/AC2 reference select group position. */ +#define VREF_DAC2REFSEL0_bm (1<<0) /* DAC2/AC2 reference select bit 0 mask. */ +#define VREF_DAC2REFSEL0_bp 0 /* DAC2/AC2 reference select bit 0 position. */ +#define VREF_DAC2REFSEL1_bm (1<<1) /* DAC2/AC2 reference select bit 1 mask. */ +#define VREF_DAC2REFSEL1_bp 1 /* DAC2/AC2 reference select bit 1 position. */ +#define VREF_DAC2REFSEL2_bm (1<<2) /* DAC2/AC2 reference select bit 2 mask. */ +#define VREF_DAC2REFSEL2_bp 2 /* DAC2/AC2 reference select bit 2 position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 14 +#define TCB1_INT_vect _VECTOR(14) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 15 +#define TCD0_OVF_vect _VECTOR(15) /* */ +#define TCD0_TRIG_vect_num 16 +#define TCD0_TRIG_vect _VECTOR(16) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 17 +#define AC0_AC_vect _VECTOR(17) /* */ + +/* AC1 interrupt vectors */ +#define AC1_AC_vect_num 18 +#define AC1_AC_vect _VECTOR(18) /* */ + +/* AC2 interrupt vectors */ +#define AC2_AC_vect_num 19 +#define AC2_AC_vect _VECTOR(19) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 20 +#define ADC0_RESRDY_vect _VECTOR(20) /* */ +#define ADC0_WCOMP_vect_num 21 +#define ADC0_WCOMP_vect _VECTOR(21) /* */ + +/* ADC1 interrupt vectors */ +#define ADC1_RESRDY_vect_num 22 +#define ADC1_RESRDY_vect _VECTOR(22) /* */ +#define ADC1_WCOMP_vect_num 23 +#define ADC1_WCOMP_vect _VECTOR(23) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 24 +#define TWI0_TWIS_vect _VECTOR(24) /* */ +#define TWI0_TWIM_vect_num 25 +#define TWI0_TWIM_vect _VECTOR(25) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 26 +#define SPI0_INT_vect _VECTOR(26) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 27 +#define USART0_RXC_vect _VECTOR(27) /* */ +#define USART0_DRE_vect_num 28 +#define USART0_DRE_vect _VECTOR(28) /* */ +#define USART0_TXC_vect_num 29 +#define USART0_TXC_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (31 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (49152) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (49152U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3800) +# define INTERNAL_SRAM_SIZE (2048) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3800U) +# define INTERNAL_SRAM_SIZE (2048U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (16384) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (16384U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (16384) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (16384U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x22 + + +#endif /* #ifdef _AVR_ATTINY1614_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn1616.h b/hardware/tools/avr/avr/include/avr/iotn1616.h new file mode 100644 index 0000000000000000000000000000000000000000..b4159933a3eb10f0118e37c83dd9dbc9bddee93e --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn1616.h @@ -0,0 +1,5543 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn1616.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY1616_H_INCLUDED +#define _AVR_ATTINY1616_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ + AC_MUXNEG_DAC_gc = (0x03<<0), /* DAC output */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_PTC_gc = (0x1B<<0), /* PTC/DAC2 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0/DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor/DAC1 */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[51]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1K cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16K cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32K cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64K cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t DATA; /* DATA Register */ + register8_t reserved_1[2]; +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t ASYNCCH2; /* Asynchronous Channel 2 Generator Selection */ + register8_t ASYNCCH3; /* Asynchronous Channel 3 Generator Selection */ + register8_t reserved_1[4]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t ASYNCUSER11; /* Asynchronous User Ch 11 Input Selection - TCB1 */ + register8_t ASYNCUSER12; /* Asynchronous User Ch 12 Input Selection - ADC1 */ + register8_t reserved_3[3]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ + EVSYS_ASYNCCH0_AC1_OUT_gc = (0x13<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH0_AC2_OUT_gc = (0x14<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ + EVSYS_ASYNCCH1_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH1_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous Channel 2 Generator Selection select */ +typedef enum EVSYS_ASYNCCH2_enum +{ + EVSYS_ASYNCCH2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH2_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH2_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH2_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH2_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH2_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH2_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH2_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH2_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH2_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH2_PORTC_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PC0 */ + EVSYS_ASYNCCH2_PORTC_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PC1 */ + EVSYS_ASYNCCH2_PORTC_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PC2 */ + EVSYS_ASYNCCH2_PORTC_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PC3 */ + EVSYS_ASYNCCH2_PORTC_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PC4 */ + EVSYS_ASYNCCH2_PORTC_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PC5 */ + EVSYS_ASYNCCH2_AC1_OUT_gc = (0x10<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH2_AC2_OUT_gc = (0x11<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH2_t; + +/* Asynchronous Channel 3 Generator Selection select */ +typedef enum EVSYS_ASYNCCH3_enum +{ + EVSYS_ASYNCCH3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH3_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH3_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH3_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH3_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter type D compare B clear */ + EVSYS_ASYNCCH3_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter type D compare A set */ + EVSYS_ASYNCCH3_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter type D compare B set */ + EVSYS_ASYNCCH3_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter type D program event */ + EVSYS_ASYNCCH3_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH3_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH3_PIT_DIV8192_gc = (0x0A<<0), /* Periodic Interrupt CLK_RTC div 8192 */ + EVSYS_ASYNCCH3_PIT_DIV4096_gc = (0x0B<<0), /* Periodic Interrupt CLK_RTC div 4096 */ + EVSYS_ASYNCCH3_PIT_DIV2048_gc = (0x0C<<0), /* Periodic Interrupt CLK_RTC div 2048 */ + EVSYS_ASYNCCH3_PIT_DIV1024_gc = (0x0D<<0), /* Periodic Interrupt CLK_RTC div 1024 */ + EVSYS_ASYNCCH3_PIT_DIV512_gc = (0x0E<<0), /* Periodic Interrupt CLK_RTC div 512 */ + EVSYS_ASYNCCH3_PIT_DIV256_gc = (0x0F<<0), /* Periodic Interrupt CLK_RTC div 256 */ + EVSYS_ASYNCCH3_PIT_DIV128_gc = (0x10<<0), /* Periodic Interrupt CLK_RTC div 128 */ + EVSYS_ASYNCCH3_PIT_DIV64_gc = (0x11<<0), /* Periodic Interrupt CLK_RTC div 64 */ + EVSYS_ASYNCCH3_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH3_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH3_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 11 Input Selection - TCB1 select */ +typedef enum EVSYS_ASYNCUSER11_enum +{ + EVSYS_ASYNCUSER11_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER11_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER11_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER11_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER11_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER11_t; + +/* Asynchronous User Ch 12 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER12_enum +{ + EVSYS_ASYNCUSER12_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER12_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER12_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER12_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER12_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER12_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ + EVSYS_SYNCCH0_TCB1_gc = (0x15<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ + EVSYS_SYNCCH1_TCB1_gc = (0x10<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB0 select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TCB1 select */ +typedef enum PORTMUX_TCB1_enum +{ + PORTMUX_TCB1_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCB1_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCB1_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_20MHZ_gc = (0x00<<5), /* 20 MHz oscillator */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External clock */ + TCD_CLKSEL_SYSCLK_gc = (0x03<<5), /* System clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Syncronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selevted clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selevted clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selevted clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selevted clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* ADC1 reference select select */ +typedef enum VREF_ADC1REFSEL_enum +{ + VREF_ADC1REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC1REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC1REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC1REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC1REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC1REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* DAC1/AC1 reference select select */ +typedef enum VREF_DAC1REFSEL_enum +{ + VREF_DAC1REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC1REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC1REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC1REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC1REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC1REFSEL_t; + +/* DAC2/AC2 reference select select */ +typedef enum VREF_DAC2REFSEL_enum +{ + VREF_DAC2REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC2REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC2REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC2REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC2REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC2REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define ADC1 (*(ADC_t *) 0x0640) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define AC1 (*(AC_t *) 0x0688) /* Analog Comparator */ +#define AC2 (*(AC_t *) 0x0690) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x06A0) /* Digital to Analog Converter */ +#define DAC1 (*(DAC_t *) 0x06A8) /* Digital to Analog Converter */ +#define DAC2 (*(DAC_t *) 0x06B0) /* Digital to Analog Converter */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0A50) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0A80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) +#define VREF_CTRLC _SFR_MEM8(0x00A2) +#define VREF_CTRLD _SFR_MEM8(0x00A3) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_ASYNCCH2 _SFR_MEM8(0x0184) +#define EVSYS_ASYNCCH3 _SFR_MEM8(0x0185) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_ASYNCUSER11 _SFR_MEM8(0x019D) +#define EVSYS_ASYNCUSER12 _SFR_MEM8(0x019E) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* ADC (ADC1) - Analog to Digital Converter */ +#define ADC1_CTRLA _SFR_MEM8(0x0640) +#define ADC1_CTRLB _SFR_MEM8(0x0641) +#define ADC1_CTRLC _SFR_MEM8(0x0642) +#define ADC1_CTRLD _SFR_MEM8(0x0643) +#define ADC1_CTRLE _SFR_MEM8(0x0644) +#define ADC1_SAMPCTRL _SFR_MEM8(0x0645) +#define ADC1_MUXPOS _SFR_MEM8(0x0646) +#define ADC1_COMMAND _SFR_MEM8(0x0648) +#define ADC1_EVCTRL _SFR_MEM8(0x0649) +#define ADC1_INTCTRL _SFR_MEM8(0x064A) +#define ADC1_INTFLAGS _SFR_MEM8(0x064B) +#define ADC1_DBGCTRL _SFR_MEM8(0x064C) +#define ADC1_TEMP _SFR_MEM8(0x064D) +#define ADC1_RES _SFR_MEM16(0x0650) +#define ADC1_RESL _SFR_MEM8(0x0650) +#define ADC1_RESH _SFR_MEM8(0x0651) +#define ADC1_WINLT _SFR_MEM16(0x0652) +#define ADC1_WINLTL _SFR_MEM8(0x0652) +#define ADC1_WINLTH _SFR_MEM8(0x0653) +#define ADC1_WINHT _SFR_MEM16(0x0654) +#define ADC1_WINHTL _SFR_MEM8(0x0654) +#define ADC1_WINHTH _SFR_MEM8(0x0655) +#define ADC1_CALIB _SFR_MEM8(0x0656) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* AC (AC1) - Analog Comparator */ +#define AC1_CTRLA _SFR_MEM8(0x0688) +#define AC1_MUXCTRLA _SFR_MEM8(0x068A) +#define AC1_INTCTRL _SFR_MEM8(0x068E) +#define AC1_STATUS _SFR_MEM8(0x068F) + + +/* AC (AC2) - Analog Comparator */ +#define AC2_CTRLA _SFR_MEM8(0x0690) +#define AC2_MUXCTRLA _SFR_MEM8(0x0692) +#define AC2_INTCTRL _SFR_MEM8(0x0696) +#define AC2_STATUS _SFR_MEM8(0x0697) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x06A0) +#define DAC0_DATA _SFR_MEM8(0x06A1) + + +/* DAC (DAC1) - Digital to Analog Converter */ +#define DAC1_CTRLA _SFR_MEM8(0x06A8) +#define DAC1_DATA _SFR_MEM8(0x06A9) + + +/* DAC (DAC2) - Digital to Analog Converter */ +#define DAC2_CTRLA _SFR_MEM8(0x06B0) +#define DAC2_DATA _SFR_MEM8(0x06B1) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0A50) +#define TCB1_CTRLB _SFR_MEM8(0x0A51) +#define TCB1_EVCTRL _SFR_MEM8(0x0A54) +#define TCB1_INTCTRL _SFR_MEM8(0x0A55) +#define TCB1_INTFLAGS _SFR_MEM8(0x0A56) +#define TCB1_STATUS _SFR_MEM8(0x0A57) +#define TCB1_DBGCTRL _SFR_MEM8(0x0A58) +#define TCB1_TEMP _SFR_MEM8(0x0A59) +#define TCB1_CNT _SFR_MEM16(0x0A5A) +#define TCB1_CNTL _SFR_MEM8(0x0A5A) +#define TCB1_CNTH _SFR_MEM8(0x0A5B) +#define TCB1_CCMP _SFR_MEM16(0x0A5C) +#define TCB1_CCMPL _SFR_MEM8(0x0A5C) +#define TCB1_CCMPH _SFR_MEM8(0x0A5D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0A80) +#define TCD0_CTRLB _SFR_MEM8(0x0A81) +#define TCD0_CTRLC _SFR_MEM8(0x0A82) +#define TCD0_CTRLD _SFR_MEM8(0x0A83) +#define TCD0_CTRLE _SFR_MEM8(0x0A84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0A88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0A89) +#define TCD0_INTCTRL _SFR_MEM8(0x0A8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0A8D) +#define TCD0_STATUS _SFR_MEM8(0x0A8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0A90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0A91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0A92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0A94) +#define TCD0_DLYVAL _SFR_MEM8(0x0A95) +#define TCD0_DITCTRL _SFR_MEM8(0x0A98) +#define TCD0_DITVAL _SFR_MEM8(0x0A99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0A9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0AA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0AA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0AA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0AA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0AA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0AA5) +#define TCD0_CMPASET _SFR_MEM16(0x0AA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0AA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0AA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0AAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0AAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0AAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0AAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0AAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0AAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0AAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0AAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0AAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH2 bit masks and bit positions */ +#define EVSYS_ASYNCCH2_gm 0xFF /* Asynchronous Channel 2 Generator Selection group mask. */ +#define EVSYS_ASYNCCH2_gp 0 /* Asynchronous Channel 2 Generator Selection group position. */ +#define EVSYS_ASYNCCH20_bm (1<<0) /* Asynchronous Channel 2 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH20_bp 0 /* Asynchronous Channel 2 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH21_bm (1<<1) /* Asynchronous Channel 2 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH21_bp 1 /* Asynchronous Channel 2 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH22_bm (1<<2) /* Asynchronous Channel 2 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH22_bp 2 /* Asynchronous Channel 2 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH23_bm (1<<3) /* Asynchronous Channel 2 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH23_bp 3 /* Asynchronous Channel 2 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH24_bm (1<<4) /* Asynchronous Channel 2 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH24_bp 4 /* Asynchronous Channel 2 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH25_bm (1<<5) /* Asynchronous Channel 2 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH25_bp 5 /* Asynchronous Channel 2 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH26_bm (1<<6) /* Asynchronous Channel 2 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH26_bp 6 /* Asynchronous Channel 2 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH27_bm (1<<7) /* Asynchronous Channel 2 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH27_bp 7 /* Asynchronous Channel 2 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH3 bit masks and bit positions */ +#define EVSYS_ASYNCCH3_gm 0xFF /* Asynchronous Channel 3 Generator Selection group mask. */ +#define EVSYS_ASYNCCH3_gp 0 /* Asynchronous Channel 3 Generator Selection group position. */ +#define EVSYS_ASYNCCH30_bm (1<<0) /* Asynchronous Channel 3 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH30_bp 0 /* Asynchronous Channel 3 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH31_bm (1<<1) /* Asynchronous Channel 3 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH31_bp 1 /* Asynchronous Channel 3 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH32_bm (1<<2) /* Asynchronous Channel 3 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH32_bp 2 /* Asynchronous Channel 3 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH33_bm (1<<3) /* Asynchronous Channel 3 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH33_bp 3 /* Asynchronous Channel 3 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH34_bm (1<<4) /* Asynchronous Channel 3 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH34_bp 4 /* Asynchronous Channel 3 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH35_bm (1<<5) /* Asynchronous Channel 3 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH35_bp 5 /* Asynchronous Channel 3 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH36_bm (1<<6) /* Asynchronous Channel 3 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH36_bp 6 /* Asynchronous Channel 3 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH37_bm (1<<7) /* Asynchronous Channel 3 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH37_bp 7 /* Asynchronous Channel 3 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.ASYNCUSER11 bit masks and bit positions */ +#define EVSYS_ASYNCUSER11_gm 0xFF /* Asynchronous User Ch 11 Input Selection - TCB1 group mask. */ +#define EVSYS_ASYNCUSER11_gp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 group position. */ +#define EVSYS_ASYNCUSER110_bm (1<<0) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 mask. */ +#define EVSYS_ASYNCUSER110_bp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 position. */ +#define EVSYS_ASYNCUSER111_bm (1<<1) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 mask. */ +#define EVSYS_ASYNCUSER111_bp 1 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 position. */ +#define EVSYS_ASYNCUSER112_bm (1<<2) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 mask. */ +#define EVSYS_ASYNCUSER112_bp 2 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 position. */ +#define EVSYS_ASYNCUSER113_bm (1<<3) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 mask. */ +#define EVSYS_ASYNCUSER113_bp 3 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 position. */ +#define EVSYS_ASYNCUSER114_bm (1<<4) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 mask. */ +#define EVSYS_ASYNCUSER114_bp 4 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 position. */ +#define EVSYS_ASYNCUSER115_bm (1<<5) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 mask. */ +#define EVSYS_ASYNCUSER115_bp 5 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 position. */ +#define EVSYS_ASYNCUSER116_bm (1<<6) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 mask. */ +#define EVSYS_ASYNCUSER116_bp 6 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 position. */ +#define EVSYS_ASYNCUSER117_bm (1<<7) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 mask. */ +#define EVSYS_ASYNCUSER117_bp 7 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 position. */ + +/* EVSYS.ASYNCUSER12 bit masks and bit positions */ +#define EVSYS_ASYNCUSER12_gm 0xFF /* Asynchronous User Ch 12 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER12_gp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER120_bm (1<<0) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER120_bp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER121_bm (1<<1) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER121_bp 1 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER122_bm (1<<2) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER122_bp 2 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER123_bm (1<<3) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER123_bp 3 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER124_bm (1<<4) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER124_bp 4 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER125_bm (1<<5) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER125_bp 5 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER126_bm (1<<6) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER126_bp 6 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER127_bm (1<<7) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER127_bp 7 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ +#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Syncronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Syncronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Syncronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Syncronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Syncronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Syncronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ +#define VREF_DAC1REFEN_bm 0x08 /* DAC1/AC1 reference enable bit mask. */ +#define VREF_DAC1REFEN_bp 3 /* DAC1/AC1 reference enable bit position. */ +#define VREF_ADC1REFEN_bm 0x10 /* ADC1 reference enable bit mask. */ +#define VREF_ADC1REFEN_bp 4 /* ADC1 reference enable bit position. */ +#define VREF_DAC2REFEN_bm 0x20 /* DAC2/AC2 reference enable bit mask. */ +#define VREF_DAC2REFEN_bp 5 /* DAC2/AC2 reference enable bit position. */ + +/* VREF.CTRLC bit masks and bit positions */ +#define VREF_DAC1REFSEL_gm 0x07 /* DAC1/AC1 reference select group mask. */ +#define VREF_DAC1REFSEL_gp 0 /* DAC1/AC1 reference select group position. */ +#define VREF_DAC1REFSEL0_bm (1<<0) /* DAC1/AC1 reference select bit 0 mask. */ +#define VREF_DAC1REFSEL0_bp 0 /* DAC1/AC1 reference select bit 0 position. */ +#define VREF_DAC1REFSEL1_bm (1<<1) /* DAC1/AC1 reference select bit 1 mask. */ +#define VREF_DAC1REFSEL1_bp 1 /* DAC1/AC1 reference select bit 1 position. */ +#define VREF_DAC1REFSEL2_bm (1<<2) /* DAC1/AC1 reference select bit 2 mask. */ +#define VREF_DAC1REFSEL2_bp 2 /* DAC1/AC1 reference select bit 2 position. */ +#define VREF_ADC1REFSEL_gm 0x70 /* ADC1 reference select group mask. */ +#define VREF_ADC1REFSEL_gp 4 /* ADC1 reference select group position. */ +#define VREF_ADC1REFSEL0_bm (1<<4) /* ADC1 reference select bit 0 mask. */ +#define VREF_ADC1REFSEL0_bp 4 /* ADC1 reference select bit 0 position. */ +#define VREF_ADC1REFSEL1_bm (1<<5) /* ADC1 reference select bit 1 mask. */ +#define VREF_ADC1REFSEL1_bp 5 /* ADC1 reference select bit 1 position. */ +#define VREF_ADC1REFSEL2_bm (1<<6) /* ADC1 reference select bit 2 mask. */ +#define VREF_ADC1REFSEL2_bp 6 /* ADC1 reference select bit 2 position. */ + +/* VREF.CTRLD bit masks and bit positions */ +#define VREF_DAC2REFSEL_gm 0x07 /* DAC2/AC2 reference select group mask. */ +#define VREF_DAC2REFSEL_gp 0 /* DAC2/AC2 reference select group position. */ +#define VREF_DAC2REFSEL0_bm (1<<0) /* DAC2/AC2 reference select bit 0 mask. */ +#define VREF_DAC2REFSEL0_bp 0 /* DAC2/AC2 reference select bit 0 position. */ +#define VREF_DAC2REFSEL1_bm (1<<1) /* DAC2/AC2 reference select bit 1 mask. */ +#define VREF_DAC2REFSEL1_bp 1 /* DAC2/AC2 reference select bit 1 position. */ +#define VREF_DAC2REFSEL2_bm (1<<2) /* DAC2/AC2 reference select bit 2 mask. */ +#define VREF_DAC2REFSEL2_bp 2 /* DAC2/AC2 reference select bit 2 position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 5 +#define PORTC_PORT_vect _VECTOR(5) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 14 +#define TCB1_INT_vect _VECTOR(14) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 15 +#define TCD0_OVF_vect _VECTOR(15) /* */ +#define TCD0_TRIG_vect_num 16 +#define TCD0_TRIG_vect _VECTOR(16) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 17 +#define AC0_AC_vect _VECTOR(17) /* */ + +/* AC1 interrupt vectors */ +#define AC1_AC_vect_num 18 +#define AC1_AC_vect _VECTOR(18) /* */ + +/* AC2 interrupt vectors */ +#define AC2_AC_vect_num 19 +#define AC2_AC_vect _VECTOR(19) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 20 +#define ADC0_RESRDY_vect _VECTOR(20) /* */ +#define ADC0_WCOMP_vect_num 21 +#define ADC0_WCOMP_vect _VECTOR(21) /* */ + +/* ADC1 interrupt vectors */ +#define ADC1_RESRDY_vect_num 22 +#define ADC1_RESRDY_vect _VECTOR(22) /* */ +#define ADC1_WCOMP_vect_num 23 +#define ADC1_WCOMP_vect _VECTOR(23) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 24 +#define TWI0_TWIS_vect _VECTOR(24) /* */ +#define TWI0_TWIM_vect_num 25 +#define TWI0_TWIM_vect _VECTOR(25) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 26 +#define SPI0_INT_vect _VECTOR(26) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 27 +#define USART0_RXC_vect _VECTOR(27) /* */ +#define USART0_DRE_vect_num 28 +#define USART0_DRE_vect _VECTOR(28) /* */ +#define USART0_TXC_vect_num 29 +#define USART0_TXC_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (31 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (49152) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (49152U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3800) +# define INTERNAL_SRAM_SIZE (2048) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3800U) +# define INTERNAL_SRAM_SIZE (2048U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (16384) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (16384U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (16384) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (16384U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x21 + + +#endif /* #ifdef _AVR_ATTINY1616_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn1617.h b/hardware/tools/avr/avr/include/avr/iotn1617.h new file mode 100644 index 0000000000000000000000000000000000000000..fd3e6e4ed9d660a20d5f6b735ecdf3c2f179d8b4 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn1617.h @@ -0,0 +1,5543 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn1617.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY1617_H_INCLUDED +#define _AVR_ATTINY1617_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ + AC_MUXNEG_DAC_gc = (0x03<<0), /* DAC output */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_PTC_gc = (0x1B<<0), /* PTC/DAC2 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0/DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor/DAC1 */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[51]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1K cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16K cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32K cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64K cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t DATA; /* DATA Register */ + register8_t reserved_1[2]; +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t ASYNCCH2; /* Asynchronous Channel 2 Generator Selection */ + register8_t ASYNCCH3; /* Asynchronous Channel 3 Generator Selection */ + register8_t reserved_1[4]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t ASYNCUSER11; /* Asynchronous User Ch 11 Input Selection - TCB1 */ + register8_t ASYNCUSER12; /* Asynchronous User Ch 12 Input Selection - ADC1 */ + register8_t reserved_3[3]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ + EVSYS_ASYNCCH0_AC1_OUT_gc = (0x13<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH0_AC2_OUT_gc = (0x14<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ + EVSYS_ASYNCCH1_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH1_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous Channel 2 Generator Selection select */ +typedef enum EVSYS_ASYNCCH2_enum +{ + EVSYS_ASYNCCH2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH2_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH2_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH2_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH2_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH2_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH2_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH2_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH2_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH2_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH2_PORTC_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PC0 */ + EVSYS_ASYNCCH2_PORTC_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PC1 */ + EVSYS_ASYNCCH2_PORTC_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PC2 */ + EVSYS_ASYNCCH2_PORTC_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PC3 */ + EVSYS_ASYNCCH2_PORTC_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PC4 */ + EVSYS_ASYNCCH2_PORTC_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PC5 */ + EVSYS_ASYNCCH2_AC1_OUT_gc = (0x10<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH2_AC2_OUT_gc = (0x11<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH2_t; + +/* Asynchronous Channel 3 Generator Selection select */ +typedef enum EVSYS_ASYNCCH3_enum +{ + EVSYS_ASYNCCH3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH3_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH3_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH3_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH3_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter type D compare B clear */ + EVSYS_ASYNCCH3_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter type D compare A set */ + EVSYS_ASYNCCH3_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter type D compare B set */ + EVSYS_ASYNCCH3_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter type D program event */ + EVSYS_ASYNCCH3_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH3_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH3_PIT_DIV8192_gc = (0x0A<<0), /* Periodic Interrupt CLK_RTC div 8192 */ + EVSYS_ASYNCCH3_PIT_DIV4096_gc = (0x0B<<0), /* Periodic Interrupt CLK_RTC div 4096 */ + EVSYS_ASYNCCH3_PIT_DIV2048_gc = (0x0C<<0), /* Periodic Interrupt CLK_RTC div 2048 */ + EVSYS_ASYNCCH3_PIT_DIV1024_gc = (0x0D<<0), /* Periodic Interrupt CLK_RTC div 1024 */ + EVSYS_ASYNCCH3_PIT_DIV512_gc = (0x0E<<0), /* Periodic Interrupt CLK_RTC div 512 */ + EVSYS_ASYNCCH3_PIT_DIV256_gc = (0x0F<<0), /* Periodic Interrupt CLK_RTC div 256 */ + EVSYS_ASYNCCH3_PIT_DIV128_gc = (0x10<<0), /* Periodic Interrupt CLK_RTC div 128 */ + EVSYS_ASYNCCH3_PIT_DIV64_gc = (0x11<<0), /* Periodic Interrupt CLK_RTC div 64 */ + EVSYS_ASYNCCH3_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH3_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH3_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 11 Input Selection - TCB1 select */ +typedef enum EVSYS_ASYNCUSER11_enum +{ + EVSYS_ASYNCUSER11_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER11_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER11_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER11_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER11_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER11_t; + +/* Asynchronous User Ch 12 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER12_enum +{ + EVSYS_ASYNCUSER12_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER12_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER12_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER12_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER12_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER12_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ + EVSYS_SYNCCH0_TCB1_gc = (0x15<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ + EVSYS_SYNCCH1_TCB1_gc = (0x10<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB0 select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TCB1 select */ +typedef enum PORTMUX_TCB1_enum +{ + PORTMUX_TCB1_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCB1_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCB1_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_20MHZ_gc = (0x00<<5), /* 20 MHz oscillator */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External clock */ + TCD_CLKSEL_SYSCLK_gc = (0x03<<5), /* System clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Syncronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selevted clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selevted clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selevted clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selevted clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* ADC1 reference select select */ +typedef enum VREF_ADC1REFSEL_enum +{ + VREF_ADC1REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC1REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC1REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC1REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC1REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC1REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* DAC1/AC1 reference select select */ +typedef enum VREF_DAC1REFSEL_enum +{ + VREF_DAC1REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC1REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC1REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC1REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC1REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC1REFSEL_t; + +/* DAC2/AC2 reference select select */ +typedef enum VREF_DAC2REFSEL_enum +{ + VREF_DAC2REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC2REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC2REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC2REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC2REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC2REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define ADC1 (*(ADC_t *) 0x0640) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define AC1 (*(AC_t *) 0x0688) /* Analog Comparator */ +#define AC2 (*(AC_t *) 0x0690) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x06A0) /* Digital to Analog Converter */ +#define DAC1 (*(DAC_t *) 0x06A8) /* Digital to Analog Converter */ +#define DAC2 (*(DAC_t *) 0x06B0) /* Digital to Analog Converter */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0A50) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0A80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) +#define VREF_CTRLC _SFR_MEM8(0x00A2) +#define VREF_CTRLD _SFR_MEM8(0x00A3) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_ASYNCCH2 _SFR_MEM8(0x0184) +#define EVSYS_ASYNCCH3 _SFR_MEM8(0x0185) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_ASYNCUSER11 _SFR_MEM8(0x019D) +#define EVSYS_ASYNCUSER12 _SFR_MEM8(0x019E) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* ADC (ADC1) - Analog to Digital Converter */ +#define ADC1_CTRLA _SFR_MEM8(0x0640) +#define ADC1_CTRLB _SFR_MEM8(0x0641) +#define ADC1_CTRLC _SFR_MEM8(0x0642) +#define ADC1_CTRLD _SFR_MEM8(0x0643) +#define ADC1_CTRLE _SFR_MEM8(0x0644) +#define ADC1_SAMPCTRL _SFR_MEM8(0x0645) +#define ADC1_MUXPOS _SFR_MEM8(0x0646) +#define ADC1_COMMAND _SFR_MEM8(0x0648) +#define ADC1_EVCTRL _SFR_MEM8(0x0649) +#define ADC1_INTCTRL _SFR_MEM8(0x064A) +#define ADC1_INTFLAGS _SFR_MEM8(0x064B) +#define ADC1_DBGCTRL _SFR_MEM8(0x064C) +#define ADC1_TEMP _SFR_MEM8(0x064D) +#define ADC1_RES _SFR_MEM16(0x0650) +#define ADC1_RESL _SFR_MEM8(0x0650) +#define ADC1_RESH _SFR_MEM8(0x0651) +#define ADC1_WINLT _SFR_MEM16(0x0652) +#define ADC1_WINLTL _SFR_MEM8(0x0652) +#define ADC1_WINLTH _SFR_MEM8(0x0653) +#define ADC1_WINHT _SFR_MEM16(0x0654) +#define ADC1_WINHTL _SFR_MEM8(0x0654) +#define ADC1_WINHTH _SFR_MEM8(0x0655) +#define ADC1_CALIB _SFR_MEM8(0x0656) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* AC (AC1) - Analog Comparator */ +#define AC1_CTRLA _SFR_MEM8(0x0688) +#define AC1_MUXCTRLA _SFR_MEM8(0x068A) +#define AC1_INTCTRL _SFR_MEM8(0x068E) +#define AC1_STATUS _SFR_MEM8(0x068F) + + +/* AC (AC2) - Analog Comparator */ +#define AC2_CTRLA _SFR_MEM8(0x0690) +#define AC2_MUXCTRLA _SFR_MEM8(0x0692) +#define AC2_INTCTRL _SFR_MEM8(0x0696) +#define AC2_STATUS _SFR_MEM8(0x0697) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x06A0) +#define DAC0_DATA _SFR_MEM8(0x06A1) + + +/* DAC (DAC1) - Digital to Analog Converter */ +#define DAC1_CTRLA _SFR_MEM8(0x06A8) +#define DAC1_DATA _SFR_MEM8(0x06A9) + + +/* DAC (DAC2) - Digital to Analog Converter */ +#define DAC2_CTRLA _SFR_MEM8(0x06B0) +#define DAC2_DATA _SFR_MEM8(0x06B1) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0A50) +#define TCB1_CTRLB _SFR_MEM8(0x0A51) +#define TCB1_EVCTRL _SFR_MEM8(0x0A54) +#define TCB1_INTCTRL _SFR_MEM8(0x0A55) +#define TCB1_INTFLAGS _SFR_MEM8(0x0A56) +#define TCB1_STATUS _SFR_MEM8(0x0A57) +#define TCB1_DBGCTRL _SFR_MEM8(0x0A58) +#define TCB1_TEMP _SFR_MEM8(0x0A59) +#define TCB1_CNT _SFR_MEM16(0x0A5A) +#define TCB1_CNTL _SFR_MEM8(0x0A5A) +#define TCB1_CNTH _SFR_MEM8(0x0A5B) +#define TCB1_CCMP _SFR_MEM16(0x0A5C) +#define TCB1_CCMPL _SFR_MEM8(0x0A5C) +#define TCB1_CCMPH _SFR_MEM8(0x0A5D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0A80) +#define TCD0_CTRLB _SFR_MEM8(0x0A81) +#define TCD0_CTRLC _SFR_MEM8(0x0A82) +#define TCD0_CTRLD _SFR_MEM8(0x0A83) +#define TCD0_CTRLE _SFR_MEM8(0x0A84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0A88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0A89) +#define TCD0_INTCTRL _SFR_MEM8(0x0A8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0A8D) +#define TCD0_STATUS _SFR_MEM8(0x0A8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0A90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0A91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0A92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0A94) +#define TCD0_DLYVAL _SFR_MEM8(0x0A95) +#define TCD0_DITCTRL _SFR_MEM8(0x0A98) +#define TCD0_DITVAL _SFR_MEM8(0x0A99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0A9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0AA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0AA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0AA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0AA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0AA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0AA5) +#define TCD0_CMPASET _SFR_MEM16(0x0AA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0AA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0AA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0AAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0AAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0AAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0AAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0AAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0AAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0AAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0AAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0AAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH2 bit masks and bit positions */ +#define EVSYS_ASYNCCH2_gm 0xFF /* Asynchronous Channel 2 Generator Selection group mask. */ +#define EVSYS_ASYNCCH2_gp 0 /* Asynchronous Channel 2 Generator Selection group position. */ +#define EVSYS_ASYNCCH20_bm (1<<0) /* Asynchronous Channel 2 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH20_bp 0 /* Asynchronous Channel 2 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH21_bm (1<<1) /* Asynchronous Channel 2 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH21_bp 1 /* Asynchronous Channel 2 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH22_bm (1<<2) /* Asynchronous Channel 2 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH22_bp 2 /* Asynchronous Channel 2 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH23_bm (1<<3) /* Asynchronous Channel 2 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH23_bp 3 /* Asynchronous Channel 2 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH24_bm (1<<4) /* Asynchronous Channel 2 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH24_bp 4 /* Asynchronous Channel 2 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH25_bm (1<<5) /* Asynchronous Channel 2 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH25_bp 5 /* Asynchronous Channel 2 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH26_bm (1<<6) /* Asynchronous Channel 2 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH26_bp 6 /* Asynchronous Channel 2 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH27_bm (1<<7) /* Asynchronous Channel 2 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH27_bp 7 /* Asynchronous Channel 2 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH3 bit masks and bit positions */ +#define EVSYS_ASYNCCH3_gm 0xFF /* Asynchronous Channel 3 Generator Selection group mask. */ +#define EVSYS_ASYNCCH3_gp 0 /* Asynchronous Channel 3 Generator Selection group position. */ +#define EVSYS_ASYNCCH30_bm (1<<0) /* Asynchronous Channel 3 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH30_bp 0 /* Asynchronous Channel 3 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH31_bm (1<<1) /* Asynchronous Channel 3 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH31_bp 1 /* Asynchronous Channel 3 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH32_bm (1<<2) /* Asynchronous Channel 3 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH32_bp 2 /* Asynchronous Channel 3 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH33_bm (1<<3) /* Asynchronous Channel 3 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH33_bp 3 /* Asynchronous Channel 3 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH34_bm (1<<4) /* Asynchronous Channel 3 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH34_bp 4 /* Asynchronous Channel 3 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH35_bm (1<<5) /* Asynchronous Channel 3 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH35_bp 5 /* Asynchronous Channel 3 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH36_bm (1<<6) /* Asynchronous Channel 3 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH36_bp 6 /* Asynchronous Channel 3 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH37_bm (1<<7) /* Asynchronous Channel 3 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH37_bp 7 /* Asynchronous Channel 3 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.ASYNCUSER11 bit masks and bit positions */ +#define EVSYS_ASYNCUSER11_gm 0xFF /* Asynchronous User Ch 11 Input Selection - TCB1 group mask. */ +#define EVSYS_ASYNCUSER11_gp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 group position. */ +#define EVSYS_ASYNCUSER110_bm (1<<0) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 mask. */ +#define EVSYS_ASYNCUSER110_bp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 position. */ +#define EVSYS_ASYNCUSER111_bm (1<<1) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 mask. */ +#define EVSYS_ASYNCUSER111_bp 1 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 position. */ +#define EVSYS_ASYNCUSER112_bm (1<<2) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 mask. */ +#define EVSYS_ASYNCUSER112_bp 2 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 position. */ +#define EVSYS_ASYNCUSER113_bm (1<<3) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 mask. */ +#define EVSYS_ASYNCUSER113_bp 3 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 position. */ +#define EVSYS_ASYNCUSER114_bm (1<<4) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 mask. */ +#define EVSYS_ASYNCUSER114_bp 4 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 position. */ +#define EVSYS_ASYNCUSER115_bm (1<<5) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 mask. */ +#define EVSYS_ASYNCUSER115_bp 5 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 position. */ +#define EVSYS_ASYNCUSER116_bm (1<<6) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 mask. */ +#define EVSYS_ASYNCUSER116_bp 6 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 position. */ +#define EVSYS_ASYNCUSER117_bm (1<<7) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 mask. */ +#define EVSYS_ASYNCUSER117_bp 7 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 position. */ + +/* EVSYS.ASYNCUSER12 bit masks and bit positions */ +#define EVSYS_ASYNCUSER12_gm 0xFF /* Asynchronous User Ch 12 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER12_gp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER120_bm (1<<0) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER120_bp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER121_bm (1<<1) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER121_bp 1 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER122_bm (1<<2) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER122_bp 2 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER123_bm (1<<3) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER123_bp 3 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER124_bm (1<<4) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER124_bp 4 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER125_bm (1<<5) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER125_bp 5 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER126_bm (1<<6) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER126_bp 6 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER127_bm (1<<7) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER127_bp 7 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ +#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Syncronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Syncronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Syncronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Syncronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Syncronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Syncronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ +#define VREF_DAC1REFEN_bm 0x08 /* DAC1/AC1 reference enable bit mask. */ +#define VREF_DAC1REFEN_bp 3 /* DAC1/AC1 reference enable bit position. */ +#define VREF_ADC1REFEN_bm 0x10 /* ADC1 reference enable bit mask. */ +#define VREF_ADC1REFEN_bp 4 /* ADC1 reference enable bit position. */ +#define VREF_DAC2REFEN_bm 0x20 /* DAC2/AC2 reference enable bit mask. */ +#define VREF_DAC2REFEN_bp 5 /* DAC2/AC2 reference enable bit position. */ + +/* VREF.CTRLC bit masks and bit positions */ +#define VREF_DAC1REFSEL_gm 0x07 /* DAC1/AC1 reference select group mask. */ +#define VREF_DAC1REFSEL_gp 0 /* DAC1/AC1 reference select group position. */ +#define VREF_DAC1REFSEL0_bm (1<<0) /* DAC1/AC1 reference select bit 0 mask. */ +#define VREF_DAC1REFSEL0_bp 0 /* DAC1/AC1 reference select bit 0 position. */ +#define VREF_DAC1REFSEL1_bm (1<<1) /* DAC1/AC1 reference select bit 1 mask. */ +#define VREF_DAC1REFSEL1_bp 1 /* DAC1/AC1 reference select bit 1 position. */ +#define VREF_DAC1REFSEL2_bm (1<<2) /* DAC1/AC1 reference select bit 2 mask. */ +#define VREF_DAC1REFSEL2_bp 2 /* DAC1/AC1 reference select bit 2 position. */ +#define VREF_ADC1REFSEL_gm 0x70 /* ADC1 reference select group mask. */ +#define VREF_ADC1REFSEL_gp 4 /* ADC1 reference select group position. */ +#define VREF_ADC1REFSEL0_bm (1<<4) /* ADC1 reference select bit 0 mask. */ +#define VREF_ADC1REFSEL0_bp 4 /* ADC1 reference select bit 0 position. */ +#define VREF_ADC1REFSEL1_bm (1<<5) /* ADC1 reference select bit 1 mask. */ +#define VREF_ADC1REFSEL1_bp 5 /* ADC1 reference select bit 1 position. */ +#define VREF_ADC1REFSEL2_bm (1<<6) /* ADC1 reference select bit 2 mask. */ +#define VREF_ADC1REFSEL2_bp 6 /* ADC1 reference select bit 2 position. */ + +/* VREF.CTRLD bit masks and bit positions */ +#define VREF_DAC2REFSEL_gm 0x07 /* DAC2/AC2 reference select group mask. */ +#define VREF_DAC2REFSEL_gp 0 /* DAC2/AC2 reference select group position. */ +#define VREF_DAC2REFSEL0_bm (1<<0) /* DAC2/AC2 reference select bit 0 mask. */ +#define VREF_DAC2REFSEL0_bp 0 /* DAC2/AC2 reference select bit 0 position. */ +#define VREF_DAC2REFSEL1_bm (1<<1) /* DAC2/AC2 reference select bit 1 mask. */ +#define VREF_DAC2REFSEL1_bp 1 /* DAC2/AC2 reference select bit 1 position. */ +#define VREF_DAC2REFSEL2_bm (1<<2) /* DAC2/AC2 reference select bit 2 mask. */ +#define VREF_DAC2REFSEL2_bp 2 /* DAC2/AC2 reference select bit 2 position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 5 +#define PORTC_PORT_vect _VECTOR(5) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 14 +#define TCB1_INT_vect _VECTOR(14) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 15 +#define TCD0_OVF_vect _VECTOR(15) /* */ +#define TCD0_TRIG_vect_num 16 +#define TCD0_TRIG_vect _VECTOR(16) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 17 +#define AC0_AC_vect _VECTOR(17) /* */ + +/* AC1 interrupt vectors */ +#define AC1_AC_vect_num 18 +#define AC1_AC_vect _VECTOR(18) /* */ + +/* AC2 interrupt vectors */ +#define AC2_AC_vect_num 19 +#define AC2_AC_vect _VECTOR(19) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 20 +#define ADC0_RESRDY_vect _VECTOR(20) /* */ +#define ADC0_WCOMP_vect_num 21 +#define ADC0_WCOMP_vect _VECTOR(21) /* */ + +/* ADC1 interrupt vectors */ +#define ADC1_RESRDY_vect_num 22 +#define ADC1_RESRDY_vect _VECTOR(22) /* */ +#define ADC1_WCOMP_vect_num 23 +#define ADC1_WCOMP_vect _VECTOR(23) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 24 +#define TWI0_TWIS_vect _VECTOR(24) /* */ +#define TWI0_TWIM_vect_num 25 +#define TWI0_TWIM_vect _VECTOR(25) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 26 +#define SPI0_INT_vect _VECTOR(26) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 27 +#define USART0_RXC_vect _VECTOR(27) /* */ +#define USART0_DRE_vect_num 28 +#define USART0_DRE_vect _VECTOR(28) /* */ +#define USART0_TXC_vect_num 29 +#define USART0_TXC_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (31 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (49152) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (49152U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3800) +# define INTERNAL_SRAM_SIZE (2048) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3800U) +# define INTERNAL_SRAM_SIZE (2048U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (16384) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (16384U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (16384) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (16384U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x20 + + +#endif /* #ifdef _AVR_ATTINY1617_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn1624.h b/hardware/tools/avr/avr/include/avr/iotn1624.h new file mode 100644 index 0000000000000000000000000000000000000000..a58cbe467112eef054c50cee1446fbeb4933d9f9 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn1624.h @@ -0,0 +1,5497 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn1624.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY1624_H_INCLUDED +#define _AVR_ATTINY1624_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPZ _SFR_MEM8(0x003B) /* Extended Z-pointer Register */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[1]; + register8_t DACREF; /* Referance scale control */ + register8_t reserved_3[1]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Both Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_PIN2_gc = (0x02<<0), /* Negative Pin 2 */ + AC_MUXNEG_DACREF_gc = (0x03<<0), /* DAC Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status register */ + register8_t DBGCTRL; /* Debug Control */ + register8_t CTRLE; /* Control E */ + register8_t CTRLF; /* Control F */ + register8_t COMMAND; /* Command register */ + register8_t PGACTRL; /* PGA Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t MUXNEG; /* Negative mux input */ + register8_t reserved_1[2]; + _DWORDREGISTER(RESULT); /* Result */ + _WORDREGISTER(SAMPLE); /* Sample */ + register8_t reserved_2[2]; + register8_t TEMP0; /* Temporary Data 0 */ + register8_t TEMP1; /* Temporary Data 1 */ + register8_t TEMP2; /* Temporary Data 2 */ + register8_t reserved_3[1]; + _WORDREGISTER(WINLT); /* Window Low Threshold */ + _WORDREGISTER(WINHT); /* Window High Threshold */ + register8_t reserved_4[32]; +} ADC_t; + +/* ADC PGA Sample Duration select */ +typedef enum ADC_ADCPGASAMPDUR_enum +{ + ADC_ADCPGASAMPDUR_6CLK_gc = (0x00<<1), /* 6 ADC cycles */ + ADC_ADCPGASAMPDUR_15CLK_gc = (0x01<<1), /* 15 ADC cycles */ + ADC_ADCPGASAMPDUR_20CLK_gc = (0x02<<1), /* 20 ADC cycles */ + ADC_ADCPGASAMPDUR_32CLK_gc = (0x03<<1), /* 32 ADC cycles */ +} ADC_ADCPGASAMPDUR_t; + +/* Gain select */ +typedef enum ADC_GAIN_enum +{ + ADC_GAIN_1X_gc = (0x00<<5), /* 1X Gain */ + ADC_GAIN_2X_gc = (0x01<<5), /* 2X Gain */ + ADC_GAIN_4X_gc = (0x02<<5), /* 4X Gain */ + ADC_GAIN_8X_gc = (0x03<<5), /* 8X Gain */ + ADC_GAIN_16X_gc = (0x04<<5), /* 16X Gain */ +} ADC_GAIN_t; + +/* Mode select */ +typedef enum ADC_MODE_enum +{ + ADC_MODE_SINGLE_8BIT_gc = (0x00<<4), /* Single Conversion 8-bit */ + ADC_MODE_SINGLE_12BIT_gc = (0x01<<4), /* Single Conversion 12-bit */ + ADC_MODE_SERIES_gc = (0x02<<4), /* Series Accumulation */ + ADC_MODE_SERIES_SCALING_gc = (0x03<<4), /* Series Accumulation with Scaling */ + ADC_MODE_BURST_gc = (0x04<<4), /* Burst Accumulation */ + ADC_MODE_BURST_SCALING_gc = (0x05<<4), /* Burst Accumulation with Scaling */ +} ADC_MODE_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXNEG_enum +{ + ADC_MUXNEG_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXNEG_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXNEG_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXNEG_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXNEG_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXNEG_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXNEG_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXNEG_GND_gc = (0x30<<0), /* Ground */ + ADC_MUXNEG_VDDDIV10_gc = (0x31<<0), /* VDD/10 */ + ADC_MUXNEG_DAC_gc = (0x33<<0), /* DAC */ +} ADC_MUXNEG_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ + ADC_MUXPOS_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ + ADC_MUXPOS_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ + ADC_MUXPOS_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ + ADC_MUXPOS_GND_gc = (0x30<<0), /* Ground */ + ADC_MUXPOS_VDDDIV10_gc = (0x31<<0), /* VDD/10 */ + ADC_MUXPOS_TEMPSENSE_gc = (0x32<<0), /* Temperature sensor */ + ADC_MUXPOS_DAC_gc = (0x33<<0), /* DAC */ +} ADC_MUXPOS_t; + +/* PGA BIAS Select select */ +typedef enum ADC_PGABIASSEL_enum +{ + ADC_PGABIASSEL_1X_gc = (0x00<<3), /* 1x BIAS curren */ + ADC_PGABIASSEL_3_4X_gc = (0x01<<3), /* 3/4x BIAS current */ + ADC_PGABIASSEL_1_2X_gc = (0x02<<3), /* 1/2x BIAS current */ + ADC_PGABIASSEL_1_4X_gc = (0x03<<3), /* 1/4x BIAS current */ +} ADC_PGABIASSEL_t; + +/* Prescaler Value select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* System clock divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* System clock divided by 4 */ + ADC_PRESC_DIV6_gc = (0x02<<0), /* System clock divided by 6 */ + ADC_PRESC_DIV8_gc = (0x03<<0), /* System clock divided by 8 */ + ADC_PRESC_DIV10_gc = (0x04<<0), /* System clock divided by 10 */ + ADC_PRESC_DIV12_gc = (0x05<<0), /* System clock divided by 12 */ + ADC_PRESC_DIV14_gc = (0x06<<0), /* System clock divided by 14 */ + ADC_PRESC_DIV16_gc = (0x07<<0), /* System clock divided by 16 */ + ADC_PRESC_DIV20_gc = (0x08<<0), /* System clock divided by 20 */ + ADC_PRESC_DIV24_gc = (0x09<<0), /* System clock divided by 24 */ + ADC_PRESC_DIV28_gc = (0x0A<<0), /* System clock divided by 28 */ + ADC_PRESC_DIV32_gc = (0x0B<<0), /* System clock divided by 32 */ + ADC_PRESC_DIV40_gc = (0x0C<<0), /* System clock divided by 40 */ + ADC_PRESC_DIV48_gc = (0x0D<<0), /* System clock divided by 48 */ + ADC_PRESC_DIV56_gc = (0x0E<<0), /* System clock divided by 56 */ + ADC_PRESC_DIV64_gc = (0x0F<<0), /* System clock divided by 64 */ +} ADC_PRESC_t; + +/* Reference select select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_VDD_gc = (0x00<<0), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<0), /* External Reference */ + ADC_REFSEL_1024MV_gc = (0x04<<0), /* Internal 1.024V Reference */ + ADC_REFSEL_2048MV_gc = (0x05<<0), /* Internal 2.048V Reference */ + ADC_REFSEL_2500MV_gc = (0x06<<0), /* Internal 2.5V Reference */ + ADC_REFSEL_4096MV_gc = (0x07<<0), /* Internal 4.096V Reference */ +} ADC_REFSEL_t; + +/* Sample numbers select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_NONE_gc = (0x00<<0), /* No accumulation */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* 2 samples accumulation */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* 4 samples accumulation */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* 8 samples accumulation */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* 16 samples accumulation */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* 32 samples accumulation */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* 64 samples accumulation */ + ADC_SAMPNUM_ACC128_gc = (0x07<<0), /* 128 samples accumulation */ + ADC_SAMPNUM_ACC256_gc = (0x08<<0), /* 256 samples accumulation */ + ADC_SAMPNUM_ACC512_gc = (0x09<<0), /* 512 samples accumulation */ + ADC_SAMPNUM_ACC1024_gc = (0x0A<<0), /* 1024 samples accumulation */ +} ADC_SAMPNUM_t; + +/* Start command select */ +typedef enum ADC_START_enum +{ + ADC_START_STOP_gc = (0x00<<0), /* Stop an ongoing conversion */ + ADC_START_IMMEDIATE_gc = (0x01<<0), /* Start immediately */ + ADC_START_MUXPOS_WRITE_gc = (0x02<<0), /* Start on MUXPOS write */ + ADC_START_MUXNEG_WRITE_gc = (0x03<<0), /* Start on MUXNEG write */ + ADC_START_EVENT_TRIGGER_gc = (0x04<<0), /* Start on event */ +} ADC_START_t; + +/* VIA select */ +typedef enum ADC_VIA_enum +{ + ADC_VIA_ADC_gc = (0x00<<6), /* Via ADC */ + ADC_VIA_PGA_gc = (0x01<<6), /* Via PGA */ +} ADC_VIA_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* Window Mode Source select */ +typedef enum ADC_WINSRC_enum +{ + ADC_WINSRC_RESULT_gc = (0x00<<3), /* Result register */ + ADC_WINSRC_SAMPLE_gc = (0x01<<3), /* Sample register */ +} ADC_WINSRC_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t SEQCTRL1; /* Sequential Control 1 */ + register8_t reserved_1[2]; + register8_t INTCTRL0; /* Interrupt Control 0 */ + register8_t reserved_2[1]; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t LUT2CTRLA; /* LUT Control 2 A */ + register8_t LUT2CTRLB; /* LUT Control 2 B */ + register8_t LUT2CTRLC; /* LUT Control 2 C */ + register8_t TRUTH2; /* Truth 2 */ + register8_t LUT3CTRLA; /* LUT Control 3 A */ + register8_t LUT3CTRLB; /* LUT Control 3 B */ + register8_t LUT3CTRLC; /* LUT Control 3 C */ + register8_t TRUTH3; /* Truth 3 */ + register8_t reserved_3[40]; +} CCL_t; + +/* Clock Source Selection select */ +typedef enum CCL_CLKSRC_enum +{ + CCL_CLKSRC_CLKPER_gc = (0x00<<1), /* CLK_PER is clocking the LUT */ + CCL_CLKSRC_IN2_gc = (0x01<<1), /* IN[2] is clocking the LUT */ + CCL_CLKSRC_OSC20M_gc = (0x04<<1), /* 20MHz oscillator before prescaler is clocking the LUT */ + CCL_CLKSRC_OSCULP32K_gc = (0x05<<1), /* 32kHz oscillator is clocking the LUT */ + CCL_CLKSRC_OSCULP1K_gc = (0x06<<1), /* 32kHz oscillator after DIV32 is clocking the LUT */ +} CCL_CLKSRC_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL0_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_USART0_gc = (0x08<<0), /* USART0 TXD input source */ + CCL_INSEL0_SPI0_gc = (0x09<<0), /* SPI0 MOSI input source */ + CCL_INSEL0_TCA0_gc = (0x0A<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCB0_gc = (0x0C<<0), /* TCB0 WO input source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENTA_gc = (0x03<<4), /* Event input source A */ + CCL_INSEL1_EVENTB_gc = (0x04<<4), /* Event input source B */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_USART1_gc = (0x08<<4), /* USART1 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x09<<4), /* SPI0 MOSI input source */ + CCL_INSEL1_TCA0_gc = (0x0A<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCB1_gc = (0x0C<<4), /* TCB1 WO input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL2_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_SPI0_gc = (0x09<<0), /* SPI0 SCK input source */ + CCL_INSEL2_TCA0_gc = (0x0A<<0), /* TCA0 WO2 input source */ +} CCL_INSEL2_t; + +/* Interrupt Mode for LUT0 select */ +typedef enum CCL_INTMODE0_enum +{ + CCL_INTMODE0_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled */ + CCL_INTMODE0_RISING_gc = (0x01<<0), /* Sense rising edge */ + CCL_INTMODE0_FALLING_gc = (0x02<<0), /* Sense falling edge */ + CCL_INTMODE0_BOTH_gc = (0x03<<0), /* Sense both edges */ +} CCL_INTMODE0_t; + +/* Interrupt Mode for LUT1 select */ +typedef enum CCL_INTMODE1_enum +{ + CCL_INTMODE1_INTDISABLE_gc = (0x00<<2), /* Interrupt disabled */ + CCL_INTMODE1_RISING_gc = (0x01<<2), /* Sense rising edge */ + CCL_INTMODE1_FALLING_gc = (0x02<<2), /* Sense falling edge */ + CCL_INTMODE1_BOTH_gc = (0x03<<2), /* Sense both edges */ +} CCL_INTMODE1_t; + +/* Interrupt Mode for LUT2 select */ +typedef enum CCL_INTMODE2_enum +{ + CCL_INTMODE2_INTDISABLE_gc = (0x00<<4), /* Interrupt disabled */ + CCL_INTMODE2_RISING_gc = (0x01<<4), /* Sense rising edge */ + CCL_INTMODE2_FALLING_gc = (0x02<<4), /* Sense falling edge */ + CCL_INTMODE2_BOTH_gc = (0x03<<4), /* Sense both edges */ +} CCL_INTMODE2_t; + +/* Interrupt Mode for LUT3 select */ +typedef enum CCL_INTMODE3_enum +{ + CCL_INTMODE3_INTDISABLE_gc = (0x00<<6), /* Interrupt disabled */ + CCL_INTMODE3_RISING_gc = (0x01<<6), /* Sense rising edge */ + CCL_INTMODE3_FALLING_gc = (0x02<<6), /* Sense falling edge */ + CCL_INTMODE3_BOTH_gc = (0x03<<6), /* Sense both edges */ +} CCL_INTMODE3_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL0_enum +{ + CCL_SEQSEL0_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL0_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL0_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL0_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL0_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL0_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL1_enum +{ + CCL_SEQSEL1_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL1_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL1_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL1_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL1_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL1_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1k cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16k cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32k cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t SWEVENTA; /* Software Event A */ + register8_t reserved_1[15]; + register8_t CHANNEL0; /* Multiplexer Channel 0 */ + register8_t CHANNEL1; /* Multiplexer Channel 1 */ + register8_t CHANNEL2; /* Multiplexer Channel 2 */ + register8_t CHANNEL3; /* Multiplexer Channel 3 */ + register8_t CHANNEL4; /* Multiplexer Channel 4 */ + register8_t CHANNEL5; /* Multiplexer Channel 5 */ + register8_t reserved_2[10]; + register8_t USERCCLLUT0A; /* User CCL LUT0 Event A */ + register8_t USERCCLLUT0B; /* User CCL LUT0 Event B */ + register8_t USERCCLLUT1A; /* User CCL LUT1 Event A */ + register8_t USERCCLLUT1B; /* User CCL LUT1 Event B */ + register8_t USERCCLLUT2A; /* User CCL LUT2 Event A */ + register8_t USERCCLLUT2B; /* User CCL LUT2 Event B */ + register8_t USERCCLLUT3A; /* User CCL LUT3 Event A */ + register8_t USERCCLLUT3B; /* User CCL LUT3 Event B */ + register8_t USERADC0START; /* User ADC0 */ + register8_t USEREVSYSEVOUTA; /* User EVOUT Port A */ + register8_t USEREVSYSEVOUTB; /* User EVOUT Port B */ + register8_t USEREVSYSEVOUTC; /* User EVOUT Port C */ + register8_t USERUSART0IRDA; /* User USART0 */ + register8_t USERUSART1IRDA; /* User USART1 */ + register8_t USERTCA0CNTA; /* User TCA0 count event */ + register8_t USERTCA0CNTB; /* User TCA0 Restart event */ + register8_t USERTCB0CAPT; /* User TCB0 Event in A */ + register8_t USERTCB0COUNT; /* User TCB0 Event in B */ + register8_t USERTCB1CAPT; /* User TCB1 Event in A */ + register8_t USERTCB1COUNT; /* User TCB1 Event in B */ + register8_t reserved_3[12]; +} EVSYS_t; + +/* Channel 0 generator select select */ +typedef enum EVSYS_CHANNEL0_enum +{ + EVSYS_CHANNEL0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL0_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_CHANNEL0_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL0_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL0_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL0_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL0_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL0_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL0_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL0_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL0_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL0_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL0_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL0_ADC0_RES_gc = (0x24<<0), /* ADC 0 Result ready event */ + EVSYS_CHANNEL0_ADC0_SAMP_gc = (0x25<<0), /* ADC 0 Sample ready event */ + EVSYS_CHANNEL0_ADC0_WCMP_gc = (0x26<<0), /* ADC 0 Window compare match event */ + EVSYS_CHANNEL0_PORTA_PIN0_gc = (0x40<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL0_PORTA_PIN1_gc = (0x41<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL0_PORTA_PIN2_gc = (0x42<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL0_PORTA_PIN3_gc = (0x43<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL0_PORTA_PIN4_gc = (0x44<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL0_PORTA_PIN5_gc = (0x45<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL0_PORTA_PIN6_gc = (0x46<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL0_PORTA_PIN7_gc = (0x47<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL0_PORTB_PIN0_gc = (0x48<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL0_PORTB_PIN1_gc = (0x49<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL0_PORTB_PIN2_gc = (0x4A<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL0_PORTB_PIN3_gc = (0x4B<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL0_PORTB_PIN4_gc = (0x4C<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL0_PORTB_PIN5_gc = (0x4D<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL0_PORTB_PIN6_gc = (0x4E<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL0_PORTB_PIN7_gc = (0x4F<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL0_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL0_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL0_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_CHANNEL0_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_CHANNEL0_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow */ + EVSYS_CHANNEL0_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL0_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL0_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL0_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL0_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL0_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL0_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ +} EVSYS_CHANNEL0_t; + +/* Channel 1 generator select select */ +typedef enum EVSYS_CHANNEL1_enum +{ + EVSYS_CHANNEL1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL1_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_CHANNEL1_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL1_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL1_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL1_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL1_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL1_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL1_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL1_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL1_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL1_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL1_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL1_ADC0_RES_gc = (0x24<<0), /* ADC 0 Result ready event */ + EVSYS_CHANNEL1_ADC0_SAMP_gc = (0x25<<0), /* ADC 0 Sample ready event */ + EVSYS_CHANNEL1_ADC0_WCMP_gc = (0x26<<0), /* ADC 0 Window compare match event */ + EVSYS_CHANNEL1_PORTA_PIN0_gc = (0x40<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL1_PORTA_PIN1_gc = (0x41<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL1_PORTA_PIN2_gc = (0x42<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL1_PORTA_PIN3_gc = (0x43<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL1_PORTA_PIN4_gc = (0x44<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL1_PORTA_PIN5_gc = (0x45<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL1_PORTA_PIN6_gc = (0x46<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL1_PORTA_PIN7_gc = (0x47<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL1_PORTB_PIN0_gc = (0x48<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL1_PORTB_PIN1_gc = (0x49<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL1_PORTB_PIN2_gc = (0x4A<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL1_PORTB_PIN3_gc = (0x4B<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL1_PORTB_PIN4_gc = (0x4C<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL1_PORTB_PIN5_gc = (0x4D<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL1_PORTB_PIN6_gc = (0x4E<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL1_PORTB_PIN7_gc = (0x4F<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL1_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL1_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL1_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_CHANNEL1_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_CHANNEL1_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow */ + EVSYS_CHANNEL1_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL1_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL1_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL1_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL1_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL1_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL1_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ +} EVSYS_CHANNEL1_t; + +/* Channel 2 generator select select */ +typedef enum EVSYS_CHANNEL2_enum +{ + EVSYS_CHANNEL2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL2_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_CHANNEL2_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL2_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL2_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL2_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL2_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL2_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL2_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL2_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL2_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL2_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL2_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL2_ADC0_RES_gc = (0x24<<0), /* ADC 0 Result ready event */ + EVSYS_CHANNEL2_ADC0_SAMP_gc = (0x25<<0), /* ADC 0 Sample ready event */ + EVSYS_CHANNEL2_ADC0_WCMP_gc = (0x26<<0), /* ADC 0 Window compare match event */ + EVSYS_CHANNEL2_PORTC_PIN0_gc = (0x40<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL2_PORTC_PIN1_gc = (0x41<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL2_PORTC_PIN2_gc = (0x42<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL2_PORTC_PIN3_gc = (0x43<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL2_PORTC_PIN4_gc = (0x44<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL2_PORTC_PIN5_gc = (0x45<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL2_PORTC_PIN6_gc = (0x46<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL2_PORTC_PIN7_gc = (0x47<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL2_PORTA_PIN0_gc = (0x48<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL2_PORTA_PIN1_gc = (0x49<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL2_PORTA_PIN2_gc = (0x4A<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL2_PORTA_PIN3_gc = (0x4B<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL2_PORTA_PIN4_gc = (0x4C<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL2_PORTA_PIN5_gc = (0x4D<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL2_PORTA_PIN6_gc = (0x4E<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL2_PORTA_PIN7_gc = (0x4F<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL2_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL2_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL2_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_CHANNEL2_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_CHANNEL2_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow */ + EVSYS_CHANNEL2_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL2_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL2_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL2_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL2_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL2_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL2_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ +} EVSYS_CHANNEL2_t; + +/* Channel 3 generator select select */ +typedef enum EVSYS_CHANNEL3_enum +{ + EVSYS_CHANNEL3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL3_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_CHANNEL3_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL3_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL3_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL3_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL3_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL3_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL3_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL3_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL3_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL3_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL3_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL3_ADC0_RES_gc = (0x24<<0), /* ADC 0 Result ready event */ + EVSYS_CHANNEL3_ADC0_SAMP_gc = (0x25<<0), /* ADC 0 Sample ready event */ + EVSYS_CHANNEL3_ADC0_WCMP_gc = (0x26<<0), /* ADC 0 Window compare match event */ + EVSYS_CHANNEL3_PORTC_PIN0_gc = (0x40<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL3_PORTC_PIN1_gc = (0x41<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL3_PORTC_PIN2_gc = (0x42<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL3_PORTC_PIN3_gc = (0x43<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL3_PORTC_PIN4_gc = (0x44<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL3_PORTC_PIN5_gc = (0x45<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL3_PORTC_PIN6_gc = (0x46<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL3_PORTC_PIN7_gc = (0x47<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL3_PORTA_PIN0_gc = (0x48<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL3_PORTA_PIN1_gc = (0x49<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL3_PORTA_PIN2_gc = (0x4A<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL3_PORTA_PIN3_gc = (0x4B<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL3_PORTA_PIN4_gc = (0x4C<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL3_PORTA_PIN5_gc = (0x4D<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL3_PORTA_PIN6_gc = (0x4E<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL3_PORTA_PIN7_gc = (0x4F<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL3_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL3_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL3_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_CHANNEL3_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_CHANNEL3_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow */ + EVSYS_CHANNEL3_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL3_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL3_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL3_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL3_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL3_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL3_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ +} EVSYS_CHANNEL3_t; + +/* Channel 4 generator select select */ +typedef enum EVSYS_CHANNEL4_enum +{ + EVSYS_CHANNEL4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL4_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_CHANNEL4_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL4_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL4_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL4_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL4_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL4_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL4_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL4_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL4_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL4_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL4_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL4_ADC0_RES_gc = (0x24<<0), /* ADC 0 Result ready event */ + EVSYS_CHANNEL4_ADC0_SAMP_gc = (0x25<<0), /* ADC 0 Sample ready event */ + EVSYS_CHANNEL4_ADC0_WCMP_gc = (0x26<<0), /* ADC 0 Window compare match event */ + EVSYS_CHANNEL4_PORTB_PIN0_gc = (0x40<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL4_PORTB_PIN1_gc = (0x41<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL4_PORTB_PIN2_gc = (0x42<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL4_PORTB_PIN3_gc = (0x43<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL4_PORTB_PIN4_gc = (0x44<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL4_PORTB_PIN5_gc = (0x45<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL4_PORTB_PIN6_gc = (0x46<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL4_PORTB_PIN7_gc = (0x47<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL4_PORTC_PIN0_gc = (0x48<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL4_PORTC_PIN1_gc = (0x49<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL4_PORTC_PIN2_gc = (0x4A<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL4_PORTC_PIN3_gc = (0x4B<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL4_PORTC_PIN4_gc = (0x4C<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL4_PORTC_PIN5_gc = (0x4D<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL4_PORTC_PIN6_gc = (0x4E<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL4_PORTC_PIN7_gc = (0x4F<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL4_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL4_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL4_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_CHANNEL4_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_CHANNEL4_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow */ + EVSYS_CHANNEL4_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL4_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL4_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL4_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL4_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL4_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL4_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ +} EVSYS_CHANNEL4_t; + +/* Channel 5 generator select select */ +typedef enum EVSYS_CHANNEL5_enum +{ + EVSYS_CHANNEL5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL5_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_CHANNEL5_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL5_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL5_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL5_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL5_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL5_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL5_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL5_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL5_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL5_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL5_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL5_ADC0_RES_gc = (0x24<<0), /* ADC 0 Result ready event */ + EVSYS_CHANNEL5_ADC0_SAMP_gc = (0x25<<0), /* ADC 0 Sample ready event */ + EVSYS_CHANNEL5_ADC0_WCMP_gc = (0x26<<0), /* ADC 0 Window compare match event */ + EVSYS_CHANNEL5_PORTB_PIN0_gc = (0x40<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL5_PORTB_PIN1_gc = (0x41<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL5_PORTB_PIN2_gc = (0x42<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL5_PORTB_PIN3_gc = (0x43<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL5_PORTB_PIN4_gc = (0x44<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL5_PORTB_PIN5_gc = (0x45<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL5_PORTB_PIN6_gc = (0x46<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL5_PORTB_PIN7_gc = (0x47<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL5_PORTC_PIN0_gc = (0x48<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL5_PORTC_PIN1_gc = (0x49<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL5_PORTC_PIN2_gc = (0x4A<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL5_PORTC_PIN3_gc = (0x4B<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL5_PORTC_PIN4_gc = (0x4C<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL5_PORTC_PIN5_gc = (0x4D<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL5_PORTC_PIN6_gc = (0x4E<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL5_PORTC_PIN7_gc = (0x4F<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL5_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL5_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL5_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_CHANNEL5_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_CHANNEL5_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow */ + EVSYS_CHANNEL5_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL5_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL5_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL5_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL5_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL5_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL5_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ +} EVSYS_CHANNEL5_t; + +/* Software event on channel select */ +typedef enum EVSYS_SWEVENTA_enum +{ + EVSYS_SWEVENTA_CH0_gc = (0x01<<0), /* Software event on channel 0 */ + EVSYS_SWEVENTA_CH1_gc = (0x02<<0), /* Software event on channel 1 */ + EVSYS_SWEVENTA_CH2_gc = (0x04<<0), /* Software event on channel 2 */ + EVSYS_SWEVENTA_CH3_gc = (0x08<<0), /* Software event on channel 3 */ + EVSYS_SWEVENTA_CH4_gc = (0x10<<0), /* Software event on channel 4 */ + EVSYS_SWEVENTA_CH5_gc = (0x20<<0), /* Software event on channel 5 */ +} EVSYS_SWEVENTA_t; + +/* Channel selector select */ +typedef enum EVSYS_USER_enum +{ + EVSYS_USER_OFF_gc = (0x00<<0), /* Off */ + EVSYS_USER_CHANNEL0_gc = (0x01<<0), /* Connect user to event channel 0 */ + EVSYS_USER_CHANNEL1_gc = (0x02<<0), /* Connect user to event channel 1 */ + EVSYS_USER_CHANNEL2_gc = (0x03<<0), /* Connect user to event channel 2 */ + EVSYS_USER_CHANNEL3_gc = (0x04<<0), /* Connect user to event channel 3 */ + EVSYS_USER_CHANNEL4_gc = (0x05<<0), /* Connect user to event channel 4 */ + EVSYS_USER_CHANNEL5_gc = (0x06<<0), /* Connect user to event channel 5 */ +} EVSYS_USER_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ + RSTPINCFG_PDIRST_gc = (0x03<<2), /* PDI on PDI pad, reset on alternative reset pad */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock Bits */ + register8_t reserved_1[1]; +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMBIST - BIST in the NVMCTRL module +-------------------------------------------------------------------------- +*/ + +/* BIST in the NVMCTRL module */ +typedef struct NVMBIST_struct +{ + register8_t CTRLA; /* Control A */ + register8_t ADDRPAT; /* Address pattern */ + register8_t DATAPAT; /* Data pattern */ + register8_t STATUS; /* Status */ + _WORDREGISTER(CNT); /* */ + _DWORDREGISTER(END); /* */ + register8_t reserved_1[6]; +} NVMBIST_t; + +/* Address mode select */ +typedef enum NVMBIST_AMODE_enum +{ + NVMBIST_AMODE_NORMAL_gc = (0x00<<4), /* No special address pattern */ + NVMBIST_AMODE_COMPLEMENT_gc = (0x04<<4), /* Post complement address */ +} NVMBIST_AMODE_t; + +/* Command select */ +typedef enum NVMBIST_CMD_enum +{ + NVMBIST_CMD_NOCMD_gc = (0x00<<0), /* No effect */ + NVMBIST_CMD_START_gc = (0x01<<0), /* Start BIST testing */ + NVMBIST_CMD_RESTART_gc = (0x02<<0), /* Re-start BIST testing */ + NVMBIST_CMD_BREAK_gc = (0x03<<0), /* Stop BIST and go to BREAK state */ +} NVMBIST_CMD_t; + +/* Data check pattern select */ +typedef enum NVMBIST_PATTERN_enum +{ + NVMBIST_PATTERN_ZEROES_gc = (0x00<<0), /* All flash programmed */ + NVMBIST_PATTERN_CHECK_gc = (0x01<<0), /* Physical checkerboard in flash */ + NVMBIST_PATTERN_INVCHECK_gc = (0x02<<0), /* Inverse physical checkerboard in flash */ + NVMBIST_PATTERN_ONES_gc = (0x03<<0), /* All flash unprogrammed */ +} NVMBIST_PATTERN_t; + +/* FSM State select */ +typedef enum NVMBIST_STATE_enum +{ + NVMBIST_STATE_IDLE_gc = (0x00<<0), /* Reset state */ + NVMBIST_STATE_BREAK_gc = (0x01<<0), /* Break command used */ + NVMBIST_STATE_FAILED0_gc = (0x04<<0), /* Test failed, data from last address */ + NVMBIST_STATE_FAILED1_gc = (0x05<<0), /* Test failed, data from address-1 */ + NVMBIST_STATE_FAILED2_gc = (0x06<<0), /* Test failed, data from address-2 */ + NVMBIST_STATE_SUCCESS_gc = (0x07<<0), /* Test success */ + NVMBIST_STATE_START0_gc = (0x08<<0), /* Startup, fetching first data */ + NVMBIST_STATE_START1_gc = (0x09<<0), /* Startup, fetching second data */ + NVMBIST_STATE_RESTART0_gc = (0x0A<<0), /* Re-start from BREAK or FAILED2 */ + NVMBIST_STATE_RESTART1_gc = (0x0B<<0), /* Re-start from FAILED1 */ + NVMBIST_STATE_RUNNING_gc = (0x0C<<0), /* Test running */ + NVMBIST_STATE_FINISH0_gc = (0x0E<<0), /* Check last word */ + NVMBIST_STATE_FINISH1_gc = (0x0F<<0), /* Count faults in last word */ +} NVMBIST_STATE_t; + +/* X address mode select */ +typedef enum NVMBIST_XMODE_enum +{ + NVMBIST_XMODE_STATIC_gc = (0x00<<0), /* X static */ + NVMBIST_XMODE_CARRY_gc = (0x01<<0), /* Carry/borrow from Y */ + NVMBIST_XMODE_INC_gc = (0x02<<0), /* X increment each cycle */ + NVMBIST_XMODE_DEC_gc = (0x03<<0), /* X decrement each cycle */ +} NVMBIST_XMODE_t; + +/* Y address mode select */ +typedef enum NVMBIST_YMODE_enum +{ + NVMBIST_YMODE_STATIC_gc = (0x00<<2), /* Y static */ + NVMBIST_YMODE_CARRY_gc = (0x01<<2), /* Carry/borrow from X */ + NVMBIST_YMODE_INC_gc = (0x02<<2), /* Y increment each cycle */ + NVMBIST_YMODE_DEC_gc = (0x03<<2), /* Y decrement each cycle */ +} NVMBIST_YMODE_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t PORTCTRL; /* Port Control */ + register8_t reserved_1[5]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t EVSYSROUTEA; /* Port Multiplexer EVSYS */ + register8_t CCLROUTEA; /* Port Multiplexer CCL */ + register8_t USARTROUTEA; /* Port Multiplexer USART register A */ + register8_t SPIROUTEA; /* Port Multiplexer TWI and SPI */ + register8_t TCAROUTEA; /* Port Multiplexer TCA */ + register8_t TCBROUTEA; /* Port Multiplexer TCB */ + register8_t reserved_1[10]; +} PORTMUX_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<0), /* SPI0 on PA[7:4] */ + PORTMUX_SPI0_ALT1_gc = (0x01<<0), /* SPI0 on PC[3:0] */ + PORTMUX_SPI0_ALT2_gc = (0x02<<0), /* SPI0 on PE[3:0] */ + PORTMUX_SPI0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 select */ +typedef enum PORTMUX_TCA0_enum +{ + PORTMUX_TCA0_PORTA_gc = (0x00<<0), /* TCA0 pins on PA[5:0] */ + PORTMUX_TCA0_PORTB_gc = (0x01<<0), /* TCA0 pins on PB[5:0] */ + PORTMUX_TCA0_PORTC_gc = (0x02<<0), /* TCA0 pins on PC[5:0] */ + PORTMUX_TCA0_PORTD_gc = (0x03<<0), /* TCA0 pins on PD[5:0] */ + PORTMUX_TCA0_PORTE_gc = (0x04<<0), /* TCA0 pins on PE[5:0] */ + PORTMUX_TCA0_PORTF_gc = (0x05<<0), /* TCA0 pins on PF[5:0] */ +} PORTMUX_TCA0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* SCL/SDA on PA[3:2], Slave mode on PC[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT1_gc = (0x01<<4), /* SCL/SDA on PA[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT2_gc = (0x02<<4), /* SCL/SDA on PC[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* USART0 on PA[3:0] */ + PORTMUX_USART0_ALT1_gc = (0x01<<0), /* USART0 on PA[7:4] */ + PORTMUX_USART0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_USART0_t; + +/* Port Multiplexer USART1 select */ +typedef enum PORTMUX_USART1_enum +{ + PORTMUX_USART1_DEFAULT_gc = (0x00<<2), /* USART1 on PC[3:0] */ + PORTMUX_USART1_ALT1_gc = (0x01<<2), /* USART1 on PC[7:4] */ + PORTMUX_USART1_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_USART1_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t CALIB; /* Calibration */ + register8_t CLKSEL; /* RTC Clock */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_1[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_2[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_3[10]; +} RTC_t; + +/* Clock select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[7]; + register8_t OSCCAL32K; /* Oscillator Calibration for 32kHz ULP */ + register8_t reserved_2[3]; + register8_t OSCCAL16M0; /* Oscillator Calibration 16 MHz Byte 0 */ + register8_t OSCCAL16M1; /* Oscillator Calibration 16 MHz Byte 1 */ + register8_t OSCCAL20M0; /* Oscillator Calibration 20 MHz Byte 0 */ + register8_t OSCCAL20M1; /* Oscillator Calibration 20 MHz Byte 1 */ + register8_t reserved_3[4]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_4[9]; + register8_t CHECKSUM1; /* CRC Checksum Byte 1 */ + register8_t reserved_5[16]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[21]; + register8_t OCDM; /* OCD Message Register */ + register8_t OCDMS; /* OCD Message Status */ + register8_t reserved_3[6]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action A select */ +typedef enum TCA_SINGLE_EVACTA_enum +{ + TCA_SINGLE_EVACTA_CNT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACTA_CNT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACTA_CNT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACTA_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACTA_t; + +/* Event Action B select */ +typedef enum TCA_SINGLE_EVACTB_enum +{ + TCA_SINGLE_EVACTB_UPDOWN_gc = (0x03<<5), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ + TCA_SINGLE_EVACTB_RESTART_POSEDGE_gc = (0x04<<5), /* Restart counter at positive edge event */ + TCA_SINGLE_EVACTB_RESTART_ANYEDGE_gc = (0x05<<5), /* Restart counter on any edge event */ + TCA_SINGLE_EVACTB_RESTART_HIGHLVL_gc = (0x06<<5), /* Restart counter while event line is 1. */ +} TCA_SINGLE_EVACTB_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* Command Enable select */ +typedef enum TCA_SPLIT_CMDEN_enum +{ + TCA_SPLIT_CMDEN_NONE_gc = (0x00<<0), /* None */ + TCA_SPLIT_CMDEN_BOTH_gc = (0x03<<0), /* Both low byte and high byte */ +} TCA_SPLIT_CMDEN_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* TCB Clock select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_DIV1_gc = (0x00<<1), /* CLK_PEP */ + TCB_CLKSEL_DIV2_gc = (0x01<<1), /* CLK_PER/2 */ + TCB_CLKSEL_TCA0_gc = (0x02<<1), /* Use CLK_TCA from TCA0 */ + TCB_CLKSEL_EVENT_gc = (0x07<<1), /* Count on event edge */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baud Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t CTRLD; /* Control D */ + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_1[1]; +} USART_t; + +/* Auto Baud Window select */ +typedef enum USART_ABW_enum +{ + USART_ABW_WDW0_gc = (0x00<<6), /* 18% tolerance */ + USART_ABW_WDW1_gc = (0x01<<6), /* 15% tolerance */ + USART_ABW_WDW2_gc = (0x02<<6), /* 21% tolerance */ + USART_ABW_WDW3_gc = (0x03<<6), /* 25% tolerance */ +} USART_ABW_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_DISABLE_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_ENABLE_gc = (0x01<<0), /* RS485 Mode enabled */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ + register8_t USERROW32; /* User Row Byte 32 */ + register8_t USERROW33; /* User Row Byte 33 */ + register8_t USERROW34; /* User Row Byte 34 */ + register8_t USERROW35; /* User Row Byte 35 */ + register8_t USERROW36; /* User Row Byte 36 */ + register8_t USERROW37; /* User Row Byte 37 */ + register8_t USERROW38; /* User Row Byte 38 */ + register8_t USERROW39; /* User Row Byte 39 */ + register8_t USERROW40; /* User Row Byte 40 */ + register8_t USERROW41; /* User Row Byte 41 */ + register8_t USERROW42; /* User Row Byte 42 */ + register8_t USERROW43; /* User Row Byte 43 */ + register8_t USERROW44; /* User Row Byte 44 */ + register8_t USERROW45; /* User Row Byte 45 */ + register8_t USERROW46; /* User Row Byte 46 */ + register8_t USERROW47; /* User Row Byte 47 */ + register8_t USERROW48; /* User Row Byte 48 */ + register8_t USERROW49; /* User Row Byte 49 */ + register8_t USERROW50; /* User Row Byte 50 */ + register8_t USERROW51; /* User Row Byte 51 */ + register8_t USERROW52; /* User Row Byte 52 */ + register8_t USERROW53; /* User Row Byte 53 */ + register8_t USERROW54; /* User Row Byte 54 */ + register8_t USERROW55; /* User Row Byte 55 */ + register8_t USERROW56; /* User Row Byte 56 */ + register8_t USERROW57; /* User Row Byte 57 */ + register8_t USERROW58; /* User Row Byte 58 */ + register8_t USERROW59; /* User Row Byte 59 */ + register8_t USERROW60; /* User Row Byte 60 */ + register8_t USERROW61; /* User Row Byte 61 */ + register8_t USERROW62; /* User Row Byte 62 */ + register8_t USERROW63; /* User Row Byte 63 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* AC0 reference select select */ +typedef enum VREF_AC0REFSEL_enum +{ + VREF_AC0REFSEL_1V024_gc = (0x00<<0), /* Voltage reference at 1.024V */ + VREF_AC0REFSEL_2V048_gc = (0x01<<0), /* Voltage reference at 2.048V */ + VREF_AC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_AC0REFSEL_4V096_gc = (0x03<<0), /* Voltage reference at 4.096V */ + VREF_AC0REFSEL_AVDD_gc = (0x07<<0), /* voltage reference at supply */ +} VREF_AC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define NVMBIST (*(NVMBIST_t *) 0x00C0) /* BIST in the NVMCTRL module */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define PORTMUX (*(PORTMUX_t *) 0x05E0) /* Port Multiplexer */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1 (*(USART_t *) 0x0820) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x08A0) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A80) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0A90) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* NVMBIST - BIST in the NVMCTRL module */ +#define NVMBIST_CTRLA _SFR_MEM8(0x00C0) +#define NVMBIST_ADDRPAT _SFR_MEM8(0x00C1) +#define NVMBIST_DATAPAT _SFR_MEM8(0x00C2) +#define NVMBIST_STATUS _SFR_MEM8(0x00C3) +#define NVMBIST_CNT _SFR_MEM16(0x00C4) +#define NVMBIST_CNTL _SFR_MEM8(0x00C4) +#define NVMBIST_CNTH _SFR_MEM8(0x00C5) +#define NVMBIST_END _SFR_MEM32(0x00C6) +#define NVMBIST_END0 _SFR_MEM8(0x00C6) +#define NVMBIST_END1 _SFR_MEM8(0x00C7) +#define NVMBIST_END2 _SFR_MEM8(0x00C8) +#define NVMBIST_END3 _SFR_MEM8(0x00C9) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CALIB _SFR_MEM8(0x0146) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_SWEVENTA _SFR_MEM8(0x0180) +#define EVSYS_CHANNEL0 _SFR_MEM8(0x0190) +#define EVSYS_CHANNEL1 _SFR_MEM8(0x0191) +#define EVSYS_CHANNEL2 _SFR_MEM8(0x0192) +#define EVSYS_CHANNEL3 _SFR_MEM8(0x0193) +#define EVSYS_CHANNEL4 _SFR_MEM8(0x0194) +#define EVSYS_CHANNEL5 _SFR_MEM8(0x0195) +#define EVSYS_USERCCLLUT0A _SFR_MEM8(0x01A0) +#define EVSYS_USERCCLLUT0B _SFR_MEM8(0x01A1) +#define EVSYS_USERCCLLUT1A _SFR_MEM8(0x01A2) +#define EVSYS_USERCCLLUT1B _SFR_MEM8(0x01A3) +#define EVSYS_USERCCLLUT2A _SFR_MEM8(0x01A4) +#define EVSYS_USERCCLLUT2B _SFR_MEM8(0x01A5) +#define EVSYS_USERCCLLUT3A _SFR_MEM8(0x01A6) +#define EVSYS_USERCCLLUT3B _SFR_MEM8(0x01A7) +#define EVSYS_USERADC0START _SFR_MEM8(0x01A8) +#define EVSYS_USEREVSYSEVOUTA _SFR_MEM8(0x01A9) +#define EVSYS_USEREVSYSEVOUTB _SFR_MEM8(0x01AA) +#define EVSYS_USEREVSYSEVOUTC _SFR_MEM8(0x01AB) +#define EVSYS_USERUSART0IRDA _SFR_MEM8(0x01AC) +#define EVSYS_USERUSART1IRDA _SFR_MEM8(0x01AD) +#define EVSYS_USERTCA0CNTA _SFR_MEM8(0x01AE) +#define EVSYS_USERTCA0CNTB _SFR_MEM8(0x01AF) +#define EVSYS_USERTCB0CAPT _SFR_MEM8(0x01B0) +#define EVSYS_USERTCB0COUNT _SFR_MEM8(0x01B1) +#define EVSYS_USERTCB1CAPT _SFR_MEM8(0x01B2) +#define EVSYS_USERTCB1COUNT _SFR_MEM8(0x01B3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_SEQCTRL1 _SFR_MEM8(0x01C2) +#define CCL_INTCTRL0 _SFR_MEM8(0x01C5) +#define CCL_INTFLAGS _SFR_MEM8(0x01C7) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C8) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C9) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01CA) +#define CCL_TRUTH0 _SFR_MEM8(0x01CB) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01CC) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CD) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CE) +#define CCL_TRUTH1 _SFR_MEM8(0x01CF) +#define CCL_LUT2CTRLA _SFR_MEM8(0x01D0) +#define CCL_LUT2CTRLB _SFR_MEM8(0x01D1) +#define CCL_LUT2CTRLC _SFR_MEM8(0x01D2) +#define CCL_TRUTH2 _SFR_MEM8(0x01D3) +#define CCL_LUT3CTRLA _SFR_MEM8(0x01D4) +#define CCL_LUT3CTRLB _SFR_MEM8(0x01D5) +#define CCL_LUT3CTRLC _SFR_MEM8(0x01D6) +#define CCL_TRUTH3 _SFR_MEM8(0x01D7) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PORTCTRL _SFR_MEM8(0x040A) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PORTCTRL _SFR_MEM8(0x042A) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PORTCTRL _SFR_MEM8(0x044A) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_EVSYSROUTEA _SFR_MEM8(0x05E0) +#define PORTMUX_CCLROUTEA _SFR_MEM8(0x05E1) +#define PORTMUX_USARTROUTEA _SFR_MEM8(0x05E2) +#define PORTMUX_SPIROUTEA _SFR_MEM8(0x05E3) +#define PORTMUX_TCAROUTEA _SFR_MEM8(0x05E4) +#define PORTMUX_TCBROUTEA _SFR_MEM8(0x05E5) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_INTCTRL _SFR_MEM8(0x0604) +#define ADC0_INTFLAGS _SFR_MEM8(0x0605) +#define ADC0_STATUS _SFR_MEM8(0x0606) +#define ADC0_DBGCTRL _SFR_MEM8(0x0607) +#define ADC0_CTRLE _SFR_MEM8(0x0608) +#define ADC0_CTRLF _SFR_MEM8(0x0609) +#define ADC0_COMMAND _SFR_MEM8(0x060A) +#define ADC0_PGACTRL _SFR_MEM8(0x060B) +#define ADC0_MUXPOS _SFR_MEM8(0x060C) +#define ADC0_MUXNEG _SFR_MEM8(0x060D) +#define ADC0_RESULT _SFR_MEM32(0x0610) +#define ADC0_RESULT0 _SFR_MEM8(0x0610) +#define ADC0_RESULT1 _SFR_MEM8(0x0611) +#define ADC0_RESULT2 _SFR_MEM8(0x0612) +#define ADC0_RESULT3 _SFR_MEM8(0x0613) +#define ADC0_SAMPLE _SFR_MEM16(0x0614) +#define ADC0_SAMPLEL _SFR_MEM8(0x0614) +#define ADC0_SAMPLEH _SFR_MEM8(0x0615) +#define ADC0_TEMP0 _SFR_MEM8(0x0618) +#define ADC0_TEMP1 _SFR_MEM8(0x0619) +#define ADC0_TEMP2 _SFR_MEM8(0x061A) +#define ADC0_WINLT _SFR_MEM16(0x061C) +#define ADC0_WINLTL _SFR_MEM8(0x061C) +#define ADC0_WINLTH _SFR_MEM8(0x061D) +#define ADC0_WINHT _SFR_MEM16(0x061E) +#define ADC0_WINHTL _SFR_MEM8(0x061E) +#define ADC0_WINHTH _SFR_MEM8(0x061F) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_DACREF _SFR_MEM8(0x0684) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_CTRLD _SFR_MEM8(0x080A) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* USART (USART1) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1_RXDATAL _SFR_MEM8(0x0820) +#define USART1_RXDATAH _SFR_MEM8(0x0821) +#define USART1_TXDATAL _SFR_MEM8(0x0822) +#define USART1_TXDATAH _SFR_MEM8(0x0823) +#define USART1_STATUS _SFR_MEM8(0x0824) +#define USART1_CTRLA _SFR_MEM8(0x0825) +#define USART1_CTRLB _SFR_MEM8(0x0826) +#define USART1_CTRLC _SFR_MEM8(0x0827) +#define USART1_BAUD _SFR_MEM16(0x0828) +#define USART1_BAUDL _SFR_MEM8(0x0828) +#define USART1_BAUDH _SFR_MEM8(0x0829) +#define USART1_CTRLD _SFR_MEM8(0x082A) +#define USART1_DBGCTRL _SFR_MEM8(0x082B) +#define USART1_EVCTRL _SFR_MEM8(0x082C) +#define USART1_TXPLCTRL _SFR_MEM8(0x082D) +#define USART1_RXPLCTRL _SFR_MEM8(0x082E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x08A0) +#define TWI0_DBGCTRL _SFR_MEM8(0x08A2) +#define TWI0_MCTRLA _SFR_MEM8(0x08A3) +#define TWI0_MCTRLB _SFR_MEM8(0x08A4) +#define TWI0_MSTATUS _SFR_MEM8(0x08A5) +#define TWI0_MBAUD _SFR_MEM8(0x08A6) +#define TWI0_MADDR _SFR_MEM8(0x08A7) +#define TWI0_MDATA _SFR_MEM8(0x08A8) +#define TWI0_SCTRLA _SFR_MEM8(0x08A9) +#define TWI0_SCTRLB _SFR_MEM8(0x08AA) +#define TWI0_SSTATUS _SFR_MEM8(0x08AB) +#define TWI0_SADDR _SFR_MEM8(0x08AC) +#define TWI0_SDATA _SFR_MEM8(0x08AD) +#define TWI0_SADDRMASK _SFR_MEM8(0x08AE) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x08C0) +#define SPI0_CTRLB _SFR_MEM8(0x08C1) +#define SPI0_INTCTRL _SFR_MEM8(0x08C2) +#define SPI0_INTFLAGS _SFR_MEM8(0x08C3) +#define SPI0_DATA _SFR_MEM8(0x08C4) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A80) +#define TCB0_CTRLB _SFR_MEM8(0x0A81) +#define TCB0_EVCTRL _SFR_MEM8(0x0A84) +#define TCB0_INTCTRL _SFR_MEM8(0x0A85) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A86) +#define TCB0_STATUS _SFR_MEM8(0x0A87) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A88) +#define TCB0_TEMP _SFR_MEM8(0x0A89) +#define TCB0_CNT _SFR_MEM16(0x0A8A) +#define TCB0_CNTL _SFR_MEM8(0x0A8A) +#define TCB0_CNTH _SFR_MEM8(0x0A8B) +#define TCB0_CCMP _SFR_MEM16(0x0A8C) +#define TCB0_CCMPL _SFR_MEM8(0x0A8C) +#define TCB0_CCMPH _SFR_MEM8(0x0A8D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0A90) +#define TCB1_CTRLB _SFR_MEM8(0x0A91) +#define TCB1_EVCTRL _SFR_MEM8(0x0A94) +#define TCB1_INTCTRL _SFR_MEM8(0x0A95) +#define TCB1_INTFLAGS _SFR_MEM8(0x0A96) +#define TCB1_STATUS _SFR_MEM8(0x0A97) +#define TCB1_DBGCTRL _SFR_MEM8(0x0A98) +#define TCB1_TEMP _SFR_MEM8(0x0A99) +#define TCB1_CNT _SFR_MEM16(0x0A9A) +#define TCB1_CNTL _SFR_MEM8(0x0A9A) +#define TCB1_CNTH _SFR_MEM8(0x0A9B) +#define TCB1_CCMP _SFR_MEM16(0x0A9C) +#define TCB1_CCMPL _SFR_MEM8(0x0A9C) +#define TCB1_CCMPH _SFR_MEM8(0x0A9D) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) +#define SYSCFG_OCDM _SFR_MEM8(0x0F18) +#define SYSCFG_OCDMS _SFR_MEM8(0x0F19) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_OSCCAL32K _SFR_MEM8(0x1114) +#define SIGROW_OSCCAL16M0 _SFR_MEM8(0x1118) +#define SIGROW_OSCCAL16M1 _SFR_MEM8(0x1119) +#define SIGROW_OSCCAL20M0 _SFR_MEM8(0x111A) +#define SIGROW_OSCCAL20M1 _SFR_MEM8(0x111B) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) +#define SIGROW_CHECKSUM1 _SFR_MEM8(0x112F) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) +#define USERROW_USERROW32 _SFR_MEM8(0x1320) +#define USERROW_USERROW33 _SFR_MEM8(0x1321) +#define USERROW_USERROW34 _SFR_MEM8(0x1322) +#define USERROW_USERROW35 _SFR_MEM8(0x1323) +#define USERROW_USERROW36 _SFR_MEM8(0x1324) +#define USERROW_USERROW37 _SFR_MEM8(0x1325) +#define USERROW_USERROW38 _SFR_MEM8(0x1326) +#define USERROW_USERROW39 _SFR_MEM8(0x1327) +#define USERROW_USERROW40 _SFR_MEM8(0x1328) +#define USERROW_USERROW41 _SFR_MEM8(0x1329) +#define USERROW_USERROW42 _SFR_MEM8(0x132A) +#define USERROW_USERROW43 _SFR_MEM8(0x132B) +#define USERROW_USERROW44 _SFR_MEM8(0x132C) +#define USERROW_USERROW45 _SFR_MEM8(0x132D) +#define USERROW_USERROW46 _SFR_MEM8(0x132E) +#define USERROW_USERROW47 _SFR_MEM8(0x132F) +#define USERROW_USERROW48 _SFR_MEM8(0x1330) +#define USERROW_USERROW49 _SFR_MEM8(0x1331) +#define USERROW_USERROW50 _SFR_MEM8(0x1332) +#define USERROW_USERROW51 _SFR_MEM8(0x1333) +#define USERROW_USERROW52 _SFR_MEM8(0x1334) +#define USERROW_USERROW53 _SFR_MEM8(0x1335) +#define USERROW_USERROW54 _SFR_MEM8(0x1336) +#define USERROW_USERROW55 _SFR_MEM8(0x1337) +#define USERROW_USERROW56 _SFR_MEM8(0x1338) +#define USERROW_USERROW57 _SFR_MEM8(0x1339) +#define USERROW_USERROW58 _SFR_MEM8(0x133A) +#define USERROW_USERROW59 _SFR_MEM8(0x133B) +#define USERROW_USERROW60 _SFR_MEM8(0x133C) +#define USERROW_USERROW61 _SFR_MEM8(0x133D) +#define USERROW_USERROW62 _SFR_MEM8(0x133E) +#define USERROW_USERROW63 _SFR_MEM8(0x133F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.DACREF bit masks and bit positions */ +#define AC_DATA_gm 0xFF /* DAC voltage reference group mask. */ +#define AC_DATA_gp 0 /* DAC voltage reference group position. */ +#define AC_DATA0_bm (1<<0) /* DAC voltage reference bit 0 mask. */ +#define AC_DATA0_bp 0 /* DAC voltage reference bit 0 position. */ +#define AC_DATA1_bm (1<<1) /* DAC voltage reference bit 1 mask. */ +#define AC_DATA1_bp 1 /* DAC voltage reference bit 1 position. */ +#define AC_DATA2_bm (1<<2) /* DAC voltage reference bit 2 mask. */ +#define AC_DATA2_bp 2 /* DAC voltage reference bit 2 position. */ +#define AC_DATA3_bm (1<<3) /* DAC voltage reference bit 3 mask. */ +#define AC_DATA3_bp 3 /* DAC voltage reference bit 3 position. */ +#define AC_DATA4_bm (1<<4) /* DAC voltage reference bit 4 mask. */ +#define AC_DATA4_bp 4 /* DAC voltage reference bit 4 position. */ +#define AC_DATA5_bm (1<<5) /* DAC voltage reference bit 5 mask. */ +#define AC_DATA5_bp 5 /* DAC voltage reference bit 5 position. */ +#define AC_DATA6_bm (1<<6) /* DAC voltage reference bit 6 mask. */ +#define AC_DATA6_bp 6 /* DAC voltage reference bit 6 position. */ +#define AC_DATA7_bm (1<<7) /* DAC voltage reference bit 7 mask. */ +#define AC_DATA7_bp 7 /* DAC voltage reference bit 7 position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_LOWLAT_bm 0x20 /* ADC Low latency mode bit mask. */ +#define ADC_LOWLAT_bp 5 /* ADC Low latency mode bit position. */ +#define ADC_RUNSTDBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTDBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_PRESC_gm 0x0F /* Prescaler Value group mask. */ +#define ADC_PRESC_gp 0 /* Prescaler Value group position. */ +#define ADC_PRESC0_bm (1<<0) /* Prescaler Value bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Prescaler Value bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Prescaler Value bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Prescaler Value bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Prescaler Value bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Prescaler Value bit 2 position. */ +#define ADC_PRESC3_bm (1<<3) /* Prescaler Value bit 3 mask. */ +#define ADC_PRESC3_bp 3 /* Prescaler Value bit 3 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_REFSEL_gm 0x07 /* Reference select group mask. */ +#define ADC_REFSEL_gp 0 /* Reference select group position. */ +#define ADC_REFSEL0_bm (1<<0) /* Reference select bit 0 mask. */ +#define ADC_REFSEL0_bp 0 /* Reference select bit 0 position. */ +#define ADC_REFSEL1_bm (1<<1) /* Reference select bit 1 mask. */ +#define ADC_REFSEL1_bp 1 /* Reference select bit 1 position. */ +#define ADC_REFSEL2_bm (1<<2) /* Reference select bit 2 mask. */ +#define ADC_REFSEL2_bp 2 /* Reference select bit 2 position. */ +#define ADC_TIMEBASE_gm 0xF8 /* Reference Selection group mask. */ +#define ADC_TIMEBASE_gp 3 /* Reference Selection group position. */ +#define ADC_TIMEBASE0_bm (1<<3) /* Reference Selection bit 0 mask. */ +#define ADC_TIMEBASE0_bp 3 /* Reference Selection bit 0 position. */ +#define ADC_TIMEBASE1_bm (1<<4) /* Reference Selection bit 1 mask. */ +#define ADC_TIMEBASE1_bp 4 /* Reference Selection bit 1 position. */ +#define ADC_TIMEBASE2_bm (1<<5) /* Reference Selection bit 2 mask. */ +#define ADC_TIMEBASE2_bp 5 /* Reference Selection bit 2 position. */ +#define ADC_TIMEBASE3_bm (1<<6) /* Reference Selection bit 3 mask. */ +#define ADC_TIMEBASE3_bp 6 /* Reference Selection bit 3 position. */ +#define ADC_TIMEBASE4_bm (1<<7) /* Reference Selection bit 4 mask. */ +#define ADC_TIMEBASE4_bp 7 /* Reference Selection bit 4 position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ +#define ADC_WINSRC_bm 0x08 /* Window Mode Source bit mask. */ +#define ADC_WINSRC_bp 3 /* Window Mode Source bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_SAMPRDY_bm 0x02 /* Sample Ready Interrupt Enable bit mask. */ +#define ADC_SAMPRDY_bp 1 /* Sample Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x04 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 2 /* Window Comparator Interrupt Enable bit position. */ +#define ADC_RESOVR_bm 0x08 /* Result Overwritten Interrupt Enable bit mask. */ +#define ADC_RESOVR_bp 3 /* Result Overwritten Interrupt Enable bit position. */ +#define ADC_SAMPOVR_bm 0x10 /* Sample Overwritten Interrupt Enable bit mask. */ +#define ADC_SAMPOVR_bp 4 /* Sample Overwritten Interrupt Enable bit position. */ +#define ADC_TRIGOVR_bm 0x20 /* Trigger Overrun Interrupt Enable bit mask. */ +#define ADC_TRIGOVR_bp 5 /* Trigger Overrun Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_SAMPRDY is already defined. */ +/* ADC_WCMP is already defined. */ +/* ADC_RESOVR is already defined. */ +/* ADC_SAMPOVR is already defined. */ +/* ADC_TRIGOVR is already defined. */ + +/* ADC.STATUS bit masks and bit positions */ +#define ADC_ADCBUSY_bm 0x01 /* ADC Busy bit mask. */ +#define ADC_ADCBUSY_bp 0 /* ADC Busy bit position. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_SAMPDUR_gm 0xFF /* Sampling time group mask. */ +#define ADC_SAMPDUR_gp 0 /* Sampling time group position. */ +#define ADC_SAMPDUR0_bm (1<<0) /* Sampling time bit 0 mask. */ +#define ADC_SAMPDUR0_bp 0 /* Sampling time bit 0 position. */ +#define ADC_SAMPDUR1_bm (1<<1) /* Sampling time bit 1 mask. */ +#define ADC_SAMPDUR1_bp 1 /* Sampling time bit 1 position. */ +#define ADC_SAMPDUR2_bm (1<<2) /* Sampling time bit 2 mask. */ +#define ADC_SAMPDUR2_bp 2 /* Sampling time bit 2 position. */ +#define ADC_SAMPDUR3_bm (1<<3) /* Sampling time bit 3 mask. */ +#define ADC_SAMPDUR3_bp 3 /* Sampling time bit 3 position. */ +#define ADC_SAMPDUR4_bm (1<<4) /* Sampling time bit 4 mask. */ +#define ADC_SAMPDUR4_bp 4 /* Sampling time bit 4 position. */ +#define ADC_SAMPDUR5_bm (1<<5) /* Sampling time bit 5 mask. */ +#define ADC_SAMPDUR5_bp 5 /* Sampling time bit 5 position. */ +#define ADC_SAMPDUR6_bm (1<<6) /* Sampling time bit 6 mask. */ +#define ADC_SAMPDUR6_bp 6 /* Sampling time bit 6 position. */ +#define ADC_SAMPDUR7_bm (1<<7) /* Sampling time bit 7 mask. */ +#define ADC_SAMPDUR7_bp 7 /* Sampling time bit 7 position. */ + +/* ADC.CTRLF bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x0F /* Sample numbers group mask. */ +#define ADC_SAMPNUM_gp 0 /* Sample numbers group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Sample numbers bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Sample numbers bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Sample numbers bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Sample numbers bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Sample numbers bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Sample numbers bit 2 position. */ +#define ADC_SAMPNUM3_bm (1<<3) /* Sample numbers bit 3 mask. */ +#define ADC_SAMPNUM3_bp 3 /* Sample numbers bit 3 position. */ +#define ADC_LEFTADJ_bm 0x10 /* Left adjust bit mask. */ +#define ADC_LEFTADJ_bp 4 /* Left adjust bit position. */ +#define ADC_FREERUN_bm 0x20 /* Free running mode bit mask. */ +#define ADC_FREERUN_bp 5 /* Free running mode bit position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_START_gm 0x07 /* Start command group mask. */ +#define ADC_START_gp 0 /* Start command group position. */ +#define ADC_START0_bm (1<<0) /* Start command bit 0 mask. */ +#define ADC_START0_bp 0 /* Start command bit 0 position. */ +#define ADC_START1_bm (1<<1) /* Start command bit 1 mask. */ +#define ADC_START1_bp 1 /* Start command bit 1 position. */ +#define ADC_START2_bm (1<<2) /* Start command bit 2 mask. */ +#define ADC_START2_bp 2 /* Start command bit 2 position. */ +#define ADC_MODE_gm 0x70 /* Mode group mask. */ +#define ADC_MODE_gp 4 /* Mode group position. */ +#define ADC_MODE0_bm (1<<4) /* Mode bit 0 mask. */ +#define ADC_MODE0_bp 4 /* Mode bit 0 position. */ +#define ADC_MODE1_bm (1<<5) /* Mode bit 1 mask. */ +#define ADC_MODE1_bp 5 /* Mode bit 1 position. */ +#define ADC_MODE2_bm (1<<6) /* Mode bit 2 mask. */ +#define ADC_MODE2_bp 6 /* Mode bit 2 position. */ +#define ADC_DIFF_bm 0x80 /* Differential mode bit mask. */ +#define ADC_DIFF_bp 7 /* Differential mode bit position. */ + +/* ADC.PGACTRL bit masks and bit positions */ +#define ADC_PGAEN_bm 0x01 /* PGA Enable bit mask. */ +#define ADC_PGAEN_bp 0 /* PGA Enable bit position. */ +#define ADC_ADCPGASAMPDUR_gm 0x06 /* ADC PGA Sample Duration group mask. */ +#define ADC_ADCPGASAMPDUR_gp 1 /* ADC PGA Sample Duration group position. */ +#define ADC_ADCPGASAMPDUR0_bm (1<<1) /* ADC PGA Sample Duration bit 0 mask. */ +#define ADC_ADCPGASAMPDUR0_bp 1 /* ADC PGA Sample Duration bit 0 position. */ +#define ADC_ADCPGASAMPDUR1_bm (1<<2) /* ADC PGA Sample Duration bit 1 mask. */ +#define ADC_ADCPGASAMPDUR1_bp 2 /* ADC PGA Sample Duration bit 1 position. */ +#define ADC_PGABIASSEL_gm 0x18 /* PGA BIAS Select group mask. */ +#define ADC_PGABIASSEL_gp 3 /* PGA BIAS Select group position. */ +#define ADC_PGABIASSEL0_bm (1<<3) /* PGA BIAS Select bit 0 mask. */ +#define ADC_PGABIASSEL0_bp 3 /* PGA BIAS Select bit 0 position. */ +#define ADC_PGABIASSEL1_bm (1<<4) /* PGA BIAS Select bit 1 mask. */ +#define ADC_PGABIASSEL1_bp 4 /* PGA BIAS Select bit 1 position. */ +#define ADC_GAIN_gm 0xE0 /* Gain group mask. */ +#define ADC_GAIN_gp 5 /* Gain group position. */ +#define ADC_GAIN0_bm (1<<5) /* Gain bit 0 mask. */ +#define ADC_GAIN0_bp 5 /* Gain bit 0 position. */ +#define ADC_GAIN1_bm (1<<6) /* Gain bit 1 mask. */ +#define ADC_GAIN1_bp 6 /* Gain bit 1 position. */ +#define ADC_GAIN2_bm (1<<7) /* Gain bit 2 mask. */ +#define ADC_GAIN2_bp 7 /* Gain bit 2 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x3F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ +#define ADC_MUXPOS5_bm (1<<5) /* Analog Channel Selection Bits bit 5 mask. */ +#define ADC_MUXPOS5_bp 5 /* Analog Channel Selection Bits bit 5 position. */ +#define ADC_VIA_gm 0xC0 /* VIA group mask. */ +#define ADC_VIA_gp 6 /* VIA group position. */ +#define ADC_VIA0_bm (1<<6) /* VIA bit 0 mask. */ +#define ADC_VIA0_bp 6 /* VIA bit 0 position. */ +#define ADC_VIA1_bm (1<<7) /* VIA bit 1 mask. */ +#define ADC_VIA1_bp 7 /* VIA bit 1 position. */ + +/* ADC.MUXNEG bit masks and bit positions */ +#define ADC_MUXNEG_gm 0x3F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXNEG_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXNEG0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXNEG0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXNEG1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXNEG1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXNEG2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXNEG2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXNEG3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXNEG3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXNEG4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXNEG4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ +#define ADC_MUXNEG5_bm (1<<5) /* Analog Channel Selection Bits bit 5 mask. */ +#define ADC_MUXNEG5_bp 5 /* Analog Channel Selection Bits bit 5 position. */ +/* ADC_VIA is already defined. */ + + + +/* ADC.TEMP0 bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + +/* ADC.TEMP1 bit masks and bit positions */ +/* ADC_TEMP is already defined. */ + +/* ADC.TEMP2 bit masks and bit positions */ +/* ADC_TEMP is already defined. */ + + + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL0_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL0_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL00_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL00_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL01_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL01_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL02_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL02_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.SEQCTRL1 bit masks and bit positions */ +#define CCL_SEQSEL1_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL1_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL10_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL10_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL11_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL11_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL12_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL12_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.INTCTRL0 bit masks and bit positions */ +#define CCL_INTMODE0_gm 0x03 /* Interrupt Mode for LUT0 group mask. */ +#define CCL_INTMODE0_gp 0 /* Interrupt Mode for LUT0 group position. */ +#define CCL_INTMODE00_bm (1<<0) /* Interrupt Mode for LUT0 bit 0 mask. */ +#define CCL_INTMODE00_bp 0 /* Interrupt Mode for LUT0 bit 0 position. */ +#define CCL_INTMODE01_bm (1<<1) /* Interrupt Mode for LUT0 bit 1 mask. */ +#define CCL_INTMODE01_bp 1 /* Interrupt Mode for LUT0 bit 1 position. */ +#define CCL_INTMODE1_gm 0x0C /* Interrupt Mode for LUT1 group mask. */ +#define CCL_INTMODE1_gp 2 /* Interrupt Mode for LUT1 group position. */ +#define CCL_INTMODE10_bm (1<<2) /* Interrupt Mode for LUT1 bit 0 mask. */ +#define CCL_INTMODE10_bp 2 /* Interrupt Mode for LUT1 bit 0 position. */ +#define CCL_INTMODE11_bm (1<<3) /* Interrupt Mode for LUT1 bit 1 mask. */ +#define CCL_INTMODE11_bp 3 /* Interrupt Mode for LUT1 bit 1 position. */ +#define CCL_INTMODE2_gm 0x30 /* Interrupt Mode for LUT2 group mask. */ +#define CCL_INTMODE2_gp 4 /* Interrupt Mode for LUT2 group position. */ +#define CCL_INTMODE20_bm (1<<4) /* Interrupt Mode for LUT2 bit 0 mask. */ +#define CCL_INTMODE20_bp 4 /* Interrupt Mode for LUT2 bit 0 position. */ +#define CCL_INTMODE21_bm (1<<5) /* Interrupt Mode for LUT2 bit 1 mask. */ +#define CCL_INTMODE21_bp 5 /* Interrupt Mode for LUT2 bit 1 position. */ +#define CCL_INTMODE3_gm 0xC0 /* Interrupt Mode for LUT3 group mask. */ +#define CCL_INTMODE3_gp 6 /* Interrupt Mode for LUT3 group position. */ +#define CCL_INTMODE30_bm (1<<6) /* Interrupt Mode for LUT3 bit 0 mask. */ +#define CCL_INTMODE30_bp 6 /* Interrupt Mode for LUT3 bit 0 position. */ +#define CCL_INTMODE31_bm (1<<7) /* Interrupt Mode for LUT3 bit 1 mask. */ +#define CCL_INTMODE31_bp 7 /* Interrupt Mode for LUT3 bit 1 position. */ + +/* CCL.INTFLAGS bit masks and bit positions */ +#define CCL_INT_gm 0x0F /* Interrupt Flags group mask. */ +#define CCL_INT_gp 0 /* Interrupt Flags group position. */ +#define CCL_INT0_bm (1<<0) /* Interrupt Flags bit 0 mask. */ +#define CCL_INT0_bp 0 /* Interrupt Flags bit 0 position. */ +#define CCL_INT1_bm (1<<1) /* Interrupt Flags bit 1 mask. */ +#define CCL_INT1_bp 1 /* Interrupt Flags bit 1 position. */ +#define CCL_INT2_bm (1<<2) /* Interrupt Flags bit 2 mask. */ +#define CCL_INT2_bp 2 /* Interrupt Flags bit 2 position. */ +#define CCL_INT3_bm (1<<3) /* Interrupt Flags bit 3 mask. */ +#define CCL_INT3_bp 3 /* Interrupt Flags bit 3 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_CLKSRC_gm 0x0E /* Clock Source Selection group mask. */ +#define CCL_CLKSRC_gp 1 /* Clock Source Selection group position. */ +#define CCL_CLKSRC0_bm (1<<1) /* Clock Source Selection bit 0 mask. */ +#define CCL_CLKSRC0_bp 1 /* Clock Source Selection bit 0 position. */ +#define CCL_CLKSRC1_bm (1<<2) /* Clock Source Selection bit 1 mask. */ +#define CCL_CLKSRC1_bp 2 /* Clock Source Selection bit 1 position. */ +#define CCL_CLKSRC2_bm (1<<3) /* Clock Source Selection bit 2 mask. */ +#define CCL_CLKSRC2_bp 3 /* Clock Source Selection bit 2 position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_OUTEN_bm 0x40 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 6 /* Output Enable bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT2CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT2CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT2CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT3CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT3CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT3CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x7F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ +#define CLKCTRL_CAL20M6_bm (1<<6) /* Calibration bit 6 mask. */ +#define CLKCTRL_CAL20M6_bp 6 /* Calibration bit 6 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.SWEVENTA bit masks and bit positions */ +#define EVSYS_SWEVENTA_gm 0xFF /* Software event on channel group mask. */ +#define EVSYS_SWEVENTA_gp 0 /* Software event on channel group position. */ +#define EVSYS_SWEVENTA0_bm (1<<0) /* Software event on channel bit 0 mask. */ +#define EVSYS_SWEVENTA0_bp 0 /* Software event on channel bit 0 position. */ +#define EVSYS_SWEVENTA1_bm (1<<1) /* Software event on channel bit 1 mask. */ +#define EVSYS_SWEVENTA1_bp 1 /* Software event on channel bit 1 position. */ +#define EVSYS_SWEVENTA2_bm (1<<2) /* Software event on channel bit 2 mask. */ +#define EVSYS_SWEVENTA2_bp 2 /* Software event on channel bit 2 position. */ +#define EVSYS_SWEVENTA3_bm (1<<3) /* Software event on channel bit 3 mask. */ +#define EVSYS_SWEVENTA3_bp 3 /* Software event on channel bit 3 position. */ +#define EVSYS_SWEVENTA4_bm (1<<4) /* Software event on channel bit 4 mask. */ +#define EVSYS_SWEVENTA4_bp 4 /* Software event on channel bit 4 position. */ +#define EVSYS_SWEVENTA5_bm (1<<5) /* Software event on channel bit 5 mask. */ +#define EVSYS_SWEVENTA5_bp 5 /* Software event on channel bit 5 position. */ +#define EVSYS_SWEVENTA6_bm (1<<6) /* Software event on channel bit 6 mask. */ +#define EVSYS_SWEVENTA6_bp 6 /* Software event on channel bit 6 position. */ +#define EVSYS_SWEVENTA7_bm (1<<7) /* Software event on channel bit 7 mask. */ +#define EVSYS_SWEVENTA7_bp 7 /* Software event on channel bit 7 position. */ + +/* EVSYS.CHANNEL0 bit masks and bit positions */ +#define EVSYS_CHANNEL0_gm 0xFF /* Channel 0 generator select group mask. */ +#define EVSYS_CHANNEL0_gp 0 /* Channel 0 generator select group position. */ +#define EVSYS_CHANNEL00_bm (1<<0) /* Channel 0 generator select bit 0 mask. */ +#define EVSYS_CHANNEL00_bp 0 /* Channel 0 generator select bit 0 position. */ +#define EVSYS_CHANNEL01_bm (1<<1) /* Channel 0 generator select bit 1 mask. */ +#define EVSYS_CHANNEL01_bp 1 /* Channel 0 generator select bit 1 position. */ +#define EVSYS_CHANNEL02_bm (1<<2) /* Channel 0 generator select bit 2 mask. */ +#define EVSYS_CHANNEL02_bp 2 /* Channel 0 generator select bit 2 position. */ +#define EVSYS_CHANNEL03_bm (1<<3) /* Channel 0 generator select bit 3 mask. */ +#define EVSYS_CHANNEL03_bp 3 /* Channel 0 generator select bit 3 position. */ +#define EVSYS_CHANNEL04_bm (1<<4) /* Channel 0 generator select bit 4 mask. */ +#define EVSYS_CHANNEL04_bp 4 /* Channel 0 generator select bit 4 position. */ +#define EVSYS_CHANNEL05_bm (1<<5) /* Channel 0 generator select bit 5 mask. */ +#define EVSYS_CHANNEL05_bp 5 /* Channel 0 generator select bit 5 position. */ +#define EVSYS_CHANNEL06_bm (1<<6) /* Channel 0 generator select bit 6 mask. */ +#define EVSYS_CHANNEL06_bp 6 /* Channel 0 generator select bit 6 position. */ +#define EVSYS_CHANNEL07_bm (1<<7) /* Channel 0 generator select bit 7 mask. */ +#define EVSYS_CHANNEL07_bp 7 /* Channel 0 generator select bit 7 position. */ + +/* EVSYS.CHANNEL1 bit masks and bit positions */ +#define EVSYS_CHANNEL1_gm 0xFF /* Channel 1 generator select group mask. */ +#define EVSYS_CHANNEL1_gp 0 /* Channel 1 generator select group position. */ +#define EVSYS_CHANNEL10_bm (1<<0) /* Channel 1 generator select bit 0 mask. */ +#define EVSYS_CHANNEL10_bp 0 /* Channel 1 generator select bit 0 position. */ +#define EVSYS_CHANNEL11_bm (1<<1) /* Channel 1 generator select bit 1 mask. */ +#define EVSYS_CHANNEL11_bp 1 /* Channel 1 generator select bit 1 position. */ +#define EVSYS_CHANNEL12_bm (1<<2) /* Channel 1 generator select bit 2 mask. */ +#define EVSYS_CHANNEL12_bp 2 /* Channel 1 generator select bit 2 position. */ +#define EVSYS_CHANNEL13_bm (1<<3) /* Channel 1 generator select bit 3 mask. */ +#define EVSYS_CHANNEL13_bp 3 /* Channel 1 generator select bit 3 position. */ +#define EVSYS_CHANNEL14_bm (1<<4) /* Channel 1 generator select bit 4 mask. */ +#define EVSYS_CHANNEL14_bp 4 /* Channel 1 generator select bit 4 position. */ +#define EVSYS_CHANNEL15_bm (1<<5) /* Channel 1 generator select bit 5 mask. */ +#define EVSYS_CHANNEL15_bp 5 /* Channel 1 generator select bit 5 position. */ +#define EVSYS_CHANNEL16_bm (1<<6) /* Channel 1 generator select bit 6 mask. */ +#define EVSYS_CHANNEL16_bp 6 /* Channel 1 generator select bit 6 position. */ +#define EVSYS_CHANNEL17_bm (1<<7) /* Channel 1 generator select bit 7 mask. */ +#define EVSYS_CHANNEL17_bp 7 /* Channel 1 generator select bit 7 position. */ + +/* EVSYS.CHANNEL2 bit masks and bit positions */ +#define EVSYS_CHANNEL2_gm 0xFF /* Channel 2 generator select group mask. */ +#define EVSYS_CHANNEL2_gp 0 /* Channel 2 generator select group position. */ +#define EVSYS_CHANNEL20_bm (1<<0) /* Channel 2 generator select bit 0 mask. */ +#define EVSYS_CHANNEL20_bp 0 /* Channel 2 generator select bit 0 position. */ +#define EVSYS_CHANNEL21_bm (1<<1) /* Channel 2 generator select bit 1 mask. */ +#define EVSYS_CHANNEL21_bp 1 /* Channel 2 generator select bit 1 position. */ +#define EVSYS_CHANNEL22_bm (1<<2) /* Channel 2 generator select bit 2 mask. */ +#define EVSYS_CHANNEL22_bp 2 /* Channel 2 generator select bit 2 position. */ +#define EVSYS_CHANNEL23_bm (1<<3) /* Channel 2 generator select bit 3 mask. */ +#define EVSYS_CHANNEL23_bp 3 /* Channel 2 generator select bit 3 position. */ +#define EVSYS_CHANNEL24_bm (1<<4) /* Channel 2 generator select bit 4 mask. */ +#define EVSYS_CHANNEL24_bp 4 /* Channel 2 generator select bit 4 position. */ +#define EVSYS_CHANNEL25_bm (1<<5) /* Channel 2 generator select bit 5 mask. */ +#define EVSYS_CHANNEL25_bp 5 /* Channel 2 generator select bit 5 position. */ +#define EVSYS_CHANNEL26_bm (1<<6) /* Channel 2 generator select bit 6 mask. */ +#define EVSYS_CHANNEL26_bp 6 /* Channel 2 generator select bit 6 position. */ +#define EVSYS_CHANNEL27_bm (1<<7) /* Channel 2 generator select bit 7 mask. */ +#define EVSYS_CHANNEL27_bp 7 /* Channel 2 generator select bit 7 position. */ + +/* EVSYS.CHANNEL3 bit masks and bit positions */ +#define EVSYS_CHANNEL3_gm 0xFF /* Channel 3 generator select group mask. */ +#define EVSYS_CHANNEL3_gp 0 /* Channel 3 generator select group position. */ +#define EVSYS_CHANNEL30_bm (1<<0) /* Channel 3 generator select bit 0 mask. */ +#define EVSYS_CHANNEL30_bp 0 /* Channel 3 generator select bit 0 position. */ +#define EVSYS_CHANNEL31_bm (1<<1) /* Channel 3 generator select bit 1 mask. */ +#define EVSYS_CHANNEL31_bp 1 /* Channel 3 generator select bit 1 position. */ +#define EVSYS_CHANNEL32_bm (1<<2) /* Channel 3 generator select bit 2 mask. */ +#define EVSYS_CHANNEL32_bp 2 /* Channel 3 generator select bit 2 position. */ +#define EVSYS_CHANNEL33_bm (1<<3) /* Channel 3 generator select bit 3 mask. */ +#define EVSYS_CHANNEL33_bp 3 /* Channel 3 generator select bit 3 position. */ +#define EVSYS_CHANNEL34_bm (1<<4) /* Channel 3 generator select bit 4 mask. */ +#define EVSYS_CHANNEL34_bp 4 /* Channel 3 generator select bit 4 position. */ +#define EVSYS_CHANNEL35_bm (1<<5) /* Channel 3 generator select bit 5 mask. */ +#define EVSYS_CHANNEL35_bp 5 /* Channel 3 generator select bit 5 position. */ +#define EVSYS_CHANNEL36_bm (1<<6) /* Channel 3 generator select bit 6 mask. */ +#define EVSYS_CHANNEL36_bp 6 /* Channel 3 generator select bit 6 position. */ +#define EVSYS_CHANNEL37_bm (1<<7) /* Channel 3 generator select bit 7 mask. */ +#define EVSYS_CHANNEL37_bp 7 /* Channel 3 generator select bit 7 position. */ + +/* EVSYS.CHANNEL4 bit masks and bit positions */ +#define EVSYS_CHANNEL4_gm 0xFF /* Channel 4 generator select group mask. */ +#define EVSYS_CHANNEL4_gp 0 /* Channel 4 generator select group position. */ +#define EVSYS_CHANNEL40_bm (1<<0) /* Channel 4 generator select bit 0 mask. */ +#define EVSYS_CHANNEL40_bp 0 /* Channel 4 generator select bit 0 position. */ +#define EVSYS_CHANNEL41_bm (1<<1) /* Channel 4 generator select bit 1 mask. */ +#define EVSYS_CHANNEL41_bp 1 /* Channel 4 generator select bit 1 position. */ +#define EVSYS_CHANNEL42_bm (1<<2) /* Channel 4 generator select bit 2 mask. */ +#define EVSYS_CHANNEL42_bp 2 /* Channel 4 generator select bit 2 position. */ +#define EVSYS_CHANNEL43_bm (1<<3) /* Channel 4 generator select bit 3 mask. */ +#define EVSYS_CHANNEL43_bp 3 /* Channel 4 generator select bit 3 position. */ +#define EVSYS_CHANNEL44_bm (1<<4) /* Channel 4 generator select bit 4 mask. */ +#define EVSYS_CHANNEL44_bp 4 /* Channel 4 generator select bit 4 position. */ +#define EVSYS_CHANNEL45_bm (1<<5) /* Channel 4 generator select bit 5 mask. */ +#define EVSYS_CHANNEL45_bp 5 /* Channel 4 generator select bit 5 position. */ +#define EVSYS_CHANNEL46_bm (1<<6) /* Channel 4 generator select bit 6 mask. */ +#define EVSYS_CHANNEL46_bp 6 /* Channel 4 generator select bit 6 position. */ +#define EVSYS_CHANNEL47_bm (1<<7) /* Channel 4 generator select bit 7 mask. */ +#define EVSYS_CHANNEL47_bp 7 /* Channel 4 generator select bit 7 position. */ + +/* EVSYS.CHANNEL5 bit masks and bit positions */ +#define EVSYS_CHANNEL5_gm 0xFF /* Channel 5 generator select group mask. */ +#define EVSYS_CHANNEL5_gp 0 /* Channel 5 generator select group position. */ +#define EVSYS_CHANNEL50_bm (1<<0) /* Channel 5 generator select bit 0 mask. */ +#define EVSYS_CHANNEL50_bp 0 /* Channel 5 generator select bit 0 position. */ +#define EVSYS_CHANNEL51_bm (1<<1) /* Channel 5 generator select bit 1 mask. */ +#define EVSYS_CHANNEL51_bp 1 /* Channel 5 generator select bit 1 position. */ +#define EVSYS_CHANNEL52_bm (1<<2) /* Channel 5 generator select bit 2 mask. */ +#define EVSYS_CHANNEL52_bp 2 /* Channel 5 generator select bit 2 position. */ +#define EVSYS_CHANNEL53_bm (1<<3) /* Channel 5 generator select bit 3 mask. */ +#define EVSYS_CHANNEL53_bp 3 /* Channel 5 generator select bit 3 position. */ +#define EVSYS_CHANNEL54_bm (1<<4) /* Channel 5 generator select bit 4 mask. */ +#define EVSYS_CHANNEL54_bp 4 /* Channel 5 generator select bit 4 position. */ +#define EVSYS_CHANNEL55_bm (1<<5) /* Channel 5 generator select bit 5 mask. */ +#define EVSYS_CHANNEL55_bp 5 /* Channel 5 generator select bit 5 position. */ +#define EVSYS_CHANNEL56_bm (1<<6) /* Channel 5 generator select bit 6 mask. */ +#define EVSYS_CHANNEL56_bp 6 /* Channel 5 generator select bit 6 position. */ +#define EVSYS_CHANNEL57_bm (1<<7) /* Channel 5 generator select bit 7 mask. */ +#define EVSYS_CHANNEL57_bp 7 /* Channel 5 generator select bit 7 position. */ + +/* EVSYS.USERCCLLUT0A bit masks and bit positions */ +#define EVSYS_USER_gm 0xFF /* Channel selector group mask. */ +#define EVSYS_USER_gp 0 /* Channel selector group position. */ +#define EVSYS_USER0_bm (1<<0) /* Channel selector bit 0 mask. */ +#define EVSYS_USER0_bp 0 /* Channel selector bit 0 position. */ +#define EVSYS_USER1_bm (1<<1) /* Channel selector bit 1 mask. */ +#define EVSYS_USER1_bp 1 /* Channel selector bit 1 position. */ +#define EVSYS_USER2_bm (1<<2) /* Channel selector bit 2 mask. */ +#define EVSYS_USER2_bp 2 /* Channel selector bit 2 position. */ +#define EVSYS_USER3_bm (1<<3) /* Channel selector bit 3 mask. */ +#define EVSYS_USER3_bp 3 /* Channel selector bit 3 position. */ +#define EVSYS_USER4_bm (1<<4) /* Channel selector bit 4 mask. */ +#define EVSYS_USER4_bp 4 /* Channel selector bit 4 position. */ +#define EVSYS_USER5_bm (1<<5) /* Channel selector bit 5 mask. */ +#define EVSYS_USER5_bp 5 /* Channel selector bit 5 position. */ +#define EVSYS_USER6_bm (1<<6) /* Channel selector bit 6 mask. */ +#define EVSYS_USER6_bp 6 /* Channel selector bit 6 position. */ +#define EVSYS_USER7_bm (1<<7) /* Channel selector bit 7 mask. */ +#define EVSYS_USER7_bp 7 /* Channel selector bit 7 position. */ + +/* EVSYS.USERCCLLUT0B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT1A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT1B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT2A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT2B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT3A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT3B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERADC0START bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTC bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART0IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART1IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA0CNTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA0CNTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB0CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB0COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB1CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB1COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMBIST - BIST in the NVMCTRL module */ +/* NVMBIST.CTRLA bit masks and bit positions */ +#define NVMBIST_CMD_gm 0x07 /* Command group mask. */ +#define NVMBIST_CMD_gp 0 /* Command group position. */ +#define NVMBIST_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMBIST_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMBIST_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMBIST_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMBIST_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMBIST_CMD2_bp 2 /* Command bit 2 position. */ +#define NVMBIST_SAF_bm 0x08 /* Stop at fault bit mask. */ +#define NVMBIST_SAF_bp 3 /* Stop at fault bit position. */ + +/* NVMBIST.ADDRPAT bit masks and bit positions */ +#define NVMBIST_XMODE_gm 0x03 /* X address mode group mask. */ +#define NVMBIST_XMODE_gp 0 /* X address mode group position. */ +#define NVMBIST_XMODE0_bm (1<<0) /* X address mode bit 0 mask. */ +#define NVMBIST_XMODE0_bp 0 /* X address mode bit 0 position. */ +#define NVMBIST_XMODE1_bm (1<<1) /* X address mode bit 1 mask. */ +#define NVMBIST_XMODE1_bp 1 /* X address mode bit 1 position. */ +#define NVMBIST_YMODE_gm 0x0C /* Y address mode group mask. */ +#define NVMBIST_YMODE_gp 2 /* Y address mode group position. */ +#define NVMBIST_YMODE0_bm (1<<2) /* Y address mode bit 0 mask. */ +#define NVMBIST_YMODE0_bp 2 /* Y address mode bit 0 position. */ +#define NVMBIST_YMODE1_bm (1<<3) /* Y address mode bit 1 mask. */ +#define NVMBIST_YMODE1_bp 3 /* Y address mode bit 1 position. */ +#define NVMBIST_AMODE_gm 0x70 /* Address mode group mask. */ +#define NVMBIST_AMODE_gp 4 /* Address mode group position. */ +#define NVMBIST_AMODE0_bm (1<<4) /* Address mode bit 0 mask. */ +#define NVMBIST_AMODE0_bp 4 /* Address mode bit 0 position. */ +#define NVMBIST_AMODE1_bm (1<<5) /* Address mode bit 1 mask. */ +#define NVMBIST_AMODE1_bp 5 /* Address mode bit 1 position. */ +#define NVMBIST_AMODE2_bm (1<<6) /* Address mode bit 2 mask. */ +#define NVMBIST_AMODE2_bp 6 /* Address mode bit 2 position. */ + +/* NVMBIST.DATAPAT bit masks and bit positions */ +#define NVMBIST_PATTERN_gm 0x03 /* Data check pattern group mask. */ +#define NVMBIST_PATTERN_gp 0 /* Data check pattern group position. */ +#define NVMBIST_PATTERN0_bm (1<<0) /* Data check pattern bit 0 mask. */ +#define NVMBIST_PATTERN0_bp 0 /* Data check pattern bit 0 position. */ +#define NVMBIST_PATTERN1_bm (1<<1) /* Data check pattern bit 1 mask. */ +#define NVMBIST_PATTERN1_bp 1 /* Data check pattern bit 1 position. */ + +/* NVMBIST.STATUS bit masks and bit positions */ +#define NVMBIST_STATE_gm 0x0F /* FSM State group mask. */ +#define NVMBIST_STATE_gp 0 /* FSM State group position. */ +#define NVMBIST_STATE0_bm (1<<0) /* FSM State bit 0 mask. */ +#define NVMBIST_STATE0_bp 0 /* FSM State bit 0 position. */ +#define NVMBIST_STATE1_bm (1<<1) /* FSM State bit 1 mask. */ +#define NVMBIST_STATE1_bp 1 /* FSM State bit 1 position. */ +#define NVMBIST_STATE2_bm (1<<2) /* FSM State bit 2 mask. */ +#define NVMBIST_STATE2_bp 2 /* FSM State bit 2 position. */ +#define NVMBIST_STATE3_bm (1<<3) /* FSM State bit 3 mask. */ +#define NVMBIST_STATE3_bp 3 /* FSM State bit 3 position. */ + +/* NVMBIST.CNT bit masks and bit positions */ +#define NVMBIST_CNT_gm 0x7FF /* Faults counter group mask. */ +#define NVMBIST_CNT_gp 0 /* Faults counter group position. */ +#define NVMBIST_CNT0_bm (1<<0) /* Faults counter bit 0 mask. */ +#define NVMBIST_CNT0_bp 0 /* Faults counter bit 0 position. */ +#define NVMBIST_CNT1_bm (1<<1) /* Faults counter bit 1 mask. */ +#define NVMBIST_CNT1_bp 1 /* Faults counter bit 1 position. */ +#define NVMBIST_CNT2_bm (1<<2) /* Faults counter bit 2 mask. */ +#define NVMBIST_CNT2_bp 2 /* Faults counter bit 2 position. */ +#define NVMBIST_CNT3_bm (1<<3) /* Faults counter bit 3 mask. */ +#define NVMBIST_CNT3_bp 3 /* Faults counter bit 3 position. */ +#define NVMBIST_CNT4_bm (1<<4) /* Faults counter bit 4 mask. */ +#define NVMBIST_CNT4_bp 4 /* Faults counter bit 4 position. */ +#define NVMBIST_CNT5_bm (1<<5) /* Faults counter bit 5 mask. */ +#define NVMBIST_CNT5_bp 5 /* Faults counter bit 5 position. */ +#define NVMBIST_CNT6_bm (1<<6) /* Faults counter bit 6 mask. */ +#define NVMBIST_CNT6_bp 6 /* Faults counter bit 6 position. */ +#define NVMBIST_CNT7_bm (1<<7) /* Faults counter bit 7 mask. */ +#define NVMBIST_CNT7_bp 7 /* Faults counter bit 7 position. */ +#define NVMBIST_CNT8_bm (1<<8) /* Faults counter bit 8 mask. */ +#define NVMBIST_CNT8_bp 8 /* Faults counter bit 8 position. */ +#define NVMBIST_CNT9_bm (1<<9) /* Faults counter bit 9 mask. */ +#define NVMBIST_CNT9_bp 9 /* Faults counter bit 9 position. */ +#define NVMBIST_CNT10_bm (1<<10) /* Faults counter bit 10 mask. */ +#define NVMBIST_CNT10_bp 10 /* Faults counter bit 10 position. */ + +/* NVMBIST.END bit masks and bit positions */ +#define NVMBIST_END_gm 0xFFFFFF /* group mask. */ +#define NVMBIST_END_gp 0 /* group position. */ +#define NVMBIST_END0_bm (1<<0) /* bit 0 mask. */ +#define NVMBIST_END0_bp 0 /* bit 0 position. */ +#define NVMBIST_END1_bm (1<<1) /* bit 1 mask. */ +#define NVMBIST_END1_bp 1 /* bit 1 position. */ +#define NVMBIST_END2_bm (1<<2) /* bit 2 mask. */ +#define NVMBIST_END2_bp 2 /* bit 2 position. */ +#define NVMBIST_END3_bm (1<<3) /* bit 3 mask. */ +#define NVMBIST_END3_bp 3 /* bit 3 position. */ +#define NVMBIST_END4_bm (1<<4) /* bit 4 mask. */ +#define NVMBIST_END4_bp 4 /* bit 4 position. */ +#define NVMBIST_END5_bm (1<<5) /* bit 5 mask. */ +#define NVMBIST_END5_bp 5 /* bit 5 position. */ +#define NVMBIST_END6_bm (1<<6) /* bit 6 mask. */ +#define NVMBIST_END6_bp 6 /* bit 6 position. */ +#define NVMBIST_END7_bm (1<<7) /* bit 7 mask. */ +#define NVMBIST_END7_bp 7 /* bit 7 position. */ +#define NVMBIST_END8_bm (1<<8) /* bit 8 mask. */ +#define NVMBIST_END8_bp 8 /* bit 8 position. */ +#define NVMBIST_END9_bm (1<<9) /* bit 9 mask. */ +#define NVMBIST_END9_bp 9 /* bit 9 position. */ +#define NVMBIST_END10_bm (1<<10) /* bit 10 mask. */ +#define NVMBIST_END10_bp 10 /* bit 10 position. */ +#define NVMBIST_END11_bm (1<<11) /* bit 11 mask. */ +#define NVMBIST_END11_bp 11 /* bit 11 position. */ +#define NVMBIST_END12_bm (1<<12) /* bit 12 mask. */ +#define NVMBIST_END12_bp 12 /* bit 12 position. */ +#define NVMBIST_END13_bm (1<<13) /* bit 13 mask. */ +#define NVMBIST_END13_bp 13 /* bit 13 position. */ +#define NVMBIST_END14_bm (1<<14) /* bit 14 mask. */ +#define NVMBIST_END14_bp 14 /* bit 14 position. */ +#define NVMBIST_END15_bm (1<<15) /* bit 15 mask. */ +#define NVMBIST_END15_bp 15 /* bit 15 position. */ +#define NVMBIST_END16_bm (1<<16) /* bit 16 mask. */ +#define NVMBIST_END16_bp 16 /* bit 16 position. */ +#define NVMBIST_END17_bm (1<<17) /* bit 17 mask. */ +#define NVMBIST_END17_bp 17 /* bit 17 position. */ +#define NVMBIST_END18_bm (1<<18) /* bit 18 mask. */ +#define NVMBIST_END18_bp 18 /* bit 18 position. */ +#define NVMBIST_END19_bm (1<<19) /* bit 19 mask. */ +#define NVMBIST_END19_bp 19 /* bit 19 position. */ +#define NVMBIST_END20_bm (1<<20) /* bit 20 mask. */ +#define NVMBIST_END20_bp 20 /* bit 20 position. */ +#define NVMBIST_END21_bm (1<<21) /* bit 21 mask. */ +#define NVMBIST_END21_bp 21 /* bit 21 position. */ +#define NVMBIST_END22_bm (1<<22) /* bit 22 mask. */ +#define NVMBIST_END22_bp 22 /* bit 22 position. */ +#define NVMBIST_END23_bm (1<<23) /* bit 23 mask. */ +#define NVMBIST_END23_bp 23 /* bit 23 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PORTCTRL bit masks and bit positions */ +#define PORT_SRL_bm 0x01 /* Slew Rate Limit Enable bit mask. */ +#define PORT_SRL_bp 0 /* Slew Rate Limit Enable bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.EVSYSROUTEA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_EVOUT3_bm 0x08 /* Event Output 3 bit mask. */ +#define PORTMUX_EVOUT3_bp 3 /* Event Output 3 bit position. */ +#define PORTMUX_EVOUT4_bm 0x10 /* Event Output 4 bit mask. */ +#define PORTMUX_EVOUT4_bp 4 /* Event Output 4 bit position. */ +#define PORTMUX_EVOUT5_bm 0x20 /* Event Output 5 bit mask. */ +#define PORTMUX_EVOUT5_bp 5 /* Event Output 5 bit position. */ + +/* PORTMUX.CCLROUTEA bit masks and bit positions */ +#define PORTMUX_LUT0_bm 0x01 /* CCL LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 0 /* CCL LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x02 /* CCL LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 1 /* CCL LUT1 bit position. */ +#define PORTMUX_LUT2_bm 0x04 /* CCL LUT2 bit mask. */ +#define PORTMUX_LUT2_bp 2 /* CCL LUT2 bit position. */ +#define PORTMUX_LUT3_bm 0x08 /* CCL LUT3 bit mask. */ +#define PORTMUX_LUT3_bp 3 /* CCL LUT3 bit position. */ + +/* PORTMUX.USARTROUTEA bit masks and bit positions */ +#define PORTMUX_USART0_gm 0x03 /* Port Multiplexer USART0 group mask. */ +#define PORTMUX_USART0_gp 0 /* Port Multiplexer USART0 group position. */ +#define PORTMUX_USART00_bm (1<<0) /* Port Multiplexer USART0 bit 0 mask. */ +#define PORTMUX_USART00_bp 0 /* Port Multiplexer USART0 bit 0 position. */ +#define PORTMUX_USART01_bm (1<<1) /* Port Multiplexer USART0 bit 1 mask. */ +#define PORTMUX_USART01_bp 1 /* Port Multiplexer USART0 bit 1 position. */ +#define PORTMUX_USART1_gm 0x0C /* Port Multiplexer USART1 group mask. */ +#define PORTMUX_USART1_gp 2 /* Port Multiplexer USART1 group position. */ +#define PORTMUX_USART10_bm (1<<2) /* Port Multiplexer USART1 bit 0 mask. */ +#define PORTMUX_USART10_bp 2 /* Port Multiplexer USART1 bit 0 position. */ +#define PORTMUX_USART11_bm (1<<3) /* Port Multiplexer USART1 bit 1 mask. */ +#define PORTMUX_USART11_bp 3 /* Port Multiplexer USART1 bit 1 position. */ + +/* PORTMUX.SPIROUTEA bit masks and bit positions */ +#define PORTMUX_SPI0_gm 0x03 /* Port Multiplexer SPI0 group mask. */ +#define PORTMUX_SPI0_gp 0 /* Port Multiplexer SPI0 group position. */ +#define PORTMUX_SPI00_bm (1<<0) /* Port Multiplexer SPI0 bit 0 mask. */ +#define PORTMUX_SPI00_bp 0 /* Port Multiplexer SPI0 bit 0 position. */ +#define PORTMUX_SPI01_bm (1<<1) /* Port Multiplexer SPI0 bit 1 mask. */ +#define PORTMUX_SPI01_bp 1 /* Port Multiplexer SPI0 bit 1 position. */ +#define PORTMUX_TWI0_gm 0x30 /* Port Multiplexer TWI0 group mask. */ +#define PORTMUX_TWI0_gp 4 /* Port Multiplexer TWI0 group position. */ +#define PORTMUX_TWI00_bm (1<<4) /* Port Multiplexer TWI0 bit 0 mask. */ +#define PORTMUX_TWI00_bp 4 /* Port Multiplexer TWI0 bit 0 position. */ +#define PORTMUX_TWI01_bm (1<<5) /* Port Multiplexer TWI0 bit 1 mask. */ +#define PORTMUX_TWI01_bp 5 /* Port Multiplexer TWI0 bit 1 position. */ + +/* PORTMUX.TCAROUTEA bit masks and bit positions */ +#define PORTMUX_TCA0_gm 0x07 /* Port Multiplexer TCA0 group mask. */ +#define PORTMUX_TCA0_gp 0 /* Port Multiplexer TCA0 group position. */ +#define PORTMUX_TCA00_bm (1<<0) /* Port Multiplexer TCA0 bit 0 mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 bit 0 position. */ +#define PORTMUX_TCA01_bm (1<<1) /* Port Multiplexer TCA0 bit 1 mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 bit 1 position. */ +#define PORTMUX_TCA02_bm (1<<2) /* Port Multiplexer TCA0 bit 2 mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 bit 2 position. */ + +/* PORTMUX.TCBROUTEA bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ +#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ +#define PORTMUX_TCB2_bm 0x04 /* Port Multiplexer TCB2 bit mask. */ +#define PORTMUX_TCB2_bp 2 /* Port Multiplexer TCB2 bit position. */ +#define PORTMUX_TCB3_bm 0x08 /* Port Multiplexer TCB3 bit mask. */ +#define PORTMUX_TCB3_bp 3 /* Port Multiplexer TCB3 bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_CORREN_bm 0x04 /* Correction enable bit mask. */ +#define RTC_CORREN_bp 2 /* Correction enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_ERROR_gm 0x7F /* Error Correction Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Correction Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Correction Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Correction Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Correction Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Correction Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Correction Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Correction Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Correction Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Correction Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Correction Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Correction Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Correction Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Correction Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Correction Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Correction Value bit 6 position. */ +#define RTC_SIGN_bm 0x80 /* Error Correction Sign Bit bit mask. */ +#define RTC_SIGN_bp 7 /* Error Correction Sign Bit bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Mode Wait for Receive bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Mode Wait for Receive bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + + +/* SYSCFG.OCDMS bit masks and bit positions */ +#define SYSCFG_OCDMR_bm 0x01 /* OCD Message Read bit mask. */ +#define SYSCFG_OCDMR_bp 0 /* OCD Message Read bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ +#define TCA_SINGLE_RUNSTDBY_bm 0x80 /* Run in Standby bit mask. */ +#define TCA_SINGLE_RUNSTDBY_bp 7 /* Run in Standby bit position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTAEI_bm 0x01 /* Count on Event Input A bit mask. */ +#define TCA_SINGLE_CNTAEI_bp 0 /* Count on Event Input A bit position. */ +#define TCA_SINGLE_EVACTA_gm 0x0E /* Event Action A group mask. */ +#define TCA_SINGLE_EVACTA_gp 1 /* Event Action A group position. */ +#define TCA_SINGLE_EVACTA0_bm (1<<1) /* Event Action A bit 0 mask. */ +#define TCA_SINGLE_EVACTA0_bp 1 /* Event Action A bit 0 position. */ +#define TCA_SINGLE_EVACTA1_bm (1<<2) /* Event Action A bit 1 mask. */ +#define TCA_SINGLE_EVACTA1_bp 2 /* Event Action A bit 1 position. */ +#define TCA_SINGLE_EVACTA2_bm (1<<3) /* Event Action A bit 2 mask. */ +#define TCA_SINGLE_EVACTA2_bp 3 /* Event Action A bit 2 position. */ +#define TCA_SINGLE_CNTBEI_bm 0x10 /* Count on Event Input B bit mask. */ +#define TCA_SINGLE_CNTBEI_bp 4 /* Count on Event Input B bit position. */ +#define TCA_SINGLE_EVACTB_gm 0xE0 /* Event Action B group mask. */ +#define TCA_SINGLE_EVACTB_gp 5 /* Event Action B group position. */ +#define TCA_SINGLE_EVACTB0_bm (1<<5) /* Event Action B bit 0 mask. */ +#define TCA_SINGLE_EVACTB0_bp 5 /* Event Action B bit 0 position. */ +#define TCA_SINGLE_EVACTB1_bm (1<<6) /* Event Action B bit 1 mask. */ +#define TCA_SINGLE_EVACTB1_bp 6 /* Event Action B bit 1 position. */ +#define TCA_SINGLE_EVACTB2_bm (1<<7) /* Event Action B bit 2 mask. */ +#define TCA_SINGLE_EVACTB2_bp 7 /* Event Action B bit 2 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ +#define TCA_SPLIT_RUNSTDBY_bm 0x80 /* Run in Standby bit mask. */ +#define TCA_SPLIT_RUNSTDBY_bp 7 /* Run in Standby bit position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TCA_SPLIT_CMDEN_gp 0 /* Command Enable group position. */ +#define TCA_SPLIT_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TCA_SPLIT_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TCA_SPLIT_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TCA_SPLIT_CMDEN1_bp 1 /* Command Enable bit 1 position. */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMDEN is already defined. */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x0E /* TCB Clock group mask. */ +#define TCB_CLKSEL_gp 1 /* TCB Clock group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* TCB Clock bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* TCB Clock bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* TCB Clock bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* TCB Clock bit 1 position. */ +#define TCB_CLKSEL2_bm (1<<3) /* TCB Clock bit 2 mask. */ +#define TCB_CLKSEL2_bp 3 /* TCB Clock bit 2 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_CASCADE_bm 0x20 /* Cascade two timers bit mask. */ +#define TCB_CASCADE_bp 5 /* Cascade two timers bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ +#define TCB_OVF_bm 0x02 /* Overflow bit mask. */ +#define TCB_OVF_bp 1 /* Overflow bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ +/* TCB_OVF is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Permissive Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Permissive Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_bm 0x01 /* RS485 Mode internal transmitter bit mask. */ +#define USART_RS485_bp 0 /* RS485 Mode internal transmitter bit position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.CTRLD bit masks and bit positions */ +#define USART_ABW_gm 0xC0 /* Auto Baud Window group mask. */ +#define USART_ABW_gp 6 /* Auto Baud Window group position. */ +#define USART_ABW0_bm (1<<6) /* Auto Baud Window bit 0 mask. */ +#define USART_ABW0_bp 6 /* Auto Baud Window bit 0 position. */ +#define USART_ABW1_bm (1<<7) /* Auto Baud Window bit 1 mask. */ +#define USART_ABW1_bp 7 /* Auto Baud Window bit 1 position. */ + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_AC0REFSEL_gm 0x07 /* AC0 reference select group mask. */ +#define VREF_AC0REFSEL_gp 0 /* AC0 reference select group position. */ +#define VREF_AC0REFSEL0_bm (1<<0) /* AC0 reference select bit 0 mask. */ +#define VREF_AC0REFSEL0_bp 0 /* AC0 reference select bit 0 position. */ +#define VREF_AC0REFSEL1_bm (1<<1) /* AC0 reference select bit 1 mask. */ +#define VREF_AC0REFSEL1_bp 1 /* AC0 reference select bit 1 position. */ +#define VREF_AC0REFSEL2_bm (1<<2) /* AC0 reference select bit 2 mask. */ +#define VREF_AC0REFSEL2_bp 2 /* AC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_AC0REFEN_bm 0x01 /* AC0 DACREF reference enable bit mask. */ +#define VREF_AC0REFEN_bp 0 /* AC0 DACREF reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ +#define VREF_NVMREFEN_bm 0x04 /* NVM reference enable bit mask. */ +#define VREF_NVMREFEN_bp 2 /* NVM reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 3 +#define RTC_CNT_vect _VECTOR(3) /* */ +#define RTC_PIT_vect_num 4 +#define RTC_PIT_vect _VECTOR(4) /* */ + +/* CCL interrupt vectors */ +#define CCL_CCL_vect_num 5 +#define CCL_CCL_vect _VECTOR(5) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 6 +#define PORTA_PORT_vect _VECTOR(6) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 7 +#define PORTB_PORT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 14 +#define TWI0_TWIS_vect _VECTOR(14) /* */ +#define TWI0_TWIM_vect_num 15 +#define TWI0_TWIM_vect _VECTOR(15) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 16 +#define SPI0_INT_vect _VECTOR(16) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 17 +#define USART0_RXC_vect _VECTOR(17) /* */ +#define USART0_DRE_vect_num 18 +#define USART0_DRE_vect _VECTOR(18) /* */ +#define USART0_TXC_vect_num 19 +#define USART0_TXC_vect _VECTOR(19) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 20 +#define AC0_AC_vect _VECTOR(20) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_ERROR_vect_num 21 +#define ADC0_ERROR_vect _VECTOR(21) /* */ +#define ADC0_RESRDY_vect_num 22 +#define ADC0_RESRDY_vect _VECTOR(22) /* */ +#define ADC0_SAMPRDY_vect_num 23 +#define ADC0_SAMPRDY_vect _VECTOR(23) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 24 +#define PORTC_PORT_vect _VECTOR(24) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 25 +#define TCB1_INT_vect _VECTOR(25) /* */ + +/* USART1 interrupt vectors */ +#define USART1_RXC_vect_num 26 +#define USART1_RXC_vect _VECTOR(26) /* */ +#define USART1_DRE_vect_num 27 +#define USART1_DRE_vect _VECTOR(27) /* */ +#define USART1_TXC_vect_num 28 +#define USART1_TXC_vect _VECTOR(28) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 29 +#define NVMCTRL_EE_vect _VECTOR(29) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (30 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (49152) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (49152U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3800) +# define INTERNAL_SRAM_SIZE (2048) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3800U) +# define INTERNAL_SRAM_SIZE (2048U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (16384) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (16384U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (16384) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (16384U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x2A + + +#endif /* #ifdef _AVR_ATTINY1624_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn1626.h b/hardware/tools/avr/avr/include/avr/iotn1626.h new file mode 100644 index 0000000000000000000000000000000000000000..87b60355e77153c9dd59cb940299b1f3e90223ba --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn1626.h @@ -0,0 +1,5497 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn1626.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY1626_H_INCLUDED +#define _AVR_ATTINY1626_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPZ _SFR_MEM8(0x003B) /* Extended Z-pointer Register */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[1]; + register8_t DACREF; /* Referance scale control */ + register8_t reserved_3[1]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Both Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_PIN2_gc = (0x02<<0), /* Negative Pin 2 */ + AC_MUXNEG_DACREF_gc = (0x03<<0), /* DAC Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status register */ + register8_t DBGCTRL; /* Debug Control */ + register8_t CTRLE; /* Control E */ + register8_t CTRLF; /* Control F */ + register8_t COMMAND; /* Command register */ + register8_t PGACTRL; /* PGA Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t MUXNEG; /* Negative mux input */ + register8_t reserved_1[2]; + _DWORDREGISTER(RESULT); /* Result */ + _WORDREGISTER(SAMPLE); /* Sample */ + register8_t reserved_2[2]; + register8_t TEMP0; /* Temporary Data 0 */ + register8_t TEMP1; /* Temporary Data 1 */ + register8_t TEMP2; /* Temporary Data 2 */ + register8_t reserved_3[1]; + _WORDREGISTER(WINLT); /* Window Low Threshold */ + _WORDREGISTER(WINHT); /* Window High Threshold */ + register8_t reserved_4[32]; +} ADC_t; + +/* ADC PGA Sample Duration select */ +typedef enum ADC_ADCPGASAMPDUR_enum +{ + ADC_ADCPGASAMPDUR_6CLK_gc = (0x00<<1), /* 6 ADC cycles */ + ADC_ADCPGASAMPDUR_15CLK_gc = (0x01<<1), /* 15 ADC cycles */ + ADC_ADCPGASAMPDUR_20CLK_gc = (0x02<<1), /* 20 ADC cycles */ + ADC_ADCPGASAMPDUR_32CLK_gc = (0x03<<1), /* 32 ADC cycles */ +} ADC_ADCPGASAMPDUR_t; + +/* Gain select */ +typedef enum ADC_GAIN_enum +{ + ADC_GAIN_1X_gc = (0x00<<5), /* 1X Gain */ + ADC_GAIN_2X_gc = (0x01<<5), /* 2X Gain */ + ADC_GAIN_4X_gc = (0x02<<5), /* 4X Gain */ + ADC_GAIN_8X_gc = (0x03<<5), /* 8X Gain */ + ADC_GAIN_16X_gc = (0x04<<5), /* 16X Gain */ +} ADC_GAIN_t; + +/* Mode select */ +typedef enum ADC_MODE_enum +{ + ADC_MODE_SINGLE_8BIT_gc = (0x00<<4), /* Single Conversion 8-bit */ + ADC_MODE_SINGLE_12BIT_gc = (0x01<<4), /* Single Conversion 12-bit */ + ADC_MODE_SERIES_gc = (0x02<<4), /* Series Accumulation */ + ADC_MODE_SERIES_SCALING_gc = (0x03<<4), /* Series Accumulation with Scaling */ + ADC_MODE_BURST_gc = (0x04<<4), /* Burst Accumulation */ + ADC_MODE_BURST_SCALING_gc = (0x05<<4), /* Burst Accumulation with Scaling */ +} ADC_MODE_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXNEG_enum +{ + ADC_MUXNEG_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXNEG_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXNEG_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXNEG_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXNEG_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXNEG_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXNEG_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXNEG_GND_gc = (0x30<<0), /* Ground */ + ADC_MUXNEG_VDDDIV10_gc = (0x31<<0), /* VDD/10 */ + ADC_MUXNEG_DAC_gc = (0x33<<0), /* DAC */ +} ADC_MUXNEG_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ + ADC_MUXPOS_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ + ADC_MUXPOS_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ + ADC_MUXPOS_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ + ADC_MUXPOS_GND_gc = (0x30<<0), /* Ground */ + ADC_MUXPOS_VDDDIV10_gc = (0x31<<0), /* VDD/10 */ + ADC_MUXPOS_TEMPSENSE_gc = (0x32<<0), /* Temperature sensor */ + ADC_MUXPOS_DAC_gc = (0x33<<0), /* DAC */ +} ADC_MUXPOS_t; + +/* PGA BIAS Select select */ +typedef enum ADC_PGABIASSEL_enum +{ + ADC_PGABIASSEL_1X_gc = (0x00<<3), /* 1x BIAS curren */ + ADC_PGABIASSEL_3_4X_gc = (0x01<<3), /* 3/4x BIAS current */ + ADC_PGABIASSEL_1_2X_gc = (0x02<<3), /* 1/2x BIAS current */ + ADC_PGABIASSEL_1_4X_gc = (0x03<<3), /* 1/4x BIAS current */ +} ADC_PGABIASSEL_t; + +/* Prescaler Value select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* System clock divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* System clock divided by 4 */ + ADC_PRESC_DIV6_gc = (0x02<<0), /* System clock divided by 6 */ + ADC_PRESC_DIV8_gc = (0x03<<0), /* System clock divided by 8 */ + ADC_PRESC_DIV10_gc = (0x04<<0), /* System clock divided by 10 */ + ADC_PRESC_DIV12_gc = (0x05<<0), /* System clock divided by 12 */ + ADC_PRESC_DIV14_gc = (0x06<<0), /* System clock divided by 14 */ + ADC_PRESC_DIV16_gc = (0x07<<0), /* System clock divided by 16 */ + ADC_PRESC_DIV20_gc = (0x08<<0), /* System clock divided by 20 */ + ADC_PRESC_DIV24_gc = (0x09<<0), /* System clock divided by 24 */ + ADC_PRESC_DIV28_gc = (0x0A<<0), /* System clock divided by 28 */ + ADC_PRESC_DIV32_gc = (0x0B<<0), /* System clock divided by 32 */ + ADC_PRESC_DIV40_gc = (0x0C<<0), /* System clock divided by 40 */ + ADC_PRESC_DIV48_gc = (0x0D<<0), /* System clock divided by 48 */ + ADC_PRESC_DIV56_gc = (0x0E<<0), /* System clock divided by 56 */ + ADC_PRESC_DIV64_gc = (0x0F<<0), /* System clock divided by 64 */ +} ADC_PRESC_t; + +/* Reference select select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_VDD_gc = (0x00<<0), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<0), /* External Reference */ + ADC_REFSEL_1024MV_gc = (0x04<<0), /* Internal 1.024V Reference */ + ADC_REFSEL_2048MV_gc = (0x05<<0), /* Internal 2.048V Reference */ + ADC_REFSEL_2500MV_gc = (0x06<<0), /* Internal 2.5V Reference */ + ADC_REFSEL_4096MV_gc = (0x07<<0), /* Internal 4.096V Reference */ +} ADC_REFSEL_t; + +/* Sample numbers select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_NONE_gc = (0x00<<0), /* No accumulation */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* 2 samples accumulation */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* 4 samples accumulation */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* 8 samples accumulation */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* 16 samples accumulation */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* 32 samples accumulation */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* 64 samples accumulation */ + ADC_SAMPNUM_ACC128_gc = (0x07<<0), /* 128 samples accumulation */ + ADC_SAMPNUM_ACC256_gc = (0x08<<0), /* 256 samples accumulation */ + ADC_SAMPNUM_ACC512_gc = (0x09<<0), /* 512 samples accumulation */ + ADC_SAMPNUM_ACC1024_gc = (0x0A<<0), /* 1024 samples accumulation */ +} ADC_SAMPNUM_t; + +/* Start command select */ +typedef enum ADC_START_enum +{ + ADC_START_STOP_gc = (0x00<<0), /* Stop an ongoing conversion */ + ADC_START_IMMEDIATE_gc = (0x01<<0), /* Start immediately */ + ADC_START_MUXPOS_WRITE_gc = (0x02<<0), /* Start on MUXPOS write */ + ADC_START_MUXNEG_WRITE_gc = (0x03<<0), /* Start on MUXNEG write */ + ADC_START_EVENT_TRIGGER_gc = (0x04<<0), /* Start on event */ +} ADC_START_t; + +/* VIA select */ +typedef enum ADC_VIA_enum +{ + ADC_VIA_ADC_gc = (0x00<<6), /* Via ADC */ + ADC_VIA_PGA_gc = (0x01<<6), /* Via PGA */ +} ADC_VIA_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* Window Mode Source select */ +typedef enum ADC_WINSRC_enum +{ + ADC_WINSRC_RESULT_gc = (0x00<<3), /* Result register */ + ADC_WINSRC_SAMPLE_gc = (0x01<<3), /* Sample register */ +} ADC_WINSRC_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t SEQCTRL1; /* Sequential Control 1 */ + register8_t reserved_1[2]; + register8_t INTCTRL0; /* Interrupt Control 0 */ + register8_t reserved_2[1]; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t LUT2CTRLA; /* LUT Control 2 A */ + register8_t LUT2CTRLB; /* LUT Control 2 B */ + register8_t LUT2CTRLC; /* LUT Control 2 C */ + register8_t TRUTH2; /* Truth 2 */ + register8_t LUT3CTRLA; /* LUT Control 3 A */ + register8_t LUT3CTRLB; /* LUT Control 3 B */ + register8_t LUT3CTRLC; /* LUT Control 3 C */ + register8_t TRUTH3; /* Truth 3 */ + register8_t reserved_3[40]; +} CCL_t; + +/* Clock Source Selection select */ +typedef enum CCL_CLKSRC_enum +{ + CCL_CLKSRC_CLKPER_gc = (0x00<<1), /* CLK_PER is clocking the LUT */ + CCL_CLKSRC_IN2_gc = (0x01<<1), /* IN[2] is clocking the LUT */ + CCL_CLKSRC_OSC20M_gc = (0x04<<1), /* 20MHz oscillator before prescaler is clocking the LUT */ + CCL_CLKSRC_OSCULP32K_gc = (0x05<<1), /* 32kHz oscillator is clocking the LUT */ + CCL_CLKSRC_OSCULP1K_gc = (0x06<<1), /* 32kHz oscillator after DIV32 is clocking the LUT */ +} CCL_CLKSRC_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL0_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_USART0_gc = (0x08<<0), /* USART0 TXD input source */ + CCL_INSEL0_SPI0_gc = (0x09<<0), /* SPI0 MOSI input source */ + CCL_INSEL0_TCA0_gc = (0x0A<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCB0_gc = (0x0C<<0), /* TCB0 WO input source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENTA_gc = (0x03<<4), /* Event input source A */ + CCL_INSEL1_EVENTB_gc = (0x04<<4), /* Event input source B */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_USART1_gc = (0x08<<4), /* USART1 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x09<<4), /* SPI0 MOSI input source */ + CCL_INSEL1_TCA0_gc = (0x0A<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCB1_gc = (0x0C<<4), /* TCB1 WO input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL2_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_SPI0_gc = (0x09<<0), /* SPI0 SCK input source */ + CCL_INSEL2_TCA0_gc = (0x0A<<0), /* TCA0 WO2 input source */ +} CCL_INSEL2_t; + +/* Interrupt Mode for LUT0 select */ +typedef enum CCL_INTMODE0_enum +{ + CCL_INTMODE0_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled */ + CCL_INTMODE0_RISING_gc = (0x01<<0), /* Sense rising edge */ + CCL_INTMODE0_FALLING_gc = (0x02<<0), /* Sense falling edge */ + CCL_INTMODE0_BOTH_gc = (0x03<<0), /* Sense both edges */ +} CCL_INTMODE0_t; + +/* Interrupt Mode for LUT1 select */ +typedef enum CCL_INTMODE1_enum +{ + CCL_INTMODE1_INTDISABLE_gc = (0x00<<2), /* Interrupt disabled */ + CCL_INTMODE1_RISING_gc = (0x01<<2), /* Sense rising edge */ + CCL_INTMODE1_FALLING_gc = (0x02<<2), /* Sense falling edge */ + CCL_INTMODE1_BOTH_gc = (0x03<<2), /* Sense both edges */ +} CCL_INTMODE1_t; + +/* Interrupt Mode for LUT2 select */ +typedef enum CCL_INTMODE2_enum +{ + CCL_INTMODE2_INTDISABLE_gc = (0x00<<4), /* Interrupt disabled */ + CCL_INTMODE2_RISING_gc = (0x01<<4), /* Sense rising edge */ + CCL_INTMODE2_FALLING_gc = (0x02<<4), /* Sense falling edge */ + CCL_INTMODE2_BOTH_gc = (0x03<<4), /* Sense both edges */ +} CCL_INTMODE2_t; + +/* Interrupt Mode for LUT3 select */ +typedef enum CCL_INTMODE3_enum +{ + CCL_INTMODE3_INTDISABLE_gc = (0x00<<6), /* Interrupt disabled */ + CCL_INTMODE3_RISING_gc = (0x01<<6), /* Sense rising edge */ + CCL_INTMODE3_FALLING_gc = (0x02<<6), /* Sense falling edge */ + CCL_INTMODE3_BOTH_gc = (0x03<<6), /* Sense both edges */ +} CCL_INTMODE3_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL0_enum +{ + CCL_SEQSEL0_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL0_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL0_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL0_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL0_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL0_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL1_enum +{ + CCL_SEQSEL1_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL1_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL1_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL1_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL1_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL1_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1k cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16k cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32k cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t SWEVENTA; /* Software Event A */ + register8_t reserved_1[15]; + register8_t CHANNEL0; /* Multiplexer Channel 0 */ + register8_t CHANNEL1; /* Multiplexer Channel 1 */ + register8_t CHANNEL2; /* Multiplexer Channel 2 */ + register8_t CHANNEL3; /* Multiplexer Channel 3 */ + register8_t CHANNEL4; /* Multiplexer Channel 4 */ + register8_t CHANNEL5; /* Multiplexer Channel 5 */ + register8_t reserved_2[10]; + register8_t USERCCLLUT0A; /* User CCL LUT0 Event A */ + register8_t USERCCLLUT0B; /* User CCL LUT0 Event B */ + register8_t USERCCLLUT1A; /* User CCL LUT1 Event A */ + register8_t USERCCLLUT1B; /* User CCL LUT1 Event B */ + register8_t USERCCLLUT2A; /* User CCL LUT2 Event A */ + register8_t USERCCLLUT2B; /* User CCL LUT2 Event B */ + register8_t USERCCLLUT3A; /* User CCL LUT3 Event A */ + register8_t USERCCLLUT3B; /* User CCL LUT3 Event B */ + register8_t USERADC0START; /* User ADC0 */ + register8_t USEREVSYSEVOUTA; /* User EVOUT Port A */ + register8_t USEREVSYSEVOUTB; /* User EVOUT Port B */ + register8_t USEREVSYSEVOUTC; /* User EVOUT Port C */ + register8_t USERUSART0IRDA; /* User USART0 */ + register8_t USERUSART1IRDA; /* User USART1 */ + register8_t USERTCA0CNTA; /* User TCA0 count event */ + register8_t USERTCA0CNTB; /* User TCA0 Restart event */ + register8_t USERTCB0CAPT; /* User TCB0 Event in A */ + register8_t USERTCB0COUNT; /* User TCB0 Event in B */ + register8_t USERTCB1CAPT; /* User TCB1 Event in A */ + register8_t USERTCB1COUNT; /* User TCB1 Event in B */ + register8_t reserved_3[12]; +} EVSYS_t; + +/* Channel 0 generator select select */ +typedef enum EVSYS_CHANNEL0_enum +{ + EVSYS_CHANNEL0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL0_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_CHANNEL0_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL0_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL0_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL0_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL0_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL0_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL0_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL0_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL0_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL0_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL0_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL0_ADC0_RES_gc = (0x24<<0), /* ADC 0 Result ready event */ + EVSYS_CHANNEL0_ADC0_SAMP_gc = (0x25<<0), /* ADC 0 Sample ready event */ + EVSYS_CHANNEL0_ADC0_WCMP_gc = (0x26<<0), /* ADC 0 Window compare match event */ + EVSYS_CHANNEL0_PORTA_PIN0_gc = (0x40<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL0_PORTA_PIN1_gc = (0x41<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL0_PORTA_PIN2_gc = (0x42<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL0_PORTA_PIN3_gc = (0x43<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL0_PORTA_PIN4_gc = (0x44<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL0_PORTA_PIN5_gc = (0x45<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL0_PORTA_PIN6_gc = (0x46<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL0_PORTA_PIN7_gc = (0x47<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL0_PORTB_PIN0_gc = (0x48<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL0_PORTB_PIN1_gc = (0x49<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL0_PORTB_PIN2_gc = (0x4A<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL0_PORTB_PIN3_gc = (0x4B<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL0_PORTB_PIN4_gc = (0x4C<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL0_PORTB_PIN5_gc = (0x4D<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL0_PORTB_PIN6_gc = (0x4E<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL0_PORTB_PIN7_gc = (0x4F<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL0_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL0_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL0_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_CHANNEL0_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_CHANNEL0_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow */ + EVSYS_CHANNEL0_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL0_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL0_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL0_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL0_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL0_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL0_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ +} EVSYS_CHANNEL0_t; + +/* Channel 1 generator select select */ +typedef enum EVSYS_CHANNEL1_enum +{ + EVSYS_CHANNEL1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL1_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_CHANNEL1_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL1_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL1_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL1_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL1_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL1_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL1_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL1_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL1_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL1_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL1_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL1_ADC0_RES_gc = (0x24<<0), /* ADC 0 Result ready event */ + EVSYS_CHANNEL1_ADC0_SAMP_gc = (0x25<<0), /* ADC 0 Sample ready event */ + EVSYS_CHANNEL1_ADC0_WCMP_gc = (0x26<<0), /* ADC 0 Window compare match event */ + EVSYS_CHANNEL1_PORTA_PIN0_gc = (0x40<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL1_PORTA_PIN1_gc = (0x41<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL1_PORTA_PIN2_gc = (0x42<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL1_PORTA_PIN3_gc = (0x43<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL1_PORTA_PIN4_gc = (0x44<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL1_PORTA_PIN5_gc = (0x45<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL1_PORTA_PIN6_gc = (0x46<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL1_PORTA_PIN7_gc = (0x47<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL1_PORTB_PIN0_gc = (0x48<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL1_PORTB_PIN1_gc = (0x49<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL1_PORTB_PIN2_gc = (0x4A<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL1_PORTB_PIN3_gc = (0x4B<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL1_PORTB_PIN4_gc = (0x4C<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL1_PORTB_PIN5_gc = (0x4D<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL1_PORTB_PIN6_gc = (0x4E<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL1_PORTB_PIN7_gc = (0x4F<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL1_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL1_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL1_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_CHANNEL1_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_CHANNEL1_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow */ + EVSYS_CHANNEL1_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL1_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL1_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL1_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL1_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL1_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL1_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ +} EVSYS_CHANNEL1_t; + +/* Channel 2 generator select select */ +typedef enum EVSYS_CHANNEL2_enum +{ + EVSYS_CHANNEL2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL2_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_CHANNEL2_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL2_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL2_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL2_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL2_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL2_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL2_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL2_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL2_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL2_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL2_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL2_ADC0_RES_gc = (0x24<<0), /* ADC 0 Result ready event */ + EVSYS_CHANNEL2_ADC0_SAMP_gc = (0x25<<0), /* ADC 0 Sample ready event */ + EVSYS_CHANNEL2_ADC0_WCMP_gc = (0x26<<0), /* ADC 0 Window compare match event */ + EVSYS_CHANNEL2_PORTC_PIN0_gc = (0x40<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL2_PORTC_PIN1_gc = (0x41<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL2_PORTC_PIN2_gc = (0x42<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL2_PORTC_PIN3_gc = (0x43<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL2_PORTC_PIN4_gc = (0x44<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL2_PORTC_PIN5_gc = (0x45<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL2_PORTC_PIN6_gc = (0x46<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL2_PORTC_PIN7_gc = (0x47<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL2_PORTA_PIN0_gc = (0x48<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL2_PORTA_PIN1_gc = (0x49<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL2_PORTA_PIN2_gc = (0x4A<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL2_PORTA_PIN3_gc = (0x4B<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL2_PORTA_PIN4_gc = (0x4C<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL2_PORTA_PIN5_gc = (0x4D<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL2_PORTA_PIN6_gc = (0x4E<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL2_PORTA_PIN7_gc = (0x4F<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL2_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL2_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL2_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_CHANNEL2_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_CHANNEL2_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow */ + EVSYS_CHANNEL2_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL2_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL2_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL2_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL2_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL2_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL2_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ +} EVSYS_CHANNEL2_t; + +/* Channel 3 generator select select */ +typedef enum EVSYS_CHANNEL3_enum +{ + EVSYS_CHANNEL3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL3_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_CHANNEL3_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL3_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL3_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL3_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL3_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL3_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL3_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL3_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL3_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL3_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL3_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL3_ADC0_RES_gc = (0x24<<0), /* ADC 0 Result ready event */ + EVSYS_CHANNEL3_ADC0_SAMP_gc = (0x25<<0), /* ADC 0 Sample ready event */ + EVSYS_CHANNEL3_ADC0_WCMP_gc = (0x26<<0), /* ADC 0 Window compare match event */ + EVSYS_CHANNEL3_PORTC_PIN0_gc = (0x40<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL3_PORTC_PIN1_gc = (0x41<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL3_PORTC_PIN2_gc = (0x42<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL3_PORTC_PIN3_gc = (0x43<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL3_PORTC_PIN4_gc = (0x44<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL3_PORTC_PIN5_gc = (0x45<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL3_PORTC_PIN6_gc = (0x46<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL3_PORTC_PIN7_gc = (0x47<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL3_PORTA_PIN0_gc = (0x48<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL3_PORTA_PIN1_gc = (0x49<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL3_PORTA_PIN2_gc = (0x4A<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL3_PORTA_PIN3_gc = (0x4B<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL3_PORTA_PIN4_gc = (0x4C<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL3_PORTA_PIN5_gc = (0x4D<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL3_PORTA_PIN6_gc = (0x4E<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL3_PORTA_PIN7_gc = (0x4F<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL3_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL3_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL3_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_CHANNEL3_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_CHANNEL3_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow */ + EVSYS_CHANNEL3_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL3_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL3_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL3_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL3_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL3_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL3_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ +} EVSYS_CHANNEL3_t; + +/* Channel 4 generator select select */ +typedef enum EVSYS_CHANNEL4_enum +{ + EVSYS_CHANNEL4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL4_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_CHANNEL4_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL4_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL4_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL4_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL4_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL4_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL4_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL4_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL4_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL4_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL4_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL4_ADC0_RES_gc = (0x24<<0), /* ADC 0 Result ready event */ + EVSYS_CHANNEL4_ADC0_SAMP_gc = (0x25<<0), /* ADC 0 Sample ready event */ + EVSYS_CHANNEL4_ADC0_WCMP_gc = (0x26<<0), /* ADC 0 Window compare match event */ + EVSYS_CHANNEL4_PORTB_PIN0_gc = (0x40<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL4_PORTB_PIN1_gc = (0x41<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL4_PORTB_PIN2_gc = (0x42<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL4_PORTB_PIN3_gc = (0x43<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL4_PORTB_PIN4_gc = (0x44<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL4_PORTB_PIN5_gc = (0x45<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL4_PORTB_PIN6_gc = (0x46<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL4_PORTB_PIN7_gc = (0x47<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL4_PORTC_PIN0_gc = (0x48<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL4_PORTC_PIN1_gc = (0x49<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL4_PORTC_PIN2_gc = (0x4A<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL4_PORTC_PIN3_gc = (0x4B<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL4_PORTC_PIN4_gc = (0x4C<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL4_PORTC_PIN5_gc = (0x4D<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL4_PORTC_PIN6_gc = (0x4E<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL4_PORTC_PIN7_gc = (0x4F<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL4_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL4_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL4_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_CHANNEL4_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_CHANNEL4_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow */ + EVSYS_CHANNEL4_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL4_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL4_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL4_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL4_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL4_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL4_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ +} EVSYS_CHANNEL4_t; + +/* Channel 5 generator select select */ +typedef enum EVSYS_CHANNEL5_enum +{ + EVSYS_CHANNEL5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL5_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_CHANNEL5_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL5_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL5_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL5_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL5_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL5_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL5_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL5_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL5_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL5_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL5_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL5_ADC0_RES_gc = (0x24<<0), /* ADC 0 Result ready event */ + EVSYS_CHANNEL5_ADC0_SAMP_gc = (0x25<<0), /* ADC 0 Sample ready event */ + EVSYS_CHANNEL5_ADC0_WCMP_gc = (0x26<<0), /* ADC 0 Window compare match event */ + EVSYS_CHANNEL5_PORTB_PIN0_gc = (0x40<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL5_PORTB_PIN1_gc = (0x41<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL5_PORTB_PIN2_gc = (0x42<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL5_PORTB_PIN3_gc = (0x43<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL5_PORTB_PIN4_gc = (0x44<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL5_PORTB_PIN5_gc = (0x45<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL5_PORTB_PIN6_gc = (0x46<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL5_PORTB_PIN7_gc = (0x47<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL5_PORTC_PIN0_gc = (0x48<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL5_PORTC_PIN1_gc = (0x49<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL5_PORTC_PIN2_gc = (0x4A<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL5_PORTC_PIN3_gc = (0x4B<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL5_PORTC_PIN4_gc = (0x4C<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL5_PORTC_PIN5_gc = (0x4D<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL5_PORTC_PIN6_gc = (0x4E<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL5_PORTC_PIN7_gc = (0x4F<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL5_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL5_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL5_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_CHANNEL5_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_CHANNEL5_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow */ + EVSYS_CHANNEL5_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL5_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL5_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL5_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL5_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL5_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL5_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ +} EVSYS_CHANNEL5_t; + +/* Software event on channel select */ +typedef enum EVSYS_SWEVENTA_enum +{ + EVSYS_SWEVENTA_CH0_gc = (0x01<<0), /* Software event on channel 0 */ + EVSYS_SWEVENTA_CH1_gc = (0x02<<0), /* Software event on channel 1 */ + EVSYS_SWEVENTA_CH2_gc = (0x04<<0), /* Software event on channel 2 */ + EVSYS_SWEVENTA_CH3_gc = (0x08<<0), /* Software event on channel 3 */ + EVSYS_SWEVENTA_CH4_gc = (0x10<<0), /* Software event on channel 4 */ + EVSYS_SWEVENTA_CH5_gc = (0x20<<0), /* Software event on channel 5 */ +} EVSYS_SWEVENTA_t; + +/* Channel selector select */ +typedef enum EVSYS_USER_enum +{ + EVSYS_USER_OFF_gc = (0x00<<0), /* Off */ + EVSYS_USER_CHANNEL0_gc = (0x01<<0), /* Connect user to event channel 0 */ + EVSYS_USER_CHANNEL1_gc = (0x02<<0), /* Connect user to event channel 1 */ + EVSYS_USER_CHANNEL2_gc = (0x03<<0), /* Connect user to event channel 2 */ + EVSYS_USER_CHANNEL3_gc = (0x04<<0), /* Connect user to event channel 3 */ + EVSYS_USER_CHANNEL4_gc = (0x05<<0), /* Connect user to event channel 4 */ + EVSYS_USER_CHANNEL5_gc = (0x06<<0), /* Connect user to event channel 5 */ +} EVSYS_USER_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ + RSTPINCFG_PDIRST_gc = (0x03<<2), /* PDI on PDI pad, reset on alternative reset pad */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock Bits */ + register8_t reserved_1[1]; +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMBIST - BIST in the NVMCTRL module +-------------------------------------------------------------------------- +*/ + +/* BIST in the NVMCTRL module */ +typedef struct NVMBIST_struct +{ + register8_t CTRLA; /* Control A */ + register8_t ADDRPAT; /* Address pattern */ + register8_t DATAPAT; /* Data pattern */ + register8_t STATUS; /* Status */ + _WORDREGISTER(CNT); /* */ + _DWORDREGISTER(END); /* */ + register8_t reserved_1[6]; +} NVMBIST_t; + +/* Address mode select */ +typedef enum NVMBIST_AMODE_enum +{ + NVMBIST_AMODE_NORMAL_gc = (0x00<<4), /* No special address pattern */ + NVMBIST_AMODE_COMPLEMENT_gc = (0x04<<4), /* Post complement address */ +} NVMBIST_AMODE_t; + +/* Command select */ +typedef enum NVMBIST_CMD_enum +{ + NVMBIST_CMD_NOCMD_gc = (0x00<<0), /* No effect */ + NVMBIST_CMD_START_gc = (0x01<<0), /* Start BIST testing */ + NVMBIST_CMD_RESTART_gc = (0x02<<0), /* Re-start BIST testing */ + NVMBIST_CMD_BREAK_gc = (0x03<<0), /* Stop BIST and go to BREAK state */ +} NVMBIST_CMD_t; + +/* Data check pattern select */ +typedef enum NVMBIST_PATTERN_enum +{ + NVMBIST_PATTERN_ZEROES_gc = (0x00<<0), /* All flash programmed */ + NVMBIST_PATTERN_CHECK_gc = (0x01<<0), /* Physical checkerboard in flash */ + NVMBIST_PATTERN_INVCHECK_gc = (0x02<<0), /* Inverse physical checkerboard in flash */ + NVMBIST_PATTERN_ONES_gc = (0x03<<0), /* All flash unprogrammed */ +} NVMBIST_PATTERN_t; + +/* FSM State select */ +typedef enum NVMBIST_STATE_enum +{ + NVMBIST_STATE_IDLE_gc = (0x00<<0), /* Reset state */ + NVMBIST_STATE_BREAK_gc = (0x01<<0), /* Break command used */ + NVMBIST_STATE_FAILED0_gc = (0x04<<0), /* Test failed, data from last address */ + NVMBIST_STATE_FAILED1_gc = (0x05<<0), /* Test failed, data from address-1 */ + NVMBIST_STATE_FAILED2_gc = (0x06<<0), /* Test failed, data from address-2 */ + NVMBIST_STATE_SUCCESS_gc = (0x07<<0), /* Test success */ + NVMBIST_STATE_START0_gc = (0x08<<0), /* Startup, fetching first data */ + NVMBIST_STATE_START1_gc = (0x09<<0), /* Startup, fetching second data */ + NVMBIST_STATE_RESTART0_gc = (0x0A<<0), /* Re-start from BREAK or FAILED2 */ + NVMBIST_STATE_RESTART1_gc = (0x0B<<0), /* Re-start from FAILED1 */ + NVMBIST_STATE_RUNNING_gc = (0x0C<<0), /* Test running */ + NVMBIST_STATE_FINISH0_gc = (0x0E<<0), /* Check last word */ + NVMBIST_STATE_FINISH1_gc = (0x0F<<0), /* Count faults in last word */ +} NVMBIST_STATE_t; + +/* X address mode select */ +typedef enum NVMBIST_XMODE_enum +{ + NVMBIST_XMODE_STATIC_gc = (0x00<<0), /* X static */ + NVMBIST_XMODE_CARRY_gc = (0x01<<0), /* Carry/borrow from Y */ + NVMBIST_XMODE_INC_gc = (0x02<<0), /* X increment each cycle */ + NVMBIST_XMODE_DEC_gc = (0x03<<0), /* X decrement each cycle */ +} NVMBIST_XMODE_t; + +/* Y address mode select */ +typedef enum NVMBIST_YMODE_enum +{ + NVMBIST_YMODE_STATIC_gc = (0x00<<2), /* Y static */ + NVMBIST_YMODE_CARRY_gc = (0x01<<2), /* Carry/borrow from X */ + NVMBIST_YMODE_INC_gc = (0x02<<2), /* Y increment each cycle */ + NVMBIST_YMODE_DEC_gc = (0x03<<2), /* Y decrement each cycle */ +} NVMBIST_YMODE_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t PORTCTRL; /* Port Control */ + register8_t reserved_1[5]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t EVSYSROUTEA; /* Port Multiplexer EVSYS */ + register8_t CCLROUTEA; /* Port Multiplexer CCL */ + register8_t USARTROUTEA; /* Port Multiplexer USART register A */ + register8_t SPIROUTEA; /* Port Multiplexer TWI and SPI */ + register8_t TCAROUTEA; /* Port Multiplexer TCA */ + register8_t TCBROUTEA; /* Port Multiplexer TCB */ + register8_t reserved_1[10]; +} PORTMUX_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<0), /* SPI0 on PA[7:4] */ + PORTMUX_SPI0_ALT1_gc = (0x01<<0), /* SPI0 on PC[3:0] */ + PORTMUX_SPI0_ALT2_gc = (0x02<<0), /* SPI0 on PE[3:0] */ + PORTMUX_SPI0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 select */ +typedef enum PORTMUX_TCA0_enum +{ + PORTMUX_TCA0_PORTA_gc = (0x00<<0), /* TCA0 pins on PA[5:0] */ + PORTMUX_TCA0_PORTB_gc = (0x01<<0), /* TCA0 pins on PB[5:0] */ + PORTMUX_TCA0_PORTC_gc = (0x02<<0), /* TCA0 pins on PC[5:0] */ + PORTMUX_TCA0_PORTD_gc = (0x03<<0), /* TCA0 pins on PD[5:0] */ + PORTMUX_TCA0_PORTE_gc = (0x04<<0), /* TCA0 pins on PE[5:0] */ + PORTMUX_TCA0_PORTF_gc = (0x05<<0), /* TCA0 pins on PF[5:0] */ +} PORTMUX_TCA0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* SCL/SDA on PA[3:2], Slave mode on PC[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT1_gc = (0x01<<4), /* SCL/SDA on PA[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT2_gc = (0x02<<4), /* SCL/SDA on PC[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* USART0 on PA[3:0] */ + PORTMUX_USART0_ALT1_gc = (0x01<<0), /* USART0 on PA[7:4] */ + PORTMUX_USART0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_USART0_t; + +/* Port Multiplexer USART1 select */ +typedef enum PORTMUX_USART1_enum +{ + PORTMUX_USART1_DEFAULT_gc = (0x00<<2), /* USART1 on PC[3:0] */ + PORTMUX_USART1_ALT1_gc = (0x01<<2), /* USART1 on PC[7:4] */ + PORTMUX_USART1_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_USART1_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t CALIB; /* Calibration */ + register8_t CLKSEL; /* RTC Clock */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_1[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_2[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_3[10]; +} RTC_t; + +/* Clock select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[7]; + register8_t OSCCAL32K; /* Oscillator Calibration for 32kHz ULP */ + register8_t reserved_2[3]; + register8_t OSCCAL16M0; /* Oscillator Calibration 16 MHz Byte 0 */ + register8_t OSCCAL16M1; /* Oscillator Calibration 16 MHz Byte 1 */ + register8_t OSCCAL20M0; /* Oscillator Calibration 20 MHz Byte 0 */ + register8_t OSCCAL20M1; /* Oscillator Calibration 20 MHz Byte 1 */ + register8_t reserved_3[4]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_4[9]; + register8_t CHECKSUM1; /* CRC Checksum Byte 1 */ + register8_t reserved_5[16]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[21]; + register8_t OCDM; /* OCD Message Register */ + register8_t OCDMS; /* OCD Message Status */ + register8_t reserved_3[6]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action A select */ +typedef enum TCA_SINGLE_EVACTA_enum +{ + TCA_SINGLE_EVACTA_CNT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACTA_CNT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACTA_CNT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACTA_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACTA_t; + +/* Event Action B select */ +typedef enum TCA_SINGLE_EVACTB_enum +{ + TCA_SINGLE_EVACTB_UPDOWN_gc = (0x03<<5), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ + TCA_SINGLE_EVACTB_RESTART_POSEDGE_gc = (0x04<<5), /* Restart counter at positive edge event */ + TCA_SINGLE_EVACTB_RESTART_ANYEDGE_gc = (0x05<<5), /* Restart counter on any edge event */ + TCA_SINGLE_EVACTB_RESTART_HIGHLVL_gc = (0x06<<5), /* Restart counter while event line is 1. */ +} TCA_SINGLE_EVACTB_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* Command Enable select */ +typedef enum TCA_SPLIT_CMDEN_enum +{ + TCA_SPLIT_CMDEN_NONE_gc = (0x00<<0), /* None */ + TCA_SPLIT_CMDEN_BOTH_gc = (0x03<<0), /* Both low byte and high byte */ +} TCA_SPLIT_CMDEN_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* TCB Clock select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_DIV1_gc = (0x00<<1), /* CLK_PEP */ + TCB_CLKSEL_DIV2_gc = (0x01<<1), /* CLK_PER/2 */ + TCB_CLKSEL_TCA0_gc = (0x02<<1), /* Use CLK_TCA from TCA0 */ + TCB_CLKSEL_EVENT_gc = (0x07<<1), /* Count on event edge */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baud Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t CTRLD; /* Control D */ + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_1[1]; +} USART_t; + +/* Auto Baud Window select */ +typedef enum USART_ABW_enum +{ + USART_ABW_WDW0_gc = (0x00<<6), /* 18% tolerance */ + USART_ABW_WDW1_gc = (0x01<<6), /* 15% tolerance */ + USART_ABW_WDW2_gc = (0x02<<6), /* 21% tolerance */ + USART_ABW_WDW3_gc = (0x03<<6), /* 25% tolerance */ +} USART_ABW_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_DISABLE_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_ENABLE_gc = (0x01<<0), /* RS485 Mode enabled */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ + register8_t USERROW32; /* User Row Byte 32 */ + register8_t USERROW33; /* User Row Byte 33 */ + register8_t USERROW34; /* User Row Byte 34 */ + register8_t USERROW35; /* User Row Byte 35 */ + register8_t USERROW36; /* User Row Byte 36 */ + register8_t USERROW37; /* User Row Byte 37 */ + register8_t USERROW38; /* User Row Byte 38 */ + register8_t USERROW39; /* User Row Byte 39 */ + register8_t USERROW40; /* User Row Byte 40 */ + register8_t USERROW41; /* User Row Byte 41 */ + register8_t USERROW42; /* User Row Byte 42 */ + register8_t USERROW43; /* User Row Byte 43 */ + register8_t USERROW44; /* User Row Byte 44 */ + register8_t USERROW45; /* User Row Byte 45 */ + register8_t USERROW46; /* User Row Byte 46 */ + register8_t USERROW47; /* User Row Byte 47 */ + register8_t USERROW48; /* User Row Byte 48 */ + register8_t USERROW49; /* User Row Byte 49 */ + register8_t USERROW50; /* User Row Byte 50 */ + register8_t USERROW51; /* User Row Byte 51 */ + register8_t USERROW52; /* User Row Byte 52 */ + register8_t USERROW53; /* User Row Byte 53 */ + register8_t USERROW54; /* User Row Byte 54 */ + register8_t USERROW55; /* User Row Byte 55 */ + register8_t USERROW56; /* User Row Byte 56 */ + register8_t USERROW57; /* User Row Byte 57 */ + register8_t USERROW58; /* User Row Byte 58 */ + register8_t USERROW59; /* User Row Byte 59 */ + register8_t USERROW60; /* User Row Byte 60 */ + register8_t USERROW61; /* User Row Byte 61 */ + register8_t USERROW62; /* User Row Byte 62 */ + register8_t USERROW63; /* User Row Byte 63 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* AC0 reference select select */ +typedef enum VREF_AC0REFSEL_enum +{ + VREF_AC0REFSEL_1V024_gc = (0x00<<0), /* Voltage reference at 1.024V */ + VREF_AC0REFSEL_2V048_gc = (0x01<<0), /* Voltage reference at 2.048V */ + VREF_AC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_AC0REFSEL_4V096_gc = (0x03<<0), /* Voltage reference at 4.096V */ + VREF_AC0REFSEL_AVDD_gc = (0x07<<0), /* voltage reference at supply */ +} VREF_AC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define NVMBIST (*(NVMBIST_t *) 0x00C0) /* BIST in the NVMCTRL module */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define PORTMUX (*(PORTMUX_t *) 0x05E0) /* Port Multiplexer */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1 (*(USART_t *) 0x0820) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x08A0) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A80) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0A90) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* NVMBIST - BIST in the NVMCTRL module */ +#define NVMBIST_CTRLA _SFR_MEM8(0x00C0) +#define NVMBIST_ADDRPAT _SFR_MEM8(0x00C1) +#define NVMBIST_DATAPAT _SFR_MEM8(0x00C2) +#define NVMBIST_STATUS _SFR_MEM8(0x00C3) +#define NVMBIST_CNT _SFR_MEM16(0x00C4) +#define NVMBIST_CNTL _SFR_MEM8(0x00C4) +#define NVMBIST_CNTH _SFR_MEM8(0x00C5) +#define NVMBIST_END _SFR_MEM32(0x00C6) +#define NVMBIST_END0 _SFR_MEM8(0x00C6) +#define NVMBIST_END1 _SFR_MEM8(0x00C7) +#define NVMBIST_END2 _SFR_MEM8(0x00C8) +#define NVMBIST_END3 _SFR_MEM8(0x00C9) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CALIB _SFR_MEM8(0x0146) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_SWEVENTA _SFR_MEM8(0x0180) +#define EVSYS_CHANNEL0 _SFR_MEM8(0x0190) +#define EVSYS_CHANNEL1 _SFR_MEM8(0x0191) +#define EVSYS_CHANNEL2 _SFR_MEM8(0x0192) +#define EVSYS_CHANNEL3 _SFR_MEM8(0x0193) +#define EVSYS_CHANNEL4 _SFR_MEM8(0x0194) +#define EVSYS_CHANNEL5 _SFR_MEM8(0x0195) +#define EVSYS_USERCCLLUT0A _SFR_MEM8(0x01A0) +#define EVSYS_USERCCLLUT0B _SFR_MEM8(0x01A1) +#define EVSYS_USERCCLLUT1A _SFR_MEM8(0x01A2) +#define EVSYS_USERCCLLUT1B _SFR_MEM8(0x01A3) +#define EVSYS_USERCCLLUT2A _SFR_MEM8(0x01A4) +#define EVSYS_USERCCLLUT2B _SFR_MEM8(0x01A5) +#define EVSYS_USERCCLLUT3A _SFR_MEM8(0x01A6) +#define EVSYS_USERCCLLUT3B _SFR_MEM8(0x01A7) +#define EVSYS_USERADC0START _SFR_MEM8(0x01A8) +#define EVSYS_USEREVSYSEVOUTA _SFR_MEM8(0x01A9) +#define EVSYS_USEREVSYSEVOUTB _SFR_MEM8(0x01AA) +#define EVSYS_USEREVSYSEVOUTC _SFR_MEM8(0x01AB) +#define EVSYS_USERUSART0IRDA _SFR_MEM8(0x01AC) +#define EVSYS_USERUSART1IRDA _SFR_MEM8(0x01AD) +#define EVSYS_USERTCA0CNTA _SFR_MEM8(0x01AE) +#define EVSYS_USERTCA0CNTB _SFR_MEM8(0x01AF) +#define EVSYS_USERTCB0CAPT _SFR_MEM8(0x01B0) +#define EVSYS_USERTCB0COUNT _SFR_MEM8(0x01B1) +#define EVSYS_USERTCB1CAPT _SFR_MEM8(0x01B2) +#define EVSYS_USERTCB1COUNT _SFR_MEM8(0x01B3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_SEQCTRL1 _SFR_MEM8(0x01C2) +#define CCL_INTCTRL0 _SFR_MEM8(0x01C5) +#define CCL_INTFLAGS _SFR_MEM8(0x01C7) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C8) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C9) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01CA) +#define CCL_TRUTH0 _SFR_MEM8(0x01CB) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01CC) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CD) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CE) +#define CCL_TRUTH1 _SFR_MEM8(0x01CF) +#define CCL_LUT2CTRLA _SFR_MEM8(0x01D0) +#define CCL_LUT2CTRLB _SFR_MEM8(0x01D1) +#define CCL_LUT2CTRLC _SFR_MEM8(0x01D2) +#define CCL_TRUTH2 _SFR_MEM8(0x01D3) +#define CCL_LUT3CTRLA _SFR_MEM8(0x01D4) +#define CCL_LUT3CTRLB _SFR_MEM8(0x01D5) +#define CCL_LUT3CTRLC _SFR_MEM8(0x01D6) +#define CCL_TRUTH3 _SFR_MEM8(0x01D7) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PORTCTRL _SFR_MEM8(0x040A) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PORTCTRL _SFR_MEM8(0x042A) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PORTCTRL _SFR_MEM8(0x044A) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_EVSYSROUTEA _SFR_MEM8(0x05E0) +#define PORTMUX_CCLROUTEA _SFR_MEM8(0x05E1) +#define PORTMUX_USARTROUTEA _SFR_MEM8(0x05E2) +#define PORTMUX_SPIROUTEA _SFR_MEM8(0x05E3) +#define PORTMUX_TCAROUTEA _SFR_MEM8(0x05E4) +#define PORTMUX_TCBROUTEA _SFR_MEM8(0x05E5) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_INTCTRL _SFR_MEM8(0x0604) +#define ADC0_INTFLAGS _SFR_MEM8(0x0605) +#define ADC0_STATUS _SFR_MEM8(0x0606) +#define ADC0_DBGCTRL _SFR_MEM8(0x0607) +#define ADC0_CTRLE _SFR_MEM8(0x0608) +#define ADC0_CTRLF _SFR_MEM8(0x0609) +#define ADC0_COMMAND _SFR_MEM8(0x060A) +#define ADC0_PGACTRL _SFR_MEM8(0x060B) +#define ADC0_MUXPOS _SFR_MEM8(0x060C) +#define ADC0_MUXNEG _SFR_MEM8(0x060D) +#define ADC0_RESULT _SFR_MEM32(0x0610) +#define ADC0_RESULT0 _SFR_MEM8(0x0610) +#define ADC0_RESULT1 _SFR_MEM8(0x0611) +#define ADC0_RESULT2 _SFR_MEM8(0x0612) +#define ADC0_RESULT3 _SFR_MEM8(0x0613) +#define ADC0_SAMPLE _SFR_MEM16(0x0614) +#define ADC0_SAMPLEL _SFR_MEM8(0x0614) +#define ADC0_SAMPLEH _SFR_MEM8(0x0615) +#define ADC0_TEMP0 _SFR_MEM8(0x0618) +#define ADC0_TEMP1 _SFR_MEM8(0x0619) +#define ADC0_TEMP2 _SFR_MEM8(0x061A) +#define ADC0_WINLT _SFR_MEM16(0x061C) +#define ADC0_WINLTL _SFR_MEM8(0x061C) +#define ADC0_WINLTH _SFR_MEM8(0x061D) +#define ADC0_WINHT _SFR_MEM16(0x061E) +#define ADC0_WINHTL _SFR_MEM8(0x061E) +#define ADC0_WINHTH _SFR_MEM8(0x061F) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_DACREF _SFR_MEM8(0x0684) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_CTRLD _SFR_MEM8(0x080A) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* USART (USART1) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1_RXDATAL _SFR_MEM8(0x0820) +#define USART1_RXDATAH _SFR_MEM8(0x0821) +#define USART1_TXDATAL _SFR_MEM8(0x0822) +#define USART1_TXDATAH _SFR_MEM8(0x0823) +#define USART1_STATUS _SFR_MEM8(0x0824) +#define USART1_CTRLA _SFR_MEM8(0x0825) +#define USART1_CTRLB _SFR_MEM8(0x0826) +#define USART1_CTRLC _SFR_MEM8(0x0827) +#define USART1_BAUD _SFR_MEM16(0x0828) +#define USART1_BAUDL _SFR_MEM8(0x0828) +#define USART1_BAUDH _SFR_MEM8(0x0829) +#define USART1_CTRLD _SFR_MEM8(0x082A) +#define USART1_DBGCTRL _SFR_MEM8(0x082B) +#define USART1_EVCTRL _SFR_MEM8(0x082C) +#define USART1_TXPLCTRL _SFR_MEM8(0x082D) +#define USART1_RXPLCTRL _SFR_MEM8(0x082E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x08A0) +#define TWI0_DBGCTRL _SFR_MEM8(0x08A2) +#define TWI0_MCTRLA _SFR_MEM8(0x08A3) +#define TWI0_MCTRLB _SFR_MEM8(0x08A4) +#define TWI0_MSTATUS _SFR_MEM8(0x08A5) +#define TWI0_MBAUD _SFR_MEM8(0x08A6) +#define TWI0_MADDR _SFR_MEM8(0x08A7) +#define TWI0_MDATA _SFR_MEM8(0x08A8) +#define TWI0_SCTRLA _SFR_MEM8(0x08A9) +#define TWI0_SCTRLB _SFR_MEM8(0x08AA) +#define TWI0_SSTATUS _SFR_MEM8(0x08AB) +#define TWI0_SADDR _SFR_MEM8(0x08AC) +#define TWI0_SDATA _SFR_MEM8(0x08AD) +#define TWI0_SADDRMASK _SFR_MEM8(0x08AE) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x08C0) +#define SPI0_CTRLB _SFR_MEM8(0x08C1) +#define SPI0_INTCTRL _SFR_MEM8(0x08C2) +#define SPI0_INTFLAGS _SFR_MEM8(0x08C3) +#define SPI0_DATA _SFR_MEM8(0x08C4) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A80) +#define TCB0_CTRLB _SFR_MEM8(0x0A81) +#define TCB0_EVCTRL _SFR_MEM8(0x0A84) +#define TCB0_INTCTRL _SFR_MEM8(0x0A85) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A86) +#define TCB0_STATUS _SFR_MEM8(0x0A87) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A88) +#define TCB0_TEMP _SFR_MEM8(0x0A89) +#define TCB0_CNT _SFR_MEM16(0x0A8A) +#define TCB0_CNTL _SFR_MEM8(0x0A8A) +#define TCB0_CNTH _SFR_MEM8(0x0A8B) +#define TCB0_CCMP _SFR_MEM16(0x0A8C) +#define TCB0_CCMPL _SFR_MEM8(0x0A8C) +#define TCB0_CCMPH _SFR_MEM8(0x0A8D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0A90) +#define TCB1_CTRLB _SFR_MEM8(0x0A91) +#define TCB1_EVCTRL _SFR_MEM8(0x0A94) +#define TCB1_INTCTRL _SFR_MEM8(0x0A95) +#define TCB1_INTFLAGS _SFR_MEM8(0x0A96) +#define TCB1_STATUS _SFR_MEM8(0x0A97) +#define TCB1_DBGCTRL _SFR_MEM8(0x0A98) +#define TCB1_TEMP _SFR_MEM8(0x0A99) +#define TCB1_CNT _SFR_MEM16(0x0A9A) +#define TCB1_CNTL _SFR_MEM8(0x0A9A) +#define TCB1_CNTH _SFR_MEM8(0x0A9B) +#define TCB1_CCMP _SFR_MEM16(0x0A9C) +#define TCB1_CCMPL _SFR_MEM8(0x0A9C) +#define TCB1_CCMPH _SFR_MEM8(0x0A9D) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) +#define SYSCFG_OCDM _SFR_MEM8(0x0F18) +#define SYSCFG_OCDMS _SFR_MEM8(0x0F19) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_OSCCAL32K _SFR_MEM8(0x1114) +#define SIGROW_OSCCAL16M0 _SFR_MEM8(0x1118) +#define SIGROW_OSCCAL16M1 _SFR_MEM8(0x1119) +#define SIGROW_OSCCAL20M0 _SFR_MEM8(0x111A) +#define SIGROW_OSCCAL20M1 _SFR_MEM8(0x111B) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) +#define SIGROW_CHECKSUM1 _SFR_MEM8(0x112F) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) +#define USERROW_USERROW32 _SFR_MEM8(0x1320) +#define USERROW_USERROW33 _SFR_MEM8(0x1321) +#define USERROW_USERROW34 _SFR_MEM8(0x1322) +#define USERROW_USERROW35 _SFR_MEM8(0x1323) +#define USERROW_USERROW36 _SFR_MEM8(0x1324) +#define USERROW_USERROW37 _SFR_MEM8(0x1325) +#define USERROW_USERROW38 _SFR_MEM8(0x1326) +#define USERROW_USERROW39 _SFR_MEM8(0x1327) +#define USERROW_USERROW40 _SFR_MEM8(0x1328) +#define USERROW_USERROW41 _SFR_MEM8(0x1329) +#define USERROW_USERROW42 _SFR_MEM8(0x132A) +#define USERROW_USERROW43 _SFR_MEM8(0x132B) +#define USERROW_USERROW44 _SFR_MEM8(0x132C) +#define USERROW_USERROW45 _SFR_MEM8(0x132D) +#define USERROW_USERROW46 _SFR_MEM8(0x132E) +#define USERROW_USERROW47 _SFR_MEM8(0x132F) +#define USERROW_USERROW48 _SFR_MEM8(0x1330) +#define USERROW_USERROW49 _SFR_MEM8(0x1331) +#define USERROW_USERROW50 _SFR_MEM8(0x1332) +#define USERROW_USERROW51 _SFR_MEM8(0x1333) +#define USERROW_USERROW52 _SFR_MEM8(0x1334) +#define USERROW_USERROW53 _SFR_MEM8(0x1335) +#define USERROW_USERROW54 _SFR_MEM8(0x1336) +#define USERROW_USERROW55 _SFR_MEM8(0x1337) +#define USERROW_USERROW56 _SFR_MEM8(0x1338) +#define USERROW_USERROW57 _SFR_MEM8(0x1339) +#define USERROW_USERROW58 _SFR_MEM8(0x133A) +#define USERROW_USERROW59 _SFR_MEM8(0x133B) +#define USERROW_USERROW60 _SFR_MEM8(0x133C) +#define USERROW_USERROW61 _SFR_MEM8(0x133D) +#define USERROW_USERROW62 _SFR_MEM8(0x133E) +#define USERROW_USERROW63 _SFR_MEM8(0x133F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.DACREF bit masks and bit positions */ +#define AC_DATA_gm 0xFF /* DAC voltage reference group mask. */ +#define AC_DATA_gp 0 /* DAC voltage reference group position. */ +#define AC_DATA0_bm (1<<0) /* DAC voltage reference bit 0 mask. */ +#define AC_DATA0_bp 0 /* DAC voltage reference bit 0 position. */ +#define AC_DATA1_bm (1<<1) /* DAC voltage reference bit 1 mask. */ +#define AC_DATA1_bp 1 /* DAC voltage reference bit 1 position. */ +#define AC_DATA2_bm (1<<2) /* DAC voltage reference bit 2 mask. */ +#define AC_DATA2_bp 2 /* DAC voltage reference bit 2 position. */ +#define AC_DATA3_bm (1<<3) /* DAC voltage reference bit 3 mask. */ +#define AC_DATA3_bp 3 /* DAC voltage reference bit 3 position. */ +#define AC_DATA4_bm (1<<4) /* DAC voltage reference bit 4 mask. */ +#define AC_DATA4_bp 4 /* DAC voltage reference bit 4 position. */ +#define AC_DATA5_bm (1<<5) /* DAC voltage reference bit 5 mask. */ +#define AC_DATA5_bp 5 /* DAC voltage reference bit 5 position. */ +#define AC_DATA6_bm (1<<6) /* DAC voltage reference bit 6 mask. */ +#define AC_DATA6_bp 6 /* DAC voltage reference bit 6 position. */ +#define AC_DATA7_bm (1<<7) /* DAC voltage reference bit 7 mask. */ +#define AC_DATA7_bp 7 /* DAC voltage reference bit 7 position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_LOWLAT_bm 0x20 /* ADC Low latency mode bit mask. */ +#define ADC_LOWLAT_bp 5 /* ADC Low latency mode bit position. */ +#define ADC_RUNSTDBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTDBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_PRESC_gm 0x0F /* Prescaler Value group mask. */ +#define ADC_PRESC_gp 0 /* Prescaler Value group position. */ +#define ADC_PRESC0_bm (1<<0) /* Prescaler Value bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Prescaler Value bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Prescaler Value bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Prescaler Value bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Prescaler Value bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Prescaler Value bit 2 position. */ +#define ADC_PRESC3_bm (1<<3) /* Prescaler Value bit 3 mask. */ +#define ADC_PRESC3_bp 3 /* Prescaler Value bit 3 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_REFSEL_gm 0x07 /* Reference select group mask. */ +#define ADC_REFSEL_gp 0 /* Reference select group position. */ +#define ADC_REFSEL0_bm (1<<0) /* Reference select bit 0 mask. */ +#define ADC_REFSEL0_bp 0 /* Reference select bit 0 position. */ +#define ADC_REFSEL1_bm (1<<1) /* Reference select bit 1 mask. */ +#define ADC_REFSEL1_bp 1 /* Reference select bit 1 position. */ +#define ADC_REFSEL2_bm (1<<2) /* Reference select bit 2 mask. */ +#define ADC_REFSEL2_bp 2 /* Reference select bit 2 position. */ +#define ADC_TIMEBASE_gm 0xF8 /* Reference Selection group mask. */ +#define ADC_TIMEBASE_gp 3 /* Reference Selection group position. */ +#define ADC_TIMEBASE0_bm (1<<3) /* Reference Selection bit 0 mask. */ +#define ADC_TIMEBASE0_bp 3 /* Reference Selection bit 0 position. */ +#define ADC_TIMEBASE1_bm (1<<4) /* Reference Selection bit 1 mask. */ +#define ADC_TIMEBASE1_bp 4 /* Reference Selection bit 1 position. */ +#define ADC_TIMEBASE2_bm (1<<5) /* Reference Selection bit 2 mask. */ +#define ADC_TIMEBASE2_bp 5 /* Reference Selection bit 2 position. */ +#define ADC_TIMEBASE3_bm (1<<6) /* Reference Selection bit 3 mask. */ +#define ADC_TIMEBASE3_bp 6 /* Reference Selection bit 3 position. */ +#define ADC_TIMEBASE4_bm (1<<7) /* Reference Selection bit 4 mask. */ +#define ADC_TIMEBASE4_bp 7 /* Reference Selection bit 4 position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ +#define ADC_WINSRC_bm 0x08 /* Window Mode Source bit mask. */ +#define ADC_WINSRC_bp 3 /* Window Mode Source bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_SAMPRDY_bm 0x02 /* Sample Ready Interrupt Enable bit mask. */ +#define ADC_SAMPRDY_bp 1 /* Sample Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x04 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 2 /* Window Comparator Interrupt Enable bit position. */ +#define ADC_RESOVR_bm 0x08 /* Result Overwritten Interrupt Enable bit mask. */ +#define ADC_RESOVR_bp 3 /* Result Overwritten Interrupt Enable bit position. */ +#define ADC_SAMPOVR_bm 0x10 /* Sample Overwritten Interrupt Enable bit mask. */ +#define ADC_SAMPOVR_bp 4 /* Sample Overwritten Interrupt Enable bit position. */ +#define ADC_TRIGOVR_bm 0x20 /* Trigger Overrun Interrupt Enable bit mask. */ +#define ADC_TRIGOVR_bp 5 /* Trigger Overrun Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_SAMPRDY is already defined. */ +/* ADC_WCMP is already defined. */ +/* ADC_RESOVR is already defined. */ +/* ADC_SAMPOVR is already defined. */ +/* ADC_TRIGOVR is already defined. */ + +/* ADC.STATUS bit masks and bit positions */ +#define ADC_ADCBUSY_bm 0x01 /* ADC Busy bit mask. */ +#define ADC_ADCBUSY_bp 0 /* ADC Busy bit position. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_SAMPDUR_gm 0xFF /* Sampling time group mask. */ +#define ADC_SAMPDUR_gp 0 /* Sampling time group position. */ +#define ADC_SAMPDUR0_bm (1<<0) /* Sampling time bit 0 mask. */ +#define ADC_SAMPDUR0_bp 0 /* Sampling time bit 0 position. */ +#define ADC_SAMPDUR1_bm (1<<1) /* Sampling time bit 1 mask. */ +#define ADC_SAMPDUR1_bp 1 /* Sampling time bit 1 position. */ +#define ADC_SAMPDUR2_bm (1<<2) /* Sampling time bit 2 mask. */ +#define ADC_SAMPDUR2_bp 2 /* Sampling time bit 2 position. */ +#define ADC_SAMPDUR3_bm (1<<3) /* Sampling time bit 3 mask. */ +#define ADC_SAMPDUR3_bp 3 /* Sampling time bit 3 position. */ +#define ADC_SAMPDUR4_bm (1<<4) /* Sampling time bit 4 mask. */ +#define ADC_SAMPDUR4_bp 4 /* Sampling time bit 4 position. */ +#define ADC_SAMPDUR5_bm (1<<5) /* Sampling time bit 5 mask. */ +#define ADC_SAMPDUR5_bp 5 /* Sampling time bit 5 position. */ +#define ADC_SAMPDUR6_bm (1<<6) /* Sampling time bit 6 mask. */ +#define ADC_SAMPDUR6_bp 6 /* Sampling time bit 6 position. */ +#define ADC_SAMPDUR7_bm (1<<7) /* Sampling time bit 7 mask. */ +#define ADC_SAMPDUR7_bp 7 /* Sampling time bit 7 position. */ + +/* ADC.CTRLF bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x0F /* Sample numbers group mask. */ +#define ADC_SAMPNUM_gp 0 /* Sample numbers group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Sample numbers bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Sample numbers bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Sample numbers bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Sample numbers bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Sample numbers bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Sample numbers bit 2 position. */ +#define ADC_SAMPNUM3_bm (1<<3) /* Sample numbers bit 3 mask. */ +#define ADC_SAMPNUM3_bp 3 /* Sample numbers bit 3 position. */ +#define ADC_LEFTADJ_bm 0x10 /* Left adjust bit mask. */ +#define ADC_LEFTADJ_bp 4 /* Left adjust bit position. */ +#define ADC_FREERUN_bm 0x20 /* Free running mode bit mask. */ +#define ADC_FREERUN_bp 5 /* Free running mode bit position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_START_gm 0x07 /* Start command group mask. */ +#define ADC_START_gp 0 /* Start command group position. */ +#define ADC_START0_bm (1<<0) /* Start command bit 0 mask. */ +#define ADC_START0_bp 0 /* Start command bit 0 position. */ +#define ADC_START1_bm (1<<1) /* Start command bit 1 mask. */ +#define ADC_START1_bp 1 /* Start command bit 1 position. */ +#define ADC_START2_bm (1<<2) /* Start command bit 2 mask. */ +#define ADC_START2_bp 2 /* Start command bit 2 position. */ +#define ADC_MODE_gm 0x70 /* Mode group mask. */ +#define ADC_MODE_gp 4 /* Mode group position. */ +#define ADC_MODE0_bm (1<<4) /* Mode bit 0 mask. */ +#define ADC_MODE0_bp 4 /* Mode bit 0 position. */ +#define ADC_MODE1_bm (1<<5) /* Mode bit 1 mask. */ +#define ADC_MODE1_bp 5 /* Mode bit 1 position. */ +#define ADC_MODE2_bm (1<<6) /* Mode bit 2 mask. */ +#define ADC_MODE2_bp 6 /* Mode bit 2 position. */ +#define ADC_DIFF_bm 0x80 /* Differential mode bit mask. */ +#define ADC_DIFF_bp 7 /* Differential mode bit position. */ + +/* ADC.PGACTRL bit masks and bit positions */ +#define ADC_PGAEN_bm 0x01 /* PGA Enable bit mask. */ +#define ADC_PGAEN_bp 0 /* PGA Enable bit position. */ +#define ADC_ADCPGASAMPDUR_gm 0x06 /* ADC PGA Sample Duration group mask. */ +#define ADC_ADCPGASAMPDUR_gp 1 /* ADC PGA Sample Duration group position. */ +#define ADC_ADCPGASAMPDUR0_bm (1<<1) /* ADC PGA Sample Duration bit 0 mask. */ +#define ADC_ADCPGASAMPDUR0_bp 1 /* ADC PGA Sample Duration bit 0 position. */ +#define ADC_ADCPGASAMPDUR1_bm (1<<2) /* ADC PGA Sample Duration bit 1 mask. */ +#define ADC_ADCPGASAMPDUR1_bp 2 /* ADC PGA Sample Duration bit 1 position. */ +#define ADC_PGABIASSEL_gm 0x18 /* PGA BIAS Select group mask. */ +#define ADC_PGABIASSEL_gp 3 /* PGA BIAS Select group position. */ +#define ADC_PGABIASSEL0_bm (1<<3) /* PGA BIAS Select bit 0 mask. */ +#define ADC_PGABIASSEL0_bp 3 /* PGA BIAS Select bit 0 position. */ +#define ADC_PGABIASSEL1_bm (1<<4) /* PGA BIAS Select bit 1 mask. */ +#define ADC_PGABIASSEL1_bp 4 /* PGA BIAS Select bit 1 position. */ +#define ADC_GAIN_gm 0xE0 /* Gain group mask. */ +#define ADC_GAIN_gp 5 /* Gain group position. */ +#define ADC_GAIN0_bm (1<<5) /* Gain bit 0 mask. */ +#define ADC_GAIN0_bp 5 /* Gain bit 0 position. */ +#define ADC_GAIN1_bm (1<<6) /* Gain bit 1 mask. */ +#define ADC_GAIN1_bp 6 /* Gain bit 1 position. */ +#define ADC_GAIN2_bm (1<<7) /* Gain bit 2 mask. */ +#define ADC_GAIN2_bp 7 /* Gain bit 2 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x3F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ +#define ADC_MUXPOS5_bm (1<<5) /* Analog Channel Selection Bits bit 5 mask. */ +#define ADC_MUXPOS5_bp 5 /* Analog Channel Selection Bits bit 5 position. */ +#define ADC_VIA_gm 0xC0 /* VIA group mask. */ +#define ADC_VIA_gp 6 /* VIA group position. */ +#define ADC_VIA0_bm (1<<6) /* VIA bit 0 mask. */ +#define ADC_VIA0_bp 6 /* VIA bit 0 position. */ +#define ADC_VIA1_bm (1<<7) /* VIA bit 1 mask. */ +#define ADC_VIA1_bp 7 /* VIA bit 1 position. */ + +/* ADC.MUXNEG bit masks and bit positions */ +#define ADC_MUXNEG_gm 0x3F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXNEG_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXNEG0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXNEG0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXNEG1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXNEG1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXNEG2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXNEG2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXNEG3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXNEG3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXNEG4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXNEG4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ +#define ADC_MUXNEG5_bm (1<<5) /* Analog Channel Selection Bits bit 5 mask. */ +#define ADC_MUXNEG5_bp 5 /* Analog Channel Selection Bits bit 5 position. */ +/* ADC_VIA is already defined. */ + + + +/* ADC.TEMP0 bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + +/* ADC.TEMP1 bit masks and bit positions */ +/* ADC_TEMP is already defined. */ + +/* ADC.TEMP2 bit masks and bit positions */ +/* ADC_TEMP is already defined. */ + + + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL0_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL0_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL00_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL00_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL01_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL01_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL02_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL02_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.SEQCTRL1 bit masks and bit positions */ +#define CCL_SEQSEL1_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL1_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL10_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL10_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL11_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL11_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL12_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL12_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.INTCTRL0 bit masks and bit positions */ +#define CCL_INTMODE0_gm 0x03 /* Interrupt Mode for LUT0 group mask. */ +#define CCL_INTMODE0_gp 0 /* Interrupt Mode for LUT0 group position. */ +#define CCL_INTMODE00_bm (1<<0) /* Interrupt Mode for LUT0 bit 0 mask. */ +#define CCL_INTMODE00_bp 0 /* Interrupt Mode for LUT0 bit 0 position. */ +#define CCL_INTMODE01_bm (1<<1) /* Interrupt Mode for LUT0 bit 1 mask. */ +#define CCL_INTMODE01_bp 1 /* Interrupt Mode for LUT0 bit 1 position. */ +#define CCL_INTMODE1_gm 0x0C /* Interrupt Mode for LUT1 group mask. */ +#define CCL_INTMODE1_gp 2 /* Interrupt Mode for LUT1 group position. */ +#define CCL_INTMODE10_bm (1<<2) /* Interrupt Mode for LUT1 bit 0 mask. */ +#define CCL_INTMODE10_bp 2 /* Interrupt Mode for LUT1 bit 0 position. */ +#define CCL_INTMODE11_bm (1<<3) /* Interrupt Mode for LUT1 bit 1 mask. */ +#define CCL_INTMODE11_bp 3 /* Interrupt Mode for LUT1 bit 1 position. */ +#define CCL_INTMODE2_gm 0x30 /* Interrupt Mode for LUT2 group mask. */ +#define CCL_INTMODE2_gp 4 /* Interrupt Mode for LUT2 group position. */ +#define CCL_INTMODE20_bm (1<<4) /* Interrupt Mode for LUT2 bit 0 mask. */ +#define CCL_INTMODE20_bp 4 /* Interrupt Mode for LUT2 bit 0 position. */ +#define CCL_INTMODE21_bm (1<<5) /* Interrupt Mode for LUT2 bit 1 mask. */ +#define CCL_INTMODE21_bp 5 /* Interrupt Mode for LUT2 bit 1 position. */ +#define CCL_INTMODE3_gm 0xC0 /* Interrupt Mode for LUT3 group mask. */ +#define CCL_INTMODE3_gp 6 /* Interrupt Mode for LUT3 group position. */ +#define CCL_INTMODE30_bm (1<<6) /* Interrupt Mode for LUT3 bit 0 mask. */ +#define CCL_INTMODE30_bp 6 /* Interrupt Mode for LUT3 bit 0 position. */ +#define CCL_INTMODE31_bm (1<<7) /* Interrupt Mode for LUT3 bit 1 mask. */ +#define CCL_INTMODE31_bp 7 /* Interrupt Mode for LUT3 bit 1 position. */ + +/* CCL.INTFLAGS bit masks and bit positions */ +#define CCL_INT_gm 0x0F /* Interrupt Flags group mask. */ +#define CCL_INT_gp 0 /* Interrupt Flags group position. */ +#define CCL_INT0_bm (1<<0) /* Interrupt Flags bit 0 mask. */ +#define CCL_INT0_bp 0 /* Interrupt Flags bit 0 position. */ +#define CCL_INT1_bm (1<<1) /* Interrupt Flags bit 1 mask. */ +#define CCL_INT1_bp 1 /* Interrupt Flags bit 1 position. */ +#define CCL_INT2_bm (1<<2) /* Interrupt Flags bit 2 mask. */ +#define CCL_INT2_bp 2 /* Interrupt Flags bit 2 position. */ +#define CCL_INT3_bm (1<<3) /* Interrupt Flags bit 3 mask. */ +#define CCL_INT3_bp 3 /* Interrupt Flags bit 3 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_CLKSRC_gm 0x0E /* Clock Source Selection group mask. */ +#define CCL_CLKSRC_gp 1 /* Clock Source Selection group position. */ +#define CCL_CLKSRC0_bm (1<<1) /* Clock Source Selection bit 0 mask. */ +#define CCL_CLKSRC0_bp 1 /* Clock Source Selection bit 0 position. */ +#define CCL_CLKSRC1_bm (1<<2) /* Clock Source Selection bit 1 mask. */ +#define CCL_CLKSRC1_bp 2 /* Clock Source Selection bit 1 position. */ +#define CCL_CLKSRC2_bm (1<<3) /* Clock Source Selection bit 2 mask. */ +#define CCL_CLKSRC2_bp 3 /* Clock Source Selection bit 2 position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_OUTEN_bm 0x40 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 6 /* Output Enable bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT2CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT2CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT2CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT3CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT3CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT3CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x7F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ +#define CLKCTRL_CAL20M6_bm (1<<6) /* Calibration bit 6 mask. */ +#define CLKCTRL_CAL20M6_bp 6 /* Calibration bit 6 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.SWEVENTA bit masks and bit positions */ +#define EVSYS_SWEVENTA_gm 0xFF /* Software event on channel group mask. */ +#define EVSYS_SWEVENTA_gp 0 /* Software event on channel group position. */ +#define EVSYS_SWEVENTA0_bm (1<<0) /* Software event on channel bit 0 mask. */ +#define EVSYS_SWEVENTA0_bp 0 /* Software event on channel bit 0 position. */ +#define EVSYS_SWEVENTA1_bm (1<<1) /* Software event on channel bit 1 mask. */ +#define EVSYS_SWEVENTA1_bp 1 /* Software event on channel bit 1 position. */ +#define EVSYS_SWEVENTA2_bm (1<<2) /* Software event on channel bit 2 mask. */ +#define EVSYS_SWEVENTA2_bp 2 /* Software event on channel bit 2 position. */ +#define EVSYS_SWEVENTA3_bm (1<<3) /* Software event on channel bit 3 mask. */ +#define EVSYS_SWEVENTA3_bp 3 /* Software event on channel bit 3 position. */ +#define EVSYS_SWEVENTA4_bm (1<<4) /* Software event on channel bit 4 mask. */ +#define EVSYS_SWEVENTA4_bp 4 /* Software event on channel bit 4 position. */ +#define EVSYS_SWEVENTA5_bm (1<<5) /* Software event on channel bit 5 mask. */ +#define EVSYS_SWEVENTA5_bp 5 /* Software event on channel bit 5 position. */ +#define EVSYS_SWEVENTA6_bm (1<<6) /* Software event on channel bit 6 mask. */ +#define EVSYS_SWEVENTA6_bp 6 /* Software event on channel bit 6 position. */ +#define EVSYS_SWEVENTA7_bm (1<<7) /* Software event on channel bit 7 mask. */ +#define EVSYS_SWEVENTA7_bp 7 /* Software event on channel bit 7 position. */ + +/* EVSYS.CHANNEL0 bit masks and bit positions */ +#define EVSYS_CHANNEL0_gm 0xFF /* Channel 0 generator select group mask. */ +#define EVSYS_CHANNEL0_gp 0 /* Channel 0 generator select group position. */ +#define EVSYS_CHANNEL00_bm (1<<0) /* Channel 0 generator select bit 0 mask. */ +#define EVSYS_CHANNEL00_bp 0 /* Channel 0 generator select bit 0 position. */ +#define EVSYS_CHANNEL01_bm (1<<1) /* Channel 0 generator select bit 1 mask. */ +#define EVSYS_CHANNEL01_bp 1 /* Channel 0 generator select bit 1 position. */ +#define EVSYS_CHANNEL02_bm (1<<2) /* Channel 0 generator select bit 2 mask. */ +#define EVSYS_CHANNEL02_bp 2 /* Channel 0 generator select bit 2 position. */ +#define EVSYS_CHANNEL03_bm (1<<3) /* Channel 0 generator select bit 3 mask. */ +#define EVSYS_CHANNEL03_bp 3 /* Channel 0 generator select bit 3 position. */ +#define EVSYS_CHANNEL04_bm (1<<4) /* Channel 0 generator select bit 4 mask. */ +#define EVSYS_CHANNEL04_bp 4 /* Channel 0 generator select bit 4 position. */ +#define EVSYS_CHANNEL05_bm (1<<5) /* Channel 0 generator select bit 5 mask. */ +#define EVSYS_CHANNEL05_bp 5 /* Channel 0 generator select bit 5 position. */ +#define EVSYS_CHANNEL06_bm (1<<6) /* Channel 0 generator select bit 6 mask. */ +#define EVSYS_CHANNEL06_bp 6 /* Channel 0 generator select bit 6 position. */ +#define EVSYS_CHANNEL07_bm (1<<7) /* Channel 0 generator select bit 7 mask. */ +#define EVSYS_CHANNEL07_bp 7 /* Channel 0 generator select bit 7 position. */ + +/* EVSYS.CHANNEL1 bit masks and bit positions */ +#define EVSYS_CHANNEL1_gm 0xFF /* Channel 1 generator select group mask. */ +#define EVSYS_CHANNEL1_gp 0 /* Channel 1 generator select group position. */ +#define EVSYS_CHANNEL10_bm (1<<0) /* Channel 1 generator select bit 0 mask. */ +#define EVSYS_CHANNEL10_bp 0 /* Channel 1 generator select bit 0 position. */ +#define EVSYS_CHANNEL11_bm (1<<1) /* Channel 1 generator select bit 1 mask. */ +#define EVSYS_CHANNEL11_bp 1 /* Channel 1 generator select bit 1 position. */ +#define EVSYS_CHANNEL12_bm (1<<2) /* Channel 1 generator select bit 2 mask. */ +#define EVSYS_CHANNEL12_bp 2 /* Channel 1 generator select bit 2 position. */ +#define EVSYS_CHANNEL13_bm (1<<3) /* Channel 1 generator select bit 3 mask. */ +#define EVSYS_CHANNEL13_bp 3 /* Channel 1 generator select bit 3 position. */ +#define EVSYS_CHANNEL14_bm (1<<4) /* Channel 1 generator select bit 4 mask. */ +#define EVSYS_CHANNEL14_bp 4 /* Channel 1 generator select bit 4 position. */ +#define EVSYS_CHANNEL15_bm (1<<5) /* Channel 1 generator select bit 5 mask. */ +#define EVSYS_CHANNEL15_bp 5 /* Channel 1 generator select bit 5 position. */ +#define EVSYS_CHANNEL16_bm (1<<6) /* Channel 1 generator select bit 6 mask. */ +#define EVSYS_CHANNEL16_bp 6 /* Channel 1 generator select bit 6 position. */ +#define EVSYS_CHANNEL17_bm (1<<7) /* Channel 1 generator select bit 7 mask. */ +#define EVSYS_CHANNEL17_bp 7 /* Channel 1 generator select bit 7 position. */ + +/* EVSYS.CHANNEL2 bit masks and bit positions */ +#define EVSYS_CHANNEL2_gm 0xFF /* Channel 2 generator select group mask. */ +#define EVSYS_CHANNEL2_gp 0 /* Channel 2 generator select group position. */ +#define EVSYS_CHANNEL20_bm (1<<0) /* Channel 2 generator select bit 0 mask. */ +#define EVSYS_CHANNEL20_bp 0 /* Channel 2 generator select bit 0 position. */ +#define EVSYS_CHANNEL21_bm (1<<1) /* Channel 2 generator select bit 1 mask. */ +#define EVSYS_CHANNEL21_bp 1 /* Channel 2 generator select bit 1 position. */ +#define EVSYS_CHANNEL22_bm (1<<2) /* Channel 2 generator select bit 2 mask. */ +#define EVSYS_CHANNEL22_bp 2 /* Channel 2 generator select bit 2 position. */ +#define EVSYS_CHANNEL23_bm (1<<3) /* Channel 2 generator select bit 3 mask. */ +#define EVSYS_CHANNEL23_bp 3 /* Channel 2 generator select bit 3 position. */ +#define EVSYS_CHANNEL24_bm (1<<4) /* Channel 2 generator select bit 4 mask. */ +#define EVSYS_CHANNEL24_bp 4 /* Channel 2 generator select bit 4 position. */ +#define EVSYS_CHANNEL25_bm (1<<5) /* Channel 2 generator select bit 5 mask. */ +#define EVSYS_CHANNEL25_bp 5 /* Channel 2 generator select bit 5 position. */ +#define EVSYS_CHANNEL26_bm (1<<6) /* Channel 2 generator select bit 6 mask. */ +#define EVSYS_CHANNEL26_bp 6 /* Channel 2 generator select bit 6 position. */ +#define EVSYS_CHANNEL27_bm (1<<7) /* Channel 2 generator select bit 7 mask. */ +#define EVSYS_CHANNEL27_bp 7 /* Channel 2 generator select bit 7 position. */ + +/* EVSYS.CHANNEL3 bit masks and bit positions */ +#define EVSYS_CHANNEL3_gm 0xFF /* Channel 3 generator select group mask. */ +#define EVSYS_CHANNEL3_gp 0 /* Channel 3 generator select group position. */ +#define EVSYS_CHANNEL30_bm (1<<0) /* Channel 3 generator select bit 0 mask. */ +#define EVSYS_CHANNEL30_bp 0 /* Channel 3 generator select bit 0 position. */ +#define EVSYS_CHANNEL31_bm (1<<1) /* Channel 3 generator select bit 1 mask. */ +#define EVSYS_CHANNEL31_bp 1 /* Channel 3 generator select bit 1 position. */ +#define EVSYS_CHANNEL32_bm (1<<2) /* Channel 3 generator select bit 2 mask. */ +#define EVSYS_CHANNEL32_bp 2 /* Channel 3 generator select bit 2 position. */ +#define EVSYS_CHANNEL33_bm (1<<3) /* Channel 3 generator select bit 3 mask. */ +#define EVSYS_CHANNEL33_bp 3 /* Channel 3 generator select bit 3 position. */ +#define EVSYS_CHANNEL34_bm (1<<4) /* Channel 3 generator select bit 4 mask. */ +#define EVSYS_CHANNEL34_bp 4 /* Channel 3 generator select bit 4 position. */ +#define EVSYS_CHANNEL35_bm (1<<5) /* Channel 3 generator select bit 5 mask. */ +#define EVSYS_CHANNEL35_bp 5 /* Channel 3 generator select bit 5 position. */ +#define EVSYS_CHANNEL36_bm (1<<6) /* Channel 3 generator select bit 6 mask. */ +#define EVSYS_CHANNEL36_bp 6 /* Channel 3 generator select bit 6 position. */ +#define EVSYS_CHANNEL37_bm (1<<7) /* Channel 3 generator select bit 7 mask. */ +#define EVSYS_CHANNEL37_bp 7 /* Channel 3 generator select bit 7 position. */ + +/* EVSYS.CHANNEL4 bit masks and bit positions */ +#define EVSYS_CHANNEL4_gm 0xFF /* Channel 4 generator select group mask. */ +#define EVSYS_CHANNEL4_gp 0 /* Channel 4 generator select group position. */ +#define EVSYS_CHANNEL40_bm (1<<0) /* Channel 4 generator select bit 0 mask. */ +#define EVSYS_CHANNEL40_bp 0 /* Channel 4 generator select bit 0 position. */ +#define EVSYS_CHANNEL41_bm (1<<1) /* Channel 4 generator select bit 1 mask. */ +#define EVSYS_CHANNEL41_bp 1 /* Channel 4 generator select bit 1 position. */ +#define EVSYS_CHANNEL42_bm (1<<2) /* Channel 4 generator select bit 2 mask. */ +#define EVSYS_CHANNEL42_bp 2 /* Channel 4 generator select bit 2 position. */ +#define EVSYS_CHANNEL43_bm (1<<3) /* Channel 4 generator select bit 3 mask. */ +#define EVSYS_CHANNEL43_bp 3 /* Channel 4 generator select bit 3 position. */ +#define EVSYS_CHANNEL44_bm (1<<4) /* Channel 4 generator select bit 4 mask. */ +#define EVSYS_CHANNEL44_bp 4 /* Channel 4 generator select bit 4 position. */ +#define EVSYS_CHANNEL45_bm (1<<5) /* Channel 4 generator select bit 5 mask. */ +#define EVSYS_CHANNEL45_bp 5 /* Channel 4 generator select bit 5 position. */ +#define EVSYS_CHANNEL46_bm (1<<6) /* Channel 4 generator select bit 6 mask. */ +#define EVSYS_CHANNEL46_bp 6 /* Channel 4 generator select bit 6 position. */ +#define EVSYS_CHANNEL47_bm (1<<7) /* Channel 4 generator select bit 7 mask. */ +#define EVSYS_CHANNEL47_bp 7 /* Channel 4 generator select bit 7 position. */ + +/* EVSYS.CHANNEL5 bit masks and bit positions */ +#define EVSYS_CHANNEL5_gm 0xFF /* Channel 5 generator select group mask. */ +#define EVSYS_CHANNEL5_gp 0 /* Channel 5 generator select group position. */ +#define EVSYS_CHANNEL50_bm (1<<0) /* Channel 5 generator select bit 0 mask. */ +#define EVSYS_CHANNEL50_bp 0 /* Channel 5 generator select bit 0 position. */ +#define EVSYS_CHANNEL51_bm (1<<1) /* Channel 5 generator select bit 1 mask. */ +#define EVSYS_CHANNEL51_bp 1 /* Channel 5 generator select bit 1 position. */ +#define EVSYS_CHANNEL52_bm (1<<2) /* Channel 5 generator select bit 2 mask. */ +#define EVSYS_CHANNEL52_bp 2 /* Channel 5 generator select bit 2 position. */ +#define EVSYS_CHANNEL53_bm (1<<3) /* Channel 5 generator select bit 3 mask. */ +#define EVSYS_CHANNEL53_bp 3 /* Channel 5 generator select bit 3 position. */ +#define EVSYS_CHANNEL54_bm (1<<4) /* Channel 5 generator select bit 4 mask. */ +#define EVSYS_CHANNEL54_bp 4 /* Channel 5 generator select bit 4 position. */ +#define EVSYS_CHANNEL55_bm (1<<5) /* Channel 5 generator select bit 5 mask. */ +#define EVSYS_CHANNEL55_bp 5 /* Channel 5 generator select bit 5 position. */ +#define EVSYS_CHANNEL56_bm (1<<6) /* Channel 5 generator select bit 6 mask. */ +#define EVSYS_CHANNEL56_bp 6 /* Channel 5 generator select bit 6 position. */ +#define EVSYS_CHANNEL57_bm (1<<7) /* Channel 5 generator select bit 7 mask. */ +#define EVSYS_CHANNEL57_bp 7 /* Channel 5 generator select bit 7 position. */ + +/* EVSYS.USERCCLLUT0A bit masks and bit positions */ +#define EVSYS_USER_gm 0xFF /* Channel selector group mask. */ +#define EVSYS_USER_gp 0 /* Channel selector group position. */ +#define EVSYS_USER0_bm (1<<0) /* Channel selector bit 0 mask. */ +#define EVSYS_USER0_bp 0 /* Channel selector bit 0 position. */ +#define EVSYS_USER1_bm (1<<1) /* Channel selector bit 1 mask. */ +#define EVSYS_USER1_bp 1 /* Channel selector bit 1 position. */ +#define EVSYS_USER2_bm (1<<2) /* Channel selector bit 2 mask. */ +#define EVSYS_USER2_bp 2 /* Channel selector bit 2 position. */ +#define EVSYS_USER3_bm (1<<3) /* Channel selector bit 3 mask. */ +#define EVSYS_USER3_bp 3 /* Channel selector bit 3 position. */ +#define EVSYS_USER4_bm (1<<4) /* Channel selector bit 4 mask. */ +#define EVSYS_USER4_bp 4 /* Channel selector bit 4 position. */ +#define EVSYS_USER5_bm (1<<5) /* Channel selector bit 5 mask. */ +#define EVSYS_USER5_bp 5 /* Channel selector bit 5 position. */ +#define EVSYS_USER6_bm (1<<6) /* Channel selector bit 6 mask. */ +#define EVSYS_USER6_bp 6 /* Channel selector bit 6 position. */ +#define EVSYS_USER7_bm (1<<7) /* Channel selector bit 7 mask. */ +#define EVSYS_USER7_bp 7 /* Channel selector bit 7 position. */ + +/* EVSYS.USERCCLLUT0B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT1A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT1B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT2A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT2B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT3A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT3B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERADC0START bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTC bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART0IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART1IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA0CNTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA0CNTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB0CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB0COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB1CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB1COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMBIST - BIST in the NVMCTRL module */ +/* NVMBIST.CTRLA bit masks and bit positions */ +#define NVMBIST_CMD_gm 0x07 /* Command group mask. */ +#define NVMBIST_CMD_gp 0 /* Command group position. */ +#define NVMBIST_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMBIST_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMBIST_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMBIST_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMBIST_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMBIST_CMD2_bp 2 /* Command bit 2 position. */ +#define NVMBIST_SAF_bm 0x08 /* Stop at fault bit mask. */ +#define NVMBIST_SAF_bp 3 /* Stop at fault bit position. */ + +/* NVMBIST.ADDRPAT bit masks and bit positions */ +#define NVMBIST_XMODE_gm 0x03 /* X address mode group mask. */ +#define NVMBIST_XMODE_gp 0 /* X address mode group position. */ +#define NVMBIST_XMODE0_bm (1<<0) /* X address mode bit 0 mask. */ +#define NVMBIST_XMODE0_bp 0 /* X address mode bit 0 position. */ +#define NVMBIST_XMODE1_bm (1<<1) /* X address mode bit 1 mask. */ +#define NVMBIST_XMODE1_bp 1 /* X address mode bit 1 position. */ +#define NVMBIST_YMODE_gm 0x0C /* Y address mode group mask. */ +#define NVMBIST_YMODE_gp 2 /* Y address mode group position. */ +#define NVMBIST_YMODE0_bm (1<<2) /* Y address mode bit 0 mask. */ +#define NVMBIST_YMODE0_bp 2 /* Y address mode bit 0 position. */ +#define NVMBIST_YMODE1_bm (1<<3) /* Y address mode bit 1 mask. */ +#define NVMBIST_YMODE1_bp 3 /* Y address mode bit 1 position. */ +#define NVMBIST_AMODE_gm 0x70 /* Address mode group mask. */ +#define NVMBIST_AMODE_gp 4 /* Address mode group position. */ +#define NVMBIST_AMODE0_bm (1<<4) /* Address mode bit 0 mask. */ +#define NVMBIST_AMODE0_bp 4 /* Address mode bit 0 position. */ +#define NVMBIST_AMODE1_bm (1<<5) /* Address mode bit 1 mask. */ +#define NVMBIST_AMODE1_bp 5 /* Address mode bit 1 position. */ +#define NVMBIST_AMODE2_bm (1<<6) /* Address mode bit 2 mask. */ +#define NVMBIST_AMODE2_bp 6 /* Address mode bit 2 position. */ + +/* NVMBIST.DATAPAT bit masks and bit positions */ +#define NVMBIST_PATTERN_gm 0x03 /* Data check pattern group mask. */ +#define NVMBIST_PATTERN_gp 0 /* Data check pattern group position. */ +#define NVMBIST_PATTERN0_bm (1<<0) /* Data check pattern bit 0 mask. */ +#define NVMBIST_PATTERN0_bp 0 /* Data check pattern bit 0 position. */ +#define NVMBIST_PATTERN1_bm (1<<1) /* Data check pattern bit 1 mask. */ +#define NVMBIST_PATTERN1_bp 1 /* Data check pattern bit 1 position. */ + +/* NVMBIST.STATUS bit masks and bit positions */ +#define NVMBIST_STATE_gm 0x0F /* FSM State group mask. */ +#define NVMBIST_STATE_gp 0 /* FSM State group position. */ +#define NVMBIST_STATE0_bm (1<<0) /* FSM State bit 0 mask. */ +#define NVMBIST_STATE0_bp 0 /* FSM State bit 0 position. */ +#define NVMBIST_STATE1_bm (1<<1) /* FSM State bit 1 mask. */ +#define NVMBIST_STATE1_bp 1 /* FSM State bit 1 position. */ +#define NVMBIST_STATE2_bm (1<<2) /* FSM State bit 2 mask. */ +#define NVMBIST_STATE2_bp 2 /* FSM State bit 2 position. */ +#define NVMBIST_STATE3_bm (1<<3) /* FSM State bit 3 mask. */ +#define NVMBIST_STATE3_bp 3 /* FSM State bit 3 position. */ + +/* NVMBIST.CNT bit masks and bit positions */ +#define NVMBIST_CNT_gm 0x7FF /* Faults counter group mask. */ +#define NVMBIST_CNT_gp 0 /* Faults counter group position. */ +#define NVMBIST_CNT0_bm (1<<0) /* Faults counter bit 0 mask. */ +#define NVMBIST_CNT0_bp 0 /* Faults counter bit 0 position. */ +#define NVMBIST_CNT1_bm (1<<1) /* Faults counter bit 1 mask. */ +#define NVMBIST_CNT1_bp 1 /* Faults counter bit 1 position. */ +#define NVMBIST_CNT2_bm (1<<2) /* Faults counter bit 2 mask. */ +#define NVMBIST_CNT2_bp 2 /* Faults counter bit 2 position. */ +#define NVMBIST_CNT3_bm (1<<3) /* Faults counter bit 3 mask. */ +#define NVMBIST_CNT3_bp 3 /* Faults counter bit 3 position. */ +#define NVMBIST_CNT4_bm (1<<4) /* Faults counter bit 4 mask. */ +#define NVMBIST_CNT4_bp 4 /* Faults counter bit 4 position. */ +#define NVMBIST_CNT5_bm (1<<5) /* Faults counter bit 5 mask. */ +#define NVMBIST_CNT5_bp 5 /* Faults counter bit 5 position. */ +#define NVMBIST_CNT6_bm (1<<6) /* Faults counter bit 6 mask. */ +#define NVMBIST_CNT6_bp 6 /* Faults counter bit 6 position. */ +#define NVMBIST_CNT7_bm (1<<7) /* Faults counter bit 7 mask. */ +#define NVMBIST_CNT7_bp 7 /* Faults counter bit 7 position. */ +#define NVMBIST_CNT8_bm (1<<8) /* Faults counter bit 8 mask. */ +#define NVMBIST_CNT8_bp 8 /* Faults counter bit 8 position. */ +#define NVMBIST_CNT9_bm (1<<9) /* Faults counter bit 9 mask. */ +#define NVMBIST_CNT9_bp 9 /* Faults counter bit 9 position. */ +#define NVMBIST_CNT10_bm (1<<10) /* Faults counter bit 10 mask. */ +#define NVMBIST_CNT10_bp 10 /* Faults counter bit 10 position. */ + +/* NVMBIST.END bit masks and bit positions */ +#define NVMBIST_END_gm 0xFFFFFF /* group mask. */ +#define NVMBIST_END_gp 0 /* group position. */ +#define NVMBIST_END0_bm (1<<0) /* bit 0 mask. */ +#define NVMBIST_END0_bp 0 /* bit 0 position. */ +#define NVMBIST_END1_bm (1<<1) /* bit 1 mask. */ +#define NVMBIST_END1_bp 1 /* bit 1 position. */ +#define NVMBIST_END2_bm (1<<2) /* bit 2 mask. */ +#define NVMBIST_END2_bp 2 /* bit 2 position. */ +#define NVMBIST_END3_bm (1<<3) /* bit 3 mask. */ +#define NVMBIST_END3_bp 3 /* bit 3 position. */ +#define NVMBIST_END4_bm (1<<4) /* bit 4 mask. */ +#define NVMBIST_END4_bp 4 /* bit 4 position. */ +#define NVMBIST_END5_bm (1<<5) /* bit 5 mask. */ +#define NVMBIST_END5_bp 5 /* bit 5 position. */ +#define NVMBIST_END6_bm (1<<6) /* bit 6 mask. */ +#define NVMBIST_END6_bp 6 /* bit 6 position. */ +#define NVMBIST_END7_bm (1<<7) /* bit 7 mask. */ +#define NVMBIST_END7_bp 7 /* bit 7 position. */ +#define NVMBIST_END8_bm (1<<8) /* bit 8 mask. */ +#define NVMBIST_END8_bp 8 /* bit 8 position. */ +#define NVMBIST_END9_bm (1<<9) /* bit 9 mask. */ +#define NVMBIST_END9_bp 9 /* bit 9 position. */ +#define NVMBIST_END10_bm (1<<10) /* bit 10 mask. */ +#define NVMBIST_END10_bp 10 /* bit 10 position. */ +#define NVMBIST_END11_bm (1<<11) /* bit 11 mask. */ +#define NVMBIST_END11_bp 11 /* bit 11 position. */ +#define NVMBIST_END12_bm (1<<12) /* bit 12 mask. */ +#define NVMBIST_END12_bp 12 /* bit 12 position. */ +#define NVMBIST_END13_bm (1<<13) /* bit 13 mask. */ +#define NVMBIST_END13_bp 13 /* bit 13 position. */ +#define NVMBIST_END14_bm (1<<14) /* bit 14 mask. */ +#define NVMBIST_END14_bp 14 /* bit 14 position. */ +#define NVMBIST_END15_bm (1<<15) /* bit 15 mask. */ +#define NVMBIST_END15_bp 15 /* bit 15 position. */ +#define NVMBIST_END16_bm (1<<16) /* bit 16 mask. */ +#define NVMBIST_END16_bp 16 /* bit 16 position. */ +#define NVMBIST_END17_bm (1<<17) /* bit 17 mask. */ +#define NVMBIST_END17_bp 17 /* bit 17 position. */ +#define NVMBIST_END18_bm (1<<18) /* bit 18 mask. */ +#define NVMBIST_END18_bp 18 /* bit 18 position. */ +#define NVMBIST_END19_bm (1<<19) /* bit 19 mask. */ +#define NVMBIST_END19_bp 19 /* bit 19 position. */ +#define NVMBIST_END20_bm (1<<20) /* bit 20 mask. */ +#define NVMBIST_END20_bp 20 /* bit 20 position. */ +#define NVMBIST_END21_bm (1<<21) /* bit 21 mask. */ +#define NVMBIST_END21_bp 21 /* bit 21 position. */ +#define NVMBIST_END22_bm (1<<22) /* bit 22 mask. */ +#define NVMBIST_END22_bp 22 /* bit 22 position. */ +#define NVMBIST_END23_bm (1<<23) /* bit 23 mask. */ +#define NVMBIST_END23_bp 23 /* bit 23 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PORTCTRL bit masks and bit positions */ +#define PORT_SRL_bm 0x01 /* Slew Rate Limit Enable bit mask. */ +#define PORT_SRL_bp 0 /* Slew Rate Limit Enable bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.EVSYSROUTEA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_EVOUT3_bm 0x08 /* Event Output 3 bit mask. */ +#define PORTMUX_EVOUT3_bp 3 /* Event Output 3 bit position. */ +#define PORTMUX_EVOUT4_bm 0x10 /* Event Output 4 bit mask. */ +#define PORTMUX_EVOUT4_bp 4 /* Event Output 4 bit position. */ +#define PORTMUX_EVOUT5_bm 0x20 /* Event Output 5 bit mask. */ +#define PORTMUX_EVOUT5_bp 5 /* Event Output 5 bit position. */ + +/* PORTMUX.CCLROUTEA bit masks and bit positions */ +#define PORTMUX_LUT0_bm 0x01 /* CCL LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 0 /* CCL LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x02 /* CCL LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 1 /* CCL LUT1 bit position. */ +#define PORTMUX_LUT2_bm 0x04 /* CCL LUT2 bit mask. */ +#define PORTMUX_LUT2_bp 2 /* CCL LUT2 bit position. */ +#define PORTMUX_LUT3_bm 0x08 /* CCL LUT3 bit mask. */ +#define PORTMUX_LUT3_bp 3 /* CCL LUT3 bit position. */ + +/* PORTMUX.USARTROUTEA bit masks and bit positions */ +#define PORTMUX_USART0_gm 0x03 /* Port Multiplexer USART0 group mask. */ +#define PORTMUX_USART0_gp 0 /* Port Multiplexer USART0 group position. */ +#define PORTMUX_USART00_bm (1<<0) /* Port Multiplexer USART0 bit 0 mask. */ +#define PORTMUX_USART00_bp 0 /* Port Multiplexer USART0 bit 0 position. */ +#define PORTMUX_USART01_bm (1<<1) /* Port Multiplexer USART0 bit 1 mask. */ +#define PORTMUX_USART01_bp 1 /* Port Multiplexer USART0 bit 1 position. */ +#define PORTMUX_USART1_gm 0x0C /* Port Multiplexer USART1 group mask. */ +#define PORTMUX_USART1_gp 2 /* Port Multiplexer USART1 group position. */ +#define PORTMUX_USART10_bm (1<<2) /* Port Multiplexer USART1 bit 0 mask. */ +#define PORTMUX_USART10_bp 2 /* Port Multiplexer USART1 bit 0 position. */ +#define PORTMUX_USART11_bm (1<<3) /* Port Multiplexer USART1 bit 1 mask. */ +#define PORTMUX_USART11_bp 3 /* Port Multiplexer USART1 bit 1 position. */ + +/* PORTMUX.SPIROUTEA bit masks and bit positions */ +#define PORTMUX_SPI0_gm 0x03 /* Port Multiplexer SPI0 group mask. */ +#define PORTMUX_SPI0_gp 0 /* Port Multiplexer SPI0 group position. */ +#define PORTMUX_SPI00_bm (1<<0) /* Port Multiplexer SPI0 bit 0 mask. */ +#define PORTMUX_SPI00_bp 0 /* Port Multiplexer SPI0 bit 0 position. */ +#define PORTMUX_SPI01_bm (1<<1) /* Port Multiplexer SPI0 bit 1 mask. */ +#define PORTMUX_SPI01_bp 1 /* Port Multiplexer SPI0 bit 1 position. */ +#define PORTMUX_TWI0_gm 0x30 /* Port Multiplexer TWI0 group mask. */ +#define PORTMUX_TWI0_gp 4 /* Port Multiplexer TWI0 group position. */ +#define PORTMUX_TWI00_bm (1<<4) /* Port Multiplexer TWI0 bit 0 mask. */ +#define PORTMUX_TWI00_bp 4 /* Port Multiplexer TWI0 bit 0 position. */ +#define PORTMUX_TWI01_bm (1<<5) /* Port Multiplexer TWI0 bit 1 mask. */ +#define PORTMUX_TWI01_bp 5 /* Port Multiplexer TWI0 bit 1 position. */ + +/* PORTMUX.TCAROUTEA bit masks and bit positions */ +#define PORTMUX_TCA0_gm 0x07 /* Port Multiplexer TCA0 group mask. */ +#define PORTMUX_TCA0_gp 0 /* Port Multiplexer TCA0 group position. */ +#define PORTMUX_TCA00_bm (1<<0) /* Port Multiplexer TCA0 bit 0 mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 bit 0 position. */ +#define PORTMUX_TCA01_bm (1<<1) /* Port Multiplexer TCA0 bit 1 mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 bit 1 position. */ +#define PORTMUX_TCA02_bm (1<<2) /* Port Multiplexer TCA0 bit 2 mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 bit 2 position. */ + +/* PORTMUX.TCBROUTEA bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ +#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ +#define PORTMUX_TCB2_bm 0x04 /* Port Multiplexer TCB2 bit mask. */ +#define PORTMUX_TCB2_bp 2 /* Port Multiplexer TCB2 bit position. */ +#define PORTMUX_TCB3_bm 0x08 /* Port Multiplexer TCB3 bit mask. */ +#define PORTMUX_TCB3_bp 3 /* Port Multiplexer TCB3 bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_CORREN_bm 0x04 /* Correction enable bit mask. */ +#define RTC_CORREN_bp 2 /* Correction enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_ERROR_gm 0x7F /* Error Correction Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Correction Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Correction Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Correction Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Correction Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Correction Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Correction Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Correction Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Correction Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Correction Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Correction Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Correction Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Correction Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Correction Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Correction Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Correction Value bit 6 position. */ +#define RTC_SIGN_bm 0x80 /* Error Correction Sign Bit bit mask. */ +#define RTC_SIGN_bp 7 /* Error Correction Sign Bit bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Mode Wait for Receive bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Mode Wait for Receive bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + + +/* SYSCFG.OCDMS bit masks and bit positions */ +#define SYSCFG_OCDMR_bm 0x01 /* OCD Message Read bit mask. */ +#define SYSCFG_OCDMR_bp 0 /* OCD Message Read bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ +#define TCA_SINGLE_RUNSTDBY_bm 0x80 /* Run in Standby bit mask. */ +#define TCA_SINGLE_RUNSTDBY_bp 7 /* Run in Standby bit position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTAEI_bm 0x01 /* Count on Event Input A bit mask. */ +#define TCA_SINGLE_CNTAEI_bp 0 /* Count on Event Input A bit position. */ +#define TCA_SINGLE_EVACTA_gm 0x0E /* Event Action A group mask. */ +#define TCA_SINGLE_EVACTA_gp 1 /* Event Action A group position. */ +#define TCA_SINGLE_EVACTA0_bm (1<<1) /* Event Action A bit 0 mask. */ +#define TCA_SINGLE_EVACTA0_bp 1 /* Event Action A bit 0 position. */ +#define TCA_SINGLE_EVACTA1_bm (1<<2) /* Event Action A bit 1 mask. */ +#define TCA_SINGLE_EVACTA1_bp 2 /* Event Action A bit 1 position. */ +#define TCA_SINGLE_EVACTA2_bm (1<<3) /* Event Action A bit 2 mask. */ +#define TCA_SINGLE_EVACTA2_bp 3 /* Event Action A bit 2 position. */ +#define TCA_SINGLE_CNTBEI_bm 0x10 /* Count on Event Input B bit mask. */ +#define TCA_SINGLE_CNTBEI_bp 4 /* Count on Event Input B bit position. */ +#define TCA_SINGLE_EVACTB_gm 0xE0 /* Event Action B group mask. */ +#define TCA_SINGLE_EVACTB_gp 5 /* Event Action B group position. */ +#define TCA_SINGLE_EVACTB0_bm (1<<5) /* Event Action B bit 0 mask. */ +#define TCA_SINGLE_EVACTB0_bp 5 /* Event Action B bit 0 position. */ +#define TCA_SINGLE_EVACTB1_bm (1<<6) /* Event Action B bit 1 mask. */ +#define TCA_SINGLE_EVACTB1_bp 6 /* Event Action B bit 1 position. */ +#define TCA_SINGLE_EVACTB2_bm (1<<7) /* Event Action B bit 2 mask. */ +#define TCA_SINGLE_EVACTB2_bp 7 /* Event Action B bit 2 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ +#define TCA_SPLIT_RUNSTDBY_bm 0x80 /* Run in Standby bit mask. */ +#define TCA_SPLIT_RUNSTDBY_bp 7 /* Run in Standby bit position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TCA_SPLIT_CMDEN_gp 0 /* Command Enable group position. */ +#define TCA_SPLIT_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TCA_SPLIT_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TCA_SPLIT_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TCA_SPLIT_CMDEN1_bp 1 /* Command Enable bit 1 position. */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMDEN is already defined. */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x0E /* TCB Clock group mask. */ +#define TCB_CLKSEL_gp 1 /* TCB Clock group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* TCB Clock bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* TCB Clock bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* TCB Clock bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* TCB Clock bit 1 position. */ +#define TCB_CLKSEL2_bm (1<<3) /* TCB Clock bit 2 mask. */ +#define TCB_CLKSEL2_bp 3 /* TCB Clock bit 2 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_CASCADE_bm 0x20 /* Cascade two timers bit mask. */ +#define TCB_CASCADE_bp 5 /* Cascade two timers bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ +#define TCB_OVF_bm 0x02 /* Overflow bit mask. */ +#define TCB_OVF_bp 1 /* Overflow bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ +/* TCB_OVF is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Permissive Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Permissive Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_bm 0x01 /* RS485 Mode internal transmitter bit mask. */ +#define USART_RS485_bp 0 /* RS485 Mode internal transmitter bit position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.CTRLD bit masks and bit positions */ +#define USART_ABW_gm 0xC0 /* Auto Baud Window group mask. */ +#define USART_ABW_gp 6 /* Auto Baud Window group position. */ +#define USART_ABW0_bm (1<<6) /* Auto Baud Window bit 0 mask. */ +#define USART_ABW0_bp 6 /* Auto Baud Window bit 0 position. */ +#define USART_ABW1_bm (1<<7) /* Auto Baud Window bit 1 mask. */ +#define USART_ABW1_bp 7 /* Auto Baud Window bit 1 position. */ + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_AC0REFSEL_gm 0x07 /* AC0 reference select group mask. */ +#define VREF_AC0REFSEL_gp 0 /* AC0 reference select group position. */ +#define VREF_AC0REFSEL0_bm (1<<0) /* AC0 reference select bit 0 mask. */ +#define VREF_AC0REFSEL0_bp 0 /* AC0 reference select bit 0 position. */ +#define VREF_AC0REFSEL1_bm (1<<1) /* AC0 reference select bit 1 mask. */ +#define VREF_AC0REFSEL1_bp 1 /* AC0 reference select bit 1 position. */ +#define VREF_AC0REFSEL2_bm (1<<2) /* AC0 reference select bit 2 mask. */ +#define VREF_AC0REFSEL2_bp 2 /* AC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_AC0REFEN_bm 0x01 /* AC0 DACREF reference enable bit mask. */ +#define VREF_AC0REFEN_bp 0 /* AC0 DACREF reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ +#define VREF_NVMREFEN_bm 0x04 /* NVM reference enable bit mask. */ +#define VREF_NVMREFEN_bp 2 /* NVM reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 3 +#define RTC_CNT_vect _VECTOR(3) /* */ +#define RTC_PIT_vect_num 4 +#define RTC_PIT_vect _VECTOR(4) /* */ + +/* CCL interrupt vectors */ +#define CCL_CCL_vect_num 5 +#define CCL_CCL_vect _VECTOR(5) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 6 +#define PORTA_PORT_vect _VECTOR(6) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 7 +#define PORTB_PORT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 14 +#define TWI0_TWIS_vect _VECTOR(14) /* */ +#define TWI0_TWIM_vect_num 15 +#define TWI0_TWIM_vect _VECTOR(15) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 16 +#define SPI0_INT_vect _VECTOR(16) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 17 +#define USART0_RXC_vect _VECTOR(17) /* */ +#define USART0_DRE_vect_num 18 +#define USART0_DRE_vect _VECTOR(18) /* */ +#define USART0_TXC_vect_num 19 +#define USART0_TXC_vect _VECTOR(19) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 20 +#define AC0_AC_vect _VECTOR(20) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_ERROR_vect_num 21 +#define ADC0_ERROR_vect _VECTOR(21) /* */ +#define ADC0_RESRDY_vect_num 22 +#define ADC0_RESRDY_vect _VECTOR(22) /* */ +#define ADC0_SAMPRDY_vect_num 23 +#define ADC0_SAMPRDY_vect _VECTOR(23) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 24 +#define PORTC_PORT_vect _VECTOR(24) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 25 +#define TCB1_INT_vect _VECTOR(25) /* */ + +/* USART1 interrupt vectors */ +#define USART1_RXC_vect_num 26 +#define USART1_RXC_vect _VECTOR(26) /* */ +#define USART1_DRE_vect_num 27 +#define USART1_DRE_vect _VECTOR(27) /* */ +#define USART1_TXC_vect_num 28 +#define USART1_TXC_vect _VECTOR(28) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 29 +#define NVMCTRL_EE_vect _VECTOR(29) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (30 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (49152) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (49152U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3800) +# define INTERNAL_SRAM_SIZE (2048) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3800U) +# define INTERNAL_SRAM_SIZE (2048U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (16384) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (16384U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (16384) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (16384U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x29 + + +#endif /* #ifdef _AVR_ATTINY1626_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn1627.h b/hardware/tools/avr/avr/include/avr/iotn1627.h new file mode 100644 index 0000000000000000000000000000000000000000..222ff24b91e1aaba168705ef3d3a7464044ccdcc --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn1627.h @@ -0,0 +1,5497 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn1627.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY1627_H_INCLUDED +#define _AVR_ATTINY1627_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPZ _SFR_MEM8(0x003B) /* Extended Z-pointer Register */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[1]; + register8_t DACREF; /* Referance scale control */ + register8_t reserved_3[1]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Both Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_PIN2_gc = (0x02<<0), /* Negative Pin 2 */ + AC_MUXNEG_DACREF_gc = (0x03<<0), /* DAC Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status register */ + register8_t DBGCTRL; /* Debug Control */ + register8_t CTRLE; /* Control E */ + register8_t CTRLF; /* Control F */ + register8_t COMMAND; /* Command register */ + register8_t PGACTRL; /* PGA Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t MUXNEG; /* Negative mux input */ + register8_t reserved_1[2]; + _DWORDREGISTER(RESULT); /* Result */ + _WORDREGISTER(SAMPLE); /* Sample */ + register8_t reserved_2[2]; + register8_t TEMP0; /* Temporary Data 0 */ + register8_t TEMP1; /* Temporary Data 1 */ + register8_t TEMP2; /* Temporary Data 2 */ + register8_t reserved_3[1]; + _WORDREGISTER(WINLT); /* Window Low Threshold */ + _WORDREGISTER(WINHT); /* Window High Threshold */ + register8_t reserved_4[32]; +} ADC_t; + +/* ADC PGA Sample Duration select */ +typedef enum ADC_ADCPGASAMPDUR_enum +{ + ADC_ADCPGASAMPDUR_6CLK_gc = (0x00<<1), /* 6 ADC cycles */ + ADC_ADCPGASAMPDUR_15CLK_gc = (0x01<<1), /* 15 ADC cycles */ + ADC_ADCPGASAMPDUR_20CLK_gc = (0x02<<1), /* 20 ADC cycles */ + ADC_ADCPGASAMPDUR_32CLK_gc = (0x03<<1), /* 32 ADC cycles */ +} ADC_ADCPGASAMPDUR_t; + +/* Gain select */ +typedef enum ADC_GAIN_enum +{ + ADC_GAIN_1X_gc = (0x00<<5), /* 1X Gain */ + ADC_GAIN_2X_gc = (0x01<<5), /* 2X Gain */ + ADC_GAIN_4X_gc = (0x02<<5), /* 4X Gain */ + ADC_GAIN_8X_gc = (0x03<<5), /* 8X Gain */ + ADC_GAIN_16X_gc = (0x04<<5), /* 16X Gain */ +} ADC_GAIN_t; + +/* Mode select */ +typedef enum ADC_MODE_enum +{ + ADC_MODE_SINGLE_8BIT_gc = (0x00<<4), /* Single Conversion 8-bit */ + ADC_MODE_SINGLE_12BIT_gc = (0x01<<4), /* Single Conversion 12-bit */ + ADC_MODE_SERIES_gc = (0x02<<4), /* Series Accumulation */ + ADC_MODE_SERIES_SCALING_gc = (0x03<<4), /* Series Accumulation with Scaling */ + ADC_MODE_BURST_gc = (0x04<<4), /* Burst Accumulation */ + ADC_MODE_BURST_SCALING_gc = (0x05<<4), /* Burst Accumulation with Scaling */ +} ADC_MODE_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXNEG_enum +{ + ADC_MUXNEG_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXNEG_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXNEG_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXNEG_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXNEG_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXNEG_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXNEG_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXNEG_GND_gc = (0x30<<0), /* Ground */ + ADC_MUXNEG_VDDDIV10_gc = (0x31<<0), /* VDD/10 */ + ADC_MUXNEG_DAC_gc = (0x33<<0), /* DAC */ +} ADC_MUXNEG_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ + ADC_MUXPOS_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ + ADC_MUXPOS_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ + ADC_MUXPOS_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ + ADC_MUXPOS_GND_gc = (0x30<<0), /* Ground */ + ADC_MUXPOS_VDDDIV10_gc = (0x31<<0), /* VDD/10 */ + ADC_MUXPOS_TEMPSENSE_gc = (0x32<<0), /* Temperature sensor */ + ADC_MUXPOS_DAC_gc = (0x33<<0), /* DAC */ +} ADC_MUXPOS_t; + +/* PGA BIAS Select select */ +typedef enum ADC_PGABIASSEL_enum +{ + ADC_PGABIASSEL_1X_gc = (0x00<<3), /* 1x BIAS curren */ + ADC_PGABIASSEL_3_4X_gc = (0x01<<3), /* 3/4x BIAS current */ + ADC_PGABIASSEL_1_2X_gc = (0x02<<3), /* 1/2x BIAS current */ + ADC_PGABIASSEL_1_4X_gc = (0x03<<3), /* 1/4x BIAS current */ +} ADC_PGABIASSEL_t; + +/* Prescaler Value select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* System clock divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* System clock divided by 4 */ + ADC_PRESC_DIV6_gc = (0x02<<0), /* System clock divided by 6 */ + ADC_PRESC_DIV8_gc = (0x03<<0), /* System clock divided by 8 */ + ADC_PRESC_DIV10_gc = (0x04<<0), /* System clock divided by 10 */ + ADC_PRESC_DIV12_gc = (0x05<<0), /* System clock divided by 12 */ + ADC_PRESC_DIV14_gc = (0x06<<0), /* System clock divided by 14 */ + ADC_PRESC_DIV16_gc = (0x07<<0), /* System clock divided by 16 */ + ADC_PRESC_DIV20_gc = (0x08<<0), /* System clock divided by 20 */ + ADC_PRESC_DIV24_gc = (0x09<<0), /* System clock divided by 24 */ + ADC_PRESC_DIV28_gc = (0x0A<<0), /* System clock divided by 28 */ + ADC_PRESC_DIV32_gc = (0x0B<<0), /* System clock divided by 32 */ + ADC_PRESC_DIV40_gc = (0x0C<<0), /* System clock divided by 40 */ + ADC_PRESC_DIV48_gc = (0x0D<<0), /* System clock divided by 48 */ + ADC_PRESC_DIV56_gc = (0x0E<<0), /* System clock divided by 56 */ + ADC_PRESC_DIV64_gc = (0x0F<<0), /* System clock divided by 64 */ +} ADC_PRESC_t; + +/* Reference select select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_VDD_gc = (0x00<<0), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<0), /* External Reference */ + ADC_REFSEL_1024MV_gc = (0x04<<0), /* Internal 1.024V Reference */ + ADC_REFSEL_2048MV_gc = (0x05<<0), /* Internal 2.048V Reference */ + ADC_REFSEL_2500MV_gc = (0x06<<0), /* Internal 2.5V Reference */ + ADC_REFSEL_4096MV_gc = (0x07<<0), /* Internal 4.096V Reference */ +} ADC_REFSEL_t; + +/* Sample numbers select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_NONE_gc = (0x00<<0), /* No accumulation */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* 2 samples accumulation */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* 4 samples accumulation */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* 8 samples accumulation */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* 16 samples accumulation */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* 32 samples accumulation */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* 64 samples accumulation */ + ADC_SAMPNUM_ACC128_gc = (0x07<<0), /* 128 samples accumulation */ + ADC_SAMPNUM_ACC256_gc = (0x08<<0), /* 256 samples accumulation */ + ADC_SAMPNUM_ACC512_gc = (0x09<<0), /* 512 samples accumulation */ + ADC_SAMPNUM_ACC1024_gc = (0x0A<<0), /* 1024 samples accumulation */ +} ADC_SAMPNUM_t; + +/* Start command select */ +typedef enum ADC_START_enum +{ + ADC_START_STOP_gc = (0x00<<0), /* Stop an ongoing conversion */ + ADC_START_IMMEDIATE_gc = (0x01<<0), /* Start immediately */ + ADC_START_MUXPOS_WRITE_gc = (0x02<<0), /* Start on MUXPOS write */ + ADC_START_MUXNEG_WRITE_gc = (0x03<<0), /* Start on MUXNEG write */ + ADC_START_EVENT_TRIGGER_gc = (0x04<<0), /* Start on event */ +} ADC_START_t; + +/* VIA select */ +typedef enum ADC_VIA_enum +{ + ADC_VIA_ADC_gc = (0x00<<6), /* Via ADC */ + ADC_VIA_PGA_gc = (0x01<<6), /* Via PGA */ +} ADC_VIA_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* Window Mode Source select */ +typedef enum ADC_WINSRC_enum +{ + ADC_WINSRC_RESULT_gc = (0x00<<3), /* Result register */ + ADC_WINSRC_SAMPLE_gc = (0x01<<3), /* Sample register */ +} ADC_WINSRC_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t SEQCTRL1; /* Sequential Control 1 */ + register8_t reserved_1[2]; + register8_t INTCTRL0; /* Interrupt Control 0 */ + register8_t reserved_2[1]; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t LUT2CTRLA; /* LUT Control 2 A */ + register8_t LUT2CTRLB; /* LUT Control 2 B */ + register8_t LUT2CTRLC; /* LUT Control 2 C */ + register8_t TRUTH2; /* Truth 2 */ + register8_t LUT3CTRLA; /* LUT Control 3 A */ + register8_t LUT3CTRLB; /* LUT Control 3 B */ + register8_t LUT3CTRLC; /* LUT Control 3 C */ + register8_t TRUTH3; /* Truth 3 */ + register8_t reserved_3[40]; +} CCL_t; + +/* Clock Source Selection select */ +typedef enum CCL_CLKSRC_enum +{ + CCL_CLKSRC_CLKPER_gc = (0x00<<1), /* CLK_PER is clocking the LUT */ + CCL_CLKSRC_IN2_gc = (0x01<<1), /* IN[2] is clocking the LUT */ + CCL_CLKSRC_OSC20M_gc = (0x04<<1), /* 20MHz oscillator before prescaler is clocking the LUT */ + CCL_CLKSRC_OSCULP32K_gc = (0x05<<1), /* 32kHz oscillator is clocking the LUT */ + CCL_CLKSRC_OSCULP1K_gc = (0x06<<1), /* 32kHz oscillator after DIV32 is clocking the LUT */ +} CCL_CLKSRC_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL0_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_USART0_gc = (0x08<<0), /* USART0 TXD input source */ + CCL_INSEL0_SPI0_gc = (0x09<<0), /* SPI0 MOSI input source */ + CCL_INSEL0_TCA0_gc = (0x0A<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCB0_gc = (0x0C<<0), /* TCB0 WO input source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENTA_gc = (0x03<<4), /* Event input source A */ + CCL_INSEL1_EVENTB_gc = (0x04<<4), /* Event input source B */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_USART1_gc = (0x08<<4), /* USART1 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x09<<4), /* SPI0 MOSI input source */ + CCL_INSEL1_TCA0_gc = (0x0A<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCB1_gc = (0x0C<<4), /* TCB1 WO input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENTA_gc = (0x03<<0), /* Event input source A */ + CCL_INSEL2_EVENTB_gc = (0x04<<0), /* Event input source B */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_SPI0_gc = (0x09<<0), /* SPI0 SCK input source */ + CCL_INSEL2_TCA0_gc = (0x0A<<0), /* TCA0 WO2 input source */ +} CCL_INSEL2_t; + +/* Interrupt Mode for LUT0 select */ +typedef enum CCL_INTMODE0_enum +{ + CCL_INTMODE0_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled */ + CCL_INTMODE0_RISING_gc = (0x01<<0), /* Sense rising edge */ + CCL_INTMODE0_FALLING_gc = (0x02<<0), /* Sense falling edge */ + CCL_INTMODE0_BOTH_gc = (0x03<<0), /* Sense both edges */ +} CCL_INTMODE0_t; + +/* Interrupt Mode for LUT1 select */ +typedef enum CCL_INTMODE1_enum +{ + CCL_INTMODE1_INTDISABLE_gc = (0x00<<2), /* Interrupt disabled */ + CCL_INTMODE1_RISING_gc = (0x01<<2), /* Sense rising edge */ + CCL_INTMODE1_FALLING_gc = (0x02<<2), /* Sense falling edge */ + CCL_INTMODE1_BOTH_gc = (0x03<<2), /* Sense both edges */ +} CCL_INTMODE1_t; + +/* Interrupt Mode for LUT2 select */ +typedef enum CCL_INTMODE2_enum +{ + CCL_INTMODE2_INTDISABLE_gc = (0x00<<4), /* Interrupt disabled */ + CCL_INTMODE2_RISING_gc = (0x01<<4), /* Sense rising edge */ + CCL_INTMODE2_FALLING_gc = (0x02<<4), /* Sense falling edge */ + CCL_INTMODE2_BOTH_gc = (0x03<<4), /* Sense both edges */ +} CCL_INTMODE2_t; + +/* Interrupt Mode for LUT3 select */ +typedef enum CCL_INTMODE3_enum +{ + CCL_INTMODE3_INTDISABLE_gc = (0x00<<6), /* Interrupt disabled */ + CCL_INTMODE3_RISING_gc = (0x01<<6), /* Sense rising edge */ + CCL_INTMODE3_FALLING_gc = (0x02<<6), /* Sense falling edge */ + CCL_INTMODE3_BOTH_gc = (0x03<<6), /* Sense both edges */ +} CCL_INTMODE3_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL0_enum +{ + CCL_SEQSEL0_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL0_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL0_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL0_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL0_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL0_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL1_enum +{ + CCL_SEQSEL1_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL1_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL1_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL1_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL1_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL1_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1k cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16k cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32k cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t SWEVENTA; /* Software Event A */ + register8_t reserved_1[15]; + register8_t CHANNEL0; /* Multiplexer Channel 0 */ + register8_t CHANNEL1; /* Multiplexer Channel 1 */ + register8_t CHANNEL2; /* Multiplexer Channel 2 */ + register8_t CHANNEL3; /* Multiplexer Channel 3 */ + register8_t CHANNEL4; /* Multiplexer Channel 4 */ + register8_t CHANNEL5; /* Multiplexer Channel 5 */ + register8_t reserved_2[10]; + register8_t USERCCLLUT0A; /* User CCL LUT0 Event A */ + register8_t USERCCLLUT0B; /* User CCL LUT0 Event B */ + register8_t USERCCLLUT1A; /* User CCL LUT1 Event A */ + register8_t USERCCLLUT1B; /* User CCL LUT1 Event B */ + register8_t USERCCLLUT2A; /* User CCL LUT2 Event A */ + register8_t USERCCLLUT2B; /* User CCL LUT2 Event B */ + register8_t USERCCLLUT3A; /* User CCL LUT3 Event A */ + register8_t USERCCLLUT3B; /* User CCL LUT3 Event B */ + register8_t USERADC0START; /* User ADC0 */ + register8_t USEREVSYSEVOUTA; /* User EVOUT Port A */ + register8_t USEREVSYSEVOUTB; /* User EVOUT Port B */ + register8_t USEREVSYSEVOUTC; /* User EVOUT Port C */ + register8_t USERUSART0IRDA; /* User USART0 */ + register8_t USERUSART1IRDA; /* User USART1 */ + register8_t USERTCA0CNTA; /* User TCA0 count event */ + register8_t USERTCA0CNTB; /* User TCA0 Restart event */ + register8_t USERTCB0CAPT; /* User TCB0 Event in A */ + register8_t USERTCB0COUNT; /* User TCB0 Event in B */ + register8_t USERTCB1CAPT; /* User TCB1 Event in A */ + register8_t USERTCB1COUNT; /* User TCB1 Event in B */ + register8_t reserved_3[12]; +} EVSYS_t; + +/* Channel 0 generator select select */ +typedef enum EVSYS_CHANNEL0_enum +{ + EVSYS_CHANNEL0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL0_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_CHANNEL0_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL0_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL0_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL0_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL0_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL0_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL0_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL0_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL0_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL0_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL0_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL0_ADC0_RES_gc = (0x24<<0), /* ADC 0 Result ready event */ + EVSYS_CHANNEL0_ADC0_SAMP_gc = (0x25<<0), /* ADC 0 Sample ready event */ + EVSYS_CHANNEL0_ADC0_WCMP_gc = (0x26<<0), /* ADC 0 Window compare match event */ + EVSYS_CHANNEL0_PORTA_PIN0_gc = (0x40<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL0_PORTA_PIN1_gc = (0x41<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL0_PORTA_PIN2_gc = (0x42<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL0_PORTA_PIN3_gc = (0x43<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL0_PORTA_PIN4_gc = (0x44<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL0_PORTA_PIN5_gc = (0x45<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL0_PORTA_PIN6_gc = (0x46<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL0_PORTA_PIN7_gc = (0x47<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL0_PORTB_PIN0_gc = (0x48<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL0_PORTB_PIN1_gc = (0x49<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL0_PORTB_PIN2_gc = (0x4A<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL0_PORTB_PIN3_gc = (0x4B<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL0_PORTB_PIN4_gc = (0x4C<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL0_PORTB_PIN5_gc = (0x4D<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL0_PORTB_PIN6_gc = (0x4E<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL0_PORTB_PIN7_gc = (0x4F<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL0_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL0_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL0_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_CHANNEL0_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_CHANNEL0_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow */ + EVSYS_CHANNEL0_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL0_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL0_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL0_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL0_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL0_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL0_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ +} EVSYS_CHANNEL0_t; + +/* Channel 1 generator select select */ +typedef enum EVSYS_CHANNEL1_enum +{ + EVSYS_CHANNEL1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL1_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_CHANNEL1_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL1_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL1_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL1_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL1_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL1_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL1_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL1_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL1_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL1_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL1_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL1_ADC0_RES_gc = (0x24<<0), /* ADC 0 Result ready event */ + EVSYS_CHANNEL1_ADC0_SAMP_gc = (0x25<<0), /* ADC 0 Sample ready event */ + EVSYS_CHANNEL1_ADC0_WCMP_gc = (0x26<<0), /* ADC 0 Window compare match event */ + EVSYS_CHANNEL1_PORTA_PIN0_gc = (0x40<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL1_PORTA_PIN1_gc = (0x41<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL1_PORTA_PIN2_gc = (0x42<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL1_PORTA_PIN3_gc = (0x43<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL1_PORTA_PIN4_gc = (0x44<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL1_PORTA_PIN5_gc = (0x45<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL1_PORTA_PIN6_gc = (0x46<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL1_PORTA_PIN7_gc = (0x47<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL1_PORTB_PIN0_gc = (0x48<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL1_PORTB_PIN1_gc = (0x49<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL1_PORTB_PIN2_gc = (0x4A<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL1_PORTB_PIN3_gc = (0x4B<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL1_PORTB_PIN4_gc = (0x4C<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL1_PORTB_PIN5_gc = (0x4D<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL1_PORTB_PIN6_gc = (0x4E<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL1_PORTB_PIN7_gc = (0x4F<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL1_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL1_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL1_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_CHANNEL1_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_CHANNEL1_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow */ + EVSYS_CHANNEL1_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL1_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL1_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL1_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL1_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL1_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL1_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ +} EVSYS_CHANNEL1_t; + +/* Channel 2 generator select select */ +typedef enum EVSYS_CHANNEL2_enum +{ + EVSYS_CHANNEL2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL2_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_CHANNEL2_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL2_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL2_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL2_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL2_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL2_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL2_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL2_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL2_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL2_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL2_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL2_ADC0_RES_gc = (0x24<<0), /* ADC 0 Result ready event */ + EVSYS_CHANNEL2_ADC0_SAMP_gc = (0x25<<0), /* ADC 0 Sample ready event */ + EVSYS_CHANNEL2_ADC0_WCMP_gc = (0x26<<0), /* ADC 0 Window compare match event */ + EVSYS_CHANNEL2_PORTC_PIN0_gc = (0x40<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL2_PORTC_PIN1_gc = (0x41<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL2_PORTC_PIN2_gc = (0x42<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL2_PORTC_PIN3_gc = (0x43<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL2_PORTC_PIN4_gc = (0x44<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL2_PORTC_PIN5_gc = (0x45<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL2_PORTC_PIN6_gc = (0x46<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL2_PORTC_PIN7_gc = (0x47<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL2_PORTA_PIN0_gc = (0x48<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL2_PORTA_PIN1_gc = (0x49<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL2_PORTA_PIN2_gc = (0x4A<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL2_PORTA_PIN3_gc = (0x4B<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL2_PORTA_PIN4_gc = (0x4C<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL2_PORTA_PIN5_gc = (0x4D<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL2_PORTA_PIN6_gc = (0x4E<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL2_PORTA_PIN7_gc = (0x4F<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL2_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL2_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL2_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_CHANNEL2_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_CHANNEL2_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow */ + EVSYS_CHANNEL2_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL2_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL2_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL2_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL2_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL2_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL2_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ +} EVSYS_CHANNEL2_t; + +/* Channel 3 generator select select */ +typedef enum EVSYS_CHANNEL3_enum +{ + EVSYS_CHANNEL3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL3_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_CHANNEL3_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL3_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL3_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL3_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL3_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL3_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL3_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL3_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL3_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL3_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL3_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL3_ADC0_RES_gc = (0x24<<0), /* ADC 0 Result ready event */ + EVSYS_CHANNEL3_ADC0_SAMP_gc = (0x25<<0), /* ADC 0 Sample ready event */ + EVSYS_CHANNEL3_ADC0_WCMP_gc = (0x26<<0), /* ADC 0 Window compare match event */ + EVSYS_CHANNEL3_PORTC_PIN0_gc = (0x40<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL3_PORTC_PIN1_gc = (0x41<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL3_PORTC_PIN2_gc = (0x42<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL3_PORTC_PIN3_gc = (0x43<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL3_PORTC_PIN4_gc = (0x44<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL3_PORTC_PIN5_gc = (0x45<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL3_PORTC_PIN6_gc = (0x46<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL3_PORTC_PIN7_gc = (0x47<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL3_PORTA_PIN0_gc = (0x48<<0), /* Port A Pin 0 */ + EVSYS_CHANNEL3_PORTA_PIN1_gc = (0x49<<0), /* Port A Pin 1 */ + EVSYS_CHANNEL3_PORTA_PIN2_gc = (0x4A<<0), /* Port A Pin 2 */ + EVSYS_CHANNEL3_PORTA_PIN3_gc = (0x4B<<0), /* Port A Pin 3 */ + EVSYS_CHANNEL3_PORTA_PIN4_gc = (0x4C<<0), /* Port A Pin 4 */ + EVSYS_CHANNEL3_PORTA_PIN5_gc = (0x4D<<0), /* Port A Pin 5 */ + EVSYS_CHANNEL3_PORTA_PIN6_gc = (0x4E<<0), /* Port A Pin 6 */ + EVSYS_CHANNEL3_PORTA_PIN7_gc = (0x4F<<0), /* Port A Pin 7 */ + EVSYS_CHANNEL3_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL3_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL3_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_CHANNEL3_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_CHANNEL3_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow */ + EVSYS_CHANNEL3_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL3_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL3_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL3_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL3_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL3_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL3_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ +} EVSYS_CHANNEL3_t; + +/* Channel 4 generator select select */ +typedef enum EVSYS_CHANNEL4_enum +{ + EVSYS_CHANNEL4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL4_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_CHANNEL4_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL4_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL4_RTC_PIT_DIV8192_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL4_RTC_PIT_DIV4096_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL4_RTC_PIT_DIV2048_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL4_RTC_PIT_DIV1024_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL4_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL4_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL4_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL4_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL4_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL4_ADC0_RES_gc = (0x24<<0), /* ADC 0 Result ready event */ + EVSYS_CHANNEL4_ADC0_SAMP_gc = (0x25<<0), /* ADC 0 Sample ready event */ + EVSYS_CHANNEL4_ADC0_WCMP_gc = (0x26<<0), /* ADC 0 Window compare match event */ + EVSYS_CHANNEL4_PORTB_PIN0_gc = (0x40<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL4_PORTB_PIN1_gc = (0x41<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL4_PORTB_PIN2_gc = (0x42<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL4_PORTB_PIN3_gc = (0x43<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL4_PORTB_PIN4_gc = (0x44<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL4_PORTB_PIN5_gc = (0x45<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL4_PORTB_PIN6_gc = (0x46<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL4_PORTB_PIN7_gc = (0x47<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL4_PORTC_PIN0_gc = (0x48<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL4_PORTC_PIN1_gc = (0x49<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL4_PORTC_PIN2_gc = (0x4A<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL4_PORTC_PIN3_gc = (0x4B<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL4_PORTC_PIN4_gc = (0x4C<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL4_PORTC_PIN5_gc = (0x4D<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL4_PORTC_PIN6_gc = (0x4E<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL4_PORTC_PIN7_gc = (0x4F<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL4_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL4_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL4_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_CHANNEL4_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_CHANNEL4_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow */ + EVSYS_CHANNEL4_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL4_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL4_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL4_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL4_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL4_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL4_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ +} EVSYS_CHANNEL4_t; + +/* Channel 5 generator select select */ +typedef enum EVSYS_CHANNEL5_enum +{ + EVSYS_CHANNEL5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHANNEL5_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ + EVSYS_CHANNEL5_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ + EVSYS_CHANNEL5_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ + EVSYS_CHANNEL5_RTC_PIT_DIV512_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ + EVSYS_CHANNEL5_RTC_PIT_DIV256_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ + EVSYS_CHANNEL5_RTC_PIT_DIV128_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ + EVSYS_CHANNEL5_RTC_PIT_DIV64_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ + EVSYS_CHANNEL5_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_CHANNEL5_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_CHANNEL5_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ + EVSYS_CHANNEL5_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ + EVSYS_CHANNEL5_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ + EVSYS_CHANNEL5_ADC0_RES_gc = (0x24<<0), /* ADC 0 Result ready event */ + EVSYS_CHANNEL5_ADC0_SAMP_gc = (0x25<<0), /* ADC 0 Sample ready event */ + EVSYS_CHANNEL5_ADC0_WCMP_gc = (0x26<<0), /* ADC 0 Window compare match event */ + EVSYS_CHANNEL5_PORTB_PIN0_gc = (0x40<<0), /* Port B Pin 0 */ + EVSYS_CHANNEL5_PORTB_PIN1_gc = (0x41<<0), /* Port B Pin 1 */ + EVSYS_CHANNEL5_PORTB_PIN2_gc = (0x42<<0), /* Port B Pin 2 */ + EVSYS_CHANNEL5_PORTB_PIN3_gc = (0x43<<0), /* Port B Pin 3 */ + EVSYS_CHANNEL5_PORTB_PIN4_gc = (0x44<<0), /* Port B Pin 4 */ + EVSYS_CHANNEL5_PORTB_PIN5_gc = (0x45<<0), /* Port B Pin 5 */ + EVSYS_CHANNEL5_PORTB_PIN6_gc = (0x46<<0), /* Port B Pin 6 */ + EVSYS_CHANNEL5_PORTB_PIN7_gc = (0x47<<0), /* Port B Pin 7 */ + EVSYS_CHANNEL5_PORTC_PIN0_gc = (0x48<<0), /* Port C Pin 0 */ + EVSYS_CHANNEL5_PORTC_PIN1_gc = (0x49<<0), /* Port C Pin 1 */ + EVSYS_CHANNEL5_PORTC_PIN2_gc = (0x4A<<0), /* Port C Pin 2 */ + EVSYS_CHANNEL5_PORTC_PIN3_gc = (0x4B<<0), /* Port C Pin 3 */ + EVSYS_CHANNEL5_PORTC_PIN4_gc = (0x4C<<0), /* Port C Pin 4 */ + EVSYS_CHANNEL5_PORTC_PIN5_gc = (0x4D<<0), /* Port C Pin 5 */ + EVSYS_CHANNEL5_PORTC_PIN6_gc = (0x4E<<0), /* Port C Pin 6 */ + EVSYS_CHANNEL5_PORTC_PIN7_gc = (0x4F<<0), /* Port C Pin 7 */ + EVSYS_CHANNEL5_USART0_XCK_gc = (0x60<<0), /* USART 0 XCK */ + EVSYS_CHANNEL5_USART1_XCK_gc = (0x61<<0), /* USART 1 XCK */ + EVSYS_CHANNEL5_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ + EVSYS_CHANNEL5_TCA0_OVF_LUNF_gc = (0x80<<0), /* Timer/Counter A0 overflow / low byte underflow */ + EVSYS_CHANNEL5_TCA0_HUNF_gc = (0x81<<0), /* Timer/Counter A0 high byte underflow */ + EVSYS_CHANNEL5_TCA0_CMP0_LCMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 / low byte timer compare 0 */ + EVSYS_CHANNEL5_TCA0_CMP1_LCMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 / low byte timer compare 1 */ + EVSYS_CHANNEL5_TCA0_CMP2_LCMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 / low byte timer compare 2 */ + EVSYS_CHANNEL5_TCB0_CAPT_gc = (0xA0<<0), /* Timer/Counter B0 capture */ + EVSYS_CHANNEL5_TCB0_OVF_gc = (0xA1<<0), /* Timer/Counter B0 overflow */ + EVSYS_CHANNEL5_TCB1_CAPT_gc = (0xA2<<0), /* Timer/Counter B1 capture */ + EVSYS_CHANNEL5_TCB1_OVF_gc = (0xA3<<0), /* Timer/Counter B1 overflow */ +} EVSYS_CHANNEL5_t; + +/* Software event on channel select */ +typedef enum EVSYS_SWEVENTA_enum +{ + EVSYS_SWEVENTA_CH0_gc = (0x01<<0), /* Software event on channel 0 */ + EVSYS_SWEVENTA_CH1_gc = (0x02<<0), /* Software event on channel 1 */ + EVSYS_SWEVENTA_CH2_gc = (0x04<<0), /* Software event on channel 2 */ + EVSYS_SWEVENTA_CH3_gc = (0x08<<0), /* Software event on channel 3 */ + EVSYS_SWEVENTA_CH4_gc = (0x10<<0), /* Software event on channel 4 */ + EVSYS_SWEVENTA_CH5_gc = (0x20<<0), /* Software event on channel 5 */ +} EVSYS_SWEVENTA_t; + +/* Channel selector select */ +typedef enum EVSYS_USER_enum +{ + EVSYS_USER_OFF_gc = (0x00<<0), /* Off */ + EVSYS_USER_CHANNEL0_gc = (0x01<<0), /* Connect user to event channel 0 */ + EVSYS_USER_CHANNEL1_gc = (0x02<<0), /* Connect user to event channel 1 */ + EVSYS_USER_CHANNEL2_gc = (0x03<<0), /* Connect user to event channel 2 */ + EVSYS_USER_CHANNEL3_gc = (0x04<<0), /* Connect user to event channel 3 */ + EVSYS_USER_CHANNEL4_gc = (0x05<<0), /* Connect user to event channel 4 */ + EVSYS_USER_CHANNEL5_gc = (0x06<<0), /* Connect user to event channel 5 */ +} EVSYS_USER_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ + RSTPINCFG_PDIRST_gc = (0x03<<2), /* PDI on PDI pad, reset on alternative reset pad */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock Bits */ + register8_t reserved_1[1]; +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMBIST - BIST in the NVMCTRL module +-------------------------------------------------------------------------- +*/ + +/* BIST in the NVMCTRL module */ +typedef struct NVMBIST_struct +{ + register8_t CTRLA; /* Control A */ + register8_t ADDRPAT; /* Address pattern */ + register8_t DATAPAT; /* Data pattern */ + register8_t STATUS; /* Status */ + _WORDREGISTER(CNT); /* */ + _DWORDREGISTER(END); /* */ + register8_t reserved_1[6]; +} NVMBIST_t; + +/* Address mode select */ +typedef enum NVMBIST_AMODE_enum +{ + NVMBIST_AMODE_NORMAL_gc = (0x00<<4), /* No special address pattern */ + NVMBIST_AMODE_COMPLEMENT_gc = (0x04<<4), /* Post complement address */ +} NVMBIST_AMODE_t; + +/* Command select */ +typedef enum NVMBIST_CMD_enum +{ + NVMBIST_CMD_NOCMD_gc = (0x00<<0), /* No effect */ + NVMBIST_CMD_START_gc = (0x01<<0), /* Start BIST testing */ + NVMBIST_CMD_RESTART_gc = (0x02<<0), /* Re-start BIST testing */ + NVMBIST_CMD_BREAK_gc = (0x03<<0), /* Stop BIST and go to BREAK state */ +} NVMBIST_CMD_t; + +/* Data check pattern select */ +typedef enum NVMBIST_PATTERN_enum +{ + NVMBIST_PATTERN_ZEROES_gc = (0x00<<0), /* All flash programmed */ + NVMBIST_PATTERN_CHECK_gc = (0x01<<0), /* Physical checkerboard in flash */ + NVMBIST_PATTERN_INVCHECK_gc = (0x02<<0), /* Inverse physical checkerboard in flash */ + NVMBIST_PATTERN_ONES_gc = (0x03<<0), /* All flash unprogrammed */ +} NVMBIST_PATTERN_t; + +/* FSM State select */ +typedef enum NVMBIST_STATE_enum +{ + NVMBIST_STATE_IDLE_gc = (0x00<<0), /* Reset state */ + NVMBIST_STATE_BREAK_gc = (0x01<<0), /* Break command used */ + NVMBIST_STATE_FAILED0_gc = (0x04<<0), /* Test failed, data from last address */ + NVMBIST_STATE_FAILED1_gc = (0x05<<0), /* Test failed, data from address-1 */ + NVMBIST_STATE_FAILED2_gc = (0x06<<0), /* Test failed, data from address-2 */ + NVMBIST_STATE_SUCCESS_gc = (0x07<<0), /* Test success */ + NVMBIST_STATE_START0_gc = (0x08<<0), /* Startup, fetching first data */ + NVMBIST_STATE_START1_gc = (0x09<<0), /* Startup, fetching second data */ + NVMBIST_STATE_RESTART0_gc = (0x0A<<0), /* Re-start from BREAK or FAILED2 */ + NVMBIST_STATE_RESTART1_gc = (0x0B<<0), /* Re-start from FAILED1 */ + NVMBIST_STATE_RUNNING_gc = (0x0C<<0), /* Test running */ + NVMBIST_STATE_FINISH0_gc = (0x0E<<0), /* Check last word */ + NVMBIST_STATE_FINISH1_gc = (0x0F<<0), /* Count faults in last word */ +} NVMBIST_STATE_t; + +/* X address mode select */ +typedef enum NVMBIST_XMODE_enum +{ + NVMBIST_XMODE_STATIC_gc = (0x00<<0), /* X static */ + NVMBIST_XMODE_CARRY_gc = (0x01<<0), /* Carry/borrow from Y */ + NVMBIST_XMODE_INC_gc = (0x02<<0), /* X increment each cycle */ + NVMBIST_XMODE_DEC_gc = (0x03<<0), /* X decrement each cycle */ +} NVMBIST_XMODE_t; + +/* Y address mode select */ +typedef enum NVMBIST_YMODE_enum +{ + NVMBIST_YMODE_STATIC_gc = (0x00<<2), /* Y static */ + NVMBIST_YMODE_CARRY_gc = (0x01<<2), /* Carry/borrow from X */ + NVMBIST_YMODE_INC_gc = (0x02<<2), /* Y increment each cycle */ + NVMBIST_YMODE_DEC_gc = (0x03<<2), /* Y decrement each cycle */ +} NVMBIST_YMODE_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t PORTCTRL; /* Port Control */ + register8_t reserved_1[5]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t EVSYSROUTEA; /* Port Multiplexer EVSYS */ + register8_t CCLROUTEA; /* Port Multiplexer CCL */ + register8_t USARTROUTEA; /* Port Multiplexer USART register A */ + register8_t SPIROUTEA; /* Port Multiplexer TWI and SPI */ + register8_t TCAROUTEA; /* Port Multiplexer TCA */ + register8_t TCBROUTEA; /* Port Multiplexer TCB */ + register8_t reserved_1[10]; +} PORTMUX_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<0), /* SPI0 on PA[7:4] */ + PORTMUX_SPI0_ALT1_gc = (0x01<<0), /* SPI0 on PC[3:0] */ + PORTMUX_SPI0_ALT2_gc = (0x02<<0), /* SPI0 on PE[3:0] */ + PORTMUX_SPI0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 select */ +typedef enum PORTMUX_TCA0_enum +{ + PORTMUX_TCA0_PORTA_gc = (0x00<<0), /* TCA0 pins on PA[5:0] */ + PORTMUX_TCA0_PORTB_gc = (0x01<<0), /* TCA0 pins on PB[5:0] */ + PORTMUX_TCA0_PORTC_gc = (0x02<<0), /* TCA0 pins on PC[5:0] */ + PORTMUX_TCA0_PORTD_gc = (0x03<<0), /* TCA0 pins on PD[5:0] */ + PORTMUX_TCA0_PORTE_gc = (0x04<<0), /* TCA0 pins on PE[5:0] */ + PORTMUX_TCA0_PORTF_gc = (0x05<<0), /* TCA0 pins on PF[5:0] */ +} PORTMUX_TCA0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* SCL/SDA on PA[3:2], Slave mode on PC[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT1_gc = (0x01<<4), /* SCL/SDA on PA[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_ALT2_gc = (0x02<<4), /* SCL/SDA on PC[3:2], Slave mode on PF[3:2] in dual TWI mode */ + PORTMUX_TWI0_NONE_gc = (0x03<<4), /* Not connected to any pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* USART0 on PA[3:0] */ + PORTMUX_USART0_ALT1_gc = (0x01<<0), /* USART0 on PA[7:4] */ + PORTMUX_USART0_NONE_gc = (0x03<<0), /* Not connected to any pins */ +} PORTMUX_USART0_t; + +/* Port Multiplexer USART1 select */ +typedef enum PORTMUX_USART1_enum +{ + PORTMUX_USART1_DEFAULT_gc = (0x00<<2), /* USART1 on PC[3:0] */ + PORTMUX_USART1_ALT1_gc = (0x01<<2), /* USART1 on PC[7:4] */ + PORTMUX_USART1_NONE_gc = (0x03<<2), /* Not connected to any pins */ +} PORTMUX_USART1_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t CALIB; /* Calibration */ + register8_t CLKSEL; /* RTC Clock */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_1[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_2[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_3[10]; +} RTC_t; + +/* Clock select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[7]; + register8_t OSCCAL32K; /* Oscillator Calibration for 32kHz ULP */ + register8_t reserved_2[3]; + register8_t OSCCAL16M0; /* Oscillator Calibration 16 MHz Byte 0 */ + register8_t OSCCAL16M1; /* Oscillator Calibration 16 MHz Byte 1 */ + register8_t OSCCAL20M0; /* Oscillator Calibration 20 MHz Byte 0 */ + register8_t OSCCAL20M1; /* Oscillator Calibration 20 MHz Byte 1 */ + register8_t reserved_3[4]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_4[9]; + register8_t CHECKSUM1; /* CRC Checksum Byte 1 */ + register8_t reserved_5[16]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[21]; + register8_t OCDM; /* OCD Message Register */ + register8_t OCDMS; /* OCD Message Status */ + register8_t reserved_3[6]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action A select */ +typedef enum TCA_SINGLE_EVACTA_enum +{ + TCA_SINGLE_EVACTA_CNT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACTA_CNT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACTA_CNT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACTA_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACTA_t; + +/* Event Action B select */ +typedef enum TCA_SINGLE_EVACTB_enum +{ + TCA_SINGLE_EVACTB_UPDOWN_gc = (0x03<<5), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ + TCA_SINGLE_EVACTB_RESTART_POSEDGE_gc = (0x04<<5), /* Restart counter at positive edge event */ + TCA_SINGLE_EVACTB_RESTART_ANYEDGE_gc = (0x05<<5), /* Restart counter on any edge event */ + TCA_SINGLE_EVACTB_RESTART_HIGHLVL_gc = (0x06<<5), /* Restart counter while event line is 1. */ +} TCA_SINGLE_EVACTB_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* Command Enable select */ +typedef enum TCA_SPLIT_CMDEN_enum +{ + TCA_SPLIT_CMDEN_NONE_gc = (0x00<<0), /* None */ + TCA_SPLIT_CMDEN_BOTH_gc = (0x03<<0), /* Both low byte and high byte */ +} TCA_SPLIT_CMDEN_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* TCB Clock select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_DIV1_gc = (0x00<<1), /* CLK_PEP */ + TCB_CLKSEL_DIV2_gc = (0x01<<1), /* CLK_PER/2 */ + TCB_CLKSEL_TCA0_gc = (0x02<<1), /* Use CLK_TCA from TCA0 */ + TCB_CLKSEL_EVENT_gc = (0x07<<1), /* Count on event edge */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baud Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t CTRLD; /* Control D */ + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_1[1]; +} USART_t; + +/* Auto Baud Window select */ +typedef enum USART_ABW_enum +{ + USART_ABW_WDW0_gc = (0x00<<6), /* 18% tolerance */ + USART_ABW_WDW1_gc = (0x01<<6), /* 15% tolerance */ + USART_ABW_WDW2_gc = (0x02<<6), /* 21% tolerance */ + USART_ABW_WDW3_gc = (0x03<<6), /* 25% tolerance */ +} USART_ABW_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_DISABLE_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_ENABLE_gc = (0x01<<0), /* RS485 Mode enabled */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ + register8_t USERROW32; /* User Row Byte 32 */ + register8_t USERROW33; /* User Row Byte 33 */ + register8_t USERROW34; /* User Row Byte 34 */ + register8_t USERROW35; /* User Row Byte 35 */ + register8_t USERROW36; /* User Row Byte 36 */ + register8_t USERROW37; /* User Row Byte 37 */ + register8_t USERROW38; /* User Row Byte 38 */ + register8_t USERROW39; /* User Row Byte 39 */ + register8_t USERROW40; /* User Row Byte 40 */ + register8_t USERROW41; /* User Row Byte 41 */ + register8_t USERROW42; /* User Row Byte 42 */ + register8_t USERROW43; /* User Row Byte 43 */ + register8_t USERROW44; /* User Row Byte 44 */ + register8_t USERROW45; /* User Row Byte 45 */ + register8_t USERROW46; /* User Row Byte 46 */ + register8_t USERROW47; /* User Row Byte 47 */ + register8_t USERROW48; /* User Row Byte 48 */ + register8_t USERROW49; /* User Row Byte 49 */ + register8_t USERROW50; /* User Row Byte 50 */ + register8_t USERROW51; /* User Row Byte 51 */ + register8_t USERROW52; /* User Row Byte 52 */ + register8_t USERROW53; /* User Row Byte 53 */ + register8_t USERROW54; /* User Row Byte 54 */ + register8_t USERROW55; /* User Row Byte 55 */ + register8_t USERROW56; /* User Row Byte 56 */ + register8_t USERROW57; /* User Row Byte 57 */ + register8_t USERROW58; /* User Row Byte 58 */ + register8_t USERROW59; /* User Row Byte 59 */ + register8_t USERROW60; /* User Row Byte 60 */ + register8_t USERROW61; /* User Row Byte 61 */ + register8_t USERROW62; /* User Row Byte 62 */ + register8_t USERROW63; /* User Row Byte 63 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* AC0 reference select select */ +typedef enum VREF_AC0REFSEL_enum +{ + VREF_AC0REFSEL_1V024_gc = (0x00<<0), /* Voltage reference at 1.024V */ + VREF_AC0REFSEL_2V048_gc = (0x01<<0), /* Voltage reference at 2.048V */ + VREF_AC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_AC0REFSEL_4V096_gc = (0x03<<0), /* Voltage reference at 4.096V */ + VREF_AC0REFSEL_AVDD_gc = (0x07<<0), /* voltage reference at supply */ +} VREF_AC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define NVMBIST (*(NVMBIST_t *) 0x00C0) /* BIST in the NVMCTRL module */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define PORTMUX (*(PORTMUX_t *) 0x05E0) /* Port Multiplexer */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1 (*(USART_t *) 0x0820) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x08A0) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A80) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0A90) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* NVMBIST - BIST in the NVMCTRL module */ +#define NVMBIST_CTRLA _SFR_MEM8(0x00C0) +#define NVMBIST_ADDRPAT _SFR_MEM8(0x00C1) +#define NVMBIST_DATAPAT _SFR_MEM8(0x00C2) +#define NVMBIST_STATUS _SFR_MEM8(0x00C3) +#define NVMBIST_CNT _SFR_MEM16(0x00C4) +#define NVMBIST_CNTL _SFR_MEM8(0x00C4) +#define NVMBIST_CNTH _SFR_MEM8(0x00C5) +#define NVMBIST_END _SFR_MEM32(0x00C6) +#define NVMBIST_END0 _SFR_MEM8(0x00C6) +#define NVMBIST_END1 _SFR_MEM8(0x00C7) +#define NVMBIST_END2 _SFR_MEM8(0x00C8) +#define NVMBIST_END3 _SFR_MEM8(0x00C9) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CALIB _SFR_MEM8(0x0146) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_SWEVENTA _SFR_MEM8(0x0180) +#define EVSYS_CHANNEL0 _SFR_MEM8(0x0190) +#define EVSYS_CHANNEL1 _SFR_MEM8(0x0191) +#define EVSYS_CHANNEL2 _SFR_MEM8(0x0192) +#define EVSYS_CHANNEL3 _SFR_MEM8(0x0193) +#define EVSYS_CHANNEL4 _SFR_MEM8(0x0194) +#define EVSYS_CHANNEL5 _SFR_MEM8(0x0195) +#define EVSYS_USERCCLLUT0A _SFR_MEM8(0x01A0) +#define EVSYS_USERCCLLUT0B _SFR_MEM8(0x01A1) +#define EVSYS_USERCCLLUT1A _SFR_MEM8(0x01A2) +#define EVSYS_USERCCLLUT1B _SFR_MEM8(0x01A3) +#define EVSYS_USERCCLLUT2A _SFR_MEM8(0x01A4) +#define EVSYS_USERCCLLUT2B _SFR_MEM8(0x01A5) +#define EVSYS_USERCCLLUT3A _SFR_MEM8(0x01A6) +#define EVSYS_USERCCLLUT3B _SFR_MEM8(0x01A7) +#define EVSYS_USERADC0START _SFR_MEM8(0x01A8) +#define EVSYS_USEREVSYSEVOUTA _SFR_MEM8(0x01A9) +#define EVSYS_USEREVSYSEVOUTB _SFR_MEM8(0x01AA) +#define EVSYS_USEREVSYSEVOUTC _SFR_MEM8(0x01AB) +#define EVSYS_USERUSART0IRDA _SFR_MEM8(0x01AC) +#define EVSYS_USERUSART1IRDA _SFR_MEM8(0x01AD) +#define EVSYS_USERTCA0CNTA _SFR_MEM8(0x01AE) +#define EVSYS_USERTCA0CNTB _SFR_MEM8(0x01AF) +#define EVSYS_USERTCB0CAPT _SFR_MEM8(0x01B0) +#define EVSYS_USERTCB0COUNT _SFR_MEM8(0x01B1) +#define EVSYS_USERTCB1CAPT _SFR_MEM8(0x01B2) +#define EVSYS_USERTCB1COUNT _SFR_MEM8(0x01B3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_SEQCTRL1 _SFR_MEM8(0x01C2) +#define CCL_INTCTRL0 _SFR_MEM8(0x01C5) +#define CCL_INTFLAGS _SFR_MEM8(0x01C7) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C8) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C9) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01CA) +#define CCL_TRUTH0 _SFR_MEM8(0x01CB) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01CC) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CD) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CE) +#define CCL_TRUTH1 _SFR_MEM8(0x01CF) +#define CCL_LUT2CTRLA _SFR_MEM8(0x01D0) +#define CCL_LUT2CTRLB _SFR_MEM8(0x01D1) +#define CCL_LUT2CTRLC _SFR_MEM8(0x01D2) +#define CCL_TRUTH2 _SFR_MEM8(0x01D3) +#define CCL_LUT3CTRLA _SFR_MEM8(0x01D4) +#define CCL_LUT3CTRLB _SFR_MEM8(0x01D5) +#define CCL_LUT3CTRLC _SFR_MEM8(0x01D6) +#define CCL_TRUTH3 _SFR_MEM8(0x01D7) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PORTCTRL _SFR_MEM8(0x040A) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PORTCTRL _SFR_MEM8(0x042A) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PORTCTRL _SFR_MEM8(0x044A) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_EVSYSROUTEA _SFR_MEM8(0x05E0) +#define PORTMUX_CCLROUTEA _SFR_MEM8(0x05E1) +#define PORTMUX_USARTROUTEA _SFR_MEM8(0x05E2) +#define PORTMUX_SPIROUTEA _SFR_MEM8(0x05E3) +#define PORTMUX_TCAROUTEA _SFR_MEM8(0x05E4) +#define PORTMUX_TCBROUTEA _SFR_MEM8(0x05E5) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_INTCTRL _SFR_MEM8(0x0604) +#define ADC0_INTFLAGS _SFR_MEM8(0x0605) +#define ADC0_STATUS _SFR_MEM8(0x0606) +#define ADC0_DBGCTRL _SFR_MEM8(0x0607) +#define ADC0_CTRLE _SFR_MEM8(0x0608) +#define ADC0_CTRLF _SFR_MEM8(0x0609) +#define ADC0_COMMAND _SFR_MEM8(0x060A) +#define ADC0_PGACTRL _SFR_MEM8(0x060B) +#define ADC0_MUXPOS _SFR_MEM8(0x060C) +#define ADC0_MUXNEG _SFR_MEM8(0x060D) +#define ADC0_RESULT _SFR_MEM32(0x0610) +#define ADC0_RESULT0 _SFR_MEM8(0x0610) +#define ADC0_RESULT1 _SFR_MEM8(0x0611) +#define ADC0_RESULT2 _SFR_MEM8(0x0612) +#define ADC0_RESULT3 _SFR_MEM8(0x0613) +#define ADC0_SAMPLE _SFR_MEM16(0x0614) +#define ADC0_SAMPLEL _SFR_MEM8(0x0614) +#define ADC0_SAMPLEH _SFR_MEM8(0x0615) +#define ADC0_TEMP0 _SFR_MEM8(0x0618) +#define ADC0_TEMP1 _SFR_MEM8(0x0619) +#define ADC0_TEMP2 _SFR_MEM8(0x061A) +#define ADC0_WINLT _SFR_MEM16(0x061C) +#define ADC0_WINLTL _SFR_MEM8(0x061C) +#define ADC0_WINLTH _SFR_MEM8(0x061D) +#define ADC0_WINHT _SFR_MEM16(0x061E) +#define ADC0_WINHTL _SFR_MEM8(0x061E) +#define ADC0_WINHTH _SFR_MEM8(0x061F) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_DACREF _SFR_MEM8(0x0684) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_CTRLD _SFR_MEM8(0x080A) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* USART (USART1) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART1_RXDATAL _SFR_MEM8(0x0820) +#define USART1_RXDATAH _SFR_MEM8(0x0821) +#define USART1_TXDATAL _SFR_MEM8(0x0822) +#define USART1_TXDATAH _SFR_MEM8(0x0823) +#define USART1_STATUS _SFR_MEM8(0x0824) +#define USART1_CTRLA _SFR_MEM8(0x0825) +#define USART1_CTRLB _SFR_MEM8(0x0826) +#define USART1_CTRLC _SFR_MEM8(0x0827) +#define USART1_BAUD _SFR_MEM16(0x0828) +#define USART1_BAUDL _SFR_MEM8(0x0828) +#define USART1_BAUDH _SFR_MEM8(0x0829) +#define USART1_CTRLD _SFR_MEM8(0x082A) +#define USART1_DBGCTRL _SFR_MEM8(0x082B) +#define USART1_EVCTRL _SFR_MEM8(0x082C) +#define USART1_TXPLCTRL _SFR_MEM8(0x082D) +#define USART1_RXPLCTRL _SFR_MEM8(0x082E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x08A0) +#define TWI0_DBGCTRL _SFR_MEM8(0x08A2) +#define TWI0_MCTRLA _SFR_MEM8(0x08A3) +#define TWI0_MCTRLB _SFR_MEM8(0x08A4) +#define TWI0_MSTATUS _SFR_MEM8(0x08A5) +#define TWI0_MBAUD _SFR_MEM8(0x08A6) +#define TWI0_MADDR _SFR_MEM8(0x08A7) +#define TWI0_MDATA _SFR_MEM8(0x08A8) +#define TWI0_SCTRLA _SFR_MEM8(0x08A9) +#define TWI0_SCTRLB _SFR_MEM8(0x08AA) +#define TWI0_SSTATUS _SFR_MEM8(0x08AB) +#define TWI0_SADDR _SFR_MEM8(0x08AC) +#define TWI0_SDATA _SFR_MEM8(0x08AD) +#define TWI0_SADDRMASK _SFR_MEM8(0x08AE) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x08C0) +#define SPI0_CTRLB _SFR_MEM8(0x08C1) +#define SPI0_INTCTRL _SFR_MEM8(0x08C2) +#define SPI0_INTFLAGS _SFR_MEM8(0x08C3) +#define SPI0_DATA _SFR_MEM8(0x08C4) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A80) +#define TCB0_CTRLB _SFR_MEM8(0x0A81) +#define TCB0_EVCTRL _SFR_MEM8(0x0A84) +#define TCB0_INTCTRL _SFR_MEM8(0x0A85) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A86) +#define TCB0_STATUS _SFR_MEM8(0x0A87) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A88) +#define TCB0_TEMP _SFR_MEM8(0x0A89) +#define TCB0_CNT _SFR_MEM16(0x0A8A) +#define TCB0_CNTL _SFR_MEM8(0x0A8A) +#define TCB0_CNTH _SFR_MEM8(0x0A8B) +#define TCB0_CCMP _SFR_MEM16(0x0A8C) +#define TCB0_CCMPL _SFR_MEM8(0x0A8C) +#define TCB0_CCMPH _SFR_MEM8(0x0A8D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0A90) +#define TCB1_CTRLB _SFR_MEM8(0x0A91) +#define TCB1_EVCTRL _SFR_MEM8(0x0A94) +#define TCB1_INTCTRL _SFR_MEM8(0x0A95) +#define TCB1_INTFLAGS _SFR_MEM8(0x0A96) +#define TCB1_STATUS _SFR_MEM8(0x0A97) +#define TCB1_DBGCTRL _SFR_MEM8(0x0A98) +#define TCB1_TEMP _SFR_MEM8(0x0A99) +#define TCB1_CNT _SFR_MEM16(0x0A9A) +#define TCB1_CNTL _SFR_MEM8(0x0A9A) +#define TCB1_CNTH _SFR_MEM8(0x0A9B) +#define TCB1_CCMP _SFR_MEM16(0x0A9C) +#define TCB1_CCMPL _SFR_MEM8(0x0A9C) +#define TCB1_CCMPH _SFR_MEM8(0x0A9D) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) +#define SYSCFG_OCDM _SFR_MEM8(0x0F18) +#define SYSCFG_OCDMS _SFR_MEM8(0x0F19) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_OSCCAL32K _SFR_MEM8(0x1114) +#define SIGROW_OSCCAL16M0 _SFR_MEM8(0x1118) +#define SIGROW_OSCCAL16M1 _SFR_MEM8(0x1119) +#define SIGROW_OSCCAL20M0 _SFR_MEM8(0x111A) +#define SIGROW_OSCCAL20M1 _SFR_MEM8(0x111B) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) +#define SIGROW_CHECKSUM1 _SFR_MEM8(0x112F) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) +#define USERROW_USERROW32 _SFR_MEM8(0x1320) +#define USERROW_USERROW33 _SFR_MEM8(0x1321) +#define USERROW_USERROW34 _SFR_MEM8(0x1322) +#define USERROW_USERROW35 _SFR_MEM8(0x1323) +#define USERROW_USERROW36 _SFR_MEM8(0x1324) +#define USERROW_USERROW37 _SFR_MEM8(0x1325) +#define USERROW_USERROW38 _SFR_MEM8(0x1326) +#define USERROW_USERROW39 _SFR_MEM8(0x1327) +#define USERROW_USERROW40 _SFR_MEM8(0x1328) +#define USERROW_USERROW41 _SFR_MEM8(0x1329) +#define USERROW_USERROW42 _SFR_MEM8(0x132A) +#define USERROW_USERROW43 _SFR_MEM8(0x132B) +#define USERROW_USERROW44 _SFR_MEM8(0x132C) +#define USERROW_USERROW45 _SFR_MEM8(0x132D) +#define USERROW_USERROW46 _SFR_MEM8(0x132E) +#define USERROW_USERROW47 _SFR_MEM8(0x132F) +#define USERROW_USERROW48 _SFR_MEM8(0x1330) +#define USERROW_USERROW49 _SFR_MEM8(0x1331) +#define USERROW_USERROW50 _SFR_MEM8(0x1332) +#define USERROW_USERROW51 _SFR_MEM8(0x1333) +#define USERROW_USERROW52 _SFR_MEM8(0x1334) +#define USERROW_USERROW53 _SFR_MEM8(0x1335) +#define USERROW_USERROW54 _SFR_MEM8(0x1336) +#define USERROW_USERROW55 _SFR_MEM8(0x1337) +#define USERROW_USERROW56 _SFR_MEM8(0x1338) +#define USERROW_USERROW57 _SFR_MEM8(0x1339) +#define USERROW_USERROW58 _SFR_MEM8(0x133A) +#define USERROW_USERROW59 _SFR_MEM8(0x133B) +#define USERROW_USERROW60 _SFR_MEM8(0x133C) +#define USERROW_USERROW61 _SFR_MEM8(0x133D) +#define USERROW_USERROW62 _SFR_MEM8(0x133E) +#define USERROW_USERROW63 _SFR_MEM8(0x133F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.DACREF bit masks and bit positions */ +#define AC_DATA_gm 0xFF /* DAC voltage reference group mask. */ +#define AC_DATA_gp 0 /* DAC voltage reference group position. */ +#define AC_DATA0_bm (1<<0) /* DAC voltage reference bit 0 mask. */ +#define AC_DATA0_bp 0 /* DAC voltage reference bit 0 position. */ +#define AC_DATA1_bm (1<<1) /* DAC voltage reference bit 1 mask. */ +#define AC_DATA1_bp 1 /* DAC voltage reference bit 1 position. */ +#define AC_DATA2_bm (1<<2) /* DAC voltage reference bit 2 mask. */ +#define AC_DATA2_bp 2 /* DAC voltage reference bit 2 position. */ +#define AC_DATA3_bm (1<<3) /* DAC voltage reference bit 3 mask. */ +#define AC_DATA3_bp 3 /* DAC voltage reference bit 3 position. */ +#define AC_DATA4_bm (1<<4) /* DAC voltage reference bit 4 mask. */ +#define AC_DATA4_bp 4 /* DAC voltage reference bit 4 position. */ +#define AC_DATA5_bm (1<<5) /* DAC voltage reference bit 5 mask. */ +#define AC_DATA5_bp 5 /* DAC voltage reference bit 5 position. */ +#define AC_DATA6_bm (1<<6) /* DAC voltage reference bit 6 mask. */ +#define AC_DATA6_bp 6 /* DAC voltage reference bit 6 position. */ +#define AC_DATA7_bm (1<<7) /* DAC voltage reference bit 7 mask. */ +#define AC_DATA7_bp 7 /* DAC voltage reference bit 7 position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_LOWLAT_bm 0x20 /* ADC Low latency mode bit mask. */ +#define ADC_LOWLAT_bp 5 /* ADC Low latency mode bit position. */ +#define ADC_RUNSTDBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTDBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_PRESC_gm 0x0F /* Prescaler Value group mask. */ +#define ADC_PRESC_gp 0 /* Prescaler Value group position. */ +#define ADC_PRESC0_bm (1<<0) /* Prescaler Value bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Prescaler Value bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Prescaler Value bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Prescaler Value bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Prescaler Value bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Prescaler Value bit 2 position. */ +#define ADC_PRESC3_bm (1<<3) /* Prescaler Value bit 3 mask. */ +#define ADC_PRESC3_bp 3 /* Prescaler Value bit 3 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_REFSEL_gm 0x07 /* Reference select group mask. */ +#define ADC_REFSEL_gp 0 /* Reference select group position. */ +#define ADC_REFSEL0_bm (1<<0) /* Reference select bit 0 mask. */ +#define ADC_REFSEL0_bp 0 /* Reference select bit 0 position. */ +#define ADC_REFSEL1_bm (1<<1) /* Reference select bit 1 mask. */ +#define ADC_REFSEL1_bp 1 /* Reference select bit 1 position. */ +#define ADC_REFSEL2_bm (1<<2) /* Reference select bit 2 mask. */ +#define ADC_REFSEL2_bp 2 /* Reference select bit 2 position. */ +#define ADC_TIMEBASE_gm 0xF8 /* Reference Selection group mask. */ +#define ADC_TIMEBASE_gp 3 /* Reference Selection group position. */ +#define ADC_TIMEBASE0_bm (1<<3) /* Reference Selection bit 0 mask. */ +#define ADC_TIMEBASE0_bp 3 /* Reference Selection bit 0 position. */ +#define ADC_TIMEBASE1_bm (1<<4) /* Reference Selection bit 1 mask. */ +#define ADC_TIMEBASE1_bp 4 /* Reference Selection bit 1 position. */ +#define ADC_TIMEBASE2_bm (1<<5) /* Reference Selection bit 2 mask. */ +#define ADC_TIMEBASE2_bp 5 /* Reference Selection bit 2 position. */ +#define ADC_TIMEBASE3_bm (1<<6) /* Reference Selection bit 3 mask. */ +#define ADC_TIMEBASE3_bp 6 /* Reference Selection bit 3 position. */ +#define ADC_TIMEBASE4_bm (1<<7) /* Reference Selection bit 4 mask. */ +#define ADC_TIMEBASE4_bp 7 /* Reference Selection bit 4 position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ +#define ADC_WINSRC_bm 0x08 /* Window Mode Source bit mask. */ +#define ADC_WINSRC_bp 3 /* Window Mode Source bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_SAMPRDY_bm 0x02 /* Sample Ready Interrupt Enable bit mask. */ +#define ADC_SAMPRDY_bp 1 /* Sample Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x04 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 2 /* Window Comparator Interrupt Enable bit position. */ +#define ADC_RESOVR_bm 0x08 /* Result Overwritten Interrupt Enable bit mask. */ +#define ADC_RESOVR_bp 3 /* Result Overwritten Interrupt Enable bit position. */ +#define ADC_SAMPOVR_bm 0x10 /* Sample Overwritten Interrupt Enable bit mask. */ +#define ADC_SAMPOVR_bp 4 /* Sample Overwritten Interrupt Enable bit position. */ +#define ADC_TRIGOVR_bm 0x20 /* Trigger Overrun Interrupt Enable bit mask. */ +#define ADC_TRIGOVR_bp 5 /* Trigger Overrun Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_SAMPRDY is already defined. */ +/* ADC_WCMP is already defined. */ +/* ADC_RESOVR is already defined. */ +/* ADC_SAMPOVR is already defined. */ +/* ADC_TRIGOVR is already defined. */ + +/* ADC.STATUS bit masks and bit positions */ +#define ADC_ADCBUSY_bm 0x01 /* ADC Busy bit mask. */ +#define ADC_ADCBUSY_bp 0 /* ADC Busy bit position. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_SAMPDUR_gm 0xFF /* Sampling time group mask. */ +#define ADC_SAMPDUR_gp 0 /* Sampling time group position. */ +#define ADC_SAMPDUR0_bm (1<<0) /* Sampling time bit 0 mask. */ +#define ADC_SAMPDUR0_bp 0 /* Sampling time bit 0 position. */ +#define ADC_SAMPDUR1_bm (1<<1) /* Sampling time bit 1 mask. */ +#define ADC_SAMPDUR1_bp 1 /* Sampling time bit 1 position. */ +#define ADC_SAMPDUR2_bm (1<<2) /* Sampling time bit 2 mask. */ +#define ADC_SAMPDUR2_bp 2 /* Sampling time bit 2 position. */ +#define ADC_SAMPDUR3_bm (1<<3) /* Sampling time bit 3 mask. */ +#define ADC_SAMPDUR3_bp 3 /* Sampling time bit 3 position. */ +#define ADC_SAMPDUR4_bm (1<<4) /* Sampling time bit 4 mask. */ +#define ADC_SAMPDUR4_bp 4 /* Sampling time bit 4 position. */ +#define ADC_SAMPDUR5_bm (1<<5) /* Sampling time bit 5 mask. */ +#define ADC_SAMPDUR5_bp 5 /* Sampling time bit 5 position. */ +#define ADC_SAMPDUR6_bm (1<<6) /* Sampling time bit 6 mask. */ +#define ADC_SAMPDUR6_bp 6 /* Sampling time bit 6 position. */ +#define ADC_SAMPDUR7_bm (1<<7) /* Sampling time bit 7 mask. */ +#define ADC_SAMPDUR7_bp 7 /* Sampling time bit 7 position. */ + +/* ADC.CTRLF bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x0F /* Sample numbers group mask. */ +#define ADC_SAMPNUM_gp 0 /* Sample numbers group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Sample numbers bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Sample numbers bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Sample numbers bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Sample numbers bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Sample numbers bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Sample numbers bit 2 position. */ +#define ADC_SAMPNUM3_bm (1<<3) /* Sample numbers bit 3 mask. */ +#define ADC_SAMPNUM3_bp 3 /* Sample numbers bit 3 position. */ +#define ADC_LEFTADJ_bm 0x10 /* Left adjust bit mask. */ +#define ADC_LEFTADJ_bp 4 /* Left adjust bit position. */ +#define ADC_FREERUN_bm 0x20 /* Free running mode bit mask. */ +#define ADC_FREERUN_bp 5 /* Free running mode bit position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_START_gm 0x07 /* Start command group mask. */ +#define ADC_START_gp 0 /* Start command group position. */ +#define ADC_START0_bm (1<<0) /* Start command bit 0 mask. */ +#define ADC_START0_bp 0 /* Start command bit 0 position. */ +#define ADC_START1_bm (1<<1) /* Start command bit 1 mask. */ +#define ADC_START1_bp 1 /* Start command bit 1 position. */ +#define ADC_START2_bm (1<<2) /* Start command bit 2 mask. */ +#define ADC_START2_bp 2 /* Start command bit 2 position. */ +#define ADC_MODE_gm 0x70 /* Mode group mask. */ +#define ADC_MODE_gp 4 /* Mode group position. */ +#define ADC_MODE0_bm (1<<4) /* Mode bit 0 mask. */ +#define ADC_MODE0_bp 4 /* Mode bit 0 position. */ +#define ADC_MODE1_bm (1<<5) /* Mode bit 1 mask. */ +#define ADC_MODE1_bp 5 /* Mode bit 1 position. */ +#define ADC_MODE2_bm (1<<6) /* Mode bit 2 mask. */ +#define ADC_MODE2_bp 6 /* Mode bit 2 position. */ +#define ADC_DIFF_bm 0x80 /* Differential mode bit mask. */ +#define ADC_DIFF_bp 7 /* Differential mode bit position. */ + +/* ADC.PGACTRL bit masks and bit positions */ +#define ADC_PGAEN_bm 0x01 /* PGA Enable bit mask. */ +#define ADC_PGAEN_bp 0 /* PGA Enable bit position. */ +#define ADC_ADCPGASAMPDUR_gm 0x06 /* ADC PGA Sample Duration group mask. */ +#define ADC_ADCPGASAMPDUR_gp 1 /* ADC PGA Sample Duration group position. */ +#define ADC_ADCPGASAMPDUR0_bm (1<<1) /* ADC PGA Sample Duration bit 0 mask. */ +#define ADC_ADCPGASAMPDUR0_bp 1 /* ADC PGA Sample Duration bit 0 position. */ +#define ADC_ADCPGASAMPDUR1_bm (1<<2) /* ADC PGA Sample Duration bit 1 mask. */ +#define ADC_ADCPGASAMPDUR1_bp 2 /* ADC PGA Sample Duration bit 1 position. */ +#define ADC_PGABIASSEL_gm 0x18 /* PGA BIAS Select group mask. */ +#define ADC_PGABIASSEL_gp 3 /* PGA BIAS Select group position. */ +#define ADC_PGABIASSEL0_bm (1<<3) /* PGA BIAS Select bit 0 mask. */ +#define ADC_PGABIASSEL0_bp 3 /* PGA BIAS Select bit 0 position. */ +#define ADC_PGABIASSEL1_bm (1<<4) /* PGA BIAS Select bit 1 mask. */ +#define ADC_PGABIASSEL1_bp 4 /* PGA BIAS Select bit 1 position. */ +#define ADC_GAIN_gm 0xE0 /* Gain group mask. */ +#define ADC_GAIN_gp 5 /* Gain group position. */ +#define ADC_GAIN0_bm (1<<5) /* Gain bit 0 mask. */ +#define ADC_GAIN0_bp 5 /* Gain bit 0 position. */ +#define ADC_GAIN1_bm (1<<6) /* Gain bit 1 mask. */ +#define ADC_GAIN1_bp 6 /* Gain bit 1 position. */ +#define ADC_GAIN2_bm (1<<7) /* Gain bit 2 mask. */ +#define ADC_GAIN2_bp 7 /* Gain bit 2 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x3F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ +#define ADC_MUXPOS5_bm (1<<5) /* Analog Channel Selection Bits bit 5 mask. */ +#define ADC_MUXPOS5_bp 5 /* Analog Channel Selection Bits bit 5 position. */ +#define ADC_VIA_gm 0xC0 /* VIA group mask. */ +#define ADC_VIA_gp 6 /* VIA group position. */ +#define ADC_VIA0_bm (1<<6) /* VIA bit 0 mask. */ +#define ADC_VIA0_bp 6 /* VIA bit 0 position. */ +#define ADC_VIA1_bm (1<<7) /* VIA bit 1 mask. */ +#define ADC_VIA1_bp 7 /* VIA bit 1 position. */ + +/* ADC.MUXNEG bit masks and bit positions */ +#define ADC_MUXNEG_gm 0x3F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXNEG_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXNEG0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXNEG0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXNEG1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXNEG1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXNEG2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXNEG2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXNEG3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXNEG3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXNEG4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXNEG4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ +#define ADC_MUXNEG5_bm (1<<5) /* Analog Channel Selection Bits bit 5 mask. */ +#define ADC_MUXNEG5_bp 5 /* Analog Channel Selection Bits bit 5 position. */ +/* ADC_VIA is already defined. */ + + + +/* ADC.TEMP0 bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + +/* ADC.TEMP1 bit masks and bit positions */ +/* ADC_TEMP is already defined. */ + +/* ADC.TEMP2 bit masks and bit positions */ +/* ADC_TEMP is already defined. */ + + + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL0_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL0_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL00_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL00_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL01_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL01_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL02_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL02_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.SEQCTRL1 bit masks and bit positions */ +#define CCL_SEQSEL1_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL1_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL10_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL10_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL11_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL11_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL12_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL12_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.INTCTRL0 bit masks and bit positions */ +#define CCL_INTMODE0_gm 0x03 /* Interrupt Mode for LUT0 group mask. */ +#define CCL_INTMODE0_gp 0 /* Interrupt Mode for LUT0 group position. */ +#define CCL_INTMODE00_bm (1<<0) /* Interrupt Mode for LUT0 bit 0 mask. */ +#define CCL_INTMODE00_bp 0 /* Interrupt Mode for LUT0 bit 0 position. */ +#define CCL_INTMODE01_bm (1<<1) /* Interrupt Mode for LUT0 bit 1 mask. */ +#define CCL_INTMODE01_bp 1 /* Interrupt Mode for LUT0 bit 1 position. */ +#define CCL_INTMODE1_gm 0x0C /* Interrupt Mode for LUT1 group mask. */ +#define CCL_INTMODE1_gp 2 /* Interrupt Mode for LUT1 group position. */ +#define CCL_INTMODE10_bm (1<<2) /* Interrupt Mode for LUT1 bit 0 mask. */ +#define CCL_INTMODE10_bp 2 /* Interrupt Mode for LUT1 bit 0 position. */ +#define CCL_INTMODE11_bm (1<<3) /* Interrupt Mode for LUT1 bit 1 mask. */ +#define CCL_INTMODE11_bp 3 /* Interrupt Mode for LUT1 bit 1 position. */ +#define CCL_INTMODE2_gm 0x30 /* Interrupt Mode for LUT2 group mask. */ +#define CCL_INTMODE2_gp 4 /* Interrupt Mode for LUT2 group position. */ +#define CCL_INTMODE20_bm (1<<4) /* Interrupt Mode for LUT2 bit 0 mask. */ +#define CCL_INTMODE20_bp 4 /* Interrupt Mode for LUT2 bit 0 position. */ +#define CCL_INTMODE21_bm (1<<5) /* Interrupt Mode for LUT2 bit 1 mask. */ +#define CCL_INTMODE21_bp 5 /* Interrupt Mode for LUT2 bit 1 position. */ +#define CCL_INTMODE3_gm 0xC0 /* Interrupt Mode for LUT3 group mask. */ +#define CCL_INTMODE3_gp 6 /* Interrupt Mode for LUT3 group position. */ +#define CCL_INTMODE30_bm (1<<6) /* Interrupt Mode for LUT3 bit 0 mask. */ +#define CCL_INTMODE30_bp 6 /* Interrupt Mode for LUT3 bit 0 position. */ +#define CCL_INTMODE31_bm (1<<7) /* Interrupt Mode for LUT3 bit 1 mask. */ +#define CCL_INTMODE31_bp 7 /* Interrupt Mode for LUT3 bit 1 position. */ + +/* CCL.INTFLAGS bit masks and bit positions */ +#define CCL_INT_gm 0x0F /* Interrupt Flags group mask. */ +#define CCL_INT_gp 0 /* Interrupt Flags group position. */ +#define CCL_INT0_bm (1<<0) /* Interrupt Flags bit 0 mask. */ +#define CCL_INT0_bp 0 /* Interrupt Flags bit 0 position. */ +#define CCL_INT1_bm (1<<1) /* Interrupt Flags bit 1 mask. */ +#define CCL_INT1_bp 1 /* Interrupt Flags bit 1 position. */ +#define CCL_INT2_bm (1<<2) /* Interrupt Flags bit 2 mask. */ +#define CCL_INT2_bp 2 /* Interrupt Flags bit 2 position. */ +#define CCL_INT3_bm (1<<3) /* Interrupt Flags bit 3 mask. */ +#define CCL_INT3_bp 3 /* Interrupt Flags bit 3 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_CLKSRC_gm 0x0E /* Clock Source Selection group mask. */ +#define CCL_CLKSRC_gp 1 /* Clock Source Selection group position. */ +#define CCL_CLKSRC0_bm (1<<1) /* Clock Source Selection bit 0 mask. */ +#define CCL_CLKSRC0_bp 1 /* Clock Source Selection bit 0 position. */ +#define CCL_CLKSRC1_bm (1<<2) /* Clock Source Selection bit 1 mask. */ +#define CCL_CLKSRC1_bp 2 /* Clock Source Selection bit 1 position. */ +#define CCL_CLKSRC2_bm (1<<3) /* Clock Source Selection bit 2 mask. */ +#define CCL_CLKSRC2_bp 3 /* Clock Source Selection bit 2 position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_OUTEN_bm 0x40 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 6 /* Output Enable bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT2CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT2CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT2CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CCL.LUT3CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT3CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT3CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x7F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ +#define CLKCTRL_CAL20M6_bm (1<<6) /* Calibration bit 6 mask. */ +#define CLKCTRL_CAL20M6_bp 6 /* Calibration bit 6 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.SWEVENTA bit masks and bit positions */ +#define EVSYS_SWEVENTA_gm 0xFF /* Software event on channel group mask. */ +#define EVSYS_SWEVENTA_gp 0 /* Software event on channel group position. */ +#define EVSYS_SWEVENTA0_bm (1<<0) /* Software event on channel bit 0 mask. */ +#define EVSYS_SWEVENTA0_bp 0 /* Software event on channel bit 0 position. */ +#define EVSYS_SWEVENTA1_bm (1<<1) /* Software event on channel bit 1 mask. */ +#define EVSYS_SWEVENTA1_bp 1 /* Software event on channel bit 1 position. */ +#define EVSYS_SWEVENTA2_bm (1<<2) /* Software event on channel bit 2 mask. */ +#define EVSYS_SWEVENTA2_bp 2 /* Software event on channel bit 2 position. */ +#define EVSYS_SWEVENTA3_bm (1<<3) /* Software event on channel bit 3 mask. */ +#define EVSYS_SWEVENTA3_bp 3 /* Software event on channel bit 3 position. */ +#define EVSYS_SWEVENTA4_bm (1<<4) /* Software event on channel bit 4 mask. */ +#define EVSYS_SWEVENTA4_bp 4 /* Software event on channel bit 4 position. */ +#define EVSYS_SWEVENTA5_bm (1<<5) /* Software event on channel bit 5 mask. */ +#define EVSYS_SWEVENTA5_bp 5 /* Software event on channel bit 5 position. */ +#define EVSYS_SWEVENTA6_bm (1<<6) /* Software event on channel bit 6 mask. */ +#define EVSYS_SWEVENTA6_bp 6 /* Software event on channel bit 6 position. */ +#define EVSYS_SWEVENTA7_bm (1<<7) /* Software event on channel bit 7 mask. */ +#define EVSYS_SWEVENTA7_bp 7 /* Software event on channel bit 7 position. */ + +/* EVSYS.CHANNEL0 bit masks and bit positions */ +#define EVSYS_CHANNEL0_gm 0xFF /* Channel 0 generator select group mask. */ +#define EVSYS_CHANNEL0_gp 0 /* Channel 0 generator select group position. */ +#define EVSYS_CHANNEL00_bm (1<<0) /* Channel 0 generator select bit 0 mask. */ +#define EVSYS_CHANNEL00_bp 0 /* Channel 0 generator select bit 0 position. */ +#define EVSYS_CHANNEL01_bm (1<<1) /* Channel 0 generator select bit 1 mask. */ +#define EVSYS_CHANNEL01_bp 1 /* Channel 0 generator select bit 1 position. */ +#define EVSYS_CHANNEL02_bm (1<<2) /* Channel 0 generator select bit 2 mask. */ +#define EVSYS_CHANNEL02_bp 2 /* Channel 0 generator select bit 2 position. */ +#define EVSYS_CHANNEL03_bm (1<<3) /* Channel 0 generator select bit 3 mask. */ +#define EVSYS_CHANNEL03_bp 3 /* Channel 0 generator select bit 3 position. */ +#define EVSYS_CHANNEL04_bm (1<<4) /* Channel 0 generator select bit 4 mask. */ +#define EVSYS_CHANNEL04_bp 4 /* Channel 0 generator select bit 4 position. */ +#define EVSYS_CHANNEL05_bm (1<<5) /* Channel 0 generator select bit 5 mask. */ +#define EVSYS_CHANNEL05_bp 5 /* Channel 0 generator select bit 5 position. */ +#define EVSYS_CHANNEL06_bm (1<<6) /* Channel 0 generator select bit 6 mask. */ +#define EVSYS_CHANNEL06_bp 6 /* Channel 0 generator select bit 6 position. */ +#define EVSYS_CHANNEL07_bm (1<<7) /* Channel 0 generator select bit 7 mask. */ +#define EVSYS_CHANNEL07_bp 7 /* Channel 0 generator select bit 7 position. */ + +/* EVSYS.CHANNEL1 bit masks and bit positions */ +#define EVSYS_CHANNEL1_gm 0xFF /* Channel 1 generator select group mask. */ +#define EVSYS_CHANNEL1_gp 0 /* Channel 1 generator select group position. */ +#define EVSYS_CHANNEL10_bm (1<<0) /* Channel 1 generator select bit 0 mask. */ +#define EVSYS_CHANNEL10_bp 0 /* Channel 1 generator select bit 0 position. */ +#define EVSYS_CHANNEL11_bm (1<<1) /* Channel 1 generator select bit 1 mask. */ +#define EVSYS_CHANNEL11_bp 1 /* Channel 1 generator select bit 1 position. */ +#define EVSYS_CHANNEL12_bm (1<<2) /* Channel 1 generator select bit 2 mask. */ +#define EVSYS_CHANNEL12_bp 2 /* Channel 1 generator select bit 2 position. */ +#define EVSYS_CHANNEL13_bm (1<<3) /* Channel 1 generator select bit 3 mask. */ +#define EVSYS_CHANNEL13_bp 3 /* Channel 1 generator select bit 3 position. */ +#define EVSYS_CHANNEL14_bm (1<<4) /* Channel 1 generator select bit 4 mask. */ +#define EVSYS_CHANNEL14_bp 4 /* Channel 1 generator select bit 4 position. */ +#define EVSYS_CHANNEL15_bm (1<<5) /* Channel 1 generator select bit 5 mask. */ +#define EVSYS_CHANNEL15_bp 5 /* Channel 1 generator select bit 5 position. */ +#define EVSYS_CHANNEL16_bm (1<<6) /* Channel 1 generator select bit 6 mask. */ +#define EVSYS_CHANNEL16_bp 6 /* Channel 1 generator select bit 6 position. */ +#define EVSYS_CHANNEL17_bm (1<<7) /* Channel 1 generator select bit 7 mask. */ +#define EVSYS_CHANNEL17_bp 7 /* Channel 1 generator select bit 7 position. */ + +/* EVSYS.CHANNEL2 bit masks and bit positions */ +#define EVSYS_CHANNEL2_gm 0xFF /* Channel 2 generator select group mask. */ +#define EVSYS_CHANNEL2_gp 0 /* Channel 2 generator select group position. */ +#define EVSYS_CHANNEL20_bm (1<<0) /* Channel 2 generator select bit 0 mask. */ +#define EVSYS_CHANNEL20_bp 0 /* Channel 2 generator select bit 0 position. */ +#define EVSYS_CHANNEL21_bm (1<<1) /* Channel 2 generator select bit 1 mask. */ +#define EVSYS_CHANNEL21_bp 1 /* Channel 2 generator select bit 1 position. */ +#define EVSYS_CHANNEL22_bm (1<<2) /* Channel 2 generator select bit 2 mask. */ +#define EVSYS_CHANNEL22_bp 2 /* Channel 2 generator select bit 2 position. */ +#define EVSYS_CHANNEL23_bm (1<<3) /* Channel 2 generator select bit 3 mask. */ +#define EVSYS_CHANNEL23_bp 3 /* Channel 2 generator select bit 3 position. */ +#define EVSYS_CHANNEL24_bm (1<<4) /* Channel 2 generator select bit 4 mask. */ +#define EVSYS_CHANNEL24_bp 4 /* Channel 2 generator select bit 4 position. */ +#define EVSYS_CHANNEL25_bm (1<<5) /* Channel 2 generator select bit 5 mask. */ +#define EVSYS_CHANNEL25_bp 5 /* Channel 2 generator select bit 5 position. */ +#define EVSYS_CHANNEL26_bm (1<<6) /* Channel 2 generator select bit 6 mask. */ +#define EVSYS_CHANNEL26_bp 6 /* Channel 2 generator select bit 6 position. */ +#define EVSYS_CHANNEL27_bm (1<<7) /* Channel 2 generator select bit 7 mask. */ +#define EVSYS_CHANNEL27_bp 7 /* Channel 2 generator select bit 7 position. */ + +/* EVSYS.CHANNEL3 bit masks and bit positions */ +#define EVSYS_CHANNEL3_gm 0xFF /* Channel 3 generator select group mask. */ +#define EVSYS_CHANNEL3_gp 0 /* Channel 3 generator select group position. */ +#define EVSYS_CHANNEL30_bm (1<<0) /* Channel 3 generator select bit 0 mask. */ +#define EVSYS_CHANNEL30_bp 0 /* Channel 3 generator select bit 0 position. */ +#define EVSYS_CHANNEL31_bm (1<<1) /* Channel 3 generator select bit 1 mask. */ +#define EVSYS_CHANNEL31_bp 1 /* Channel 3 generator select bit 1 position. */ +#define EVSYS_CHANNEL32_bm (1<<2) /* Channel 3 generator select bit 2 mask. */ +#define EVSYS_CHANNEL32_bp 2 /* Channel 3 generator select bit 2 position. */ +#define EVSYS_CHANNEL33_bm (1<<3) /* Channel 3 generator select bit 3 mask. */ +#define EVSYS_CHANNEL33_bp 3 /* Channel 3 generator select bit 3 position. */ +#define EVSYS_CHANNEL34_bm (1<<4) /* Channel 3 generator select bit 4 mask. */ +#define EVSYS_CHANNEL34_bp 4 /* Channel 3 generator select bit 4 position. */ +#define EVSYS_CHANNEL35_bm (1<<5) /* Channel 3 generator select bit 5 mask. */ +#define EVSYS_CHANNEL35_bp 5 /* Channel 3 generator select bit 5 position. */ +#define EVSYS_CHANNEL36_bm (1<<6) /* Channel 3 generator select bit 6 mask. */ +#define EVSYS_CHANNEL36_bp 6 /* Channel 3 generator select bit 6 position. */ +#define EVSYS_CHANNEL37_bm (1<<7) /* Channel 3 generator select bit 7 mask. */ +#define EVSYS_CHANNEL37_bp 7 /* Channel 3 generator select bit 7 position. */ + +/* EVSYS.CHANNEL4 bit masks and bit positions */ +#define EVSYS_CHANNEL4_gm 0xFF /* Channel 4 generator select group mask. */ +#define EVSYS_CHANNEL4_gp 0 /* Channel 4 generator select group position. */ +#define EVSYS_CHANNEL40_bm (1<<0) /* Channel 4 generator select bit 0 mask. */ +#define EVSYS_CHANNEL40_bp 0 /* Channel 4 generator select bit 0 position. */ +#define EVSYS_CHANNEL41_bm (1<<1) /* Channel 4 generator select bit 1 mask. */ +#define EVSYS_CHANNEL41_bp 1 /* Channel 4 generator select bit 1 position. */ +#define EVSYS_CHANNEL42_bm (1<<2) /* Channel 4 generator select bit 2 mask. */ +#define EVSYS_CHANNEL42_bp 2 /* Channel 4 generator select bit 2 position. */ +#define EVSYS_CHANNEL43_bm (1<<3) /* Channel 4 generator select bit 3 mask. */ +#define EVSYS_CHANNEL43_bp 3 /* Channel 4 generator select bit 3 position. */ +#define EVSYS_CHANNEL44_bm (1<<4) /* Channel 4 generator select bit 4 mask. */ +#define EVSYS_CHANNEL44_bp 4 /* Channel 4 generator select bit 4 position. */ +#define EVSYS_CHANNEL45_bm (1<<5) /* Channel 4 generator select bit 5 mask. */ +#define EVSYS_CHANNEL45_bp 5 /* Channel 4 generator select bit 5 position. */ +#define EVSYS_CHANNEL46_bm (1<<6) /* Channel 4 generator select bit 6 mask. */ +#define EVSYS_CHANNEL46_bp 6 /* Channel 4 generator select bit 6 position. */ +#define EVSYS_CHANNEL47_bm (1<<7) /* Channel 4 generator select bit 7 mask. */ +#define EVSYS_CHANNEL47_bp 7 /* Channel 4 generator select bit 7 position. */ + +/* EVSYS.CHANNEL5 bit masks and bit positions */ +#define EVSYS_CHANNEL5_gm 0xFF /* Channel 5 generator select group mask. */ +#define EVSYS_CHANNEL5_gp 0 /* Channel 5 generator select group position. */ +#define EVSYS_CHANNEL50_bm (1<<0) /* Channel 5 generator select bit 0 mask. */ +#define EVSYS_CHANNEL50_bp 0 /* Channel 5 generator select bit 0 position. */ +#define EVSYS_CHANNEL51_bm (1<<1) /* Channel 5 generator select bit 1 mask. */ +#define EVSYS_CHANNEL51_bp 1 /* Channel 5 generator select bit 1 position. */ +#define EVSYS_CHANNEL52_bm (1<<2) /* Channel 5 generator select bit 2 mask. */ +#define EVSYS_CHANNEL52_bp 2 /* Channel 5 generator select bit 2 position. */ +#define EVSYS_CHANNEL53_bm (1<<3) /* Channel 5 generator select bit 3 mask. */ +#define EVSYS_CHANNEL53_bp 3 /* Channel 5 generator select bit 3 position. */ +#define EVSYS_CHANNEL54_bm (1<<4) /* Channel 5 generator select bit 4 mask. */ +#define EVSYS_CHANNEL54_bp 4 /* Channel 5 generator select bit 4 position. */ +#define EVSYS_CHANNEL55_bm (1<<5) /* Channel 5 generator select bit 5 mask. */ +#define EVSYS_CHANNEL55_bp 5 /* Channel 5 generator select bit 5 position. */ +#define EVSYS_CHANNEL56_bm (1<<6) /* Channel 5 generator select bit 6 mask. */ +#define EVSYS_CHANNEL56_bp 6 /* Channel 5 generator select bit 6 position. */ +#define EVSYS_CHANNEL57_bm (1<<7) /* Channel 5 generator select bit 7 mask. */ +#define EVSYS_CHANNEL57_bp 7 /* Channel 5 generator select bit 7 position. */ + +/* EVSYS.USERCCLLUT0A bit masks and bit positions */ +#define EVSYS_USER_gm 0xFF /* Channel selector group mask. */ +#define EVSYS_USER_gp 0 /* Channel selector group position. */ +#define EVSYS_USER0_bm (1<<0) /* Channel selector bit 0 mask. */ +#define EVSYS_USER0_bp 0 /* Channel selector bit 0 position. */ +#define EVSYS_USER1_bm (1<<1) /* Channel selector bit 1 mask. */ +#define EVSYS_USER1_bp 1 /* Channel selector bit 1 position. */ +#define EVSYS_USER2_bm (1<<2) /* Channel selector bit 2 mask. */ +#define EVSYS_USER2_bp 2 /* Channel selector bit 2 position. */ +#define EVSYS_USER3_bm (1<<3) /* Channel selector bit 3 mask. */ +#define EVSYS_USER3_bp 3 /* Channel selector bit 3 position. */ +#define EVSYS_USER4_bm (1<<4) /* Channel selector bit 4 mask. */ +#define EVSYS_USER4_bp 4 /* Channel selector bit 4 position. */ +#define EVSYS_USER5_bm (1<<5) /* Channel selector bit 5 mask. */ +#define EVSYS_USER5_bp 5 /* Channel selector bit 5 position. */ +#define EVSYS_USER6_bm (1<<6) /* Channel selector bit 6 mask. */ +#define EVSYS_USER6_bp 6 /* Channel selector bit 6 position. */ +#define EVSYS_USER7_bm (1<<7) /* Channel selector bit 7 mask. */ +#define EVSYS_USER7_bp 7 /* Channel selector bit 7 position. */ + +/* EVSYS.USERCCLLUT0B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT1A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT1B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT2A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT2B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT3A bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERCCLLUT3B bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERADC0START bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USEREVSYSEVOUTC bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART0IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERUSART1IRDA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA0CNTA bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCA0CNTB bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB0CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB0COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB1CAPT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* EVSYS.USERTCB1COUNT bit masks and bit positions */ +/* EVSYS_USER is already defined. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMBIST - BIST in the NVMCTRL module */ +/* NVMBIST.CTRLA bit masks and bit positions */ +#define NVMBIST_CMD_gm 0x07 /* Command group mask. */ +#define NVMBIST_CMD_gp 0 /* Command group position. */ +#define NVMBIST_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMBIST_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMBIST_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMBIST_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMBIST_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMBIST_CMD2_bp 2 /* Command bit 2 position. */ +#define NVMBIST_SAF_bm 0x08 /* Stop at fault bit mask. */ +#define NVMBIST_SAF_bp 3 /* Stop at fault bit position. */ + +/* NVMBIST.ADDRPAT bit masks and bit positions */ +#define NVMBIST_XMODE_gm 0x03 /* X address mode group mask. */ +#define NVMBIST_XMODE_gp 0 /* X address mode group position. */ +#define NVMBIST_XMODE0_bm (1<<0) /* X address mode bit 0 mask. */ +#define NVMBIST_XMODE0_bp 0 /* X address mode bit 0 position. */ +#define NVMBIST_XMODE1_bm (1<<1) /* X address mode bit 1 mask. */ +#define NVMBIST_XMODE1_bp 1 /* X address mode bit 1 position. */ +#define NVMBIST_YMODE_gm 0x0C /* Y address mode group mask. */ +#define NVMBIST_YMODE_gp 2 /* Y address mode group position. */ +#define NVMBIST_YMODE0_bm (1<<2) /* Y address mode bit 0 mask. */ +#define NVMBIST_YMODE0_bp 2 /* Y address mode bit 0 position. */ +#define NVMBIST_YMODE1_bm (1<<3) /* Y address mode bit 1 mask. */ +#define NVMBIST_YMODE1_bp 3 /* Y address mode bit 1 position. */ +#define NVMBIST_AMODE_gm 0x70 /* Address mode group mask. */ +#define NVMBIST_AMODE_gp 4 /* Address mode group position. */ +#define NVMBIST_AMODE0_bm (1<<4) /* Address mode bit 0 mask. */ +#define NVMBIST_AMODE0_bp 4 /* Address mode bit 0 position. */ +#define NVMBIST_AMODE1_bm (1<<5) /* Address mode bit 1 mask. */ +#define NVMBIST_AMODE1_bp 5 /* Address mode bit 1 position. */ +#define NVMBIST_AMODE2_bm (1<<6) /* Address mode bit 2 mask. */ +#define NVMBIST_AMODE2_bp 6 /* Address mode bit 2 position. */ + +/* NVMBIST.DATAPAT bit masks and bit positions */ +#define NVMBIST_PATTERN_gm 0x03 /* Data check pattern group mask. */ +#define NVMBIST_PATTERN_gp 0 /* Data check pattern group position. */ +#define NVMBIST_PATTERN0_bm (1<<0) /* Data check pattern bit 0 mask. */ +#define NVMBIST_PATTERN0_bp 0 /* Data check pattern bit 0 position. */ +#define NVMBIST_PATTERN1_bm (1<<1) /* Data check pattern bit 1 mask. */ +#define NVMBIST_PATTERN1_bp 1 /* Data check pattern bit 1 position. */ + +/* NVMBIST.STATUS bit masks and bit positions */ +#define NVMBIST_STATE_gm 0x0F /* FSM State group mask. */ +#define NVMBIST_STATE_gp 0 /* FSM State group position. */ +#define NVMBIST_STATE0_bm (1<<0) /* FSM State bit 0 mask. */ +#define NVMBIST_STATE0_bp 0 /* FSM State bit 0 position. */ +#define NVMBIST_STATE1_bm (1<<1) /* FSM State bit 1 mask. */ +#define NVMBIST_STATE1_bp 1 /* FSM State bit 1 position. */ +#define NVMBIST_STATE2_bm (1<<2) /* FSM State bit 2 mask. */ +#define NVMBIST_STATE2_bp 2 /* FSM State bit 2 position. */ +#define NVMBIST_STATE3_bm (1<<3) /* FSM State bit 3 mask. */ +#define NVMBIST_STATE3_bp 3 /* FSM State bit 3 position. */ + +/* NVMBIST.CNT bit masks and bit positions */ +#define NVMBIST_CNT_gm 0x7FF /* Faults counter group mask. */ +#define NVMBIST_CNT_gp 0 /* Faults counter group position. */ +#define NVMBIST_CNT0_bm (1<<0) /* Faults counter bit 0 mask. */ +#define NVMBIST_CNT0_bp 0 /* Faults counter bit 0 position. */ +#define NVMBIST_CNT1_bm (1<<1) /* Faults counter bit 1 mask. */ +#define NVMBIST_CNT1_bp 1 /* Faults counter bit 1 position. */ +#define NVMBIST_CNT2_bm (1<<2) /* Faults counter bit 2 mask. */ +#define NVMBIST_CNT2_bp 2 /* Faults counter bit 2 position. */ +#define NVMBIST_CNT3_bm (1<<3) /* Faults counter bit 3 mask. */ +#define NVMBIST_CNT3_bp 3 /* Faults counter bit 3 position. */ +#define NVMBIST_CNT4_bm (1<<4) /* Faults counter bit 4 mask. */ +#define NVMBIST_CNT4_bp 4 /* Faults counter bit 4 position. */ +#define NVMBIST_CNT5_bm (1<<5) /* Faults counter bit 5 mask. */ +#define NVMBIST_CNT5_bp 5 /* Faults counter bit 5 position. */ +#define NVMBIST_CNT6_bm (1<<6) /* Faults counter bit 6 mask. */ +#define NVMBIST_CNT6_bp 6 /* Faults counter bit 6 position. */ +#define NVMBIST_CNT7_bm (1<<7) /* Faults counter bit 7 mask. */ +#define NVMBIST_CNT7_bp 7 /* Faults counter bit 7 position. */ +#define NVMBIST_CNT8_bm (1<<8) /* Faults counter bit 8 mask. */ +#define NVMBIST_CNT8_bp 8 /* Faults counter bit 8 position. */ +#define NVMBIST_CNT9_bm (1<<9) /* Faults counter bit 9 mask. */ +#define NVMBIST_CNT9_bp 9 /* Faults counter bit 9 position. */ +#define NVMBIST_CNT10_bm (1<<10) /* Faults counter bit 10 mask. */ +#define NVMBIST_CNT10_bp 10 /* Faults counter bit 10 position. */ + +/* NVMBIST.END bit masks and bit positions */ +#define NVMBIST_END_gm 0xFFFFFF /* group mask. */ +#define NVMBIST_END_gp 0 /* group position. */ +#define NVMBIST_END0_bm (1<<0) /* bit 0 mask. */ +#define NVMBIST_END0_bp 0 /* bit 0 position. */ +#define NVMBIST_END1_bm (1<<1) /* bit 1 mask. */ +#define NVMBIST_END1_bp 1 /* bit 1 position. */ +#define NVMBIST_END2_bm (1<<2) /* bit 2 mask. */ +#define NVMBIST_END2_bp 2 /* bit 2 position. */ +#define NVMBIST_END3_bm (1<<3) /* bit 3 mask. */ +#define NVMBIST_END3_bp 3 /* bit 3 position. */ +#define NVMBIST_END4_bm (1<<4) /* bit 4 mask. */ +#define NVMBIST_END4_bp 4 /* bit 4 position. */ +#define NVMBIST_END5_bm (1<<5) /* bit 5 mask. */ +#define NVMBIST_END5_bp 5 /* bit 5 position. */ +#define NVMBIST_END6_bm (1<<6) /* bit 6 mask. */ +#define NVMBIST_END6_bp 6 /* bit 6 position. */ +#define NVMBIST_END7_bm (1<<7) /* bit 7 mask. */ +#define NVMBIST_END7_bp 7 /* bit 7 position. */ +#define NVMBIST_END8_bm (1<<8) /* bit 8 mask. */ +#define NVMBIST_END8_bp 8 /* bit 8 position. */ +#define NVMBIST_END9_bm (1<<9) /* bit 9 mask. */ +#define NVMBIST_END9_bp 9 /* bit 9 position. */ +#define NVMBIST_END10_bm (1<<10) /* bit 10 mask. */ +#define NVMBIST_END10_bp 10 /* bit 10 position. */ +#define NVMBIST_END11_bm (1<<11) /* bit 11 mask. */ +#define NVMBIST_END11_bp 11 /* bit 11 position. */ +#define NVMBIST_END12_bm (1<<12) /* bit 12 mask. */ +#define NVMBIST_END12_bp 12 /* bit 12 position. */ +#define NVMBIST_END13_bm (1<<13) /* bit 13 mask. */ +#define NVMBIST_END13_bp 13 /* bit 13 position. */ +#define NVMBIST_END14_bm (1<<14) /* bit 14 mask. */ +#define NVMBIST_END14_bp 14 /* bit 14 position. */ +#define NVMBIST_END15_bm (1<<15) /* bit 15 mask. */ +#define NVMBIST_END15_bp 15 /* bit 15 position. */ +#define NVMBIST_END16_bm (1<<16) /* bit 16 mask. */ +#define NVMBIST_END16_bp 16 /* bit 16 position. */ +#define NVMBIST_END17_bm (1<<17) /* bit 17 mask. */ +#define NVMBIST_END17_bp 17 /* bit 17 position. */ +#define NVMBIST_END18_bm (1<<18) /* bit 18 mask. */ +#define NVMBIST_END18_bp 18 /* bit 18 position. */ +#define NVMBIST_END19_bm (1<<19) /* bit 19 mask. */ +#define NVMBIST_END19_bp 19 /* bit 19 position. */ +#define NVMBIST_END20_bm (1<<20) /* bit 20 mask. */ +#define NVMBIST_END20_bp 20 /* bit 20 position. */ +#define NVMBIST_END21_bm (1<<21) /* bit 21 mask. */ +#define NVMBIST_END21_bp 21 /* bit 21 position. */ +#define NVMBIST_END22_bm (1<<22) /* bit 22 mask. */ +#define NVMBIST_END22_bp 22 /* bit 22 position. */ +#define NVMBIST_END23_bm (1<<23) /* bit 23 mask. */ +#define NVMBIST_END23_bp 23 /* bit 23 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PORTCTRL bit masks and bit positions */ +#define PORT_SRL_bm 0x01 /* Slew Rate Limit Enable bit mask. */ +#define PORT_SRL_bp 0 /* Slew Rate Limit Enable bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.EVSYSROUTEA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_EVOUT3_bm 0x08 /* Event Output 3 bit mask. */ +#define PORTMUX_EVOUT3_bp 3 /* Event Output 3 bit position. */ +#define PORTMUX_EVOUT4_bm 0x10 /* Event Output 4 bit mask. */ +#define PORTMUX_EVOUT4_bp 4 /* Event Output 4 bit position. */ +#define PORTMUX_EVOUT5_bm 0x20 /* Event Output 5 bit mask. */ +#define PORTMUX_EVOUT5_bp 5 /* Event Output 5 bit position. */ + +/* PORTMUX.CCLROUTEA bit masks and bit positions */ +#define PORTMUX_LUT0_bm 0x01 /* CCL LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 0 /* CCL LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x02 /* CCL LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 1 /* CCL LUT1 bit position. */ +#define PORTMUX_LUT2_bm 0x04 /* CCL LUT2 bit mask. */ +#define PORTMUX_LUT2_bp 2 /* CCL LUT2 bit position. */ +#define PORTMUX_LUT3_bm 0x08 /* CCL LUT3 bit mask. */ +#define PORTMUX_LUT3_bp 3 /* CCL LUT3 bit position. */ + +/* PORTMUX.USARTROUTEA bit masks and bit positions */ +#define PORTMUX_USART0_gm 0x03 /* Port Multiplexer USART0 group mask. */ +#define PORTMUX_USART0_gp 0 /* Port Multiplexer USART0 group position. */ +#define PORTMUX_USART00_bm (1<<0) /* Port Multiplexer USART0 bit 0 mask. */ +#define PORTMUX_USART00_bp 0 /* Port Multiplexer USART0 bit 0 position. */ +#define PORTMUX_USART01_bm (1<<1) /* Port Multiplexer USART0 bit 1 mask. */ +#define PORTMUX_USART01_bp 1 /* Port Multiplexer USART0 bit 1 position. */ +#define PORTMUX_USART1_gm 0x0C /* Port Multiplexer USART1 group mask. */ +#define PORTMUX_USART1_gp 2 /* Port Multiplexer USART1 group position. */ +#define PORTMUX_USART10_bm (1<<2) /* Port Multiplexer USART1 bit 0 mask. */ +#define PORTMUX_USART10_bp 2 /* Port Multiplexer USART1 bit 0 position. */ +#define PORTMUX_USART11_bm (1<<3) /* Port Multiplexer USART1 bit 1 mask. */ +#define PORTMUX_USART11_bp 3 /* Port Multiplexer USART1 bit 1 position. */ + +/* PORTMUX.SPIROUTEA bit masks and bit positions */ +#define PORTMUX_SPI0_gm 0x03 /* Port Multiplexer SPI0 group mask. */ +#define PORTMUX_SPI0_gp 0 /* Port Multiplexer SPI0 group position. */ +#define PORTMUX_SPI00_bm (1<<0) /* Port Multiplexer SPI0 bit 0 mask. */ +#define PORTMUX_SPI00_bp 0 /* Port Multiplexer SPI0 bit 0 position. */ +#define PORTMUX_SPI01_bm (1<<1) /* Port Multiplexer SPI0 bit 1 mask. */ +#define PORTMUX_SPI01_bp 1 /* Port Multiplexer SPI0 bit 1 position. */ +#define PORTMUX_TWI0_gm 0x30 /* Port Multiplexer TWI0 group mask. */ +#define PORTMUX_TWI0_gp 4 /* Port Multiplexer TWI0 group position. */ +#define PORTMUX_TWI00_bm (1<<4) /* Port Multiplexer TWI0 bit 0 mask. */ +#define PORTMUX_TWI00_bp 4 /* Port Multiplexer TWI0 bit 0 position. */ +#define PORTMUX_TWI01_bm (1<<5) /* Port Multiplexer TWI0 bit 1 mask. */ +#define PORTMUX_TWI01_bp 5 /* Port Multiplexer TWI0 bit 1 position. */ + +/* PORTMUX.TCAROUTEA bit masks and bit positions */ +#define PORTMUX_TCA0_gm 0x07 /* Port Multiplexer TCA0 group mask. */ +#define PORTMUX_TCA0_gp 0 /* Port Multiplexer TCA0 group position. */ +#define PORTMUX_TCA00_bm (1<<0) /* Port Multiplexer TCA0 bit 0 mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 bit 0 position. */ +#define PORTMUX_TCA01_bm (1<<1) /* Port Multiplexer TCA0 bit 1 mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 bit 1 position. */ +#define PORTMUX_TCA02_bm (1<<2) /* Port Multiplexer TCA0 bit 2 mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 bit 2 position. */ + +/* PORTMUX.TCBROUTEA bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ +#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ +#define PORTMUX_TCB2_bm 0x04 /* Port Multiplexer TCB2 bit mask. */ +#define PORTMUX_TCB2_bp 2 /* Port Multiplexer TCB2 bit position. */ +#define PORTMUX_TCB3_bm 0x08 /* Port Multiplexer TCB3 bit mask. */ +#define PORTMUX_TCB3_bp 3 /* Port Multiplexer TCB3 bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_CORREN_bm 0x04 /* Correction enable bit mask. */ +#define RTC_CORREN_bp 2 /* Correction enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_ERROR_gm 0x7F /* Error Correction Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Correction Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Correction Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Correction Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Correction Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Correction Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Correction Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Correction Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Correction Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Correction Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Correction Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Correction Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Correction Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Correction Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Correction Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Correction Value bit 6 position. */ +#define RTC_SIGN_bm 0x80 /* Error Correction Sign Bit bit mask. */ +#define RTC_SIGN_bp 7 /* Error Correction Sign Bit bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Mode Wait for Receive bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Mode Wait for Receive bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + + +/* SYSCFG.OCDMS bit masks and bit positions */ +#define SYSCFG_OCDMR_bm 0x01 /* OCD Message Read bit mask. */ +#define SYSCFG_OCDMR_bp 0 /* OCD Message Read bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ +#define TCA_SINGLE_RUNSTDBY_bm 0x80 /* Run in Standby bit mask. */ +#define TCA_SINGLE_RUNSTDBY_bp 7 /* Run in Standby bit position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTAEI_bm 0x01 /* Count on Event Input A bit mask. */ +#define TCA_SINGLE_CNTAEI_bp 0 /* Count on Event Input A bit position. */ +#define TCA_SINGLE_EVACTA_gm 0x0E /* Event Action A group mask. */ +#define TCA_SINGLE_EVACTA_gp 1 /* Event Action A group position. */ +#define TCA_SINGLE_EVACTA0_bm (1<<1) /* Event Action A bit 0 mask. */ +#define TCA_SINGLE_EVACTA0_bp 1 /* Event Action A bit 0 position. */ +#define TCA_SINGLE_EVACTA1_bm (1<<2) /* Event Action A bit 1 mask. */ +#define TCA_SINGLE_EVACTA1_bp 2 /* Event Action A bit 1 position. */ +#define TCA_SINGLE_EVACTA2_bm (1<<3) /* Event Action A bit 2 mask. */ +#define TCA_SINGLE_EVACTA2_bp 3 /* Event Action A bit 2 position. */ +#define TCA_SINGLE_CNTBEI_bm 0x10 /* Count on Event Input B bit mask. */ +#define TCA_SINGLE_CNTBEI_bp 4 /* Count on Event Input B bit position. */ +#define TCA_SINGLE_EVACTB_gm 0xE0 /* Event Action B group mask. */ +#define TCA_SINGLE_EVACTB_gp 5 /* Event Action B group position. */ +#define TCA_SINGLE_EVACTB0_bm (1<<5) /* Event Action B bit 0 mask. */ +#define TCA_SINGLE_EVACTB0_bp 5 /* Event Action B bit 0 position. */ +#define TCA_SINGLE_EVACTB1_bm (1<<6) /* Event Action B bit 1 mask. */ +#define TCA_SINGLE_EVACTB1_bp 6 /* Event Action B bit 1 position. */ +#define TCA_SINGLE_EVACTB2_bm (1<<7) /* Event Action B bit 2 mask. */ +#define TCA_SINGLE_EVACTB2_bp 7 /* Event Action B bit 2 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ +#define TCA_SPLIT_RUNSTDBY_bm 0x80 /* Run in Standby bit mask. */ +#define TCA_SPLIT_RUNSTDBY_bp 7 /* Run in Standby bit position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TCA_SPLIT_CMDEN_gp 0 /* Command Enable group position. */ +#define TCA_SPLIT_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TCA_SPLIT_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TCA_SPLIT_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TCA_SPLIT_CMDEN1_bp 1 /* Command Enable bit 1 position. */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMDEN is already defined. */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x0E /* TCB Clock group mask. */ +#define TCB_CLKSEL_gp 1 /* TCB Clock group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* TCB Clock bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* TCB Clock bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* TCB Clock bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* TCB Clock bit 1 position. */ +#define TCB_CLKSEL2_bm (1<<3) /* TCB Clock bit 2 mask. */ +#define TCB_CLKSEL2_bp 3 /* TCB Clock bit 2 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_CASCADE_bm 0x20 /* Cascade two timers bit mask. */ +#define TCB_CASCADE_bp 5 /* Cascade two timers bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ +#define TCB_OVF_bm 0x02 /* Overflow bit mask. */ +#define TCB_OVF_bp 1 /* Overflow bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ +/* TCB_OVF is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Permissive Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Permissive Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_bm 0x01 /* RS485 Mode internal transmitter bit mask. */ +#define USART_RS485_bp 0 /* RS485 Mode internal transmitter bit position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.CTRLD bit masks and bit positions */ +#define USART_ABW_gm 0xC0 /* Auto Baud Window group mask. */ +#define USART_ABW_gp 6 /* Auto Baud Window group position. */ +#define USART_ABW0_bm (1<<6) /* Auto Baud Window bit 0 mask. */ +#define USART_ABW0_bp 6 /* Auto Baud Window bit 0 position. */ +#define USART_ABW1_bm (1<<7) /* Auto Baud Window bit 1 mask. */ +#define USART_ABW1_bp 7 /* Auto Baud Window bit 1 position. */ + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_AC0REFSEL_gm 0x07 /* AC0 reference select group mask. */ +#define VREF_AC0REFSEL_gp 0 /* AC0 reference select group position. */ +#define VREF_AC0REFSEL0_bm (1<<0) /* AC0 reference select bit 0 mask. */ +#define VREF_AC0REFSEL0_bp 0 /* AC0 reference select bit 0 position. */ +#define VREF_AC0REFSEL1_bm (1<<1) /* AC0 reference select bit 1 mask. */ +#define VREF_AC0REFSEL1_bp 1 /* AC0 reference select bit 1 position. */ +#define VREF_AC0REFSEL2_bm (1<<2) /* AC0 reference select bit 2 mask. */ +#define VREF_AC0REFSEL2_bp 2 /* AC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_AC0REFEN_bm 0x01 /* AC0 DACREF reference enable bit mask. */ +#define VREF_AC0REFEN_bp 0 /* AC0 DACREF reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ +#define VREF_NVMREFEN_bm 0x04 /* NVM reference enable bit mask. */ +#define VREF_NVMREFEN_bp 2 /* NVM reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 3 +#define RTC_CNT_vect _VECTOR(3) /* */ +#define RTC_PIT_vect_num 4 +#define RTC_PIT_vect _VECTOR(4) /* */ + +/* CCL interrupt vectors */ +#define CCL_CCL_vect_num 5 +#define CCL_CCL_vect _VECTOR(5) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 6 +#define PORTA_PORT_vect _VECTOR(6) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 7 +#define PORTB_PORT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 14 +#define TWI0_TWIS_vect _VECTOR(14) /* */ +#define TWI0_TWIM_vect_num 15 +#define TWI0_TWIM_vect _VECTOR(15) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 16 +#define SPI0_INT_vect _VECTOR(16) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 17 +#define USART0_RXC_vect _VECTOR(17) /* */ +#define USART0_DRE_vect_num 18 +#define USART0_DRE_vect _VECTOR(18) /* */ +#define USART0_TXC_vect_num 19 +#define USART0_TXC_vect _VECTOR(19) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 20 +#define AC0_AC_vect _VECTOR(20) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_ERROR_vect_num 21 +#define ADC0_ERROR_vect _VECTOR(21) /* */ +#define ADC0_RESRDY_vect_num 22 +#define ADC0_RESRDY_vect _VECTOR(22) /* */ +#define ADC0_SAMPRDY_vect_num 23 +#define ADC0_SAMPRDY_vect _VECTOR(23) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 24 +#define PORTC_PORT_vect _VECTOR(24) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 25 +#define TCB1_INT_vect _VECTOR(25) /* */ + +/* USART1 interrupt vectors */ +#define USART1_RXC_vect_num 26 +#define USART1_RXC_vect _VECTOR(26) /* */ +#define USART1_DRE_vect_num 27 +#define USART1_DRE_vect _VECTOR(27) /* */ +#define USART1_TXC_vect_num 28 +#define USART1_TXC_vect _VECTOR(28) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 29 +#define NVMCTRL_EE_vect _VECTOR(29) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (30 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (49152) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (49152U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3800) +# define INTERNAL_SRAM_SIZE (2048) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3800U) +# define INTERNAL_SRAM_SIZE (2048U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (16384) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (16384U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (16384) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (16384U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x28 + + +#endif /* #ifdef _AVR_ATTINY1627_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn1634.h b/hardware/tools/avr/avr/include/avr/iotn1634.h new file mode 100644 index 0000000000000000000000000000000000000000..b0ca5b5c8183bc0aceb3075290077cb94a2e926a --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn1634.h @@ -0,0 +1,914 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_ATTINY1634_H_INCLUDED +#define _AVR_ATTINY1634_H_INCLUDED + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn1634.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +/* Combine ADCL and ADCH */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x00) +#endif +#define ADCW _SFR_IO16(0x00) + +#define ADCL _SFR_IO8(0x00) +#define ADCH _SFR_IO8(0x01) + +#define ADCSRB _SFR_IO8(0x02) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 +#define ADLAR 3 +#define VDPD 6 +#define VDEN 7 + +#define ADCSRA _SFR_IO8(0x03) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +#define ADMUX _SFR_IO8(0x04) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define ADC0EN 4 +#define REFEN 5 +#define REFS0 6 +#define REFS1 7 + +#define ACSRB _SFR_IO8(0x05) +#define ACIRS0 0 +#define ACIRS1 1 +#define ACME 2 +#define ACCE 3 +#define ACLP 5 +#define HLEV 6 +#define HSEL 7 + +#define ACSRA _SFR_IO8(0x06) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define PINC _SFR_IO8(0x07) +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x08) +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x09) +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PUEC _SFR_IO8(0x0A) +#define PUEC0 0 +#define PUEC1 1 +#define PUEC2 2 +#define PUEC3 3 +#define PUEC4 4 +#define PUEC5 5 + +#define PINB _SFR_IO8(0x0B) +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x0C) +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x0D) +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PUEB _SFR_IO8(0x0E) +#define PUEB0 0 +#define PUEB1 1 +#define PUEB2 2 +#define PUEB3 3 + +#define PINA _SFR_IO8(0x0F) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x10) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x11) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PUEA _SFR_IO8(0x12) +#define PUEA0 0 +#define PUEA1 1 +#define PUEA2 2 +#define PUEA3 3 +#define PUEA4 4 +#define PUEA5 5 +#define PUEA6 6 +#define PUEA7 7 + +#define PORTCR _SFR_IO8(0x13) +#define BBMB 1 +#define BBMC 2 +#define BBMA 0 + +#define GPIOR0 _SFR_IO8(0x14) + +#define GPIOR1 _SFR_IO8(0x15) + +#define GPIOR2 _SFR_IO8(0x16) + +#define OCR0B _SFR_IO8(0x17) + +#define OCR0A _SFR_IO8(0x18) + +#define TCNT0 _SFR_IO8(0x19) + +#define TCCR0B _SFR_IO8(0x1A) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCCR0A _SFR_IO8(0x1B) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x1D) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x1E) + +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +#define UDR0 _SFR_IO8(0x20) + +/* Combine UBRR0L and UBRR0H */ +#define UBRR0 _SFR_IO16(0x21) + +#define UBRR0L _SFR_IO8(0x21) +#define UBRR0H _SFR_IO8(0x22) + +#define UCSR0D _SFR_IO8(0x23) +#define SFDE0 5 +#define RXS0 6 +#define RXSIE0 7 + +#define UCSR0C _SFR_IO8(0x24) +#define UCPOL0 0 +#define UCSZ00 1 +#define UCSZ01 2 +#define USBS0 3 +#define UPM00 4 +#define UPM01 5 +#define UMSEL00 6 +#define UMSEL01 7 + +#define UCSR0B _SFR_IO8(0x25) +#define TXB80 0 +#define RXB80 1 +#define UCSZ02 2 +#define TXEN0 3 +#define RXEN0 4 +#define UDRIE0 5 +#define TXCIE0 6 +#define RXCIE0 7 + +#define UCSR0A _SFR_IO8(0x26) +#define MPCM0 0 +#define U2X0 1 +#define UPE0 2 +#define DOR0 3 +#define FE0 4 +#define UDRE0 5 +#define TXC0 6 +#define RXC0 7 + +#define PCMSK0 _SFR_IO8(0x27) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 +#define PCINT4 4 +#define PCINT5 5 +#define PCINT6 6 +#define PCINT7 7 + +#define PCMSK1 _SFR_IO8(0x28) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 +#define PCINT11 3 + +#define PCMSK2 _SFR_IO8(0x29) +#define PCINT12 0 +#define PCINT13 1 +#define PCINT14 2 +#define PCINT15 3 +#define PCINT16 4 +#define PCINT17 5 + +#define USICR _SFR_IO8(0x2A) +#define USITC 0 +#define USICLK 1 +#define USICS0 2 +#define USICS1 3 +#define USIWM0 4 +#define USIWM1 5 +#define USIOIE 6 +#define USISIE 7 + +#define USISR _SFR_IO8(0x2B) +#define USICNT0 0 +#define USICNT1 1 +#define USICNT2 2 +#define USICNT3 3 +#define USIDC 4 +#define USIPF 5 +#define USIOIF 6 +#define USISIF 7 + +#define USIDR _SFR_IO8(0x2C) + +#define USIBR _SFR_IO8(0x2D) + +/* Reserved [0x2E] */ + +#define CCP _SFR_IO8(0x2F) + +#define WDTCSR _SFR_IO8(0x30) +#define WDE 3 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +/* Reserved [0x31] */ + +#define CLKSR _SFR_IO8(0x32) +#define CKSEL0 0 +#define CKSEL1 1 +#define CKSEL2 2 +#define CKSEL3 3 +#define SUT 4 +#define CKOUT_IO 5 +#define CSTR 6 +#define OSCRDY 7 + +#define CLKPR _SFR_IO8(0x33) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 + +#define PRR _SFR_IO8(0x34) +#define PRADC 0 +#define PRUSART0 1 +#define PRUSART1 2 +#define PRUSI 3 +#define PRTIM0 4 +#define PRTIM1 5 +#define PRTWI 6 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn167.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_IOTN167_H_ +#define _AVR_IOTN167_H_ 1 + + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 +#define PINA4 4 +#define PINA5 5 +#define PINA6 6 +#define PINA7 7 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 +#define PORTA4 4 +#define PORTA5 5 +#define PORTA6 6 +#define PORTA7 7 + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PORTCR _SFR_IO8(0x12) +#define PUDA 0 +#define PUDB 1 +#define BBMA 4 +#define BBMB 5 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 + +#define GTCCR _SFR_IO8(0x23) +#define PSR1 0 +#define PSR0 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x25) +#define WGM00 0 +#define WGM01 1 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x26) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x27) +#define TCNT00 0 +#define TCNT01 1 +#define TCNT02 2 +#define TCNT03 3 +#define TCNT04 4 +#define TCNT05 5 +#define TCNT06 6 +#define TCNT07 7 + +#define OCR0A _SFR_IO8(0x28) +#define OCR00 0 +#define OCR01 1 +#define OCR02 2 +#define OCR03 3 +#define OCR04 4 +#define OCR05 5 +#define OCR06 6 +#define OCR07 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACIRS 6 +#define ACD 7 + +#define DWDR _SFR_IO8(0x31) +#define DWDR0 0 +#define DWDR1 1 +#define DWDR2 2 +#define DWDR3 3 +#define DWDR4 4 +#define DWDR5 5 +#define DWDR6 6 +#define DWDR7 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define SIGRD 5 +#define RWWSB 6 + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define CLKCSR _SFR_MEM8(0x62) +#define CLKC0 0 +#define CLKC1 1 +#define CLKC2 2 +#define CLKC3 3 +#define CLKRDY 4 +#define CLKCCE 7 + +#define CLKSELR _SFR_MEM8(0x63) +#define CSEL0 0 +#define CSEL1 1 +#define CSEL2 2 +#define CSEL3 3 +#define CSUT0 4 +#define CSUT1 5 +#define COUT 6 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 +#define PRSPI 4 +#define PRLIN 5 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn20.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATtiny20_H_ +#define _AVR_ATtiny20_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINA _SFR_IO8(0x00) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 +#define PINA4 4 +#define PINA5 5 +#define PINA6 6 +#define PINA7 7 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 +#define PORTA4 4 +#define PORTA5 5 +#define PORTA6 6 +#define PORTA7 7 + +#define PUEA _SFR_IO8(0x03) +#define PUEA0 0 +#define PUEA1 1 +#define PUEA2 2 +#define PUEA3 3 +#define PUEA4 4 +#define PUEA5 5 +#define PUEA6 6 +#define PUEA7 7 + +#define PINB _SFR_IO8(0x04) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 + +#define DDRB _SFR_IO8(0x05) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 + +#define PORTB _SFR_IO8(0x06) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 + +#define PUEB _SFR_IO8(0x07) +#define PUEB0 0 +#define PUEB1 1 +#define PUEB2 2 +#define PUEB3 3 + +#define PORTCR _SFR_IO8(0x08) +#define BBMA 0 +#define BBMB 1 + +#define PCMSK0 _SFR_IO8(0x09) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 +#define PCINT4 4 +#define PCINT5 5 +#define PCINT6 6 +#define PCINT7 7 + +#define PCMSK1 _SFR_IO8(0x0A) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 +#define PCINT11 3 + +#define GIFR _SFR_IO8(0x0B) +#define INTF0 0 +#define PCIF0 4 +#define PCIF1 5 + +#define GIMSK _SFR_IO8(0x0C) +#define INT0 0 +#define PCIE0 4 +#define PCIE1 5 + +#define DIDR0 _SFR_IO8(0x0D) +#define ADC0D 0 +#define ADC1D 1 +#define ADC2D 2 +#define ADC3D 3 +#define ADC4D 4 +#define ADC5D 5 +#define ADC6D 6 +#define ADC7D 7 + +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x0E) +#endif +#define ADCW _SFR_IO16(0x0E) + +#define ADCL _SFR_IO8(0x0E) +#define ADCL0 0 +#define ADCL1 1 +#define ADCL2 2 +#define ADCL3 3 +#define ADCL4 4 +#define ADCL5 5 +#define ADCL6 6 +#define ADCL7 7 + +#define ADCH _SFR_IO8(0x0F) +#define ADCH0 0 +#define ADCH1 1 +#define ADCH2 2 +#define ADCH3 3 +#define ADCH4 4 +#define ADCH5 5 +#define ADCH6 6 +#define ADCH7 7 + +#define ADMUX _SFR_IO8(0x10) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define REFS 6 + +#define ADCSRB _SFR_IO8(0x11) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 +#define ADLAR 3 + +#define ADCSRA _SFR_IO8(0x12) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +#define ACSRB _SFR_IO8(0x13) +#define ACME 2 +#define HLEV 6 +#define HSEL 7 + +#define ACSRA _SFR_IO8(0x14) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCR0B _SFR_IO8(0x15) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define OCR0A _SFR_IO8(0x16) +#define OCR0_0 0 +#define OCR0_1 1 +#define OCR0_2 2 +#define OCR0_3 3 +#define OCR0_4 4 +#define OCR0_5 5 +#define OCR0_6 6 +#define OCR0_7 7 + +#define TCNT0 _SFR_IO8(0x17) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define TCCR0B _SFR_IO8(0x18) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCCR0A _SFR_IO8(0x19) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define ICR1 _SFR_IO16(0x1A) + +#define ICR1L _SFR_IO8(0x1A) +#define ICR1_0 0 +#define ICR1_1 1 +#define ICR1_2 2 +#define ICR1_3 3 +#define ICR1_4 4 +#define ICR1_5 5 +#define ICR1_6 6 +#define ICR1_7 7 + +#define ICR1H _SFR_IO8(0x1B) +#define ICR1_8 0 +#define ICR1_9 1 +#define ICR1_10 2 +#define ICR1_11 3 +#define ICR1_12 4 +#define ICR1_13 5 +#define ICR1_14 6 +#define ICR1_15 7 + +#define OCR1B _SFR_IO16(0x1C) + +#define OCR1BL _SFR_IO8(0x1C) +#define OCR1B0 0 +#define OCR1B1 1 +#define OCR1B2 2 +#define OCR1B3 3 +#define OCR1B4 4 +#define OCR1B5 5 +#define OCR1B6 6 +#define OCR1B7 7 + +#define OCR1BH _SFR_IO8(0x1D) +#define OCR1B8 0 +#define OCR1B9 1 +#define OCR1B10 2 +#define OCR1B11 3 +#define OCR1B12 4 +#define OCR1B13 5 +#define OCR1B14 6 +#define OCR1B15 7 + +#define OCR1A _SFR_IO16(0x1E) + +#define OCR1AL _SFR_IO8(0x1E) +#define OCR1A0 0 +#define OCR1A1 1 +#define OCR1A2 2 +#define OCR1A3 3 +#define OCR1A4 4 +#define OCR1A5 5 +#define OCR1A6 6 +#define OCR1A7 7 + +#define OCR1AH _SFR_IO8(0x1F) +#define OCR1A8 0 +#define OCR1A9 1 +#define OCR1A10 2 +#define OCR1A11 3 +#define OCR1A12 4 +#define OCR1A13 5 +#define OCR1A14 6 +#define OCR1A15 7 + +#define TCNT1 _SFR_IO16(0x20) + +#define TCNT1L _SFR_IO8(0x20) +#define TCNT1_0 0 +#define TCNT1_1 1 +#define TCNT1_2 2 +#define TCNT1_3 3 +#define TCNT1_4 4 +#define TCNT1_5 5 +#define TCNT1_6 6 +#define TCNT1_7 7 + +#define TCNT1H _SFR_IO8(0x21) +#define TCNT1_8 0 +#define TCNT1_9 1 +#define TCNT1_10 2 +#define TCNT1_11 3 +#define TCNT1_12 4 +#define TCNT1_13 5 +#define TCNT1_14 6 +#define TCNT1_15 7 + +#define TCCR1C _SFR_IO8(0x22) +#define FOC1B 6 +#define FOC1A 7 + +#define TCCR1B _SFR_IO8(0x23) +#define CS10 0 +#define CS11 1 +#define CS12 2 +#define WGM12 3 +#define WGM13 4 +#define ICES1 6 +#define ICNC1 7 + +#define TCCR1A _SFR_IO8(0x24) +#define WGM10 0 +#define WGM11 1 +#define COM1B0 4 +#define COM1B1 5 +#define COM1A0 6 +#define COM1A1 7 + +#define TIFR _SFR_IO8(0x25) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define TOV1 3 +#define OCF1A 4 +#define OCF1B 5 +#define ICF1 7 + +#define TIMSK _SFR_IO8(0x26) +#define TOIE0 0 +#define OCIE0A 1 +#define OCIE0B 2 +#define TOIE1 3 +#define OCIE1A 4 +#define OCIE1B 5 +#define ICIE1 7 + +#define GTCCR _SFR_IO8(0x27) +#define PSR 0 +#define TSM 7 + +#define TWSD _SFR_IO8(0x28) +#define TWSD0 0 +#define TWSD1 1 +#define TWSD2 2 +#define TWSD3 3 +#define TWSD4 4 +#define TWSD5 5 +#define TWSD6 6 +#define TWSD7 7 + +#define TWSAM _SFR_IO8(0x29) +#define TWAE 0 +#define TWSAM1 1 +#define TWSAM2 2 +#define TWSAM3 3 +#define TWSAM4 4 +#define TWSAM5 5 +#define TWSAM6 6 +#define TWSAM7 7 + +#define TWSA _SFR_IO8(0x2A) +#define TWSA0 0 +#define TWSA1 1 +#define TWSA2 2 +#define TWSA3 3 +#define TWSA4 4 +#define TWSA5 5 +#define TWSA6 6 +#define TWSA7 7 + +#define TWSSRA _SFR_IO8(0x2B) +#define TWAS 0 +#define TWDIR 1 +#define TWBE 2 +#define TWC 3 +#define TWRA 4 +#define TWCH 5 +#define TWASIF 6 +#define TWDIF 7 + +#define TWSCRB _SFR_IO8(0x2C) +#define TWCMD0 0 +#define TWCMD1 1 +#define TWAA 2 + +#define TWSCRA _SFR_IO8(0x2D) +#define TWSME 0 +#define TWPME 1 +#define TWSIE 2 +#define TWEN 3 +#define TWASIE 4 +#define TWDIE 5 +#define TWSHE 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define SPSR _SFR_IO8(0x2F) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPCR _SFR_IO8(0x30) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define WDTCSR _SFR_IO8(0x31) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define NVMCSR _SFR_IO8(0x32) +#define NVMBSY 7 + +#define NVMCMD _SFR_IO8(0x33) +#define NVMCMD0 0 +#define NVMCMD1 1 +#define NVMCMD2 2 +#define NVMCMD3 3 +#define NVMCMD4 4 +#define NVMCMD5 5 + +#define QTCSR _SFR_IO8(0x34) + +#define PRR _SFR_IO8(0x35) +#define PRADC 0 +#define PRTIM0 1 +#define PRTIM1 2 +#define PRSPI 3 +#define PRTWI 4 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn202.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY202_H_INCLUDED +#define _AVR_ATTINY202_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wakeup halt */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling */ + BOD_SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[3]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[7]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t reserved_1[6]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t reserved_3[5]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 Input Selection - TCA0 */ + register8_t reserved_4[29]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 Input Selection - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ +} EVSYS_SYNCUSER0_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHz_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0670) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0670) +#define AC0_MUXCTRLA _SFR_MEM8(0x0672) +#define AC0_INTCTRL _SFR_MEM8(0x0676) +#define AC0_STATUS _SFR_MEM8(0x0677) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 Input Selection - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 Input Selection - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 16 +#define AC0_AC_vect _VECTOR(16) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 17 +#define ADC0_RESRDY_vect _VECTOR(17) /* */ +#define ADC0_WCOMP_vect_num 18 +#define ADC0_WCOMP_vect _VECTOR(18) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 19 +#define TWI0_TWIS_vect _VECTOR(19) /* */ +#define TWI0_TWIM_vect_num 20 +#define TWI0_TWIM_vect _VECTOR(20) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 21 +#define SPI0_INT_vect _VECTOR(21) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 22 +#define USART0_RXC_vect _VECTOR(22) /* */ +#define USART0_DRE_vect_num 23 +#define USART0_DRE_vect _VECTOR(23) /* */ +#define USART0_TXC_vect_num 24 +#define USART0_TXC_vect _VECTOR(24) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 25 +#define NVMCTRL_EE_vect _VECTOR(25) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (26 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (34816) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (34816U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (64) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (64U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3F80) +# define INTERNAL_SRAM_SIZE (128) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3F80U) +# define INTERNAL_SRAM_SIZE (128U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (2048) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (2048U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (2048) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (2048U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x91 +#define SIGNATURE_2 0x23 + + +#endif /* #ifdef _AVR_ATTINY202_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn204.h b/hardware/tools/avr/avr/include/avr/iotn204.h new file mode 100644 index 0000000000000000000000000000000000000000..adc0da3edf13756295ad292d8f4d5bce3e107e1e --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn204.h @@ -0,0 +1,4631 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn204.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY204_H_INCLUDED +#define _AVR_ATTINY204_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wakeup halt */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling */ + BOD_SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[3]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[7]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t reserved_1[6]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t reserved_2[7]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t reserved_3[5]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 Input Selection - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 Input Selection - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous User Ch 0 Input Selection - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 Input Selection - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHz_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0670) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0670) +#define AC0_MUXCTRLA _SFR_MEM8(0x0672) +#define AC0_INTCTRL _SFR_MEM8(0x0676) +#define AC0_STATUS _SFR_MEM8(0x0677) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 Input Selection - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 Input Selection - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 Input Selection - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 Input Selection - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 Input Selection - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 Input Selection - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 Input Selection - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 Input Selection - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 Input Selection - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 Input Selection - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 Input Selection - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 Input Selection - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 Input Selection - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 Input Selection - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 Input Selection - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 Input Selection - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 Input Selection - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 Input Selection - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 Input Selection - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 Input Selection - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 16 +#define AC0_AC_vect _VECTOR(16) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 17 +#define ADC0_RESRDY_vect _VECTOR(17) /* */ +#define ADC0_WCOMP_vect_num 18 +#define ADC0_WCOMP_vect _VECTOR(18) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 19 +#define TWI0_TWIS_vect _VECTOR(19) /* */ +#define TWI0_TWIM_vect_num 20 +#define TWI0_TWIM_vect _VECTOR(20) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 21 +#define SPI0_INT_vect _VECTOR(21) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 22 +#define USART0_RXC_vect _VECTOR(22) /* */ +#define USART0_DRE_vect_num 23 +#define USART0_DRE_vect _VECTOR(23) /* */ +#define USART0_TXC_vect_num 24 +#define USART0_TXC_vect _VECTOR(24) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 25 +#define NVMCTRL_EE_vect _VECTOR(25) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (26 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (34816) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (34816U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (64) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (64U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3F80) +# define INTERNAL_SRAM_SIZE (128) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3F80U) +# define INTERNAL_SRAM_SIZE (128U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (2048) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (2048U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (2048) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (2048U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x91 +#define SIGNATURE_2 0x22 + + +#endif /* #ifdef _AVR_ATTINY204_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn212.h b/hardware/tools/avr/avr/include/avr/iotn212.h new file mode 100644 index 0000000000000000000000000000000000000000..34970eede277836c2a685fbd417257d4d61918a4 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn212.h @@ -0,0 +1,5212 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn212.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY212_H_INCLUDED +#define _AVR_ATTINY212_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ + AC_MUXNEG_DAC_gc = (0x03<<0), /* DAC output */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wakeup halt */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling */ + BOD_SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[3]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1K cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16K cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32K cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64K cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t DATA; /* DATA Register */ + register8_t reserved_1[2]; +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t ASYNCCH2; /* Asynchronous Channel 2 Generator Selection */ + register8_t ASYNCCH3; /* Asynchronous Channel 3 Generator Selection */ + register8_t reserved_1[4]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t reserved_3[5]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 Input Selection - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 Input Selection - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous Channel 2 Generator Selection select */ +typedef enum EVSYS_ASYNCCH2_enum +{ + EVSYS_ASYNCCH2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH2_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH2_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH2_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH2_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH2_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH2_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH2_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH2_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH2_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH2_PORTC_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PC0 */ + EVSYS_ASYNCCH2_PORTC_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PC1 */ + EVSYS_ASYNCCH2_PORTC_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PC2 */ + EVSYS_ASYNCCH2_PORTC_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PC3 */ + EVSYS_ASYNCCH2_PORTC_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PC4 */ + EVSYS_ASYNCCH2_PORTC_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PC5 */ +} EVSYS_ASYNCCH2_t; + +/* Asynchronous Channel 3 Generator Selection select */ +typedef enum EVSYS_ASYNCCH3_enum +{ + EVSYS_ASYNCCH3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH3_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH3_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH3_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH3_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter type D compare B clear */ + EVSYS_ASYNCCH3_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter type D compare A set */ + EVSYS_ASYNCCH3_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter type D compare B set */ + EVSYS_ASYNCCH3_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter type D program event */ + EVSYS_ASYNCCH3_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH3_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH3_PIT_DIV8192_gc = (0x0A<<0), /* Periodic Interrupt CLK_RTC div 8192 */ + EVSYS_ASYNCCH3_PIT_DIV4096_gc = (0x0B<<0), /* Periodic Interrupt CLK_RTC div 4096 */ + EVSYS_ASYNCCH3_PIT_DIV2048_gc = (0x0C<<0), /* Periodic Interrupt CLK_RTC div 2048 */ + EVSYS_ASYNCCH3_PIT_DIV1024_gc = (0x0D<<0), /* Periodic Interrupt CLK_RTC div 1024 */ + EVSYS_ASYNCCH3_PIT_DIV512_gc = (0x0E<<0), /* Periodic Interrupt CLK_RTC div 512 */ + EVSYS_ASYNCCH3_PIT_DIV256_gc = (0x0F<<0), /* Periodic Interrupt CLK_RTC div 256 */ + EVSYS_ASYNCCH3_PIT_DIV128_gc = (0x10<<0), /* Periodic Interrupt CLK_RTC div 128 */ + EVSYS_ASYNCCH3_PIT_DIV64_gc = (0x11<<0), /* Periodic Interrupt CLK_RTC div 64 */ +} EVSYS_ASYNCCH3_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 Input Selection - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 Input Selection - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHz_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_20MHZ_gc = (0x00<<5), /* 20 MHz oscillator */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External clock */ + TCD_CLKSEL_SYSCLK_gc = (0x03<<5), /* System clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Syncronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selevted clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selevted clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selevted clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selevted clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0670) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x0680) /* Digital to Analog Converter */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0A80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_ASYNCCH2 _SFR_MEM8(0x0184) +#define EVSYS_ASYNCCH3 _SFR_MEM8(0x0185) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0670) +#define AC0_MUXCTRLA _SFR_MEM8(0x0672) +#define AC0_INTCTRL _SFR_MEM8(0x0676) +#define AC0_STATUS _SFR_MEM8(0x0677) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x0680) +#define DAC0_DATA _SFR_MEM8(0x0681) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0A80) +#define TCD0_CTRLB _SFR_MEM8(0x0A81) +#define TCD0_CTRLC _SFR_MEM8(0x0A82) +#define TCD0_CTRLD _SFR_MEM8(0x0A83) +#define TCD0_CTRLE _SFR_MEM8(0x0A84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0A88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0A89) +#define TCD0_INTCTRL _SFR_MEM8(0x0A8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0A8D) +#define TCD0_STATUS _SFR_MEM8(0x0A8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0A90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0A91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0A92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0A94) +#define TCD0_DLYVAL _SFR_MEM8(0x0A95) +#define TCD0_DITCTRL _SFR_MEM8(0x0A98) +#define TCD0_DITVAL _SFR_MEM8(0x0A99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0A9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0AA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0AA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0AA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0AA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0AA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0AA5) +#define TCD0_CMPASET _SFR_MEM16(0x0AA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0AA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0AA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0AAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0AAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0AAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0AAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0AAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0AAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0AAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0AAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0AAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH2 bit masks and bit positions */ +#define EVSYS_ASYNCCH2_gm 0xFF /* Asynchronous Channel 2 Generator Selection group mask. */ +#define EVSYS_ASYNCCH2_gp 0 /* Asynchronous Channel 2 Generator Selection group position. */ +#define EVSYS_ASYNCCH20_bm (1<<0) /* Asynchronous Channel 2 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH20_bp 0 /* Asynchronous Channel 2 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH21_bm (1<<1) /* Asynchronous Channel 2 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH21_bp 1 /* Asynchronous Channel 2 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH22_bm (1<<2) /* Asynchronous Channel 2 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH22_bp 2 /* Asynchronous Channel 2 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH23_bm (1<<3) /* Asynchronous Channel 2 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH23_bp 3 /* Asynchronous Channel 2 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH24_bm (1<<4) /* Asynchronous Channel 2 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH24_bp 4 /* Asynchronous Channel 2 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH25_bm (1<<5) /* Asynchronous Channel 2 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH25_bp 5 /* Asynchronous Channel 2 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH26_bm (1<<6) /* Asynchronous Channel 2 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH26_bp 6 /* Asynchronous Channel 2 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH27_bm (1<<7) /* Asynchronous Channel 2 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH27_bp 7 /* Asynchronous Channel 2 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH3 bit masks and bit positions */ +#define EVSYS_ASYNCCH3_gm 0xFF /* Asynchronous Channel 3 Generator Selection group mask. */ +#define EVSYS_ASYNCCH3_gp 0 /* Asynchronous Channel 3 Generator Selection group position. */ +#define EVSYS_ASYNCCH30_bm (1<<0) /* Asynchronous Channel 3 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH30_bp 0 /* Asynchronous Channel 3 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH31_bm (1<<1) /* Asynchronous Channel 3 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH31_bp 1 /* Asynchronous Channel 3 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH32_bm (1<<2) /* Asynchronous Channel 3 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH32_bp 2 /* Asynchronous Channel 3 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH33_bm (1<<3) /* Asynchronous Channel 3 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH33_bp 3 /* Asynchronous Channel 3 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH34_bm (1<<4) /* Asynchronous Channel 3 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH34_bp 4 /* Asynchronous Channel 3 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH35_bm (1<<5) /* Asynchronous Channel 3 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH35_bp 5 /* Asynchronous Channel 3 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH36_bm (1<<6) /* Asynchronous Channel 3 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH36_bp 6 /* Asynchronous Channel 3 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH37_bm (1<<7) /* Asynchronous Channel 3 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH37_bp 7 /* Asynchronous Channel 3 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 Input Selection - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 Input Selection - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 Input Selection - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 Input Selection - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 Input Selection - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 Input Selection - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 Input Selection - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 Input Selection - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 Input Selection - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 Input Selection - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 Input Selection - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 Input Selection - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 Input Selection - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 Input Selection - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 Input Selection - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 Input Selection - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 Input Selection - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 Input Selection - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 Input Selection - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 Input Selection - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Syncronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Syncronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Syncronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Syncronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Syncronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Syncronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 14 +#define TCD0_OVF_vect _VECTOR(14) /* */ +#define TCD0_TRIG_vect_num 15 +#define TCD0_TRIG_vect _VECTOR(15) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 16 +#define AC0_AC_vect _VECTOR(16) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 17 +#define ADC0_RESRDY_vect _VECTOR(17) /* */ +#define ADC0_WCOMP_vect_num 18 +#define ADC0_WCOMP_vect _VECTOR(18) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 19 +#define TWI0_TWIS_vect _VECTOR(19) /* */ +#define TWI0_TWIM_vect_num 20 +#define TWI0_TWIM_vect _VECTOR(20) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 21 +#define SPI0_INT_vect _VECTOR(21) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 22 +#define USART0_RXC_vect _VECTOR(22) /* */ +#define USART0_DRE_vect_num 23 +#define USART0_DRE_vect _VECTOR(23) /* */ +#define USART0_TXC_vect_num 24 +#define USART0_TXC_vect _VECTOR(24) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 25 +#define NVMCTRL_EE_vect _VECTOR(25) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (26 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (34816) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (34816U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (64) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (64U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3F80) +# define INTERNAL_SRAM_SIZE (128) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3F80U) +# define INTERNAL_SRAM_SIZE (128U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (2048) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (2048U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (2048) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (2048U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x91 +#define SIGNATURE_2 0x21 + + +#endif /* #ifdef _AVR_ATTINY212_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn214.h b/hardware/tools/avr/avr/include/avr/iotn214.h new file mode 100644 index 0000000000000000000000000000000000000000..7a8f82d4493828431263360546602002339d6120 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn214.h @@ -0,0 +1,5265 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn214.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY214_H_INCLUDED +#define _AVR_ATTINY214_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ + AC_MUXNEG_DAC_gc = (0x03<<0), /* DAC output */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wakeup halt */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling */ + BOD_SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[3]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1K cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16K cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32K cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t DATA; /* DATA Register */ + register8_t reserved_1[2]; +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t ASYNCCH2; /* Asynchronous Channel 2 Generator Selection */ + register8_t ASYNCCH3; /* Asynchronous Channel 3 Generator Selection */ + register8_t reserved_1[4]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t reserved_3[5]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 Input Selection - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 Input Selection - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous Channel 2 Generator Selection select */ +typedef enum EVSYS_ASYNCCH2_enum +{ + EVSYS_ASYNCCH2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH2_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH2_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH2_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH2_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH2_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH2_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH2_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH2_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH2_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH2_PORTC_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PC0 */ + EVSYS_ASYNCCH2_PORTC_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PC1 */ + EVSYS_ASYNCCH2_PORTC_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PC2 */ + EVSYS_ASYNCCH2_PORTC_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PC3 */ + EVSYS_ASYNCCH2_PORTC_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PC4 */ + EVSYS_ASYNCCH2_PORTC_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PC5 */ +} EVSYS_ASYNCCH2_t; + +/* Asynchronous Channel 3 Generator Selection select */ +typedef enum EVSYS_ASYNCCH3_enum +{ + EVSYS_ASYNCCH3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH3_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH3_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH3_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH3_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter type D compare B clear */ + EVSYS_ASYNCCH3_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter type D compare A set */ + EVSYS_ASYNCCH3_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter type D compare B set */ + EVSYS_ASYNCCH3_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter type D program event */ + EVSYS_ASYNCCH3_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH3_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH3_PIT_DIV8192_gc = (0x0A<<0), /* Periodic Interrupt CLK_RTC div 8192 */ + EVSYS_ASYNCCH3_PIT_DIV4096_gc = (0x0B<<0), /* Periodic Interrupt CLK_RTC div 4096 */ + EVSYS_ASYNCCH3_PIT_DIV2048_gc = (0x0C<<0), /* Periodic Interrupt CLK_RTC div 2048 */ + EVSYS_ASYNCCH3_PIT_DIV1024_gc = (0x0D<<0), /* Periodic Interrupt CLK_RTC div 1024 */ + EVSYS_ASYNCCH3_PIT_DIV512_gc = (0x0E<<0), /* Periodic Interrupt CLK_RTC div 512 */ + EVSYS_ASYNCCH3_PIT_DIV256_gc = (0x0F<<0), /* Periodic Interrupt CLK_RTC div 256 */ + EVSYS_ASYNCCH3_PIT_DIV128_gc = (0x10<<0), /* Periodic Interrupt CLK_RTC div 128 */ + EVSYS_ASYNCCH3_PIT_DIV64_gc = (0x11<<0), /* Periodic Interrupt CLK_RTC div 64 */ +} EVSYS_ASYNCCH3_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 Input Selection - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 Input Selection - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHz_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_20MHZ_gc = (0x00<<5), /* 20 MHz oscillator */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External clock */ + TCD_CLKSEL_SYSCLK_gc = (0x03<<5), /* System clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Syncronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selevted clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selevted clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selevted clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selevted clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0670) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x0680) /* Digital to Analog Converter */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0A80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_ASYNCCH2 _SFR_MEM8(0x0184) +#define EVSYS_ASYNCCH3 _SFR_MEM8(0x0185) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0670) +#define AC0_MUXCTRLA _SFR_MEM8(0x0672) +#define AC0_INTCTRL _SFR_MEM8(0x0676) +#define AC0_STATUS _SFR_MEM8(0x0677) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x0680) +#define DAC0_DATA _SFR_MEM8(0x0681) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0A80) +#define TCD0_CTRLB _SFR_MEM8(0x0A81) +#define TCD0_CTRLC _SFR_MEM8(0x0A82) +#define TCD0_CTRLD _SFR_MEM8(0x0A83) +#define TCD0_CTRLE _SFR_MEM8(0x0A84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0A88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0A89) +#define TCD0_INTCTRL _SFR_MEM8(0x0A8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0A8D) +#define TCD0_STATUS _SFR_MEM8(0x0A8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0A90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0A91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0A92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0A94) +#define TCD0_DLYVAL _SFR_MEM8(0x0A95) +#define TCD0_DITCTRL _SFR_MEM8(0x0A98) +#define TCD0_DITVAL _SFR_MEM8(0x0A99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0A9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0AA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0AA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0AA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0AA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0AA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0AA5) +#define TCD0_CMPASET _SFR_MEM16(0x0AA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0AA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0AA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0AAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0AAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0AAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0AAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0AAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0AAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0AAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0AAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0AAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH2 bit masks and bit positions */ +#define EVSYS_ASYNCCH2_gm 0xFF /* Asynchronous Channel 2 Generator Selection group mask. */ +#define EVSYS_ASYNCCH2_gp 0 /* Asynchronous Channel 2 Generator Selection group position. */ +#define EVSYS_ASYNCCH20_bm (1<<0) /* Asynchronous Channel 2 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH20_bp 0 /* Asynchronous Channel 2 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH21_bm (1<<1) /* Asynchronous Channel 2 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH21_bp 1 /* Asynchronous Channel 2 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH22_bm (1<<2) /* Asynchronous Channel 2 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH22_bp 2 /* Asynchronous Channel 2 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH23_bm (1<<3) /* Asynchronous Channel 2 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH23_bp 3 /* Asynchronous Channel 2 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH24_bm (1<<4) /* Asynchronous Channel 2 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH24_bp 4 /* Asynchronous Channel 2 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH25_bm (1<<5) /* Asynchronous Channel 2 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH25_bp 5 /* Asynchronous Channel 2 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH26_bm (1<<6) /* Asynchronous Channel 2 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH26_bp 6 /* Asynchronous Channel 2 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH27_bm (1<<7) /* Asynchronous Channel 2 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH27_bp 7 /* Asynchronous Channel 2 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH3 bit masks and bit positions */ +#define EVSYS_ASYNCCH3_gm 0xFF /* Asynchronous Channel 3 Generator Selection group mask. */ +#define EVSYS_ASYNCCH3_gp 0 /* Asynchronous Channel 3 Generator Selection group position. */ +#define EVSYS_ASYNCCH30_bm (1<<0) /* Asynchronous Channel 3 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH30_bp 0 /* Asynchronous Channel 3 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH31_bm (1<<1) /* Asynchronous Channel 3 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH31_bp 1 /* Asynchronous Channel 3 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH32_bm (1<<2) /* Asynchronous Channel 3 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH32_bp 2 /* Asynchronous Channel 3 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH33_bm (1<<3) /* Asynchronous Channel 3 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH33_bp 3 /* Asynchronous Channel 3 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH34_bm (1<<4) /* Asynchronous Channel 3 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH34_bp 4 /* Asynchronous Channel 3 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH35_bm (1<<5) /* Asynchronous Channel 3 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH35_bp 5 /* Asynchronous Channel 3 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH36_bm (1<<6) /* Asynchronous Channel 3 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH36_bp 6 /* Asynchronous Channel 3 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH37_bm (1<<7) /* Asynchronous Channel 3 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH37_bp 7 /* Asynchronous Channel 3 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 Input Selection - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 Input Selection - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 Input Selection - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 Input Selection - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 Input Selection - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 Input Selection - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 Input Selection - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 Input Selection - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 Input Selection - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 Input Selection - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 Input Selection - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 Input Selection - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 Input Selection - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 Input Selection - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 Input Selection - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 Input Selection - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 Input Selection - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 Input Selection - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 Input Selection - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 Input Selection - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Syncronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Syncronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Syncronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Syncronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Syncronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Syncronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 14 +#define TCD0_OVF_vect _VECTOR(14) /* */ +#define TCD0_TRIG_vect_num 15 +#define TCD0_TRIG_vect _VECTOR(15) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 16 +#define AC0_AC_vect _VECTOR(16) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 17 +#define ADC0_RESRDY_vect _VECTOR(17) /* */ +#define ADC0_WCOMP_vect_num 18 +#define ADC0_WCOMP_vect _VECTOR(18) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 19 +#define TWI0_TWIS_vect _VECTOR(19) /* */ +#define TWI0_TWIM_vect_num 20 +#define TWI0_TWIM_vect _VECTOR(20) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 21 +#define SPI0_INT_vect _VECTOR(21) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 22 +#define USART0_RXC_vect _VECTOR(22) /* */ +#define USART0_DRE_vect_num 23 +#define USART0_DRE_vect _VECTOR(23) /* */ +#define USART0_TXC_vect_num 24 +#define USART0_TXC_vect _VECTOR(24) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 25 +#define NVMCTRL_EE_vect _VECTOR(25) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (26 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (34816) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (34816U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (64) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (64U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3F80) +# define INTERNAL_SRAM_SIZE (128) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3F80U) +# define INTERNAL_SRAM_SIZE (128U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (2048) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (2048U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (2048) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (2048U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x91 +#define SIGNATURE_2 0x20 + + +#endif /* #ifdef _AVR_ATTINY214_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn22.h b/hardware/tools/avr/avr/include/avr/iotn22.h new file mode 100644 index 0000000000000000000000000000000000000000..607078375d155040e2e31c946775dbe3ebfd78a1 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn22.h @@ -0,0 +1,221 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iotn22.h 2236 2011-03-17 21:53:39Z arcanum $ */ + +/* avr/iotn22.h - definitions for ATtiny22 */ + +#ifndef _AVR_IOTN22_H_ +#define _AVR_IOTN22_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn22.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* Input Pins, Port B */ +#define PINB _SFR_IO8(0x16) + +/* Data Direction Register, Port B */ +#define DDRB _SFR_IO8(0x17) + +/* Data Register, Port B */ +#define PORTB _SFR_IO8(0x18) + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO8(0x1E) +#define EEARL _SFR_IO8(0x1E) + +/* Watchdog Timer Control Register */ +#define WDTCR _SFR_IO8(0x21) + +/* Timer/Counter 0 */ +#define TCNT0 _SFR_IO8(0x32) + +/* Timer/Counter 0 Control Register */ +#define TCCR0 _SFR_IO8(0x33) + +/* MCU Status Register */ +#define MCUSR _SFR_IO8(0x34) + +/* MCU general Control Register */ +#define MCUCR _SFR_IO8(0x35) + +/* Timer/Counter Interrupt Flag register */ +#define TIFR _SFR_IO8(0x38) + +/* Timer/Counter Interrupt MaSK register */ +#define TIMSK _SFR_IO8(0x39) + +/* General Interrupt Flag register */ +#define GIFR _SFR_IO8(0x3A) + +/* General Interrupt MaSK register */ +#define GIMSK _SFR_IO8(0x3B) + +/* 0x3D SP */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF0_vect_num 2 +#define TIMER0_OVF0_vect _VECTOR(2) +#define SIG_OVERFLOW0 _VECTOR(2) + +#define _VECTORS_SIZE 6 + +/* + The Register Bit names are represented by their bit number (0-7). + */ + +/* General Interrupt MaSK register */ +#define INT0 6 +#define INTF0 6 + +/* General Interrupt Flag Register */ +#define TOIE0 1 +#define TOV0 1 + +/* MCU general Control Register */ +#define SE 5 +#define SM 4 +#define ISC01 1 +#define ISC00 0 + +/* Timer/Counter 0 Control Register */ +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* Watchdog Timer Control Register */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* + PB2 = SCK/T0 + PB1 = MISO/INT0 + PB0 = MOSI + */ + +/* Data Register, Port B */ +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Data Direction Register, Port B */ +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Input Pins, Port B */ +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* EEPROM Control Register */ +#define EERIE 3 +#define EEMWE 2 +#define EEWE 1 +#define EERE 0 + +/* Constants */ +#define RAMSTART 0x60 +#define RAMEND 0xDF +#define XRAMEND RAMEND +#define E2END 0x7F +#define E2PAGESIZE 0 +#define FLASHEND 0x07FF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 1 + +/* Fuse Byte */ +#define FUSE_CKSEL (unsigned char)~_BV(0) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_DEFAULT (FUSE_SPIEN) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x91 +#define SIGNATURE_2 0x06 + + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_OVERFLOW0 + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + +#define SLEEP_MODE_IDLE (0x00<<4) +#define SLEEP_MODE_PWR_DOWN (0x01<<4) + +#endif /* _AVR_IOTN22_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iotn2313.h b/hardware/tools/avr/avr/include/avr/iotn2313.h new file mode 100644 index 0000000000000000000000000000000000000000..570caf4746f2f5ddc1256030511b120e348a3cf5 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn2313.h @@ -0,0 +1,702 @@ +/* Copyright (c) 2004, 2005, 2006 Bob Paddock + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iotn2313.h 2236 2011-03-17 21:53:39Z arcanum $ */ + +/* iotn2313.h derived from io2313.h by Bob Paddock. + + The changes between the AT90S2313 and the ATtiny2313 are extensive. + + Atmel has renamed several registers, and bits. See Atmel application note + AVR091, as well as the errata at the end of the current ATtiny2313 data + sheet. Some of the names have changed more than once during the sampling + period of the ATtiny2313. + + Where there is no conflict the new and old names are both supported. + + In the case of a new feature in a register, only the new name is used. + This intentionally breaks old code, so that there are no silent bugs. The + source code must be updated to the new name in this case. + + The hardware interrupt vector table has changed from that of the AT90S2313. + + ATtiny2313 programs in page mode rather than the byte mode of the + AT90S2313. Beware of programming the ATtiny2313 as a AT90S2313 device, + when programming the Flash. + + ATtiny2313 has Signature Bytes: 0x1E 0x91 0x0A. + + Changes and/or additions are noted by "ATtiny" in the comments below. */ + +/* avr/iotn2313.h - definitions for ATtiny2313 */ + +#ifndef _AVR_IOTN2313_H_ +#define _AVR_IOTN2313_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn2313.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* + * The Register Bit names are represented by their bit number (0-7). + * Example: PORTB |= _BV(PORTB7); Set MSB of PORTB. + */ + +/* 0x00 Reserved */ + +/* ATtiny Digital Input Disable Register DIDR */ +#define DIDR _SFR_IO8(0x01) + +#define AIN1D 1 +#define AIN0D 0 + +/* ATtiny USART Baud Rate Register High UBBRH[11:8] */ +#define UBRRH _SFR_IO8(0x02) + +/* ATtiny USART Control and Status Register C UCSRC */ +#define UCSRC _SFR_IO8(0x03) + +#define UMSEL 6 +#define UPM1 5 +#define UPM0 4 +#define USBS 3 +#define UCSZ1 2 +#define UCSZ0 1 +#define UCPOL 0 + +/* 0x04 -> 0x07 Reserved */ + +/* ATtiny Analog Comparator Control and Status Register ACSR */ +#define ACSR _SFR_IO8(0x08) + +#define ACD 7 +#define ACBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +/* USART Baud Rate Register Low UBBRL[7:0] */ +#define UBRRL _SFR_IO8(0x09) + +/* ATtiny USART Control Register UCSRB */ +#define UCSRB _SFR_IO8(0x0A) + +#define RXCIE 7 +#define TXCIE 6 +#define UDRIE 5 +#define RXEN 4 +#define TXEN 3 +#define UCSZ2 2 +#define RXB8 1 +#define TXB8 0 + +/* ATtiny USART Status Register UCSRA */ +#define UCSRA _SFR_IO8(0x0B) + +#define RXC 7 +#define TXC 6 +#define UDRE 5 +#define FE 4 +#define DOR 3 +#define UPE 2 +#define U2X 1 +#define MPCM 0 + +/* USART I/O Data Register UBR or RXB[7:0], TXB[7:0] */ +#define UDR _SFR_IO8(0x0C) +#define RXB _SFR_IO8(0x0C) +#define TXB _SFR_IO8(0x0C) + +/* ATtiny USI Control Register USICR */ +#define USICR _SFR_IO8(0x0D) + +#define USISIE 7 +#define USIOIE 6 +#define USIWM1 5 +#define USIWM0 4 +#define USICS1 3 +#define USICS0 2 +#define USICLK 1 +#define USITC 0 + +/* ATtiny USI Status Register USISR */ +#define USISR _SFR_IO8(0x0E) + +#define USISIF 7 +#define USIOIF 6 +#define USIPF 5 +#define USIDC 4 +#define USICNT3 3 +#define USICNT2 2 +#define USICNT1 1 +#define USICNT0 0 + +/* ATtiny USI Data Register USIDR[7:0] */ +#define USIDR _SFR_IO8(0x0F) + +/* Input Pins, Port D PIND[6:0] */ +#define PIND _SFR_IO8(0x10) + +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* Data Direction Register, Port D DDRD[6:0] */ +#define DDRD _SFR_IO8(0x11) + +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* Data Register, Port D PORTD[6:0] */ +#define PORTD _SFR_IO8(0x12) + +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* ATtiny General Purpose I/O Register Zero GPIOR0[7:0] */ +#define GPIOR0 _SFR_IO8(0x13) + +/* ATtiny General Purpose I/O Register One GPIOR1[7:0] */ +#define GPIOR1 _SFR_IO8(0x14) + +/* ATtiny General Purpose I/O Register Two One GPIOR2[7:0] */ +#define GPIOR2 _SFR_IO8(0x15) + +/* Input Pins, Port B PORTB[7:0] */ +#define PINB _SFR_IO8(0x16) + +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* Data Direction Register, Port B PORTB[7:0] */ +#define DDRB _SFR_IO8(0x17) + +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/* Data Register, Port B PORTB[7:0] */ +#define PORTB _SFR_IO8(0x18) + +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Port A Input Pins Address PINA[2:0] */ +#define PINA _SFR_IO8(0x19) + +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +/* Port A Data Direction Register DDRA[2:0] */ +#define DDRA _SFR_IO8(0x1A) + +#define DDRA2 2 +#define DDRA1 1 +#define DDRA0 0 + +/* Port A Data Register PORTA[2:0] */ +#define PORTA _SFR_IO8(0x1B) + +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* ATtiny EEPROM Control Register EECR */ +#define EECR _SFR_IO8(0x1C) +#define EEPM1 5 +#define EEPM0 4 +#define EERIE 3 +#define EEMPE 2 +#define EEPE 1 +#define EERE 0 + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* The EEPROM Address Register EEAR[6:0] */ +#define EEAR _SFR_IO8(0x1E) +#define EEARL _SFR_IO8(0x1E) +#define EEAR6 6 +#define EEAR5 5 +#define EEAR4 4 +#define EEAR3 3 +#define EEAR2 2 +#define EEAR1 1 +#define EEAR0 0 + +/* 0x1F Reserved */ + +/* ATtiny Pin Change Mask Register PCMSK PCINT[7:0] */ +#define PCMSK _SFR_IO8(0x20) + +#define PCINT7 7 +#define PCINT6 6 +#define PCINT5 5 +#define PCINT4 4 +#define PCINT3 3 +#define PCINT2 2 +#define PCINT1 1 +#define PCINT0 0 + +/* ATtiny Watchdog Timer Control Register WDTCSR */ +#define WDTCSR _SFR_IO8(0x21) + +#define WDIF 7 +#define WDIE 6 +#define WDP3 5 +#define WDCE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* ATtiny Timer/Counter1 Control Register C TCCR1C */ +#define TCCR1C _SFR_IO8(0x22) + +#define FOC1A 7 +#define FOC1B 6 + +/* General Timer/Counter Control Register GTCCR */ +#define GTCCR _SFR_IO8(0x23) + +#define PSR10 0 + +/* T/C 1 Input Capture Register ICR1[15:0] */ +#define ICR1 _SFR_IO16(0x24) +#define ICR1L _SFR_IO8(0x24) +#define ICR1H _SFR_IO8(0x25) + +/* ATtiny Clock Prescale Register */ +#define CLKPR _SFR_IO8(0x26) + +#define CLKPCE 7 +#define CLKPS3 3 +#define CLKPS2 2 +#define CLKPS1 1 +#define CLKPS0 0 + +/* 0x27 Reserved */ + +/* ATtiny Output Compare Register 1 B OCR1B[15:0] */ +#define OCR1B _SFR_IO16(0x28) +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Output Compare Register 1 OCR1A[15:0] */ +#define OCR1 _SFR_IO16(0x2A) +#define OCR1L _SFR_IO8(0x2A) +#define OCR1H _SFR_IO8(0x2B) +#define OCR1A _SFR_IO16(0x2A) +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Timer/Counter 1 TCNT1[15:0] */ +#define TCNT1 _SFR_IO16(0x2C) +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +/* ATtiny Timer/Counter 1 Control and Status Register TCCR1B */ +#define TCCR1B _SFR_IO8(0x2E) + +#define ICNC1 7 +#define ICES1 6 +#define WGM13 4 +#define WGM12 3 /* Was CTC1 in AT90S2313 */ +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/* ATtiny Timer/Counter 1 Control Register TCCR1A */ +#define TCCR1A _SFR_IO8(0x2F) + +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define WGM11 1 /* Was PWM11 in AT90S2313 */ +#define WGM10 0 /* Was PWM10 in AT90S2313 */ + +/* ATtiny Timer/Counter Control Register A TCCR0A */ +#define TCCR0A _SFR_IO8(0x30) + +#define COM0A1 7 +#define COM0A0 6 +#define COM0B1 5 +#define COM0B0 4 +#define WGM01 1 +#define WGM00 0 + +/* ATtiny Oscillator Calibration Register OSCCAL[6:0] */ +#define OSCCAL _SFR_IO8(0x31) + +#define CAL6 6 +#define CAL5 5 +#define CAL4 4 +#define CAL3 3 +#define CAL2 2 +#define CAL1 1 +#define CAL0 0 + +/* Timer/Counter 0 TCNT0[7:0] */ +#define TCNT0 _SFR_IO8(0x32) + +/* ATtiny Timer/Counter 0 Control Register TCCR0B */ +#define TCCR0B _SFR_IO8(0x33) + +#define FOC0A 7 +#define FOC0B 6 +#define WGM02 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* ATtiny MCU Status Register MCUSR */ +#define MCUSR _SFR_IO8(0x34) + +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +/* ATtiny MCU general Control Register MCUCR */ +#define MCUCR _SFR_IO8(0x35) + +#define PUD 7 +#define SM1 6 +#define SE 5 +#define SM0 4 /* Some preliminary ATtiny2313 data sheets incorrectly refer + to this bit as SMD; was SM in AT90S2313. */ +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/* ATtiny Output Compare Register A OCR0A[7:0] */ +#define OCR0A _SFR_IO8(0x36) + +/* ATtiny Store Program Memory Control and Status Register SPMCSR */ +#define SPMCSR _SFR_IO8(0x37) + +#define CTPB 4 +#define RFLB 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 /* The name is used in ATtiny2313.xml file. */ +#define SELFPRGEN 0 /* The name is used in datasheet. */ +#define SELFPRGE 0 /* The name is left for compatibility. */ + +/* ATtiny Timer/Counter Interrupt Flag register TIFR */ +#define TIFR _SFR_IO8(0x38) + +#define TOV1 7 +#define OCF1A 6 +#define OCF1B 5 +#define ICF1 3 +#define OCF0B 2 +#define TOV0 1 +#define OCF0A 0 + +/* ATtiny Timer/Counter Interrupt MaSK register TIMSK */ +#define TIMSK _SFR_IO8(0x39) + +#define TOIE1 7 +#define OCIE1A 6 +#define OCIE1B 5 +#define ICIE1 3 +#define OCIE0B 2 +#define TOIE0 1 +#define OCIE0A 0 + +/* ATtiny External Interrupt Flag Register EIFR, was GIFR */ +#define EIFR _SFR_IO8(0x3A) + +#define INTF1 7 +#define INTF0 6 +#define PCIF 5 + +/* ATtiny General Interrupt MaSK register GIMSK */ +#define GIMSK _SFR_IO8(0x3B) + +#define INT1 7 +#define INT0 6 +#define PCIE 5 + +/* ATtiny Output Compare Register B OCR0B[7:0] */ +#define OCR0B _SFR_IO8(0x3C) + +/* Interrupt vectors: */ + +/* External Interrupt Request 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) +#define SIG_INT0 _VECTOR(1) + +/* External Interrupt Request 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) +#define SIG_INT1 _VECTOR(2) + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect_num 3 +#define TIMER1_CAPT_vect _VECTOR(3) +#define SIG_INPUT_CAPTURE1 _VECTOR(3) +#define SIG_TIMER1_CAPT _VECTOR(3) + +/* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPA_vect_num 4 +#define TIMER1_COMPA_vect _VECTOR(4) +#define SIG_OUTPUT_COMPARE1A _VECTOR(4) +#define SIG_TIMER1_COMPA _VECTOR(4) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 5 +#define TIMER1_OVF_vect _VECTOR(5) +#define SIG_OVERFLOW1 _VECTOR(5) +#define SIG_TIMER1_OVF _VECTOR(5) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 6 +#define TIMER0_OVF_vect _VECTOR(6) +#define SIG_OVERFLOW0 _VECTOR(6) +#define SIG_TIMER0_OVF _VECTOR(6) + +/* USART, Rx Complete */ +#define USART_RX_vect_num 7 +#define USART_RX_vect _VECTOR(7) +#define SIG_USART0_RECV _VECTOR(7) +#define SIG_USART0_RX _VECTOR(7) + +/* USART Data Register Empty */ +#define USART_UDRE_vect_num 8 +#define USART_UDRE_vect _VECTOR(8) +#define SIG_USART0_DATA _VECTOR(8) +#define SIG_USART0_UDRE _VECTOR(8) + +/* USART, Tx Complete */ +#define USART_TX_vect_num 9 +#define USART_TX_vect _VECTOR(9) +#define SIG_USART0_TRANS _VECTOR(9) +#define SIG_USART0_TX _VECTOR(9) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 10 +#define ANA_COMP_vect _VECTOR(10) +#define SIG_COMPARATOR _VECTOR(10) +#define SIG_ANALOG_COMP _VECTOR(10) + +#define PCINT_vect_num 11 +#define PCINT_vect _VECTOR(11) +#define SIG_PIN_CHANGE _VECTOR(11) +#define SIG_PCINT _VECTOR(11) + +#define TIMER1_COMPB_vect_num 12 +#define TIMER1_COMPB_vect _VECTOR(12) +#define SIG_OUTPUT_COMPARE1B _VECTOR(12) +#define SIG_TIMER1_COMPB _VECTOR(12) + +#define TIMER0_COMPA_vect_num 13 +#define TIMER0_COMPA_vect _VECTOR(13) +#define SIG_OUTPUT_COMPARE0A _VECTOR(13) +#define SIG_TIMER0_COMPA _VECTOR(13) + +#define TIMER0_COMPB_vect_num 14 +#define TIMER0_COMPB_vect _VECTOR(14) +#define SIG_OUTPUT_COMPARE0B _VECTOR(14) +#define SIG_TIMER0_COMPB _VECTOR(14) + +/* USI Start Condition */ +#define USI_START_vect_num 15 +#define USI_START_vect _VECTOR(15) +#define SIG_USI_START _VECTOR(15) + +/* USI Overflow */ +#define USI_OVERFLOW_vect_num 16 +#define USI_OVERFLOW_vect _VECTOR(16) +#define SIG_USI_OVERFLOW _VECTOR(16) + +#define EEPROM_READY_vect_num 17 +#define EEPROM_READY_vect _VECTOR(17) +#define SIG_EEPROM_READY _VECTOR(17) +#define SIG_EE_READY _VECTOR(17) + +/* Watchdog Timer Overflow */ +#define WDT_OVERFLOW_vect_num 18 +#define WDT_OVERFLOW_vect _VECTOR(18) +#define SIG_WATCHDOG_TIMEOUT _VECTOR(18) +#define SIG_WDT_OVERFLOW _VECTOR(18) + +/* 38 = (18*2)+2: Number of vectors times two, plus the reset vector */ +#define _VECTORS_SIZE 38 + +/* Constants */ +#define SPM_PAGESIZE 32 +#define RAMSTART (0x60) +#define RAMEND 0xDF +#define XRAMEND RAMEND +#define E2END 0x7F +#define E2PAGESIZE 4 +#define FLASHEND 0x07FF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_RSTDISBL (unsigned char)~_BV(0) +#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_EESAVE (unsigned char)~_BV(6) +#define FUSE_DWEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_SPIEN) + +/* Extended Fuse Byte */ +#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x91 +#define SIGNATURE_2 0x0A + + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_INT0 +#pragma GCC poison SIG_INTERRUPT1 +#pragma GCC poison SIG_INT1 +#pragma GCC poison SIG_INPUT_CAPTURE1 +#pragma GCC poison SIG_TIMER1_CAPT +#pragma GCC poison SIG_OUTPUT_COMPARE1A +#pragma GCC poison SIG_TIMER1_COMPA +#pragma GCC poison SIG_OVERFLOW1 +#pragma GCC poison SIG_TIMER1_OVF +#pragma GCC poison SIG_OVERFLOW0 +#pragma GCC poison SIG_TIMER0_OVF +#pragma GCC poison SIG_USART0_RECV +#pragma GCC poison SIG_USART0_RX +#pragma GCC poison SIG_USART0_DATA +#pragma GCC poison SIG_USART0_UDRE +#pragma GCC poison SIG_USART0_TRANS +#pragma GCC poison SIG_USART0_TX +#pragma GCC poison SIG_COMPARATOR +#pragma GCC poison SIG_ANALOG_COMP +#pragma GCC poison SIG_PIN_CHANGE +#pragma GCC poison SIG_PCINT +#pragma GCC poison SIG_OUTPUT_COMPARE1B +#pragma GCC poison SIG_TIMER1_COMPB +#pragma GCC poison SIG_OUTPUT_COMPARE0A +#pragma GCC poison SIG_TIMER0_COMPA +#pragma GCC poison SIG_OUTPUT_COMPARE0B +#pragma GCC poison SIG_TIMER0_COMPB +#pragma GCC poison SIG_USI_START +#pragma GCC poison SIG_USI_OVERFLOW +#pragma GCC poison SIG_EEPROM_READY +#pragma GCC poison SIG_EE_READY +#pragma GCC poison SIG_WATCHDOG_TIMEOUT +#pragma GCC poison SIG_WDT_OVERFLOW + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + + +#define SLEEP_MODE_IDLE (0x00<<4) +#define SLEEP_MODE_STANDBY (0x04<<4) +#define SLEEP_MODE_PWR_DOWN (0x05<<4) + +#endif /* _AVR_IOTN2313_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iotn2313a.h b/hardware/tools/avr/avr/include/avr/iotn2313a.h new file mode 100644 index 0000000000000000000000000000000000000000..ea991cf98c882bb264f75de56068fdffdb98b1db --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn2313a.h @@ -0,0 +1,812 @@ +/* Copyright (c) 2009 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iotn2313a.h 2412 2014-03-20 11:21:20Z pitchumani $ */ + +/* avr/iotn2313a.h - definitions for ATtiny2313A */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn2313a.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATtiny2313A_H_ +#define _AVR_ATtiny2313A_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define USIBR _SFR_IO8(0x000) +#define USIBR0 0 +#define USIBR1 1 +#define USIBR2 2 +#define USIBR3 3 +#define USIBR4 4 +#define USIBR5 5 +#define USIBR6 6 +#define USIBR7 7 + +#define DIDR _SFR_IO8(0x001) +#define AIN0D 0 +#define AIN1D 1 + +#define UBRRH _SFR_IO8(0x002) +#define UBRR8 0 +#define UBRR9 1 +#define UBRR10 2 +#define UBRR11 3 + +#define UCSRC _SFR_IO8(0x003) +#define UCPOL 0 +#define UCSZ0 1 +#define UCSZ1 2 +#define USBS 3 +#define UPM0 4 +#define UPM1 5 +#define UMSEL0 6 +#define UMSEL1 7 + +/* When in MSPIM mode */ +#define UCPHA 1 +#define UDORD 2 + +#define PCMSK1 _SFR_IO8(0x004) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 + +#define PCMSK2 _SFR_IO8(0x005) +#define PCINT11 0 +#define PCINT12 1 +#define PCINT13 2 +#define PCINT14 3 +#define PCINT15 4 +#define PCINT16 5 +#define PCINT17 6 + +#define PRR _SFR_IO8(0x006) +#define PRUSART 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 + +#define __AVR_HAVE_PRR ((1< + +#define SPM_PAGESIZE 32 +#define RAMSTART (0x60) +#define RAMEND 0xDF +#define XRAMEND RAMEND +#define E2END 0x7F +#define E2PAGESIZE 4 +#define FLASHEND 0x7FF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_DWEN (unsigned char)~_BV(6) +#define FUSE_RSTDISBL (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_SPIEN) + +/* Extended Fuse Byte */ +#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x91 +#define SIGNATURE_2 0x0B + +#define SLEEP_MODE_IDLE (0x00<<3) +#define SLEEP_MODE_ADC (0x01<<3) +#define SLEEP_MODE_PWR_DOWN (0x02<<3) +#define SLEEP_MODE_STANDBY (0x03<<3) + +#endif /* _AVR_IOTN24_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iotn24a.h b/hardware/tools/avr/avr/include/avr/iotn24a.h new file mode 100644 index 0000000000000000000000000000000000000000..35d5277db52de27d4aef8e4bb8c272d1028d169e --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn24a.h @@ -0,0 +1,846 @@ +/* Copyright (c) 2009 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iotn24a.h 2414 2014-03-21 16:04:00Z pitchumani $ */ + +/* avr/iotn24a.h - definitions for ATtiny24A */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn24a.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATtiny24A_H_ +#define _AVR_ATtiny24A_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PRR _SFR_IO8(0x00) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 + +#define __AVR_HAVE_PRR ((1< + +#define SPM_PAGESIZE 32 +#define RAMSTART (0x60) +#define RAMEND 0xDF +#define XRAMEND RAMEND +#define E2END 0x7F +#define E2PAGESIZE 4 +#define FLASHEND 0x7FF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_DWEN (unsigned char)~_BV(6) +#define FUSE_RSTDISBL (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_SPIEN) + +/* Extended Fuse Byte */ +#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x91 +#define SIGNATURE_2 0x08 + +#define SLEEP_MODE_IDLE (0x00<<3) +#define SLEEP_MODE_ADC (0x01<<3) +#define SLEEP_MODE_PWR_DOWN (0x02<<3) + +#endif /* _AVR_IOTN25_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iotn26.h b/hardware/tools/avr/avr/include/avr/iotn26.h new file mode 100644 index 0000000000000000000000000000000000000000..e0d81a3d439f6599acda5e4a980940ed81f13688 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn26.h @@ -0,0 +1,422 @@ +/* Copyright (c) 2004,2005 Eric B. Weddington + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iotn26.h 2236 2011-03-17 21:53:39Z arcanum $ */ + +/* avr/iotn26.h - definitions for ATtiny26 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn26.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_IOTN26_H_ +#define _AVR_IOTN26_H_ 1 + +/* Registers and associated bit numbers */ + +/* Reserved [0x00..0x03] */ + +#define ADCW _SFR_IO16(0x04) +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif + +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) + +#define ADCSR _SFR_IO8(0x06) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADFR 5 +#define ADSC 6 +#define ADEN 7 + +#define ADMUX _SFR_IO8(0x07) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define MUX4 4 +#define ADLAR 5 +#define REFS0 6 +#define REFS1 7 + +#define ACSR _SFR_IO8(0x08) +#define ACIS0 0 +#define ACIS1 1 +#define ACME 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x09..0x0C] */ + +#define USICR _SFR_IO8(0x0D) +#define USITC 0 +#define USICLK 1 +#define USICS0 2 +#define USICS1 3 +#define USIWM0 4 +#define USIWM1 5 +#define USIOIE 6 +#define USISIE 7 + +#define USISR _SFR_IO8(0x0E) +#define USICNT0 0 +#define USICNT1 1 +#define USICNT2 2 +#define USICNT3 3 +#define USIDC 4 +#define USIPF 5 +#define USIOIF 6 +#define USISIF 7 + +#define USIDR _SFR_IO8(0x0F) + +/* Reserved [0x10..0x15] */ + + +#define PINB _SFR_IO8(0x16) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x17) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x18) +#define PB0 0 +#define PB1 1 +#define PB2 2 +#define PB3 3 +#define PB4 4 +#define PB5 5 +#define PB6 6 +#define PB7 7 + +#define PINA _SFR_IO8(0x19) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 +#define PINA4 4 +#define PINA5 5 +#define PINA6 6 +#define PINA7 7 + +#define DDRA _SFR_IO8(0x1A) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x1B) +#define PA0 0 +#define PA1 1 +#define PA2 2 +#define PA3 3 +#define PA4 4 +#define PA5 5 +#define PA6 6 +#define PA7 7 + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO8(0x1E) +#define EEARL _SFR_IO8(0x1E) + +/* Reserved [0x1F..0x20] */ + +#define WDTCR _SFR_IO8(0x21) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +/* Reserved [0x22..0x28] */ + +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 +#define PLLE 1 +#define PCKE 2 + +/* Reserved [0x2A] */ + +#define OCR1C _SFR_IO8(0x2B) + +#define OCR1B _SFR_IO8(0x2C) + +#define OCR1A _SFR_IO8(0x2D) + +#define TCNT1 _SFR_IO8(0x2E) + +#define TCCR1B _SFR_IO8(0x2F) +#define CS10 0 +#define CS11 1 +#define CS12 2 +#define CS13 3 +#define PSR1 6 +#define CTC1 7 + +#define TCCR1A _SFR_IO8(0x30) +#define PWM1B 0 +#define PWM1A 1 +#define FOC1B 2 +#define FOC1A 3 +#define COM1B0 4 +#define COM1B1 5 +#define COM1A0 6 +#define COM1A1 7 + +#define OSCCAL _SFR_IO8(0x31) + +#define TCNT0 _SFR_IO8(0x32) + +#define TCCR0 _SFR_IO8(0x33) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define PSR0 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define ISC00 0 +#define ISC01 1 +#define SM0 3 +#define SM1 4 +#define SE 5 +#define PUD 6 + +/* Reserved [0x36..0x37] */ + +#define TIFR _SFR_IO8(0x38) +#define TOV0 1 +#define TOV1 2 +#define OCF1B 5 +#define OCF1A 6 + +#define TIMSK _SFR_IO8(0x39) +#define TOIE0 1 +#define TOIE1 2 +#define OCIE1B 5 +#define OCIE1A 6 + +#define GIFR _SFR_IO8(0x3A) +#define PCIF 5 +#define INTF0 6 + +#define GIMSK _SFR_IO8(0x3B) +#define PCIE0 4 +#define PCIE1 5 +#define INT0 6 + +/* Reserved [0x3C] */ + +/* SP [0x3D] */ + +/* Reserved [0x3E] */ + +/* SREG [0x3F] */ + + +/* Interrupt vectors */ +/* Interrupt vector 0 is the reset vector. */ +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt Request 0 */ +#define IO_PINS_vect_num 2 +#define IO_PINS_vect _VECTOR(2) +#define SIG_PIN_CHANGE _VECTOR(2) + +/* Timer/Counter1 Compare Match 1A */ +#define TIMER1_CMPA_vect_num 3 +#define TIMER1_CMPA_vect _VECTOR(3) +#define SIG_OUTPUT_COMPARE1A _VECTOR(3) + +/* Timer/Counter1 Compare Match 1B */ +#define TIMER1_CMPB_vect_num 4 +#define TIMER1_CMPB_vect _VECTOR(4) +#define SIG_OUTPUT_COMPARE1B _VECTOR(4) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF1_vect_num 5 +#define TIMER1_OVF1_vect _VECTOR(5) +#define SIG_OVERFLOW1 _VECTOR(5) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF0_vect_num 6 +#define TIMER0_OVF0_vect _VECTOR(6) +#define SIG_OVERFLOW0 _VECTOR(6) + +/* USI Start */ +#define USI_STRT_vect_num 7 +#define USI_STRT_vect _VECTOR(7) +#define SIG_USI_START _VECTOR(7) + +/* USI Overflow */ +#define USI_OVF_vect_num 8 +#define USI_OVF_vect _VECTOR(8) +#define SIG_USI_OVERFLOW _VECTOR(8) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 9 +#define EE_RDY_vect _VECTOR(9) +#define SIG_EEPROM_READY _VECTOR(9) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 10 +#define ANA_COMP_vect _VECTOR(10) +#define SIG_ANA_COMP _VECTOR(10) +#define SIG_COMPARATOR _VECTOR(10) + +/* ADC Conversion Complete */ +#define ADC_vect_num 11 +#define ADC_vect _VECTOR(11) +#define SIG_ADC _VECTOR(11) + +#define _VECTORS_SIZE 24 + + +/* Constants */ +#define RAMSTART 0x60 +#define RAMEND 0xDF +#define XRAMEND RAMEND +#define E2END 0x7F +#define E2PAGESIZE 4 +#define FLASHEND 0x07FF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 2 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOPT (unsigned char)~_BV(6) +#define FUSE_PLLCK (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) + +/* High Fuse Byte */ +#define FUSE_BODEN (unsigned char)~_BV(0) +#define FUSE_BODLEVEL (unsigned char)~_BV(1) +#define FUSE_EESAVE (unsigned char)~_BV(2) +#define FUSE_SPIEN (unsigned char)~_BV(3) +#define FUSE_RSTDISBL (unsigned char)~_BV(4) +#define HFUSE_DEFAULT (FUSE_SPIEN) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x91 +#define SIGNATURE_2 0x09 + + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_PIN_CHANGE +#pragma GCC poison SIG_OUTPUT_COMPARE1A +#pragma GCC poison SIG_OUTPUT_COMPARE1B +#pragma GCC poison SIG_OVERFLOW1 +#pragma GCC poison SIG_OVERFLOW0 +#pragma GCC poison SIG_USI_START +#pragma GCC poison SIG_USI_OVERFLOW +#pragma GCC poison SIG_EEPROM_READY +#pragma GCC poison SIG_ANA_COMP +#pragma GCC poison SIG_COMPARATOR +#pragma GCC poison SIG_ADC + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + +#define SLEEP_MODE_IDLE (0x00<<3) +#define SLEEP_MODE_ADC (0x01<<3) +#define SLEEP_MODE_PWR_DOWN (0x02<<3) +#define SLEEP_MODE_STANDBY (0x03<<3) + +#endif /* _AVR_IOTN26_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iotn261.h b/hardware/tools/avr/avr/include/avr/iotn261.h new file mode 100644 index 0000000000000000000000000000000000000000..0bce89d7ff41cab943ea4c1264fc8d8e152dcdba --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn261.h @@ -0,0 +1,93 @@ +/* Copyright (c) 2006, Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iotn261.h 2115 2010-04-05 23:19:53Z arcanum $ */ + +/* avr/iotn261.h - definitions for ATtiny261 */ + +#ifndef _AVR_IOTN261_H_ +#define _AVR_IOTN261_H_ 1 + +#include + +#define SPM_PAGESIZE 32 +#define RAMSTART (0x60) +#define RAMEND 0xDF +#define XRAMEND RAMEND +#define E2END 0x7F +#define E2PAGESIZE 4 +#define FLASHEND 0x7FF + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_DWEN (unsigned char)~_BV(6) +#define FUSE_RSTDISBL (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_SPIEN) + +/* Extended Fuse Byte */ +#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x91 +#define SIGNATURE_2 0x0C + +#define SLEEP_MODE_IDLE (0x00<<3) +#define SLEEP_MODE_ADC (0x01<<3) +#define SLEEP_MODE_PWR_DOWN (0x02<<3) +#define SLEEP_MODE_STANDBY (0x03<<3) + +#endif /* _AVR_IOTN261_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iotn261a.h b/hardware/tools/avr/avr/include/avr/iotn261a.h new file mode 100644 index 0000000000000000000000000000000000000000..f4a7fa099c297c8724563425a4e3d6d0ee3b1993 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn261a.h @@ -0,0 +1,987 @@ +/* Copyright (c) 2009 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iotn261a.h 2063 2009-11-18 22:06:28Z arcanum $ */ + +/* avr/iotn261a.h - definitions for ATtiny261A */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn261a.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATtiny261A_H_ +#define _AVR_ATtiny261A_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define TCCR1E _SFR_IO8(0x00) +#define OC1OE0 0 +#define OC1OE1 1 +#define OC1OE2 2 +#define OC1OE3 3 +#define OC1OE4 4 +#define OC1OE5 5 + +#define DIDR0 _SFR_IO8(0x01) +#define ADC0D 0 +#define ADC1D 1 +#define ADC2D 2 +#define AREFD 3 +#define ADC3D 4 +#define ADC4D 5 +#define ADC5D 6 +#define ADC6D 7 + +#define DIDR1 _SFR_IO8(0x02) +#define ADC7D 4 +#define ADC8D 5 +#define ADC9D 6 +#define ADC10D 7 + +#define ADCSRB _SFR_IO8(0x03) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 +#define MUX5 3 +#define REFS2 4 +#define IPR 5 +#define GSEL 6 +#define BIN 7 + +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) + +#define ADCL _SFR_IO8(0x04) +#define ADCL0 0 +#define ADCL1 1 +#define ADCL2 2 +#define ADCL3 3 +#define ADCL4 4 +#define ADCL5 5 +#define ADCL6 6 +#define ADCL7 7 + +#define ADCH _SFR_IO8(0x05) +#define ADCH0 0 +#define ADCH1 1 +#define ADCH2 2 +#define ADCH3 3 +#define ADCH4 4 +#define ADCH5 5 +#define ADCH6 6 +#define ADCH7 7 + +#define ADCSRA _SFR_IO8(0x06) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +#define ADMUX _SFR_IO8(0x07) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define MUX4 4 +#define ADLAR 5 +#define REFS0 6 +#define REFS1 7 + +#define ACSRA _SFR_IO8(0x08) +#define ACIS0 0 +#define ACIS1 1 +#define ACME 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define ACSRB _SFR_IO8(0x09) +#define ACM0 0 +#define ACM1 1 +#define ACM2 2 +#define HLEV 6 +#define HSEL 7 + +#define GPIOR0 _SFR_IO8(0x0A) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define GPIOR1 _SFR_IO8(0x0B) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x0C) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define USICR _SFR_IO8(0x0D) +#define USITC 0 +#define USICLK 1 +#define USICS0 2 +#define USICS1 3 +#define USIWM0 4 +#define USIWM1 5 +#define USIOIE 6 +#define USISIE 7 + +#define USISR _SFR_IO8(0x0E) +#define USICNT0 0 +#define USICNT1 1 +#define USICNT2 2 +#define USICNT3 3 +#define USIDC 4 +#define USIPF 5 +#define USIOIF 6 +#define USISIF 7 + +#define USIDR _SFR_IO8(0x0F) +#define USIDR0 0 +#define USIDR1 1 +#define USIDR2 2 +#define USIDR3 3 +#define USIDR4 4 +#define USIDR5 5 +#define USIDR6 6 +#define USIDR7 7 + +#define USIBR _SFR_IO8(0x10) +#define USIBR0 0 +#define USIBR1 1 +#define USIBR2 2 +#define USIBR3 3 +#define USIBR4 4 +#define USIBR5 5 +#define USIBR6 6 +#define USIBR7 7 + +#define USIPP _SFR_IO8(0x11) +#define USIPOS 0 + +#define OCR0B _SFR_IO8(0x12) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define OCR0A _SFR_IO8(0x13) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define TCNT0H _SFR_IO8(0x14) +#define TCNT0H_0 0 +#define TCNT0H_1 1 +#define TCNT0H_2 2 +#define TCNT0H_3 3 +#define TCNT0H_4 4 +#define TCNT0H_5 5 +#define TCNT0H_6 6 +#define TCNT0H_7 7 + +#define TCCR0A _SFR_IO8(0x15) +#define WGM00 0 +#define ACIC0 3 +#define ICES0 4 +#define ICNC0 5 +#define ICEN0 6 +#define TCW0 7 + +#define PINB _SFR_IO8(0x16) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x17) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x18) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINA _SFR_IO8(0x19) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 +#define PINA4 4 +#define PINA5 5 +#define PINA6 6 +#define PINA7 7 + +#define DDRA _SFR_IO8(0x1A) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x1B) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 +#define PORTA4 4 +#define PORTA5 5 +#define PORTA6 6 +#define PORTA7 7 + +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x1D) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x1E) + +#define EEARL _SFR_IO8(0x1E) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x1F) +#define EEAR8 0 + +#define DWDR _SFR_IO8(0x20) +#define DWDR0 0 +#define DWDR1 1 +#define DWDR2 2 +#define DWDR3 3 +#define DWDR4 4 +#define DWDR5 5 +#define DWDR6 6 +#define DWDR7 7 + +#define WDTCR _SFR_IO8(0x21) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define PCMSK1 _SFR_IO8(0x22) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 +#define PCINT11 3 +#define PCINT12 4 +#define PCINT13 5 +#define PCINT14 6 +#define PCINT15 7 + +#define PCMSK0 _SFR_IO8(0x23) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 +#define PCINT4 4 +#define PCINT5 5 +#define PCINT6 6 +#define PCINT7 7 + +#define DT1 _SFR_IO8(0x24) +#define DT1L0 0 +#define DT1L1 1 +#define DT1L2 2 +#define DT1L3 3 +#define DT1H0 4 +#define DT1H1 5 +#define DT1H2 6 +#define DT1H3 7 + +#define TC1H _SFR_IO8(0x25) +#define TC18 0 +#define TC19 1 + +#define TCCR1D _SFR_IO8(0x26) +#define WGM10 0 +#define WGM11 1 +#define FPF1 2 +#define FPAC1 3 +#define FPES1 4 +#define FPNC1 5 +#define FPEN1 6 +#define FPIE1 7 + +#define TCCR1C _SFR_IO8(0x27) +#define PWM1D 0 +#define FOC1D 1 +#define COM1D0 2 +#define COM1D1 3 +#define COM1B0S 4 +#define COM1B1S 5 +#define COM1A0S 6 +#define COM1A1S 7 + +#define CLKPR _SFR_IO8(0x28) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 +#define PLLE 1 +#define PCKE 2 +#define LSM 7 + +#define OCR1D _SFR_IO8(0x2A) +#define OCR1D0 0 +#define OCR1D1 1 +#define OCR1D2 2 +#define OCR1D3 3 +#define OCR1D4 4 +#define OCR1D5 5 +#define OCR1D6 6 +#define OCR1D7 7 + +#define OCR1C _SFR_IO8(0x2B) +#define OCR1C0 0 +#define OCR1C1 1 +#define OCR1C2 2 +#define OCR1C3 3 +#define OCR1C4 4 +#define OCR1C5 5 +#define OCR1C6 6 +#define OCR1C7 7 + +#define OCR1B _SFR_IO8(0x2C) +#define OCR1B0 0 +#define OCR1B1 1 +#define OCR1B2 2 +#define OCR1B3 3 +#define OCR1B4 4 +#define OCR1B5 5 +#define OCR1B6 6 +#define OCR1B7 7 + +#define OCR1A _SFR_IO8(0x2D) +#define OCR1A0 0 +#define OCR1A1 1 +#define OCR1A2 2 +#define OCR1A3 3 +#define OCR1A4 4 +#define OCR1A5 5 +#define OCR1A6 6 +#define OCR1A7 7 + +#define TCNT1 _SFR_IO8(0x2E) +#define TC1H_0 0 +#define TC1H_1 1 +#define TC1H_2 2 +#define TC1H_3 3 +#define TC1H_4 4 +#define TC1H_5 5 +#define TC1H_6 6 +#define TC1H_7 7 + +#define TCCR1B _SFR_IO8(0x2F) +#define CS10 0 +#define CS11 1 +#define CS12 2 +#define CS13 3 +#define DTPS10 4 +#define DTPS11 5 +#define PSR1 6 + +#define TCCR1A _SFR_IO8(0x30) +#define PWM1B 0 +#define PWM1A 1 +#define FOC1B 2 +#define FOC1A 3 +#define COM1B0 4 +#define COM1B1 5 +#define COM1A0 6 +#define COM1A1 7 + +#define OSCCAL _SFR_IO8(0x31) +#define CAL0 0 +#define CAL1 1 +#define CAL2 2 +#define CAL3 3 +#define CAL4 4 +#define CAL5 5 +#define CAL6 6 +#define CAL7 7 + +#define TCNT0L _SFR_IO8(0x32) +#define TCNT0L_0 0 +#define TCNT0L_1 1 +#define TCNT0L_2 2 +#define TCNT0L_3 3 +#define TCNT0L_4 4 +#define TCNT0L_5 5 +#define TCNT0L_6 6 +#define TCNT0L_7 7 + +#define TCCR0B _SFR_IO8(0x33) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define PSR0 3 +#define TSM 4 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define ISC00 0 +#define ISC01 1 +#define BODSE 2 +#define SM0 3 +#define SM1 4 +#define SE 5 +#define PUD 6 +#define BODS 7 + +#define PRR _SFR_IO8(0x36) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn28.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef __ASSEMBLER__ +# warning "MCU not supported by the C compiler" +#endif + +/* I/O registers */ + +#define OSCCAL _SFR_IO8(0x00) + +#define WDTCR _SFR_IO8(0x01) + +#define MODCR _SFR_IO8(0x02) + +#define TCNT0 _SFR_IO8(0x03) +#define TCCR0 _SFR_IO8(0x04) + +#define IFR _SFR_IO8(0x05) +#define ICR _SFR_IO8(0x06) + +#define MCUCS _SFR_IO8(0x07) + +#define ACSR _SFR_IO8(0x08) + +/* 0x09..0x0F reserved */ + +#define PIND _SFR_IO8(0x10) +#define DDRD _SFR_IO8(0x11) +#define PORTD _SFR_IO8(0x12) + +/* 0x13..0x15 reserved */ + +#define PINB _SFR_IO8(0x16) + +/* 0x17..0x18 reserved */ + +#define PINA _SFR_IO8(0x19) +#define PACR _SFR_IO8(0x1A) +#define PORTA _SFR_IO8(0x1B) + +/* 0x1C..0x3E reserved */ + +/* 0x3F SREG */ + +/* Interrupt vectors */ + +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* External Interrupt 1 */ +#define INT1_vect_num 2 +#define INT1_vect _VECTOR(2) +#define SIG_INTERRUPT1 _VECTOR(2) + +/* Low-level Input on Port B */ +#define LOWLEVEL_IO_PINS_vect_num 3 +#define LOWLEVEL_IO_PINS_vect _VECTOR(3) +#define SIG_PIN _VECTOR(3) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 4 +#define TIMER0_OVF_vect _VECTOR(4) +#define SIG_OVERFLOW0 _VECTOR(4) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 5 +#define ANA_COMP_vect _VECTOR(5) +#define SIG_COMPARATOR _VECTOR(5) + +#define _VECTORS_SIZE 12 + + +/* Bit numbers */ + +/* ICR */ +#define INT1 7 +#define INT0 6 +#define LLIE 5 +#define TOIE0 4 +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 + +/* IFR */ +#define INTF1 7 +#define INTF0 6 +#define TOV0 4 + +/* MCUCS */ +#define PLUPB 7 +#define SE 5 +#define SM 4 +#define WDRF 3 +#define EXTRF 1 +#define PORF 0 + +/* TCCR0 */ +#define FOV0 7 +#define OOM01 4 +#define OOM00 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/* MODCR */ +#define ONTIM4 7 +#define ONTIM3 6 +#define ONTIM2 5 +#define ONTIM1 4 +#define ONTIM0 3 +#define MCONF2 2 +#define MCONF1 1 +#define MCONF0 0 + +/* WDTCR */ +#define WDTOE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* + PA2 = IR + */ + +/* PORTA */ +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +/* PACR */ +#define DDA3 3 +#define PA2HC 2 +#define DDA1 1 +#define DDA0 0 + +/* PINA */ +#define PINA3 3 +#define PINA1 1 +#define PINA0 0 + +/* + PB4 = INT1 + PB3 = INT0 + PB2 = T0 + PB1 = AIN1 + PB0 = AIN0 + */ + +/* PINB */ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +/* PORTD */ +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* DDRD */ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/* PIND */ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/* ACSR */ +#define ACD 7 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIS1 1 +#define ACIS0 0 + +#define RAMSTART 0x60 +/* Last memory addresses */ +#define RAMEND 0x1F +#define XRAMEND 0x0 +#define E2END 0x0 +#define E2PAGESIZE 0 +#define FLASHEND 0x7FF + + +/* Fuses */ + +#define FUSE_MEMORY_SIZE 1 + +/* Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_INTCAP (unsigned char)~_BV(4) +#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x91 +#define SIGNATURE_2 0x07 + + +/* Deprecated items */ +#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) + +#pragma GCC system_header + +#pragma GCC poison SIG_INTERRUPT0 +#pragma GCC poison SIG_INTERRUPT1 +#pragma GCC poison SIG_PIN +#pragma GCC poison SIG_OVERFLOW0 +#pragma GCC poison SIG_COMPARATOR + +#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ + +#define SLEEP_MODE_IDLE (0x00<<4) +#define SLEEP_MODE_PWR_DOWN (0x01<<4) + +#endif /* _AVR_IOTN28_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iotn3216.h b/hardware/tools/avr/avr/include/avr/iotn3216.h new file mode 100644 index 0000000000000000000000000000000000000000..6a460da9abd18dc6cdba5f0ea543cd11333facba --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn3216.h @@ -0,0 +1,5624 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn3216.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY3216_H_INCLUDED +#define _AVR_ATTINY3216_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ + AC_MUXNEG_DAC_gc = (0x03<<0), /* DAC output */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_PTC_gc = (0x1B<<0), /* PTC/DAC2 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0/DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor/DAC1 */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[51]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1K cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16K cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32K cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64K cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t DATA; /* DATA Register */ + register8_t reserved_1[2]; +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t ASYNCCH2; /* Asynchronous Channel 2 Generator Selection */ + register8_t ASYNCCH3; /* Asynchronous Channel 3 Generator Selection */ + register8_t reserved_1[4]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t ASYNCUSER11; /* Asynchronous User Ch 11 Input Selection - TCB1 */ + register8_t ASYNCUSER12; /* Asynchronous User Ch 12 Input Selection - ADC1 */ + register8_t reserved_3[3]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ + EVSYS_ASYNCCH0_AC1_OUT_gc = (0x13<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH0_AC2_OUT_gc = (0x14<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ + EVSYS_ASYNCCH1_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH1_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous Channel 2 Generator Selection select */ +typedef enum EVSYS_ASYNCCH2_enum +{ + EVSYS_ASYNCCH2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH2_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH2_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH2_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH2_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH2_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH2_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH2_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH2_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH2_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH2_PORTC_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PC0 */ + EVSYS_ASYNCCH2_PORTC_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PC1 */ + EVSYS_ASYNCCH2_PORTC_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PC2 */ + EVSYS_ASYNCCH2_PORTC_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PC3 */ + EVSYS_ASYNCCH2_PORTC_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PC4 */ + EVSYS_ASYNCCH2_PORTC_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PC5 */ + EVSYS_ASYNCCH2_AC1_OUT_gc = (0x10<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH2_AC2_OUT_gc = (0x11<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH2_t; + +/* Asynchronous Channel 3 Generator Selection select */ +typedef enum EVSYS_ASYNCCH3_enum +{ + EVSYS_ASYNCCH3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH3_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH3_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH3_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH3_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter type D compare B clear */ + EVSYS_ASYNCCH3_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter type D compare A set */ + EVSYS_ASYNCCH3_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter type D compare B set */ + EVSYS_ASYNCCH3_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter type D program event */ + EVSYS_ASYNCCH3_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH3_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH3_PIT_DIV8192_gc = (0x0A<<0), /* Periodic Interrupt CLK_RTC div 8192 */ + EVSYS_ASYNCCH3_PIT_DIV4096_gc = (0x0B<<0), /* Periodic Interrupt CLK_RTC div 4096 */ + EVSYS_ASYNCCH3_PIT_DIV2048_gc = (0x0C<<0), /* Periodic Interrupt CLK_RTC div 2048 */ + EVSYS_ASYNCCH3_PIT_DIV1024_gc = (0x0D<<0), /* Periodic Interrupt CLK_RTC div 1024 */ + EVSYS_ASYNCCH3_PIT_DIV512_gc = (0x0E<<0), /* Periodic Interrupt CLK_RTC div 512 */ + EVSYS_ASYNCCH3_PIT_DIV256_gc = (0x0F<<0), /* Periodic Interrupt CLK_RTC div 256 */ + EVSYS_ASYNCCH3_PIT_DIV128_gc = (0x10<<0), /* Periodic Interrupt CLK_RTC div 128 */ + EVSYS_ASYNCCH3_PIT_DIV64_gc = (0x11<<0), /* Periodic Interrupt CLK_RTC div 64 */ + EVSYS_ASYNCCH3_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH3_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH3_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 11 Input Selection - TCB1 select */ +typedef enum EVSYS_ASYNCUSER11_enum +{ + EVSYS_ASYNCUSER11_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER11_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER11_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER11_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER11_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER11_t; + +/* Asynchronous User Ch 12 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER12_enum +{ + EVSYS_ASYNCUSER12_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER12_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER12_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER12_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER12_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER12_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ + EVSYS_SYNCCH0_TCB1_gc = (0x15<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ + EVSYS_SYNCCH1_TCB1_gc = (0x10<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB0 select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TCB1 select */ +typedef enum PORTMUX_TCB1_enum +{ + PORTMUX_TCB1_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCB1_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCB1_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_20MHZ_gc = (0x00<<5), /* 20 MHz oscillator */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External clock */ + TCD_CLKSEL_SYSCLK_gc = (0x03<<5), /* System clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Synchronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selected clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selected clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selected clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selected clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ + register8_t USERROW32; /* User Row Byte 32 */ + register8_t USERROW33; /* User Row Byte 33 */ + register8_t USERROW34; /* User Row Byte 34 */ + register8_t USERROW35; /* User Row Byte 35 */ + register8_t USERROW36; /* User Row Byte 36 */ + register8_t USERROW37; /* User Row Byte 37 */ + register8_t USERROW38; /* User Row Byte 38 */ + register8_t USERROW39; /* User Row Byte 39 */ + register8_t USERROW40; /* User Row Byte 40 */ + register8_t USERROW41; /* User Row Byte 41 */ + register8_t USERROW42; /* User Row Byte 42 */ + register8_t USERROW43; /* User Row Byte 43 */ + register8_t USERROW44; /* User Row Byte 44 */ + register8_t USERROW45; /* User Row Byte 45 */ + register8_t USERROW46; /* User Row Byte 46 */ + register8_t USERROW47; /* User Row Byte 47 */ + register8_t USERROW48; /* User Row Byte 48 */ + register8_t USERROW49; /* User Row Byte 49 */ + register8_t USERROW50; /* User Row Byte 50 */ + register8_t USERROW51; /* User Row Byte 51 */ + register8_t USERROW52; /* User Row Byte 52 */ + register8_t USERROW53; /* User Row Byte 53 */ + register8_t USERROW54; /* User Row Byte 54 */ + register8_t USERROW55; /* User Row Byte 55 */ + register8_t USERROW56; /* User Row Byte 56 */ + register8_t USERROW57; /* User Row Byte 57 */ + register8_t USERROW58; /* User Row Byte 58 */ + register8_t USERROW59; /* User Row Byte 59 */ + register8_t USERROW60; /* User Row Byte 60 */ + register8_t USERROW61; /* User Row Byte 61 */ + register8_t USERROW62; /* User Row Byte 62 */ + register8_t USERROW63; /* User Row Byte 63 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* ADC1 reference select select */ +typedef enum VREF_ADC1REFSEL_enum +{ + VREF_ADC1REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC1REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC1REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC1REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC1REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC1REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* DAC1/AC1 reference select select */ +typedef enum VREF_DAC1REFSEL_enum +{ + VREF_DAC1REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC1REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC1REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC1REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC1REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC1REFSEL_t; + +/* DAC2/AC2 reference select select */ +typedef enum VREF_DAC2REFSEL_enum +{ + VREF_DAC2REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC2REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC2REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC2REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC2REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC2REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define ADC1 (*(ADC_t *) 0x0640) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define AC1 (*(AC_t *) 0x0688) /* Analog Comparator */ +#define AC2 (*(AC_t *) 0x0690) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x06A0) /* Digital to Analog Converter */ +#define DAC1 (*(DAC_t *) 0x06A8) /* Digital to Analog Converter */ +#define DAC2 (*(DAC_t *) 0x06B0) /* Digital to Analog Converter */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0A50) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0A80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) +#define VREF_CTRLC _SFR_MEM8(0x00A2) +#define VREF_CTRLD _SFR_MEM8(0x00A3) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_ASYNCCH2 _SFR_MEM8(0x0184) +#define EVSYS_ASYNCCH3 _SFR_MEM8(0x0185) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_ASYNCUSER11 _SFR_MEM8(0x019D) +#define EVSYS_ASYNCUSER12 _SFR_MEM8(0x019E) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* ADC (ADC1) - Analog to Digital Converter */ +#define ADC1_CTRLA _SFR_MEM8(0x0640) +#define ADC1_CTRLB _SFR_MEM8(0x0641) +#define ADC1_CTRLC _SFR_MEM8(0x0642) +#define ADC1_CTRLD _SFR_MEM8(0x0643) +#define ADC1_CTRLE _SFR_MEM8(0x0644) +#define ADC1_SAMPCTRL _SFR_MEM8(0x0645) +#define ADC1_MUXPOS _SFR_MEM8(0x0646) +#define ADC1_COMMAND _SFR_MEM8(0x0648) +#define ADC1_EVCTRL _SFR_MEM8(0x0649) +#define ADC1_INTCTRL _SFR_MEM8(0x064A) +#define ADC1_INTFLAGS _SFR_MEM8(0x064B) +#define ADC1_DBGCTRL _SFR_MEM8(0x064C) +#define ADC1_TEMP _SFR_MEM8(0x064D) +#define ADC1_RES _SFR_MEM16(0x0650) +#define ADC1_RESL _SFR_MEM8(0x0650) +#define ADC1_RESH _SFR_MEM8(0x0651) +#define ADC1_WINLT _SFR_MEM16(0x0652) +#define ADC1_WINLTL _SFR_MEM8(0x0652) +#define ADC1_WINLTH _SFR_MEM8(0x0653) +#define ADC1_WINHT _SFR_MEM16(0x0654) +#define ADC1_WINHTL _SFR_MEM8(0x0654) +#define ADC1_WINHTH _SFR_MEM8(0x0655) +#define ADC1_CALIB _SFR_MEM8(0x0656) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* AC (AC1) - Analog Comparator */ +#define AC1_CTRLA _SFR_MEM8(0x0688) +#define AC1_MUXCTRLA _SFR_MEM8(0x068A) +#define AC1_INTCTRL _SFR_MEM8(0x068E) +#define AC1_STATUS _SFR_MEM8(0x068F) + + +/* AC (AC2) - Analog Comparator */ +#define AC2_CTRLA _SFR_MEM8(0x0690) +#define AC2_MUXCTRLA _SFR_MEM8(0x0692) +#define AC2_INTCTRL _SFR_MEM8(0x0696) +#define AC2_STATUS _SFR_MEM8(0x0697) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x06A0) +#define DAC0_DATA _SFR_MEM8(0x06A1) + + +/* DAC (DAC1) - Digital to Analog Converter */ +#define DAC1_CTRLA _SFR_MEM8(0x06A8) +#define DAC1_DATA _SFR_MEM8(0x06A9) + + +/* DAC (DAC2) - Digital to Analog Converter */ +#define DAC2_CTRLA _SFR_MEM8(0x06B0) +#define DAC2_DATA _SFR_MEM8(0x06B1) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0A50) +#define TCB1_CTRLB _SFR_MEM8(0x0A51) +#define TCB1_EVCTRL _SFR_MEM8(0x0A54) +#define TCB1_INTCTRL _SFR_MEM8(0x0A55) +#define TCB1_INTFLAGS _SFR_MEM8(0x0A56) +#define TCB1_STATUS _SFR_MEM8(0x0A57) +#define TCB1_DBGCTRL _SFR_MEM8(0x0A58) +#define TCB1_TEMP _SFR_MEM8(0x0A59) +#define TCB1_CNT _SFR_MEM16(0x0A5A) +#define TCB1_CNTL _SFR_MEM8(0x0A5A) +#define TCB1_CNTH _SFR_MEM8(0x0A5B) +#define TCB1_CCMP _SFR_MEM16(0x0A5C) +#define TCB1_CCMPL _SFR_MEM8(0x0A5C) +#define TCB1_CCMPH _SFR_MEM8(0x0A5D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0A80) +#define TCD0_CTRLB _SFR_MEM8(0x0A81) +#define TCD0_CTRLC _SFR_MEM8(0x0A82) +#define TCD0_CTRLD _SFR_MEM8(0x0A83) +#define TCD0_CTRLE _SFR_MEM8(0x0A84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0A88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0A89) +#define TCD0_INTCTRL _SFR_MEM8(0x0A8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0A8D) +#define TCD0_STATUS _SFR_MEM8(0x0A8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0A90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0A91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0A92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0A94) +#define TCD0_DLYVAL _SFR_MEM8(0x0A95) +#define TCD0_DITCTRL _SFR_MEM8(0x0A98) +#define TCD0_DITVAL _SFR_MEM8(0x0A99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0A9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0AA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0AA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0AA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0AA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0AA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0AA5) +#define TCD0_CMPASET _SFR_MEM16(0x0AA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0AA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0AA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0AAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0AAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0AAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0AAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0AAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0AAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0AAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0AAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0AAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) +#define USERROW_USERROW32 _SFR_MEM8(0x1320) +#define USERROW_USERROW33 _SFR_MEM8(0x1321) +#define USERROW_USERROW34 _SFR_MEM8(0x1322) +#define USERROW_USERROW35 _SFR_MEM8(0x1323) +#define USERROW_USERROW36 _SFR_MEM8(0x1324) +#define USERROW_USERROW37 _SFR_MEM8(0x1325) +#define USERROW_USERROW38 _SFR_MEM8(0x1326) +#define USERROW_USERROW39 _SFR_MEM8(0x1327) +#define USERROW_USERROW40 _SFR_MEM8(0x1328) +#define USERROW_USERROW41 _SFR_MEM8(0x1329) +#define USERROW_USERROW42 _SFR_MEM8(0x132A) +#define USERROW_USERROW43 _SFR_MEM8(0x132B) +#define USERROW_USERROW44 _SFR_MEM8(0x132C) +#define USERROW_USERROW45 _SFR_MEM8(0x132D) +#define USERROW_USERROW46 _SFR_MEM8(0x132E) +#define USERROW_USERROW47 _SFR_MEM8(0x132F) +#define USERROW_USERROW48 _SFR_MEM8(0x1330) +#define USERROW_USERROW49 _SFR_MEM8(0x1331) +#define USERROW_USERROW50 _SFR_MEM8(0x1332) +#define USERROW_USERROW51 _SFR_MEM8(0x1333) +#define USERROW_USERROW52 _SFR_MEM8(0x1334) +#define USERROW_USERROW53 _SFR_MEM8(0x1335) +#define USERROW_USERROW54 _SFR_MEM8(0x1336) +#define USERROW_USERROW55 _SFR_MEM8(0x1337) +#define USERROW_USERROW56 _SFR_MEM8(0x1338) +#define USERROW_USERROW57 _SFR_MEM8(0x1339) +#define USERROW_USERROW58 _SFR_MEM8(0x133A) +#define USERROW_USERROW59 _SFR_MEM8(0x133B) +#define USERROW_USERROW60 _SFR_MEM8(0x133C) +#define USERROW_USERROW61 _SFR_MEM8(0x133D) +#define USERROW_USERROW62 _SFR_MEM8(0x133E) +#define USERROW_USERROW63 _SFR_MEM8(0x133F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH2 bit masks and bit positions */ +#define EVSYS_ASYNCCH2_gm 0xFF /* Asynchronous Channel 2 Generator Selection group mask. */ +#define EVSYS_ASYNCCH2_gp 0 /* Asynchronous Channel 2 Generator Selection group position. */ +#define EVSYS_ASYNCCH20_bm (1<<0) /* Asynchronous Channel 2 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH20_bp 0 /* Asynchronous Channel 2 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH21_bm (1<<1) /* Asynchronous Channel 2 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH21_bp 1 /* Asynchronous Channel 2 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH22_bm (1<<2) /* Asynchronous Channel 2 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH22_bp 2 /* Asynchronous Channel 2 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH23_bm (1<<3) /* Asynchronous Channel 2 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH23_bp 3 /* Asynchronous Channel 2 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH24_bm (1<<4) /* Asynchronous Channel 2 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH24_bp 4 /* Asynchronous Channel 2 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH25_bm (1<<5) /* Asynchronous Channel 2 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH25_bp 5 /* Asynchronous Channel 2 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH26_bm (1<<6) /* Asynchronous Channel 2 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH26_bp 6 /* Asynchronous Channel 2 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH27_bm (1<<7) /* Asynchronous Channel 2 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH27_bp 7 /* Asynchronous Channel 2 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH3 bit masks and bit positions */ +#define EVSYS_ASYNCCH3_gm 0xFF /* Asynchronous Channel 3 Generator Selection group mask. */ +#define EVSYS_ASYNCCH3_gp 0 /* Asynchronous Channel 3 Generator Selection group position. */ +#define EVSYS_ASYNCCH30_bm (1<<0) /* Asynchronous Channel 3 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH30_bp 0 /* Asynchronous Channel 3 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH31_bm (1<<1) /* Asynchronous Channel 3 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH31_bp 1 /* Asynchronous Channel 3 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH32_bm (1<<2) /* Asynchronous Channel 3 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH32_bp 2 /* Asynchronous Channel 3 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH33_bm (1<<3) /* Asynchronous Channel 3 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH33_bp 3 /* Asynchronous Channel 3 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH34_bm (1<<4) /* Asynchronous Channel 3 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH34_bp 4 /* Asynchronous Channel 3 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH35_bm (1<<5) /* Asynchronous Channel 3 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH35_bp 5 /* Asynchronous Channel 3 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH36_bm (1<<6) /* Asynchronous Channel 3 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH36_bp 6 /* Asynchronous Channel 3 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH37_bm (1<<7) /* Asynchronous Channel 3 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH37_bp 7 /* Asynchronous Channel 3 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.ASYNCUSER11 bit masks and bit positions */ +#define EVSYS_ASYNCUSER11_gm 0xFF /* Asynchronous User Ch 11 Input Selection - TCB1 group mask. */ +#define EVSYS_ASYNCUSER11_gp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 group position. */ +#define EVSYS_ASYNCUSER110_bm (1<<0) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 mask. */ +#define EVSYS_ASYNCUSER110_bp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 position. */ +#define EVSYS_ASYNCUSER111_bm (1<<1) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 mask. */ +#define EVSYS_ASYNCUSER111_bp 1 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 position. */ +#define EVSYS_ASYNCUSER112_bm (1<<2) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 mask. */ +#define EVSYS_ASYNCUSER112_bp 2 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 position. */ +#define EVSYS_ASYNCUSER113_bm (1<<3) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 mask. */ +#define EVSYS_ASYNCUSER113_bp 3 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 position. */ +#define EVSYS_ASYNCUSER114_bm (1<<4) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 mask. */ +#define EVSYS_ASYNCUSER114_bp 4 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 position. */ +#define EVSYS_ASYNCUSER115_bm (1<<5) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 mask. */ +#define EVSYS_ASYNCUSER115_bp 5 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 position. */ +#define EVSYS_ASYNCUSER116_bm (1<<6) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 mask. */ +#define EVSYS_ASYNCUSER116_bp 6 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 position. */ +#define EVSYS_ASYNCUSER117_bm (1<<7) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 mask. */ +#define EVSYS_ASYNCUSER117_bp 7 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 position. */ + +/* EVSYS.ASYNCUSER12 bit masks and bit positions */ +#define EVSYS_ASYNCUSER12_gm 0xFF /* Asynchronous User Ch 12 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER12_gp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER120_bm (1<<0) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER120_bp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER121_bm (1<<1) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER121_bp 1 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER122_bm (1<<2) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER122_bp 2 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER123_bm (1<<3) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER123_bp 3 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER124_bm (1<<4) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER124_bp 4 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER125_bm (1<<5) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER125_bp 5 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER126_bm (1<<6) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER126_bp 6 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER127_bm (1<<7) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER127_bp 7 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ +#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Synchronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Synchronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Synchronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Synchronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Synchronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Synchronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ +#define VREF_DAC1REFEN_bm 0x08 /* DAC1/AC1 reference enable bit mask. */ +#define VREF_DAC1REFEN_bp 3 /* DAC1/AC1 reference enable bit position. */ +#define VREF_ADC1REFEN_bm 0x10 /* ADC1 reference enable bit mask. */ +#define VREF_ADC1REFEN_bp 4 /* ADC1 reference enable bit position. */ +#define VREF_DAC2REFEN_bm 0x20 /* DAC2/AC2 reference enable bit mask. */ +#define VREF_DAC2REFEN_bp 5 /* DAC2/AC2 reference enable bit position. */ + +/* VREF.CTRLC bit masks and bit positions */ +#define VREF_DAC1REFSEL_gm 0x07 /* DAC1/AC1 reference select group mask. */ +#define VREF_DAC1REFSEL_gp 0 /* DAC1/AC1 reference select group position. */ +#define VREF_DAC1REFSEL0_bm (1<<0) /* DAC1/AC1 reference select bit 0 mask. */ +#define VREF_DAC1REFSEL0_bp 0 /* DAC1/AC1 reference select bit 0 position. */ +#define VREF_DAC1REFSEL1_bm (1<<1) /* DAC1/AC1 reference select bit 1 mask. */ +#define VREF_DAC1REFSEL1_bp 1 /* DAC1/AC1 reference select bit 1 position. */ +#define VREF_DAC1REFSEL2_bm (1<<2) /* DAC1/AC1 reference select bit 2 mask. */ +#define VREF_DAC1REFSEL2_bp 2 /* DAC1/AC1 reference select bit 2 position. */ +#define VREF_ADC1REFSEL_gm 0x70 /* ADC1 reference select group mask. */ +#define VREF_ADC1REFSEL_gp 4 /* ADC1 reference select group position. */ +#define VREF_ADC1REFSEL0_bm (1<<4) /* ADC1 reference select bit 0 mask. */ +#define VREF_ADC1REFSEL0_bp 4 /* ADC1 reference select bit 0 position. */ +#define VREF_ADC1REFSEL1_bm (1<<5) /* ADC1 reference select bit 1 mask. */ +#define VREF_ADC1REFSEL1_bp 5 /* ADC1 reference select bit 1 position. */ +#define VREF_ADC1REFSEL2_bm (1<<6) /* ADC1 reference select bit 2 mask. */ +#define VREF_ADC1REFSEL2_bp 6 /* ADC1 reference select bit 2 position. */ + +/* VREF.CTRLD bit masks and bit positions */ +#define VREF_DAC2REFSEL_gm 0x07 /* DAC2/AC2 reference select group mask. */ +#define VREF_DAC2REFSEL_gp 0 /* DAC2/AC2 reference select group position. */ +#define VREF_DAC2REFSEL0_bm (1<<0) /* DAC2/AC2 reference select bit 0 mask. */ +#define VREF_DAC2REFSEL0_bp 0 /* DAC2/AC2 reference select bit 0 position. */ +#define VREF_DAC2REFSEL1_bm (1<<1) /* DAC2/AC2 reference select bit 1 mask. */ +#define VREF_DAC2REFSEL1_bp 1 /* DAC2/AC2 reference select bit 1 position. */ +#define VREF_DAC2REFSEL2_bm (1<<2) /* DAC2/AC2 reference select bit 2 mask. */ +#define VREF_DAC2REFSEL2_bp 2 /* DAC2/AC2 reference select bit 2 position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 5 +#define PORTC_PORT_vect _VECTOR(5) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 14 +#define TCB1_INT_vect _VECTOR(14) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 15 +#define TCD0_OVF_vect _VECTOR(15) /* */ +#define TCD0_TRIG_vect_num 16 +#define TCD0_TRIG_vect _VECTOR(16) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 17 +#define AC0_AC_vect _VECTOR(17) /* */ + +/* AC1 interrupt vectors */ +#define AC1_AC_vect_num 18 +#define AC1_AC_vect _VECTOR(18) /* */ + +/* AC2 interrupt vectors */ +#define AC2_AC_vect_num 19 +#define AC2_AC_vect _VECTOR(19) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 20 +#define ADC0_RESRDY_vect _VECTOR(20) /* */ +#define ADC0_WCOMP_vect_num 21 +#define ADC0_WCOMP_vect _VECTOR(21) /* */ + +/* ADC1 interrupt vectors */ +#define ADC1_RESRDY_vect_num 22 +#define ADC1_RESRDY_vect _VECTOR(22) /* */ +#define ADC1_WCOMP_vect_num 23 +#define ADC1_WCOMP_vect _VECTOR(23) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 24 +#define TWI0_TWIS_vect _VECTOR(24) /* */ +#define TWI0_TWIM_vect_num 25 +#define TWI0_TWIM_vect _VECTOR(25) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 26 +#define SPI0_INT_vect _VECTOR(26) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 27 +#define USART0_RXC_vect _VECTOR(27) /* */ +#define USART0_DRE_vect_num 28 +#define USART0_DRE_vect _VECTOR(28) /* */ +#define USART0_TXC_vect_num 29 +#define USART0_TXC_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (31 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (65536) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (65536U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (64) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (64U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (64) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (64U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3800) +# define INTERNAL_SRAM_SIZE (2048) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3800U) +# define INTERNAL_SRAM_SIZE (2048U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (64) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (64U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (32768) +# define MAPPED_PROGMEM_PAGE_SIZE (128) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (32768U) +# define MAPPED_PROGMEM_PAGE_SIZE (128U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (128) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (128U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (128) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (128U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (64) +# define USER_SIGNATURES_PAGE_SIZE (64) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (64U) +# define USER_SIGNATURES_PAGE_SIZE (64U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (32768) +# define PROGMEM_PAGE_SIZE (128) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (32768U) +# define PROGMEM_PAGE_SIZE (128U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x21 + + +#endif /* #ifdef _AVR_ATTINY3216_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn3217.h b/hardware/tools/avr/avr/include/avr/iotn3217.h new file mode 100644 index 0000000000000000000000000000000000000000..a40244625d06dfeea16a4873f159f1387ef87b5a --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn3217.h @@ -0,0 +1,5624 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn3217.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY3217_H_INCLUDED +#define _AVR_ATTINY3217_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ + AC_MUXNEG_DAC_gc = (0x03<<0), /* DAC output */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_PTC_gc = (0x1B<<0), /* PTC/DAC2 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0/DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor/DAC1 */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[51]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1K cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16K cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32K cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64K cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t DATA; /* DATA Register */ + register8_t reserved_1[2]; +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t ASYNCCH2; /* Asynchronous Channel 2 Generator Selection */ + register8_t ASYNCCH3; /* Asynchronous Channel 3 Generator Selection */ + register8_t reserved_1[4]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t ASYNCUSER11; /* Asynchronous User Ch 11 Input Selection - TCB1 */ + register8_t ASYNCUSER12; /* Asynchronous User Ch 12 Input Selection - ADC1 */ + register8_t reserved_3[3]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ + EVSYS_ASYNCCH0_AC1_OUT_gc = (0x13<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH0_AC2_OUT_gc = (0x14<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ + EVSYS_ASYNCCH1_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH1_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous Channel 2 Generator Selection select */ +typedef enum EVSYS_ASYNCCH2_enum +{ + EVSYS_ASYNCCH2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH2_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH2_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH2_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH2_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH2_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH2_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH2_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH2_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH2_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH2_PORTC_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PC0 */ + EVSYS_ASYNCCH2_PORTC_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PC1 */ + EVSYS_ASYNCCH2_PORTC_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PC2 */ + EVSYS_ASYNCCH2_PORTC_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PC3 */ + EVSYS_ASYNCCH2_PORTC_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PC4 */ + EVSYS_ASYNCCH2_PORTC_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PC5 */ + EVSYS_ASYNCCH2_AC1_OUT_gc = (0x10<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH2_AC2_OUT_gc = (0x11<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH2_t; + +/* Asynchronous Channel 3 Generator Selection select */ +typedef enum EVSYS_ASYNCCH3_enum +{ + EVSYS_ASYNCCH3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH3_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH3_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH3_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH3_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter type D compare B clear */ + EVSYS_ASYNCCH3_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter type D compare A set */ + EVSYS_ASYNCCH3_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter type D compare B set */ + EVSYS_ASYNCCH3_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter type D program event */ + EVSYS_ASYNCCH3_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH3_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH3_PIT_DIV8192_gc = (0x0A<<0), /* Periodic Interrupt CLK_RTC div 8192 */ + EVSYS_ASYNCCH3_PIT_DIV4096_gc = (0x0B<<0), /* Periodic Interrupt CLK_RTC div 4096 */ + EVSYS_ASYNCCH3_PIT_DIV2048_gc = (0x0C<<0), /* Periodic Interrupt CLK_RTC div 2048 */ + EVSYS_ASYNCCH3_PIT_DIV1024_gc = (0x0D<<0), /* Periodic Interrupt CLK_RTC div 1024 */ + EVSYS_ASYNCCH3_PIT_DIV512_gc = (0x0E<<0), /* Periodic Interrupt CLK_RTC div 512 */ + EVSYS_ASYNCCH3_PIT_DIV256_gc = (0x0F<<0), /* Periodic Interrupt CLK_RTC div 256 */ + EVSYS_ASYNCCH3_PIT_DIV128_gc = (0x10<<0), /* Periodic Interrupt CLK_RTC div 128 */ + EVSYS_ASYNCCH3_PIT_DIV64_gc = (0x11<<0), /* Periodic Interrupt CLK_RTC div 64 */ + EVSYS_ASYNCCH3_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH3_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH3_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 11 Input Selection - TCB1 select */ +typedef enum EVSYS_ASYNCUSER11_enum +{ + EVSYS_ASYNCUSER11_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER11_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER11_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER11_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER11_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER11_t; + +/* Asynchronous User Ch 12 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER12_enum +{ + EVSYS_ASYNCUSER12_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER12_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER12_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER12_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER12_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER12_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ + EVSYS_SYNCCH0_TCB1_gc = (0x15<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ + EVSYS_SYNCCH1_TCB1_gc = (0x10<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB0 select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TCB1 select */ +typedef enum PORTMUX_TCB1_enum +{ + PORTMUX_TCB1_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCB1_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCB1_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_20MHZ_gc = (0x00<<5), /* 20 MHz oscillator */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External clock */ + TCD_CLKSEL_SYSCLK_gc = (0x03<<5), /* System clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Synchronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selected clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selected clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selected clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selected clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ + register8_t USERROW32; /* User Row Byte 32 */ + register8_t USERROW33; /* User Row Byte 33 */ + register8_t USERROW34; /* User Row Byte 34 */ + register8_t USERROW35; /* User Row Byte 35 */ + register8_t USERROW36; /* User Row Byte 36 */ + register8_t USERROW37; /* User Row Byte 37 */ + register8_t USERROW38; /* User Row Byte 38 */ + register8_t USERROW39; /* User Row Byte 39 */ + register8_t USERROW40; /* User Row Byte 40 */ + register8_t USERROW41; /* User Row Byte 41 */ + register8_t USERROW42; /* User Row Byte 42 */ + register8_t USERROW43; /* User Row Byte 43 */ + register8_t USERROW44; /* User Row Byte 44 */ + register8_t USERROW45; /* User Row Byte 45 */ + register8_t USERROW46; /* User Row Byte 46 */ + register8_t USERROW47; /* User Row Byte 47 */ + register8_t USERROW48; /* User Row Byte 48 */ + register8_t USERROW49; /* User Row Byte 49 */ + register8_t USERROW50; /* User Row Byte 50 */ + register8_t USERROW51; /* User Row Byte 51 */ + register8_t USERROW52; /* User Row Byte 52 */ + register8_t USERROW53; /* User Row Byte 53 */ + register8_t USERROW54; /* User Row Byte 54 */ + register8_t USERROW55; /* User Row Byte 55 */ + register8_t USERROW56; /* User Row Byte 56 */ + register8_t USERROW57; /* User Row Byte 57 */ + register8_t USERROW58; /* User Row Byte 58 */ + register8_t USERROW59; /* User Row Byte 59 */ + register8_t USERROW60; /* User Row Byte 60 */ + register8_t USERROW61; /* User Row Byte 61 */ + register8_t USERROW62; /* User Row Byte 62 */ + register8_t USERROW63; /* User Row Byte 63 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* ADC1 reference select select */ +typedef enum VREF_ADC1REFSEL_enum +{ + VREF_ADC1REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC1REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC1REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC1REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC1REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC1REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* DAC1/AC1 reference select select */ +typedef enum VREF_DAC1REFSEL_enum +{ + VREF_DAC1REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC1REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC1REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC1REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC1REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC1REFSEL_t; + +/* DAC2/AC2 reference select select */ +typedef enum VREF_DAC2REFSEL_enum +{ + VREF_DAC2REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC2REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC2REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC2REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC2REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC2REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define ADC1 (*(ADC_t *) 0x0640) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define AC1 (*(AC_t *) 0x0688) /* Analog Comparator */ +#define AC2 (*(AC_t *) 0x0690) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x06A0) /* Digital to Analog Converter */ +#define DAC1 (*(DAC_t *) 0x06A8) /* Digital to Analog Converter */ +#define DAC2 (*(DAC_t *) 0x06B0) /* Digital to Analog Converter */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define TCB1 (*(TCB_t *) 0x0A50) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0A80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) +#define VREF_CTRLC _SFR_MEM8(0x00A2) +#define VREF_CTRLD _SFR_MEM8(0x00A3) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_ASYNCCH2 _SFR_MEM8(0x0184) +#define EVSYS_ASYNCCH3 _SFR_MEM8(0x0185) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_ASYNCUSER11 _SFR_MEM8(0x019D) +#define EVSYS_ASYNCUSER12 _SFR_MEM8(0x019E) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* ADC (ADC1) - Analog to Digital Converter */ +#define ADC1_CTRLA _SFR_MEM8(0x0640) +#define ADC1_CTRLB _SFR_MEM8(0x0641) +#define ADC1_CTRLC _SFR_MEM8(0x0642) +#define ADC1_CTRLD _SFR_MEM8(0x0643) +#define ADC1_CTRLE _SFR_MEM8(0x0644) +#define ADC1_SAMPCTRL _SFR_MEM8(0x0645) +#define ADC1_MUXPOS _SFR_MEM8(0x0646) +#define ADC1_COMMAND _SFR_MEM8(0x0648) +#define ADC1_EVCTRL _SFR_MEM8(0x0649) +#define ADC1_INTCTRL _SFR_MEM8(0x064A) +#define ADC1_INTFLAGS _SFR_MEM8(0x064B) +#define ADC1_DBGCTRL _SFR_MEM8(0x064C) +#define ADC1_TEMP _SFR_MEM8(0x064D) +#define ADC1_RES _SFR_MEM16(0x0650) +#define ADC1_RESL _SFR_MEM8(0x0650) +#define ADC1_RESH _SFR_MEM8(0x0651) +#define ADC1_WINLT _SFR_MEM16(0x0652) +#define ADC1_WINLTL _SFR_MEM8(0x0652) +#define ADC1_WINLTH _SFR_MEM8(0x0653) +#define ADC1_WINHT _SFR_MEM16(0x0654) +#define ADC1_WINHTL _SFR_MEM8(0x0654) +#define ADC1_WINHTH _SFR_MEM8(0x0655) +#define ADC1_CALIB _SFR_MEM8(0x0656) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* AC (AC1) - Analog Comparator */ +#define AC1_CTRLA _SFR_MEM8(0x0688) +#define AC1_MUXCTRLA _SFR_MEM8(0x068A) +#define AC1_INTCTRL _SFR_MEM8(0x068E) +#define AC1_STATUS _SFR_MEM8(0x068F) + + +/* AC (AC2) - Analog Comparator */ +#define AC2_CTRLA _SFR_MEM8(0x0690) +#define AC2_MUXCTRLA _SFR_MEM8(0x0692) +#define AC2_INTCTRL _SFR_MEM8(0x0696) +#define AC2_STATUS _SFR_MEM8(0x0697) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x06A0) +#define DAC0_DATA _SFR_MEM8(0x06A1) + + +/* DAC (DAC1) - Digital to Analog Converter */ +#define DAC1_CTRLA _SFR_MEM8(0x06A8) +#define DAC1_DATA _SFR_MEM8(0x06A9) + + +/* DAC (DAC2) - Digital to Analog Converter */ +#define DAC2_CTRLA _SFR_MEM8(0x06B0) +#define DAC2_DATA _SFR_MEM8(0x06B1) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* TCB (TCB1) - 16-bit Timer Type B */ +#define TCB1_CTRLA _SFR_MEM8(0x0A50) +#define TCB1_CTRLB _SFR_MEM8(0x0A51) +#define TCB1_EVCTRL _SFR_MEM8(0x0A54) +#define TCB1_INTCTRL _SFR_MEM8(0x0A55) +#define TCB1_INTFLAGS _SFR_MEM8(0x0A56) +#define TCB1_STATUS _SFR_MEM8(0x0A57) +#define TCB1_DBGCTRL _SFR_MEM8(0x0A58) +#define TCB1_TEMP _SFR_MEM8(0x0A59) +#define TCB1_CNT _SFR_MEM16(0x0A5A) +#define TCB1_CNTL _SFR_MEM8(0x0A5A) +#define TCB1_CNTH _SFR_MEM8(0x0A5B) +#define TCB1_CCMP _SFR_MEM16(0x0A5C) +#define TCB1_CCMPL _SFR_MEM8(0x0A5C) +#define TCB1_CCMPH _SFR_MEM8(0x0A5D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0A80) +#define TCD0_CTRLB _SFR_MEM8(0x0A81) +#define TCD0_CTRLC _SFR_MEM8(0x0A82) +#define TCD0_CTRLD _SFR_MEM8(0x0A83) +#define TCD0_CTRLE _SFR_MEM8(0x0A84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0A88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0A89) +#define TCD0_INTCTRL _SFR_MEM8(0x0A8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0A8D) +#define TCD0_STATUS _SFR_MEM8(0x0A8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0A90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0A91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0A92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0A94) +#define TCD0_DLYVAL _SFR_MEM8(0x0A95) +#define TCD0_DITCTRL _SFR_MEM8(0x0A98) +#define TCD0_DITVAL _SFR_MEM8(0x0A99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0A9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0AA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0AA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0AA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0AA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0AA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0AA5) +#define TCD0_CMPASET _SFR_MEM16(0x0AA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0AA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0AA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0AAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0AAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0AAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0AAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0AAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0AAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0AAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0AAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0AAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) +#define USERROW_USERROW32 _SFR_MEM8(0x1320) +#define USERROW_USERROW33 _SFR_MEM8(0x1321) +#define USERROW_USERROW34 _SFR_MEM8(0x1322) +#define USERROW_USERROW35 _SFR_MEM8(0x1323) +#define USERROW_USERROW36 _SFR_MEM8(0x1324) +#define USERROW_USERROW37 _SFR_MEM8(0x1325) +#define USERROW_USERROW38 _SFR_MEM8(0x1326) +#define USERROW_USERROW39 _SFR_MEM8(0x1327) +#define USERROW_USERROW40 _SFR_MEM8(0x1328) +#define USERROW_USERROW41 _SFR_MEM8(0x1329) +#define USERROW_USERROW42 _SFR_MEM8(0x132A) +#define USERROW_USERROW43 _SFR_MEM8(0x132B) +#define USERROW_USERROW44 _SFR_MEM8(0x132C) +#define USERROW_USERROW45 _SFR_MEM8(0x132D) +#define USERROW_USERROW46 _SFR_MEM8(0x132E) +#define USERROW_USERROW47 _SFR_MEM8(0x132F) +#define USERROW_USERROW48 _SFR_MEM8(0x1330) +#define USERROW_USERROW49 _SFR_MEM8(0x1331) +#define USERROW_USERROW50 _SFR_MEM8(0x1332) +#define USERROW_USERROW51 _SFR_MEM8(0x1333) +#define USERROW_USERROW52 _SFR_MEM8(0x1334) +#define USERROW_USERROW53 _SFR_MEM8(0x1335) +#define USERROW_USERROW54 _SFR_MEM8(0x1336) +#define USERROW_USERROW55 _SFR_MEM8(0x1337) +#define USERROW_USERROW56 _SFR_MEM8(0x1338) +#define USERROW_USERROW57 _SFR_MEM8(0x1339) +#define USERROW_USERROW58 _SFR_MEM8(0x133A) +#define USERROW_USERROW59 _SFR_MEM8(0x133B) +#define USERROW_USERROW60 _SFR_MEM8(0x133C) +#define USERROW_USERROW61 _SFR_MEM8(0x133D) +#define USERROW_USERROW62 _SFR_MEM8(0x133E) +#define USERROW_USERROW63 _SFR_MEM8(0x133F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH2 bit masks and bit positions */ +#define EVSYS_ASYNCCH2_gm 0xFF /* Asynchronous Channel 2 Generator Selection group mask. */ +#define EVSYS_ASYNCCH2_gp 0 /* Asynchronous Channel 2 Generator Selection group position. */ +#define EVSYS_ASYNCCH20_bm (1<<0) /* Asynchronous Channel 2 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH20_bp 0 /* Asynchronous Channel 2 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH21_bm (1<<1) /* Asynchronous Channel 2 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH21_bp 1 /* Asynchronous Channel 2 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH22_bm (1<<2) /* Asynchronous Channel 2 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH22_bp 2 /* Asynchronous Channel 2 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH23_bm (1<<3) /* Asynchronous Channel 2 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH23_bp 3 /* Asynchronous Channel 2 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH24_bm (1<<4) /* Asynchronous Channel 2 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH24_bp 4 /* Asynchronous Channel 2 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH25_bm (1<<5) /* Asynchronous Channel 2 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH25_bp 5 /* Asynchronous Channel 2 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH26_bm (1<<6) /* Asynchronous Channel 2 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH26_bp 6 /* Asynchronous Channel 2 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH27_bm (1<<7) /* Asynchronous Channel 2 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH27_bp 7 /* Asynchronous Channel 2 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH3 bit masks and bit positions */ +#define EVSYS_ASYNCCH3_gm 0xFF /* Asynchronous Channel 3 Generator Selection group mask. */ +#define EVSYS_ASYNCCH3_gp 0 /* Asynchronous Channel 3 Generator Selection group position. */ +#define EVSYS_ASYNCCH30_bm (1<<0) /* Asynchronous Channel 3 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH30_bp 0 /* Asynchronous Channel 3 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH31_bm (1<<1) /* Asynchronous Channel 3 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH31_bp 1 /* Asynchronous Channel 3 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH32_bm (1<<2) /* Asynchronous Channel 3 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH32_bp 2 /* Asynchronous Channel 3 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH33_bm (1<<3) /* Asynchronous Channel 3 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH33_bp 3 /* Asynchronous Channel 3 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH34_bm (1<<4) /* Asynchronous Channel 3 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH34_bp 4 /* Asynchronous Channel 3 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH35_bm (1<<5) /* Asynchronous Channel 3 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH35_bp 5 /* Asynchronous Channel 3 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH36_bm (1<<6) /* Asynchronous Channel 3 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH36_bp 6 /* Asynchronous Channel 3 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH37_bm (1<<7) /* Asynchronous Channel 3 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH37_bp 7 /* Asynchronous Channel 3 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.ASYNCUSER11 bit masks and bit positions */ +#define EVSYS_ASYNCUSER11_gm 0xFF /* Asynchronous User Ch 11 Input Selection - TCB1 group mask. */ +#define EVSYS_ASYNCUSER11_gp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 group position. */ +#define EVSYS_ASYNCUSER110_bm (1<<0) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 mask. */ +#define EVSYS_ASYNCUSER110_bp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 position. */ +#define EVSYS_ASYNCUSER111_bm (1<<1) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 mask. */ +#define EVSYS_ASYNCUSER111_bp 1 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 position. */ +#define EVSYS_ASYNCUSER112_bm (1<<2) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 mask. */ +#define EVSYS_ASYNCUSER112_bp 2 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 position. */ +#define EVSYS_ASYNCUSER113_bm (1<<3) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 mask. */ +#define EVSYS_ASYNCUSER113_bp 3 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 position. */ +#define EVSYS_ASYNCUSER114_bm (1<<4) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 mask. */ +#define EVSYS_ASYNCUSER114_bp 4 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 position. */ +#define EVSYS_ASYNCUSER115_bm (1<<5) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 mask. */ +#define EVSYS_ASYNCUSER115_bp 5 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 position. */ +#define EVSYS_ASYNCUSER116_bm (1<<6) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 mask. */ +#define EVSYS_ASYNCUSER116_bp 6 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 position. */ +#define EVSYS_ASYNCUSER117_bm (1<<7) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 mask. */ +#define EVSYS_ASYNCUSER117_bp 7 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 position. */ + +/* EVSYS.ASYNCUSER12 bit masks and bit positions */ +#define EVSYS_ASYNCUSER12_gm 0xFF /* Asynchronous User Ch 12 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER12_gp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER120_bm (1<<0) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER120_bp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER121_bm (1<<1) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER121_bp 1 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER122_bm (1<<2) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER122_bp 2 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER123_bm (1<<3) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER123_bp 3 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER124_bm (1<<4) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER124_bp 4 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER125_bm (1<<5) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER125_bp 5 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER126_bm (1<<6) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER126_bp 6 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER127_bm (1<<7) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER127_bp 7 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ +#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ +#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Synchronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Synchronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Synchronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Synchronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Synchronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Synchronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ +#define VREF_DAC1REFEN_bm 0x08 /* DAC1/AC1 reference enable bit mask. */ +#define VREF_DAC1REFEN_bp 3 /* DAC1/AC1 reference enable bit position. */ +#define VREF_ADC1REFEN_bm 0x10 /* ADC1 reference enable bit mask. */ +#define VREF_ADC1REFEN_bp 4 /* ADC1 reference enable bit position. */ +#define VREF_DAC2REFEN_bm 0x20 /* DAC2/AC2 reference enable bit mask. */ +#define VREF_DAC2REFEN_bp 5 /* DAC2/AC2 reference enable bit position. */ + +/* VREF.CTRLC bit masks and bit positions */ +#define VREF_DAC1REFSEL_gm 0x07 /* DAC1/AC1 reference select group mask. */ +#define VREF_DAC1REFSEL_gp 0 /* DAC1/AC1 reference select group position. */ +#define VREF_DAC1REFSEL0_bm (1<<0) /* DAC1/AC1 reference select bit 0 mask. */ +#define VREF_DAC1REFSEL0_bp 0 /* DAC1/AC1 reference select bit 0 position. */ +#define VREF_DAC1REFSEL1_bm (1<<1) /* DAC1/AC1 reference select bit 1 mask. */ +#define VREF_DAC1REFSEL1_bp 1 /* DAC1/AC1 reference select bit 1 position. */ +#define VREF_DAC1REFSEL2_bm (1<<2) /* DAC1/AC1 reference select bit 2 mask. */ +#define VREF_DAC1REFSEL2_bp 2 /* DAC1/AC1 reference select bit 2 position. */ +#define VREF_ADC1REFSEL_gm 0x70 /* ADC1 reference select group mask. */ +#define VREF_ADC1REFSEL_gp 4 /* ADC1 reference select group position. */ +#define VREF_ADC1REFSEL0_bm (1<<4) /* ADC1 reference select bit 0 mask. */ +#define VREF_ADC1REFSEL0_bp 4 /* ADC1 reference select bit 0 position. */ +#define VREF_ADC1REFSEL1_bm (1<<5) /* ADC1 reference select bit 1 mask. */ +#define VREF_ADC1REFSEL1_bp 5 /* ADC1 reference select bit 1 position. */ +#define VREF_ADC1REFSEL2_bm (1<<6) /* ADC1 reference select bit 2 mask. */ +#define VREF_ADC1REFSEL2_bp 6 /* ADC1 reference select bit 2 position. */ + +/* VREF.CTRLD bit masks and bit positions */ +#define VREF_DAC2REFSEL_gm 0x07 /* DAC2/AC2 reference select group mask. */ +#define VREF_DAC2REFSEL_gp 0 /* DAC2/AC2 reference select group position. */ +#define VREF_DAC2REFSEL0_bm (1<<0) /* DAC2/AC2 reference select bit 0 mask. */ +#define VREF_DAC2REFSEL0_bp 0 /* DAC2/AC2 reference select bit 0 position. */ +#define VREF_DAC2REFSEL1_bm (1<<1) /* DAC2/AC2 reference select bit 1 mask. */ +#define VREF_DAC2REFSEL1_bp 1 /* DAC2/AC2 reference select bit 1 position. */ +#define VREF_DAC2REFSEL2_bm (1<<2) /* DAC2/AC2 reference select bit 2 mask. */ +#define VREF_DAC2REFSEL2_bp 2 /* DAC2/AC2 reference select bit 2 position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 5 +#define PORTC_PORT_vect _VECTOR(5) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TCB1 interrupt vectors */ +#define TCB1_INT_vect_num 14 +#define TCB1_INT_vect _VECTOR(14) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 15 +#define TCD0_OVF_vect _VECTOR(15) /* */ +#define TCD0_TRIG_vect_num 16 +#define TCD0_TRIG_vect _VECTOR(16) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 17 +#define AC0_AC_vect _VECTOR(17) /* */ + +/* AC1 interrupt vectors */ +#define AC1_AC_vect_num 18 +#define AC1_AC_vect _VECTOR(18) /* */ + +/* AC2 interrupt vectors */ +#define AC2_AC_vect_num 19 +#define AC2_AC_vect _VECTOR(19) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 20 +#define ADC0_RESRDY_vect _VECTOR(20) /* */ +#define ADC0_WCOMP_vect_num 21 +#define ADC0_WCOMP_vect _VECTOR(21) /* */ + +/* ADC1 interrupt vectors */ +#define ADC1_RESRDY_vect_num 22 +#define ADC1_RESRDY_vect _VECTOR(22) /* */ +#define ADC1_WCOMP_vect_num 23 +#define ADC1_WCOMP_vect _VECTOR(23) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 24 +#define TWI0_TWIS_vect _VECTOR(24) /* */ +#define TWI0_TWIM_vect_num 25 +#define TWI0_TWIM_vect _VECTOR(25) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 26 +#define SPI0_INT_vect _VECTOR(26) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 27 +#define USART0_RXC_vect _VECTOR(27) /* */ +#define USART0_DRE_vect_num 28 +#define USART0_DRE_vect _VECTOR(28) /* */ +#define USART0_TXC_vect_num 29 +#define USART0_TXC_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (31 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (65536) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (65536U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (256) +# define EEPROM_PAGE_SIZE (64) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (256U) +# define EEPROM_PAGE_SIZE (64U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (64) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (64U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3800) +# define INTERNAL_SRAM_SIZE (2048) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3800U) +# define INTERNAL_SRAM_SIZE (2048U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (64) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (64U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (32768) +# define MAPPED_PROGMEM_PAGE_SIZE (128) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (32768U) +# define MAPPED_PROGMEM_PAGE_SIZE (128U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (128) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (128U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (128) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (128U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (64) +# define USER_SIGNATURES_PAGE_SIZE (64) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (64U) +# define USER_SIGNATURES_PAGE_SIZE (64U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (32768) +# define PROGMEM_PAGE_SIZE (128) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (32768U) +# define PROGMEM_PAGE_SIZE (128U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x22 + + +#endif /* #ifdef _AVR_ATTINY3217_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn4.h b/hardware/tools/avr/avr/include/avr/iotn4.h new file mode 100644 index 0000000000000000000000000000000000000000..6e2c8808cf033d12e91748a1a02bb608dfb368dc --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn4.h @@ -0,0 +1,477 @@ +/* Copyright (c) 2009 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iotn4.h 2063 2009-11-18 22:06:28Z arcanum $ */ + +/* avr/iotn4.h - definitions for ATtiny4 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn4.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATtiny4_H_ +#define _AVR_ATtiny4_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINB _SFR_IO8(0x00) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 + +#define DDRB _SFR_IO8(0x01) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 + +#define PORTB _SFR_IO8(0x02) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 + +#define PUEB _SFR_IO8(0x03) +#define PUEB0 0 +#define PUEB1 1 +#define PUEB2 2 +#define PUEB3 3 + +#define PORTCR _SFR_IO8(0x0C) +#define BBMB 1 + +#define PCMSK _SFR_IO8(0x10) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 + +#define PCIFR _SFR_IO8(0x11) +#define PCIF0 0 + +#define PCICR _SFR_IO8(0x12) +#define PCIE0 0 + +#define EIMSK _SFR_IO8(0x13) +#define INT0 0 + +#define EIFR _SFR_IO8(0x14) +#define INTF0 0 + +#define EICRA _SFR_IO8(0x15) +#define ISC00 0 +#define ISC01 1 + +#define DIDR0 _SFR_IO8(0x17) +#define AIN0D 0 +#define AIN1D 1 + +#define ACSR _SFR_IO8(0x1F) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACD 7 + +#define ICR0 _SFR_IO16(0x22) + +#define ICR0L _SFR_IO8(0x22) +#define ICR0_0 0 +#define ICR0_1 1 +#define ICR0_2 2 +#define ICR0_3 3 +#define ICR0_4 4 +#define ICR0_5 5 +#define ICR0_6 6 +#define ICR0_7 7 + +#define ICR0H _SFR_IO8(0x23) +#define ICR0_8 0 +#define ICR0_9 1 +#define ICR0_10 2 +#define ICR0_11 3 +#define ICR0_12 4 +#define ICR0_13 5 +#define ICR0_14 6 +#define ICR0_15 7 + +#define OCR0B _SFR_IO16(0x24) + +#define OCR0BL _SFR_IO8(0x24) +#define OCR0B0 0 +#define OCR0B1 1 +#define OCR0B2 2 +#define OCR0B3 3 +#define OCR0B4 4 +#define OCR0B5 5 +#define OCR0B6 6 +#define OCR0B7 7 + +#define OCR0BH _SFR_IO8(0x25) +#define OCR0B8 0 +#define OCR0B9 1 +#define OCR0B10 2 +#define OCR0B11 3 +#define OCR0B12 4 +#define OCR0B13 5 +#define OCR0B14 6 +#define OCR0B15 7 + +#define OCR0A _SFR_IO16(0x26) + +#define OCR0AL _SFR_IO8(0x26) +#define OCR0A0 0 +#define OCR0A1 1 +#define OCR0A2 2 +#define OCR0A3 3 +#define OCR0A4 4 +#define OCR0A5 5 +#define OCR0A6 6 +#define OCR0A7 7 + +#define OCR0AH _SFR_IO8(0x27) +#define OCR0A8 0 +#define OCR0A9 1 +#define OCR0A10 2 +#define OCR0A11 3 +#define OCR0A12 4 +#define OCR0A13 5 +#define OCR0A14 6 +#define OCR0A15 7 + +#define TCNT0 _SFR_IO16(0x28) + +#define TCNT0L _SFR_IO8(0x28) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define TCNT0H _SFR_IO8(0x29) +#define TCNT0_8 0 +#define TCNT0_9 1 +#define TCNT0_10 2 +#define TCNT0_11 3 +#define TCNT0_12 4 +#define TCNT0_13 5 +#define TCNT0_14 6 +#define TCNT0_15 7 + +#define TIFR0 _SFR_IO8(0x2A) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define ICF0 5 + +#define TIMSK0 _SFR_IO8(0x2B) +#define TOIE0 0 +#define OCIE0A 1 +#define OCIE0B 2 +#define ICIE0 5 + +#define TCCR0C _SFR_IO8(0x2C) +#define FOC0B 6 +#define FOC0A 7 + +#define TCCR0B _SFR_IO8(0x2D) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define WGM03 4 +#define ICES0 6 +#define ICNC0 7 + +#define TCCR0A _SFR_IO8(0x2E) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define GTCCR _SFR_IO8(0x2F) +#define PSR 0 +#define TSM 7 + +#define WDTCSR _SFR_IO8(0x31) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define NVMCSR _SFR_IO8(0x32) +#define NVMBSY 7 + +#define NVMCMD _SFR_IO8(0x33) +#define NVMCMD0 0 +#define NVMCMD1 1 +#define NVMCMD2 2 +#define NVMCMD3 3 +#define NVMCMD4 4 +#define NVMCMD5 5 + +#define VLMCSR _SFR_IO8(0x34) +#define VLM0 0 +#define VLM1 1 +#define VLM2 2 +#define VLMIE 6 +#define VLMF 7 + +#define PRR _SFR_IO8(0x35) +#define PRTIM0 0 +#define PRADC 1 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn40.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATtiny40_H_ +#define _AVR_ATtiny40_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINA _SFR_IO8(0x00) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 +#define PINA4 4 +#define PINA5 5 +#define PINA6 6 +#define PINA7 7 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 +#define PORTA4 4 +#define PORTA5 5 +#define PORTA6 6 +#define PORTA7 7 + +#define PUEA _SFR_IO8(0x03) +#define PUEA0 0 +#define PUEA1 1 +#define PUEA2 2 +#define PUEA3 3 +#define PUEA4 4 +#define PUEA5 5 +#define PUEA6 6 +#define PUEA7 7 + +#define PINB _SFR_IO8(0x04) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 + +#define DDRB _SFR_IO8(0x05) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 + +#define PORTB _SFR_IO8(0x06) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 + +#define PUEB _SFR_IO8(0x07) +#define PUEB0 0 +#define PUEB1 1 +#define PUEB2 2 +#define PUEB3 3 + +#define PORTCR _SFR_IO8(0x08) +#define BBMA 0 +#define BBMB 1 +#define BBMC 2 +#define ADC8D 4 +#define ADC9D 5 +#define ADC10D 6 +#define ADC11D 7 + +#define PCMSK0 _SFR_IO8(0x09) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 +#define PCINT4 4 +#define PCINT5 5 +#define PCINT6 6 +#define PCINT7 7 + +#define PCMSK1 _SFR_IO8(0x0A) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 +#define PCINT11 3 + +#define GIFR _SFR_IO8(0x0B) +#define INTF0 0 +#define PCIF0 4 +#define PCIF1 5 +#define PCIF2 6 + +#define GIMSK _SFR_IO8(0x0C) +#define INT0 0 +#define PCIE0 4 +#define PCIE1 5 +#define PCIE2 6 + +#define DIDR0 _SFR_IO8(0x0D) +#define ADC0D 0 +#define ADC1D 1 +#define ADC2D 2 +#define ADC3D 3 +#define ADC4D 4 +#define ADC5D 5 +#define ADC6D 6 +#define ADC7D 7 + +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x0E) +#endif +#define ADCW _SFR_IO16(0x0E) + +#define ADCL _SFR_IO8(0x0E) +#define ADCL0 0 +#define ADCL1 1 +#define ADCL2 2 +#define ADCL3 3 +#define ADCL4 4 +#define ADCL5 5 +#define ADCL6 6 +#define ADCL7 7 + +#define ADCH _SFR_IO8(0x0F) +#define ADCH0 0 +#define ADCH1 1 +#define ADCH2 2 +#define ADCH3 3 +#define ADCH4 4 +#define ADCH5 5 +#define ADCH6 6 +#define ADCH7 7 + +#define ADMUX _SFR_IO8(0x10) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define REFS 6 + +#define ADCSRB _SFR_IO8(0x11) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 +#define ADLAR 3 + +#define ADCSRA _SFR_IO8(0x12) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +#define ACSRB _SFR_IO8(0x13) +#define ACME 2 +#define HLEV 6 +#define HSEL 7 + +#define ACSRA _SFR_IO8(0x14) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCR0B _SFR_IO8(0x15) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define OCR0A _SFR_IO8(0x16) +#define OCR0_0 0 +#define OCR0_1 1 +#define OCR0_2 2 +#define OCR0_3 3 +#define OCR0_4 4 +#define OCR0_5 5 +#define OCR0_6 6 +#define OCR0_7 7 + +#define TCNT0 _SFR_IO8(0x17) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define TCCR0B _SFR_IO8(0x18) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define PSR 4 +#define TSM 5 +#define FOC0B 6 +#define FOC0A 7 + +#define TCCR0A _SFR_IO8(0x19) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define PCMSK2 _SFR_IO8(0x1A) +#define PCINT12 0 +#define PCINT13 1 +#define PCINT14 2 +#define PCINT15 3 +#define PCINT16 4 +#define PCINT17 5 + +#define PINC _SFR_IO8(0x1B) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 + +#define DDRC _SFR_IO8(0x1C) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 + +#define PORTC _SFR_IO8(0x1D) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 + +#define PUEC _SFR_IO8(0x1E) +#define PUEC0 0 +#define PUEC1 1 +#define PUEC2 2 +#define PUEC3 3 +#define PUEC4 4 +#define PUEC5 5 + +#define RAMDR _SFR_IO8(0x1F) +#define RAMDR0 0 +#define RAMDR1 1 +#define RAMDR2 2 +#define RAMDR3 3 +#define RAMDR4 4 +#define RAMDR5 5 +#define RAMDR6 6 +#define RAMDR7 7 + +#define RAMAR _SFR_IO8(0x20) +#define RAMAR0 0 +#define RAMAR1 1 +#define RAMAR2 2 +#define RAMAR3 3 +#define RAMAR4 4 +#define RAMAR5 5 +#define RAMAR6 6 +#define RAMAR7 7 + +#define OCR1B _SFR_IO8(0x21) +#define OCR1B0 0 +#define OCR1B1 1 +#define OCR1B2 2 +#define OCR1B3 3 +#define OCR1B4 4 +#define OCR1B5 5 +#define OCR1B6 6 +#define OCR1B7 7 + +#define OCR1A _SFR_IO8(0x22) +#define OCR1A0 0 +#define OCR1A1 1 +#define OCR1A2 2 +#define OCR1A3 3 +#define OCR1A4 4 +#define OCR1A5 5 +#define OCR1A6 6 +#define OCR1A7 7 + +#define TCNT1L _SFR_IO8(0x23) +#define TCNT1_0 0 +#define TCNT1_1 1 +#define TCNT1_2 2 +#define TCNT1_3 3 +#define TCNT1_4 4 +#define TCNT1_5 5 +#define TCNT1_6 6 +#define TCNT1_7 7 + +#define TCCR1A _SFR_IO8(0x24) +#define CS10 0 +#define CS11 1 +#define CS12 2 +#define CTC1 3 +#define ICES1 4 +#define ICNC1 5 +#define ICEN1 6 +#define TCW1 7 + +#define TIFR _SFR_IO8(0x25) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define TOV1 3 +#define OCF1A 4 +#define OCF1B 5 +#define ICF1 7 + +#define TIMSK _SFR_IO8(0x26) +#define TOIE0 0 +#define OCIE0A 1 +#define OCIE0B 2 +#define TOIE1 3 +#define OCIE1A 4 +#define OCIE1B 5 +#define ICIE1 7 + +#define TCNT1H _SFR_IO8(0x27) +#define TCNT1_8 0 +#define TCNT1_9 1 +#define TCNT1_10 2 +#define TCNT1_11 3 +#define TCNT1_12 4 +#define TCNT1_13 5 +#define TCNT1_14 6 +#define TCNT1_15 7 + +#define TWSD _SFR_IO8(0x28) +#define TWSD0 0 +#define TWSD1 1 +#define TWSD2 2 +#define TWSD3 3 +#define TWSD4 4 +#define TWSD5 5 +#define TWSD6 6 +#define TWSD7 7 + +#define TWSAM _SFR_IO8(0x29) +#define TWAE 0 +#define TWSAM1 1 +#define TWSAM2 2 +#define TWSAM3 3 +#define TWSAM4 4 +#define TWSAM5 5 +#define TWSAM6 6 +#define TWSAM7 7 + +#define TWSA _SFR_IO8(0x2A) +#define TWSA0 0 +#define TWSA1 1 +#define TWSA2 2 +#define TWSA3 3 +#define TWSA4 4 +#define TWSA5 5 +#define TWSA6 6 +#define TWSA7 7 + +#define TWSSRA _SFR_IO8(0x2B) +#define TWAS 0 +#define TWDIR 1 +#define TWBE 2 +#define TWC 3 +#define TWRA 4 +#define TWCH 5 +#define TWASIF 6 +#define TWDIF 7 + +#define TWSCRB _SFR_IO8(0x2C) +#define TWCMD0 0 +#define TWCMD1 1 +#define TWAA 2 + +#define TWSCRA _SFR_IO8(0x2D) +#define TWSME 0 +#define TWPME 1 +#define TWSIE 2 +#define TWEN 3 +#define TWASIE 4 +#define TWDIE 5 +#define TWSHE 7 + +#define SPDR _SFR_IO8(0x2E) + +#define SPSR _SFR_IO8(0x2F) + +#define SPCR _SFR_IO8(0x30) + +#define WDTCSR _SFR_IO8(0x31) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define NVMCSR _SFR_IO8(0x32) +#define NVMBSY 7 + +#define NVMCMD _SFR_IO8(0x33) +#define NVMCMD0 0 +#define NVMCMD1 1 +#define NVMCMD2 2 +#define NVMCMD3 3 +#define NVMCMD4 4 +#define NVMCMD5 5 + +#define QTCSR _SFR_IO8(0x34) + +#define PRR _SFR_IO8(0x35) +#define PRADC 0 +#define PRTIM0 1 +#define PRTIM1 2 +#define PRSPI 3 +#define PRTWI 4 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn402.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY402_H_INCLUDED +#define _AVR_ATTINY402_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wakeup halt */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling */ + BOD_SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[3]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[7]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t reserved_1[6]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t reserved_3[5]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 Input Selection - TCA0 */ + register8_t reserved_4[29]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 Input Selection - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ +} EVSYS_SYNCUSER0_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHz_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0670) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0670) +#define AC0_MUXCTRLA _SFR_MEM8(0x0672) +#define AC0_INTCTRL _SFR_MEM8(0x0676) +#define AC0_STATUS _SFR_MEM8(0x0677) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 Input Selection - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 Input Selection - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 16 +#define AC0_AC_vect _VECTOR(16) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 17 +#define ADC0_RESRDY_vect _VECTOR(17) /* */ +#define ADC0_WCOMP_vect_num 18 +#define ADC0_WCOMP_vect _VECTOR(18) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 19 +#define TWI0_TWIS_vect _VECTOR(19) /* */ +#define TWI0_TWIM_vect_num 20 +#define TWI0_TWIM_vect _VECTOR(20) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 21 +#define SPI0_INT_vect _VECTOR(21) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 22 +#define USART0_RXC_vect _VECTOR(22) /* */ +#define USART0_DRE_vect_num 23 +#define USART0_DRE_vect _VECTOR(23) /* */ +#define USART0_TXC_vect_num 24 +#define USART0_TXC_vect _VECTOR(24) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 25 +#define NVMCTRL_EE_vect _VECTOR(25) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (26 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (36864) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (36864U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (128) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (128U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3F00) +# define INTERNAL_SRAM_SIZE (256) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3F00U) +# define INTERNAL_SRAM_SIZE (256U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (4096) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (4096U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (4096) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (4096U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x92 +#define SIGNATURE_2 0x27 + + +#endif /* #ifdef _AVR_ATTINY402_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn404.h b/hardware/tools/avr/avr/include/avr/iotn404.h new file mode 100644 index 0000000000000000000000000000000000000000..10b9ace05fd3fa815cd3e9bdc80f0b8a8d24bdd5 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn404.h @@ -0,0 +1,4631 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn404.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY404_H_INCLUDED +#define _AVR_ATTINY404_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wakeup halt */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling */ + BOD_SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[3]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[7]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t reserved_1[6]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t reserved_2[7]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t reserved_3[5]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 Input Selection - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 Input Selection - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous User Ch 0 Input Selection - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 Input Selection - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHz_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0670) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0670) +#define AC0_MUXCTRLA _SFR_MEM8(0x0672) +#define AC0_INTCTRL _SFR_MEM8(0x0676) +#define AC0_STATUS _SFR_MEM8(0x0677) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 Input Selection - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 Input Selection - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 Input Selection - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 Input Selection - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 Input Selection - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 Input Selection - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 Input Selection - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 Input Selection - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 Input Selection - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 Input Selection - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 Input Selection - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 Input Selection - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 Input Selection - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 Input Selection - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 Input Selection - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 Input Selection - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 Input Selection - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 Input Selection - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 Input Selection - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 Input Selection - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 16 +#define AC0_AC_vect _VECTOR(16) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 17 +#define ADC0_RESRDY_vect _VECTOR(17) /* */ +#define ADC0_WCOMP_vect_num 18 +#define ADC0_WCOMP_vect _VECTOR(18) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 19 +#define TWI0_TWIS_vect _VECTOR(19) /* */ +#define TWI0_TWIM_vect_num 20 +#define TWI0_TWIM_vect _VECTOR(20) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 21 +#define SPI0_INT_vect _VECTOR(21) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 22 +#define USART0_RXC_vect _VECTOR(22) /* */ +#define USART0_DRE_vect_num 23 +#define USART0_DRE_vect _VECTOR(23) /* */ +#define USART0_TXC_vect_num 24 +#define USART0_TXC_vect _VECTOR(24) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 25 +#define NVMCTRL_EE_vect _VECTOR(25) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (26 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (36864) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (36864U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (128) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (128U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3F00) +# define INTERNAL_SRAM_SIZE (256) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3F00U) +# define INTERNAL_SRAM_SIZE (256U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (4096) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (4096U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (4096) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (4096U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x92 +#define SIGNATURE_2 0x26 + + +#endif /* #ifdef _AVR_ATTINY404_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn406.h b/hardware/tools/avr/avr/include/avr/iotn406.h new file mode 100644 index 0000000000000000000000000000000000000000..d11ef52c3dd30d309da5110fdfec0a2fb64ea838 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn406.h @@ -0,0 +1,4628 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn406.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY406_H_INCLUDED +#define _AVR_ATTINY406_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wakeup halt */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling */ + BOD_SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[3]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[7]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t reserved_1[6]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t reserved_3[5]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 Input Selection - TCA0 */ + register8_t reserved_4[29]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 Input Selection - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ +} EVSYS_SYNCUSER0_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHz_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0670) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0670) +#define AC0_MUXCTRLA _SFR_MEM8(0x0672) +#define AC0_INTCTRL _SFR_MEM8(0x0676) +#define AC0_STATUS _SFR_MEM8(0x0677) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 Input Selection - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 Input Selection - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 5 +#define PORTC_PORT_vect _VECTOR(5) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 16 +#define AC0_AC_vect _VECTOR(16) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 17 +#define ADC0_RESRDY_vect _VECTOR(17) /* */ +#define ADC0_WCOMP_vect_num 18 +#define ADC0_WCOMP_vect _VECTOR(18) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 19 +#define TWI0_TWIS_vect _VECTOR(19) /* */ +#define TWI0_TWIM_vect_num 20 +#define TWI0_TWIM_vect _VECTOR(20) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 21 +#define SPI0_INT_vect _VECTOR(21) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 22 +#define USART0_RXC_vect _VECTOR(22) /* */ +#define USART0_DRE_vect_num 23 +#define USART0_DRE_vect _VECTOR(23) /* */ +#define USART0_TXC_vect_num 24 +#define USART0_TXC_vect _VECTOR(24) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 25 +#define NVMCTRL_EE_vect _VECTOR(25) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (26 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (36864) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (36864U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (128) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (128U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3F00) +# define INTERNAL_SRAM_SIZE (256) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3F00U) +# define INTERNAL_SRAM_SIZE (256U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (4096) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (4096U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (4096) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (4096U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x92 +#define SIGNATURE_2 0x25 + + +#endif /* #ifdef _AVR_ATTINY406_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn412.h b/hardware/tools/avr/avr/include/avr/iotn412.h new file mode 100644 index 0000000000000000000000000000000000000000..b6e056a5f2d6a5847a992d930598e513c60cf34b --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn412.h @@ -0,0 +1,5212 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn412.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY412_H_INCLUDED +#define _AVR_ATTINY412_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ + AC_MUXNEG_DAC_gc = (0x03<<0), /* DAC output */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wakeup halt */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling */ + BOD_SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[3]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1K cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16K cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32K cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64K cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t DATA; /* DATA Register */ + register8_t reserved_1[2]; +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t ASYNCCH2; /* Asynchronous Channel 2 Generator Selection */ + register8_t ASYNCCH3; /* Asynchronous Channel 3 Generator Selection */ + register8_t reserved_1[4]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t reserved_3[5]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 Input Selection - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 Input Selection - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous Channel 2 Generator Selection select */ +typedef enum EVSYS_ASYNCCH2_enum +{ + EVSYS_ASYNCCH2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH2_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH2_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH2_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH2_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH2_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH2_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH2_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH2_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH2_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH2_PORTC_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PC0 */ + EVSYS_ASYNCCH2_PORTC_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PC1 */ + EVSYS_ASYNCCH2_PORTC_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PC2 */ + EVSYS_ASYNCCH2_PORTC_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PC3 */ + EVSYS_ASYNCCH2_PORTC_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PC4 */ + EVSYS_ASYNCCH2_PORTC_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PC5 */ +} EVSYS_ASYNCCH2_t; + +/* Asynchronous Channel 3 Generator Selection select */ +typedef enum EVSYS_ASYNCCH3_enum +{ + EVSYS_ASYNCCH3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH3_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH3_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH3_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH3_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter type D compare B clear */ + EVSYS_ASYNCCH3_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter type D compare A set */ + EVSYS_ASYNCCH3_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter type D compare B set */ + EVSYS_ASYNCCH3_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter type D program event */ + EVSYS_ASYNCCH3_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH3_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH3_PIT_DIV8192_gc = (0x0A<<0), /* Periodic Interrupt CLK_RTC div 8192 */ + EVSYS_ASYNCCH3_PIT_DIV4096_gc = (0x0B<<0), /* Periodic Interrupt CLK_RTC div 4096 */ + EVSYS_ASYNCCH3_PIT_DIV2048_gc = (0x0C<<0), /* Periodic Interrupt CLK_RTC div 2048 */ + EVSYS_ASYNCCH3_PIT_DIV1024_gc = (0x0D<<0), /* Periodic Interrupt CLK_RTC div 1024 */ + EVSYS_ASYNCCH3_PIT_DIV512_gc = (0x0E<<0), /* Periodic Interrupt CLK_RTC div 512 */ + EVSYS_ASYNCCH3_PIT_DIV256_gc = (0x0F<<0), /* Periodic Interrupt CLK_RTC div 256 */ + EVSYS_ASYNCCH3_PIT_DIV128_gc = (0x10<<0), /* Periodic Interrupt CLK_RTC div 128 */ + EVSYS_ASYNCCH3_PIT_DIV64_gc = (0x11<<0), /* Periodic Interrupt CLK_RTC div 64 */ +} EVSYS_ASYNCCH3_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 Input Selection - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 Input Selection - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHz_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_20MHZ_gc = (0x00<<5), /* 20 MHz oscillator */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External clock */ + TCD_CLKSEL_SYSCLK_gc = (0x03<<5), /* System clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Syncronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selevted clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selevted clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selevted clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selevted clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0670) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x0680) /* Digital to Analog Converter */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0A80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_ASYNCCH2 _SFR_MEM8(0x0184) +#define EVSYS_ASYNCCH3 _SFR_MEM8(0x0185) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0670) +#define AC0_MUXCTRLA _SFR_MEM8(0x0672) +#define AC0_INTCTRL _SFR_MEM8(0x0676) +#define AC0_STATUS _SFR_MEM8(0x0677) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x0680) +#define DAC0_DATA _SFR_MEM8(0x0681) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0A80) +#define TCD0_CTRLB _SFR_MEM8(0x0A81) +#define TCD0_CTRLC _SFR_MEM8(0x0A82) +#define TCD0_CTRLD _SFR_MEM8(0x0A83) +#define TCD0_CTRLE _SFR_MEM8(0x0A84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0A88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0A89) +#define TCD0_INTCTRL _SFR_MEM8(0x0A8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0A8D) +#define TCD0_STATUS _SFR_MEM8(0x0A8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0A90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0A91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0A92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0A94) +#define TCD0_DLYVAL _SFR_MEM8(0x0A95) +#define TCD0_DITCTRL _SFR_MEM8(0x0A98) +#define TCD0_DITVAL _SFR_MEM8(0x0A99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0A9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0AA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0AA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0AA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0AA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0AA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0AA5) +#define TCD0_CMPASET _SFR_MEM16(0x0AA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0AA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0AA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0AAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0AAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0AAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0AAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0AAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0AAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0AAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0AAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0AAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH2 bit masks and bit positions */ +#define EVSYS_ASYNCCH2_gm 0xFF /* Asynchronous Channel 2 Generator Selection group mask. */ +#define EVSYS_ASYNCCH2_gp 0 /* Asynchronous Channel 2 Generator Selection group position. */ +#define EVSYS_ASYNCCH20_bm (1<<0) /* Asynchronous Channel 2 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH20_bp 0 /* Asynchronous Channel 2 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH21_bm (1<<1) /* Asynchronous Channel 2 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH21_bp 1 /* Asynchronous Channel 2 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH22_bm (1<<2) /* Asynchronous Channel 2 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH22_bp 2 /* Asynchronous Channel 2 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH23_bm (1<<3) /* Asynchronous Channel 2 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH23_bp 3 /* Asynchronous Channel 2 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH24_bm (1<<4) /* Asynchronous Channel 2 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH24_bp 4 /* Asynchronous Channel 2 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH25_bm (1<<5) /* Asynchronous Channel 2 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH25_bp 5 /* Asynchronous Channel 2 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH26_bm (1<<6) /* Asynchronous Channel 2 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH26_bp 6 /* Asynchronous Channel 2 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH27_bm (1<<7) /* Asynchronous Channel 2 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH27_bp 7 /* Asynchronous Channel 2 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH3 bit masks and bit positions */ +#define EVSYS_ASYNCCH3_gm 0xFF /* Asynchronous Channel 3 Generator Selection group mask. */ +#define EVSYS_ASYNCCH3_gp 0 /* Asynchronous Channel 3 Generator Selection group position. */ +#define EVSYS_ASYNCCH30_bm (1<<0) /* Asynchronous Channel 3 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH30_bp 0 /* Asynchronous Channel 3 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH31_bm (1<<1) /* Asynchronous Channel 3 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH31_bp 1 /* Asynchronous Channel 3 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH32_bm (1<<2) /* Asynchronous Channel 3 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH32_bp 2 /* Asynchronous Channel 3 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH33_bm (1<<3) /* Asynchronous Channel 3 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH33_bp 3 /* Asynchronous Channel 3 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH34_bm (1<<4) /* Asynchronous Channel 3 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH34_bp 4 /* Asynchronous Channel 3 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH35_bm (1<<5) /* Asynchronous Channel 3 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH35_bp 5 /* Asynchronous Channel 3 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH36_bm (1<<6) /* Asynchronous Channel 3 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH36_bp 6 /* Asynchronous Channel 3 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH37_bm (1<<7) /* Asynchronous Channel 3 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH37_bp 7 /* Asynchronous Channel 3 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 Input Selection - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 Input Selection - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 Input Selection - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 Input Selection - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 Input Selection - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 Input Selection - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 Input Selection - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 Input Selection - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 Input Selection - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 Input Selection - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 Input Selection - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 Input Selection - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 Input Selection - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 Input Selection - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 Input Selection - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 Input Selection - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 Input Selection - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 Input Selection - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 Input Selection - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 Input Selection - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Syncronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Syncronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Syncronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Syncronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Syncronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Syncronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 14 +#define TCD0_OVF_vect _VECTOR(14) /* */ +#define TCD0_TRIG_vect_num 15 +#define TCD0_TRIG_vect _VECTOR(15) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 16 +#define AC0_AC_vect _VECTOR(16) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 17 +#define ADC0_RESRDY_vect _VECTOR(17) /* */ +#define ADC0_WCOMP_vect_num 18 +#define ADC0_WCOMP_vect _VECTOR(18) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 19 +#define TWI0_TWIS_vect _VECTOR(19) /* */ +#define TWI0_TWIM_vect_num 20 +#define TWI0_TWIM_vect _VECTOR(20) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 21 +#define SPI0_INT_vect _VECTOR(21) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 22 +#define USART0_RXC_vect _VECTOR(22) /* */ +#define USART0_DRE_vect_num 23 +#define USART0_DRE_vect _VECTOR(23) /* */ +#define USART0_TXC_vect_num 24 +#define USART0_TXC_vect _VECTOR(24) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 25 +#define NVMCTRL_EE_vect _VECTOR(25) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (26 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (36864) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (36864U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (128) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (128U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3F00) +# define INTERNAL_SRAM_SIZE (256) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3F00U) +# define INTERNAL_SRAM_SIZE (256U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (4096) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (4096U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (4096) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (4096U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x92 +#define SIGNATURE_2 0x23 + + +#endif /* #ifdef _AVR_ATTINY412_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn414.h b/hardware/tools/avr/avr/include/avr/iotn414.h new file mode 100644 index 0000000000000000000000000000000000000000..52c5bbfef0fc7dd3024a531cf13bab4d597962ed --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn414.h @@ -0,0 +1,5265 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn414.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY414_H_INCLUDED +#define _AVR_ATTINY414_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ + AC_MUXNEG_DAC_gc = (0x03<<0), /* DAC output */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wakeup halt */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling */ + BOD_SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[3]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1K cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16K cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32K cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t DATA; /* DATA Register */ + register8_t reserved_1[2]; +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t ASYNCCH2; /* Asynchronous Channel 2 Generator Selection */ + register8_t ASYNCCH3; /* Asynchronous Channel 3 Generator Selection */ + register8_t reserved_1[4]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t reserved_3[5]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 Input Selection - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 Input Selection - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous Channel 2 Generator Selection select */ +typedef enum EVSYS_ASYNCCH2_enum +{ + EVSYS_ASYNCCH2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH2_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH2_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH2_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH2_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH2_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH2_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH2_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH2_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH2_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH2_PORTC_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PC0 */ + EVSYS_ASYNCCH2_PORTC_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PC1 */ + EVSYS_ASYNCCH2_PORTC_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PC2 */ + EVSYS_ASYNCCH2_PORTC_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PC3 */ + EVSYS_ASYNCCH2_PORTC_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PC4 */ + EVSYS_ASYNCCH2_PORTC_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PC5 */ +} EVSYS_ASYNCCH2_t; + +/* Asynchronous Channel 3 Generator Selection select */ +typedef enum EVSYS_ASYNCCH3_enum +{ + EVSYS_ASYNCCH3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH3_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH3_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH3_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH3_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter type D compare B clear */ + EVSYS_ASYNCCH3_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter type D compare A set */ + EVSYS_ASYNCCH3_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter type D compare B set */ + EVSYS_ASYNCCH3_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter type D program event */ + EVSYS_ASYNCCH3_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH3_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH3_PIT_DIV8192_gc = (0x0A<<0), /* Periodic Interrupt CLK_RTC div 8192 */ + EVSYS_ASYNCCH3_PIT_DIV4096_gc = (0x0B<<0), /* Periodic Interrupt CLK_RTC div 4096 */ + EVSYS_ASYNCCH3_PIT_DIV2048_gc = (0x0C<<0), /* Periodic Interrupt CLK_RTC div 2048 */ + EVSYS_ASYNCCH3_PIT_DIV1024_gc = (0x0D<<0), /* Periodic Interrupt CLK_RTC div 1024 */ + EVSYS_ASYNCCH3_PIT_DIV512_gc = (0x0E<<0), /* Periodic Interrupt CLK_RTC div 512 */ + EVSYS_ASYNCCH3_PIT_DIV256_gc = (0x0F<<0), /* Periodic Interrupt CLK_RTC div 256 */ + EVSYS_ASYNCCH3_PIT_DIV128_gc = (0x10<<0), /* Periodic Interrupt CLK_RTC div 128 */ + EVSYS_ASYNCCH3_PIT_DIV64_gc = (0x11<<0), /* Periodic Interrupt CLK_RTC div 64 */ +} EVSYS_ASYNCCH3_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 Input Selection - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 Input Selection - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHz_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_20MHZ_gc = (0x00<<5), /* 20 MHz oscillator */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External clock */ + TCD_CLKSEL_SYSCLK_gc = (0x03<<5), /* System clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Syncronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selevted clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selevted clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selevted clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selevted clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0670) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x0680) /* Digital to Analog Converter */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0A80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_ASYNCCH2 _SFR_MEM8(0x0184) +#define EVSYS_ASYNCCH3 _SFR_MEM8(0x0185) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0670) +#define AC0_MUXCTRLA _SFR_MEM8(0x0672) +#define AC0_INTCTRL _SFR_MEM8(0x0676) +#define AC0_STATUS _SFR_MEM8(0x0677) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x0680) +#define DAC0_DATA _SFR_MEM8(0x0681) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0A80) +#define TCD0_CTRLB _SFR_MEM8(0x0A81) +#define TCD0_CTRLC _SFR_MEM8(0x0A82) +#define TCD0_CTRLD _SFR_MEM8(0x0A83) +#define TCD0_CTRLE _SFR_MEM8(0x0A84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0A88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0A89) +#define TCD0_INTCTRL _SFR_MEM8(0x0A8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0A8D) +#define TCD0_STATUS _SFR_MEM8(0x0A8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0A90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0A91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0A92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0A94) +#define TCD0_DLYVAL _SFR_MEM8(0x0A95) +#define TCD0_DITCTRL _SFR_MEM8(0x0A98) +#define TCD0_DITVAL _SFR_MEM8(0x0A99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0A9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0AA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0AA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0AA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0AA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0AA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0AA5) +#define TCD0_CMPASET _SFR_MEM16(0x0AA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0AA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0AA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0AAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0AAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0AAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0AAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0AAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0AAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0AAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0AAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0AAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH2 bit masks and bit positions */ +#define EVSYS_ASYNCCH2_gm 0xFF /* Asynchronous Channel 2 Generator Selection group mask. */ +#define EVSYS_ASYNCCH2_gp 0 /* Asynchronous Channel 2 Generator Selection group position. */ +#define EVSYS_ASYNCCH20_bm (1<<0) /* Asynchronous Channel 2 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH20_bp 0 /* Asynchronous Channel 2 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH21_bm (1<<1) /* Asynchronous Channel 2 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH21_bp 1 /* Asynchronous Channel 2 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH22_bm (1<<2) /* Asynchronous Channel 2 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH22_bp 2 /* Asynchronous Channel 2 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH23_bm (1<<3) /* Asynchronous Channel 2 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH23_bp 3 /* Asynchronous Channel 2 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH24_bm (1<<4) /* Asynchronous Channel 2 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH24_bp 4 /* Asynchronous Channel 2 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH25_bm (1<<5) /* Asynchronous Channel 2 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH25_bp 5 /* Asynchronous Channel 2 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH26_bm (1<<6) /* Asynchronous Channel 2 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH26_bp 6 /* Asynchronous Channel 2 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH27_bm (1<<7) /* Asynchronous Channel 2 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH27_bp 7 /* Asynchronous Channel 2 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH3 bit masks and bit positions */ +#define EVSYS_ASYNCCH3_gm 0xFF /* Asynchronous Channel 3 Generator Selection group mask. */ +#define EVSYS_ASYNCCH3_gp 0 /* Asynchronous Channel 3 Generator Selection group position. */ +#define EVSYS_ASYNCCH30_bm (1<<0) /* Asynchronous Channel 3 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH30_bp 0 /* Asynchronous Channel 3 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH31_bm (1<<1) /* Asynchronous Channel 3 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH31_bp 1 /* Asynchronous Channel 3 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH32_bm (1<<2) /* Asynchronous Channel 3 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH32_bp 2 /* Asynchronous Channel 3 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH33_bm (1<<3) /* Asynchronous Channel 3 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH33_bp 3 /* Asynchronous Channel 3 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH34_bm (1<<4) /* Asynchronous Channel 3 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH34_bp 4 /* Asynchronous Channel 3 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH35_bm (1<<5) /* Asynchronous Channel 3 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH35_bp 5 /* Asynchronous Channel 3 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH36_bm (1<<6) /* Asynchronous Channel 3 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH36_bp 6 /* Asynchronous Channel 3 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH37_bm (1<<7) /* Asynchronous Channel 3 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH37_bp 7 /* Asynchronous Channel 3 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 Input Selection - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 Input Selection - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 Input Selection - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 Input Selection - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 Input Selection - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 Input Selection - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 Input Selection - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 Input Selection - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 Input Selection - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 Input Selection - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 Input Selection - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 Input Selection - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 Input Selection - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 Input Selection - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 Input Selection - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 Input Selection - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 Input Selection - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 Input Selection - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 Input Selection - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 Input Selection - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Syncronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Syncronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Syncronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Syncronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Syncronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Syncronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 14 +#define TCD0_OVF_vect _VECTOR(14) /* */ +#define TCD0_TRIG_vect_num 15 +#define TCD0_TRIG_vect _VECTOR(15) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 16 +#define AC0_AC_vect _VECTOR(16) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 17 +#define ADC0_RESRDY_vect _VECTOR(17) /* */ +#define ADC0_WCOMP_vect_num 18 +#define ADC0_WCOMP_vect _VECTOR(18) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 19 +#define TWI0_TWIS_vect _VECTOR(19) /* */ +#define TWI0_TWIM_vect_num 20 +#define TWI0_TWIM_vect _VECTOR(20) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 21 +#define SPI0_INT_vect _VECTOR(21) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 22 +#define USART0_RXC_vect _VECTOR(22) /* */ +#define USART0_DRE_vect_num 23 +#define USART0_DRE_vect _VECTOR(23) /* */ +#define USART0_TXC_vect_num 24 +#define USART0_TXC_vect _VECTOR(24) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 25 +#define NVMCTRL_EE_vect _VECTOR(25) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (26 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (36864) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (36864U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (128) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (128U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3F00) +# define INTERNAL_SRAM_SIZE (256) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3F00U) +# define INTERNAL_SRAM_SIZE (256U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (4096) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (4096U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (4096) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (4096U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x92 +#define SIGNATURE_2 0x22 + + +#endif /* #ifdef _AVR_ATTINY414_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn416.h b/hardware/tools/avr/avr/include/avr/iotn416.h new file mode 100644 index 0000000000000000000000000000000000000000..d30f572806b15685ac22d0f14476f42a872dcd2f --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn416.h @@ -0,0 +1,5293 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn416.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY416_H_INCLUDED +#define _AVR_ATTINY416_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ + AC_MUXNEG_DAC_gc = (0x03<<0), /* DAC output */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wakeup halt */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling */ + BOD_SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[3]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1K cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16K cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32K cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64K cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t DATA; /* DATA Register */ + register8_t reserved_1[2]; +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t ASYNCCH2; /* Asynchronous Channel 2 Generator Selection */ + register8_t ASYNCCH3; /* Asynchronous Channel 3 Generator Selection */ + register8_t reserved_1[4]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t reserved_3[5]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 Input Selection - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 Input Selection - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous Channel 2 Generator Selection select */ +typedef enum EVSYS_ASYNCCH2_enum +{ + EVSYS_ASYNCCH2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH2_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH2_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH2_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH2_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH2_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH2_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH2_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH2_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH2_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH2_PORTC_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PC0 */ + EVSYS_ASYNCCH2_PORTC_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PC1 */ + EVSYS_ASYNCCH2_PORTC_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PC2 */ + EVSYS_ASYNCCH2_PORTC_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PC3 */ + EVSYS_ASYNCCH2_PORTC_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PC4 */ + EVSYS_ASYNCCH2_PORTC_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PC5 */ +} EVSYS_ASYNCCH2_t; + +/* Asynchronous Channel 3 Generator Selection select */ +typedef enum EVSYS_ASYNCCH3_enum +{ + EVSYS_ASYNCCH3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH3_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH3_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH3_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH3_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter type D compare B clear */ + EVSYS_ASYNCCH3_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter type D compare A set */ + EVSYS_ASYNCCH3_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter type D compare B set */ + EVSYS_ASYNCCH3_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter type D program event */ + EVSYS_ASYNCCH3_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH3_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH3_PIT_DIV8192_gc = (0x0A<<0), /* Periodic Interrupt CLK_RTC div 8192 */ + EVSYS_ASYNCCH3_PIT_DIV4096_gc = (0x0B<<0), /* Periodic Interrupt CLK_RTC div 4096 */ + EVSYS_ASYNCCH3_PIT_DIV2048_gc = (0x0C<<0), /* Periodic Interrupt CLK_RTC div 2048 */ + EVSYS_ASYNCCH3_PIT_DIV1024_gc = (0x0D<<0), /* Periodic Interrupt CLK_RTC div 1024 */ + EVSYS_ASYNCCH3_PIT_DIV512_gc = (0x0E<<0), /* Periodic Interrupt CLK_RTC div 512 */ + EVSYS_ASYNCCH3_PIT_DIV256_gc = (0x0F<<0), /* Periodic Interrupt CLK_RTC div 256 */ + EVSYS_ASYNCCH3_PIT_DIV128_gc = (0x10<<0), /* Periodic Interrupt CLK_RTC div 128 */ + EVSYS_ASYNCCH3_PIT_DIV64_gc = (0x11<<0), /* Periodic Interrupt CLK_RTC div 64 */ +} EVSYS_ASYNCCH3_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 Input Selection - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 Input Selection - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHz_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_20MHZ_gc = (0x00<<5), /* 20 MHz oscillator */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External clock */ + TCD_CLKSEL_SYSCLK_gc = (0x03<<5), /* System clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Syncronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selevted clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selevted clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selevted clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selevted clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0670) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x0680) /* Digital to Analog Converter */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0A80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_ASYNCCH2 _SFR_MEM8(0x0184) +#define EVSYS_ASYNCCH3 _SFR_MEM8(0x0185) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0670) +#define AC0_MUXCTRLA _SFR_MEM8(0x0672) +#define AC0_INTCTRL _SFR_MEM8(0x0676) +#define AC0_STATUS _SFR_MEM8(0x0677) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x0680) +#define DAC0_DATA _SFR_MEM8(0x0681) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0A80) +#define TCD0_CTRLB _SFR_MEM8(0x0A81) +#define TCD0_CTRLC _SFR_MEM8(0x0A82) +#define TCD0_CTRLD _SFR_MEM8(0x0A83) +#define TCD0_CTRLE _SFR_MEM8(0x0A84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0A88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0A89) +#define TCD0_INTCTRL _SFR_MEM8(0x0A8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0A8D) +#define TCD0_STATUS _SFR_MEM8(0x0A8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0A90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0A91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0A92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0A94) +#define TCD0_DLYVAL _SFR_MEM8(0x0A95) +#define TCD0_DITCTRL _SFR_MEM8(0x0A98) +#define TCD0_DITVAL _SFR_MEM8(0x0A99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0A9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0AA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0AA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0AA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0AA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0AA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0AA5) +#define TCD0_CMPASET _SFR_MEM16(0x0AA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0AA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0AA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0AAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0AAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0AAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0AAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0AAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0AAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0AAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0AAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0AAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH2 bit masks and bit positions */ +#define EVSYS_ASYNCCH2_gm 0xFF /* Asynchronous Channel 2 Generator Selection group mask. */ +#define EVSYS_ASYNCCH2_gp 0 /* Asynchronous Channel 2 Generator Selection group position. */ +#define EVSYS_ASYNCCH20_bm (1<<0) /* Asynchronous Channel 2 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH20_bp 0 /* Asynchronous Channel 2 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH21_bm (1<<1) /* Asynchronous Channel 2 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH21_bp 1 /* Asynchronous Channel 2 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH22_bm (1<<2) /* Asynchronous Channel 2 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH22_bp 2 /* Asynchronous Channel 2 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH23_bm (1<<3) /* Asynchronous Channel 2 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH23_bp 3 /* Asynchronous Channel 2 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH24_bm (1<<4) /* Asynchronous Channel 2 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH24_bp 4 /* Asynchronous Channel 2 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH25_bm (1<<5) /* Asynchronous Channel 2 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH25_bp 5 /* Asynchronous Channel 2 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH26_bm (1<<6) /* Asynchronous Channel 2 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH26_bp 6 /* Asynchronous Channel 2 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH27_bm (1<<7) /* Asynchronous Channel 2 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH27_bp 7 /* Asynchronous Channel 2 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH3 bit masks and bit positions */ +#define EVSYS_ASYNCCH3_gm 0xFF /* Asynchronous Channel 3 Generator Selection group mask. */ +#define EVSYS_ASYNCCH3_gp 0 /* Asynchronous Channel 3 Generator Selection group position. */ +#define EVSYS_ASYNCCH30_bm (1<<0) /* Asynchronous Channel 3 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH30_bp 0 /* Asynchronous Channel 3 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH31_bm (1<<1) /* Asynchronous Channel 3 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH31_bp 1 /* Asynchronous Channel 3 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH32_bm (1<<2) /* Asynchronous Channel 3 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH32_bp 2 /* Asynchronous Channel 3 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH33_bm (1<<3) /* Asynchronous Channel 3 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH33_bp 3 /* Asynchronous Channel 3 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH34_bm (1<<4) /* Asynchronous Channel 3 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH34_bp 4 /* Asynchronous Channel 3 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH35_bm (1<<5) /* Asynchronous Channel 3 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH35_bp 5 /* Asynchronous Channel 3 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH36_bm (1<<6) /* Asynchronous Channel 3 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH36_bp 6 /* Asynchronous Channel 3 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH37_bm (1<<7) /* Asynchronous Channel 3 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH37_bp 7 /* Asynchronous Channel 3 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 Input Selection - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 Input Selection - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 Input Selection - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 Input Selection - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 Input Selection - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 Input Selection - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 Input Selection - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 Input Selection - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 Input Selection - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 Input Selection - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 Input Selection - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 Input Selection - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 Input Selection - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 Input Selection - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 Input Selection - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 Input Selection - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 Input Selection - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 Input Selection - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 Input Selection - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 Input Selection - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Syncronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Syncronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Syncronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Syncronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Syncronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Syncronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 5 +#define PORTC_PORT_vect _VECTOR(5) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 14 +#define TCD0_OVF_vect _VECTOR(14) /* */ +#define TCD0_TRIG_vect_num 15 +#define TCD0_TRIG_vect _VECTOR(15) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 16 +#define AC0_AC_vect _VECTOR(16) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 17 +#define ADC0_RESRDY_vect _VECTOR(17) /* */ +#define ADC0_WCOMP_vect_num 18 +#define ADC0_WCOMP_vect _VECTOR(18) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 19 +#define TWI0_TWIS_vect _VECTOR(19) /* */ +#define TWI0_TWIM_vect_num 20 +#define TWI0_TWIM_vect _VECTOR(20) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 21 +#define SPI0_INT_vect _VECTOR(21) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 22 +#define USART0_RXC_vect _VECTOR(22) /* */ +#define USART0_DRE_vect_num 23 +#define USART0_DRE_vect _VECTOR(23) /* */ +#define USART0_TXC_vect_num 24 +#define USART0_TXC_vect _VECTOR(24) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 25 +#define NVMCTRL_EE_vect _VECTOR(25) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (26 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (36864) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (36864U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (128) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (128U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3F00) +# define INTERNAL_SRAM_SIZE (256) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3F00U) +# define INTERNAL_SRAM_SIZE (256U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (4096) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (4096U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (4096) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (4096U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x92 +#define SIGNATURE_2 0x21 + + +#endif /* #ifdef _AVR_ATTINY416_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn417.h b/hardware/tools/avr/avr/include/avr/iotn417.h new file mode 100644 index 0000000000000000000000000000000000000000..55c29a17f8e2d6e7c73134cefdb0ee7d9ce4d700 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn417.h @@ -0,0 +1,5292 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn417.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY417_H_INCLUDED +#define _AVR_ATTINY417_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ + AC_MUXNEG_DAC_gc = (0x03<<0), /* DAC output */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wakeup halt */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL1_gc = (0x01<<0), /* 2.1 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL3_gc = (0x03<<0), /* 2.9 V */ + BOD_LVL_BODLEVEL4_gc = (0x04<<0), /* 3.3 V */ + BOD_LVL_BODLEVEL5_gc = (0x05<<0), /* 3.7 V */ + BOD_LVL_BODLEVEL6_gc = (0x06<<0), /* 4.0 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling */ + BOD_SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[3]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1K cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16K cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32K cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64K cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t DATA; /* DATA Register */ + register8_t reserved_1[2]; +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t ASYNCCH2; /* Asynchronous Channel 2 Generator Selection */ + register8_t ASYNCCH3; /* Asynchronous Channel 3 Generator Selection */ + register8_t reserved_1[4]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t reserved_3[5]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 Input Selection - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 Input Selection - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous Channel 2 Generator Selection select */ +typedef enum EVSYS_ASYNCCH2_enum +{ + EVSYS_ASYNCCH2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH2_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH2_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH2_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH2_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH2_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH2_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH2_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH2_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH2_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH2_PORTC_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PC0 */ + EVSYS_ASYNCCH2_PORTC_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PC1 */ + EVSYS_ASYNCCH2_PORTC_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PC2 */ + EVSYS_ASYNCCH2_PORTC_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PC3 */ + EVSYS_ASYNCCH2_PORTC_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PC4 */ + EVSYS_ASYNCCH2_PORTC_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PC5 */ +} EVSYS_ASYNCCH2_t; + +/* Asynchronous Channel 3 Generator Selection select */ +typedef enum EVSYS_ASYNCCH3_enum +{ + EVSYS_ASYNCCH3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH3_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH3_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH3_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH3_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter type D compare B clear */ + EVSYS_ASYNCCH3_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter type D compare A set */ + EVSYS_ASYNCCH3_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter type D compare B set */ + EVSYS_ASYNCCH3_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter type D program event */ + EVSYS_ASYNCCH3_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH3_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH3_PIT_DIV8192_gc = (0x0A<<0), /* Periodic Interrupt CLK_RTC div 8192 */ + EVSYS_ASYNCCH3_PIT_DIV4096_gc = (0x0B<<0), /* Periodic Interrupt CLK_RTC div 4096 */ + EVSYS_ASYNCCH3_PIT_DIV2048_gc = (0x0C<<0), /* Periodic Interrupt CLK_RTC div 2048 */ + EVSYS_ASYNCCH3_PIT_DIV1024_gc = (0x0D<<0), /* Periodic Interrupt CLK_RTC div 1024 */ + EVSYS_ASYNCCH3_PIT_DIV512_gc = (0x0E<<0), /* Periodic Interrupt CLK_RTC div 512 */ + EVSYS_ASYNCCH3_PIT_DIV256_gc = (0x0F<<0), /* Periodic Interrupt CLK_RTC div 256 */ + EVSYS_ASYNCCH3_PIT_DIV128_gc = (0x10<<0), /* Periodic Interrupt CLK_RTC div 128 */ + EVSYS_ASYNCCH3_PIT_DIV64_gc = (0x11<<0), /* Periodic Interrupt CLK_RTC div 64 */ +} EVSYS_ASYNCCH3_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 Input Selection - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 Input Selection - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHz_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_20MHZ_gc = (0x00<<5), /* 20 MHz oscillator */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External clock */ + TCD_CLKSEL_SYSCLK_gc = (0x03<<5), /* System clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Syncronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selevted clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selevted clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selevted clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selevted clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0670) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x0680) /* Digital to Analog Converter */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0A80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_ASYNCCH2 _SFR_MEM8(0x0184) +#define EVSYS_ASYNCCH3 _SFR_MEM8(0x0185) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0670) +#define AC0_MUXCTRLA _SFR_MEM8(0x0672) +#define AC0_INTCTRL _SFR_MEM8(0x0676) +#define AC0_STATUS _SFR_MEM8(0x0677) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x0680) +#define DAC0_DATA _SFR_MEM8(0x0681) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0A80) +#define TCD0_CTRLB _SFR_MEM8(0x0A81) +#define TCD0_CTRLC _SFR_MEM8(0x0A82) +#define TCD0_CTRLD _SFR_MEM8(0x0A83) +#define TCD0_CTRLE _SFR_MEM8(0x0A84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0A88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0A89) +#define TCD0_INTCTRL _SFR_MEM8(0x0A8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0A8D) +#define TCD0_STATUS _SFR_MEM8(0x0A8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0A90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0A91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0A92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0A94) +#define TCD0_DLYVAL _SFR_MEM8(0x0A95) +#define TCD0_DITCTRL _SFR_MEM8(0x0A98) +#define TCD0_DITVAL _SFR_MEM8(0x0A99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0A9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0AA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0AA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0AA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0AA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0AA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0AA5) +#define TCD0_CMPASET _SFR_MEM16(0x0AA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0AA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0AA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0AAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0AAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0AAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0AAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0AAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0AAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0AAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0AAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0AAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_bm 0x08 /* Positive Input MUX Selection bit mask. */ +#define AC_MUXPOS_bp 3 /* Positive Input MUX Selection bit position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH2 bit masks and bit positions */ +#define EVSYS_ASYNCCH2_gm 0xFF /* Asynchronous Channel 2 Generator Selection group mask. */ +#define EVSYS_ASYNCCH2_gp 0 /* Asynchronous Channel 2 Generator Selection group position. */ +#define EVSYS_ASYNCCH20_bm (1<<0) /* Asynchronous Channel 2 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH20_bp 0 /* Asynchronous Channel 2 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH21_bm (1<<1) /* Asynchronous Channel 2 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH21_bp 1 /* Asynchronous Channel 2 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH22_bm (1<<2) /* Asynchronous Channel 2 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH22_bp 2 /* Asynchronous Channel 2 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH23_bm (1<<3) /* Asynchronous Channel 2 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH23_bp 3 /* Asynchronous Channel 2 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH24_bm (1<<4) /* Asynchronous Channel 2 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH24_bp 4 /* Asynchronous Channel 2 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH25_bm (1<<5) /* Asynchronous Channel 2 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH25_bp 5 /* Asynchronous Channel 2 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH26_bm (1<<6) /* Asynchronous Channel 2 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH26_bp 6 /* Asynchronous Channel 2 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH27_bm (1<<7) /* Asynchronous Channel 2 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH27_bp 7 /* Asynchronous Channel 2 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH3 bit masks and bit positions */ +#define EVSYS_ASYNCCH3_gm 0xFF /* Asynchronous Channel 3 Generator Selection group mask. */ +#define EVSYS_ASYNCCH3_gp 0 /* Asynchronous Channel 3 Generator Selection group position. */ +#define EVSYS_ASYNCCH30_bm (1<<0) /* Asynchronous Channel 3 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH30_bp 0 /* Asynchronous Channel 3 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH31_bm (1<<1) /* Asynchronous Channel 3 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH31_bp 1 /* Asynchronous Channel 3 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH32_bm (1<<2) /* Asynchronous Channel 3 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH32_bp 2 /* Asynchronous Channel 3 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH33_bm (1<<3) /* Asynchronous Channel 3 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH33_bp 3 /* Asynchronous Channel 3 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH34_bm (1<<4) /* Asynchronous Channel 3 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH34_bp 4 /* Asynchronous Channel 3 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH35_bm (1<<5) /* Asynchronous Channel 3 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH35_bp 5 /* Asynchronous Channel 3 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH36_bm (1<<6) /* Asynchronous Channel 3 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH36_bp 6 /* Asynchronous Channel 3 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH37_bm (1<<7) /* Asynchronous Channel 3 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH37_bp 7 /* Asynchronous Channel 3 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 Input Selection - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 Input Selection - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 Input Selection - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 Input Selection - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 Input Selection - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 Input Selection - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 Input Selection - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 Input Selection - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 Input Selection - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 Input Selection - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 Input Selection - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 Input Selection - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 Input Selection - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 Input Selection - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 Input Selection - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 Input Selection - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 Input Selection - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 Input Selection - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 Input Selection - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 Input Selection - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Syncronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Syncronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Syncronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Syncronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Syncronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Syncronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 5 +#define PORTC_PORT_vect _VECTOR(5) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 14 +#define TCD0_OVF_vect _VECTOR(14) /* */ +#define TCD0_TRIG_vect_num 15 +#define TCD0_TRIG_vect _VECTOR(15) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 16 +#define AC0_AC_vect _VECTOR(16) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 17 +#define ADC0_RESRDY_vect _VECTOR(17) /* */ +#define ADC0_WCOMP_vect_num 18 +#define ADC0_WCOMP_vect _VECTOR(18) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 19 +#define TWI0_TWIS_vect _VECTOR(19) /* */ +#define TWI0_TWIM_vect_num 20 +#define TWI0_TWIM_vect _VECTOR(20) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 21 +#define SPI0_INT_vect _VECTOR(21) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 22 +#define USART0_RXC_vect _VECTOR(22) /* */ +#define USART0_DRE_vect_num 23 +#define USART0_DRE_vect _VECTOR(23) /* */ +#define USART0_TXC_vect_num 24 +#define USART0_TXC_vect _VECTOR(24) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 25 +#define NVMCTRL_EE_vect _VECTOR(25) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (26 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (36864) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (36864U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (128) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (128U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3F00) +# define INTERNAL_SRAM_SIZE (256) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3F00U) +# define INTERNAL_SRAM_SIZE (256U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (4096) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (4096U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (4096) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (4096U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x92 +#define SIGNATURE_2 0x20 + + +#endif /* #ifdef _AVR_ATTINY417_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn4313.h b/hardware/tools/avr/avr/include/avr/iotn4313.h new file mode 100644 index 0000000000000000000000000000000000000000..2568ddaded10eef972037850de8f4d3e7523bfdc --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn4313.h @@ -0,0 +1,813 @@ +/* Copyright (c) 2009 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iotn4313.h 2412 2014-03-20 11:21:20Z pitchumani $ */ + +/* avr/iotn4313.h - definitions for ATtiny4313 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn4313.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATtiny4313_H_ +#define _AVR_ATtiny4313_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define USIBR _SFR_IO8(0x000) +#define USIBR0 0 +#define USIBR1 1 +#define USIBR2 2 +#define USIBR3 3 +#define USIBR4 4 +#define USIBR5 5 +#define USIBR6 6 +#define USIBR7 7 + +#define DIDR _SFR_IO8(0x001) +#define AIN0D 0 +#define AIN1D 1 + +#define UBRRH _SFR_IO8(0x002) +#define UBRR8 0 +#define UBRR9 1 +#define UBRR10 2 +#define UBRR11 3 + +#define UCSRC _SFR_IO8(0x003) +#define UCPOL 0 +#define UCSZ0 1 +#define UCSZ1 2 +#define USBS 3 +#define UPM0 4 +#define UPM1 5 +#define UMSEL0 6 +#define UMSEL1 7 + +/* When in MSPIM mode */ +#define UCPHA 1 +#define UDORD 2 + +#define PCMSK1 _SFR_IO8(0x004) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 + +#define PCMSK2 _SFR_IO8(0x005) +#define PCINT11 0 +#define PCINT12 1 +#define PCINT13 2 +#define PCINT14 3 +#define PCINT15 4 +#define PCINT16 5 +#define PCINT17 6 + +#define PRR _SFR_IO8(0x006) +#define PRUSART 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn43u.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_IOTN43U_H_ +#define _AVR_IOTN43U_H_ 1 + +/* Registers and associated bit numbers */ + +#define PRR _SFR_IO8(0x00) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 + +#define __AVR_HAVE_PRR ((1< + +/* Constants */ +#define SPM_PAGESIZE 64 +#define RAMSTART (0x60) +#define RAMEND 0x15F +#define XRAMEND RAMEND +#define E2END 0xFF +#define E2PAGESIZE 4 +#define FLASHEND 0xFFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_DWEN (unsigned char)~_BV(6) +#define FUSE_RSTDISBL (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_SPIEN) + +/* Extended Fuse Byte */ +#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x92 +#define SIGNATURE_2 0x07 + +#define SLEEP_MODE_IDLE (0x00<<3) +#define SLEEP_MODE_ADC (0x01<<3) +#define SLEEP_MODE_PWR_DOWN (0x02<<3) +#define SLEEP_MODE_STANDBY (0x03<<3) + +#endif /* _AVR_IOTN44_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iotn441.h b/hardware/tools/avr/avr/include/avr/iotn441.h new file mode 100644 index 0000000000000000000000000000000000000000..b1471ca58657f8463a69d4a2c3a9cffa010ee7e3 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn441.h @@ -0,0 +1,903 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_ATTINY441_H_INCLUDED +#define _AVR_ATTINY441_H_INCLUDED + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn441.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define ADCSRB _SFR_IO8(0x04) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 +#define ADLAR 3 + +#define ADCSRA _SFR_IO8(0x05) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +/* Combine ADCL and ADCH */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x06) +#endif +#define ADCW _SFR_IO16(0x06) + +#define ADCL _SFR_IO8(0x06) +#define ADCH _SFR_IO8(0x07) + +#define ADMUXB _SFR_IO8(0x08) +#define GSEL0 0 +#define GSEL1 1 +#define REFS0 5 +#define REFS1 6 +#define REFS2 7 + +#define ADMUXA _SFR_IO8(0x09) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define MUX4 4 +#define MUX5 5 + +#define ACSR0A _SFR_IO8(0x0A) +#define ACIS00 0 +#define ACIS01 1 +#define ACIC0 2 +#define ACIE0 3 +#define ACI0 4 +#define ACO0 5 +#define ACPMUX2 6 +#define ACD0 7 + +#define ACSR0B _SFR_IO8(0x0B) +#define ACPMUX0 0 +#define ACPMUX1 1 +#define ACNMUX0 2 +#define ACNMUX1 3 +#define ACOE0 4 +#define HLEV0 6 +#define HSEL0 7 + +#define ACSR1A _SFR_IO8(0x0C) +#define ACIS10 0 +#define ACIS11 1 +#define ACIC1 2 +#define ACIE1 3 +#define ACI1 4 +#define ACO1 5 +#define ACBG1 6 +#define ACD1 7 + +#define ACSR1B _SFR_IO8(0x0D) +#define ACME1 2 +#define ACOE1 4 +#define HLEV1 6 +#define HSEL1 7 + +#define TIFR1 _SFR_IO8(0x0E) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIMSK1 _SFR_IO8(0x0F) +#define TOIE1 0 +#define OCIE1A 1 +#define OCIE1B 2 +#define ICIE1 5 + +#define TIFR2 _SFR_IO8(0x10) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 +#define ICF2 5 + +#define TIMSK2 _SFR_IO8(0x11) +#define TOIE2 0 +#define OCIE2A 1 +#define OCIE2B 2 +#define ICIE2 5 + +#define PCMSK0 _SFR_IO8(0x12) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 +#define PCINT4 4 +#define PCINT5 5 +#define PCINT6 6 +#define PCINT7 7 + +#define GPIOR0 _SFR_IO8(0x13) + +#define GPIOR1 _SFR_IO8(0x14) + +#define GPIOR2 _SFR_IO8(0x15) + +#define PINB _SFR_IO8(0x16) +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x17) +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x18) +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINA _SFR_IO8(0x19) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x1A) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x1B) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x1D) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x1E) + +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +#define PCMSK1 _SFR_IO8(0x20) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 +#define PCINT11 3 + +#define WDTCSR _SFR_IO8(0x21) +#define WDE 3 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define TCCR1C _SFR_IO8(0x22) +#define FOC1B 6 +#define FOC1A 7 + +#define GTCCR _SFR_IO8(0x23) +#define PSR 0 +#define TSM 7 + +/* Combine ICR1L and ICR1H */ +#define ICR1 _SFR_IO16(0x24) + +#define ICR1L _SFR_IO8(0x24) +#define ICR1H _SFR_IO8(0x25) + +/* Reserved [0x26..0x27] */ + +/* Combine OCR1BL and OCR1BH */ +#define OCR1B _SFR_IO16(0x28) + +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Combine OCR1AL and OCR1AH */ +#define OCR1A _SFR_IO16(0x2A) + +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Combine TCNT1L and TCNT1H */ +#define TCNT1 _SFR_IO16(0x2C) + +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +#define TCCR1B _SFR_IO8(0x2E) +#define CS10 0 +#define CS11 1 +#define CS12 2 +#define WGM12 3 +#define WGM13 4 +#define ICES1 6 +#define ICNC1 7 + +#define TCCR1A _SFR_IO8(0x2F) +#define WGM10 0 +#define WGM11 1 +#define COM1B0 4 +#define COM1B1 5 +#define COM1A0 6 +#define COM1A1 7 + +#define TCCR0A _SFR_IO8(0x30) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +/* Reserved [0x31] */ + +#define TCNT0 _SFR_IO8(0x32) + +#define TCCR0B _SFR_IO8(0x33) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define ISC00 0 +#define ISC01 1 +#define SM0 3 +#define SM1 4 +#define SE 5 + +#define OCR0A _SFR_IO8(0x36) + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define RSIG 5 + +#define TIFR0 _SFR_IO8(0x38) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIMSK0 _SFR_IO8(0x39) +#define TOIE0 0 +#define OCIE0A 1 +#define OCIE0B 2 + +#define GIFR _SFR_IO8(0x3A) +#define PCIF0 4 +#define PCIF1 5 +#define INTF0 6 + +#define GIMSK _SFR_IO8(0x3B) +#define PCIE0 4 +#define PCIE1 5 +#define INT0 6 + +#define OCR0B _SFR_IO8(0x3C) + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define DIDR0 _SFR_MEM8(0x60) +#define ADC0D 0 +#define ADC1D 1 +#define ADC2D 2 +#define ADC3D 3 +#define ADC4D 4 +#define ADC5D 5 +#define ADC6D 6 +#define ADC7D 7 + +#define DIDR1 _SFR_MEM8(0x61) +#define ADC11D 0 +#define ADC10D 1 +#define ADC8D 2 +#define ADC9D 3 + +#define PUEB _SFR_MEM8(0x62) + +#define PUEA _SFR_MEM8(0x63) + +#define PORTCR _SFR_MEM8(0x64) +#define BBMB 1 +#define BBMA 0 + +#define REMAP _SFR_MEM8(0x65) +#define U0MAP 0 +#define SPIMAP 1 + +#define TOCPMCOE _SFR_MEM8(0x66) +#define TOCC0OE 0 +#define TOCC1OE 1 +#define TOCC2OE 2 +#define TOCC3OE 3 +#define TOCC4OE 4 +#define TOCC5OE 5 +#define TOCC6OE 6 +#define TOCC7OE 7 + +#define TOCPMSA0 _SFR_MEM8(0x67) +#define TOCC0S0 0 +#define TOCC0S1 1 +#define TOCC1S0 2 +#define TOCC1S1 3 +#define TOCC2S0 4 +#define TOCC2S1 5 +#define TOCC3S0 6 +#define TOCC3S1 7 + +#define TOCPMSA1 _SFR_MEM8(0x68) +#define TOCC4S0 0 +#define TOCC4S1 1 +#define TOCC5S0 2 +#define TOCC5S1 3 +#define TOCC6S0 4 +#define TOCC6S1 5 +#define TOCC7S0 6 +#define TOCC7S1 7 + +/* Reserved [0x69] */ + +#define PHDE _SFR_MEM8(0x6A) +#define PHDEA0 0 +#define PHDEA1 1 + +/* Reserved [0x6B..0x6F] */ + +#define PRR _SFR_MEM8(0x70) +#define PRADC 0 +#define PRTIM0 1 +#define PRTIM1 2 +#define PRTIM2 3 +#define PRSPI 4 +#define PRUSART0 5 +#define PRUSART1 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn44a.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATtiny44A_H_ +#define _AVR_ATtiny44A_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PRR _SFR_IO8(0x00) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 + +#define __AVR_HAVE_PRR ((1< + +/* Constants */ +#define SPM_PAGESIZE 64 +#define RAMSTART (0x60) +#define RAMEND 0x15F +#define XRAMEND RAMEND +#define E2END 0xFF +#define E2PAGESIZE 4 +#define FLASHEND 0xFFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_DWEN (unsigned char)~_BV(6) +#define FUSE_RSTDISBL (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_SPIEN) + +/* Extended Fuse Byte */ +#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x92 +#define SIGNATURE_2 0x06 + +#define SLEEP_MODE_IDLE (0x00<<3) +#define SLEEP_MODE_ADC (0x01<<3) +#define SLEEP_MODE_PWR_DOWN (0x02<<3) + +#endif /* _AVR_IOTN45_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iotn461.h b/hardware/tools/avr/avr/include/avr/iotn461.h new file mode 100644 index 0000000000000000000000000000000000000000..eef716f88f888ef0129d4ecf33c08164ac403de7 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn461.h @@ -0,0 +1,94 @@ +/* Copyright (c) 2006, Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iotn461.h 2115 2010-04-05 23:19:53Z arcanum $ */ + +/* avr/iotn461.h - definitions for ATtiny461 */ + +#ifndef _AVR_IOTN461_H_ +#define _AVR_IOTN461_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 64 +#define RAMSTART (0x60) +#define RAMEND 0x15F +#define XRAMEND RAMEND +#define E2END 0xFF +#define E2PAGESIZE 4 +#define FLASHEND 0xFFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_DWEN (unsigned char)~_BV(6) +#define FUSE_RSTDISBL (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_SPIEN) + +/* Extended Fuse Byte */ +#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x92 +#define SIGNATURE_2 0x08 + +#define SLEEP_MODE_IDLE (0x00<<3) +#define SLEEP_MODE_ADC (0x01<<3) +#define SLEEP_MODE_PWR_DOWN (0x02<<3) +#define SLEEP_MODE_STANDBY (0x03<<3) + +#endif /* _AVR_IOTN461_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iotn461a.h b/hardware/tools/avr/avr/include/avr/iotn461a.h new file mode 100644 index 0000000000000000000000000000000000000000..809e23b8b32d00638434c5f938437bb0ae1aafa8 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn461a.h @@ -0,0 +1,987 @@ +/* Copyright (c) 2009 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iotn461a.h 2063 2009-11-18 22:06:28Z arcanum $ */ + +/* avr/iotn461a.h - definitions for ATtiny461A */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn461a.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATtiny461A_H_ +#define _AVR_ATtiny461A_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define TCCR1E _SFR_IO8(0x00) +#define OC1OE0 0 +#define OC1OE1 1 +#define OC1OE2 2 +#define OC1OE3 3 +#define OC1OE4 4 +#define OC1OE5 5 + +#define DIDR0 _SFR_IO8(0x01) +#define ADC0D 0 +#define ADC1D 1 +#define ADC2D 2 +#define AREFD 3 +#define ADC3D 4 +#define ADC4D 5 +#define ADC5D 6 +#define ADC6D 7 + +#define DIDR1 _SFR_IO8(0x02) +#define ADC7D 4 +#define ADC8D 5 +#define ADC9D 6 +#define ADC10D 7 + +#define ADCSRB _SFR_IO8(0x03) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 +#define MUX5 3 +#define REFS2 4 +#define IPR 5 +#define GSEL 6 +#define BIN 7 + +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) + +#define ADCL _SFR_IO8(0x04) +#define ADCL0 0 +#define ADCL1 1 +#define ADCL2 2 +#define ADCL3 3 +#define ADCL4 4 +#define ADCL5 5 +#define ADCL6 6 +#define ADCL7 7 + +#define ADCH _SFR_IO8(0x05) +#define ADCH0 0 +#define ADCH1 1 +#define ADCH2 2 +#define ADCH3 3 +#define ADCH4 4 +#define ADCH5 5 +#define ADCH6 6 +#define ADCH7 7 + +#define ADCSRA _SFR_IO8(0x06) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +#define ADMUX _SFR_IO8(0x07) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define MUX4 4 +#define ADLAR 5 +#define REFS0 6 +#define REFS1 7 + +#define ACSRA _SFR_IO8(0x08) +#define ACIS0 0 +#define ACIS1 1 +#define ACME 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define ACSRB _SFR_IO8(0x09) +#define ACM0 0 +#define ACM1 1 +#define ACM2 2 +#define HLEV 6 +#define HSEL 7 + +#define GPIOR0 _SFR_IO8(0x0A) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define GPIOR1 _SFR_IO8(0x0B) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x0C) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define USICR _SFR_IO8(0x0D) +#define USITC 0 +#define USICLK 1 +#define USICS0 2 +#define USICS1 3 +#define USIWM0 4 +#define USIWM1 5 +#define USIOIE 6 +#define USISIE 7 + +#define USISR _SFR_IO8(0x0E) +#define USICNT0 0 +#define USICNT1 1 +#define USICNT2 2 +#define USICNT3 3 +#define USIDC 4 +#define USIPF 5 +#define USIOIF 6 +#define USISIF 7 + +#define USIDR _SFR_IO8(0x0F) +#define USIDR0 0 +#define USIDR1 1 +#define USIDR2 2 +#define USIDR3 3 +#define USIDR4 4 +#define USIDR5 5 +#define USIDR6 6 +#define USIDR7 7 + +#define USIBR _SFR_IO8(0x10) +#define USIBR0 0 +#define USIBR1 1 +#define USIBR2 2 +#define USIBR3 3 +#define USIBR4 4 +#define USIBR5 5 +#define USIBR6 6 +#define USIBR7 7 + +#define USIPP _SFR_IO8(0x11) +#define USIPOS 0 + +#define OCR0B _SFR_IO8(0x12) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define OCR0A _SFR_IO8(0x13) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define TCNT0H _SFR_IO8(0x14) +#define TCNT0H_0 0 +#define TCNT0H_1 1 +#define TCNT0H_2 2 +#define TCNT0H_3 3 +#define TCNT0H_4 4 +#define TCNT0H_5 5 +#define TCNT0H_6 6 +#define TCNT0H_7 7 + +#define TCCR0A _SFR_IO8(0x15) +#define WGM00 0 +#define ACIC0 3 +#define ICES0 4 +#define ICNC0 5 +#define ICEN0 6 +#define TCW0 7 + +#define PINB _SFR_IO8(0x16) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x17) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x18) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINA _SFR_IO8(0x19) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 +#define PINA4 4 +#define PINA5 5 +#define PINA6 6 +#define PINA7 7 + +#define DDRA _SFR_IO8(0x1A) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x1B) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 +#define PORTA4 4 +#define PORTA5 5 +#define PORTA6 6 +#define PORTA7 7 + +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x1D) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x1E) + +#define EEARL _SFR_IO8(0x1E) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x1F) +#define EEAR8 0 + +#define DWDR _SFR_IO8(0x20) +#define DWDR0 0 +#define DWDR1 1 +#define DWDR2 2 +#define DWDR3 3 +#define DWDR4 4 +#define DWDR5 5 +#define DWDR6 6 +#define DWDR7 7 + +#define WDTCR _SFR_IO8(0x21) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define PCMSK1 _SFR_IO8(0x22) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 +#define PCINT11 3 +#define PCINT12 4 +#define PCINT13 5 +#define PCINT14 6 +#define PCINT15 7 + +#define PCMSK0 _SFR_IO8(0x23) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 +#define PCINT4 4 +#define PCINT5 5 +#define PCINT6 6 +#define PCINT7 7 + +#define DT1 _SFR_IO8(0x24) +#define DT1L0 0 +#define DT1L1 1 +#define DT1L2 2 +#define DT1L3 3 +#define DT1H0 4 +#define DT1H1 5 +#define DT1H2 6 +#define DT1H3 7 + +#define TC1H _SFR_IO8(0x25) +#define TC18 0 +#define TC19 1 + +#define TCCR1D _SFR_IO8(0x26) +#define WGM10 0 +#define WGM11 1 +#define FPF1 2 +#define FPAC1 3 +#define FPES1 4 +#define FPNC1 5 +#define FPEN1 6 +#define FPIE1 7 + +#define TCCR1C _SFR_IO8(0x27) +#define PWM1D 0 +#define FOC1D 1 +#define COM1D0 2 +#define COM1D1 3 +#define COM1B0S 4 +#define COM1B1S 5 +#define COM1A0S 6 +#define COM1A1S 7 + +#define CLKPR _SFR_IO8(0x28) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 +#define PLLE 1 +#define PCKE 2 +#define LSM 7 + +#define OCR1D _SFR_IO8(0x2A) +#define OCR1D0 0 +#define OCR1D1 1 +#define OCR1D2 2 +#define OCR1D3 3 +#define OCR1D4 4 +#define OCR1D5 5 +#define OCR1D6 6 +#define OCR1D7 7 + +#define OCR1C _SFR_IO8(0x2B) +#define OCR1C0 0 +#define OCR1C1 1 +#define OCR1C2 2 +#define OCR1C3 3 +#define OCR1C4 4 +#define OCR1C5 5 +#define OCR1C6 6 +#define OCR1C7 7 + +#define OCR1B _SFR_IO8(0x2C) +#define OCR1B0 0 +#define OCR1B1 1 +#define OCR1B2 2 +#define OCR1B3 3 +#define OCR1B4 4 +#define OCR1B5 5 +#define OCR1B6 6 +#define OCR1B7 7 + +#define OCR1A _SFR_IO8(0x2D) +#define OCR1A0 0 +#define OCR1A1 1 +#define OCR1A2 2 +#define OCR1A3 3 +#define OCR1A4 4 +#define OCR1A5 5 +#define OCR1A6 6 +#define OCR1A7 7 + +#define TCNT1 _SFR_IO8(0x2E) +#define TC1H_0 0 +#define TC1H_1 1 +#define TC1H_2 2 +#define TC1H_3 3 +#define TC1H_4 4 +#define TC1H_5 5 +#define TC1H_6 6 +#define TC1H_7 7 + +#define TCCR1B _SFR_IO8(0x2F) +#define CS10 0 +#define CS11 1 +#define CS12 2 +#define CS13 3 +#define DTPS10 4 +#define DTPS11 5 +#define PSR1 6 + +#define TCCR1A _SFR_IO8(0x30) +#define PWM1B 0 +#define PWM1A 1 +#define FOC1B 2 +#define FOC1A 3 +#define COM1B0 4 +#define COM1B1 5 +#define COM1A0 6 +#define COM1A1 7 + +#define OSCCAL _SFR_IO8(0x31) +#define CAL0 0 +#define CAL1 1 +#define CAL2 2 +#define CAL3 3 +#define CAL4 4 +#define CAL5 5 +#define CAL6 6 +#define CAL7 7 + +#define TCNT0L _SFR_IO8(0x32) +#define TCNT0L_0 0 +#define TCNT0L_1 1 +#define TCNT0L_2 2 +#define TCNT0L_3 3 +#define TCNT0L_4 4 +#define TCNT0L_5 5 +#define TCNT0L_6 6 +#define TCNT0L_7 7 + +#define TCCR0B _SFR_IO8(0x33) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define PSR0 3 +#define TSM 4 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define ISC00 0 +#define ISC01 1 +#define BODSE 2 +#define SM0 3 +#define SM1 4 +#define SE 5 +#define PUD 6 +#define BODS 7 + +#define PRR _SFR_IO8(0x36) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn48.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_IOTN48_H_ +#define _AVR_IOTN48_H_ 1 + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define PINA _SFR_IO8(0x0C) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 + +#define DDRA _SFR_IO8(0x0D) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 + +#define PORTA _SFR_IO8(0x0E) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 + +#define PORTCR _SFR_IO8(0x12) +#define PUDA 0 +#define PUDB 1 +#define PUDC 2 +#define PUDD 3 +#define BBMA 4 +#define BBMB 5 +#define BBMC 6 +#define BBMD 7 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define CTC0 3 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define RWWSB 6 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1<